arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  56 #define POWERNV_IOMMU_MAX_LEVELS        5
  57
  58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
  59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  60
  61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  62                             const char *fmt, ...)
  63 {
  64         struct va_format vaf;
  65         va_list args;
  66         char pfix[32];
  67
  68         va_start(args, fmt);
  69
  70         vaf.fmt = fmt;
  71         vaf.va = &args;
  72
  73         if (pe->flags & PNV_IODA_PE_DEV)
  74                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  75         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  76                 sprintf(pfix, "%04x:%02x     ",
  77                         pci_domain_nr(pe->pbus), pe->pbus->number);
  78 #ifdef CONFIG_PCI_IOV
  79         else if (pe->flags & PNV_IODA_PE_VF)
  80                 sprintf(pfix, "%04x:%02x:%2x.%d",
  81                         pci_domain_nr(pe->parent_dev->bus),
  82                         (pe->rid & 0xff00) >> 8,
  83                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  84 #endif /* CONFIG_PCI_IOV*/
  85
  86         printk("%spci %s: [PE# %.3d] %pV",
  87                level, pfix, pe->pe_number, &vaf);
  88
  89         va_end(args);
  90 }
  91
  92 static bool pnv_iommu_bypass_disabled __read_mostly;
  93
  94 static int __init iommu_setup(char *str)
  95 {
  96         if (!str)
  97                 return -EINVAL;
  98
  99         while (*str) {
 100                 if (!strncmp(str, "nobypass", 8)) {
 101                         pnv_iommu_bypass_disabled = true;
 102                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 103                         break;
 104                 }
 105                 str += strcspn(str, ",");
 106                 if (*str == ',')
 107                         str++;
 108         }
 109
 110         return 0;
 111 }
 112 early_param("iommu", iommu_setup);
 113
 114 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 115 {
 116         /*
 117          * WARNING: We cannot rely on the resource flags. The Linux PCI
 118          * allocation code sometimes decides to put a 64-bit prefetchable
 119          * BAR in the 32-bit window, so we have to compare the addresses.
 120          *
 121          * For simplicity we only test resource start.
 122          */
 123         return (r->start >= phb->ioda.m64_base &&
 124                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 125 }
 126
 127 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 128 {
 129         phb->ioda.pe_array[pe_no].phb = phb;
 130         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 131
 132         return &phb->ioda.pe_array[pe_no];
 133 }
 134
 135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 136 {
 137         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 138                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 139                         __func__, pe_no, phb->hose->global_number);
 140                 return;
 141         }
 142
 143         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 144                 pr_debug("%s: PE %d was reserved on PHB#%x\n",
 145                          __func__, pe_no, phb->hose->global_number);
 146
 147         pnv_ioda_init_pe(phb, pe_no);
 148 }
 149
 150 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 151 {
 152         unsigned long pe = phb->ioda.total_pe_num - 1;
 153
 154         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 155                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 156                         return pnv_ioda_init_pe(phb, pe);
 157         }
 158
 159         return NULL;
 160 }
 161
 162 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 163 {
 164         struct pnv_phb *phb = pe->phb;
 165
 166         WARN_ON(pe->pdev);
 167
 168         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 169         clear_bit(pe->pe_number, phb->ioda.pe_alloc);
 170 }
 171
 172 /* The default M64 BAR is shared by all PEs */
 173 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 174 {
 175         const char *desc;
 176         struct resource *r;
 177         s64 rc;
 178
 179         /* Configure the default M64 BAR */
 180         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 181                                          OPAL_M64_WINDOW_TYPE,
 182                                          phb->ioda.m64_bar_idx,
 183                                          phb->ioda.m64_base,
 184                                          0, /* unused */
 185                                          phb->ioda.m64_size);
 186         if (rc != OPAL_SUCCESS) {
 187                 desc = "configuring";
 188                 goto fail;
 189         }
 190
 191         /* Enable the default M64 BAR */
 192         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 193                                       OPAL_M64_WINDOW_TYPE,
 194                                       phb->ioda.m64_bar_idx,
 195                                       OPAL_ENABLE_M64_SPLIT);
 196         if (rc != OPAL_SUCCESS) {
 197                 desc = "enabling";
 198                 goto fail;
 199         }
 200
 201         /*
 202          * Exclude the segments for reserved and root bus PE, which
 203          * are first or last two PEs.
 204          */
 205         r = &phb->hose->mem_resources[1];
 206         if (phb->ioda.reserved_pe_idx == 0)
 207                 r->start += (2 * phb->ioda.m64_segsize);
 208         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 209                 r->end -= (2 * phb->ioda.m64_segsize);
 210         else
 211                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 212                         phb->ioda.reserved_pe_idx);
 213
 214         return 0;
 215
 216 fail:
 217         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 218                 rc, desc, phb->ioda.m64_bar_idx);
 219         opal_pci_phb_mmio_enable(phb->opal_id,
 220                                  OPAL_M64_WINDOW_TYPE,
 221                                  phb->ioda.m64_bar_idx,
 222                                  OPAL_DISABLE_M64);
 223         return -EIO;
 224 }
 225
 226 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 227                                          unsigned long *pe_bitmap)
 228 {
 229         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 230         struct pnv_phb *phb = hose->private_data;
 231         struct resource *r;
 232         resource_size_t base, sgsz, start, end;
 233         int segno, i;
 234
 235         base = phb->ioda.m64_base;
 236         sgsz = phb->ioda.m64_segsize;
 237         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 238                 r = &pdev->resource[i];
 239                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 240                         continue;
 241
 242                 start = _ALIGN_DOWN(r->start - base, sgsz);
 243                 end = _ALIGN_UP(r->end - base, sgsz);
 244                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 245                         if (pe_bitmap)
 246                                 set_bit(segno, pe_bitmap);
 247                         else
 248                                 pnv_ioda_reserve_pe(phb, segno);
 249                 }
 250         }
 251 }
 252
 253 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 254 {
 255         struct resource *r;
 256         int index;
 257
 258         /*
 259          * There are 16 M64 BARs, each of which has 8 segments. So
 260          * there are as many M64 segments as the maximum number of
 261          * PEs, which is 128.
 262          */
 263         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 264                 unsigned long base, segsz = phb->ioda.m64_segsize;
 265                 int64_t rc;
 266
 267                 base = phb->ioda.m64_base +
 268                        index * PNV_IODA1_M64_SEGS * segsz;
 269                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 270                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 271                                 PNV_IODA1_M64_SEGS * segsz);
 272                 if (rc != OPAL_SUCCESS) {
 273                         pr_warn("  Error %lld setting M64 PHB#%d-BAR#%d\n",
 274                                 rc, phb->hose->global_number, index);
 275                         goto fail;
 276                 }
 277
 278                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 279                                 OPAL_M64_WINDOW_TYPE, index,
 280                                 OPAL_ENABLE_M64_SPLIT);
 281                 if (rc != OPAL_SUCCESS) {
 282                         pr_warn("  Error %lld enabling M64 PHB#%d-BAR#%d\n",
 283                                 rc, phb->hose->global_number, index);
 284                         goto fail;
 285                 }
 286         }
 287
 288         /*
 289          * Exclude the segments for reserved and root bus PE, which
 290          * are first or last two PEs.
 291          */
 292         r = &phb->hose->mem_resources[1];
 293         if (phb->ioda.reserved_pe_idx == 0)
 294                 r->start += (2 * phb->ioda.m64_segsize);
 295         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 296                 r->end -= (2 * phb->ioda.m64_segsize);
 297         else
 298                 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
 299                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 300
 301         return 0;
 302
 303 fail:
 304         for ( ; index >= 0; index--)
 305                 opal_pci_phb_mmio_enable(phb->opal_id,
 306                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 307
 308         return -EIO;
 309 }
 310
 311 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 312                                     unsigned long *pe_bitmap,
 313                                     bool all)
 314 {
 315         struct pci_dev *pdev;
 316
 317         list_for_each_entry(pdev, &bus->devices, bus_list) {
 318                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 319
 320                 if (all && pdev->subordinate)
 321                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 322                                                 pe_bitmap, all);
 323         }
 324 }
 325
 326 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 327 {
 328         struct pci_controller *hose = pci_bus_to_host(bus);
 329         struct pnv_phb *phb = hose->private_data;
 330         struct pnv_ioda_pe *master_pe, *pe;
 331         unsigned long size, *pe_alloc;
 332         int i;
 333
 334         /* Root bus shouldn't use M64 */
 335         if (pci_is_root_bus(bus))
 336                 return NULL;
 337
 338         /* Allocate bitmap */
 339         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 340         pe_alloc = kzalloc(size, GFP_KERNEL);
 341         if (!pe_alloc) {
 342                 pr_warn("%s: Out of memory !\n",
 343                         __func__);
 344                 return NULL;
 345         }
 346
 347         /* Figure out reserved PE numbers by the PE */
 348         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 349
 350         /*
 351          * the current bus might not own M64 window and that's all
 352          * contributed by its child buses. For the case, we needn't
 353          * pick M64 dependent PE#.
 354          */
 355         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 356                 kfree(pe_alloc);
 357                 return NULL;
 358         }
 359
 360         /*
 361          * Figure out the master PE and put all slave PEs to master
 362          * PE's list to form compound PE.
 363          */
 364         master_pe = NULL;
 365         i = -1;
 366         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 367                 phb->ioda.total_pe_num) {
 368                 pe = &phb->ioda.pe_array[i];
 369
 370                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 371                 if (!master_pe) {
 372                         pe->flags |= PNV_IODA_PE_MASTER;
 373                         INIT_LIST_HEAD(&pe->slaves);
 374                         master_pe = pe;
 375                 } else {
 376                         pe->flags |= PNV_IODA_PE_SLAVE;
 377                         pe->master = master_pe;
 378                         list_add_tail(&pe->list, &master_pe->slaves);
 379                 }
 380
 381                 /*
 382                  * P7IOC supports M64DT, which helps mapping M64 segment
 383                  * to one particular PE#. However, PHB3 has fixed mapping
 384                  * between M64 segment and PE#. In order to have same logic
 385                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 386                  * segment and PE# on P7IOC.
 387                  */
 388                 if (phb->type == PNV_PHB_IODA1) {
 389                         int64_t rc;
 390
 391                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 392                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 393                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 394                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 395                         if (rc != OPAL_SUCCESS)
 396                                 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
 397                                         __func__, rc, phb->hose->global_number,
 398                                         pe->pe_number);
 399                 }
 400         }
 401
 402         kfree(pe_alloc);
 403         return master_pe;
 404 }
 405
 406 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 407 {
 408         struct pci_controller *hose = phb->hose;
 409         struct device_node *dn = hose->dn;
 410         struct resource *res;
 411         u32 m64_range[2], i;
 412         const u32 *r;
 413         u64 pci_addr;
 414
 415         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 416                 pr_info("  Not support M64 window\n");
 417                 return;
 418         }
 419
 420         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 421                 pr_info("  Firmware too old to support M64 window\n");
 422                 return;
 423         }
 424
 425         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 426         if (!r) {
 427                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 428                         dn->full_name);
 429                 return;
 430         }
 431
 432         /*
 433          * Find the available M64 BAR range and pickup the last one for
 434          * covering the whole 64-bits space. We support only one range.
 435          */
 436         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 437                                        m64_range, 2)) {
 438                 /* In absence of the property, assume 0..15 */
 439                 m64_range[0] = 0;
 440                 m64_range[1] = 16;
 441         }
 442         /* We only support 64 bits in our allocator */
 443         if (m64_range[1] > 63) {
 444                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 445                         __func__, m64_range[1], phb->hose->global_number);
 446                 m64_range[1] = 63;
 447         }
 448         /* Empty range, no m64 */
 449         if (m64_range[1] <= m64_range[0]) {
 450                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 451                         __func__, phb->hose->global_number);
 452                 return;
 453         }
 454
 455         /* Configure M64 informations */
 456         res = &hose->mem_resources[1];
 457         res->name = dn->full_name;
 458         res->start = of_translate_address(dn, r + 2);
 459         res->end = res->start + of_read_number(r + 4, 2) - 1;
 460         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 461         pci_addr = of_read_number(r, 2);
 462         hose->mem_offset[1] = res->start - pci_addr;
 463
 464         phb->ioda.m64_size = resource_size(res);
 465         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 466         phb->ioda.m64_base = pci_addr;
 467
 468         /* This lines up nicely with the display from processing OF ranges */
 469         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 470                 res->start, res->end, pci_addr, m64_range[0],
 471                 m64_range[0] + m64_range[1] - 1);
 472
 473         /* Mark all M64 used up by default */
 474         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 475
 476         /* Use last M64 BAR to cover M64 window */
 477         m64_range[1]--;
 478         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 479
 480         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 481
 482         /* Mark remaining ones free */
 483         for (i = m64_range[0]; i < m64_range[1]; i++)
 484                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 485
 486         /*
 487          * Setup init functions for M64 based on IODA version, IODA3 uses
 488          * the IODA2 code.
 489          */
 490         if (phb->type == PNV_PHB_IODA1)
 491                 phb->init_m64 = pnv_ioda1_init_m64;
 492         else
 493                 phb->init_m64 = pnv_ioda2_init_m64;
 494         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 495         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 496 }
 497
 498 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 499 {
 500         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 501         struct pnv_ioda_pe *slave;
 502         s64 rc;
 503
 504         /* Fetch master PE */
 505         if (pe->flags & PNV_IODA_PE_SLAVE) {
 506                 pe = pe->master;
 507                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 508                         return;
 509
 510                 pe_no = pe->pe_number;
 511         }
 512
 513         /* Freeze master PE */
 514         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 515                                      pe_no,
 516                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 517         if (rc != OPAL_SUCCESS) {
 518                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 519                         __func__, rc, phb->hose->global_number, pe_no);
 520                 return;
 521         }
 522
 523         /* Freeze slave PEs */
 524         if (!(pe->flags & PNV_IODA_PE_MASTER))
 525                 return;
 526
 527         list_for_each_entry(slave, &pe->slaves, list) {
 528                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 529                                              slave->pe_number,
 530                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 531                 if (rc != OPAL_SUCCESS)
 532                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 533                                 __func__, rc, phb->hose->global_number,
 534                                 slave->pe_number);
 535         }
 536 }
 537
 538 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 539 {
 540         struct pnv_ioda_pe *pe, *slave;
 541         s64 rc;
 542
 543         /* Find master PE */
 544         pe = &phb->ioda.pe_array[pe_no];
 545         if (pe->flags & PNV_IODA_PE_SLAVE) {
 546                 pe = pe->master;
 547                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 548                 pe_no = pe->pe_number;
 549         }
 550
 551         /* Clear frozen state for master PE */
 552         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 553         if (rc != OPAL_SUCCESS) {
 554                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 555                         __func__, rc, opt, phb->hose->global_number, pe_no);
 556                 return -EIO;
 557         }
 558
 559         if (!(pe->flags & PNV_IODA_PE_MASTER))
 560                 return 0;
 561
 562         /* Clear frozen state for slave PEs */
 563         list_for_each_entry(slave, &pe->slaves, list) {
 564                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 565                                              slave->pe_number,
 566                                              opt);
 567                 if (rc != OPAL_SUCCESS) {
 568                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 569                                 __func__, rc, opt, phb->hose->global_number,
 570                                 slave->pe_number);
 571                         return -EIO;
 572                 }
 573         }
 574
 575         return 0;
 576 }
 577
 578 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 579 {
 580         struct pnv_ioda_pe *slave, *pe;
 581         u8 fstate, state;
 582         __be16 pcierr;
 583         s64 rc;
 584
 585         /* Sanity check on PE number */
 586         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 587                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 588
 589         /*
 590          * Fetch the master PE and the PE instance might be
 591          * not initialized yet.
 592          */
 593         pe = &phb->ioda.pe_array[pe_no];
 594         if (pe->flags & PNV_IODA_PE_SLAVE) {
 595                 pe = pe->master;
 596                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 597                 pe_no = pe->pe_number;
 598         }
 599
 600         /* Check the master PE */
 601         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 602                                         &state, &pcierr, NULL);
 603         if (rc != OPAL_SUCCESS) {
 604                 pr_warn("%s: Failure %lld getting "
 605                         "PHB#%x-PE#%x state\n",
 606                         __func__, rc,
 607                         phb->hose->global_number, pe_no);
 608                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 609         }
 610
 611         /* Check the slave PE */
 612         if (!(pe->flags & PNV_IODA_PE_MASTER))
 613                 return state;
 614
 615         list_for_each_entry(slave, &pe->slaves, list) {
 616                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 617                                                 slave->pe_number,
 618                                                 &fstate,
 619                                                 &pcierr,
 620                                                 NULL);
 621                 if (rc != OPAL_SUCCESS) {
 622                         pr_warn("%s: Failure %lld getting "
 623                                 "PHB#%x-PE#%x state\n",
 624                                 __func__, rc,
 625                                 phb->hose->global_number, slave->pe_number);
 626                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 627                 }
 628
 629                 /*
 630                  * Override the result based on the ascending
 631                  * priority.
 632                  */
 633                 if (fstate > state)
 634                         state = fstate;
 635         }
 636
 637         return state;
 638 }
 639
 640 /* Currently those 2 are only used when MSIs are enabled, this will change
 641  * but in the meantime, we need to protect them to avoid warnings
 642  */
 643 #ifdef CONFIG_PCI_MSI
 644 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 645 {
 646         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 647         struct pnv_phb *phb = hose->private_data;
 648         struct pci_dn *pdn = pci_get_pdn(dev);
 649
 650         if (!pdn)
 651                 return NULL;
 652         if (pdn->pe_number == IODA_INVALID_PE)
 653                 return NULL;
 654         return &phb->ioda.pe_array[pdn->pe_number];
 655 }
 656 #endif /* CONFIG_PCI_MSI */
 657
 658 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 659                                   struct pnv_ioda_pe *parent,
 660                                   struct pnv_ioda_pe *child,
 661                                   bool is_add)
 662 {
 663         const char *desc = is_add ? "adding" : "removing";
 664         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 665                               OPAL_REMOVE_PE_FROM_DOMAIN;
 666         struct pnv_ioda_pe *slave;
 667         long rc;
 668
 669         /* Parent PE affects child PE */
 670         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 671                                 child->pe_number, op);
 672         if (rc != OPAL_SUCCESS) {
 673                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 674                         rc, desc);
 675                 return -ENXIO;
 676         }
 677
 678         if (!(child->flags & PNV_IODA_PE_MASTER))
 679                 return 0;
 680
 681         /* Compound case: parent PE affects slave PEs */
 682         list_for_each_entry(slave, &child->slaves, list) {
 683                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 684                                         slave->pe_number, op);
 685                 if (rc != OPAL_SUCCESS) {
 686                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 687                                 rc, desc);
 688                         return -ENXIO;
 689                 }
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 696                               struct pnv_ioda_pe *pe,
 697                               bool is_add)
 698 {
 699         struct pnv_ioda_pe *slave;
 700         struct pci_dev *pdev = NULL;
 701         int ret;
 702
 703         /*
 704          * Clear PE frozen state. If it's master PE, we need
 705          * clear slave PE frozen state as well.
 706          */
 707         if (is_add) {
 708                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 709                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 710                 if (pe->flags & PNV_IODA_PE_MASTER) {
 711                         list_for_each_entry(slave, &pe->slaves, list)
 712                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 713                                                           slave->pe_number,
 714                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 715                 }
 716         }
 717
 718         /*
 719          * Associate PE in PELT. We need add the PE into the
 720          * corresponding PELT-V as well. Otherwise, the error
 721          * originated from the PE might contribute to other
 722          * PEs.
 723          */
 724         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 725         if (ret)
 726                 return ret;
 727
 728         /* For compound PEs, any one affects all of them */
 729         if (pe->flags & PNV_IODA_PE_MASTER) {
 730                 list_for_each_entry(slave, &pe->slaves, list) {
 731                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 732                         if (ret)
 733                                 return ret;
 734                 }
 735         }
 736
 737         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 738                 pdev = pe->pbus->self;
 739         else if (pe->flags & PNV_IODA_PE_DEV)
 740                 pdev = pe->pdev->bus->self;
 741 #ifdef CONFIG_PCI_IOV
 742         else if (pe->flags & PNV_IODA_PE_VF)
 743                 pdev = pe->parent_dev;
 744 #endif /* CONFIG_PCI_IOV */
 745         while (pdev) {
 746                 struct pci_dn *pdn = pci_get_pdn(pdev);
 747                 struct pnv_ioda_pe *parent;
 748
 749                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 750                         parent = &phb->ioda.pe_array[pdn->pe_number];
 751                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 752                         if (ret)
 753                                 return ret;
 754                 }
 755
 756                 pdev = pdev->bus->self;
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 763 {
 764         struct pci_dev *parent;
 765         uint8_t bcomp, dcomp, fcomp;
 766         int64_t rc;
 767         long rid_end, rid;
 768
 769         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 770         if (pe->pbus) {
 771                 int count;
 772
 773                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 774                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 775                 parent = pe->pbus->self;
 776                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 777                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 778                 else
 779                         count = 1;
 780
 781                 switch(count) {
 782                 case  1: bcomp = OpalPciBusAll;         break;
 783                 case  2: bcomp = OpalPciBus7Bits;       break;
 784                 case  4: bcomp = OpalPciBus6Bits;       break;
 785                 case  8: bcomp = OpalPciBus5Bits;       break;
 786                 case 16: bcomp = OpalPciBus4Bits;       break;
 787                 case 32: bcomp = OpalPciBus3Bits;       break;
 788                 default:
 789                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 790                                 count);
 791                         /* Do an exact match only */
 792                         bcomp = OpalPciBusAll;
 793                 }
 794                 rid_end = pe->rid + (count << 8);
 795         } else {
 796 #ifdef CONFIG_PCI_IOV
 797                 if (pe->flags & PNV_IODA_PE_VF)
 798                         parent = pe->parent_dev;
 799                 else
 800 #endif
 801                         parent = pe->pdev->bus->self;
 802                 bcomp = OpalPciBusAll;
 803                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 804                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 805                 rid_end = pe->rid + 1;
 806         }
 807
 808         /* Clear the reverse map */
 809         for (rid = pe->rid; rid < rid_end; rid++)
 810                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 811
 812         /* Release from all parents PELT-V */
 813         while (parent) {
 814                 struct pci_dn *pdn = pci_get_pdn(parent);
 815                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 816                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 817                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 818                         /* XXX What to do in case of error ? */
 819                 }
 820                 parent = parent->bus->self;
 821         }
 822
 823         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 824                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 825
 826         /* Disassociate PE in PELT */
 827         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 828                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 829         if (rc)
 830                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 831         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 832                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 833         if (rc)
 834                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 835
 836         pe->pbus = NULL;
 837         pe->pdev = NULL;
 838 #ifdef CONFIG_PCI_IOV
 839         pe->parent_dev = NULL;
 840 #endif
 841
 842         return 0;
 843 }
 844
 845 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 846 {
 847         struct pci_dev *parent;
 848         uint8_t bcomp, dcomp, fcomp;
 849         long rc, rid_end, rid;
 850
 851         /* Bus validation ? */
 852         if (pe->pbus) {
 853                 int count;
 854
 855                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 856                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 857                 parent = pe->pbus->self;
 858                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 859                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 860                 else
 861                         count = 1;
 862
 863                 switch(count) {
 864                 case  1: bcomp = OpalPciBusAll;         break;
 865                 case  2: bcomp = OpalPciBus7Bits;       break;
 866                 case  4: bcomp = OpalPciBus6Bits;       break;
 867                 case  8: bcomp = OpalPciBus5Bits;       break;
 868                 case 16: bcomp = OpalPciBus4Bits;       break;
 869                 case 32: bcomp = OpalPciBus3Bits;       break;
 870                 default:
 871                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 872                                 count);
 873                         /* Do an exact match only */
 874                         bcomp = OpalPciBusAll;
 875                 }
 876                 rid_end = pe->rid + (count << 8);
 877         } else {
 878 #ifdef CONFIG_PCI_IOV
 879                 if (pe->flags & PNV_IODA_PE_VF)
 880                         parent = pe->parent_dev;
 881                 else
 882 #endif /* CONFIG_PCI_IOV */
 883                         parent = pe->pdev->bus->self;
 884                 bcomp = OpalPciBusAll;
 885                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 886                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 887                 rid_end = pe->rid + 1;
 888         }
 889
 890         /*
 891          * Associate PE in PELT. We need add the PE into the
 892          * corresponding PELT-V as well. Otherwise, the error
 893          * originated from the PE might contribute to other
 894          * PEs.
 895          */
 896         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 897                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 898         if (rc) {
 899                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 900                 return -ENXIO;
 901         }
 902
 903         /*
 904          * Configure PELTV. NPUs don't have a PELTV table so skip
 905          * configuration on them.
 906          */
 907         if (phb->type != PNV_PHB_NPU)
 908                 pnv_ioda_set_peltv(phb, pe, true);
 909
 910         /* Setup reverse map */
 911         for (rid = pe->rid; rid < rid_end; rid++)
 912                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 913
 914         /* Setup one MVTs on IODA1 */
 915         if (phb->type != PNV_PHB_IODA1) {
 916                 pe->mve_number = 0;
 917                 goto out;
 918         }
 919
 920         pe->mve_number = pe->pe_number;
 921         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 922         if (rc != OPAL_SUCCESS) {
 923                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 924                        rc, pe->mve_number);
 925                 pe->mve_number = -1;
 926         } else {
 927                 rc = opal_pci_set_mve_enable(phb->opal_id,
 928                                              pe->mve_number, OPAL_ENABLE_MVE);
 929                 if (rc) {
 930                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 931                                rc, pe->mve_number);
 932                         pe->mve_number = -1;
 933                 }
 934         }
 935
 936 out:
 937         return 0;
 938 }
 939
 940 #ifdef CONFIG_PCI_IOV
 941 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 942 {
 943         struct pci_dn *pdn = pci_get_pdn(dev);
 944         int i;
 945         struct resource *res, res2;
 946         resource_size_t size;
 947         u16 num_vfs;
 948
 949         if (!dev->is_physfn)
 950                 return -EINVAL;
 951
 952         /*
 953          * "offset" is in VFs.  The M64 windows are sized so that when they
 954          * are segmented, each segment is the same size as the IOV BAR.
 955          * Each segment is in a separate PE, and the high order bits of the
 956          * address are the PE number.  Therefore, each VF's BAR is in a
 957          * separate PE, and changing the IOV BAR start address changes the
 958          * range of PEs the VFs are in.
 959          */
 960         num_vfs = pdn->num_vfs;
 961         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 962                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 963                 if (!res->flags || !res->parent)
 964                         continue;
 965
 966                 /*
 967                  * The actual IOV BAR range is determined by the start address
 968                  * and the actual size for num_vfs VFs BAR.  This check is to
 969                  * make sure that after shifting, the range will not overlap
 970                  * with another device.
 971                  */
 972                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 973                 res2.flags = res->flags;
 974                 res2.start = res->start + (size * offset);
 975                 res2.end = res2.start + (size * num_vfs) - 1;
 976
 977                 if (res2.end > res->end) {
 978                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 979                                 i, &res2, res, num_vfs, offset);
 980                         return -EBUSY;
 981                 }
 982         }
 983
 984         /*
 985          * After doing so, there would be a "hole" in the /proc/iomem when
 986          * offset is a positive value. It looks like the device return some
 987          * mmio back to the system, which actually no one could use it.
 988          */
 989         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 990                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 991                 if (!res->flags || !res->parent)
 992                         continue;
 993
 994                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 995                 res2 = *res;
 996                 res->start += size * offset;
 997
 998                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
 999                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1000                          num_vfs, offset);
1001                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1002         }
1003         return 0;
1004 }
1005 #endif /* CONFIG_PCI_IOV */
1006
1007 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1008 {
1009         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1010         struct pnv_phb *phb = hose->private_data;
1011         struct pci_dn *pdn = pci_get_pdn(dev);
1012         struct pnv_ioda_pe *pe;
1013
1014         if (!pdn) {
1015                 pr_err("%s: Device tree node not associated properly\n",
1016                            pci_name(dev));
1017                 return NULL;
1018         }
1019         if (pdn->pe_number != IODA_INVALID_PE)
1020                 return NULL;
1021
1022         pe = pnv_ioda_alloc_pe(phb);
1023         if (!pe) {
1024                 pr_warning("%s: Not enough PE# available, disabling device\n",
1025                            pci_name(dev));
1026                 return NULL;
1027         }
1028
1029         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1030          * pointer in the PE data structure, both should be destroyed at the
1031          * same time. However, this needs to be looked at more closely again
1032          * once we actually start removing things (Hotplug, SR-IOV, ...)
1033          *
1034          * At some point we want to remove the PDN completely anyways
1035          */
1036         pci_dev_get(dev);
1037         pdn->pcidev = dev;
1038         pdn->pe_number = pe->pe_number;
1039         pe->flags = PNV_IODA_PE_DEV;
1040         pe->pdev = dev;
1041         pe->pbus = NULL;
1042         pe->mve_number = -1;
1043         pe->rid = dev->bus->number << 8 | pdn->devfn;
1044
1045         pe_info(pe, "Associated device to PE\n");
1046
1047         if (pnv_ioda_configure_pe(phb, pe)) {
1048                 /* XXX What do we do here ? */
1049                 pnv_ioda_free_pe(pe);
1050                 pdn->pe_number = IODA_INVALID_PE;
1051                 pe->pdev = NULL;
1052                 pci_dev_put(dev);
1053                 return NULL;
1054         }
1055
1056         /* Put PE to the list */
1057         list_add_tail(&pe->list, &phb->ioda.pe_list);
1058
1059         return pe;
1060 }
1061
1062 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1063 {
1064         struct pci_dev *dev;
1065
1066         list_for_each_entry(dev, &bus->devices, bus_list) {
1067                 struct pci_dn *pdn = pci_get_pdn(dev);
1068
1069                 if (pdn == NULL) {
1070                         pr_warn("%s: No device node associated with device !\n",
1071                                 pci_name(dev));
1072                         continue;
1073                 }
1074
1075                 /*
1076                  * In partial hotplug case, the PCI device might be still
1077                  * associated with the PE and needn't attach it to the PE
1078                  * again.
1079                  */
1080                 if (pdn->pe_number != IODA_INVALID_PE)
1081                         continue;
1082
1083                 pe->device_count++;
1084                 pdn->pcidev = dev;
1085                 pdn->pe_number = pe->pe_number;
1086                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1087                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1088         }
1089 }
1090
1091 /*
1092  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1093  * single PCI bus. Another one that contains the primary PCI bus and its
1094  * subordinate PCI devices and buses. The second type of PE is normally
1095  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1096  */
1097 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1098 {
1099         struct pci_controller *hose = pci_bus_to_host(bus);
1100         struct pnv_phb *phb = hose->private_data;
1101         struct pnv_ioda_pe *pe = NULL;
1102         unsigned int pe_num;
1103
1104         /*
1105          * In partial hotplug case, the PE instance might be still alive.
1106          * We should reuse it instead of allocating a new one.
1107          */
1108         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1109         if (pe_num != IODA_INVALID_PE) {
1110                 pe = &phb->ioda.pe_array[pe_num];
1111                 pnv_ioda_setup_same_PE(bus, pe);
1112                 return NULL;
1113         }
1114
1115         /* PE number for root bus should have been reserved */
1116         if (pci_is_root_bus(bus) &&
1117             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1118                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1119
1120         /* Check if PE is determined by M64 */
1121         if (!pe && phb->pick_m64_pe)
1122                 pe = phb->pick_m64_pe(bus, all);
1123
1124         /* The PE number isn't pinned by M64 */
1125         if (!pe)
1126                 pe = pnv_ioda_alloc_pe(phb);
1127
1128         if (!pe) {
1129                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1130                         __func__, pci_domain_nr(bus), bus->number);
1131                 return NULL;
1132         }
1133
1134         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1135         pe->pbus = bus;
1136         pe->pdev = NULL;
1137         pe->mve_number = -1;
1138         pe->rid = bus->busn_res.start << 8;
1139
1140         if (all)
1141                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1142                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1143         else
1144                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1145                         bus->busn_res.start, pe->pe_number);
1146
1147         if (pnv_ioda_configure_pe(phb, pe)) {
1148                 /* XXX What do we do here ? */
1149                 pnv_ioda_free_pe(pe);
1150                 pe->pbus = NULL;
1151                 return NULL;
1152         }
1153
1154         /* Associate it with all child devices */
1155         pnv_ioda_setup_same_PE(bus, pe);
1156
1157         /* Put PE to the list */
1158         list_add_tail(&pe->list, &phb->ioda.pe_list);
1159
1160         return pe;
1161 }
1162
1163 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1164 {
1165         int pe_num, found_pe = false, rc;
1166         long rid;
1167         struct pnv_ioda_pe *pe;
1168         struct pci_dev *gpu_pdev;
1169         struct pci_dn *npu_pdn;
1170         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1171         struct pnv_phb *phb = hose->private_data;
1172
1173         /*
1174          * Due to a hardware errata PE#0 on the NPU is reserved for
1175          * error handling. This means we only have three PEs remaining
1176          * which need to be assigned to four links, implying some
1177          * links must share PEs.
1178          *
1179          * To achieve this we assign PEs such that NPUs linking the
1180          * same GPU get assigned the same PE.
1181          */
1182         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1183         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1184                 pe = &phb->ioda.pe_array[pe_num];
1185                 if (!pe->pdev)
1186                         continue;
1187
1188                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1189                         /*
1190                          * This device has the same peer GPU so should
1191                          * be assigned the same PE as the existing
1192                          * peer NPU.
1193                          */
1194                         dev_info(&npu_pdev->dev,
1195                                 "Associating to existing PE %d\n", pe_num);
1196                         pci_dev_get(npu_pdev);
1197                         npu_pdn = pci_get_pdn(npu_pdev);
1198                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1199                         npu_pdn->pcidev = npu_pdev;
1200                         npu_pdn->pe_number = pe_num;
1201                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1202
1203                         /* Map the PE to this link */
1204                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1205                                         OpalPciBusAll,
1206                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1207                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1208                                         OPAL_MAP_PE);
1209                         WARN_ON(rc != OPAL_SUCCESS);
1210                         found_pe = true;
1211                         break;
1212                 }
1213         }
1214
1215         if (!found_pe)
1216                 /*
1217                  * Could not find an existing PE so allocate a new
1218                  * one.
1219                  */
1220                 return pnv_ioda_setup_dev_PE(npu_pdev);
1221         else
1222                 return pe;
1223 }
1224
1225 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1226 {
1227         struct pci_dev *pdev;
1228
1229         list_for_each_entry(pdev, &bus->devices, bus_list)
1230                 pnv_ioda_setup_npu_PE(pdev);
1231 }
1232
1233 static void pnv_pci_ioda_setup_PEs(void)
1234 {
1235         struct pci_controller *hose, *tmp;
1236         struct pnv_phb *phb;
1237
1238         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1239                 phb = hose->private_data;
1240                 if (phb->type == PNV_PHB_NPU) {
1241                         /* PE#0 is needed for error reporting */
1242                         pnv_ioda_reserve_pe(phb, 0);
1243                         pnv_ioda_setup_npu_PEs(hose->bus);
1244                 }
1245         }
1246 }
1247
1248 #ifdef CONFIG_PCI_IOV
1249 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1250 {
1251         struct pci_bus        *bus;
1252         struct pci_controller *hose;
1253         struct pnv_phb        *phb;
1254         struct pci_dn         *pdn;
1255         int                    i, j;
1256         int                    m64_bars;
1257
1258         bus = pdev->bus;
1259         hose = pci_bus_to_host(bus);
1260         phb = hose->private_data;
1261         pdn = pci_get_pdn(pdev);
1262
1263         if (pdn->m64_single_mode)
1264                 m64_bars = num_vfs;
1265         else
1266                 m64_bars = 1;
1267
1268         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1269                 for (j = 0; j < m64_bars; j++) {
1270                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1271                                 continue;
1272                         opal_pci_phb_mmio_enable(phb->opal_id,
1273                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1274                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1275                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1276                 }
1277
1278         kfree(pdn->m64_map);
1279         return 0;
1280 }
1281
1282 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1283 {
1284         struct pci_bus        *bus;
1285         struct pci_controller *hose;
1286         struct pnv_phb        *phb;
1287         struct pci_dn         *pdn;
1288         unsigned int           win;
1289         struct resource       *res;
1290         int                    i, j;
1291         int64_t                rc;
1292         int                    total_vfs;
1293         resource_size_t        size, start;
1294         int                    pe_num;
1295         int                    m64_bars;
1296
1297         bus = pdev->bus;
1298         hose = pci_bus_to_host(bus);
1299         phb = hose->private_data;
1300         pdn = pci_get_pdn(pdev);
1301         total_vfs = pci_sriov_get_totalvfs(pdev);
1302
1303         if (pdn->m64_single_mode)
1304                 m64_bars = num_vfs;
1305         else
1306                 m64_bars = 1;
1307
1308         pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1309         if (!pdn->m64_map)
1310                 return -ENOMEM;
1311         /* Initialize the m64_map to IODA_INVALID_M64 */
1312         for (i = 0; i < m64_bars ; i++)
1313                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1314                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1315
1316
1317         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1318                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1319                 if (!res->flags || !res->parent)
1320                         continue;
1321
1322                 for (j = 0; j < m64_bars; j++) {
1323                         do {
1324                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1325                                                 phb->ioda.m64_bar_idx + 1, 0);
1326
1327                                 if (win >= phb->ioda.m64_bar_idx + 1)
1328                                         goto m64_failed;
1329                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1330
1331                         pdn->m64_map[j][i] = win;
1332
1333                         if (pdn->m64_single_mode) {
1334                                 size = pci_iov_resource_size(pdev,
1335                                                         PCI_IOV_RESOURCES + i);
1336                                 start = res->start + size * j;
1337                         } else {
1338                                 size = resource_size(res);
1339                                 start = res->start;
1340                         }
1341
1342                         /* Map the M64 here */
1343                         if (pdn->m64_single_mode) {
1344                                 pe_num = pdn->pe_num_map[j];
1345                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1346                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1347                                                 pdn->m64_map[j][i], 0);
1348                         }
1349
1350                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1351                                                  OPAL_M64_WINDOW_TYPE,
1352                                                  pdn->m64_map[j][i],
1353                                                  start,
1354                                                  0, /* unused */
1355                                                  size);
1356
1357
1358                         if (rc != OPAL_SUCCESS) {
1359                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1360                                         win, rc);
1361                                 goto m64_failed;
1362                         }
1363
1364                         if (pdn->m64_single_mode)
1365                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1366                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1367                         else
1368                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1369                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1370
1371                         if (rc != OPAL_SUCCESS) {
1372                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1373                                         win, rc);
1374                                 goto m64_failed;
1375                         }
1376                 }
1377         }
1378         return 0;
1379
1380 m64_failed:
1381         pnv_pci_vf_release_m64(pdev, num_vfs);
1382         return -EBUSY;
1383 }
1384
1385 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1386                 int num);
1387 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1388
1389 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1390 {
1391         struct iommu_table    *tbl;
1392         int64_t               rc;
1393
1394         tbl = pe->table_group.tables[0];
1395         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1396         if (rc)
1397                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1398
1399         pnv_pci_ioda2_set_bypass(pe, false);
1400         if (pe->table_group.group) {
1401                 iommu_group_put(pe->table_group.group);
1402                 BUG_ON(pe->table_group.group);
1403         }
1404         pnv_pci_ioda2_table_free_pages(tbl);
1405         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1406 }
1407
1408 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1409 {
1410         struct pci_bus        *bus;
1411         struct pci_controller *hose;
1412         struct pnv_phb        *phb;
1413         struct pnv_ioda_pe    *pe, *pe_n;
1414         struct pci_dn         *pdn;
1415
1416         bus = pdev->bus;
1417         hose = pci_bus_to_host(bus);
1418         phb = hose->private_data;
1419         pdn = pci_get_pdn(pdev);
1420
1421         if (!pdev->is_physfn)
1422                 return;
1423
1424         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1425                 if (pe->parent_dev != pdev)
1426                         continue;
1427
1428                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1429
1430                 /* Remove from list */
1431                 mutex_lock(&phb->ioda.pe_list_mutex);
1432                 list_del(&pe->list);
1433                 mutex_unlock(&phb->ioda.pe_list_mutex);
1434
1435                 pnv_ioda_deconfigure_pe(phb, pe);
1436
1437                 pnv_ioda_free_pe(pe);
1438         }
1439 }
1440
1441 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1442 {
1443         struct pci_bus        *bus;
1444         struct pci_controller *hose;
1445         struct pnv_phb        *phb;
1446         struct pnv_ioda_pe    *pe;
1447         struct pci_dn         *pdn;
1448         struct pci_sriov      *iov;
1449         u16                    num_vfs, i;
1450
1451         bus = pdev->bus;
1452         hose = pci_bus_to_host(bus);
1453         phb = hose->private_data;
1454         pdn = pci_get_pdn(pdev);
1455         iov = pdev->sriov;
1456         num_vfs = pdn->num_vfs;
1457
1458         /* Release VF PEs */
1459         pnv_ioda_release_vf_PE(pdev);
1460
1461         if (phb->type == PNV_PHB_IODA2) {
1462                 if (!pdn->m64_single_mode)
1463                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1464
1465                 /* Release M64 windows */
1466                 pnv_pci_vf_release_m64(pdev, num_vfs);
1467
1468                 /* Release PE numbers */
1469                 if (pdn->m64_single_mode) {
1470                         for (i = 0; i < num_vfs; i++) {
1471                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1472                                         continue;
1473
1474                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1475                                 pnv_ioda_free_pe(pe);
1476                         }
1477                 } else
1478                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1479                 /* Releasing pe_num_map */
1480                 kfree(pdn->pe_num_map);
1481         }
1482 }
1483
1484 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1485                                        struct pnv_ioda_pe *pe);
1486 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1487 {
1488         struct pci_bus        *bus;
1489         struct pci_controller *hose;
1490         struct pnv_phb        *phb;
1491         struct pnv_ioda_pe    *pe;
1492         int                    pe_num;
1493         u16                    vf_index;
1494         struct pci_dn         *pdn;
1495
1496         bus = pdev->bus;
1497         hose = pci_bus_to_host(bus);
1498         phb = hose->private_data;
1499         pdn = pci_get_pdn(pdev);
1500
1501         if (!pdev->is_physfn)
1502                 return;
1503
1504         /* Reserve PE for each VF */
1505         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1506                 if (pdn->m64_single_mode)
1507                         pe_num = pdn->pe_num_map[vf_index];
1508                 else
1509                         pe_num = *pdn->pe_num_map + vf_index;
1510
1511                 pe = &phb->ioda.pe_array[pe_num];
1512                 pe->pe_number = pe_num;
1513                 pe->phb = phb;
1514                 pe->flags = PNV_IODA_PE_VF;
1515                 pe->pbus = NULL;
1516                 pe->parent_dev = pdev;
1517                 pe->mve_number = -1;
1518                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1519                            pci_iov_virtfn_devfn(pdev, vf_index);
1520
1521                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1522                         hose->global_number, pdev->bus->number,
1523                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1524                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1525
1526                 if (pnv_ioda_configure_pe(phb, pe)) {
1527                         /* XXX What do we do here ? */
1528                         pnv_ioda_free_pe(pe);
1529                         pe->pdev = NULL;
1530                         continue;
1531                 }
1532
1533                 /* Put PE to the list */
1534                 mutex_lock(&phb->ioda.pe_list_mutex);
1535                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1536                 mutex_unlock(&phb->ioda.pe_list_mutex);
1537
1538                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1539         }
1540 }
1541
1542 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1543 {
1544         struct pci_bus        *bus;
1545         struct pci_controller *hose;
1546         struct pnv_phb        *phb;
1547         struct pnv_ioda_pe    *pe;
1548         struct pci_dn         *pdn;
1549         int                    ret;
1550         u16                    i;
1551
1552         bus = pdev->bus;
1553         hose = pci_bus_to_host(bus);
1554         phb = hose->private_data;
1555         pdn = pci_get_pdn(pdev);
1556
1557         if (phb->type == PNV_PHB_IODA2) {
1558                 if (!pdn->vfs_expanded) {
1559                         dev_info(&pdev->dev, "don't support this SRIOV device"
1560                                 " with non 64bit-prefetchable IOV BAR\n");
1561                         return -ENOSPC;
1562                 }
1563
1564                 /*
1565                  * When M64 BARs functions in Single PE mode, the number of VFs
1566                  * could be enabled must be less than the number of M64 BARs.
1567                  */
1568                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1569                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1570                         return -EBUSY;
1571                 }
1572
1573                 /* Allocating pe_num_map */
1574                 if (pdn->m64_single_mode)
1575                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1576                                         GFP_KERNEL);
1577                 else
1578                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1579
1580                 if (!pdn->pe_num_map)
1581                         return -ENOMEM;
1582
1583                 if (pdn->m64_single_mode)
1584                         for (i = 0; i < num_vfs; i++)
1585                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1586
1587                 /* Calculate available PE for required VFs */
1588                 if (pdn->m64_single_mode) {
1589                         for (i = 0; i < num_vfs; i++) {
1590                                 pe = pnv_ioda_alloc_pe(phb);
1591                                 if (!pe) {
1592                                         ret = -EBUSY;
1593                                         goto m64_failed;
1594                                 }
1595
1596                                 pdn->pe_num_map[i] = pe->pe_number;
1597                         }
1598                 } else {
1599                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1600                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1601                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1602                                 0, num_vfs, 0);
1603                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1604                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1605                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1606                                 kfree(pdn->pe_num_map);
1607                                 return -EBUSY;
1608                         }
1609                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1610                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1611                 }
1612                 pdn->num_vfs = num_vfs;
1613
1614                 /* Assign M64 window accordingly */
1615                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1616                 if (ret) {
1617                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1618                         goto m64_failed;
1619                 }
1620
1621                 /*
1622                  * When using one M64 BAR to map one IOV BAR, we need to shift
1623                  * the IOV BAR according to the PE# allocated to the VFs.
1624                  * Otherwise, the PE# for the VF will conflict with others.
1625                  */
1626                 if (!pdn->m64_single_mode) {
1627                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1628                         if (ret)
1629                                 goto m64_failed;
1630                 }
1631         }
1632
1633         /* Setup VF PEs */
1634         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1635
1636         return 0;
1637
1638 m64_failed:
1639         if (pdn->m64_single_mode) {
1640                 for (i = 0; i < num_vfs; i++) {
1641                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1642                                 continue;
1643
1644                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1645                         pnv_ioda_free_pe(pe);
1646                 }
1647         } else
1648                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1649
1650         /* Releasing pe_num_map */
1651         kfree(pdn->pe_num_map);
1652
1653         return ret;
1654 }
1655
1656 int pcibios_sriov_disable(struct pci_dev *pdev)
1657 {
1658         pnv_pci_sriov_disable(pdev);
1659
1660         /* Release PCI data */
1661         remove_dev_pci_data(pdev);
1662         return 0;
1663 }
1664
1665 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1666 {
1667         /* Allocate PCI data */
1668         add_dev_pci_data(pdev);
1669
1670         return pnv_pci_sriov_enable(pdev, num_vfs);
1671 }
1672 #endif /* CONFIG_PCI_IOV */
1673
1674 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1675 {
1676         struct pci_dn *pdn = pci_get_pdn(pdev);
1677         struct pnv_ioda_pe *pe;
1678
1679         /*
1680          * The function can be called while the PE#
1681          * hasn't been assigned. Do nothing for the
1682          * case.
1683          */
1684         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1685                 return;
1686
1687         pe = &phb->ioda.pe_array[pdn->pe_number];
1688         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1689         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1690         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1691         /*
1692          * Note: iommu_add_device() will fail here as
1693          * for physical PE: the device is already added by now;
1694          * for virtual PE: sysfs entries are not ready yet and
1695          * tce_iommu_bus_notifier will add the device to a group later.
1696          */
1697 }
1698
1699 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1700 {
1701         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1702         struct pnv_phb *phb = hose->private_data;
1703         struct pci_dn *pdn = pci_get_pdn(pdev);
1704         struct pnv_ioda_pe *pe;
1705         uint64_t top;
1706         bool bypass = false;
1707
1708         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1709                 return -ENODEV;;
1710
1711         pe = &phb->ioda.pe_array[pdn->pe_number];
1712         if (pe->tce_bypass_enabled) {
1713                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1714                 bypass = (dma_mask >= top);
1715         }
1716
1717         if (bypass) {
1718                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1719                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1720         } else {
1721                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1722                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1723         }
1724         *pdev->dev.dma_mask = dma_mask;
1725
1726         /* Update peer npu devices */
1727         pnv_npu_try_dma_set_bypass(pdev, bypass);
1728
1729         return 0;
1730 }
1731
1732 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1733 {
1734         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1735         struct pnv_phb *phb = hose->private_data;
1736         struct pci_dn *pdn = pci_get_pdn(pdev);
1737         struct pnv_ioda_pe *pe;
1738         u64 end, mask;
1739
1740         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1741                 return 0;
1742
1743         pe = &phb->ioda.pe_array[pdn->pe_number];
1744         if (!pe->tce_bypass_enabled)
1745                 return __dma_get_required_mask(&pdev->dev);
1746
1747
1748         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1749         mask = 1ULL << (fls64(end) - 1);
1750         mask += mask - 1;
1751
1752         return mask;
1753 }
1754
1755 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1756                                    struct pci_bus *bus)
1757 {
1758         struct pci_dev *dev;
1759
1760         list_for_each_entry(dev, &bus->devices, bus_list) {
1761                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1762                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1763                 iommu_add_device(&dev->dev);
1764
1765                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1766                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1767         }
1768 }
1769
1770 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1771                                                      bool real_mode)
1772 {
1773         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1774                 (phb->regs + 0x210);
1775 }
1776
1777 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1778                 unsigned long index, unsigned long npages, bool rm)
1779 {
1780         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1781                         &tbl->it_group_list, struct iommu_table_group_link,
1782                         next);
1783         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1784                         struct pnv_ioda_pe, table_group);
1785         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1786         unsigned long start, end, inc;
1787
1788         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1789         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1790                         npages - 1);
1791
1792         /* p7ioc-style invalidation, 2 TCEs per write */
1793         start |= (1ull << 63);
1794         end |= (1ull << 63);
1795         inc = 16;
1796         end |= inc - 1; /* round up end to be different than start */
1797
1798         mb(); /* Ensure above stores are visible */
1799         while (start <= end) {
1800                 if (rm)
1801                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1802                 else
1803                         __raw_writeq(cpu_to_be64(start), invalidate);
1804                 start += inc;
1805         }
1806
1807         /*
1808          * The iommu layer will do another mb() for us on build()
1809          * and we don't care on free()
1810          */
1811 }
1812
1813 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1814                 long npages, unsigned long uaddr,
1815                 enum dma_data_direction direction,
1816                 unsigned long attrs)
1817 {
1818         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1819                         attrs);
1820
1821         if (!ret)
1822                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1823
1824         return ret;
1825 }
1826
1827 #ifdef CONFIG_IOMMU_API
1828 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1829                 unsigned long *hpa, enum dma_data_direction *direction)
1830 {
1831         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1832
1833         if (!ret)
1834                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1835
1836         return ret;
1837 }
1838 #endif
1839
1840 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1841                 long npages)
1842 {
1843         pnv_tce_free(tbl, index, npages);
1844
1845         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1846 }
1847
1848 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1849         .set = pnv_ioda1_tce_build,
1850 #ifdef CONFIG_IOMMU_API
1851         .exchange = pnv_ioda1_tce_xchg,
1852 #endif
1853         .clear = pnv_ioda1_tce_free,
1854         .get = pnv_tce_get,
1855 };
1856
1857 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1858 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1859 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1860
1861 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1862 {
1863         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1864         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1865
1866         mb(); /* Ensure previous TCE table stores are visible */
1867         if (rm)
1868                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1869         else
1870                 __raw_writeq(cpu_to_be64(val), invalidate);
1871 }
1872
1873 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1874 {
1875         /* 01xb - invalidate TCEs that match the specified PE# */
1876         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1877         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1878
1879         mb(); /* Ensure above stores are visible */
1880         __raw_writeq(cpu_to_be64(val), invalidate);
1881 }
1882
1883 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1884                                         unsigned shift, unsigned long index,
1885                                         unsigned long npages)
1886 {
1887         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1888         unsigned long start, end, inc;
1889
1890         /* We'll invalidate DMA address in PE scope */
1891         start = PHB3_TCE_KILL_INVAL_ONE;
1892         start |= (pe->pe_number & 0xFF);
1893         end = start;
1894
1895         /* Figure out the start, end and step */
1896         start |= (index << shift);
1897         end |= ((index + npages - 1) << shift);
1898         inc = (0x1ull << shift);
1899         mb();
1900
1901         while (start <= end) {
1902                 if (rm)
1903                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1904                 else
1905                         __raw_writeq(cpu_to_be64(start), invalidate);
1906                 start += inc;
1907         }
1908 }
1909
1910 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1911 {
1912         struct pnv_phb *phb = pe->phb;
1913
1914         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1915                 pnv_pci_phb3_tce_invalidate_pe(pe);
1916         else
1917                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1918                                   pe->pe_number, 0, 0, 0);
1919 }
1920
1921 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1922                 unsigned long index, unsigned long npages, bool rm)
1923 {
1924         struct iommu_table_group_link *tgl;
1925
1926         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1927                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1928                                 struct pnv_ioda_pe, table_group);
1929                 struct pnv_phb *phb = pe->phb;
1930                 unsigned int shift = tbl->it_page_shift;
1931
1932                 if (phb->type == PNV_PHB_NPU) {
1933                         /*
1934                          * The NVLink hardware does not support TCE kill
1935                          * per TCE entry so we have to invalidate
1936                          * the entire cache for it.
1937                          */
1938                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1939                         continue;
1940                 }
1941                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1942                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1943                                                     index, npages);
1944                 else if (rm)
1945                         opal_rm_pci_tce_kill(phb->opal_id,
1946                                              OPAL_PCI_TCE_KILL_PAGES,
1947                                              pe->pe_number, 1u << shift,
1948                                              index << shift, npages);
1949                 else
1950                         opal_pci_tce_kill(phb->opal_id,
1951                                           OPAL_PCI_TCE_KILL_PAGES,
1952                                           pe->pe_number, 1u << shift,
1953                                           index << shift, npages);
1954         }
1955 }
1956
1957 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1958                 long npages, unsigned long uaddr,
1959                 enum dma_data_direction direction,
1960                 unsigned long attrs)
1961 {
1962         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1963                         attrs);
1964
1965         if (!ret)
1966                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1967
1968         return ret;
1969 }
1970
1971 #ifdef CONFIG_IOMMU_API
1972 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1973                 unsigned long *hpa, enum dma_data_direction *direction)
1974 {
1975         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1976
1977         if (!ret)
1978                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1979
1980         return ret;
1981 }
1982 #endif
1983
1984 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1985                 long npages)
1986 {
1987         pnv_tce_free(tbl, index, npages);
1988
1989         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1990 }
1991
1992 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1993 {
1994         pnv_pci_ioda2_table_free_pages(tbl);
1995         iommu_free_table(tbl, "pnv");
1996 }
1997
1998 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1999         .set = pnv_ioda2_tce_build,
2000 #ifdef CONFIG_IOMMU_API
2001         .exchange = pnv_ioda2_tce_xchg,
2002 #endif
2003         .clear = pnv_ioda2_tce_free,
2004         .get = pnv_tce_get,
2005         .free = pnv_ioda2_table_free,
2006 };
2007
2008 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2009 {
2010         unsigned int *weight = (unsigned int *)data;
2011
2012         /* This is quite simplistic. The "base" weight of a device
2013          * is 10. 0 means no DMA is to be accounted for it.
2014          */
2015         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2016                 return 0;
2017
2018         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2019             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2020             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2021                 *weight += 3;
2022         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2023                 *weight += 15;
2024         else
2025                 *weight += 10;
2026
2027         return 0;
2028 }
2029
2030 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2031 {
2032         unsigned int weight = 0;
2033
2034         /* SRIOV VF has same DMA32 weight as its PF */
2035 #ifdef CONFIG_PCI_IOV
2036         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2037                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2038                 return weight;
2039         }
2040 #endif
2041
2042         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2043                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2044         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2045                 struct pci_dev *pdev;
2046
2047                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2048                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2049         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2050                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2051         }
2052
2053         return weight;
2054 }
2055
2056 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2057                                        struct pnv_ioda_pe *pe)
2058 {
2059
2060         struct page *tce_mem = NULL;
2061         struct iommu_table *tbl;
2062         unsigned int weight, total_weight = 0;
2063         unsigned int tce32_segsz, base, segs, avail, i;
2064         int64_t rc;
2065         void *addr;
2066
2067         /* XXX FIXME: Handle 64-bit only DMA devices */
2068         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2069         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2070         weight = pnv_pci_ioda_pe_dma_weight(pe);
2071         if (!weight)
2072                 return;
2073
2074         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2075                      &total_weight);
2076         segs = (weight * phb->ioda.dma32_count) / total_weight;
2077         if (!segs)
2078                 segs = 1;
2079
2080         /*
2081          * Allocate contiguous DMA32 segments. We begin with the expected
2082          * number of segments. With one more attempt, the number of DMA32
2083          * segments to be allocated is decreased by one until one segment
2084          * is allocated successfully.
2085          */
2086         do {
2087                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2088                         for (avail = 0, i = base; i < base + segs; i++) {
2089                                 if (phb->ioda.dma32_segmap[i] ==
2090                                     IODA_INVALID_PE)
2091                                         avail++;
2092                         }
2093
2094                         if (avail == segs)
2095                                 goto found;
2096                 }
2097         } while (--segs);
2098
2099         if (!segs) {
2100                 pe_warn(pe, "No available DMA32 segments\n");
2101                 return;
2102         }
2103
2104 found:
2105         tbl = pnv_pci_table_alloc(phb->hose->node);
2106         iommu_register_group(&pe->table_group, phb->hose->global_number,
2107                         pe->pe_number);
2108         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2109
2110         /* Grab a 32-bit TCE table */
2111         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2112                 weight, total_weight, base, segs);
2113         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2114                 base * PNV_IODA1_DMA32_SEGSIZE,
2115                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2116
2117         /* XXX Currently, we allocate one big contiguous table for the
2118          * TCEs. We only really need one chunk per 256M of TCE space
2119          * (ie per segment) but that's an optimization for later, it
2120          * requires some added smarts with our get/put_tce implementation
2121          *
2122          * Each TCE page is 4KB in size and each TCE entry occupies 8
2123          * bytes
2124          */
2125         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2126         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2127                                    get_order(tce32_segsz * segs));
2128         if (!tce_mem) {
2129                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2130                 goto fail;
2131         }
2132         addr = page_address(tce_mem);
2133         memset(addr, 0, tce32_segsz * segs);
2134
2135         /* Configure HW */
2136         for (i = 0; i < segs; i++) {
2137                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2138                                               pe->pe_number,
2139                                               base + i, 1,
2140                                               __pa(addr) + tce32_segsz * i,
2141                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2142                 if (rc) {
2143                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2144                                " err %ld\n", rc);
2145                         goto fail;
2146                 }
2147         }
2148
2149         /* Setup DMA32 segment mapping */
2150         for (i = base; i < base + segs; i++)
2151                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2152
2153         /* Setup linux iommu table */
2154         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2155                                   base * PNV_IODA1_DMA32_SEGSIZE,
2156                                   IOMMU_PAGE_SHIFT_4K);
2157
2158         tbl->it_ops = &pnv_ioda1_iommu_ops;
2159         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2160         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2161         iommu_init_table(tbl, phb->hose->node);
2162
2163         if (pe->flags & PNV_IODA_PE_DEV) {
2164                 /*
2165                  * Setting table base here only for carrying iommu_group
2166                  * further down to let iommu_add_device() do the job.
2167                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2168                  */
2169                 set_iommu_table_base(&pe->pdev->dev, tbl);
2170                 iommu_add_device(&pe->pdev->dev);
2171         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2172                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2173
2174         return;
2175  fail:
2176         /* XXX Failure: Try to fallback to 64-bit only ? */
2177         if (tce_mem)
2178                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2179         if (tbl) {
2180                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2181                 iommu_free_table(tbl, "pnv");
2182         }
2183 }
2184
2185 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2186                 int num, struct iommu_table *tbl)
2187 {
2188         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2189                         table_group);
2190         struct pnv_phb *phb = pe->phb;
2191         int64_t rc;
2192         const unsigned long size = tbl->it_indirect_levels ?
2193                         tbl->it_level_size : tbl->it_size;
2194         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2195         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2196
2197         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2198                         start_addr, start_addr + win_size - 1,
2199                         IOMMU_PAGE_SIZE(tbl));
2200
2201         /*
2202          * Map TCE table through TVT. The TVE index is the PE number
2203          * shifted by 1 bit for 32-bits DMA space.
2204          */
2205         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2206                         pe->pe_number,
2207                         (pe->pe_number << 1) + num,
2208                         tbl->it_indirect_levels + 1,
2209                         __pa(tbl->it_base),
2210                         size << 3,
2211                         IOMMU_PAGE_SIZE(tbl));
2212         if (rc) {
2213                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2214                 return rc;
2215         }
2216
2217         pnv_pci_link_table_and_group(phb->hose->node, num,
2218                         tbl, &pe->table_group);
2219         pnv_pci_phb3_tce_invalidate_pe(pe);
2220
2221         return 0;
2222 }
2223
2224 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2225 {
2226         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2227         int64_t rc;
2228
2229         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2230         if (enable) {
2231                 phys_addr_t top = memblock_end_of_DRAM();
2232
2233                 top = roundup_pow_of_two(top);
2234                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2235                                                      pe->pe_number,
2236                                                      window_id,
2237                                                      pe->tce_bypass_base,
2238                                                      top);
2239         } else {
2240                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2241                                                      pe->pe_number,
2242                                                      window_id,
2243                                                      pe->tce_bypass_base,
2244                                                      0);
2245         }
2246         if (rc)
2247                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2248         else
2249                 pe->tce_bypass_enabled = enable;
2250 }
2251
2252 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2253                 __u32 page_shift, __u64 window_size, __u32 levels,
2254                 struct iommu_table *tbl);
2255
2256 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2257                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2258                 struct iommu_table **ptbl)
2259 {
2260         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2261                         table_group);
2262         int nid = pe->phb->hose->node;
2263         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2264         long ret;
2265         struct iommu_table *tbl;
2266
2267         tbl = pnv_pci_table_alloc(nid);
2268         if (!tbl)
2269                 return -ENOMEM;
2270
2271         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2272                         bus_offset, page_shift, window_size,
2273                         levels, tbl);
2274         if (ret) {
2275                 iommu_free_table(tbl, "pnv");
2276                 return ret;
2277         }
2278
2279         tbl->it_ops = &pnv_ioda2_iommu_ops;
2280
2281         *ptbl = tbl;
2282
2283         return 0;
2284 }
2285
2286 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2287 {
2288         struct iommu_table *tbl = NULL;
2289         long rc;
2290
2291         /*
2292          * crashkernel= specifies the kdump kernel's maximum memory at
2293          * some offset and there is no guaranteed the result is a power
2294          * of 2, which will cause errors later.
2295          */
2296         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2297
2298         /*
2299          * In memory constrained environments, e.g. kdump kernel, the
2300          * DMA window can be larger than available memory, which will
2301          * cause errors later.
2302          */
2303         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2304
2305         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2306                         IOMMU_PAGE_SHIFT_4K,
2307                         window_size,
2308                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2309         if (rc) {
2310                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2311                                 rc);
2312                 return rc;
2313         }
2314
2315         iommu_init_table(tbl, pe->phb->hose->node);
2316
2317         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2318         if (rc) {
2319                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2320                                 rc);
2321                 pnv_ioda2_table_free(tbl);
2322                 return rc;
2323         }
2324
2325         if (!pnv_iommu_bypass_disabled)
2326                 pnv_pci_ioda2_set_bypass(pe, true);
2327
2328         /*
2329          * Setting table base here only for carrying iommu_group
2330          * further down to let iommu_add_device() do the job.
2331          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2332          */
2333         if (pe->flags & PNV_IODA_PE_DEV)
2334                 set_iommu_table_base(&pe->pdev->dev, tbl);
2335
2336         return 0;
2337 }
2338
2339 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2340 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2341                 int num)
2342 {
2343         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2344                         table_group);
2345         struct pnv_phb *phb = pe->phb;
2346         long ret;
2347
2348         pe_info(pe, "Removing DMA window #%d\n", num);
2349
2350         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2351                         (pe->pe_number << 1) + num,
2352                         0/* levels */, 0/* table address */,
2353                         0/* table size */, 0/* page size */);
2354         if (ret)
2355                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2356         else
2357                 pnv_pci_phb3_tce_invalidate_pe(pe);
2358
2359         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2360
2361         return ret;
2362 }
2363 #endif
2364
2365 #ifdef CONFIG_IOMMU_API
2366 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2367                 __u64 window_size, __u32 levels)
2368 {
2369         unsigned long bytes = 0;
2370         const unsigned window_shift = ilog2(window_size);
2371         unsigned entries_shift = window_shift - page_shift;
2372         unsigned table_shift = entries_shift + 3;
2373         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2374         unsigned long direct_table_size;
2375
2376         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2377                         (window_size > memory_hotplug_max()) ||
2378                         !is_power_of_2(window_size))
2379                 return 0;
2380
2381         /* Calculate a direct table size from window_size and levels */
2382         entries_shift = (entries_shift + levels - 1) / levels;
2383         table_shift = entries_shift + 3;
2384         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2385         direct_table_size =  1UL << table_shift;
2386
2387         for ( ; levels; --levels) {
2388                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2389
2390                 tce_table_size /= direct_table_size;
2391                 tce_table_size <<= 3;
2392                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2393         }
2394
2395         return bytes;
2396 }
2397
2398 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2399 {
2400         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2401                                                 table_group);
2402         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2403         struct iommu_table *tbl = pe->table_group.tables[0];
2404
2405         pnv_pci_ioda2_set_bypass(pe, false);
2406         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2407         pnv_ioda2_table_free(tbl);
2408 }
2409
2410 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2411 {
2412         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2413                                                 table_group);
2414
2415         pnv_pci_ioda2_setup_default_config(pe);
2416 }
2417
2418 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2419         .get_table_size = pnv_pci_ioda2_get_table_size,
2420         .create_table = pnv_pci_ioda2_create_table,
2421         .set_window = pnv_pci_ioda2_set_window,
2422         .unset_window = pnv_pci_ioda2_unset_window,
2423         .take_ownership = pnv_ioda2_take_ownership,
2424         .release_ownership = pnv_ioda2_release_ownership,
2425 };
2426
2427 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2428 {
2429         struct pci_controller *hose;
2430         struct pnv_phb *phb;
2431         struct pnv_ioda_pe **ptmppe = opaque;
2432         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2433         struct pci_dn *pdn = pci_get_pdn(pdev);
2434
2435         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2436                 return 0;
2437
2438         hose = pci_bus_to_host(pdev->bus);
2439         phb = hose->private_data;
2440         if (phb->type != PNV_PHB_NPU)
2441                 return 0;
2442
2443         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2444
2445         return 1;
2446 }
2447
2448 /*
2449  * This returns PE of associated NPU.
2450  * This assumes that NPU is in the same IOMMU group with GPU and there is
2451  * no other PEs.
2452  */
2453 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2454                 struct iommu_table_group *table_group)
2455 {
2456         struct pnv_ioda_pe *npe = NULL;
2457         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2458                         gpe_table_group_to_npe_cb);
2459
2460         BUG_ON(!ret || !npe);
2461
2462         return npe;
2463 }
2464
2465 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2466                 int num, struct iommu_table *tbl)
2467 {
2468         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2469
2470         if (ret)
2471                 return ret;
2472
2473         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2474         if (ret)
2475                 pnv_pci_ioda2_unset_window(table_group, num);
2476
2477         return ret;
2478 }
2479
2480 static long pnv_pci_ioda2_npu_unset_window(
2481                 struct iommu_table_group *table_group,
2482                 int num)
2483 {
2484         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2485
2486         if (ret)
2487                 return ret;
2488
2489         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2490 }
2491
2492 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2493 {
2494         /*
2495          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2496          * the iommu_table if 32bit DMA is enabled.
2497          */
2498         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2499         pnv_ioda2_take_ownership(table_group);
2500 }
2501
2502 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2503         .get_table_size = pnv_pci_ioda2_get_table_size,
2504         .create_table = pnv_pci_ioda2_create_table,
2505         .set_window = pnv_pci_ioda2_npu_set_window,
2506         .unset_window = pnv_pci_ioda2_npu_unset_window,
2507         .take_ownership = pnv_ioda2_npu_take_ownership,
2508         .release_ownership = pnv_ioda2_release_ownership,
2509 };
2510
2511 static void pnv_pci_ioda_setup_iommu_api(void)
2512 {
2513         struct pci_controller *hose, *tmp;
2514         struct pnv_phb *phb;
2515         struct pnv_ioda_pe *pe, *gpe;
2516
2517         /*
2518          * Now we have all PHBs discovered, time to add NPU devices to
2519          * the corresponding IOMMU groups.
2520          */
2521         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2522                 phb = hose->private_data;
2523
2524                 if (phb->type != PNV_PHB_NPU)
2525                         continue;
2526
2527                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2528                         gpe = pnv_pci_npu_setup_iommu(pe);
2529                         if (gpe)
2530                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2531                 }
2532         }
2533 }
2534 #else /* !CONFIG_IOMMU_API */
2535 static void pnv_pci_ioda_setup_iommu_api(void) { };
2536 #endif
2537
2538 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2539                 unsigned levels, unsigned long limit,
2540                 unsigned long *current_offset, unsigned long *total_allocated)
2541 {
2542         struct page *tce_mem = NULL;
2543         __be64 *addr, *tmp;
2544         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2545         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2546         unsigned entries = 1UL << (shift - 3);
2547         long i;
2548
2549         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2550         if (!tce_mem) {
2551                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2552                 return NULL;
2553         }
2554         addr = page_address(tce_mem);
2555         memset(addr, 0, allocated);
2556         *total_allocated += allocated;
2557
2558         --levels;
2559         if (!levels) {
2560                 *current_offset += allocated;
2561                 return addr;
2562         }
2563
2564         for (i = 0; i < entries; ++i) {
2565                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2566                                 levels, limit, current_offset, total_allocated);
2567                 if (!tmp)
2568                         break;
2569
2570                 addr[i] = cpu_to_be64(__pa(tmp) |
2571                                 TCE_PCI_READ | TCE_PCI_WRITE);
2572
2573                 if (*current_offset >= limit)
2574                         break;
2575         }
2576
2577         return addr;
2578 }
2579
2580 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2581                 unsigned long size, unsigned level);
2582
2583 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2584                 __u32 page_shift, __u64 window_size, __u32 levels,
2585                 struct iommu_table *tbl)
2586 {
2587         void *addr;
2588         unsigned long offset = 0, level_shift, total_allocated = 0;
2589         const unsigned window_shift = ilog2(window_size);
2590         unsigned entries_shift = window_shift - page_shift;
2591         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2592         const unsigned long tce_table_size = 1UL << table_shift;
2593
2594         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2595                 return -EINVAL;
2596
2597         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2598                 return -EINVAL;
2599
2600         /* Adjust direct table size from window_size and levels */
2601         entries_shift = (entries_shift + levels - 1) / levels;
2602         level_shift = entries_shift + 3;
2603         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2604
2605         /* Allocate TCE table */
2606         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2607                         levels, tce_table_size, &offset, &total_allocated);
2608
2609         /* addr==NULL means that the first level allocation failed */
2610         if (!addr)
2611                 return -ENOMEM;
2612
2613         /*
2614          * First level was allocated but some lower level failed as
2615          * we did not allocate as much as we wanted,
2616          * release partially allocated table.
2617          */
2618         if (offset < tce_table_size) {
2619                 pnv_pci_ioda2_table_do_free_pages(addr,
2620                                 1ULL << (level_shift - 3), levels - 1);
2621                 return -ENOMEM;
2622         }
2623
2624         /* Setup linux iommu table */
2625         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2626                         page_shift);
2627         tbl->it_level_size = 1ULL << (level_shift - 3);
2628         tbl->it_indirect_levels = levels - 1;
2629         tbl->it_allocated_size = total_allocated;
2630
2631         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2632                         window_size, tce_table_size, bus_offset);
2633
2634         return 0;
2635 }
2636
2637 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2638                 unsigned long size, unsigned level)
2639 {
2640         const unsigned long addr_ul = (unsigned long) addr &
2641                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2642
2643         if (level) {
2644                 long i;
2645                 u64 *tmp = (u64 *) addr_ul;
2646
2647                 for (i = 0; i < size; ++i) {
2648                         unsigned long hpa = be64_to_cpu(tmp[i]);
2649
2650                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2651                                 continue;
2652
2653                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2654                                         level - 1);
2655                 }
2656         }
2657
2658         free_pages(addr_ul, get_order(size << 3));
2659 }
2660
2661 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2662 {
2663         const unsigned long size = tbl->it_indirect_levels ?
2664                         tbl->it_level_size : tbl->it_size;
2665
2666         if (!tbl->it_size)
2667                 return;
2668
2669         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2670                         tbl->it_indirect_levels);
2671 }
2672
2673 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2674                                        struct pnv_ioda_pe *pe)
2675 {
2676         int64_t rc;
2677
2678         if (!pnv_pci_ioda_pe_dma_weight(pe))
2679                 return;
2680
2681         /* TVE #1 is selected by PCI address bit 59 */
2682         pe->tce_bypass_base = 1ull << 59;
2683
2684         iommu_register_group(&pe->table_group, phb->hose->global_number,
2685                         pe->pe_number);
2686
2687         /* The PE will reserve all possible 32-bits space */
2688         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2689                 phb->ioda.m32_pci_base);
2690
2691         /* Setup linux iommu table */
2692         pe->table_group.tce32_start = 0;
2693         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2694         pe->table_group.max_dynamic_windows_supported =
2695                         IOMMU_TABLE_GROUP_MAX_TABLES;
2696         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2697         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2698 #ifdef CONFIG_IOMMU_API
2699         pe->table_group.ops = &pnv_pci_ioda2_ops;
2700 #endif
2701
2702         rc = pnv_pci_ioda2_setup_default_config(pe);
2703         if (rc)
2704                 return;
2705
2706         if (pe->flags & PNV_IODA_PE_DEV)
2707                 iommu_add_device(&pe->pdev->dev);
2708         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2709                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2710 }
2711
2712 #ifdef CONFIG_PCI_MSI
2713 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2714 {
2715         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2716                                            ioda.irq_chip);
2717
2718         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2719 }
2720
2721 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2722 {
2723         int64_t rc;
2724         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2725         struct irq_chip *chip = irq_data_get_irq_chip(d);
2726
2727         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2728         WARN_ON_ONCE(rc);
2729
2730         icp_native_eoi(d);
2731 }
2732
2733
2734 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2735 {
2736         struct irq_data *idata;
2737         struct irq_chip *ichip;
2738
2739         /* The MSI EOI OPAL call is only needed on PHB3 */
2740         if (phb->model != PNV_PHB_MODEL_PHB3)
2741                 return;
2742
2743         if (!phb->ioda.irq_chip_init) {
2744                 /*
2745                  * First time we setup an MSI IRQ, we need to setup the
2746                  * corresponding IRQ chip to route correctly.
2747                  */
2748                 idata = irq_get_irq_data(virq);
2749                 ichip = irq_data_get_irq_chip(idata);
2750                 phb->ioda.irq_chip_init = 1;
2751                 phb->ioda.irq_chip = *ichip;
2752                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2753         }
2754         irq_set_chip(virq, &phb->ioda.irq_chip);
2755 }
2756
2757 /*
2758  * Returns true iff chip is something that we could call
2759  * pnv_opal_pci_msi_eoi for.
2760  */
2761 bool is_pnv_opal_msi(struct irq_chip *chip)
2762 {
2763         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2764 }
2765 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2766
2767 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2768                                   unsigned int hwirq, unsigned int virq,
2769                                   unsigned int is_64, struct msi_msg *msg)
2770 {
2771         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2772         unsigned int xive_num = hwirq - phb->msi_base;
2773         __be32 data;
2774         int rc;
2775
2776         /* No PE assigned ? bail out ... no MSI for you ! */
2777         if (pe == NULL)
2778                 return -ENXIO;
2779
2780         /* Check if we have an MVE */
2781         if (pe->mve_number < 0)
2782                 return -ENXIO;
2783
2784         /* Force 32-bit MSI on some broken devices */
2785         if (dev->no_64bit_msi)
2786                 is_64 = 0;
2787
2788         /* Assign XIVE to PE */
2789         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2790         if (rc) {
2791                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2792                         pci_name(dev), rc, xive_num);
2793                 return -EIO;
2794         }
2795
2796         if (is_64) {
2797                 __be64 addr64;
2798
2799                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2800                                      &addr64, &data);
2801                 if (rc) {
2802                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2803                                 pci_name(dev), rc);
2804                         return -EIO;
2805                 }
2806                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2807                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2808         } else {
2809                 __be32 addr32;
2810
2811                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2812                                      &addr32, &data);
2813                 if (rc) {
2814                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2815                                 pci_name(dev), rc);
2816                         return -EIO;
2817                 }
2818                 msg->address_hi = 0;
2819                 msg->address_lo = be32_to_cpu(addr32);
2820         }
2821         msg->data = be32_to_cpu(data);
2822
2823         pnv_set_msi_irq_chip(phb, virq);
2824
2825         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2826                  " address=%x_%08x data=%x PE# %d\n",
2827                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2828                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2829
2830         return 0;
2831 }
2832
2833 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2834 {
2835         unsigned int count;
2836         const __be32 *prop = of_get_property(phb->hose->dn,
2837                                              "ibm,opal-msi-ranges", NULL);
2838         if (!prop) {
2839                 /* BML Fallback */
2840                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2841         }
2842         if (!prop)
2843                 return;
2844
2845         phb->msi_base = be32_to_cpup(prop);
2846         count = be32_to_cpup(prop + 1);
2847         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2848                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2849                        phb->hose->global_number);
2850                 return;
2851         }
2852
2853         phb->msi_setup = pnv_pci_ioda_msi_setup;
2854         phb->msi32_support = 1;
2855         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2856                 count, phb->msi_base);
2857 }
2858 #else
2859 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2860 #endif /* CONFIG_PCI_MSI */
2861
2862 #ifdef CONFIG_PCI_IOV
2863 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2864 {
2865         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2866         struct pnv_phb *phb = hose->private_data;
2867         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2868         struct resource *res;
2869         int i;
2870         resource_size_t size, total_vf_bar_sz;
2871         struct pci_dn *pdn;
2872         int mul, total_vfs;
2873
2874         if (!pdev->is_physfn || pdev->is_added)
2875                 return;
2876
2877         pdn = pci_get_pdn(pdev);
2878         pdn->vfs_expanded = 0;
2879         pdn->m64_single_mode = false;
2880
2881         total_vfs = pci_sriov_get_totalvfs(pdev);
2882         mul = phb->ioda.total_pe_num;
2883         total_vf_bar_sz = 0;
2884
2885         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2886                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2887                 if (!res->flags || res->parent)
2888                         continue;
2889                 if (!pnv_pci_is_m64(phb, res)) {
2890                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2891                                         " non M64 VF BAR%d: %pR. \n",
2892                                  i, res);
2893                         goto truncate_iov;
2894                 }
2895
2896                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2897                                 i + PCI_IOV_RESOURCES);
2898
2899                 /*
2900                  * If bigger than quarter of M64 segment size, just round up
2901                  * power of two.
2902                  *
2903                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2904                  * with other devices, IOV BAR size is expanded to be
2905                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2906                  * segment size , the expanded size would equal to half of the
2907                  * whole M64 space size, which will exhaust the M64 Space and
2908                  * limit the system flexibility.  This is a design decision to
2909                  * set the boundary to quarter of the M64 segment size.
2910                  */
2911                 if (total_vf_bar_sz > gate) {
2912                         mul = roundup_pow_of_two(total_vfs);
2913                         dev_info(&pdev->dev,
2914                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2915                                 total_vf_bar_sz, gate, mul);
2916                         pdn->m64_single_mode = true;
2917                         break;
2918                 }
2919         }
2920
2921         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2922                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2923                 if (!res->flags || res->parent)
2924                         continue;
2925
2926                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2927                 /*
2928                  * On PHB3, the minimum size alignment of M64 BAR in single
2929                  * mode is 32MB.
2930                  */
2931                 if (pdn->m64_single_mode && (size < SZ_32M))
2932                         goto truncate_iov;
2933                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2934                 res->end = res->start + size * mul - 1;
2935                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2936                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2937                          i, res, mul);
2938         }
2939         pdn->vfs_expanded = mul;
2940
2941         return;
2942
2943 truncate_iov:
2944         /* To save MMIO space, IOV BAR is truncated. */
2945         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2946                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2947                 res->flags = 0;
2948                 res->end = res->start - 1;
2949         }
2950 }
2951 #endif /* CONFIG_PCI_IOV */
2952
2953 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2954                                   struct resource *res)
2955 {
2956         struct pnv_phb *phb = pe->phb;
2957         struct pci_bus_region region;
2958         int index;
2959         int64_t rc;
2960
2961         if (!res || !res->flags || res->start > res->end)
2962                 return;
2963
2964         if (res->flags & IORESOURCE_IO) {
2965                 region.start = res->start - phb->ioda.io_pci_base;
2966                 region.end   = res->end - phb->ioda.io_pci_base;
2967                 index = region.start / phb->ioda.io_segsize;
2968
2969                 while (index < phb->ioda.total_pe_num &&
2970                        region.start <= region.end) {
2971                         phb->ioda.io_segmap[index] = pe->pe_number;
2972                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2973                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2974                         if (rc != OPAL_SUCCESS) {
2975                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
2976                                        __func__, rc, index, pe->pe_number);
2977                                 break;
2978                         }
2979
2980                         region.start += phb->ioda.io_segsize;
2981                         index++;
2982                 }
2983         } else if ((res->flags & IORESOURCE_MEM) &&
2984                    !pnv_pci_is_m64(phb, res)) {
2985                 region.start = res->start -
2986                                phb->hose->mem_offset[0] -
2987                                phb->ioda.m32_pci_base;
2988                 region.end   = res->end -
2989                                phb->hose->mem_offset[0] -
2990                                phb->ioda.m32_pci_base;
2991                 index = region.start / phb->ioda.m32_segsize;
2992
2993                 while (index < phb->ioda.total_pe_num &&
2994                        region.start <= region.end) {
2995                         phb->ioda.m32_segmap[index] = pe->pe_number;
2996                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2997                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2998                         if (rc != OPAL_SUCCESS) {
2999                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
3000                                        __func__, rc, index, pe->pe_number);
3001                                 break;
3002                         }
3003
3004                         region.start += phb->ioda.m32_segsize;
3005                         index++;
3006                 }
3007         }
3008 }
3009
3010 /*
3011  * This function is supposed to be called on basis of PE from top
3012  * to bottom style. So the the I/O or MMIO segment assigned to
3013  * parent PE could be overrided by its child PEs if necessary.
3014  */
3015 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3016 {
3017         struct pci_dev *pdev;
3018         int i;
3019
3020         /*
3021          * NOTE: We only care PCI bus based PE for now. For PCI
3022          * device based PE, for example SRIOV sensitive VF should
3023          * be figured out later.
3024          */
3025         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3026
3027         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3028                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3029                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3030
3031                 /*
3032                  * If the PE contains all subordinate PCI buses, the
3033                  * windows of the child bridges should be mapped to
3034                  * the PE as well.
3035                  */
3036                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3037                         continue;
3038                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3039                         pnv_ioda_setup_pe_res(pe,
3040                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3041         }
3042 }
3043
3044 static void pnv_pci_ioda_create_dbgfs(void)
3045 {
3046 #ifdef CONFIG_DEBUG_FS
3047         struct pci_controller *hose, *tmp;
3048         struct pnv_phb *phb;
3049         char name[16];
3050
3051         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3052                 phb = hose->private_data;
3053
3054                 /* Notify initialization of PHB done */
3055                 phb->initialized = 1;
3056
3057                 sprintf(name, "PCI%04x", hose->global_number);
3058                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3059                 if (!phb->dbgfs)
3060                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3061                                 __func__, hose->global_number);
3062         }
3063 #endif /* CONFIG_DEBUG_FS */
3064 }
3065
3066 static void pnv_pci_ioda_fixup(void)
3067 {
3068         pnv_pci_ioda_setup_PEs();
3069         pnv_pci_ioda_setup_iommu_api();
3070         pnv_pci_ioda_create_dbgfs();
3071
3072 #ifdef CONFIG_EEH
3073         eeh_init();
3074         eeh_addr_cache_build();
3075 #endif
3076 }
3077
3078 /*
3079  * Returns the alignment for I/O or memory windows for P2P
3080  * bridges. That actually depends on how PEs are segmented.
3081  * For now, we return I/O or M32 segment size for PE sensitive
3082  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3083  * 1MiB for memory) will be returned.
3084  *
3085  * The current PCI bus might be put into one PE, which was
3086  * create against the parent PCI bridge. For that case, we
3087  * needn't enlarge the alignment so that we can save some
3088  * resources.
3089  */
3090 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3091                                                 unsigned long type)
3092 {
3093         struct pci_dev *bridge;
3094         struct pci_controller *hose = pci_bus_to_host(bus);
3095         struct pnv_phb *phb = hose->private_data;
3096         int num_pci_bridges = 0;
3097
3098         bridge = bus->self;
3099         while (bridge) {
3100                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3101                         num_pci_bridges++;
3102                         if (num_pci_bridges >= 2)
3103                                 return 1;
3104                 }
3105
3106                 bridge = bridge->bus->self;
3107         }
3108
3109         /*
3110          * We fall back to M32 if M64 isn't supported. We enforce the M64
3111          * alignment for any 64-bit resource, PCIe doesn't care and
3112          * bridges only do 64-bit prefetchable anyway.
3113          */
3114         if (phb->ioda.m64_segsize && (type & IORESOURCE_MEM_64))
3115                 return phb->ioda.m64_segsize;
3116         if (type & IORESOURCE_MEM)
3117                 return phb->ioda.m32_segsize;
3118
3119         return phb->ioda.io_segsize;
3120 }
3121
3122 /*
3123  * We are updating root port or the upstream port of the
3124  * bridge behind the root port with PHB's windows in order
3125  * to accommodate the changes on required resources during
3126  * PCI (slot) hotplug, which is connected to either root
3127  * port or the downstream ports of PCIe switch behind the
3128  * root port.
3129  */
3130 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3131                                            unsigned long type)
3132 {
3133         struct pci_controller *hose = pci_bus_to_host(bus);
3134         struct pnv_phb *phb = hose->private_data;
3135         struct pci_dev *bridge = bus->self;
3136         struct resource *r, *w;
3137         bool msi_region = false;
3138         int i;
3139
3140         /* Check if we need apply fixup to the bridge's windows */
3141         if (!pci_is_root_bus(bridge->bus) &&
3142             !pci_is_root_bus(bridge->bus->self->bus))
3143                 return;
3144
3145         /* Fixup the resources */
3146         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3147                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3148                 if (!r->flags || !r->parent)
3149                         continue;
3150
3151                 w = NULL;
3152                 if (r->flags & type & IORESOURCE_IO)
3153                         w = &hose->io_resource;
3154                 else if (pnv_pci_is_m64(phb, r) &&
3155                          (type & IORESOURCE_PREFETCH) &&
3156                          phb->ioda.m64_segsize)
3157                         w = &hose->mem_resources[1];
3158                 else if (r->flags & type & IORESOURCE_MEM) {
3159                         w = &hose->mem_resources[0];
3160                         msi_region = true;
3161                 }
3162
3163                 r->start = w->start;
3164                 r->end = w->end;
3165
3166                 /* The 64KB 32-bits MSI region shouldn't be included in
3167                  * the 32-bits bridge window. Otherwise, we can see strange
3168                  * issues. One of them is EEH error observed on Garrison.
3169                  *
3170                  * Exclude top 1MB region which is the minimal alignment of
3171                  * 32-bits bridge window.
3172                  */
3173                 if (msi_region) {
3174                         r->end += 0x10000;
3175                         r->end -= 0x100000;
3176                 }
3177         }
3178 }
3179
3180 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3181 {
3182         struct pci_controller *hose = pci_bus_to_host(bus);
3183         struct pnv_phb *phb = hose->private_data;
3184         struct pci_dev *bridge = bus->self;
3185         struct pnv_ioda_pe *pe;
3186         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3187
3188         /* Extend bridge's windows if necessary */
3189         pnv_pci_fixup_bridge_resources(bus, type);
3190
3191         /* The PE for root bus should be realized before any one else */
3192         if (!phb->ioda.root_pe_populated) {
3193                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3194                 if (pe) {
3195                         phb->ioda.root_pe_idx = pe->pe_number;
3196                         phb->ioda.root_pe_populated = true;
3197                 }
3198         }
3199
3200         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3201         if (list_empty(&bus->devices))
3202                 return;
3203
3204         /* Reserve PEs according to used M64 resources */
3205         if (phb->reserve_m64_pe)
3206                 phb->reserve_m64_pe(bus, NULL, all);
3207
3208         /*
3209          * Assign PE. We might run here because of partial hotplug.
3210          * For the case, we just pick up the existing PE and should
3211          * not allocate resources again.
3212          */
3213         pe = pnv_ioda_setup_bus_PE(bus, all);
3214         if (!pe)
3215                 return;
3216
3217         pnv_ioda_setup_pe_seg(pe);
3218         switch (phb->type) {
3219         case PNV_PHB_IODA1:
3220                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3221                 break;
3222         case PNV_PHB_IODA2:
3223                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3224                 break;
3225         default:
3226                 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3227                         __func__, phb->hose->global_number, phb->type);
3228         }
3229 }
3230
3231 #ifdef CONFIG_PCI_IOV
3232 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3233                                                       int resno)
3234 {
3235         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3236         struct pnv_phb *phb = hose->private_data;
3237         struct pci_dn *pdn = pci_get_pdn(pdev);
3238         resource_size_t align;
3239
3240         /*
3241          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3242          * SR-IOV. While from hardware perspective, the range mapped by M64
3243          * BAR should be size aligned.
3244          *
3245          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3246          * powernv-specific hardware restriction is gone. But if just use the
3247          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3248          * in one segment of M64 #15, which introduces the PE conflict between
3249          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3250          * m64_segsize.
3251          *
3252          * This function returns the total IOV BAR size if M64 BAR is in
3253          * Shared PE mode or just VF BAR size if not.
3254          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3255          * M64 segment size if IOV BAR size is less.
3256          */
3257         align = pci_iov_resource_size(pdev, resno);
3258         if (!pdn->vfs_expanded)
3259                 return align;
3260         if (pdn->m64_single_mode)
3261                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3262
3263         return pdn->vfs_expanded * align;
3264 }
3265 #endif /* CONFIG_PCI_IOV */
3266
3267 /* Prevent enabling devices for which we couldn't properly
3268  * assign a PE
3269  */
3270 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3271 {
3272         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3273         struct pnv_phb *phb = hose->private_data;
3274         struct pci_dn *pdn;
3275
3276         /* The function is probably called while the PEs have
3277          * not be created yet. For example, resource reassignment
3278          * during PCI probe period. We just skip the check if
3279          * PEs isn't ready.
3280          */
3281         if (!phb->initialized)
3282                 return true;
3283
3284         pdn = pci_get_pdn(dev);
3285         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3286                 return false;
3287
3288         return true;
3289 }
3290
3291 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3292                                        int num)
3293 {
3294         struct pnv_ioda_pe *pe = container_of(table_group,
3295                                               struct pnv_ioda_pe, table_group);
3296         struct pnv_phb *phb = pe->phb;
3297         unsigned int idx;
3298         long rc;
3299
3300         pe_info(pe, "Removing DMA window #%d\n", num);
3301         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3302                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3303                         continue;
3304
3305                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3306                                                 idx, 0, 0ul, 0ul, 0ul);
3307                 if (rc != OPAL_SUCCESS) {
3308                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3309                                 rc, idx);
3310                         return rc;
3311                 }
3312
3313                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3314         }
3315
3316         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3317         return OPAL_SUCCESS;
3318 }
3319
3320 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3321 {
3322         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3323         struct iommu_table *tbl = pe->table_group.tables[0];
3324         int64_t rc;
3325
3326         if (!weight)
3327                 return;
3328
3329         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3330         if (rc != OPAL_SUCCESS)
3331                 return;
3332
3333         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3334         if (pe->table_group.group) {
3335                 iommu_group_put(pe->table_group.group);
3336                 WARN_ON(pe->table_group.group);
3337         }
3338
3339         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3340         iommu_free_table(tbl, "pnv");
3341 }
3342
3343 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3344 {
3345         struct iommu_table *tbl = pe->table_group.tables[0];
3346         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3347 #ifdef CONFIG_IOMMU_API
3348         int64_t rc;
3349 #endif
3350
3351         if (!weight)
3352                 return;
3353
3354 #ifdef CONFIG_IOMMU_API
3355         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3356         if (rc)
3357                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3358 #endif
3359
3360         pnv_pci_ioda2_set_bypass(pe, false);
3361         if (pe->table_group.group) {
3362                 iommu_group_put(pe->table_group.group);
3363                 WARN_ON(pe->table_group.group);
3364         }
3365
3366         pnv_pci_ioda2_table_free_pages(tbl);
3367         iommu_free_table(tbl, "pnv");
3368 }
3369
3370 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3371                                  unsigned short win,
3372                                  unsigned int *map)
3373 {
3374         struct pnv_phb *phb = pe->phb;
3375         int idx;
3376         int64_t rc;
3377
3378         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3379                 if (map[idx] != pe->pe_number)
3380                         continue;
3381
3382                 if (win == OPAL_M64_WINDOW_TYPE)
3383                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3384                                         phb->ioda.reserved_pe_idx, win,
3385                                         idx / PNV_IODA1_M64_SEGS,
3386                                         idx % PNV_IODA1_M64_SEGS);
3387                 else
3388                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3389                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3390
3391                 if (rc != OPAL_SUCCESS)
3392                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3393                                 rc, win, idx);
3394
3395                 map[idx] = IODA_INVALID_PE;
3396         }
3397 }
3398
3399 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3400 {
3401         struct pnv_phb *phb = pe->phb;
3402
3403         if (phb->type == PNV_PHB_IODA1) {
3404                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3405                                      phb->ioda.io_segmap);
3406                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3407                                      phb->ioda.m32_segmap);
3408                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3409                                      phb->ioda.m64_segmap);
3410         } else if (phb->type == PNV_PHB_IODA2) {
3411                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3412                                      phb->ioda.m32_segmap);
3413         }
3414 }
3415
3416 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3417 {
3418         struct pnv_phb *phb = pe->phb;
3419         struct pnv_ioda_pe *slave, *tmp;
3420
3421         /* Release slave PEs in compound PE */
3422         if (pe->flags & PNV_IODA_PE_MASTER) {
3423                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list)
3424                         pnv_ioda_release_pe(slave);
3425         }
3426
3427         list_del(&pe->list);
3428         switch (phb->type) {
3429         case PNV_PHB_IODA1:
3430                 pnv_pci_ioda1_release_pe_dma(pe);
3431                 break;
3432         case PNV_PHB_IODA2:
3433                 pnv_pci_ioda2_release_pe_dma(pe);
3434                 break;
3435         default:
3436                 WARN_ON(1);
3437         }
3438
3439         pnv_ioda_release_pe_seg(pe);
3440         pnv_ioda_deconfigure_pe(pe->phb, pe);
3441         pnv_ioda_free_pe(pe);
3442 }
3443
3444 static void pnv_pci_release_device(struct pci_dev *pdev)
3445 {
3446         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3447         struct pnv_phb *phb = hose->private_data;
3448         struct pci_dn *pdn = pci_get_pdn(pdev);
3449         struct pnv_ioda_pe *pe;
3450
3451         if (pdev->is_virtfn)
3452                 return;
3453
3454         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3455                 return;
3456
3457         pe = &phb->ioda.pe_array[pdn->pe_number];
3458         WARN_ON(--pe->device_count < 0);
3459         if (pe->device_count == 0)
3460                 pnv_ioda_release_pe(pe);
3461 }
3462
3463 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3464 {
3465         struct pnv_phb *phb = hose->private_data;
3466
3467         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3468                        OPAL_ASSERT_RESET);
3469 }
3470
3471 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3472         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3473         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3474 #ifdef CONFIG_PCI_MSI
3475         .setup_msi_irqs         = pnv_setup_msi_irqs,
3476         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3477 #endif
3478         .enable_device_hook     = pnv_pci_enable_device_hook,
3479         .release_device         = pnv_pci_release_device,
3480         .window_alignment       = pnv_pci_window_alignment,
3481         .setup_bridge           = pnv_pci_setup_bridge,
3482         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3483         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3484         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3485         .shutdown               = pnv_pci_ioda_shutdown,
3486 };
3487
3488 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3489 {
3490         dev_err_once(&npdev->dev,
3491                         "%s operation unsupported for NVLink devices\n",
3492                         __func__);
3493         return -EPERM;
3494 }
3495
3496 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3497         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3498 #ifdef CONFIG_PCI_MSI
3499         .setup_msi_irqs         = pnv_setup_msi_irqs,
3500         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3501 #endif
3502         .enable_device_hook     = pnv_pci_enable_device_hook,
3503         .window_alignment       = pnv_pci_window_alignment,
3504         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3505         .dma_set_mask           = pnv_npu_dma_set_mask,
3506         .shutdown               = pnv_pci_ioda_shutdown,
3507 };
3508
3509 #ifdef CONFIG_CXL_BASE
3510 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3511         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3512         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3513 #ifdef CONFIG_PCI_MSI
3514         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3515         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3516 #endif
3517         .enable_device_hook     = pnv_cxl_enable_device_hook,
3518         .disable_device         = pnv_cxl_disable_device,
3519         .release_device         = pnv_pci_release_device,
3520         .window_alignment       = pnv_pci_window_alignment,
3521         .setup_bridge           = pnv_pci_setup_bridge,
3522         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3523         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3524         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3525         .shutdown               = pnv_pci_ioda_shutdown,
3526 };
3527 #endif
3528
3529 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3530                                          u64 hub_id, int ioda_type)
3531 {
3532         struct pci_controller *hose;
3533         struct pnv_phb *phb;
3534         unsigned long size, m64map_off, m32map_off, pemap_off;
3535         unsigned long iomap_off = 0, dma32map_off = 0;
3536         struct resource r;
3537         const __be64 *prop64;
3538         const __be32 *prop32;
3539         int len;
3540         unsigned int segno;
3541         u64 phb_id;
3542         void *aux;
3543         long rc;
3544
3545         if (!of_device_is_available(np))
3546                 return;
3547
3548         pr_info("Initializing %s PHB (%s)\n",
3549                 pnv_phb_names[ioda_type], of_node_full_name(np));
3550
3551         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3552         if (!prop64) {
3553                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3554                 return;
3555         }
3556         phb_id = be64_to_cpup(prop64);
3557         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3558
3559         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3560
3561         /* Allocate PCI controller */
3562         phb->hose = hose = pcibios_alloc_controller(np);
3563         if (!phb->hose) {
3564                 pr_err("  Can't allocate PCI controller for %s\n",
3565                        np->full_name);
3566                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3567                 return;
3568         }
3569
3570         spin_lock_init(&phb->lock);
3571         prop32 = of_get_property(np, "bus-range", &len);
3572         if (prop32 && len == 8) {
3573                 hose->first_busno = be32_to_cpu(prop32[0]);
3574                 hose->last_busno = be32_to_cpu(prop32[1]);
3575         } else {
3576                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3577                 hose->first_busno = 0;
3578                 hose->last_busno = 0xff;
3579         }
3580         hose->private_data = phb;
3581         phb->hub_id = hub_id;
3582         phb->opal_id = phb_id;
3583         phb->type = ioda_type;
3584         mutex_init(&phb->ioda.pe_alloc_mutex);
3585
3586         /* Detect specific models for error handling */
3587         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3588                 phb->model = PNV_PHB_MODEL_P7IOC;
3589         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3590                 phb->model = PNV_PHB_MODEL_PHB3;
3591         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3592                 phb->model = PNV_PHB_MODEL_NPU;
3593         else
3594                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3595
3596         /* Parse 32-bit and IO ranges (if any) */
3597         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3598
3599         /* Get registers */
3600         if (!of_address_to_resource(np, 0, &r)) {
3601                 phb->regs_phys = r.start;
3602                 phb->regs = ioremap(r.start, resource_size(&r));
3603                 if (phb->regs == NULL)
3604                         pr_err("  Failed to map registers !\n");
3605         }
3606
3607         /* Initialize more IODA stuff */
3608         phb->ioda.total_pe_num = 1;
3609         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3610         if (prop32)
3611                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3612         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3613         if (prop32)
3614                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3615
3616         /* Invalidate RID to PE# mapping */
3617         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3618                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3619
3620         /* Parse 64-bit MMIO range */
3621         pnv_ioda_parse_m64_window(phb);
3622
3623         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3624         /* FW Has already off top 64k of M32 space (MSI space) */
3625         phb->ioda.m32_size += 0x10000;
3626
3627         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3628         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3629         phb->ioda.io_size = hose->pci_io_size;
3630         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3631         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3632
3633         /* Calculate how many 32-bit TCE segments we have */
3634         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3635                                 PNV_IODA1_DMA32_SEGSIZE;
3636
3637         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3638         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3639                         sizeof(unsigned long));
3640         m64map_off = size;
3641         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3642         m32map_off = size;
3643         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3644         if (phb->type == PNV_PHB_IODA1) {
3645                 iomap_off = size;
3646                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3647                 dma32map_off = size;
3648                 size += phb->ioda.dma32_count *
3649                         sizeof(phb->ioda.dma32_segmap[0]);
3650         }
3651         pemap_off = size;
3652         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3653         aux = memblock_virt_alloc(size, 0);
3654         phb->ioda.pe_alloc = aux;
3655         phb->ioda.m64_segmap = aux + m64map_off;
3656         phb->ioda.m32_segmap = aux + m32map_off;
3657         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3658                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3659                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3660         }
3661         if (phb->type == PNV_PHB_IODA1) {
3662                 phb->ioda.io_segmap = aux + iomap_off;
3663                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3664                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3665
3666                 phb->ioda.dma32_segmap = aux + dma32map_off;
3667                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3668                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3669         }
3670         phb->ioda.pe_array = aux + pemap_off;
3671
3672         /*
3673          * Choose PE number for root bus, which shouldn't have
3674          * M64 resources consumed by its child devices. To pick
3675          * the PE number adjacent to the reserved one if possible.
3676          */
3677         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3678         if (phb->ioda.reserved_pe_idx == 0) {
3679                 phb->ioda.root_pe_idx = 1;
3680                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3681         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3682                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3683                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3684         } else {
3685                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3686         }
3687
3688         INIT_LIST_HEAD(&phb->ioda.pe_list);
3689         mutex_init(&phb->ioda.pe_list_mutex);
3690
3691         /* Calculate how many 32-bit TCE segments we have */
3692         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3693                                 PNV_IODA1_DMA32_SEGSIZE;
3694
3695 #if 0 /* We should really do that ... */
3696         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3697                                          window_type,
3698                                          window_num,
3699                                          starting_real_address,
3700                                          starting_pci_address,
3701                                          segment_size);
3702 #endif
3703
3704         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3705                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3706                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3707         if (phb->ioda.m64_size)
3708                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3709                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3710         if (phb->ioda.io_size)
3711                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3712                         phb->ioda.io_size, phb->ioda.io_segsize);
3713
3714
3715         phb->hose->ops = &pnv_pci_ops;
3716         phb->get_pe_state = pnv_ioda_get_pe_state;
3717         phb->freeze_pe = pnv_ioda_freeze_pe;
3718         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3719
3720         /* Setup MSI support */
3721         pnv_pci_init_ioda_msis(phb);
3722
3723         /*
3724          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3725          * to let the PCI core do resource assignment. It's supposed
3726          * that the PCI core will do correct I/O and MMIO alignment
3727          * for the P2P bridge bars so that each PCI bus (excluding
3728          * the child P2P bridges) can form individual PE.
3729          */
3730         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3731
3732         if (phb->type == PNV_PHB_NPU) {
3733                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3734         } else {
3735                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3736                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3737         }
3738
3739 #ifdef CONFIG_PCI_IOV
3740         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3741         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3742 #endif
3743
3744         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3745
3746         /* Reset IODA tables to a clean state */
3747         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3748         if (rc)
3749                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3750
3751         /* If we're running in kdump kerenl, the previous kerenl never
3752          * shutdown PCI devices correctly. We already got IODA table
3753          * cleaned out. So we have to issue PHB reset to stop all PCI
3754          * transactions from previous kerenl.
3755          */
3756         if (is_kdump_kernel()) {
3757                 pr_info("  Issue PHB reset ...\n");
3758                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3759                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3760         }
3761
3762         /* Remove M64 resource if we can't configure it successfully */
3763         if (!phb->init_m64 || phb->init_m64(phb))
3764                 hose->mem_resources[1].flags = 0;
3765 }
3766
3767 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3768 {
3769         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3770 }
3771
3772 void __init pnv_pci_init_npu_phb(struct device_node *np)
3773 {
3774         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3775 }
3776
3777 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3778 {
3779         struct device_node *phbn;
3780         const __be64 *prop64;
3781         u64 hub_id;
3782
3783         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3784
3785         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3786         if (!prop64) {
3787                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3788                 return;
3789         }
3790         hub_id = be64_to_cpup(prop64);
3791         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3792
3793         /* Count child PHBs */
3794         for_each_child_of_node(np, phbn) {
3795                 /* Look for IODA1 PHBs */
3796                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3797                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3798         }
3799 }