2 * Support PCI/PCIe on PowerNV platforms
4 * Currently supports only P5IOC2
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
22 #include <linux/msi.h>
24 #include <asm/sections.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/msi_bitmap.h>
30 #include <asm/ppc-pci.h>
32 #include <asm/iommu.h>
38 /* For now, use a fixed amount of TCE memory for each p5ioc2
41 #define P5IOC2_TCE_MEMORY 0x01000000
44 static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
45 unsigned int hwirq, unsigned int virq,
46 unsigned int is_64, struct msi_msg *msg)
50 msg->data = hwirq - phb->msi_base;
51 msg->address_hi = 0x10000000;
57 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
60 const __be32 *prop = of_get_property(phb->hose->dn,
61 "ibm,opal-msi-ranges", NULL);
65 /* Don't do MSI's on p5ioc2 PCI-X are they are not properly
68 if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
70 phb->msi_base = be32_to_cpup(prop);
71 count = be32_to_cpup(prop + 1);
72 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
73 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
74 phb->hose->global_number);
77 phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
78 phb->msi32_support = 0;
79 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
80 count, phb->msi_base);
83 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
84 #endif /* CONFIG_PCI_MSI */
86 static struct iommu_table_ops pnv_p5ioc2_iommu_ops = {
88 #ifdef CONFIG_IOMMU_API
89 .exchange = pnv_tce_xchg,
91 .clear = pnv_tce_free,
95 static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
98 struct iommu_table *tbl = phb->p5ioc2.table_group.tables[0];
101 tbl->it_ops = &pnv_p5ioc2_iommu_ops;
102 iommu_init_table(tbl, phb->hose->node);
103 iommu_register_group(&phb->p5ioc2.table_group,
104 pci_domain_nr(phb->hose->bus), phb->opal_id);
105 INIT_LIST_HEAD_RCU(&tbl->it_group_list);
106 pnv_pci_link_table_and_group(phb->hose->node, 0,
107 tbl, &phb->p5ioc2.table_group);
110 set_iommu_table_base(&pdev->dev, tbl);
111 iommu_add_device(&pdev->dev);
114 static const struct pci_controller_ops pnv_pci_p5ioc2_controller_ops = {
115 .dma_dev_setup = pnv_pci_dma_dev_setup,
116 #ifdef CONFIG_PCI_MSI
117 .setup_msi_irqs = pnv_setup_msi_irqs,
118 .teardown_msi_irqs = pnv_teardown_msi_irqs,
122 static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
123 void *tce_mem, u64 tce_size)
126 const __be64 *prop64;
129 static int primary = 1;
131 pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
133 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
135 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
138 phb_id = be64_to_cpup(prop64);
139 pr_devel(" PHB-ID : 0x%016llx\n", phb_id);
140 pr_devel(" TCE AT : 0x%016lx\n", __pa(tce_mem));
141 pr_devel(" TCE SZ : 0x%016llx\n", tce_size);
143 rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size);
144 if (rc != OPAL_SUCCESS) {
145 pr_err(" Failed to set TCE memory, OPAL error %lld\n", rc);
149 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
150 phb->hose = pcibios_alloc_controller(np);
152 pr_err(" Failed to allocate PCI controller\n");
156 spin_lock_init(&phb->lock);
157 phb->hose->first_busno = 0;
158 phb->hose->last_busno = 0xff;
159 phb->hose->private_data = phb;
160 phb->hose->controller_ops = pnv_pci_p5ioc2_controller_ops;
161 phb->hub_id = hub_id;
162 phb->opal_id = phb_id;
163 phb->type = PNV_PHB_P5IOC2;
164 phb->model = PNV_PHB_MODEL_P5IOC2;
166 phb->regs = of_iomap(np, 0);
168 if (phb->regs == NULL)
169 pr_err(" Failed to map registers !\n");
171 pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100));
172 pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0));
173 pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0));
174 pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0));
175 pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190));
176 pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0));
177 pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0));
178 pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0));
179 pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0));
180 pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0));
181 pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0));
184 /* Interpret the "ranges" property */
185 /* This also maps the I/O region and sets isa_io/mem_base */
186 pci_process_bridge_OF_ranges(phb->hose, np, primary);
189 phb->hose->ops = &pnv_pci_ops;
191 /* Setup MSI support */
192 pnv_pci_init_p5ioc2_msis(phb);
195 phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
196 pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
197 tce_mem, tce_size, 0,
198 IOMMU_PAGE_SHIFT_4K);
200 * We do not allocate iommu_table as we do not support
201 * hotplug or SRIOV on P5IOC2 and therefore iommu_free_table()
202 * should not be called for phb->p5ioc2.table_group.tables[0] ever.
204 phb->p5ioc2.table_group.tables[0] = &phb->p5ioc2.iommu_table;
207 void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
209 struct device_node *phbn;
210 const __be64 *prop64;
213 uint64_t tce_per_phb;
217 pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name);
219 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
221 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
224 hub_id = be64_to_cpup(prop64);
225 pr_info(" HUB-ID : 0x%016llx\n", hub_id);
227 /* Count child PHBs and calculate TCE space per PHB */
228 for_each_child_of_node(np, phbn) {
229 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
230 of_device_is_compatible(phbn, "ibm,p5ioc2-pciex"))
234 if (phb_count <= 0) {
235 pr_info(" No PHBs for Hub %s\n", np->full_name);
239 tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count);
240 pr_info(" Allocating %lld MB of TCE memory per PHB\n",
243 /* Currently allocate 16M of TCE memory for every Hub
245 * XXX TODO: Make it chip local if possible
247 tce_mem = memblock_virt_alloc(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY);
248 pr_debug(" TCE : 0x%016lx..0x%016lx\n",
249 __pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1);
250 rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem),
252 if (rc != OPAL_SUCCESS) {
253 pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc);
257 /* Initialize PHBs */
258 for_each_child_of_node(np, phbn) {
259 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
260 of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
261 pnv_pci_init_p5ioc2_phb(phbn, hub_id,
262 tce_mem, tce_per_phb);
263 tce_mem += tce_per_phb;