arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <linux/of.h>
  39 #include <linux/iommu.h>
  40 #include <asm/io.h>
  41 #include <asm/prom.h>
  42 #include <asm/rtas.h>
  43 #include <asm/iommu.h>
  44 #include <asm/pci-bridge.h>
  45 #include <asm/machdep.h>
  46 #include <asm/firmware.h>
  47 #include <asm/tce.h>
  48 #include <asm/ppc-pci.h>
  49 #include <asm/udbg.h>
  50 #include <asm/mmzone.h>
  51 #include <asm/plpar_wrappers.h>
  52
  53 #include "pseries.h"
  54
  55 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
  56 {
  57         struct iommu_table_group *table_group = NULL;
  58         struct iommu_table *tbl = NULL;
  59
  60         table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
  61                            node);
  62         if (!table_group)
  63                 goto fail_exit;
  64
  65         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
  66         if (!tbl)
  67                 goto fail_exit;
  68
  69         tbl->it_table_group = table_group;
  70         table_group->tables[0] = tbl;
  71
  72         return table_group;
  73
  74 fail_exit:
  75         kfree(table_group);
  76         kfree(tbl);
  77
  78         return NULL;
  79 }
  80
  81 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
  82                 const char *node_name)
  83 {
  84         struct iommu_table *tbl;
  85
  86         if (!table_group)
  87                 return;
  88
  89 #ifdef CONFIG_IOMMU_API
  90         if (table_group->group) {
  91                 iommu_group_put(table_group->group);
  92                 BUG_ON(table_group->group);
  93         }
  94 #endif
  95
  96         tbl = table_group->tables[0];
  97         iommu_free_table(tbl, node_name);
  98
  99         kfree(table_group);
 100 }
 101
 102 static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
 103                                       __be64 *startp, __be64 *endp)
 104 {
 105         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 106         unsigned long start, end, inc;
 107
 108         start = __pa(startp);
 109         end = __pa(endp);
 110         inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
 111
 112         /* If this is non-zero, change the format.  We shift the
 113          * address and or in the magic from the device tree. */
 114         if (tbl->it_busno) {
 115                 start <<= 12;
 116                 end <<= 12;
 117                 inc <<= 12;
 118                 start |= tbl->it_busno;
 119                 end |= tbl->it_busno;
 120         }
 121
 122         end |= inc - 1; /* round up end to be different than start */
 123
 124         mb(); /* Make sure TCEs in memory are written */
 125         while (start <= end) {
 126                 out_be64(invalidate, start);
 127                 start += inc;
 128         }
 129 }
 130
 131 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 132                               long npages, unsigned long uaddr,
 133                               enum dma_data_direction direction,
 134                               struct dma_attrs *attrs)
 135 {
 136         u64 proto_tce;
 137         __be64 *tcep, *tces;
 138         u64 rpn;
 139
 140         proto_tce = TCE_PCI_READ; // Read allowed
 141
 142         if (direction != DMA_TO_DEVICE)
 143                 proto_tce |= TCE_PCI_WRITE;
 144
 145         tces = tcep = ((__be64 *)tbl->it_base) + index;
 146
 147         while (npages--) {
 148                 /* can't move this out since we might cross MEMBLOCK boundary */
 149                 rpn = __pa(uaddr) >> TCE_SHIFT;
 150                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 151
 152                 uaddr += TCE_PAGE_SIZE;
 153                 tcep++;
 154         }
 155
 156         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 157                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 158         return 0;
 159 }
 160
 161
 162 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 163 {
 164         __be64 *tcep, *tces;
 165
 166         tces = tcep = ((__be64 *)tbl->it_base) + index;
 167
 168         while (npages--)
 169                 *(tcep++) = 0;
 170
 171         if (tbl->it_type & TCE_PCI_SWINV_FREE)
 172                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 173 }
 174
 175 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 176 {
 177         __be64 *tcep;
 178
 179         tcep = ((__be64 *)tbl->it_base) + index;
 180
 181         return be64_to_cpu(*tcep);
 182 }
 183
 184 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
 185 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 186
 187 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
 188                                 long npages, unsigned long uaddr,
 189                                 enum dma_data_direction direction,
 190                                 struct dma_attrs *attrs)
 191 {
 192         u64 rc = 0;
 193         u64 proto_tce, tce;
 194         u64 rpn;
 195         int ret = 0;
 196         long tcenum_start = tcenum, npages_start = npages;
 197
 198         rpn = __pa(uaddr) >> TCE_SHIFT;
 199         proto_tce = TCE_PCI_READ;
 200         if (direction != DMA_TO_DEVICE)
 201                 proto_tce |= TCE_PCI_WRITE;
 202
 203         while (npages--) {
 204                 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
 205                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
 206
 207                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 208                         ret = (int)rc;
 209                         tce_free_pSeriesLP(tbl, tcenum_start,
 210                                            (npages_start - (npages + 1)));
 211                         break;
 212                 }
 213
 214                 if (rc && printk_ratelimit()) {
 215                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 216                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 217                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 218                         printk("\ttce val = 0x%llx\n", tce );
 219                         dump_stack();
 220                 }
 221
 222                 tcenum++;
 223                 rpn++;
 224         }
 225         return ret;
 226 }
 227
 228 static DEFINE_PER_CPU(__be64 *, tce_page);
 229
 230 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 231                                      long npages, unsigned long uaddr,
 232                                      enum dma_data_direction direction,
 233                                      struct dma_attrs *attrs)
 234 {
 235         u64 rc = 0;
 236         u64 proto_tce;
 237         __be64 *tcep;
 238         u64 rpn;
 239         long l, limit;
 240         long tcenum_start = tcenum, npages_start = npages;
 241         int ret = 0;
 242         unsigned long flags;
 243
 244         if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
 245                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 246                                            direction, attrs);
 247         }
 248
 249         local_irq_save(flags);  /* to protect tcep and the page behind it */
 250
 251         tcep = __this_cpu_read(tce_page);
 252
 253         /* This is safe to do since interrupts are off when we're called
 254          * from iommu_alloc{,_sg}()
 255          */
 256         if (!tcep) {
 257                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 258                 /* If allocation fails, fall back to the loop implementation */
 259                 if (!tcep) {
 260                         local_irq_restore(flags);
 261                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
 262                                             direction, attrs);
 263                 }
 264                 __this_cpu_write(tce_page, tcep);
 265         }
 266
 267         rpn = __pa(uaddr) >> TCE_SHIFT;
 268         proto_tce = TCE_PCI_READ;
 269         if (direction != DMA_TO_DEVICE)
 270                 proto_tce |= TCE_PCI_WRITE;
 271
 272         /* We can map max one pageful of TCEs at a time */
 273         do {
 274                 /*
 275                  * Set up the page with TCE data, looping through and setting
 276                  * the values.
 277                  */
 278                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 279
 280                 for (l = 0; l < limit; l++) {
 281                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 282                         rpn++;
 283                 }
 284
 285                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 286                                             (u64)tcenum << 12,
 287                                             (u64)__pa(tcep),
 288                                             limit);
 289
 290                 npages -= limit;
 291                 tcenum += limit;
 292         } while (npages > 0 && !rc);
 293
 294         local_irq_restore(flags);
 295
 296         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 297                 ret = (int)rc;
 298                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 299                                         (npages_start - (npages + limit)));
 300                 return ret;
 301         }
 302
 303         if (rc && printk_ratelimit()) {
 304                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 305                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 306                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 307                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 308                 dump_stack();
 309         }
 310         return ret;
 311 }
 312
 313 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 314 {
 315         u64 rc;
 316
 317         while (npages--) {
 318                 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
 319
 320                 if (rc && printk_ratelimit()) {
 321                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 322                         printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 323                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 324                         dump_stack();
 325                 }
 326
 327                 tcenum++;
 328         }
 329 }
 330
 331
 332 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 333 {
 334         u64 rc;
 335
 336         if (!firmware_has_feature(FW_FEATURE_MULTITCE))
 337                 return tce_free_pSeriesLP(tbl, tcenum, npages);
 338
 339         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 340
 341         if (rc && printk_ratelimit()) {
 342                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 343                 printk("\trc      = %lld\n", rc);
 344                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 345                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 346                 dump_stack();
 347         }
 348 }
 349
 350 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 351 {
 352         u64 rc;
 353         unsigned long tce_ret;
 354
 355         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 356
 357         if (rc && printk_ratelimit()) {
 358                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 359                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 360                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 361                 dump_stack();
 362         }
 363
 364         return tce_ret;
 365 }
 366
 367 /* this is compatible with cells for the device tree property */
 368 struct dynamic_dma_window_prop {
 369         __be32  liobn;          /* tce table number */
 370         __be64  dma_base;       /* address hi,lo */
 371         __be32  tce_shift;      /* ilog2(tce_page_size) */
 372         __be32  window_shift;   /* ilog2(tce_window_size) */
 373 };
 374
 375 struct direct_window {
 376         struct device_node *device;
 377         const struct dynamic_dma_window_prop *prop;
 378         struct list_head list;
 379 };
 380
 381 /* Dynamic DMA Window support */
 382 struct ddw_query_response {
 383         u32 windows_available;
 384         u32 largest_available_block;
 385         u32 page_size;
 386         u32 migration_capable;
 387 };
 388
 389 struct ddw_create_response {
 390         u32 liobn;
 391         u32 addr_hi;
 392         u32 addr_lo;
 393 };
 394
 395 static LIST_HEAD(direct_window_list);
 396 /* prevents races between memory on/offline and window creation */
 397 static DEFINE_SPINLOCK(direct_window_list_lock);
 398 /* protects initializing window twice for same device */
 399 static DEFINE_MUTEX(direct_window_init_mutex);
 400 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 401
 402 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 403                                         unsigned long num_pfn, const void *arg)
 404 {
 405         const struct dynamic_dma_window_prop *maprange = arg;
 406         int rc;
 407         u64 tce_size, num_tce, dma_offset, next;
 408         u32 tce_shift;
 409         long limit;
 410
 411         tce_shift = be32_to_cpu(maprange->tce_shift);
 412         tce_size = 1ULL << tce_shift;
 413         next = start_pfn << PAGE_SHIFT;
 414         num_tce = num_pfn << PAGE_SHIFT;
 415
 416         /* round back to the beginning of the tce page size */
 417         num_tce += next & (tce_size - 1);
 418         next &= ~(tce_size - 1);
 419
 420         /* covert to number of tces */
 421         num_tce |= tce_size - 1;
 422         num_tce >>= tce_shift;
 423
 424         do {
 425                 /*
 426                  * Set up the page with TCE data, looping through and setting
 427                  * the values.
 428                  */
 429                 limit = min_t(long, num_tce, 512);
 430                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 431
 432                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 433                                              dma_offset,
 434                                              0, limit);
 435                 next += limit * tce_size;
 436                 num_tce -= limit;
 437         } while (num_tce > 0 && !rc);
 438
 439         return rc;
 440 }
 441
 442 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 443                                         unsigned long num_pfn, const void *arg)
 444 {
 445         const struct dynamic_dma_window_prop *maprange = arg;
 446         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 447         __be64 *tcep;
 448         u32 tce_shift;
 449         u64 rc = 0;
 450         long l, limit;
 451
 452         local_irq_disable();    /* to protect tcep and the page behind it */
 453         tcep = __this_cpu_read(tce_page);
 454
 455         if (!tcep) {
 456                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 457                 if (!tcep) {
 458                         local_irq_enable();
 459                         return -ENOMEM;
 460                 }
 461                 __this_cpu_write(tce_page, tcep);
 462         }
 463
 464         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 465
 466         liobn = (u64)be32_to_cpu(maprange->liobn);
 467         tce_shift = be32_to_cpu(maprange->tce_shift);
 468         tce_size = 1ULL << tce_shift;
 469         next = start_pfn << PAGE_SHIFT;
 470         num_tce = num_pfn << PAGE_SHIFT;
 471
 472         /* round back to the beginning of the tce page size */
 473         num_tce += next & (tce_size - 1);
 474         next &= ~(tce_size - 1);
 475
 476         /* covert to number of tces */
 477         num_tce |= tce_size - 1;
 478         num_tce >>= tce_shift;
 479
 480         /* We can map max one pageful of TCEs at a time */
 481         do {
 482                 /*
 483                  * Set up the page with TCE data, looping through and setting
 484                  * the values.
 485                  */
 486                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 487                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 488
 489                 for (l = 0; l < limit; l++) {
 490                         tcep[l] = cpu_to_be64(proto_tce | next);
 491                         next += tce_size;
 492                 }
 493
 494                 rc = plpar_tce_put_indirect(liobn,
 495                                             dma_offset,
 496                                             (u64)__pa(tcep),
 497                                             limit);
 498
 499                 num_tce -= limit;
 500         } while (num_tce > 0 && !rc);
 501
 502         /* error cleanup: caller will clear whole range */
 503
 504         local_irq_enable();
 505         return rc;
 506 }
 507
 508 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 509                 unsigned long num_pfn, void *arg)
 510 {
 511         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 512 }
 513
 514 #ifdef CONFIG_PCI
 515 static void iommu_table_setparms(struct pci_controller *phb,
 516                                  struct device_node *dn,
 517                                  struct iommu_table *tbl)
 518 {
 519         struct device_node *node;
 520         const unsigned long *basep, *sw_inval;
 521         const u32 *sizep;
 522
 523         node = phb->dn;
 524
 525         basep = of_get_property(node, "linux,tce-base", NULL);
 526         sizep = of_get_property(node, "linux,tce-size", NULL);
 527         if (basep == NULL || sizep == NULL) {
 528                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 529                                 "missing tce entries !\n", dn->full_name);
 530                 return;
 531         }
 532
 533         tbl->it_base = (unsigned long)__va(*basep);
 534
 535         if (!is_kdump_kernel())
 536                 memset((void *)tbl->it_base, 0, *sizep);
 537
 538         tbl->it_busno = phb->bus->number;
 539         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 540
 541         /* Units of tce entries */
 542         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 543
 544         /* Test if we are going over 2GB of DMA space */
 545         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 546                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 547                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 548         }
 549
 550         phb->dma_window_base_cur += phb->dma_window_size;
 551
 552         /* Set the tce table size - measured in entries */
 553         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 554
 555         tbl->it_index = 0;
 556         tbl->it_blocksize = 16;
 557         tbl->it_type = TCE_PCI;
 558
 559         sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
 560         if (sw_inval) {
 561                 /*
 562                  * This property contains information on how to
 563                  * invalidate the TCE entry.  The first property is
 564                  * the base MMIO address used to invalidate entries.
 565                  * The second property tells us the format of the TCE
 566                  * invalidate (whether it needs to be shifted) and
 567                  * some magic routing info to add to our invalidate
 568                  * command.
 569                  */
 570                 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
 571                 tbl->it_busno = sw_inval[1]; /* overload this with magic */
 572                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 573         }
 574 }
 575
 576 /*
 577  * iommu_table_setparms_lpar
 578  *
 579  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 580  */
 581 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 582                                       struct device_node *dn,
 583                                       struct iommu_table *tbl,
 584                                       const __be32 *dma_window)
 585 {
 586         unsigned long offset, size;
 587
 588         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 589
 590         tbl->it_busno = phb->bus->number;
 591         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 592         tbl->it_base   = 0;
 593         tbl->it_blocksize  = 16;
 594         tbl->it_type = TCE_PCI;
 595         tbl->it_offset = offset >> tbl->it_page_shift;
 596         tbl->it_size = size >> tbl->it_page_shift;
 597 }
 598
 599 struct iommu_table_ops iommu_table_pseries_ops = {
 600         .set = tce_build_pSeries,
 601         .clear = tce_free_pSeries,
 602         .get = tce_get_pseries
 603 };
 604
 605 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 606 {
 607         struct device_node *dn;
 608         struct iommu_table *tbl;
 609         struct device_node *isa_dn, *isa_dn_orig;
 610         struct device_node *tmp;
 611         struct pci_dn *pci;
 612         int children;
 613
 614         dn = pci_bus_to_OF_node(bus);
 615
 616         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 617
 618         if (bus->self) {
 619                 /* This is not a root bus, any setup will be done for the
 620                  * device-side of the bridge in iommu_dev_setup_pSeries().
 621                  */
 622                 return;
 623         }
 624         pci = PCI_DN(dn);
 625
 626         /* Check if the ISA bus on the system is under
 627          * this PHB.
 628          */
 629         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 630
 631         while (isa_dn && isa_dn != dn)
 632                 isa_dn = isa_dn->parent;
 633
 634         of_node_put(isa_dn_orig);
 635
 636         /* Count number of direct PCI children of the PHB. */
 637         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 638                 children++;
 639
 640         pr_debug("Children: %d\n", children);
 641
 642         /* Calculate amount of DMA window per slot. Each window must be
 643          * a power of two (due to pci_alloc_consistent requirements).
 644          *
 645          * Keep 256MB aside for PHBs with ISA.
 646          */
 647
 648         if (!isa_dn) {
 649                 /* No ISA/IDE - just set window size and return */
 650                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 651
 652                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 653                         pci->phb->dma_window_size >>= 1;
 654                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 655                          pci->phb->dma_window_size);
 656                 pci->phb->dma_window_base_cur = 0;
 657
 658                 return;
 659         }
 660
 661         /* If we have ISA, then we probably have an IDE
 662          * controller too. Allocate a 128MB table but
 663          * skip the first 128MB to avoid stepping on ISA
 664          * space.
 665          */
 666         pci->phb->dma_window_size = 0x8000000ul;
 667         pci->phb->dma_window_base_cur = 0x8000000ul;
 668
 669         pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
 670         tbl = pci->table_group->tables[0];
 671
 672         iommu_table_setparms(pci->phb, dn, tbl);
 673         tbl->it_ops = &iommu_table_pseries_ops;
 674         iommu_init_table(tbl, pci->phb->node);
 675         iommu_register_group(pci->table_group, pci_domain_nr(bus), 0);
 676
 677         /* Divide the rest (1.75GB) among the children */
 678         pci->phb->dma_window_size = 0x80000000ul;
 679         while (pci->phb->dma_window_size * children > 0x70000000ul)
 680                 pci->phb->dma_window_size >>= 1;
 681
 682         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 683 }
 684
 685 struct iommu_table_ops iommu_table_lpar_multi_ops = {
 686         .set = tce_buildmulti_pSeriesLP,
 687         .clear = tce_freemulti_pSeriesLP,
 688         .get = tce_get_pSeriesLP
 689 };
 690
 691 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 692 {
 693         struct iommu_table *tbl;
 694         struct device_node *dn, *pdn;
 695         struct pci_dn *ppci;
 696         const __be32 *dma_window = NULL;
 697
 698         dn = pci_bus_to_OF_node(bus);
 699
 700         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 701                  dn->full_name);
 702
 703         /* Find nearest ibm,dma-window, walking up the device tree */
 704         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 705                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 706                 if (dma_window != NULL)
 707                         break;
 708         }
 709
 710         if (dma_window == NULL) {
 711                 pr_debug("  no ibm,dma-window property !\n");
 712                 return;
 713         }
 714
 715         ppci = PCI_DN(pdn);
 716
 717         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 718                  pdn->full_name, ppci->table_group);
 719
 720         if (!ppci->table_group) {
 721                 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
 722                 tbl = ppci->table_group->tables[0];
 723                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 724                 tbl->it_ops = &iommu_table_lpar_multi_ops;
 725                 iommu_init_table(tbl, ppci->phb->node);
 726                 iommu_register_group(ppci->table_group,
 727                                 pci_domain_nr(bus), 0);
 728                 pr_debug("  created table: %p\n", ppci->table_group);
 729         }
 730 }
 731
 732
 733 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 734 {
 735         struct device_node *dn;
 736         struct iommu_table *tbl;
 737
 738         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 739
 740         dn = dev->dev.of_node;
 741
 742         /* If we're the direct child of a root bus, then we need to allocate
 743          * an iommu table ourselves. The bus setup code should have setup
 744          * the window sizes already.
 745          */
 746         if (!dev->bus->self) {
 747                 struct pci_controller *phb = PCI_DN(dn)->phb;
 748
 749                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 750                 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
 751                 tbl = PCI_DN(dn)->table_group->tables[0];
 752                 iommu_table_setparms(phb, dn, tbl);
 753                 tbl->it_ops = &iommu_table_pseries_ops;
 754                 iommu_init_table(tbl, phb->node);
 755                 iommu_register_group(PCI_DN(dn)->table_group,
 756                                 pci_domain_nr(phb->bus), 0);
 757                 set_iommu_table_base(&dev->dev, tbl);
 758                 iommu_add_device(&dev->dev);
 759                 return;
 760         }
 761
 762         /* If this device is further down the bus tree, search upwards until
 763          * an already allocated iommu table is found and use that.
 764          */
 765
 766         while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
 767                 dn = dn->parent;
 768
 769         if (dn && PCI_DN(dn)) {
 770                 set_iommu_table_base(&dev->dev,
 771                                 PCI_DN(dn)->table_group->tables[0]);
 772                 iommu_add_device(&dev->dev);
 773         } else
 774                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 775                        pci_name(dev));
 776 }
 777
 778 static int __read_mostly disable_ddw;
 779
 780 static int __init disable_ddw_setup(char *str)
 781 {
 782         disable_ddw = 1;
 783         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 784
 785         return 0;
 786 }
 787
 788 early_param("disable_ddw", disable_ddw_setup);
 789
 790 static void remove_ddw(struct device_node *np, bool remove_prop)
 791 {
 792         struct dynamic_dma_window_prop *dwp;
 793         struct property *win64;
 794         u32 ddw_avail[3];
 795         u64 liobn;
 796         int ret = 0;
 797
 798         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 799                                          &ddw_avail[0], 3);
 800
 801         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 802         if (!win64)
 803                 return;
 804
 805         if (ret || win64->length < sizeof(*dwp))
 806                 goto delprop;
 807
 808         dwp = win64->value;
 809         liobn = (u64)be32_to_cpu(dwp->liobn);
 810
 811         /* clear the whole window, note the arg is in kernel pages */
 812         ret = tce_clearrange_multi_pSeriesLP(0,
 813                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 814         if (ret)
 815                 pr_warning("%s failed to clear tces in window.\n",
 816                          np->full_name);
 817         else
 818                 pr_debug("%s successfully cleared tces in window.\n",
 819                          np->full_name);
 820
 821         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 822         if (ret)
 823                 pr_warning("%s: failed to remove direct window: rtas returned "
 824                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 825                         np->full_name, ret, ddw_avail[2], liobn);
 826         else
 827                 pr_debug("%s: successfully removed direct window: rtas returned "
 828                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 829                         np->full_name, ret, ddw_avail[2], liobn);
 830
 831 delprop:
 832         if (remove_prop)
 833                 ret = of_remove_property(np, win64);
 834         if (ret)
 835                 pr_warning("%s: failed to remove direct window property: %d\n",
 836                         np->full_name, ret);
 837 }
 838
 839 static u64 find_existing_ddw(struct device_node *pdn)
 840 {
 841         struct direct_window *window;
 842         const struct dynamic_dma_window_prop *direct64;
 843         u64 dma_addr = 0;
 844
 845         spin_lock(&direct_window_list_lock);
 846         /* check if we already created a window and dupe that config if so */
 847         list_for_each_entry(window, &direct_window_list, list) {
 848                 if (window->device == pdn) {
 849                         direct64 = window->prop;
 850                         dma_addr = be64_to_cpu(direct64->dma_base);
 851                         break;
 852                 }
 853         }
 854         spin_unlock(&direct_window_list_lock);
 855
 856         return dma_addr;
 857 }
 858
 859 static int find_existing_ddw_windows(void)
 860 {
 861         int len;
 862         struct device_node *pdn;
 863         struct direct_window *window;
 864         const struct dynamic_dma_window_prop *direct64;
 865
 866         if (!firmware_has_feature(FW_FEATURE_LPAR))
 867                 return 0;
 868
 869         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 870                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 871                 if (!direct64)
 872                         continue;
 873
 874                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 875                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 876                         kfree(window);
 877                         remove_ddw(pdn, true);
 878                         continue;
 879                 }
 880
 881                 window->device = pdn;
 882                 window->prop = direct64;
 883                 spin_lock(&direct_window_list_lock);
 884                 list_add(&window->list, &direct_window_list);
 885                 spin_unlock(&direct_window_list_lock);
 886         }
 887
 888         return 0;
 889 }
 890 machine_arch_initcall(pseries, find_existing_ddw_windows);
 891
 892 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 893                         struct ddw_query_response *query)
 894 {
 895         struct eeh_dev *edev;
 896         u32 cfg_addr;
 897         u64 buid;
 898         int ret;
 899
 900         /*
 901          * Get the config address and phb buid of the PE window.
 902          * Rely on eeh to retrieve this for us.
 903          * Retrieve them from the pci device, not the node with the
 904          * dma-window property
 905          */
 906         edev = pci_dev_to_eeh_dev(dev);
 907         cfg_addr = edev->config_addr;
 908         if (edev->pe_config_addr)
 909                 cfg_addr = edev->pe_config_addr;
 910         buid = edev->phb->buid;
 911
 912         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 913                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 914         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 915                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 916                 BUID_LO(buid), ret);
 917         return ret;
 918 }
 919
 920 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 921                         struct ddw_create_response *create, int page_shift,
 922                         int window_shift)
 923 {
 924         struct eeh_dev *edev;
 925         u32 cfg_addr;
 926         u64 buid;
 927         int ret;
 928
 929         /*
 930          * Get the config address and phb buid of the PE window.
 931          * Rely on eeh to retrieve this for us.
 932          * Retrieve them from the pci device, not the node with the
 933          * dma-window property
 934          */
 935         edev = pci_dev_to_eeh_dev(dev);
 936         cfg_addr = edev->config_addr;
 937         if (edev->pe_config_addr)
 938                 cfg_addr = edev->pe_config_addr;
 939         buid = edev->phb->buid;
 940
 941         do {
 942                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 943                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 944                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 945                                 page_shift, window_shift);
 946         } while (rtas_busy_delay(ret));
 947         dev_info(&dev->dev,
 948                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 949                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 950                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 951                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 952
 953         return ret;
 954 }
 955
 956 struct failed_ddw_pdn {
 957         struct device_node *pdn;
 958         struct list_head list;
 959 };
 960
 961 static LIST_HEAD(failed_ddw_pdn_list);
 962
 963 /*
 964  * If the PE supports dynamic dma windows, and there is space for a table
 965  * that can map all pages in a linear offset, then setup such a table,
 966  * and record the dma-offset in the struct device.
 967  *
 968  * dev: the pci device we are checking
 969  * pdn: the parent pe node with the ibm,dma_window property
 970  * Future: also check if we can remap the base window for our base page size
 971  *
 972  * returns the dma offset for use by dma_set_mask
 973  */
 974 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 975 {
 976         int len, ret;
 977         struct ddw_query_response query;
 978         struct ddw_create_response create;
 979         int page_shift;
 980         u64 dma_addr, max_addr;
 981         struct device_node *dn;
 982         u32 ddw_avail[3];
 983         struct direct_window *window;
 984         struct property *win64;
 985         struct dynamic_dma_window_prop *ddwprop;
 986         struct failed_ddw_pdn *fpdn;
 987
 988         mutex_lock(&direct_window_init_mutex);
 989
 990         dma_addr = find_existing_ddw(pdn);
 991         if (dma_addr != 0)
 992                 goto out_unlock;
 993
 994         /*
 995          * If we already went through this for a previous function of
 996          * the same device and failed, we don't want to muck with the
 997          * DMA window again, as it will race with in-flight operations
 998          * and can lead to EEHs. The above mutex protects access to the
 999          * list.
1000          */
1001         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
1002                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
1003                         goto out_unlock;
1004         }
1005
1006         /*
1007          * the ibm,ddw-applicable property holds the tokens for:
1008          * ibm,query-pe-dma-window
1009          * ibm,create-pe-dma-window
1010          * ibm,remove-pe-dma-window
1011          * for the given node in that order.
1012          * the property is actually in the parent, not the PE
1013          */
1014         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
1015                                          &ddw_avail[0], 3);
1016         if (ret)
1017                 goto out_failed;
1018
1019        /*
1020          * Query if there is a second window of size to map the
1021          * whole partition.  Query returns number of windows, largest
1022          * block assigned to PE (partition endpoint), and two bitmasks
1023          * of page sizes: supported and supported for migrate-dma.
1024          */
1025         dn = pci_device_to_OF_node(dev);
1026         ret = query_ddw(dev, ddw_avail, &query);
1027         if (ret != 0)
1028                 goto out_failed;
1029
1030         if (query.windows_available == 0) {
1031                 /*
1032                  * no additional windows are available for this device.
1033                  * We might be able to reallocate the existing window,
1034                  * trading in for a larger page size.
1035                  */
1036                 dev_dbg(&dev->dev, "no free dynamic windows");
1037                 goto out_failed;
1038         }
1039         if (query.page_size & 4) {
1040                 page_shift = 24; /* 16MB */
1041         } else if (query.page_size & 2) {
1042                 page_shift = 16; /* 64kB */
1043         } else if (query.page_size & 1) {
1044                 page_shift = 12; /* 4kB */
1045         } else {
1046                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1047                           query.page_size);
1048                 goto out_failed;
1049         }
1050         /* verify the window * number of ptes will map the partition */
1051         /* check largest block * page size > max memory hotplug addr */
1052         max_addr = memory_hotplug_max();
1053         if (query.largest_available_block < (max_addr >> page_shift)) {
1054                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1055                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1056                           1ULL << page_shift);
1057                 goto out_failed;
1058         }
1059         len = order_base_2(max_addr);
1060         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1061         if (!win64) {
1062                 dev_info(&dev->dev,
1063                         "couldn't allocate property for 64bit dma window\n");
1064                 goto out_failed;
1065         }
1066         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1067         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1068         win64->length = sizeof(*ddwprop);
1069         if (!win64->name || !win64->value) {
1070                 dev_info(&dev->dev,
1071                         "couldn't allocate property name and value\n");
1072                 goto out_free_prop;
1073         }
1074
1075         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1076         if (ret != 0)
1077                 goto out_free_prop;
1078
1079         ddwprop->liobn = cpu_to_be32(create.liobn);
1080         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1081                         create.addr_lo);
1082         ddwprop->tce_shift = cpu_to_be32(page_shift);
1083         ddwprop->window_shift = cpu_to_be32(len);
1084
1085         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1086                   create.liobn, dn->full_name);
1087
1088         window = kzalloc(sizeof(*window), GFP_KERNEL);
1089         if (!window)
1090                 goto out_clear_window;
1091
1092         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1093                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1094         if (ret) {
1095                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1096                          dn->full_name, ret);
1097                 goto out_free_window;
1098         }
1099
1100         ret = of_add_property(pdn, win64);
1101         if (ret) {
1102                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1103                          pdn->full_name, ret);
1104                 goto out_free_window;
1105         }
1106
1107         window->device = pdn;
1108         window->prop = ddwprop;
1109         spin_lock(&direct_window_list_lock);
1110         list_add(&window->list, &direct_window_list);
1111         spin_unlock(&direct_window_list_lock);
1112
1113         dma_addr = be64_to_cpu(ddwprop->dma_base);
1114         goto out_unlock;
1115
1116 out_free_window:
1117         kfree(window);
1118
1119 out_clear_window:
1120         remove_ddw(pdn, true);
1121
1122 out_free_prop:
1123         kfree(win64->name);
1124         kfree(win64->value);
1125         kfree(win64);
1126
1127 out_failed:
1128
1129         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1130         if (!fpdn)
1131                 goto out_unlock;
1132         fpdn->pdn = pdn;
1133         list_add(&fpdn->list, &failed_ddw_pdn_list);
1134
1135 out_unlock:
1136         mutex_unlock(&direct_window_init_mutex);
1137         return dma_addr;
1138 }
1139
1140 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1141 {
1142         struct device_node *pdn, *dn;
1143         struct iommu_table *tbl;
1144         const __be32 *dma_window = NULL;
1145         struct pci_dn *pci;
1146
1147         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1148
1149         /* dev setup for LPAR is a little tricky, since the device tree might
1150          * contain the dma-window properties per-device and not necessarily
1151          * for the bus. So we need to search upwards in the tree until we
1152          * either hit a dma-window property, OR find a parent with a table
1153          * already allocated.
1154          */
1155         dn = pci_device_to_OF_node(dev);
1156         pr_debug("  node is %s\n", dn->full_name);
1157
1158         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1159              pdn = pdn->parent) {
1160                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1161                 if (dma_window)
1162                         break;
1163         }
1164
1165         if (!pdn || !PCI_DN(pdn)) {
1166                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1167                        "no DMA window found for pci dev=%s dn=%s\n",
1168                                  pci_name(dev), of_node_full_name(dn));
1169                 return;
1170         }
1171         pr_debug("  parent is %s\n", pdn->full_name);
1172
1173         pci = PCI_DN(pdn);
1174         if (!pci->table_group) {
1175                 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1176                 tbl = pci->table_group->tables[0];
1177                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1178                 tbl->it_ops = &iommu_table_lpar_multi_ops;
1179                 iommu_init_table(tbl, pci->phb->node);
1180                 iommu_register_group(pci->table_group,
1181                                 pci_domain_nr(pci->phb->bus), 0);
1182                 pr_debug("  created table: %p\n", pci->table_group);
1183         } else {
1184                 pr_debug("  found DMA window, table: %p\n", pci->table_group);
1185         }
1186
1187         set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1188         iommu_add_device(&dev->dev);
1189 }
1190
1191 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1192 {
1193         bool ddw_enabled = false;
1194         struct device_node *pdn, *dn;
1195         struct pci_dev *pdev;
1196         const __be32 *dma_window = NULL;
1197         u64 dma_offset;
1198
1199         if (!dev->dma_mask)
1200                 return -EIO;
1201
1202         if (!dev_is_pci(dev))
1203                 goto check_mask;
1204
1205         pdev = to_pci_dev(dev);
1206
1207         /* only attempt to use a new window if 64-bit DMA is requested */
1208         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1209                 dn = pci_device_to_OF_node(pdev);
1210                 dev_dbg(dev, "node is %s\n", dn->full_name);
1211
1212                 /*
1213                  * the device tree might contain the dma-window properties
1214                  * per-device and not necessarily for the bus. So we need to
1215                  * search upwards in the tree until we either hit a dma-window
1216                  * property, OR find a parent with a table already allocated.
1217                  */
1218                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1219                                 pdn = pdn->parent) {
1220                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1221                         if (dma_window)
1222                                 break;
1223                 }
1224                 if (pdn && PCI_DN(pdn)) {
1225                         dma_offset = enable_ddw(pdev, pdn);
1226                         if (dma_offset != 0) {
1227                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1228                                 set_dma_offset(dev, dma_offset);
1229                                 set_dma_ops(dev, &dma_direct_ops);
1230                                 ddw_enabled = true;
1231                         }
1232                 }
1233         }
1234
1235         /* fall back on iommu ops, restore table pointer with ops */
1236         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1237                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1238                 set_dma_ops(dev, &dma_iommu_ops);
1239                 pci_dma_dev_setup_pSeriesLP(pdev);
1240         }
1241
1242 check_mask:
1243         if (!dma_supported(dev, dma_mask))
1244                 return -EIO;
1245
1246         *dev->dma_mask = dma_mask;
1247         return 0;
1248 }
1249
1250 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1251 {
1252         if (!dev->dma_mask)
1253                 return 0;
1254
1255         if (!disable_ddw && dev_is_pci(dev)) {
1256                 struct pci_dev *pdev = to_pci_dev(dev);
1257                 struct device_node *dn;
1258
1259                 dn = pci_device_to_OF_node(pdev);
1260
1261                 /* search upwards for ibm,dma-window */
1262                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group;
1263                                 dn = dn->parent)
1264                         if (of_get_property(dn, "ibm,dma-window", NULL))
1265                                 break;
1266                 /* if there is a ibm,ddw-applicable property require 64 bits */
1267                 if (dn && PCI_DN(dn) &&
1268                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1269                         return DMA_BIT_MASK(64);
1270         }
1271
1272         return dma_iommu_ops.get_required_mask(dev);
1273 }
1274
1275 #else  /* CONFIG_PCI */
1276 #define pci_dma_bus_setup_pSeries       NULL
1277 #define pci_dma_dev_setup_pSeries       NULL
1278 #define pci_dma_bus_setup_pSeriesLP     NULL
1279 #define pci_dma_dev_setup_pSeriesLP     NULL
1280 #define dma_set_mask_pSeriesLP          NULL
1281 #define dma_get_required_mask_pSeriesLP NULL
1282 #endif /* !CONFIG_PCI */
1283
1284 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1285                 void *data)
1286 {
1287         struct direct_window *window;
1288         struct memory_notify *arg = data;
1289         int ret = 0;
1290
1291         switch (action) {
1292         case MEM_GOING_ONLINE:
1293                 spin_lock(&direct_window_list_lock);
1294                 list_for_each_entry(window, &direct_window_list, list) {
1295                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1296                                         arg->nr_pages, window->prop);
1297                         /* XXX log error */
1298                 }
1299                 spin_unlock(&direct_window_list_lock);
1300                 break;
1301         case MEM_CANCEL_ONLINE:
1302         case MEM_OFFLINE:
1303                 spin_lock(&direct_window_list_lock);
1304                 list_for_each_entry(window, &direct_window_list, list) {
1305                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1306                                         arg->nr_pages, window->prop);
1307                         /* XXX log error */
1308                 }
1309                 spin_unlock(&direct_window_list_lock);
1310                 break;
1311         default:
1312                 break;
1313         }
1314         if (ret && action != MEM_CANCEL_ONLINE)
1315                 return NOTIFY_BAD;
1316
1317         return NOTIFY_OK;
1318 }
1319
1320 static struct notifier_block iommu_mem_nb = {
1321         .notifier_call = iommu_mem_notifier,
1322 };
1323
1324 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1325 {
1326         int err = NOTIFY_OK;
1327         struct of_reconfig_data *rd = data;
1328         struct device_node *np = rd->dn;
1329         struct pci_dn *pci = PCI_DN(np);
1330         struct direct_window *window;
1331
1332         switch (action) {
1333         case OF_RECONFIG_DETACH_NODE:
1334                 /*
1335                  * Removing the property will invoke the reconfig
1336                  * notifier again, which causes dead-lock on the
1337                  * read-write semaphore of the notifier chain. So
1338                  * we have to remove the property when releasing
1339                  * the device node.
1340                  */
1341                 remove_ddw(np, false);
1342                 if (pci && pci->table_group)
1343                         iommu_pseries_free_group(pci->table_group,
1344                                         np->full_name);
1345
1346                 spin_lock(&direct_window_list_lock);
1347                 list_for_each_entry(window, &direct_window_list, list) {
1348                         if (window->device == np) {
1349                                 list_del(&window->list);
1350                                 kfree(window);
1351                                 break;
1352                         }
1353                 }
1354                 spin_unlock(&direct_window_list_lock);
1355                 break;
1356         default:
1357                 err = NOTIFY_DONE;
1358                 break;
1359         }
1360         return err;
1361 }
1362
1363 static struct notifier_block iommu_reconfig_nb = {
1364         .notifier_call = iommu_reconfig_notifier,
1365 };
1366
1367 /* These are called very early. */
1368 void iommu_init_early_pSeries(void)
1369 {
1370         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1371                 return;
1372
1373         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1374                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1375                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1376                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1377                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1378         } else {
1379                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1380                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1381         }
1382
1383
1384         of_reconfig_notifier_register(&iommu_reconfig_nb);
1385         register_memory_notifier(&iommu_mem_nb);
1386
1387         set_pci_dma_ops(&dma_iommu_ops);
1388 }
1389
1390 static int __init disable_multitce(char *str)
1391 {
1392         if (strcmp(str, "off") == 0 &&
1393             firmware_has_feature(FW_FEATURE_LPAR) &&
1394             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1395                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1396                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1397         }
1398         return 1;
1399 }
1400
1401 __setup("multitce=", disable_multitce);
1402
1403 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);