arch/ppc64/kernel/cputable.c

   1 /*
   2  *  arch/ppc64/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/threads.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cputable.h>
  23
  24 struct cpu_spec* cur_cpu_spec = NULL;
  25 EXPORT_SYMBOL(cur_cpu_spec);
  26
  27 /* NOTE:
  28  * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  29  * the responsibility of the appropriate CPU save/restore functions to
  30  * eventually copy these settings over. Those save/restore aren't yet
  31  * part of the cputable though. That has to be fixed for both ppc32
  32  * and ppc64
  33  */
  34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  36 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  37 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  38
  39
  40 /* We only set the altivec features if the kernel was compiled with altivec
  41  * support
  42  */
  43 #ifdef CONFIG_ALTIVEC
  44 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
  45 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
  46 #else
  47 #define CPU_FTR_ALTIVEC_COMP    0
  48 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
  49 #endif
  50
  51 struct cpu_spec cpu_specs[] = {
  52         {       /* Power3 */
  53                 .pvr_mask               = 0xffff0000,
  54                 .pvr_value              = 0x00400000,
  55                 .cpu_name               = "POWER3 (630)",
  56                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  57                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  58                         CPU_FTR_PMC8,
  59                 .cpu_user_features = COMMON_USER_PPC64,
  60                 .icache_bsize           = 128,
  61                 .dcache_bsize           = 128,
  62                 .cpu_setup              = __setup_cpu_power3,
  63         },
  64         {       /* Power3+ */
  65                 .pvr_mask               = 0xffff0000,
  66                 .pvr_value              = 0x00410000,
  67                 .cpu_name               = "POWER3 (630+)",
  68                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  69                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  70                         CPU_FTR_PMC8,
  71                 .cpu_user_features      = COMMON_USER_PPC64,
  72                 .icache_bsize           = 128,
  73                 .dcache_bsize           = 128,
  74                 .cpu_setup              = __setup_cpu_power3,
  75         },
  76         {       /* Northstar */
  77                 .pvr_mask               = 0xffff0000,
  78                 .pvr_value              = 0x00330000,
  79                 .cpu_name               = "RS64-II (northstar)",
  80                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  81                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  82                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  83                 .cpu_user_features      = COMMON_USER_PPC64,
  84                 .icache_bsize           = 128,
  85                 .dcache_bsize           = 128,
  86                 .cpu_setup              = __setup_cpu_power3,
  87         },
  88         {       /* Pulsar */
  89                 .pvr_mask               = 0xffff0000,
  90                 .pvr_value              = 0x00340000,
  91                 .cpu_name               = "RS64-III (pulsar)",
  92                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  93                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  94                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  95                 .cpu_user_features      = COMMON_USER_PPC64,
  96                 .icache_bsize           = 128,
  97                 .dcache_bsize           = 128,
  98                 .cpu_setup              = __setup_cpu_power3,
  99         },
 100         {       /* I-star */
 101                 .pvr_mask               = 0xffff0000,
 102                 .pvr_value              = 0x00360000,
 103                 .cpu_name               = "RS64-III (icestar)",
 104                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 105                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 106                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
 107                 .cpu_user_features      = COMMON_USER_PPC64,
 108                 .icache_bsize           = 128,
 109                 .dcache_bsize           = 128,
 110                 .cpu_setup              = __setup_cpu_power3,
 111         },
 112         {       /* S-star */
 113                 .pvr_mask               = 0xffff0000,
 114                 .pvr_value              = 0x00370000,
 115                 .cpu_name               = "RS64-IV (sstar)",
 116                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 117                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 118                         CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
 119                 .cpu_user_features      = COMMON_USER_PPC64,
 120                 .icache_bsize           = 128,
 121                 .dcache_bsize           = 128,
 122                 .cpu_setup              = __setup_cpu_power3,
 123         },
 124         {       /* Power4 */
 125                 .pvr_mask               = 0xffff0000,
 126                 .pvr_value              = 0x00350000,
 127                 .cpu_name               = "POWER4 (gp)",
 128                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 129                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 130                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 131                 .cpu_user_features      = COMMON_USER_PPC64,
 132                 .icache_bsize           = 128,
 133                 .dcache_bsize           = 128,
 134                 .cpu_setup              = __setup_cpu_power4,
 135         },
 136         {       /* Power4+ */
 137                 .pvr_mask               = 0xffff0000,
 138                 .pvr_value              = 0x00380000,
 139                 .cpu_name               = "POWER4+ (gq)",
 140                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 141                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 142                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 143                 .cpu_user_features      = COMMON_USER_PPC64,
 144                 .icache_bsize           = 128,
 145                 .dcache_bsize           = 128,
 146                 .cpu_setup              = __setup_cpu_power4,
 147         },
 148         {       /* PPC970 */
 149                 .pvr_mask               = 0xffff0000,
 150                 .pvr_value              = 0x00390000,
 151                 .cpu_name               = "PPC970",
 152                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 153                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 154                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 155                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 156                 .cpu_user_features      = COMMON_USER_PPC64 |
 157                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 158                 .icache_bsize           = 128,
 159                 .dcache_bsize           = 128,
 160                 .cpu_setup              = __setup_cpu_ppc970,
 161         },
 162         {       /* PPC970FX */
 163                 .pvr_mask               = 0xffff0000,
 164                 .pvr_value              = 0x003c0000,
 165                 .cpu_name               = "PPC970FX",
 166                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 167                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 168                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 169                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 170                 .cpu_user_features      = COMMON_USER_PPC64 |
 171                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 172                 .icache_bsize           = 128,
 173                 .dcache_bsize           = 128,
 174                 .cpu_setup              = __setup_cpu_ppc970,
 175         },
 176         {       /* PPC970MP */
 177                 .pvr_mask               = 0xffff0000,
 178                 .pvr_value              = 0x00440000,
 179                 .cpu_name               = "PPC970MP",
 180                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 181                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 182                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 183                         CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
 184                 .cpu_user_features      = COMMON_USER_PPC64 |
 185                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 186                 .icache_bsize           = 128,
 187                 .dcache_bsize           = 128,
 188                 .cpu_setup              = __setup_cpu_ppc970,
 189         },
 190         {       /* Power5 */
 191                 .pvr_mask               = 0xffff0000,
 192                 .pvr_value              = 0x003a0000,
 193                 .cpu_name               = "POWER5 (gr)",
 194                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 195                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 196                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 197                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 198                         CPU_FTR_MMCRA_SIHV,
 199                 .cpu_user_features      = COMMON_USER_PPC64,
 200                 .icache_bsize           = 128,
 201                 .dcache_bsize           = 128,
 202                 .cpu_setup              = __setup_cpu_power4,
 203         },
 204         {       /* Power5 */
 205                 .pvr_mask               = 0xffff0000,
 206                 .pvr_value              = 0x003b0000,
 207                 .cpu_name               = "POWER5 (gs)",
 208                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 209                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 210                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 211                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 212                         CPU_FTR_MMCRA_SIHV,
 213                 .cpu_user_features      = COMMON_USER_PPC64,
 214                 .icache_bsize           = 128,
 215                 .dcache_bsize           = 128,
 216                 .cpu_setup              = __setup_cpu_power4,
 217         },
 218         {       /* BE DD1.x */
 219                 .pvr_mask               = 0xffff0000,
 220                 .pvr_value              = 0x00700000,
 221                 .cpu_name               = "Broadband Engine",
 222                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 223                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 224                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 225                         CPU_FTR_SMT,
 226                 .cpu_user_features      = COMMON_USER_PPC64 |
 227                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 228                 .icache_bsize           = 128,
 229                 .dcache_bsize           = 128,
 230                 .cpu_setup              = __setup_cpu_be,
 231         },
 232         {       /* default match */
 233                 .pvr_mask               = 0x00000000,
 234                 .pvr_value              = 0x00000000,
 235                 .cpu_name               = "POWER4 (compatible)",
 236                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 237                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 238                         CPU_FTR_PPCAS_ARCH_V2,
 239                 .cpu_user_features      = COMMON_USER_PPC64,
 240                 .icache_bsize           = 128,
 241                 .dcache_bsize           = 128,
 242                 .cpu_setup              = __setup_cpu_power4,
 243         }
 244 };