arch/s390/kernel/irq.c

   1 /*
   2  *    Copyright IBM Corp. 2004, 2011
   3  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
   4  *               Holger Smolinski <Holger.Smolinski@de.ibm.com>,
   5  *               Thomas Spatzier <tspat@de.ibm.com>,
   6  *
   7  * This file contains interrupt related functions.
   8  */
   9
  10 #include <linux/kernel_stat.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/seq_file.h>
  13 #include <linux/proc_fs.h>
  14 #include <linux/profile.h>
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ftrace.h>
  18 #include <linux/errno.h>
  19 #include <linux/slab.h>
  20 #include <linux/cpu.h>
  21 #include <linux/irq.h>
  22 #include <asm/irq_regs.h>
  23 #include <asm/cputime.h>
  24 #include <asm/lowcore.h>
  25 #include <asm/irq.h>
  26 #include <asm/hw_irq.h>
  27 #include "entry.h"
  28
  29 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
  30 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
  31
  32 struct irq_class {
  33         char *name;
  34         char *desc;
  35 };
  36
  37 /*
  38  * The list of "main" irq classes on s390. This is the list of interrupts
  39  * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
  40  * Historically only external and I/O interrupts have been part of /proc/stat.
  41  * We can't add the split external and I/O sub classes since the first field
  42  * in the "intr" line in /proc/stat is supposed to be the sum of all other
  43  * fields.
  44  * Since the external and I/O interrupt fields are already sums we would end
  45  * up with having a sum which accounts each interrupt twice.
  46  */
  47 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
  48         [EXT_INTERRUPT]  = {.name = "EXT"},
  49         [IO_INTERRUPT]   = {.name = "I/O"},
  50         [THIN_INTERRUPT] = {.name = "AIO"},
  51 };
  52
  53 /*
  54  * The list of split external and I/O interrupts that appear only in
  55  * /proc/interrupts.
  56  * In addition this list contains non external / I/O events like NMIs.
  57  */
  58 static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = {
  59         [IRQEXT_CLK] = {.name = "CLK", .desc = "[EXT] Clock Comparator"},
  60         [IRQEXT_EXC] = {.name = "EXC", .desc = "[EXT] External Call"},
  61         [IRQEXT_EMS] = {.name = "EMS", .desc = "[EXT] Emergency Signal"},
  62         [IRQEXT_TMR] = {.name = "TMR", .desc = "[EXT] CPU Timer"},
  63         [IRQEXT_TLA] = {.name = "TAL", .desc = "[EXT] Timing Alert"},
  64         [IRQEXT_PFL] = {.name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
  65         [IRQEXT_DSD] = {.name = "DSD", .desc = "[EXT] DASD Diag"},
  66         [IRQEXT_VRT] = {.name = "VRT", .desc = "[EXT] Virtio"},
  67         [IRQEXT_SCP] = {.name = "SCP", .desc = "[EXT] Service Call"},
  68         [IRQEXT_IUC] = {.name = "IUC", .desc = "[EXT] IUCV"},
  69         [IRQEXT_CMS] = {.name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
  70         [IRQEXT_CMC] = {.name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
  71         [IRQEXT_CMR] = {.name = "CMR", .desc = "[EXT] CPU-Measurement: RI"},
  72         [IRQIO_CIO]  = {.name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
  73         [IRQIO_QAI]  = {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
  74         [IRQIO_DAS]  = {.name = "DAS", .desc = "[I/O] DASD"},
  75         [IRQIO_C15]  = {.name = "C15", .desc = "[I/O] 3215"},
  76         [IRQIO_C70]  = {.name = "C70", .desc = "[I/O] 3270"},
  77         [IRQIO_TAP]  = {.name = "TAP", .desc = "[I/O] Tape"},
  78         [IRQIO_VMR]  = {.name = "VMR", .desc = "[I/O] Unit Record Devices"},
  79         [IRQIO_LCS]  = {.name = "LCS", .desc = "[I/O] LCS"},
  80         [IRQIO_CLW]  = {.name = "CLW", .desc = "[I/O] CLAW"},
  81         [IRQIO_CTC]  = {.name = "CTC", .desc = "[I/O] CTC"},
  82         [IRQIO_APB]  = {.name = "APB", .desc = "[I/O] AP Bus"},
  83         [IRQIO_ADM]  = {.name = "ADM", .desc = "[I/O] EADM Subchannel"},
  84         [IRQIO_CSC]  = {.name = "CSC", .desc = "[I/O] CHSC Subchannel"},
  85         [IRQIO_PCI]  = {.name = "PCI", .desc = "[I/O] PCI Interrupt" },
  86         [IRQIO_MSI]  = {.name = "MSI", .desc = "[I/O] MSI Interrupt" },
  87         [IRQIO_VIR]  = {.name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
  88         [IRQIO_VAI]  = {.name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
  89         [NMI_NMI]    = {.name = "NMI", .desc = "[NMI] Machine Check"},
  90         [CPU_RST]    = {.name = "RST", .desc = "[CPU] CPU Restart"},
  91 };
  92
  93 void __init init_IRQ(void)
  94 {
  95         init_cio_interrupts();
  96         init_airq_interrupts();
  97         init_ext_interrupts();
  98 }
  99
 100 void do_IRQ(struct pt_regs *regs, int irq)
 101 {
 102         struct pt_regs *old_regs;
 103
 104         old_regs = set_irq_regs(regs);
 105         irq_enter();
 106         if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
 107                 /* Serve timer interrupts first. */
 108                 clock_comparator_work();
 109         generic_handle_irq(irq);
 110         irq_exit();
 111         set_irq_regs(old_regs);
 112 }
 113
 114 /*
 115  * show_interrupts is needed by /proc/interrupts.
 116  */
 117 int show_interrupts(struct seq_file *p, void *v)
 118 {
 119         int irq = *(loff_t *) v;
 120         int cpu;
 121
 122         get_online_cpus();
 123         if (irq == 0) {
 124                 seq_puts(p, "           ");
 125                 for_each_online_cpu(cpu)
 126                         seq_printf(p, "CPU%d       ", cpu);
 127                 seq_putc(p, '\n');
 128                 goto out;
 129         }
 130         if (irq < NR_IRQS) {
 131                 if (irq >= NR_IRQS_BASE)
 132                         goto out;
 133                 seq_printf(p, "%s: ", irqclass_main_desc[irq].name);
 134                 for_each_online_cpu(cpu)
 135                         seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
 136                 seq_putc(p, '\n');
 137                 goto out;
 138         }
 139         for (irq = 0; irq < NR_ARCH_IRQS; irq++) {
 140                 seq_printf(p, "%s: ", irqclass_sub_desc[irq].name);
 141                 for_each_online_cpu(cpu)
 142                         seq_printf(p, "%10u ",
 143                                    per_cpu(irq_stat, cpu).irqs[irq]);
 144                 if (irqclass_sub_desc[irq].desc)
 145                         seq_printf(p, "  %s", irqclass_sub_desc[irq].desc);
 146                 seq_putc(p, '\n');
 147         }
 148 out:
 149         put_online_cpus();
 150         return 0;
 151 }
 152
 153 unsigned int arch_dynirq_lower_bound(unsigned int from)
 154 {
 155         return from < THIN_INTERRUPT ? THIN_INTERRUPT : from;
 156 }
 157
 158 /*
 159  * Switch to the asynchronous interrupt stack for softirq execution.
 160  */
 161 void do_softirq_own_stack(void)
 162 {
 163         unsigned long old, new;
 164
 165         /* Get current stack pointer. */
 166         asm volatile("la %0,0(15)" : "=a" (old));
 167         /* Check against async. stack address range. */
 168         new = S390_lowcore.async_stack;
 169         if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {
 170                 /* Need to switch to the async. stack. */
 171                 new -= STACK_FRAME_OVERHEAD;
 172                 ((struct stack_frame *) new)->back_chain = old;
 173                 asm volatile("   la    15,0(%0)\n"
 174                              "   basr  14,%2\n"
 175                              "   la    15,0(%1)\n"
 176                              : : "a" (new), "a" (old),
 177                                  "a" (__do_softirq)
 178                              : "0", "1", "2", "3", "4", "5", "14",
 179                                "cc", "memory" );
 180         } else {
 181                 /* We are already on the async stack. */
 182                 __do_softirq();
 183         }
 184 }
 185
 186 /*
 187  * ext_int_hash[index] is the list head for all external interrupts that hash
 188  * to this index.
 189  */
 190 static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
 191
 192 struct ext_int_info {
 193         ext_int_handler_t handler;
 194         struct hlist_node entry;
 195         struct rcu_head rcu;
 196         u16 code;
 197 };
 198
 199 /* ext_int_hash_lock protects the handler lists for external interrupts */
 200 static DEFINE_SPINLOCK(ext_int_hash_lock);
 201
 202 static inline int ext_hash(u16 code)
 203 {
 204         BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
 205
 206         return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
 207 }
 208
 209 int register_external_irq(u16 code, ext_int_handler_t handler)
 210 {
 211         struct ext_int_info *p;
 212         unsigned long flags;
 213         int index;
 214
 215         p = kmalloc(sizeof(*p), GFP_ATOMIC);
 216         if (!p)
 217                 return -ENOMEM;
 218         p->code = code;
 219         p->handler = handler;
 220         index = ext_hash(code);
 221
 222         spin_lock_irqsave(&ext_int_hash_lock, flags);
 223         hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
 224         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
 225         return 0;
 226 }
 227 EXPORT_SYMBOL(register_external_irq);
 228
 229 int unregister_external_irq(u16 code, ext_int_handler_t handler)
 230 {
 231         struct ext_int_info *p;
 232         unsigned long flags;
 233         int index = ext_hash(code);
 234
 235         spin_lock_irqsave(&ext_int_hash_lock, flags);
 236         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
 237                 if (p->code == code && p->handler == handler) {
 238                         hlist_del_rcu(&p->entry);
 239                         kfree_rcu(p, rcu);
 240                 }
 241         }
 242         spin_unlock_irqrestore(&ext_int_hash_lock, flags);
 243         return 0;
 244 }
 245 EXPORT_SYMBOL(unregister_external_irq);
 246
 247 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
 248 {
 249         struct pt_regs *regs = get_irq_regs();
 250         struct ext_code ext_code;
 251         struct ext_int_info *p;
 252         int index;
 253
 254         ext_code = *(struct ext_code *) &regs->int_code;
 255         if (ext_code.code != EXT_IRQ_CLK_COMP)
 256                 __get_cpu_var(s390_idle).nohz_delay = 1;
 257
 258         index = ext_hash(ext_code.code);
 259         rcu_read_lock();
 260         hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
 261                 if (unlikely(p->code != ext_code.code))
 262                         continue;
 263                 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
 264         }
 265         rcu_read_unlock();
 266         return IRQ_HANDLED;
 267 }
 268
 269 static struct irqaction external_interrupt = {
 270         .name    = "EXT",
 271         .handler = do_ext_interrupt,
 272 };
 273
 274 void __init init_ext_interrupts(void)
 275 {
 276         int idx;
 277
 278         for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
 279                 INIT_HLIST_HEAD(&ext_int_hash[idx]);
 280
 281         irq_set_chip_and_handler(EXT_INTERRUPT,
 282                                  &dummy_irq_chip, handle_percpu_irq);
 283         setup_irq(EXT_INTERRUPT, &external_interrupt);
 284 }
 285
 286 static DEFINE_SPINLOCK(irq_subclass_lock);
 287 static unsigned char irq_subclass_refcount[64];
 288
 289 void irq_subclass_register(enum irq_subclass subclass)
 290 {
 291         spin_lock(&irq_subclass_lock);
 292         if (!irq_subclass_refcount[subclass])
 293                 ctl_set_bit(0, subclass);
 294         irq_subclass_refcount[subclass]++;
 295         spin_unlock(&irq_subclass_lock);
 296 }
 297 EXPORT_SYMBOL(irq_subclass_register);
 298
 299 void irq_subclass_unregister(enum irq_subclass subclass)
 300 {
 301         spin_lock(&irq_subclass_lock);
 302         irq_subclass_refcount[subclass]--;
 303         if (!irq_subclass_refcount[subclass])
 304                 ctl_clear_bit(0, subclass);
 305         spin_unlock(&irq_subclass_lock);
 306 }
 307 EXPORT_SYMBOL(irq_subclass_unregister);