arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/mm.h>
  15 #include <linux/uio_driver.h>
  16 #include <linux/usb/m66592.h>
  17 #include <linux/sh_timer.h>
  18 #include <asm/clock.h>
  19 #include <asm/mmzone.h>
  20
  21 static struct resource rtc_resources[] = {
  22         [0] = {
  23                 .start  = 0xa465fec0,
  24                 .end    = 0xa465fec0 + 0x58 - 1,
  25                 .flags  = IORESOURCE_IO,
  26         },
  27         [1] = {
  28                 /* Period IRQ */
  29                 .start  = 45,
  30                 .flags  = IORESOURCE_IRQ,
  31         },
  32         [2] = {
  33                 /* Carry IRQ */
  34                 .start  = 46,
  35                 .flags  = IORESOURCE_IRQ,
  36         },
  37         [3] = {
  38                 /* Alarm IRQ */
  39                 .start  = 44,
  40                 .flags  = IORESOURCE_IRQ,
  41         },
  42 };
  43
  44 static struct platform_device rtc_device = {
  45         .name           = "sh-rtc",
  46         .id             = -1,
  47         .num_resources  = ARRAY_SIZE(rtc_resources),
  48         .resource       = rtc_resources,
  49 };
  50
  51 static struct m66592_platdata usbf_platdata = {
  52         .on_chip = 1,
  53 };
  54
  55 static struct resource usbf_resources[] = {
  56         [0] = {
  57                 .name   = "USBF",
  58                 .start  = 0x04480000,
  59                 .end    = 0x044800FF,
  60                 .flags  = IORESOURCE_MEM,
  61         },
  62         [1] = {
  63                 .start  = 65,
  64                 .end    = 65,
  65                 .flags  = IORESOURCE_IRQ,
  66         },
  67 };
  68
  69 static struct platform_device usbf_device = {
  70         .name           = "m66592_udc",
  71         .id             = 0, /* "usbf0" clock */
  72         .dev = {
  73                 .dma_mask               = NULL,
  74                 .coherent_dma_mask      = 0xffffffff,
  75                 .platform_data          = &usbf_platdata,
  76         },
  77         .num_resources  = ARRAY_SIZE(usbf_resources),
  78         .resource       = usbf_resources,
  79 };
  80
  81 static struct resource iic_resources[] = {
  82         [0] = {
  83                 .name   = "IIC",
  84                 .start  = 0x04470000,
  85                 .end    = 0x04470017,
  86                 .flags  = IORESOURCE_MEM,
  87         },
  88         [1] = {
  89                 .start  = 96,
  90                 .end    = 99,
  91                 .flags  = IORESOURCE_IRQ,
  92        },
  93 };
  94
  95 static struct platform_device iic_device = {
  96         .name           = "i2c-sh_mobile",
  97         .id             = 0, /* "i2c0" clock */
  98         .num_resources  = ARRAY_SIZE(iic_resources),
  99         .resource       = iic_resources,
 100 };
 101
 102 static struct uio_info vpu_platform_data = {
 103         .name = "VPU4",
 104         .version = "0",
 105         .irq = 60,
 106 };
 107
 108 static struct resource vpu_resources[] = {
 109         [0] = {
 110                 .name   = "VPU",
 111                 .start  = 0xfe900000,
 112                 .end    = 0xfe9022eb,
 113                 .flags  = IORESOURCE_MEM,
 114         },
 115         [1] = {
 116                 /* place holder for contiguous memory */
 117         },
 118 };
 119
 120 static struct platform_device vpu_device = {
 121         .name           = "uio_pdrv_genirq",
 122         .id             = 0,
 123         .dev = {
 124                 .platform_data  = &vpu_platform_data,
 125         },
 126         .resource       = vpu_resources,
 127         .num_resources  = ARRAY_SIZE(vpu_resources),
 128 };
 129
 130 static struct uio_info veu_platform_data = {
 131         .name = "VEU",
 132         .version = "0",
 133         .irq = 54,
 134 };
 135
 136 static struct resource veu_resources[] = {
 137         [0] = {
 138                 .name   = "VEU",
 139                 .start  = 0xfe920000,
 140                 .end    = 0xfe9200b7,
 141                 .flags  = IORESOURCE_MEM,
 142         },
 143         [1] = {
 144                 /* place holder for contiguous memory */
 145         },
 146 };
 147
 148 static struct platform_device veu_device = {
 149         .name           = "uio_pdrv_genirq",
 150         .id             = 1,
 151         .dev = {
 152                 .platform_data  = &veu_platform_data,
 153         },
 154         .resource       = veu_resources,
 155         .num_resources  = ARRAY_SIZE(veu_resources),
 156 };
 157
 158 static struct uio_info jpu_platform_data = {
 159         .name = "JPU",
 160         .version = "0",
 161         .irq = 27,
 162 };
 163
 164 static struct resource jpu_resources[] = {
 165         [0] = {
 166                 .name   = "JPU",
 167                 .start  = 0xfea00000,
 168                 .end    = 0xfea102d3,
 169                 .flags  = IORESOURCE_MEM,
 170         },
 171         [1] = {
 172                 /* place holder for contiguous memory */
 173         },
 174 };
 175
 176 static struct platform_device jpu_device = {
 177         .name           = "uio_pdrv_genirq",
 178         .id             = 2,
 179         .dev = {
 180                 .platform_data  = &jpu_platform_data,
 181         },
 182         .resource       = jpu_resources,
 183         .num_resources  = ARRAY_SIZE(jpu_resources),
 184 };
 185
 186 static struct sh_timer_config cmt_platform_data = {
 187         .name = "CMT",
 188         .channel_offset = 0x60,
 189         .timer_bit = 5,
 190         .clk = "cmt0",
 191         .clockevent_rating = 125,
 192         .clocksource_rating = 125,
 193 };
 194
 195 static struct resource cmt_resources[] = {
 196         [0] = {
 197                 .name   = "CMT",
 198                 .start  = 0x044a0060,
 199                 .end    = 0x044a006b,
 200                 .flags  = IORESOURCE_MEM,
 201         },
 202         [1] = {
 203                 .start  = 104,
 204                 .flags  = IORESOURCE_IRQ,
 205         },
 206 };
 207
 208 static struct platform_device cmt_device = {
 209         .name           = "sh_cmt",
 210         .id             = 0,
 211         .dev = {
 212                 .platform_data  = &cmt_platform_data,
 213         },
 214         .resource       = cmt_resources,
 215         .num_resources  = ARRAY_SIZE(cmt_resources),
 216 };
 217
 218 static struct sh_timer_config tmu0_platform_data = {
 219         .name = "TMU0",
 220         .channel_offset = 0x04,
 221         .timer_bit = 0,
 222         .clk = "tmu0",
 223         .clockevent_rating = 200,
 224 };
 225
 226 static struct resource tmu0_resources[] = {
 227         [0] = {
 228                 .name   = "TMU0",
 229                 .start  = 0xffd80008,
 230                 .end    = 0xffd80013,
 231                 .flags  = IORESOURCE_MEM,
 232         },
 233         [1] = {
 234                 .start  = 16,
 235                 .flags  = IORESOURCE_IRQ,
 236         },
 237 };
 238
 239 static struct platform_device tmu0_device = {
 240         .name           = "sh_tmu",
 241         .id             = 0,
 242         .dev = {
 243                 .platform_data  = &tmu0_platform_data,
 244         },
 245         .resource       = tmu0_resources,
 246         .num_resources  = ARRAY_SIZE(tmu0_resources),
 247 };
 248
 249 static struct sh_timer_config tmu1_platform_data = {
 250         .name = "TMU1",
 251         .channel_offset = 0x10,
 252         .timer_bit = 1,
 253         .clk = "tmu0",
 254         .clocksource_rating = 200,
 255 };
 256
 257 static struct resource tmu1_resources[] = {
 258         [0] = {
 259                 .name   = "TMU1",
 260                 .start  = 0xffd80014,
 261                 .end    = 0xffd8001f,
 262                 .flags  = IORESOURCE_MEM,
 263         },
 264         [1] = {
 265                 .start  = 17,
 266                 .flags  = IORESOURCE_IRQ,
 267         },
 268 };
 269
 270 static struct platform_device tmu1_device = {
 271         .name           = "sh_tmu",
 272         .id             = 1,
 273         .dev = {
 274                 .platform_data  = &tmu1_platform_data,
 275         },
 276         .resource       = tmu1_resources,
 277         .num_resources  = ARRAY_SIZE(tmu1_resources),
 278 };
 279
 280 static struct sh_timer_config tmu2_platform_data = {
 281         .name = "TMU2",
 282         .channel_offset = 0x1c,
 283         .timer_bit = 2,
 284         .clk = "tmu0",
 285 };
 286
 287 static struct resource tmu2_resources[] = {
 288         [0] = {
 289                 .name   = "TMU2",
 290                 .start  = 0xffd80020,
 291                 .end    = 0xffd8002b,
 292                 .flags  = IORESOURCE_MEM,
 293         },
 294         [1] = {
 295                 .start  = 18,
 296                 .flags  = IORESOURCE_IRQ,
 297         },
 298 };
 299
 300 static struct platform_device tmu2_device = {
 301         .name           = "sh_tmu",
 302         .id             = 2,
 303         .dev = {
 304                 .platform_data  = &tmu2_platform_data,
 305         },
 306         .resource       = tmu2_resources,
 307         .num_resources  = ARRAY_SIZE(tmu2_resources),
 308 };
 309
 310 static struct plat_sci_port sci_platform_data[] = {
 311         {
 312                 .mapbase        = 0xffe00000,
 313                 .flags          = UPF_BOOT_AUTOCONF,
 314                 .type           = PORT_SCIF,
 315                 .irqs           = { 80, 80, 80, 80 },
 316                 .clk            = "scif0",
 317         },
 318         {
 319                 .mapbase        = 0xffe10000,
 320                 .flags          = UPF_BOOT_AUTOCONF,
 321                 .type           = PORT_SCIF,
 322                 .irqs           = { 81, 81, 81, 81 },
 323                 .clk            = "scif1",
 324         },
 325         {
 326                 .mapbase        = 0xffe20000,
 327                 .flags          = UPF_BOOT_AUTOCONF,
 328                 .type           = PORT_SCIF,
 329                 .irqs           = { 82, 82, 82, 82 },
 330                 .clk            = "scif2",
 331         },
 332         {
 333                 .flags = 0,
 334         }
 335 };
 336
 337 static struct platform_device sci_device = {
 338         .name           = "sh-sci",
 339         .id             = -1,
 340         .dev            = {
 341                 .platform_data  = sci_platform_data,
 342         },
 343 };
 344
 345 static struct platform_device *sh7722_devices[] __initdata = {
 346         &cmt_device,
 347         &tmu0_device,
 348         &tmu1_device,
 349         &tmu2_device,
 350         &rtc_device,
 351         &usbf_device,
 352         &iic_device,
 353         &sci_device,
 354         &vpu_device,
 355         &veu_device,
 356         &jpu_device,
 357 };
 358
 359 static int __init sh7722_devices_setup(void)
 360 {
 361         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 362         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 363         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 364
 365         return platform_add_devices(sh7722_devices,
 366                                     ARRAY_SIZE(sh7722_devices));
 367 }
 368 __initcall(sh7722_devices_setup);
 369
 370 static struct platform_device *sh7722_early_devices[] __initdata = {
 371         &cmt_device,
 372         &tmu0_device,
 373         &tmu1_device,
 374         &tmu2_device,
 375 };
 376
 377 void __init plat_early_device_setup(void)
 378 {
 379         early_platform_add_devices(sh7722_early_devices,
 380                                    ARRAY_SIZE(sh7722_early_devices));
 381 }
 382
 383 enum {
 384         UNUSED=0,
 385
 386         /* interrupt sources */
 387         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 388         HUDI,
 389         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 390         RTC_ATI, RTC_PRI, RTC_CUI,
 391         DMAC0, DMAC1, DMAC2, DMAC3,
 392         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 393         VPU, TPU,
 394         USB_USBI0, USB_USBI1,
 395         DMAC4, DMAC5, DMAC_DADERR,
 396         KEYSC,
 397         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 398         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 399         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 400         SDHI0, SDHI1, SDHI2, SDHI3,
 401         CMT, TSIF, SIU, TWODG,
 402         TMU0, TMU1, TMU2,
 403         IRDA, JPU, LCDC,
 404
 405         /* interrupt groups */
 406         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 407 };
 408
 409 static struct intc_vect vectors[] __initdata = {
 410         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 411         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 412         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 413         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 414         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 415         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 416         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 417         INTC_VECT(RTC_CUI, 0x7c0),
 418         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 419         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 420         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 421         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 422         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 423         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 424         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 425         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 426         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 427         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 428         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 429         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 430         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 431         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 432         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 433         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 434         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 435         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 436         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 437         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 438         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 439         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 440 };
 441
 442 static struct intc_group groups[] __initdata = {
 443         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 444         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 445         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 446         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 447         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 448         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 449         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 450                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 451         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 452         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 453 };
 454
 455 static struct intc_mask_reg mask_registers[] __initdata = {
 456         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 457           { } },
 458         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 459           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 460         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 461           { 0, 0, 0, VPU, } },
 462         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 463           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 464         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 465           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 466         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 467           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 468         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 469           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 470         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 471           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 472             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 473         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 474           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
 475         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 476           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 477         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 478           { } },
 479         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 480           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 481         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 482           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 483 };
 484
 485 static struct intc_prio_reg prio_registers[] __initdata = {
 486         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 487         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 488         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 489         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 490         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 491         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 492         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 493         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 494         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 495         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 496         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 497         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 498         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 499           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 500 };
 501
 502 static struct intc_sense_reg sense_registers[] __initdata = {
 503         { 0xa414001c, 16, 2, /* ICR1 */
 504           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 505 };
 506
 507 static struct intc_mask_reg ack_registers[] __initdata = {
 508         { 0xa4140024, 0, 8, /* INTREQ00 */
 509           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 510 };
 511
 512 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
 513                              mask_registers, prio_registers, sense_registers,
 514                              ack_registers);
 515
 516 void __init plat_irq_setup(void)
 517 {
 518         register_intc_controller(&intc_desc);
 519 }
 520
 521 void __init plat_mem_setup(void)
 522 {
 523         /* Register the URAM space as Node 1 */
 524         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 525 }