arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/mm.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <linux/uio_driver.h>
  18 #include <linux/usb/m66592.h>
  19
  20 #include <asm/clock.h>
  21 #include <asm/mmzone.h>
  22 #include <asm/siu.h>
  23
  24 #include <cpu/dma-register.h>
  25 #include <cpu/sh7722.h>
  26 #include <cpu/serial.h>
  27
  28 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
  29         {
  30                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
  31                 .addr           = 0xffe0000c,
  32                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  33                 .mid_rid        = 0x21,
  34         }, {
  35                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
  36                 .addr           = 0xffe00014,
  37                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  38                 .mid_rid        = 0x22,
  39         }, {
  40                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
  41                 .addr           = 0xffe1000c,
  42                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  43                 .mid_rid        = 0x25,
  44         }, {
  45                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
  46                 .addr           = 0xffe10014,
  47                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  48                 .mid_rid        = 0x26,
  49         }, {
  50                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
  51                 .addr           = 0xffe2000c,
  52                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  53                 .mid_rid        = 0x29,
  54         }, {
  55                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
  56                 .addr           = 0xffe20014,
  57                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  58                 .mid_rid        = 0x2a,
  59         }, {
  60                 .slave_id       = SHDMA_SLAVE_SIUA_TX,
  61                 .addr           = 0xa454c098,
  62                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  63                 .mid_rid        = 0xb1,
  64         }, {
  65                 .slave_id       = SHDMA_SLAVE_SIUA_RX,
  66                 .addr           = 0xa454c090,
  67                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  68                 .mid_rid        = 0xb2,
  69         }, {
  70                 .slave_id       = SHDMA_SLAVE_SIUB_TX,
  71                 .addr           = 0xa454c09c,
  72                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  73                 .mid_rid        = 0xb5,
  74         }, {
  75                 .slave_id       = SHDMA_SLAVE_SIUB_RX,
  76                 .addr           = 0xa454c094,
  77                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  78                 .mid_rid        = 0xb6,
  79         }, {
  80                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
  81                 .addr           = 0x04ce0030,
  82                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
  83                 .mid_rid        = 0xc1,
  84         }, {
  85                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
  86                 .addr           = 0x04ce0030,
  87                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
  88                 .mid_rid        = 0xc2,
  89         },
  90 };
  91
  92 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
  93         {
  94                 .offset = 0,
  95                 .dmars = 0,
  96                 .dmars_bit = 0,
  97         }, {
  98                 .offset = 0x10,
  99                 .dmars = 0,
 100                 .dmars_bit = 8,
 101         }, {
 102                 .offset = 0x20,
 103                 .dmars = 4,
 104                 .dmars_bit = 0,
 105         }, {
 106                 .offset = 0x30,
 107                 .dmars = 4,
 108                 .dmars_bit = 8,
 109         }, {
 110                 .offset = 0x50,
 111                 .dmars = 8,
 112                 .dmars_bit = 0,
 113         }, {
 114                 .offset = 0x60,
 115                 .dmars = 8,
 116                 .dmars_bit = 8,
 117         }
 118 };
 119
 120 static const unsigned int ts_shift[] = TS_SHIFT;
 121
 122 static struct sh_dmae_pdata dma_platform_data = {
 123         .slave          = sh7722_dmae_slaves,
 124         .slave_num      = ARRAY_SIZE(sh7722_dmae_slaves),
 125         .channel        = sh7722_dmae_channels,
 126         .channel_num    = ARRAY_SIZE(sh7722_dmae_channels),
 127         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 128         .ts_low_mask    = CHCR_TS_LOW_MASK,
 129         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 130         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 131         .ts_shift       = ts_shift,
 132         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 133         .dmaor_init     = DMAOR_INIT,
 134 };
 135
 136 static struct resource sh7722_dmae_resources[] = {
 137         [0] = {
 138                 /* Channel registers and DMAOR */
 139                 .start  = 0xfe008020,
 140                 .end    = 0xfe00808f,
 141                 .flags  = IORESOURCE_MEM,
 142         },
 143         [1] = {
 144                 /* DMARSx */
 145                 .start  = 0xfe009000,
 146                 .end    = 0xfe00900b,
 147                 .flags  = IORESOURCE_MEM,
 148         },
 149         {
 150                 .name   = "error_irq",
 151                 .start  = evt2irq(0xbc0),
 152                 .end    = evt2irq(0xbc0),
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155         {
 156                 /* IRQ for channels 0-3 */
 157                 .start  = evt2irq(0x800),
 158                 .end    = evt2irq(0x860),
 159                 .flags  = IORESOURCE_IRQ,
 160         },
 161         {
 162                 /* IRQ for channels 4-5 */
 163                 .start  = evt2irq(0xb80),
 164                 .end    = evt2irq(0xba0),
 165                 .flags  = IORESOURCE_IRQ,
 166         },
 167 };
 168
 169 struct platform_device dma_device = {
 170         .name           = "sh-dma-engine",
 171         .id             = -1,
 172         .resource       = sh7722_dmae_resources,
 173         .num_resources  = ARRAY_SIZE(sh7722_dmae_resources),
 174         .dev            = {
 175                 .platform_data  = &dma_platform_data,
 176         },
 177 };
 178
 179 /* Serial */
 180 static struct plat_sci_port scif0_platform_data = {
 181         .mapbase        = 0xffe00000,
 182         .flags          = UPF_BOOT_AUTOCONF,
 183         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 184         .scbrr_algo_id  = SCBRR_ALGO_2,
 185         .type           = PORT_SCIF,
 186         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
 187         .ops            = &sh7722_sci_port_ops,
 188         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 189 };
 190
 191 static struct platform_device scif0_device = {
 192         .name           = "sh-sci",
 193         .id             = 0,
 194         .dev            = {
 195                 .platform_data  = &scif0_platform_data,
 196         },
 197 };
 198
 199 static struct plat_sci_port scif1_platform_data = {
 200         .mapbase        = 0xffe10000,
 201         .flags          = UPF_BOOT_AUTOCONF,
 202         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 203         .scbrr_algo_id  = SCBRR_ALGO_2,
 204         .type           = PORT_SCIF,
 205         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
 206         .ops            = &sh7722_sci_port_ops,
 207         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 208 };
 209
 210 static struct platform_device scif1_device = {
 211         .name           = "sh-sci",
 212         .id             = 1,
 213         .dev            = {
 214                 .platform_data  = &scif1_platform_data,
 215         },
 216 };
 217
 218 static struct plat_sci_port scif2_platform_data = {
 219         .mapbase        = 0xffe20000,
 220         .flags          = UPF_BOOT_AUTOCONF,
 221         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 222         .scbrr_algo_id  = SCBRR_ALGO_2,
 223         .type           = PORT_SCIF,
 224         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc40)),
 225         .ops            = &sh7722_sci_port_ops,
 226         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 227 };
 228
 229 static struct platform_device scif2_device = {
 230         .name           = "sh-sci",
 231         .id             = 2,
 232         .dev            = {
 233                 .platform_data  = &scif2_platform_data,
 234         },
 235 };
 236
 237 static struct resource rtc_resources[] = {
 238         [0] = {
 239                 .start  = 0xa465fec0,
 240                 .end    = 0xa465fec0 + 0x58 - 1,
 241                 .flags  = IORESOURCE_IO,
 242         },
 243         [1] = {
 244                 /* Period IRQ */
 245                 .start  = evt2irq(0x7a0),
 246                 .flags  = IORESOURCE_IRQ,
 247         },
 248         [2] = {
 249                 /* Carry IRQ */
 250                 .start  = evt2irq(0x7c0),
 251                 .flags  = IORESOURCE_IRQ,
 252         },
 253         [3] = {
 254                 /* Alarm IRQ */
 255                 .start  = evt2irq(0x780),
 256                 .flags  = IORESOURCE_IRQ,
 257         },
 258 };
 259
 260 static struct platform_device rtc_device = {
 261         .name           = "sh-rtc",
 262         .id             = -1,
 263         .num_resources  = ARRAY_SIZE(rtc_resources),
 264         .resource       = rtc_resources,
 265 };
 266
 267 static struct m66592_platdata usbf_platdata = {
 268         .on_chip = 1,
 269 };
 270
 271 static struct resource usbf_resources[] = {
 272         [0] = {
 273                 .name   = "USBF",
 274                 .start  = 0x04480000,
 275                 .end    = 0x044800FF,
 276                 .flags  = IORESOURCE_MEM,
 277         },
 278         [1] = {
 279                 .start  = evt2irq(0xa20),
 280                 .end    = evt2irq(0xa20),
 281                 .flags  = IORESOURCE_IRQ,
 282         },
 283 };
 284
 285 static struct platform_device usbf_device = {
 286         .name           = "m66592_udc",
 287         .id             = 0, /* "usbf0" clock */
 288         .dev = {
 289                 .dma_mask               = NULL,
 290                 .coherent_dma_mask      = 0xffffffff,
 291                 .platform_data          = &usbf_platdata,
 292         },
 293         .num_resources  = ARRAY_SIZE(usbf_resources),
 294         .resource       = usbf_resources,
 295 };
 296
 297 static struct resource iic_resources[] = {
 298         [0] = {
 299                 .name   = "IIC",
 300                 .start  = 0x04470000,
 301                 .end    = 0x04470017,
 302                 .flags  = IORESOURCE_MEM,
 303         },
 304         [1] = {
 305                 .start  = evt2irq(0xe00),
 306                 .end    = evt2irq(0xe60),
 307                 .flags  = IORESOURCE_IRQ,
 308        },
 309 };
 310
 311 static struct platform_device iic_device = {
 312         .name           = "i2c-sh_mobile",
 313         .id             = 0, /* "i2c0" clock */
 314         .num_resources  = ARRAY_SIZE(iic_resources),
 315         .resource       = iic_resources,
 316 };
 317
 318 static struct uio_info vpu_platform_data = {
 319         .name = "VPU4",
 320         .version = "0",
 321         .irq = evt2irq(0x980),
 322 };
 323
 324 static struct resource vpu_resources[] = {
 325         [0] = {
 326                 .name   = "VPU",
 327                 .start  = 0xfe900000,
 328                 .end    = 0xfe9022eb,
 329                 .flags  = IORESOURCE_MEM,
 330         },
 331         [1] = {
 332                 /* place holder for contiguous memory */
 333         },
 334 };
 335
 336 static struct platform_device vpu_device = {
 337         .name           = "uio_pdrv_genirq",
 338         .id             = 0,
 339         .dev = {
 340                 .platform_data  = &vpu_platform_data,
 341         },
 342         .resource       = vpu_resources,
 343         .num_resources  = ARRAY_SIZE(vpu_resources),
 344 };
 345
 346 static struct uio_info veu_platform_data = {
 347         .name = "VEU",
 348         .version = "0",
 349         .irq = evt2irq(0x8c0),
 350 };
 351
 352 static struct resource veu_resources[] = {
 353         [0] = {
 354                 .name   = "VEU",
 355                 .start  = 0xfe920000,
 356                 .end    = 0xfe9200b7,
 357                 .flags  = IORESOURCE_MEM,
 358         },
 359         [1] = {
 360                 /* place holder for contiguous memory */
 361         },
 362 };
 363
 364 static struct platform_device veu_device = {
 365         .name           = "uio_pdrv_genirq",
 366         .id             = 1,
 367         .dev = {
 368                 .platform_data  = &veu_platform_data,
 369         },
 370         .resource       = veu_resources,
 371         .num_resources  = ARRAY_SIZE(veu_resources),
 372 };
 373
 374 static struct uio_info jpu_platform_data = {
 375         .name = "JPU",
 376         .version = "0",
 377         .irq = evt2irq(0x560),
 378 };
 379
 380 static struct resource jpu_resources[] = {
 381         [0] = {
 382                 .name   = "JPU",
 383                 .start  = 0xfea00000,
 384                 .end    = 0xfea102d3,
 385                 .flags  = IORESOURCE_MEM,
 386         },
 387         [1] = {
 388                 /* place holder for contiguous memory */
 389         },
 390 };
 391
 392 static struct platform_device jpu_device = {
 393         .name           = "uio_pdrv_genirq",
 394         .id             = 2,
 395         .dev = {
 396                 .platform_data  = &jpu_platform_data,
 397         },
 398         .resource       = jpu_resources,
 399         .num_resources  = ARRAY_SIZE(jpu_resources),
 400 };
 401
 402 static struct sh_timer_config cmt_platform_data = {
 403         .channel_offset = 0x60,
 404         .timer_bit = 5,
 405         .clockevent_rating = 125,
 406         .clocksource_rating = 125,
 407 };
 408
 409 static struct resource cmt_resources[] = {
 410         [0] = {
 411                 .start  = 0x044a0060,
 412                 .end    = 0x044a006b,
 413                 .flags  = IORESOURCE_MEM,
 414         },
 415         [1] = {
 416                 .start  = evt2irq(0xf00),
 417                 .flags  = IORESOURCE_IRQ,
 418         },
 419 };
 420
 421 static struct platform_device cmt_device = {
 422         .name           = "sh_cmt",
 423         .id             = 0,
 424         .dev = {
 425                 .platform_data  = &cmt_platform_data,
 426         },
 427         .resource       = cmt_resources,
 428         .num_resources  = ARRAY_SIZE(cmt_resources),
 429 };
 430
 431 static struct sh_timer_config tmu0_platform_data = {
 432         .channel_offset = 0x04,
 433         .timer_bit = 0,
 434         .clockevent_rating = 200,
 435 };
 436
 437 static struct resource tmu0_resources[] = {
 438         [0] = {
 439                 .start  = 0xffd80008,
 440                 .end    = 0xffd80013,
 441                 .flags  = IORESOURCE_MEM,
 442         },
 443         [1] = {
 444                 .start  = evt2irq(0x400),
 445                 .flags  = IORESOURCE_IRQ,
 446         },
 447 };
 448
 449 static struct platform_device tmu0_device = {
 450         .name           = "sh_tmu",
 451         .id             = 0,
 452         .dev = {
 453                 .platform_data  = &tmu0_platform_data,
 454         },
 455         .resource       = tmu0_resources,
 456         .num_resources  = ARRAY_SIZE(tmu0_resources),
 457 };
 458
 459 static struct sh_timer_config tmu1_platform_data = {
 460         .channel_offset = 0x10,
 461         .timer_bit = 1,
 462         .clocksource_rating = 200,
 463 };
 464
 465 static struct resource tmu1_resources[] = {
 466         [0] = {
 467                 .start  = 0xffd80014,
 468                 .end    = 0xffd8001f,
 469                 .flags  = IORESOURCE_MEM,
 470         },
 471         [1] = {
 472                 .start  = evt2irq(0x420),
 473                 .flags  = IORESOURCE_IRQ,
 474         },
 475 };
 476
 477 static struct platform_device tmu1_device = {
 478         .name           = "sh_tmu",
 479         .id             = 1,
 480         .dev = {
 481                 .platform_data  = &tmu1_platform_data,
 482         },
 483         .resource       = tmu1_resources,
 484         .num_resources  = ARRAY_SIZE(tmu1_resources),
 485 };
 486
 487 static struct sh_timer_config tmu2_platform_data = {
 488         .channel_offset = 0x1c,
 489         .timer_bit = 2,
 490 };
 491
 492 static struct resource tmu2_resources[] = {
 493         [0] = {
 494                 .start  = 0xffd80020,
 495                 .end    = 0xffd8002b,
 496                 .flags  = IORESOURCE_MEM,
 497         },
 498         [1] = {
 499                 .start  = 18,
 500                 .flags  = IORESOURCE_IRQ,
 501         },
 502 };
 503
 504 static struct platform_device tmu2_device = {
 505         .name           = "sh_tmu",
 506         .id             = 2,
 507         .dev = {
 508                 .platform_data  = &tmu2_platform_data,
 509         },
 510         .resource       = tmu2_resources,
 511         .num_resources  = ARRAY_SIZE(tmu2_resources),
 512 };
 513
 514 static struct siu_platform siu_platform_data = {
 515         .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
 516         .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
 517         .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
 518         .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
 519 };
 520
 521 static struct resource siu_resources[] = {
 522         [0] = {
 523                 .start  = 0xa4540000,
 524                 .end    = 0xa454c10f,
 525                 .flags  = IORESOURCE_MEM,
 526         },
 527         [1] = {
 528                 .start  = evt2irq(0xf80),
 529                 .flags  = IORESOURCE_IRQ,
 530         },
 531 };
 532
 533 static struct platform_device siu_device = {
 534         .name           = "siu-pcm-audio",
 535         .id             = -1,
 536         .dev = {
 537                 .platform_data  = &siu_platform_data,
 538         },
 539         .resource       = siu_resources,
 540         .num_resources  = ARRAY_SIZE(siu_resources),
 541 };
 542
 543 static struct platform_device *sh7722_devices[] __initdata = {
 544         &scif0_device,
 545         &scif1_device,
 546         &scif2_device,
 547         &cmt_device,
 548         &tmu0_device,
 549         &tmu1_device,
 550         &tmu2_device,
 551         &rtc_device,
 552         &usbf_device,
 553         &iic_device,
 554         &vpu_device,
 555         &veu_device,
 556         &jpu_device,
 557         &siu_device,
 558         &dma_device,
 559 };
 560
 561 static int __init sh7722_devices_setup(void)
 562 {
 563         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 564         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 565         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 566
 567         return platform_add_devices(sh7722_devices,
 568                                     ARRAY_SIZE(sh7722_devices));
 569 }
 570 arch_initcall(sh7722_devices_setup);
 571
 572 static struct platform_device *sh7722_early_devices[] __initdata = {
 573         &scif0_device,
 574         &scif1_device,
 575         &scif2_device,
 576         &cmt_device,
 577         &tmu0_device,
 578         &tmu1_device,
 579         &tmu2_device,
 580 };
 581
 582 void __init plat_early_device_setup(void)
 583 {
 584         early_platform_add_devices(sh7722_early_devices,
 585                                    ARRAY_SIZE(sh7722_early_devices));
 586 }
 587
 588 enum {
 589         UNUSED=0,
 590         ENABLED,
 591         DISABLED,
 592
 593         /* interrupt sources */
 594         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 595         HUDI,
 596         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 597         RTC_ATI, RTC_PRI, RTC_CUI,
 598         DMAC0, DMAC1, DMAC2, DMAC3,
 599         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 600         VPU, TPU,
 601         USB_USBI0, USB_USBI1,
 602         DMAC4, DMAC5, DMAC_DADERR,
 603         KEYSC,
 604         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 605         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 606         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 607         CMT, TSIF, SIU, TWODG,
 608         TMU0, TMU1, TMU2,
 609         IRDA, JPU, LCDC,
 610
 611         /* interrupt groups */
 612         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 613 };
 614
 615 static struct intc_vect vectors[] __initdata = {
 616         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 617         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 618         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 619         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 620         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 621         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 622         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 623         INTC_VECT(RTC_CUI, 0x7c0),
 624         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 625         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 626         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 627         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 628         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 629         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 630         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 631         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 632         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 633         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 634         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 635         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 636         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 637         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 638         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 639         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 640         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 641         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 642         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 643         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 644         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 645         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 646 };
 647
 648 static struct intc_group groups[] __initdata = {
 649         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 650         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 651         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 652         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 653         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 654         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 655         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 656                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 657         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 658 };
 659
 660 static struct intc_mask_reg mask_registers[] __initdata = {
 661         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 662           { } },
 663         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 664           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 665         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 666           { 0, 0, 0, VPU, } },
 667         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 668           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 669         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 670           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 671         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 672           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 673         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 674           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 675         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 676           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 677             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 678         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 679           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
 680         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 681           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 682         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 683           { } },
 684         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 685           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 686         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 687           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 688 };
 689
 690 static struct intc_prio_reg prio_registers[] __initdata = {
 691         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 692         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 693         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 694         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 695         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 696         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 697         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 698         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 699         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 700         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 701         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 702         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 703         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 704           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 705 };
 706
 707 static struct intc_sense_reg sense_registers[] __initdata = {
 708         { 0xa414001c, 16, 2, /* ICR1 */
 709           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 710 };
 711
 712 static struct intc_mask_reg ack_registers[] __initdata = {
 713         { 0xa4140024, 0, 8, /* INTREQ00 */
 714           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 715 };
 716
 717 static struct intc_desc intc_desc __initdata = {
 718         .name = "sh7722",
 719         .force_enable = ENABLED,
 720         .force_disable = DISABLED,
 721         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 722                            prio_registers, sense_registers, ack_registers),
 723 };
 724
 725 void __init plat_irq_setup(void)
 726 {
 727         register_intc_controller(&intc_desc);
 728 }
 729
 730 void __init plat_mem_setup(void)
 731 {
 732         /* Register the URAM space as Node 1 */
 733         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 734 }