4 /* The sparc64 TSB is similar to the powerpc hashtables. It's a
5 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
6 * pointers into this table for 8K and 64K page sizes, and also a
7 * comparison TAG based upon the virtual address and context which
10 * TLB miss trap handler software does the actual lookup via something
13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
14 * ldxa [%g0] ASI_{D,I}MMU, %g6
17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
19 * bne,pn %xcc, tsb_miss_{d,i}tlb
20 * mov FAULT_CODE_{D,I}TLB, %g3
21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
26 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
29 * -------------------------------------------------
30 * | - | CONTEXT | - | VADDR bits 63:22 |
31 * -------------------------------------------------
32 * 63 61 60 48 47 42 41 0
34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
37 * Like the powerpc hashtables we need to use locking in order to
38 * synchronize while we update the entries. PTE updates need locking
41 * We need to carefully choose a lock bits for the TSB entry. We
42 * choose to use bit 47 in the tag. Also, since we never map anything
43 * at page zero in context zero, we use zero as an invalid tag entry.
44 * When the lock bit is set, this forces a tag comparison failure.
47 #define TSB_TAG_LOCK_BIT 47
48 #define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
50 #define TSB_TAG_INVALID_BIT 46
51 #define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
53 /* Some cpus support physical address quad loads. We want to use
54 * those if possible so we don't need to hard-lock the TSB mapping
55 * into the TLB. We encode some instruction patching in order to
58 * The kernel TSB is locked into the TLB by virtue of being in the
59 * kernel image, so we don't play these games for swapper_tsb access.
62 struct tsb_ldquad_phys_patch_entry {
64 unsigned int sun4u_insn;
65 unsigned int sun4v_insn;
67 extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
68 __tsb_ldquad_phys_patch_end;
70 struct tsb_phys_patch_entry {
74 extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
76 #define TSB_LOAD_QUAD(TSB, REG) \
77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
78 .section .tsb_ldquad_phys_patch, "ax"; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
84 #define TSB_LOAD_TAG_HIGH(TSB, REG) \
85 661: lduwa [TSB] ASI_N, REG; \
86 .section .tsb_phys_patch, "ax"; \
88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
91 #define TSB_LOAD_TAG(TSB, REG) \
92 661: ldxa [TSB] ASI_N, REG; \
93 .section .tsb_phys_patch, "ax"; \
95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99 661: casa [TSB] ASI_N, REG1, REG2; \
100 .section .tsb_phys_patch, "ax"; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \
106 661: casxa [TSB] ASI_N, REG1, REG2; \
107 .section .tsb_phys_patch, "ax"; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
112 #define TSB_STORE(ADDR, VAL) \
113 661: stxa VAL, [ADDR] ASI_N; \
114 .section .tsb_phys_patch, "ax"; \
116 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \
120 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122 andcc REG1, REG2, %g0; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
130 #define TSB_WRITE(TSB, TTE, TAG) \
132 TSB_STORE(TSB, TTE); \
136 /* Do a kernel page table walk. Leaves physical PTE pointer in
137 * REG1. Jumps to FAIL_LABEL on early page table walk termination.
138 * VADDR will not be clobbered, but REG2 will.
140 #define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
141 sethi %hi(swapper_pg_dir), REG1; \
142 or REG1, %lo(swapper_pg_dir), REG1; \
143 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
144 srlx REG2, 64 - PAGE_SHIFT, REG2; \
145 andn REG2, 0x7, REG2; \
146 ldx [REG1 + REG2], REG1; \
147 brz,pn REG1, FAIL_LABEL; \
148 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
149 srlx REG2, 64 - PAGE_SHIFT, REG2; \
150 andn REG2, 0x7, REG2; \
151 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
152 brz,pn REG1, FAIL_LABEL; \
153 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
154 srlx REG2, 64 - PAGE_SHIFT, REG2; \
155 andn REG2, 0x7, REG2; \
156 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
157 brz,pn REG1, FAIL_LABEL; \
158 sllx VADDR, 64 - PMD_SHIFT, REG2; \
159 srlx REG2, 64 - PAGE_SHIFT, REG2; \
160 andn REG2, 0x7, REG2; \
161 add REG1, REG2, REG1;
163 /* PMD has been loaded into REG1, interpret the value, seeing
164 * if it is a HUGE PMD or a normal one. If it is not valid
165 * then jump to FAIL_LABEL. If it is a HUGE PMD, and it
166 * translates to a valid PTE, branch to PTE_LABEL.
168 * We have to propagate the 4MB bit of the virtual address
169 * because we are fabricating 8MB pages using 4MB hw pages.
171 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
172 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
173 brz,pn REG1, FAIL_LABEL; \
174 sethi %uhi(_PAGE_PMD_HUGE), REG2; \
175 sllx REG2, 32, REG2; \
176 andcc REG1, REG2, %g0; \
178 sethi %hi(4 * 1024 * 1024), REG2; \
179 brgez,pn REG1, FAIL_LABEL; \
180 andn REG1, REG2, REG1; \
181 and VADDR, REG2, REG2; \
182 brlz,pt REG1, PTE_LABEL; \
183 or REG1, REG2, REG1; \
186 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
187 brz,pn REG1, FAIL_LABEL; \
191 /* Do a user page table walk in MMU globals. Leaves final,
192 * valid, PTE value in REG1. Jumps to FAIL_LABEL on early
193 * page table walk termination or if the PTE is not valid.
195 * Physical base of page tables is in PHYS_PGD which will not
198 * VADDR will not be clobbered, but REG1 and REG2 will.
200 #define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
201 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
202 srlx REG2, 64 - PAGE_SHIFT, REG2; \
203 andn REG2, 0x7, REG2; \
204 ldxa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
205 brz,pn REG1, FAIL_LABEL; \
206 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
207 srlx REG2, 64 - PAGE_SHIFT, REG2; \
208 andn REG2, 0x7, REG2; \
209 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
210 brz,pn REG1, FAIL_LABEL; \
211 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
212 srlx REG2, 64 - PAGE_SHIFT, REG2; \
213 andn REG2, 0x7, REG2; \
214 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
215 USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
216 sllx VADDR, 64 - PMD_SHIFT, REG2; \
217 srlx REG2, 64 - PAGE_SHIFT, REG2; \
218 andn REG2, 0x7, REG2; \
219 add REG1, REG2, REG1; \
220 ldxa [REG1] ASI_PHYS_USE_EC, REG1; \
221 brgez,pn REG1, FAIL_LABEL; \
225 /* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
226 * If no entry is found, FAIL_LABEL will be branched to. On success
227 * the resulting PTE value will be left in REG1. VADDR is preserved
230 #define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
231 sethi %hi(prom_trans), REG1; \
232 or REG1, %lo(prom_trans), REG1; \
233 97: ldx [REG1 + 0x00], REG2; \
234 brz,pn REG2, FAIL_LABEL; \
236 ldx [REG1 + 0x08], REG3; \
237 add REG2, REG3, REG3; \
242 ldx [REG1 + 0x10], REG3; \
243 sub VADDR, REG2, REG2; \
245 add REG3, REG2, REG1; \
246 98: ba,pt %xcc, 97b; \
247 add REG1, (3 * 8), REG1; \
250 /* We use a 32K TSB for the whole kernel, this allows to
251 * handle about 16MB of modules and vmalloc mappings without
252 * incurring many hash conflicts.
254 #define KERNEL_TSB_SIZE_BYTES (32 * 1024)
255 #define KERNEL_TSB_NENTRIES \
256 (KERNEL_TSB_SIZE_BYTES / 16)
257 #define KERNEL_TSB4M_NENTRIES 4096
259 #define KTSB_PHYS_SHIFT 15
261 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
262 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
263 * and the found TTE will be left in REG1. REG3 and REG4 must
264 * be an even/odd pair of registers.
266 * VADDR and TAG will be preserved and not clobbered by this macro.
268 #define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
269 661: sethi %hi(swapper_tsb), REG1; \
270 or REG1, %lo(swapper_tsb), REG1; \
271 .section .swapper_tsb_phys_patch, "ax"; \
275 .section .tsb_ldquad_phys_patch, "ax"; \
277 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
278 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
280 srlx VADDR, PAGE_SHIFT, REG2; \
281 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
282 sllx REG2, 4, REG2; \
283 add REG1, REG2, REG2; \
284 TSB_LOAD_QUAD(REG2, REG3); \
286 be,a,pt %xcc, OK_LABEL; \
289 #ifndef CONFIG_DEBUG_PAGEALLOC
290 /* This version uses a trick, the TAG is already (VADDR >> 22) so
291 * we can make use of that for the index computation.
293 #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
294 661: sethi %hi(swapper_4m_tsb), REG1; \
295 or REG1, %lo(swapper_4m_tsb), REG1; \
296 .section .swapper_4m_tsb_phys_patch, "ax"; \
300 .section .tsb_ldquad_phys_patch, "ax"; \
302 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
303 sllx REG1, KTSB_PHYS_SHIFT, REG1; \
305 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
306 sllx REG2, 4, REG2; \
307 add REG1, REG2, REG2; \
308 TSB_LOAD_QUAD(REG2, REG3); \
310 be,a,pt %xcc, OK_LABEL; \
314 #endif /* !(_SPARC64_TSB_H) */