arch/sparc/kernel/time_32.c

   1 /* linux/arch/sparc/kernel/time.c
   2  *
   3  * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
   5  *
   6  * Chris Davis (cdavis@cois.on.ca) 03/27/1998
   7  * Added support for the intersil on the sun4/4200
   8  *
   9  * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
  10  * Support for MicroSPARC-IIep, PCI CPU.
  11  *
  12  * This file handles the Sparc specific time handling details.
  13  *
  14  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
  15  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  16  */
  17 #include <linux/errno.h>
  18 #include <linux/module.h>
  19 #include <linux/sched.h>
  20 #include <linux/kernel.h>
  21 #include <linux/param.h>
  22 #include <linux/string.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/time.h>
  26 #include <linux/rtc.h>
  27 #include <linux/rtc/m48t59.h>
  28 #include <linux/timex.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/ioport.h>
  34 #include <linux/profile.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37 #include <linux/platform_device.h>
  38
  39 #include <asm/oplib.h>
  40 #include <asm/timex.h>
  41 #include <asm/timer.h>
  42 #include <asm/irq.h>
  43 #include <asm/io.h>
  44 #include <asm/idprom.h>
  45 #include <asm/machines.h>
  46 #include <asm/page.h>
  47 #include <asm/pcic.h>
  48 #include <asm/irq_regs.h>
  49 #include <asm/setup.h>
  50
  51 #include "irq.h"
  52
  53 static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
  54 static __volatile__ u64 timer_cs_internal_counter = 0;
  55 static char timer_cs_enabled = 0;
  56
  57 static struct clock_event_device timer_ce;
  58 static char timer_ce_enabled = 0;
  59
  60 #ifdef CONFIG_SMP
  61 DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
  62 #endif
  63
  64 DEFINE_SPINLOCK(rtc_lock);
  65 EXPORT_SYMBOL(rtc_lock);
  66
  67 static int set_rtc_mmss(unsigned long);
  68
  69 unsigned long profile_pc(struct pt_regs *regs)
  70 {
  71         extern char __copy_user_begin[], __copy_user_end[];
  72         extern char __atomic_begin[], __atomic_end[];
  73         extern char __bzero_begin[], __bzero_end[];
  74
  75         unsigned long pc = regs->pc;
  76
  77         if (in_lock_functions(pc) ||
  78             (pc >= (unsigned long) __copy_user_begin &&
  79              pc < (unsigned long) __copy_user_end) ||
  80             (pc >= (unsigned long) __atomic_begin &&
  81              pc < (unsigned long) __atomic_end) ||
  82             (pc >= (unsigned long) __bzero_begin &&
  83              pc < (unsigned long) __bzero_end))
  84                 pc = regs->u_regs[UREG_RETPC];
  85         return pc;
  86 }
  87
  88 EXPORT_SYMBOL(profile_pc);
  89
  90 __volatile__ unsigned int *master_l10_counter;
  91
  92 int update_persistent_clock(struct timespec now)
  93 {
  94         return set_rtc_mmss(now.tv_sec);
  95 }
  96
  97 irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
  98 {
  99         if (timer_cs_enabled) {
 100                 write_seqlock(&timer_cs_lock);
 101                 timer_cs_internal_counter++;
 102                 clear_clock_irq();
 103                 write_sequnlock(&timer_cs_lock);
 104         } else {
 105                 clear_clock_irq();
 106         }
 107
 108         if (timer_ce_enabled)
 109                 timer_ce.event_handler(&timer_ce);
 110
 111         return IRQ_HANDLED;
 112 }
 113
 114 static void timer_ce_set_mode(enum clock_event_mode mode,
 115                               struct clock_event_device *evt)
 116 {
 117         switch (mode) {
 118                 case CLOCK_EVT_MODE_PERIODIC:
 119                 case CLOCK_EVT_MODE_RESUME:
 120                         timer_ce_enabled = 1;
 121                         break;
 122                 case CLOCK_EVT_MODE_SHUTDOWN:
 123                         timer_ce_enabled = 0;
 124                         break;
 125                 default:
 126                         break;
 127         }
 128         smp_mb();
 129 }
 130
 131 static __init void setup_timer_ce(void)
 132 {
 133         struct clock_event_device *ce = &timer_ce;
 134
 135         BUG_ON(smp_processor_id() != boot_cpu_id);
 136
 137         ce->name     = "timer_ce";
 138         ce->rating   = 100;
 139         ce->features = CLOCK_EVT_FEAT_PERIODIC;
 140         ce->set_mode = timer_ce_set_mode;
 141         ce->cpumask  = cpu_possible_mask;
 142         ce->shift    = 32;
 143         ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
 144                               ce->shift);
 145         clockevents_register_device(ce);
 146 }
 147
 148 static unsigned int sbus_cycles_offset(void)
 149 {
 150         unsigned int val, offset;
 151
 152         val = *master_l10_counter;
 153         offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
 154
 155         /* Limit hit? */
 156         if (val & TIMER_LIMIT_BIT)
 157                 offset += sparc_config.cs_period;
 158
 159         return offset;
 160 }
 161
 162 static cycle_t timer_cs_read(struct clocksource *cs)
 163 {
 164         unsigned int seq, offset;
 165         u64 cycles;
 166
 167         do {
 168                 seq = read_seqbegin(&timer_cs_lock);
 169
 170                 cycles = timer_cs_internal_counter;
 171                 offset = sparc_config.get_cycles_offset();
 172         } while (read_seqretry(&timer_cs_lock, seq));
 173
 174         /* Count absolute cycles */
 175         cycles *= sparc_config.cs_period;
 176         cycles += offset;
 177
 178         return cycles;
 179 }
 180
 181 static struct clocksource timer_cs = {
 182         .name   = "timer_cs",
 183         .rating = 100,
 184         .read   = timer_cs_read,
 185         .mask   = CLOCKSOURCE_MASK(64),
 186         .shift  = 2,
 187         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 188 };
 189
 190 static __init int setup_timer_cs(void)
 191 {
 192         timer_cs_enabled = 1;
 193         timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
 194                                             timer_cs.shift);
 195
 196         return clocksource_register(&timer_cs);
 197 }
 198
 199 #ifdef CONFIG_SMP
 200 static void percpu_ce_setup(enum clock_event_mode mode,
 201                         struct clock_event_device *evt)
 202 {
 203         int cpu = __first_cpu(evt->cpumask);
 204
 205         switch (mode) {
 206                 case CLOCK_EVT_MODE_PERIODIC:
 207                         load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
 208                         break;
 209                 case CLOCK_EVT_MODE_ONESHOT:
 210                 case CLOCK_EVT_MODE_SHUTDOWN:
 211                 case CLOCK_EVT_MODE_UNUSED:
 212                         load_profile_irq(cpu, 0);
 213                         break;
 214                 default:
 215                         break;
 216         }
 217 }
 218
 219 static int percpu_ce_set_next_event(unsigned long delta,
 220                                     struct clock_event_device *evt)
 221 {
 222         int cpu = __first_cpu(evt->cpumask);
 223         unsigned int next = (unsigned int)delta;
 224
 225         load_profile_irq(cpu, next);
 226         return 0;
 227 }
 228
 229 void register_percpu_ce(int cpu)
 230 {
 231         struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
 232         unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
 233
 234         if (sparc_config.features & FEAT_L14_ONESHOT)
 235                 features |= CLOCK_EVT_FEAT_ONESHOT;
 236
 237         ce->name           = "percpu_ce";
 238         ce->rating         = 200;
 239         ce->features       = features;
 240         ce->set_mode       = percpu_ce_setup;
 241         ce->set_next_event = percpu_ce_set_next_event;
 242         ce->cpumask        = cpumask_of(cpu);
 243         ce->shift          = 32;
 244         ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
 245                                     ce->shift);
 246         ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
 247         ce->min_delta_ns   = clockevent_delta2ns(100, ce);
 248
 249         clockevents_register_device(ce);
 250 }
 251 #endif
 252
 253 static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
 254 {
 255         struct platform_device *pdev = to_platform_device(dev);
 256         struct m48t59_plat_data *pdata = pdev->dev.platform_data;
 257
 258         return readb(pdata->ioaddr + ofs);
 259 }
 260
 261 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
 262 {
 263         struct platform_device *pdev = to_platform_device(dev);
 264         struct m48t59_plat_data *pdata = pdev->dev.platform_data;
 265
 266         writeb(val, pdata->ioaddr + ofs);
 267 }
 268
 269 static struct m48t59_plat_data m48t59_data = {
 270         .read_byte = mostek_read_byte,
 271         .write_byte = mostek_write_byte,
 272 };
 273
 274 /* resource is set at runtime */
 275 static struct platform_device m48t59_rtc = {
 276         .name           = "rtc-m48t59",
 277         .id             = 0,
 278         .num_resources  = 1,
 279         .dev    = {
 280                 .platform_data = &m48t59_data,
 281         },
 282 };
 283
 284 static int __devinit clock_probe(struct platform_device *op)
 285 {
 286         struct device_node *dp = op->dev.of_node;
 287         const char *model = of_get_property(dp, "model", NULL);
 288
 289         if (!model)
 290                 return -ENODEV;
 291
 292         /* Only the primary RTC has an address property */
 293         if (!of_find_property(dp, "address", NULL))
 294                 return -ENODEV;
 295
 296         m48t59_rtc.resource = &op->resource[0];
 297         if (!strcmp(model, "mk48t02")) {
 298                 /* Map the clock register io area read-only */
 299                 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
 300                                                 2048, "rtc-m48t59");
 301                 m48t59_data.type = M48T59RTC_TYPE_M48T02;
 302         } else if (!strcmp(model, "mk48t08")) {
 303                 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
 304                                                 8192, "rtc-m48t59");
 305                 m48t59_data.type = M48T59RTC_TYPE_M48T08;
 306         } else
 307                 return -ENODEV;
 308
 309         if (platform_device_register(&m48t59_rtc) < 0)
 310                 printk(KERN_ERR "Registering RTC device failed\n");
 311
 312         return 0;
 313 }
 314
 315 static struct of_device_id clock_match[] = {
 316         {
 317                 .name = "eeprom",
 318         },
 319         {},
 320 };
 321
 322 static struct platform_driver clock_driver = {
 323         .probe          = clock_probe,
 324         .driver = {
 325                 .name = "rtc",
 326                 .owner = THIS_MODULE,
 327                 .of_match_table = clock_match,
 328         },
 329 };
 330
 331
 332 /* Probe for the mostek real time clock chip. */
 333 static int __init clock_init(void)
 334 {
 335         return platform_driver_register(&clock_driver);
 336 }
 337 /* Must be after subsys_initcall() so that busses are probed.  Must
 338  * be before device_initcall() because things like the RTC driver
 339  * need to see the clock registers.
 340  */
 341 fs_initcall(clock_init);
 342
 343 static void __init sparc32_late_time_init(void)
 344 {
 345         if (sparc_config.features & FEAT_L10_CLOCKEVENT)
 346                 setup_timer_ce();
 347         if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
 348                 setup_timer_cs();
 349 #ifdef CONFIG_SMP
 350         register_percpu_ce(smp_processor_id());
 351 #endif
 352 }
 353
 354 static void __init sbus_time_init(void)
 355 {
 356         sparc_config.get_cycles_offset = sbus_cycles_offset;
 357         sparc_config.init_timers();
 358 }
 359
 360 void __init time_init(void)
 361 {
 362         btfixup();
 363
 364         sparc_config.features = 0;
 365         late_time_init = sparc32_late_time_init;
 366
 367         if (pcic_present())
 368                 pci_time_init();
 369         else
 370                 sbus_time_init();
 371 }
 372
 373
 374 static int set_rtc_mmss(unsigned long secs)
 375 {
 376         struct rtc_device *rtc = rtc_class_open("rtc0");
 377         int err = -1;
 378
 379         if (rtc) {
 380                 err = rtc_set_mmss(rtc, secs);
 381                 rtc_class_close(rtc);
 382         }
 383
 384         return err;
 385 }