1 #include <linux/perf_event.h>
2 #include <linux/types.h>
4 #include <asm/perf_event.h>
8 #include "../perf_event.h"
12 LBR_FORMAT_LIP = 0x01,
13 LBR_FORMAT_EIP = 0x02,
14 LBR_FORMAT_EIP_FLAGS = 0x03,
15 LBR_FORMAT_EIP_FLAGS2 = 0x04,
16 LBR_FORMAT_INFO = 0x05,
17 LBR_FORMAT_TIME = 0x06,
18 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
24 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
25 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
26 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
30 * Intel LBR_SELECT bits
31 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
33 * Hardware branch filter (not available on all CPUs)
35 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
36 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
37 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
38 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
39 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
40 #define LBR_RETURN_BIT 5 /* do not capture near returns */
41 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
42 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
43 #define LBR_FAR_BIT 8 /* do not capture far branches */
44 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
47 * Following bit only exists in Linux; we mask it out before writing it to
48 * the actual MSR. But it helps the constraint perf code to understand
49 * that this is a separate configuration.
51 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */
53 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
54 #define LBR_USER (1 << LBR_USER_BIT)
55 #define LBR_JCC (1 << LBR_JCC_BIT)
56 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
57 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
58 #define LBR_RETURN (1 << LBR_RETURN_BIT)
59 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
60 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
61 #define LBR_FAR (1 << LBR_FAR_BIT)
62 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
63 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT)
65 #define LBR_PLM (LBR_KERNEL | LBR_USER)
67 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
68 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
69 #define LBR_IGN 0 /* ignored */
80 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
81 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
82 #define LBR_FROM_FLAG_ABORT BIT_ULL(61)
84 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
87 * x86control flow change classification
88 * x86control flow changes include branches, interrupts, traps, faults
91 X86_BR_NONE = 0, /* unknown */
93 X86_BR_USER = 1 << 0, /* branch target is user */
94 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
96 X86_BR_CALL = 1 << 2, /* call */
97 X86_BR_RET = 1 << 3, /* return */
98 X86_BR_SYSCALL = 1 << 4, /* syscall */
99 X86_BR_SYSRET = 1 << 5, /* syscall return */
100 X86_BR_INT = 1 << 6, /* sw interrupt */
101 X86_BR_IRET = 1 << 7, /* return from interrupt */
102 X86_BR_JCC = 1 << 8, /* conditional */
103 X86_BR_JMP = 1 << 9, /* jump */
104 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
105 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
106 X86_BR_ABORT = 1 << 12,/* transaction abort */
107 X86_BR_IN_TX = 1 << 13,/* in transaction */
108 X86_BR_NO_TX = 1 << 14,/* not in transaction */
109 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
110 X86_BR_CALL_STACK = 1 << 16,/* call stack */
111 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
114 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
115 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
132 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
134 #define X86_BR_ANY_CALL \
142 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
145 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
146 * otherwise it becomes near impossible to get a reliable stack.
149 static void __intel_pmu_lbr_enable(bool pmi)
151 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
152 u64 debugctl, lbr_select = 0, orig_debugctl;
155 * No need to unfreeze manually, as v4 can do that as part
156 * of the GLOBAL_STATUS ack.
158 if (pmi && x86_pmu.version >= 4)
162 * No need to reprogram LBR_SELECT in a PMI, as it
166 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
167 if (!pmi && cpuc->lbr_sel)
168 wrmsrl(MSR_LBR_SELECT, lbr_select);
170 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
171 orig_debugctl = debugctl;
172 debugctl |= DEBUGCTLMSR_LBR;
174 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
175 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
176 * may cause superfluous increase/decrease of LBR_TOS.
178 if (!(lbr_select & LBR_CALL_STACK))
179 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
180 if (orig_debugctl != debugctl)
181 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
184 static void __intel_pmu_lbr_disable(void)
188 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
189 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
190 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
193 static void intel_pmu_lbr_reset_32(void)
197 for (i = 0; i < x86_pmu.lbr_nr; i++)
198 wrmsrl(x86_pmu.lbr_from + i, 0);
201 static void intel_pmu_lbr_reset_64(void)
205 for (i = 0; i < x86_pmu.lbr_nr; i++) {
206 wrmsrl(x86_pmu.lbr_from + i, 0);
207 wrmsrl(x86_pmu.lbr_to + i, 0);
208 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
209 wrmsrl(MSR_LBR_INFO_0 + i, 0);
213 void intel_pmu_lbr_reset(void)
218 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
219 intel_pmu_lbr_reset_32();
221 intel_pmu_lbr_reset_64();
225 * TOS = most recently recorded branch
227 static inline u64 intel_pmu_lbr_tos(void)
231 rdmsrl(x86_pmu.lbr_tos, tos);
241 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
242 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
243 * TSX is not supported they have no consistent behavior:
245 * - For wrmsr(), bits 61:62 are considered part of the sign extension.
246 * - For HW updates (branch captures) bits 61:62 are always OFF and are not
247 * part of the sign extension.
251 * 1) LBR has TSX format
252 * 2) CPU has no TSX support enabled
254 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any
255 * value from rdmsr() must be converted to have a 61 bits sign extension,
256 * ignoring the TSX flags.
258 static inline bool lbr_from_signext_quirk_needed(void)
260 int lbr_format = x86_pmu.intel_cap.lbr_format;
261 bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
262 boot_cpu_has(X86_FEATURE_RTM);
264 return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX);
267 DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
269 /* If quirk is enabled, ensure sign extension is 63 bits: */
270 inline u64 lbr_from_signext_quirk_wr(u64 val)
272 if (static_branch_unlikely(&lbr_from_quirk_key)) {
274 * Sign extend into bits 61:62 while preserving bit 63.
276 * Quirk is enabled when TSX is disabled. Therefore TSX bits
277 * in val are always OFF and must be changed to be sign
278 * extension bits. Since bits 59:60 are guaranteed to be
279 * part of the sign extension bits, we can just copy them
282 val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2;
288 * If quirk is needed, ensure sign extension is 61 bits:
290 u64 lbr_from_signext_quirk_rd(u64 val)
292 if (static_branch_unlikely(&lbr_from_quirk_key)) {
294 * Quirk is on when TSX is not enabled. Therefore TSX
295 * flags must be read as OFF.
297 val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT);
302 static inline void wrlbr_from(unsigned int idx, u64 val)
304 val = lbr_from_signext_quirk_wr(val);
305 wrmsrl(x86_pmu.lbr_from + idx, val);
308 static inline void wrlbr_to(unsigned int idx, u64 val)
310 wrmsrl(x86_pmu.lbr_to + idx, val);
313 static inline u64 rdlbr_from(unsigned int idx)
317 rdmsrl(x86_pmu.lbr_from + idx, val);
319 return lbr_from_signext_quirk_rd(val);
322 static inline u64 rdlbr_to(unsigned int idx)
326 rdmsrl(x86_pmu.lbr_to + idx, val);
331 static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
334 unsigned lbr_idx, mask;
337 if (task_ctx->lbr_callstack_users == 0 ||
338 task_ctx->lbr_stack_state == LBR_NONE) {
339 intel_pmu_lbr_reset();
343 mask = x86_pmu.lbr_nr - 1;
345 for (i = 0; i < tos; i++) {
346 lbr_idx = (tos - i) & mask;
347 wrlbr_from(lbr_idx, task_ctx->lbr_from[i]);
348 wrlbr_to (lbr_idx, task_ctx->lbr_to[i]);
350 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
351 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
353 wrmsrl(x86_pmu.lbr_tos, tos);
354 task_ctx->lbr_stack_state = LBR_NONE;
357 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
359 unsigned lbr_idx, mask;
363 if (task_ctx->lbr_callstack_users == 0) {
364 task_ctx->lbr_stack_state = LBR_NONE;
368 mask = x86_pmu.lbr_nr - 1;
369 tos = intel_pmu_lbr_tos();
370 for (i = 0; i < tos; i++) {
371 lbr_idx = (tos - i) & mask;
372 task_ctx->lbr_from[i] = rdlbr_from(lbr_idx);
373 task_ctx->lbr_to[i] = rdlbr_to(lbr_idx);
374 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
375 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
378 task_ctx->lbr_stack_state = LBR_VALID;
381 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
383 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
384 struct x86_perf_task_context *task_ctx;
387 * If LBR callstack feature is enabled and the stack was saved when
388 * the task was scheduled out, restore the stack. Otherwise flush
391 task_ctx = ctx ? ctx->task_ctx_data : NULL;
394 __intel_pmu_lbr_restore(task_ctx);
395 cpuc->lbr_context = ctx;
397 __intel_pmu_lbr_save(task_ctx);
403 * When sampling the branck stack in system-wide, it may be
404 * necessary to flush the stack on context switch. This happens
405 * when the branch stack does not tag its entries with the pid
406 * of the current task. Otherwise it becomes impossible to
407 * associate a branch entry with a task. This ambiguity is more
408 * likely to appear when the branch stack supports priv level
409 * filtering and the user sets it to monitor only at the user
410 * level (which could be a useful measurement in system-wide
411 * mode). In that case, the risk is high of having a branch
412 * stack with branch from multiple tasks.
415 intel_pmu_lbr_reset();
416 cpuc->lbr_context = ctx;
420 static inline bool branch_user_callstack(unsigned br_sel)
422 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK);
425 void intel_pmu_lbr_enable(struct perf_event *event)
427 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
428 struct x86_perf_task_context *task_ctx;
434 * Reset the LBR stack if we changed task context to
437 if (event->ctx->task && cpuc->lbr_context != event->ctx) {
438 intel_pmu_lbr_reset();
439 cpuc->lbr_context = event->ctx;
441 cpuc->br_sel = event->hw.branch_reg.reg;
443 if (branch_user_callstack(cpuc->br_sel) && event->ctx &&
444 event->ctx->task_ctx_data) {
445 task_ctx = event->ctx->task_ctx_data;
446 task_ctx->lbr_callstack_users++;
450 perf_sched_cb_inc(event->ctx->pmu);
453 void intel_pmu_lbr_disable(struct perf_event *event)
455 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
456 struct x86_perf_task_context *task_ctx;
461 if (branch_user_callstack(cpuc->br_sel) && event->ctx &&
462 event->ctx->task_ctx_data) {
463 task_ctx = event->ctx->task_ctx_data;
464 task_ctx->lbr_callstack_users--;
468 WARN_ON_ONCE(cpuc->lbr_users < 0);
469 perf_sched_cb_dec(event->ctx->pmu);
471 if (cpuc->enabled && !cpuc->lbr_users) {
472 __intel_pmu_lbr_disable();
473 /* avoid stale pointer */
474 cpuc->lbr_context = NULL;
478 void intel_pmu_lbr_enable_all(bool pmi)
480 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
483 __intel_pmu_lbr_enable(pmi);
486 void intel_pmu_lbr_disable_all(void)
488 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
491 __intel_pmu_lbr_disable();
494 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
496 unsigned long mask = x86_pmu.lbr_nr - 1;
497 u64 tos = intel_pmu_lbr_tos();
500 for (i = 0; i < x86_pmu.lbr_nr; i++) {
501 unsigned long lbr_idx = (tos - i) & mask;
510 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
512 cpuc->lbr_entries[i].from = msr_lastbranch.from;
513 cpuc->lbr_entries[i].to = msr_lastbranch.to;
514 cpuc->lbr_entries[i].mispred = 0;
515 cpuc->lbr_entries[i].predicted = 0;
516 cpuc->lbr_entries[i].reserved = 0;
518 cpuc->lbr_stack.nr = i;
522 * Due to lack of segmentation in Linux the effective address (offset)
523 * is the same as the linear address, allowing us to merge the LIP and EIP
526 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
528 bool need_info = false;
529 unsigned long mask = x86_pmu.lbr_nr - 1;
530 int lbr_format = x86_pmu.intel_cap.lbr_format;
531 u64 tos = intel_pmu_lbr_tos();
534 int num = x86_pmu.lbr_nr;
537 need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
538 if (cpuc->lbr_sel->config & LBR_CALL_STACK)
542 for (i = 0; i < num; i++) {
543 unsigned long lbr_idx = (tos - i) & mask;
544 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
547 int lbr_flags = lbr_desc[lbr_format];
549 from = rdlbr_from(lbr_idx);
550 to = rdlbr_to(lbr_idx);
552 if (lbr_format == LBR_FORMAT_INFO && need_info) {
555 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info);
556 mis = !!(info & LBR_INFO_MISPRED);
558 in_tx = !!(info & LBR_INFO_IN_TX);
559 abort = !!(info & LBR_INFO_ABORT);
560 cycles = (info & LBR_INFO_CYCLES);
563 if (lbr_format == LBR_FORMAT_TIME) {
564 mis = !!(from & LBR_FROM_FLAG_MISPRED);
567 cycles = ((to >> 48) & LBR_INFO_CYCLES);
569 to = (u64)((((s64)to) << 16) >> 16);
572 if (lbr_flags & LBR_EIP_FLAGS) {
573 mis = !!(from & LBR_FROM_FLAG_MISPRED);
577 if (lbr_flags & LBR_TSX) {
578 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
579 abort = !!(from & LBR_FROM_FLAG_ABORT);
582 from = (u64)((((s64)from) << skip) >> skip);
585 * Some CPUs report duplicated abort records,
586 * with the second entry not having an abort bit set.
587 * Skip them here. This loop runs backwards,
588 * so we need to undo the previous record.
589 * If the abort just happened outside the window
590 * the extra entry cannot be removed.
592 if (abort && x86_pmu.lbr_double_abort && out > 0)
595 cpuc->lbr_entries[out].from = from;
596 cpuc->lbr_entries[out].to = to;
597 cpuc->lbr_entries[out].mispred = mis;
598 cpuc->lbr_entries[out].predicted = pred;
599 cpuc->lbr_entries[out].in_tx = in_tx;
600 cpuc->lbr_entries[out].abort = abort;
601 cpuc->lbr_entries[out].cycles = cycles;
602 cpuc->lbr_entries[out].reserved = 0;
605 cpuc->lbr_stack.nr = out;
608 void intel_pmu_lbr_read(void)
610 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
612 if (!cpuc->lbr_users)
615 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
616 intel_pmu_lbr_read_32(cpuc);
618 intel_pmu_lbr_read_64(cpuc);
620 intel_pmu_lbr_filter(cpuc);
625 * - in case there is no HW filter
626 * - in case the HW filter has errata or limitations
628 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
630 u64 br_type = event->attr.branch_sample_type;
633 if (br_type & PERF_SAMPLE_BRANCH_USER)
636 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
637 mask |= X86_BR_KERNEL;
639 /* we ignore BRANCH_HV here */
641 if (br_type & PERF_SAMPLE_BRANCH_ANY)
644 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
645 mask |= X86_BR_ANY_CALL;
647 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
648 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
650 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
651 mask |= X86_BR_IND_CALL;
653 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
654 mask |= X86_BR_ABORT;
656 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
657 mask |= X86_BR_IN_TX;
659 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
660 mask |= X86_BR_NO_TX;
662 if (br_type & PERF_SAMPLE_BRANCH_COND)
665 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) {
666 if (!x86_pmu_has_lbr_callstack())
668 if (mask & ~(X86_BR_USER | X86_BR_KERNEL))
670 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET |
674 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP)
675 mask |= X86_BR_IND_JMP;
677 if (br_type & PERF_SAMPLE_BRANCH_CALL)
678 mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
680 * stash actual user request into reg, it may
681 * be used by fixup code for some CPU
683 event->hw.branch_reg.reg = mask;
688 * setup the HW LBR filter
689 * Used only when available, may not be enough to disambiguate
690 * all branches, may need the help of the SW filter
692 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
694 struct hw_perf_event_extra *reg;
695 u64 br_type = event->attr.branch_sample_type;
699 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
700 if (!(br_type & (1ULL << i)))
703 v = x86_pmu.lbr_sel_map[i];
704 if (v == LBR_NOT_SUPP)
711 reg = &event->hw.branch_reg;
712 reg->idx = EXTRA_REG_LBR;
715 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
716 * in suppress mode. So LBR_SELECT should be set to
717 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
718 * But the 10th bit LBR_CALL_STACK does not operate
721 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
723 if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
724 (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
725 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO))
726 reg->config |= LBR_NO_INFO;
731 int intel_pmu_setup_lbr_filter(struct perf_event *event)
742 * setup SW LBR filter
744 ret = intel_pmu_setup_sw_lbr_filter(event);
749 * setup HW LBR filter, if any
751 if (x86_pmu.lbr_sel_map)
752 ret = intel_pmu_setup_hw_lbr_filter(event);
758 * return the type of control flow change at address "from"
759 * instruction is not necessarily a branch (in case of interrupt).
761 * The branch type returned also includes the priv level of the
762 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
764 * If a branch type is unknown OR the instruction cannot be
765 * decoded (e.g., text page not present), then X86_BR_NONE is
768 static int branch_type(unsigned long from, unsigned long to, int abort)
772 int bytes_read, bytes_left;
773 int ret = X86_BR_NONE;
774 int ext, to_plm, from_plm;
775 u8 buf[MAX_INSN_SIZE];
778 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
779 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
782 * maybe zero if lbr did not fill up after a reset by the time
783 * we get a PMU interrupt
785 if (from == 0 || to == 0)
789 return X86_BR_ABORT | to_plm;
791 if (from_plm == X86_BR_USER) {
793 * can happen if measuring at the user level only
794 * and we interrupt in a kernel thread, e.g., idle.
799 /* may fail if text not present */
800 bytes_left = copy_from_user_nmi(buf, (void __user *)from,
802 bytes_read = MAX_INSN_SIZE - bytes_left;
809 * The LBR logs any address in the IP, even if the IP just
810 * faulted. This means userspace can control the from address.
811 * Ensure we don't blindy read any address by validating it is
812 * a known text address.
814 if (kernel_text_address(from)) {
817 * Assume we can get the maximum possible size
818 * when grabbing kernel data. This is not
819 * _strictly_ true since we could possibly be
820 * executing up next to a memory hole, but
821 * it is very unlikely to be a problem.
823 bytes_read = MAX_INSN_SIZE;
830 * decoder needs to know the ABI especially
831 * on 64-bit systems running 32-bit apps
834 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
836 insn_init(&insn, addr, bytes_read, is64);
837 insn_get_opcode(&insn);
838 if (!insn.opcode.got)
841 switch (insn.opcode.bytes[0]) {
843 switch (insn.opcode.bytes[1]) {
844 case 0x05: /* syscall */
845 case 0x34: /* sysenter */
846 ret = X86_BR_SYSCALL;
848 case 0x07: /* sysret */
849 case 0x35: /* sysexit */
852 case 0x80 ... 0x8f: /* conditional */
859 case 0x70 ... 0x7f: /* conditional */
862 case 0xc2: /* near ret */
863 case 0xc3: /* near ret */
864 case 0xca: /* far ret */
865 case 0xcb: /* far ret */
868 case 0xcf: /* iret */
871 case 0xcc ... 0xce: /* int */
874 case 0xe8: /* call near rel */
875 insn_get_immediate(&insn);
876 if (insn.immediate1.value == 0) {
877 /* zero length call */
878 ret = X86_BR_ZERO_CALL;
881 case 0x9a: /* call far absolute */
884 case 0xe0 ... 0xe3: /* loop jmp */
887 case 0xe9 ... 0xeb: /* jmp */
890 case 0xff: /* call near absolute, call far absolute ind */
891 insn_get_modrm(&insn);
892 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
894 case 2: /* near ind call */
895 case 3: /* far ind call */
896 ret = X86_BR_IND_CALL;
900 ret = X86_BR_IND_JMP;
908 * interrupts, traps, faults (and thus ring transition) may
909 * occur on any instructions. Thus, to classify them correctly,
910 * we need to first look at the from and to priv levels. If they
911 * are different and to is in the kernel, then it indicates
912 * a ring transition. If the from instruction is not a ring
913 * transition instr (syscall, systenter, int), then it means
914 * it was a irq, trap or fault.
916 * we have no way of detecting kernel to kernel faults.
918 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
919 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
923 * branch priv level determined by target as
924 * is done by HW when LBR_SELECT is implemented
926 if (ret != X86_BR_NONE)
933 * implement actual branch filter based on user demand.
934 * Hardware may not exactly satisfy that request, thus
935 * we need to inspect opcodes. Mismatched branches are
936 * discarded. Therefore, the number of branches returned
937 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
940 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
943 int br_sel = cpuc->br_sel;
945 bool compress = false;
947 /* if sampling all branches, then nothing to filter */
948 if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
951 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
953 from = cpuc->lbr_entries[i].from;
954 to = cpuc->lbr_entries[i].to;
956 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
957 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
958 if (cpuc->lbr_entries[i].in_tx)
959 type |= X86_BR_IN_TX;
961 type |= X86_BR_NO_TX;
964 /* if type does not correspond, then discard */
965 if (type == X86_BR_NONE || (br_sel & type) != type) {
966 cpuc->lbr_entries[i].from = 0;
974 /* remove all entries with from=0 */
975 for (i = 0; i < cpuc->lbr_stack.nr; ) {
976 if (!cpuc->lbr_entries[i].from) {
978 while (++j < cpuc->lbr_stack.nr)
979 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
980 cpuc->lbr_stack.nr--;
981 if (!cpuc->lbr_entries[i].from)
989 * Map interface branch filters onto LBR filters
991 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
992 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
993 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
994 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
995 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
996 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP
997 | LBR_IND_JMP | LBR_FAR,
999 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
1001 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] =
1002 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
1004 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
1006 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP,
1007 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1008 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1011 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1012 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1013 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1014 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1015 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1016 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1017 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1019 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1020 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1021 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1022 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1025 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1026 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1027 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1028 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1029 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1030 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1031 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1033 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1034 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1035 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1036 | LBR_RETURN | LBR_CALL_STACK,
1037 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1038 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1042 void __init intel_pmu_lbr_init_core(void)
1045 x86_pmu.lbr_tos = MSR_LBR_TOS;
1046 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1047 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1050 * SW branch filter usage:
1051 * - compensate for lack of HW filter
1055 /* nehalem/westmere */
1056 void __init intel_pmu_lbr_init_nhm(void)
1058 x86_pmu.lbr_nr = 16;
1059 x86_pmu.lbr_tos = MSR_LBR_TOS;
1060 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1061 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1063 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1064 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1067 * SW branch filter usage:
1068 * - workaround LBR_SEL errata (see above)
1069 * - support syscall, sysret capture.
1070 * That requires LBR_FAR but that means far
1071 * jmp need to be filtered out
1076 void __init intel_pmu_lbr_init_snb(void)
1078 x86_pmu.lbr_nr = 16;
1079 x86_pmu.lbr_tos = MSR_LBR_TOS;
1080 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1081 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1083 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1084 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1087 * SW branch filter usage:
1088 * - support syscall, sysret capture.
1089 * That requires LBR_FAR but that means far
1090 * jmp need to be filtered out
1095 void intel_pmu_lbr_init_hsw(void)
1097 x86_pmu.lbr_nr = 16;
1098 x86_pmu.lbr_tos = MSR_LBR_TOS;
1099 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1100 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1102 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1103 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1105 if (lbr_from_signext_quirk_needed())
1106 static_branch_enable(&lbr_from_quirk_key);
1110 __init void intel_pmu_lbr_init_skl(void)
1112 x86_pmu.lbr_nr = 32;
1113 x86_pmu.lbr_tos = MSR_LBR_TOS;
1114 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1115 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1117 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1118 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1121 * SW branch filter usage:
1122 * - support syscall, sysret capture.
1123 * That requires LBR_FAR but that means far
1124 * jmp need to be filtered out
1129 void __init intel_pmu_lbr_init_atom(void)
1132 * only models starting at stepping 10 seems
1133 * to have an operational LBR which can freeze
1136 if (boot_cpu_data.x86_model == 28
1137 && boot_cpu_data.x86_mask < 10) {
1138 pr_cont("LBR disabled due to erratum");
1143 x86_pmu.lbr_tos = MSR_LBR_TOS;
1144 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1145 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1148 * SW branch filter usage:
1149 * - compensate for lack of HW filter
1154 void __init intel_pmu_lbr_init_slm(void)
1157 x86_pmu.lbr_tos = MSR_LBR_TOS;
1158 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1159 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1161 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1162 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1165 * SW branch filter usage:
1166 * - compensate for lack of HW filter
1168 pr_cont("8-deep LBR, ");
1171 /* Knights Landing */
1172 void intel_pmu_lbr_init_knl(void)
1175 x86_pmu.lbr_tos = MSR_LBR_TOS;
1176 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1177 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1179 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1180 x86_pmu.lbr_sel_map = snb_lbr_sel_map;