2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV architectural definitions
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
15 #include <linux/numa.h>
16 #include <linux/percpu.h>
17 #include <linux/timer.h>
19 #include <asm/types.h>
20 #include <asm/percpu.h>
21 #include <asm/uv/uv_mmrs.h>
25 * Addressing Terminology
27 * M - The low M bits of a physical address represent the offset
28 * into the blade local memory. RAM memory on a blade is physically
29 * contiguous (although various IO spaces may punch holes in
32 * N - Number of bits in the node portion of a socket physical
35 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
36 * routers always have low bit of 1, C/MBricks have low bit
37 * equal to 0. Most addressing macros that target UV hub chips
38 * right shift the NASID by 1 to exclude the always-zero bit.
39 * NASIDs contain up to 15 bits.
41 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
44 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * of the nasid for socket usage.
48 * NumaLink Global Physical Address Format:
49 * +--------------------------------+---------------------+
50 * |00..000| GNODE | NodeOffset |
51 * +--------------------------------+---------------------+
52 * |<-------53 - M bits --->|<--------M bits ----->
54 * M - number of node offset bits (35 .. 40)
57 * Memory/UV-HUB Processor Socket Address Format:
58 * +----------------+---------------+---------------------+
59 * |00..000000000000| PNODE | NodeOffset |
60 * +----------------+---------------+---------------------+
61 * <--- N bits --->|<--------M bits ----->
63 * M - number of node offset bits (35 .. 40)
64 * N - number of PNODE bits (0 .. 10)
66 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
67 * The actual values are configuration dependent and are set at
68 * boot time. M & N values are set by the hardware/BIOS at boot.
72 * NOTE!!!!!! This is the current format of the APICID. However, code
73 * should assume that this will change in the future. Use functions
74 * in this file for all APICID bit manipulations and conversion.
82 * l = socket number on board
85 * s = bits that are in the SOCKET_ID CSR
87 * Note: Processor only supports 12 bits in the APICID register. The ACPI
88 * tables hold all 16 bits. Software needs to be aware of this.
90 * Unless otherwise specified, all references to APICID refer to
91 * the FULL value contained in ACPI tables, not the subset in the
92 * processor APICID register.
97 * Maximum number of bricks in all partitions and in all coherency domains.
98 * This is the total number of bricks accessible in the numalink fabric. It
99 * includes all C & M bricks. Routers are NOT included.
101 * This value is also the value of the maximum number of non-router NASIDs
102 * in the numalink fabric.
104 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
106 #define UV_MAX_NUMALINK_BLADES 16384
109 * Maximum number of C/Mbricks within a software SSI (hardware may support
112 #define UV_MAX_SSI_BLADES 256
115 * The largest possible NASID of a C or M brick (+ 2)
117 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
120 struct timer_list timer;
121 unsigned long offset;
123 unsigned long idle_on;
124 unsigned long idle_off;
126 unsigned char enabled;
130 * The following defines attributes of the HUB chip. These attributes are
131 * frequently referenced and are kept in the per-cpu data areas of each cpu.
132 * They are kept together in a struct to minimize cache misses.
134 struct uv_hub_info_s {
135 unsigned long global_mmr_base;
136 unsigned long gpa_mask;
137 unsigned int gnode_extra;
138 unsigned long gnode_upper;
139 unsigned long lowmem_remap_top;
140 unsigned long lowmem_remap_base;
141 unsigned short pnode;
142 unsigned short pnode_mask;
143 unsigned short coherency_domain_number;
144 unsigned short numa_blade_id;
145 unsigned char blade_processor_id;
148 struct uv_scir_s scir;
151 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
152 #define uv_hub_info (&__get_cpu_var(__uv_hub_info))
153 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
156 * Local & Global MMR space macros.
157 * Note: macros are intended to be used ONLY by inline functions
158 * in this file - not by other kernel code.
159 * n - NASID (full 15-bit global nasid)
160 * g - GNODE (full 15-bit global nasid, right shifted 1)
161 * p - PNODE (local part of nsids, right shifted 1)
163 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
164 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
165 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
167 #define UV_LOCAL_MMR_BASE 0xf4000000UL
168 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL
169 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
170 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
171 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
173 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
174 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26
176 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
178 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \
179 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
181 #define UV_APIC_PNODE_SHIFT 6
183 /* Local Bus from cpu's perspective */
184 #define LOCAL_BUS_BASE 0x1c00000
185 #define LOCAL_BUS_SIZE (4 * 1024 * 1024)
188 * System Controller Interface Reg
190 * Note there are NO leds on a UV system. This register is only
191 * used by the system controller to monitor system-wide operation.
192 * There are 64 regs per node. With Nahelem cpus (2 cores per node,
193 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
196 * The window is located at top of ACPI MMR space
198 #define SCIR_WINDOW_COUNT 64
199 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
203 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
204 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */
205 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
207 /* Loop through all installed blades */
208 #define for_each_possible_blade(bid) \
209 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
212 * Macros for converting between kernel virtual addresses, socket local physical
213 * addresses, and UV global physical addresses.
214 * Note: use the standard __pa() & __va() macros for converting
215 * between socket virtual and socket physical addresses.
218 /* socket phys RAM --> UV global physical address */
219 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
221 if (paddr < uv_hub_info->lowmem_remap_top)
222 paddr |= uv_hub_info->lowmem_remap_base;
223 return paddr | uv_hub_info->gnode_upper;
227 /* socket virtual --> UV global physical address */
228 static inline unsigned long uv_gpa(void *v)
230 return uv_soc_phys_ram_to_gpa(__pa(v));
234 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
236 return gpa >> uv_hub_info->m_val;
240 static inline int uv_gpa_to_pnode(unsigned long gpa)
242 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
244 return uv_gpa_to_gnode(gpa) & n_mask;
247 /* pnode, offset --> socket virtual */
248 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
250 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
255 * Extract a PNODE from an APICID (full apicid, not processor subset)
257 static inline int uv_apicid_to_pnode(int apicid)
259 return (apicid >> UV_APIC_PNODE_SHIFT);
263 * Access global MMRs using the low memory MMR32 space. This region supports
264 * faster MMR access but not all MMRs are accessible in this space.
266 static inline unsigned long *uv_global_mmr32_address(int pnode,
267 unsigned long offset)
269 return __va(UV_GLOBAL_MMR32_BASE |
270 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
273 static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
276 writeq(val, uv_global_mmr32_address(pnode, offset));
279 static inline unsigned long uv_read_global_mmr32(int pnode,
280 unsigned long offset)
282 return readq(uv_global_mmr32_address(pnode, offset));
286 * Access Global MMR space using the MMR space located at the top of physical
289 static inline unsigned long *uv_global_mmr64_address(int pnode,
290 unsigned long offset)
292 return __va(UV_GLOBAL_MMR64_BASE |
293 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
296 static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
299 writeq(val, uv_global_mmr64_address(pnode, offset));
302 static inline unsigned long uv_read_global_mmr64(int pnode,
303 unsigned long offset)
305 return readq(uv_global_mmr64_address(pnode, offset));
309 * Access hub local MMRs. Faster than using global space but only local MMRs
312 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
314 return __va(UV_LOCAL_MMR_BASE | offset);
317 static inline unsigned long uv_read_local_mmr(unsigned long offset)
319 return readq(uv_local_mmr_address(offset));
322 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
324 writeq(val, uv_local_mmr_address(offset));
327 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
329 return readb(uv_local_mmr_address(offset));
332 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
334 writeb(val, uv_local_mmr_address(offset));
338 * Structures and definitions for converting between cpu, node, pnode, and blade
341 struct uv_blade_info {
342 unsigned short nr_possible_cpus;
343 unsigned short nr_online_cpus;
344 unsigned short pnode;
347 extern struct uv_blade_info *uv_blade_info;
348 extern short *uv_node_to_blade;
349 extern short *uv_cpu_to_blade;
350 extern short uv_possible_blades;
352 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
353 static inline int uv_blade_processor_id(void)
355 return uv_hub_info->blade_processor_id;
358 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
359 static inline int uv_numa_blade_id(void)
361 return uv_hub_info->numa_blade_id;
364 /* Convert a cpu number to the the UV blade number */
365 static inline int uv_cpu_to_blade_id(int cpu)
367 return uv_cpu_to_blade[cpu];
370 /* Convert linux node number to the UV blade number */
371 static inline int uv_node_to_blade_id(int nid)
373 return uv_node_to_blade[nid];
376 /* Convert a blade id to the PNODE of the blade */
377 static inline int uv_blade_to_pnode(int bid)
379 return uv_blade_info[bid].pnode;
382 /* Nid of memory node on blade. -1 if no blade-local memory */
383 static inline int uv_blade_to_memory_nid(int bid)
385 return uv_blade_info[bid].memory_nid;
388 /* Determine the number of possible cpus on a blade */
389 static inline int uv_blade_nr_possible_cpus(int bid)
391 return uv_blade_info[bid].nr_possible_cpus;
394 /* Determine the number of online cpus on a blade */
395 static inline int uv_blade_nr_online_cpus(int bid)
397 return uv_blade_info[bid].nr_online_cpus;
400 /* Convert a cpu id to the PNODE of the blade containing the cpu */
401 static inline int uv_cpu_to_pnode(int cpu)
403 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
406 /* Convert a linux node number to the PNODE of the blade */
407 static inline int uv_node_to_pnode(int nid)
409 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
412 /* Maximum possible number of blades */
413 static inline int uv_num_possible_blades(void)
415 return uv_possible_blades;
418 /* Update SCIR state */
419 static inline void uv_set_scir_bits(unsigned char value)
421 if (uv_hub_info->scir.state != value) {
422 uv_hub_info->scir.state = value;
423 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
427 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
429 if (uv_cpu_hub_info(cpu)->scir.state != value) {
430 uv_cpu_hub_info(cpu)->scir.state = value;
431 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
435 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
439 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
440 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
441 (vector << UVH_IPI_INT_VECTOR_SHFT);
442 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
445 #endif /* CONFIG_X86_64 */
446 #endif /* _ASM_X86_UV_UV_HUB_H */