2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
62 unsigned long start_page,
64 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
66 #ifndef BUS_NOTIFY_UNBOUND_DRIVER
67 #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
70 #ifdef CONFIG_AMD_IOMMU_STATS
73 * Initialization code for statistics collection
76 DECLARE_STATS_COUNTER(compl_wait);
77 DECLARE_STATS_COUNTER(cnt_map_single);
78 DECLARE_STATS_COUNTER(cnt_unmap_single);
79 DECLARE_STATS_COUNTER(cnt_map_sg);
80 DECLARE_STATS_COUNTER(cnt_unmap_sg);
81 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
82 DECLARE_STATS_COUNTER(cnt_free_coherent);
83 DECLARE_STATS_COUNTER(cross_page);
84 DECLARE_STATS_COUNTER(domain_flush_single);
85 DECLARE_STATS_COUNTER(domain_flush_all);
86 DECLARE_STATS_COUNTER(alloced_io_mem);
87 DECLARE_STATS_COUNTER(total_map_requests);
89 static struct dentry *stats_dir;
90 static struct dentry *de_isolate;
91 static struct dentry *de_fflush;
93 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
95 if (stats_dir == NULL)
98 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
102 static void amd_iommu_stats_init(void)
104 stats_dir = debugfs_create_dir("amd-iommu", NULL);
105 if (stats_dir == NULL)
108 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
109 (u32 *)&amd_iommu_isolate);
111 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
112 (u32 *)&amd_iommu_unmap_flush);
114 amd_iommu_stats_add(&compl_wait);
115 amd_iommu_stats_add(&cnt_map_single);
116 amd_iommu_stats_add(&cnt_unmap_single);
117 amd_iommu_stats_add(&cnt_map_sg);
118 amd_iommu_stats_add(&cnt_unmap_sg);
119 amd_iommu_stats_add(&cnt_alloc_coherent);
120 amd_iommu_stats_add(&cnt_free_coherent);
121 amd_iommu_stats_add(&cross_page);
122 amd_iommu_stats_add(&domain_flush_single);
123 amd_iommu_stats_add(&domain_flush_all);
124 amd_iommu_stats_add(&alloced_io_mem);
125 amd_iommu_stats_add(&total_map_requests);
130 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
131 static int iommu_has_npcache(struct amd_iommu *iommu)
133 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
136 /****************************************************************************
138 * Interrupt handling functions
140 ****************************************************************************/
142 static void dump_dte_entry(u16 devid)
146 for (i = 0; i < 8; ++i)
147 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
148 amd_iommu_dev_table[devid].data[i]);
151 static void dump_command(unsigned long phys_addr)
153 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
156 for (i = 0; i < 4; ++i)
157 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
160 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
163 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
164 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
165 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
166 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
167 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
169 printk(KERN_ERR "AMD IOMMU: Event logged [");
172 case EVENT_TYPE_ILL_DEV:
173 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
174 "address=0x%016llx flags=0x%04x]\n",
175 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
177 dump_dte_entry(devid);
179 case EVENT_TYPE_IO_FAULT:
180 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
181 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
182 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
183 domid, address, flags);
185 case EVENT_TYPE_DEV_TAB_ERR:
186 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
187 "address=0x%016llx flags=0x%04x]\n",
188 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
191 case EVENT_TYPE_PAGE_TAB_ERR:
192 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
193 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
194 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
195 domid, address, flags);
197 case EVENT_TYPE_ILL_CMD:
198 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
199 reset_iommu_command_buffer(iommu);
200 dump_command(address);
202 case EVENT_TYPE_CMD_HARD_ERR:
203 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
204 "flags=0x%04x]\n", address, flags);
206 case EVENT_TYPE_IOTLB_INV_TO:
207 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
208 "address=0x%016llx]\n",
209 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
212 case EVENT_TYPE_INV_DEV_REQ:
213 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
214 "address=0x%016llx flags=0x%04x]\n",
215 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
219 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
223 static void iommu_poll_events(struct amd_iommu *iommu)
228 spin_lock_irqsave(&iommu->lock, flags);
230 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
231 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
233 while (head != tail) {
234 iommu_print_event(iommu, iommu->evt_buf + head);
235 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
238 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
240 spin_unlock_irqrestore(&iommu->lock, flags);
243 irqreturn_t amd_iommu_int_handler(int irq, void *data)
245 struct amd_iommu *iommu;
247 for_each_iommu(iommu)
248 iommu_poll_events(iommu);
253 /****************************************************************************
255 * IOMMU command queuing functions
257 ****************************************************************************/
260 * Writes the command to the IOMMUs command buffer and informs the
261 * hardware about the new command. Must be called with iommu->lock held.
263 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
268 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
269 target = iommu->cmd_buf + tail;
270 memcpy_toio(target, cmd, sizeof(*cmd));
271 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
272 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
275 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
281 * General queuing function for commands. Takes iommu->lock and calls
282 * __iommu_queue_command().
284 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
289 spin_lock_irqsave(&iommu->lock, flags);
290 ret = __iommu_queue_command(iommu, cmd);
292 iommu->need_sync = true;
293 spin_unlock_irqrestore(&iommu->lock, flags);
299 * This function waits until an IOMMU has completed a completion
302 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
308 INC_STATS_COUNTER(compl_wait);
310 while (!ready && (i < EXIT_LOOP_COUNT)) {
312 /* wait for the bit to become one */
313 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
314 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
317 /* set bit back to zero */
318 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
319 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
321 if (unlikely(i == EXIT_LOOP_COUNT)) {
322 spin_unlock(&iommu->lock);
323 reset_iommu_command_buffer(iommu);
324 spin_lock(&iommu->lock);
329 * This function queues a completion wait command into the command
332 static int __iommu_completion_wait(struct amd_iommu *iommu)
334 struct iommu_cmd cmd;
336 memset(&cmd, 0, sizeof(cmd));
337 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
338 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
340 return __iommu_queue_command(iommu, &cmd);
344 * This function is called whenever we need to ensure that the IOMMU has
345 * completed execution of all commands we sent. It sends a
346 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
347 * us about that by writing a value to a physical address we pass with
350 static int iommu_completion_wait(struct amd_iommu *iommu)
355 spin_lock_irqsave(&iommu->lock, flags);
357 if (!iommu->need_sync)
360 ret = __iommu_completion_wait(iommu);
362 iommu->need_sync = false;
367 __iommu_wait_for_completion(iommu);
370 spin_unlock_irqrestore(&iommu->lock, flags);
376 * Command send function for invalidating a device table entry
378 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
380 struct iommu_cmd cmd;
383 BUG_ON(iommu == NULL);
385 memset(&cmd, 0, sizeof(cmd));
386 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
389 ret = iommu_queue_command(iommu, &cmd);
394 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
395 u16 domid, int pde, int s)
397 memset(cmd, 0, sizeof(*cmd));
398 address &= PAGE_MASK;
399 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
400 cmd->data[1] |= domid;
401 cmd->data[2] = lower_32_bits(address);
402 cmd->data[3] = upper_32_bits(address);
403 if (s) /* size bit - we flush more than one 4kb page */
404 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
405 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
406 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
410 * Generic command send function for invalidaing TLB entries
412 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
413 u64 address, u16 domid, int pde, int s)
415 struct iommu_cmd cmd;
418 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
420 ret = iommu_queue_command(iommu, &cmd);
426 * TLB invalidation function which is called from the mapping functions.
427 * It invalidates a single PTE if the range to flush is within a single
428 * page. Otherwise it flushes the whole TLB of the IOMMU.
430 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
431 u64 address, size_t size)
434 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
436 address &= PAGE_MASK;
440 * If we have to flush more than one page, flush all
441 * TLB entries for this domain
443 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
447 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
452 /* Flush the whole IO/TLB for a given protection domain */
453 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
455 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
457 INC_STATS_COUNTER(domain_flush_single);
459 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
462 /* Flush the whole IO/TLB for a given protection domain - including PDE */
463 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
465 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
467 INC_STATS_COUNTER(domain_flush_single);
469 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
473 * This function flushes one domain on one IOMMU
475 static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid)
477 struct iommu_cmd cmd;
480 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
483 spin_lock_irqsave(&iommu->lock, flags);
484 __iommu_queue_command(iommu, &cmd);
485 __iommu_completion_wait(iommu);
486 __iommu_wait_for_completion(iommu);
487 spin_unlock_irqrestore(&iommu->lock, flags);
490 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
494 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
495 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
497 flush_domain_on_iommu(iommu, i);
503 * This function is used to flush the IO/TLB for a given protection domain
504 * on every IOMMU in the system
506 static void iommu_flush_domain(u16 domid)
508 struct amd_iommu *iommu;
510 INC_STATS_COUNTER(domain_flush_all);
512 for_each_iommu(iommu)
513 flush_domain_on_iommu(iommu, domid);
516 void amd_iommu_flush_all_domains(void)
518 struct amd_iommu *iommu;
520 for_each_iommu(iommu)
521 flush_all_domains_on_iommu(iommu);
524 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
528 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
529 if (iommu != amd_iommu_rlookup_table[i])
532 iommu_queue_inv_dev_entry(iommu, i);
533 iommu_completion_wait(iommu);
537 void amd_iommu_flush_all_devices(void)
539 struct amd_iommu *iommu;
542 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
543 if (amd_iommu_pd_table[i] == NULL)
546 iommu = amd_iommu_rlookup_table[i];
550 iommu_queue_inv_dev_entry(iommu, i);
551 iommu_completion_wait(iommu);
555 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
557 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
559 if (iommu->reset_in_progress)
560 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
562 iommu->reset_in_progress = true;
564 amd_iommu_reset_cmd_buffer(iommu);
565 flush_all_devices_for_iommu(iommu);
566 flush_all_domains_on_iommu(iommu);
568 iommu->reset_in_progress = false;
571 /****************************************************************************
573 * The functions below are used the create the page table mappings for
574 * unity mapped regions.
576 ****************************************************************************/
579 * Generic mapping functions. It maps a physical address into a DMA
580 * address space. It allocates the page table pages if necessary.
581 * In the future it can be extended to a generic mapping function
582 * supporting all features of AMD IOMMU page tables like level skipping
583 * and full 64 bit address spaces.
585 static int iommu_map_page(struct protection_domain *dom,
586 unsigned long bus_addr,
587 unsigned long phys_addr,
592 bus_addr = PAGE_ALIGN(bus_addr);
593 phys_addr = PAGE_ALIGN(phys_addr);
595 /* only support 512GB address spaces for now */
596 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
599 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
601 if (IOMMU_PTE_PRESENT(*pte))
604 __pte = phys_addr | IOMMU_PTE_P;
605 if (prot & IOMMU_PROT_IR)
606 __pte |= IOMMU_PTE_IR;
607 if (prot & IOMMU_PROT_IW)
608 __pte |= IOMMU_PTE_IW;
615 static void iommu_unmap_page(struct protection_domain *dom,
616 unsigned long bus_addr)
620 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
622 if (!IOMMU_PTE_PRESENT(*pte))
625 pte = IOMMU_PTE_PAGE(*pte);
626 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
628 if (!IOMMU_PTE_PRESENT(*pte))
631 pte = IOMMU_PTE_PAGE(*pte);
632 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
638 * This function checks if a specific unity mapping entry is needed for
639 * this specific IOMMU.
641 static int iommu_for_unity_map(struct amd_iommu *iommu,
642 struct unity_map_entry *entry)
646 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
647 bdf = amd_iommu_alias_table[i];
648 if (amd_iommu_rlookup_table[bdf] == iommu)
656 * Init the unity mappings for a specific IOMMU in the system
658 * Basically iterates over all unity mapping entries and applies them to
659 * the default domain DMA of that IOMMU if necessary.
661 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
663 struct unity_map_entry *entry;
666 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
667 if (!iommu_for_unity_map(iommu, entry))
669 ret = dma_ops_unity_map(iommu->default_dom, entry);
678 * This function actually applies the mapping to the page table of the
681 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
682 struct unity_map_entry *e)
687 for (addr = e->address_start; addr < e->address_end;
689 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
693 * if unity mapping is in aperture range mark the page
694 * as allocated in the aperture
696 if (addr < dma_dom->aperture_size)
697 __set_bit(addr >> PAGE_SHIFT,
698 dma_dom->aperture[0]->bitmap);
705 * Inits the unity mappings required for a specific device
707 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
710 struct unity_map_entry *e;
713 list_for_each_entry(e, &amd_iommu_unity_map, list) {
714 if (!(devid >= e->devid_start && devid <= e->devid_end))
716 ret = dma_ops_unity_map(dma_dom, e);
724 /****************************************************************************
726 * The next functions belong to the address allocator for the dma_ops
727 * interface functions. They work like the allocators in the other IOMMU
728 * drivers. Its basically a bitmap which marks the allocated pages in
729 * the aperture. Maybe it could be enhanced in the future to a more
730 * efficient allocator.
732 ****************************************************************************/
735 * The address allocator core functions.
737 * called with domain->lock held
741 * This function checks if there is a PTE for a given dma address. If
742 * there is one, it returns the pointer to it.
744 static u64* fetch_pte(struct protection_domain *domain,
745 unsigned long address)
749 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
751 if (!IOMMU_PTE_PRESENT(*pte))
754 pte = IOMMU_PTE_PAGE(*pte);
755 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
757 if (!IOMMU_PTE_PRESENT(*pte))
760 pte = IOMMU_PTE_PAGE(*pte);
761 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
767 * This function is used to add a new aperture range to an existing
768 * aperture in case of dma_ops domain allocation or address allocation
771 static int alloc_new_range(struct amd_iommu *iommu,
772 struct dma_ops_domain *dma_dom,
773 bool populate, gfp_t gfp)
775 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
778 #ifdef CONFIG_IOMMU_STRESS
782 if (index >= APERTURE_MAX_RANGES)
785 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
786 if (!dma_dom->aperture[index])
789 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
790 if (!dma_dom->aperture[index]->bitmap)
793 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
796 unsigned long address = dma_dom->aperture_size;
797 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
800 for (i = 0; i < num_ptes; ++i) {
801 pte = alloc_pte(&dma_dom->domain, address,
806 dma_dom->aperture[index]->pte_pages[i] = pte_page;
808 address += APERTURE_RANGE_SIZE / 64;
812 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
814 /* Intialize the exclusion range if necessary */
815 if (iommu->exclusion_start &&
816 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
817 iommu->exclusion_start < dma_dom->aperture_size) {
818 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
819 int pages = iommu_num_pages(iommu->exclusion_start,
820 iommu->exclusion_length,
822 dma_ops_reserve_addresses(dma_dom, startpage, pages);
826 * Check for areas already mapped as present in the new aperture
827 * range and mark those pages as reserved in the allocator. Such
828 * mappings may already exist as a result of requested unity
829 * mappings for devices.
831 for (i = dma_dom->aperture[index]->offset;
832 i < dma_dom->aperture_size;
834 u64 *pte = fetch_pte(&dma_dom->domain, i);
835 if (!pte || !IOMMU_PTE_PRESENT(*pte))
838 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
844 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
846 kfree(dma_dom->aperture[index]);
847 dma_dom->aperture[index] = NULL;
852 static unsigned long dma_ops_area_alloc(struct device *dev,
853 struct dma_ops_domain *dom,
855 unsigned long align_mask,
859 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
860 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
861 int i = start >> APERTURE_RANGE_SHIFT;
862 unsigned long boundary_size;
863 unsigned long address = -1;
866 next_bit >>= PAGE_SHIFT;
868 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
869 PAGE_SIZE) >> PAGE_SHIFT;
871 for (;i < max_index; ++i) {
872 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
874 if (dom->aperture[i]->offset >= dma_mask)
877 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
878 dma_mask >> PAGE_SHIFT);
880 address = iommu_area_alloc(dom->aperture[i]->bitmap,
881 limit, next_bit, pages, 0,
882 boundary_size, align_mask);
884 address = dom->aperture[i]->offset +
885 (address << PAGE_SHIFT);
886 dom->next_address = address + (pages << PAGE_SHIFT);
896 static unsigned long dma_ops_alloc_addresses(struct device *dev,
897 struct dma_ops_domain *dom,
899 unsigned long align_mask,
902 unsigned long address;
904 #ifdef CONFIG_IOMMU_STRESS
905 dom->next_address = 0;
906 dom->need_flush = true;
909 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
910 dma_mask, dom->next_address);
913 dom->next_address = 0;
914 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
916 dom->need_flush = true;
919 if (unlikely(address == -1))
920 address = bad_dma_address;
922 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
928 * The address free function.
930 * called with domain->lock held
932 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
933 unsigned long address,
936 unsigned i = address >> APERTURE_RANGE_SHIFT;
937 struct aperture_range *range = dom->aperture[i];
939 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
941 #ifdef CONFIG_IOMMU_STRESS
946 if (address >= dom->next_address)
947 dom->need_flush = true;
949 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
951 iommu_area_free(range->bitmap, address, pages);
955 /****************************************************************************
957 * The next functions belong to the domain allocation. A domain is
958 * allocated for every IOMMU as the default domain. If device isolation
959 * is enabled, every device get its own domain. The most important thing
960 * about domains is the page table mapping the DMA address space they
963 ****************************************************************************/
965 static u16 domain_id_alloc(void)
970 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
971 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
973 if (id > 0 && id < MAX_DOMAIN_ID)
974 __set_bit(id, amd_iommu_pd_alloc_bitmap);
977 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
982 static void domain_id_free(int id)
986 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
987 if (id > 0 && id < MAX_DOMAIN_ID)
988 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
989 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
993 * Used to reserve address ranges in the aperture (e.g. for exclusion
996 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
997 unsigned long start_page,
1000 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1002 if (start_page + pages > last_page)
1003 pages = last_page - start_page;
1005 for (i = start_page; i < start_page + pages; ++i) {
1006 int index = i / APERTURE_RANGE_PAGES;
1007 int page = i % APERTURE_RANGE_PAGES;
1008 __set_bit(page, dom->aperture[index]->bitmap);
1012 static void free_pagetable(struct protection_domain *domain)
1017 p1 = domain->pt_root;
1022 for (i = 0; i < 512; ++i) {
1023 if (!IOMMU_PTE_PRESENT(p1[i]))
1026 p2 = IOMMU_PTE_PAGE(p1[i]);
1027 for (j = 0; j < 512; ++j) {
1028 if (!IOMMU_PTE_PRESENT(p2[j]))
1030 p3 = IOMMU_PTE_PAGE(p2[j]);
1031 free_page((unsigned long)p3);
1034 free_page((unsigned long)p2);
1037 free_page((unsigned long)p1);
1039 domain->pt_root = NULL;
1043 * Free a domain, only used if something went wrong in the
1044 * allocation path and we need to free an already allocated page table
1046 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1053 free_pagetable(&dom->domain);
1055 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1056 if (!dom->aperture[i])
1058 free_page((unsigned long)dom->aperture[i]->bitmap);
1059 kfree(dom->aperture[i]);
1066 * Allocates a new protection domain usable for the dma_ops functions.
1067 * It also intializes the page table and the address allocator data
1068 * structures required for the dma_ops interface
1070 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1072 struct dma_ops_domain *dma_dom;
1074 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1078 spin_lock_init(&dma_dom->domain.lock);
1080 dma_dom->domain.id = domain_id_alloc();
1081 if (dma_dom->domain.id == 0)
1083 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1084 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1085 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1086 dma_dom->domain.priv = dma_dom;
1087 if (!dma_dom->domain.pt_root)
1090 dma_dom->need_flush = false;
1091 dma_dom->target_dev = 0xffff;
1093 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1097 * mark the first page as allocated so we never return 0 as
1098 * a valid dma-address. So we can use 0 as error value
1100 dma_dom->aperture[0]->bitmap[0] = 1;
1101 dma_dom->next_address = 0;
1107 dma_ops_domain_free(dma_dom);
1113 * little helper function to check whether a given protection domain is a
1116 static bool dma_ops_domain(struct protection_domain *domain)
1118 return domain->flags & PD_DMA_OPS_MASK;
1122 * Find out the protection domain structure for a given PCI device. This
1123 * will give us the pointer to the page table root for example.
1125 static struct protection_domain *domain_for_device(u16 devid)
1127 struct protection_domain *dom;
1128 unsigned long flags;
1130 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1131 dom = amd_iommu_pd_table[devid];
1132 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1138 * If a device is not yet associated with a domain, this function does
1139 * assigns it visible for the hardware
1141 static void attach_device(struct amd_iommu *iommu,
1142 struct protection_domain *domain,
1145 unsigned long flags;
1146 u64 pte_root = virt_to_phys(domain->pt_root);
1148 domain->dev_cnt += 1;
1150 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1151 << DEV_ENTRY_MODE_SHIFT;
1152 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1154 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1155 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1156 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1157 amd_iommu_dev_table[devid].data[2] = domain->id;
1159 amd_iommu_pd_table[devid] = domain;
1160 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1163 * We might boot into a crash-kernel here. The crashed kernel
1164 * left the caches in the IOMMU dirty. So we have to flush
1165 * here to evict all dirty stuff.
1167 iommu_queue_inv_dev_entry(iommu, devid);
1168 iommu_flush_tlb_pde(iommu, domain->id);
1172 * Removes a device from a protection domain (unlocked)
1174 static void __detach_device(struct protection_domain *domain, u16 devid)
1178 spin_lock(&domain->lock);
1180 /* remove domain from the lookup table */
1181 amd_iommu_pd_table[devid] = NULL;
1183 /* remove entry from the device table seen by the hardware */
1184 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1185 amd_iommu_dev_table[devid].data[1] = 0;
1186 amd_iommu_dev_table[devid].data[2] = 0;
1188 /* decrease reference counter */
1189 domain->dev_cnt -= 1;
1192 spin_unlock(&domain->lock);
1196 * Removes a device from a protection domain (with devtable_lock held)
1198 static void detach_device(struct protection_domain *domain, u16 devid)
1200 unsigned long flags;
1202 /* lock device table */
1203 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1204 __detach_device(domain, devid);
1205 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1208 static int device_change_notifier(struct notifier_block *nb,
1209 unsigned long action, void *data)
1211 struct device *dev = data;
1212 struct pci_dev *pdev = to_pci_dev(dev);
1213 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1214 struct protection_domain *domain;
1215 struct dma_ops_domain *dma_domain;
1216 struct amd_iommu *iommu;
1217 unsigned long flags;
1219 if (devid > amd_iommu_last_bdf)
1222 devid = amd_iommu_alias_table[devid];
1224 iommu = amd_iommu_rlookup_table[devid];
1228 domain = domain_for_device(devid);
1230 if (domain && !dma_ops_domain(domain))
1231 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1232 "to a non-dma-ops domain\n", dev_name(dev));
1235 case BUS_NOTIFY_UNBOUND_DRIVER:
1238 detach_device(domain, devid);
1240 case BUS_NOTIFY_ADD_DEVICE:
1241 /* allocate a protection domain if a device is added */
1242 dma_domain = find_protection_domain(devid);
1245 dma_domain = dma_ops_domain_alloc(iommu);
1248 dma_domain->target_dev = devid;
1250 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1251 list_add_tail(&dma_domain->list, &iommu_pd_list);
1252 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1259 iommu_queue_inv_dev_entry(iommu, devid);
1260 iommu_completion_wait(iommu);
1266 static struct notifier_block device_nb = {
1267 .notifier_call = device_change_notifier,
1270 /*****************************************************************************
1272 * The next functions belong to the dma_ops mapping/unmapping code.
1274 *****************************************************************************/
1277 * This function checks if the driver got a valid device from the caller to
1278 * avoid dereferencing invalid pointers.
1280 static bool check_device(struct device *dev)
1282 if (!dev || !dev->dma_mask)
1289 * In this function the list of preallocated protection domains is traversed to
1290 * find the domain for a specific device
1292 static struct dma_ops_domain *find_protection_domain(u16 devid)
1294 struct dma_ops_domain *entry, *ret = NULL;
1295 unsigned long flags;
1297 if (list_empty(&iommu_pd_list))
1300 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1302 list_for_each_entry(entry, &iommu_pd_list, list) {
1303 if (entry->target_dev == devid) {
1309 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1315 * In the dma_ops path we only have the struct device. This function
1316 * finds the corresponding IOMMU, the protection domain and the
1317 * requestor id for a given device.
1318 * If the device is not yet associated with a domain this is also done
1321 static int get_device_resources(struct device *dev,
1322 struct amd_iommu **iommu,
1323 struct protection_domain **domain,
1326 struct dma_ops_domain *dma_dom;
1327 struct pci_dev *pcidev;
1334 if (dev->bus != &pci_bus_type)
1337 pcidev = to_pci_dev(dev);
1338 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1340 /* device not translated by any IOMMU in the system? */
1341 if (_bdf > amd_iommu_last_bdf)
1344 *bdf = amd_iommu_alias_table[_bdf];
1346 *iommu = amd_iommu_rlookup_table[*bdf];
1349 *domain = domain_for_device(*bdf);
1350 if (*domain == NULL) {
1351 dma_dom = find_protection_domain(*bdf);
1353 dma_dom = (*iommu)->default_dom;
1354 *domain = &dma_dom->domain;
1355 attach_device(*iommu, *domain, *bdf);
1356 DUMP_printk("Using protection domain %d for device %s\n",
1357 (*domain)->id, dev_name(dev));
1360 if (domain_for_device(_bdf) == NULL)
1361 attach_device(*iommu, *domain, _bdf);
1367 * If the pte_page is not yet allocated this function is called
1369 static u64* alloc_pte(struct protection_domain *dom,
1370 unsigned long address, u64 **pte_page, gfp_t gfp)
1374 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1376 if (!IOMMU_PTE_PRESENT(*pte)) {
1377 page = (u64 *)get_zeroed_page(gfp);
1380 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1383 pte = IOMMU_PTE_PAGE(*pte);
1384 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1386 if (!IOMMU_PTE_PRESENT(*pte)) {
1387 page = (u64 *)get_zeroed_page(gfp);
1390 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1393 pte = IOMMU_PTE_PAGE(*pte);
1398 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1404 * This function fetches the PTE for a given address in the aperture
1406 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1407 unsigned long address)
1409 struct aperture_range *aperture;
1410 u64 *pte, *pte_page;
1412 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1416 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1418 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1419 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1421 pte += IOMMU_PTE_L0_INDEX(address);
1427 * This is the generic map function. It maps one 4kb page at paddr to
1428 * the given address in the DMA address space for the domain.
1430 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1431 struct dma_ops_domain *dom,
1432 unsigned long address,
1438 WARN_ON(address > dom->aperture_size);
1442 pte = dma_ops_get_pte(dom, address);
1444 return bad_dma_address;
1446 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1448 if (direction == DMA_TO_DEVICE)
1449 __pte |= IOMMU_PTE_IR;
1450 else if (direction == DMA_FROM_DEVICE)
1451 __pte |= IOMMU_PTE_IW;
1452 else if (direction == DMA_BIDIRECTIONAL)
1453 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1459 return (dma_addr_t)address;
1463 * The generic unmapping function for on page in the DMA address space.
1465 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1466 struct dma_ops_domain *dom,
1467 unsigned long address)
1469 struct aperture_range *aperture;
1472 if (address >= dom->aperture_size)
1475 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1479 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1483 pte += IOMMU_PTE_L0_INDEX(address);
1491 * This function contains common code for mapping of a physically
1492 * contiguous memory region into DMA address space. It is used by all
1493 * mapping functions provided with this IOMMU driver.
1494 * Must be called with the domain lock held.
1496 static dma_addr_t __map_single(struct device *dev,
1497 struct amd_iommu *iommu,
1498 struct dma_ops_domain *dma_dom,
1505 dma_addr_t offset = paddr & ~PAGE_MASK;
1506 dma_addr_t address, start, ret;
1508 unsigned long align_mask = 0;
1511 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1514 INC_STATS_COUNTER(total_map_requests);
1517 INC_STATS_COUNTER(cross_page);
1520 align_mask = (1UL << get_order(size)) - 1;
1523 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1525 if (unlikely(address == bad_dma_address)) {
1527 * setting next_address here will let the address
1528 * allocator only scan the new allocated range in the
1529 * first run. This is a small optimization.
1531 dma_dom->next_address = dma_dom->aperture_size;
1533 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1537 * aperture was sucessfully enlarged by 128 MB, try
1544 for (i = 0; i < pages; ++i) {
1545 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1546 if (ret == bad_dma_address)
1554 ADD_STATS_COUNTER(alloced_io_mem, size);
1556 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1557 iommu_flush_tlb(iommu, dma_dom->domain.id);
1558 dma_dom->need_flush = false;
1559 } else if (unlikely(iommu_has_npcache(iommu)))
1560 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1567 for (--i; i >= 0; --i) {
1569 dma_ops_domain_unmap(iommu, dma_dom, start);
1572 dma_ops_free_addresses(dma_dom, address, pages);
1574 return bad_dma_address;
1578 * Does the reverse of the __map_single function. Must be called with
1579 * the domain lock held too
1581 static void __unmap_single(struct amd_iommu *iommu,
1582 struct dma_ops_domain *dma_dom,
1583 dma_addr_t dma_addr,
1587 dma_addr_t i, start;
1590 if ((dma_addr == bad_dma_address) ||
1591 (dma_addr + size > dma_dom->aperture_size))
1594 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1595 dma_addr &= PAGE_MASK;
1598 for (i = 0; i < pages; ++i) {
1599 dma_ops_domain_unmap(iommu, dma_dom, start);
1603 SUB_STATS_COUNTER(alloced_io_mem, size);
1605 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1607 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1608 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1609 dma_dom->need_flush = false;
1614 * The exported map_single function for dma_ops.
1616 static dma_addr_t map_page(struct device *dev, struct page *page,
1617 unsigned long offset, size_t size,
1618 enum dma_data_direction dir,
1619 struct dma_attrs *attrs)
1621 unsigned long flags;
1622 struct amd_iommu *iommu;
1623 struct protection_domain *domain;
1627 phys_addr_t paddr = page_to_phys(page) + offset;
1629 INC_STATS_COUNTER(cnt_map_single);
1631 if (!check_device(dev))
1632 return bad_dma_address;
1634 dma_mask = *dev->dma_mask;
1636 get_device_resources(dev, &iommu, &domain, &devid);
1638 if (iommu == NULL || domain == NULL)
1639 /* device not handled by any AMD IOMMU */
1640 return (dma_addr_t)paddr;
1642 if (!dma_ops_domain(domain))
1643 return bad_dma_address;
1645 spin_lock_irqsave(&domain->lock, flags);
1646 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1648 if (addr == bad_dma_address)
1651 iommu_completion_wait(iommu);
1654 spin_unlock_irqrestore(&domain->lock, flags);
1660 * The exported unmap_single function for dma_ops.
1662 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1663 enum dma_data_direction dir, struct dma_attrs *attrs)
1665 unsigned long flags;
1666 struct amd_iommu *iommu;
1667 struct protection_domain *domain;
1670 INC_STATS_COUNTER(cnt_unmap_single);
1672 if (!check_device(dev) ||
1673 !get_device_resources(dev, &iommu, &domain, &devid))
1674 /* device not handled by any AMD IOMMU */
1677 if (!dma_ops_domain(domain))
1680 spin_lock_irqsave(&domain->lock, flags);
1682 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1684 iommu_completion_wait(iommu);
1686 spin_unlock_irqrestore(&domain->lock, flags);
1690 * This is a special map_sg function which is used if we should map a
1691 * device which is not handled by an AMD IOMMU in the system.
1693 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1694 int nelems, int dir)
1696 struct scatterlist *s;
1699 for_each_sg(sglist, s, nelems, i) {
1700 s->dma_address = (dma_addr_t)sg_phys(s);
1701 s->dma_length = s->length;
1708 * The exported map_sg function for dma_ops (handles scatter-gather
1711 static int map_sg(struct device *dev, struct scatterlist *sglist,
1712 int nelems, enum dma_data_direction dir,
1713 struct dma_attrs *attrs)
1715 unsigned long flags;
1716 struct amd_iommu *iommu;
1717 struct protection_domain *domain;
1720 struct scatterlist *s;
1722 int mapped_elems = 0;
1725 INC_STATS_COUNTER(cnt_map_sg);
1727 if (!check_device(dev))
1730 dma_mask = *dev->dma_mask;
1732 get_device_resources(dev, &iommu, &domain, &devid);
1734 if (!iommu || !domain)
1735 return map_sg_no_iommu(dev, sglist, nelems, dir);
1737 if (!dma_ops_domain(domain))
1740 spin_lock_irqsave(&domain->lock, flags);
1742 for_each_sg(sglist, s, nelems, i) {
1745 s->dma_address = __map_single(dev, iommu, domain->priv,
1746 paddr, s->length, dir, false,
1749 if (s->dma_address) {
1750 s->dma_length = s->length;
1756 iommu_completion_wait(iommu);
1759 spin_unlock_irqrestore(&domain->lock, flags);
1761 return mapped_elems;
1763 for_each_sg(sglist, s, mapped_elems, i) {
1765 __unmap_single(iommu, domain->priv, s->dma_address,
1766 s->dma_length, dir);
1767 s->dma_address = s->dma_length = 0;
1776 * The exported map_sg function for dma_ops (handles scatter-gather
1779 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1780 int nelems, enum dma_data_direction dir,
1781 struct dma_attrs *attrs)
1783 unsigned long flags;
1784 struct amd_iommu *iommu;
1785 struct protection_domain *domain;
1786 struct scatterlist *s;
1790 INC_STATS_COUNTER(cnt_unmap_sg);
1792 if (!check_device(dev) ||
1793 !get_device_resources(dev, &iommu, &domain, &devid))
1796 if (!dma_ops_domain(domain))
1799 spin_lock_irqsave(&domain->lock, flags);
1801 for_each_sg(sglist, s, nelems, i) {
1802 __unmap_single(iommu, domain->priv, s->dma_address,
1803 s->dma_length, dir);
1804 s->dma_address = s->dma_length = 0;
1807 iommu_completion_wait(iommu);
1809 spin_unlock_irqrestore(&domain->lock, flags);
1813 * The exported alloc_coherent function for dma_ops.
1815 static void *alloc_coherent(struct device *dev, size_t size,
1816 dma_addr_t *dma_addr, gfp_t flag)
1818 unsigned long flags;
1820 struct amd_iommu *iommu;
1821 struct protection_domain *domain;
1824 u64 dma_mask = dev->coherent_dma_mask;
1826 INC_STATS_COUNTER(cnt_alloc_coherent);
1828 if (!check_device(dev))
1831 if (!get_device_resources(dev, &iommu, &domain, &devid))
1832 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1835 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1839 paddr = virt_to_phys(virt_addr);
1841 if (!iommu || !domain) {
1842 *dma_addr = (dma_addr_t)paddr;
1846 if (!dma_ops_domain(domain))
1850 dma_mask = *dev->dma_mask;
1852 spin_lock_irqsave(&domain->lock, flags);
1854 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1855 size, DMA_BIDIRECTIONAL, true, dma_mask);
1857 if (*dma_addr == bad_dma_address) {
1858 spin_unlock_irqrestore(&domain->lock, flags);
1862 iommu_completion_wait(iommu);
1864 spin_unlock_irqrestore(&domain->lock, flags);
1870 free_pages((unsigned long)virt_addr, get_order(size));
1876 * The exported free_coherent function for dma_ops.
1878 static void free_coherent(struct device *dev, size_t size,
1879 void *virt_addr, dma_addr_t dma_addr)
1881 unsigned long flags;
1882 struct amd_iommu *iommu;
1883 struct protection_domain *domain;
1886 INC_STATS_COUNTER(cnt_free_coherent);
1888 if (!check_device(dev))
1891 get_device_resources(dev, &iommu, &domain, &devid);
1893 if (!iommu || !domain)
1896 if (!dma_ops_domain(domain))
1899 spin_lock_irqsave(&domain->lock, flags);
1901 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1903 iommu_completion_wait(iommu);
1905 spin_unlock_irqrestore(&domain->lock, flags);
1908 free_pages((unsigned long)virt_addr, get_order(size));
1912 * This function is called by the DMA layer to find out if we can handle a
1913 * particular device. It is part of the dma_ops.
1915 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1918 struct pci_dev *pcidev;
1920 /* No device or no PCI device */
1921 if (!dev || dev->bus != &pci_bus_type)
1924 pcidev = to_pci_dev(dev);
1926 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1928 /* Out of our scope? */
1929 if (bdf > amd_iommu_last_bdf)
1936 * The function for pre-allocating protection domains.
1938 * If the driver core informs the DMA layer if a driver grabs a device
1939 * we don't need to preallocate the protection domains anymore.
1940 * For now we have to.
1942 static void prealloc_protection_domains(void)
1944 struct pci_dev *dev = NULL;
1945 struct dma_ops_domain *dma_dom;
1946 struct amd_iommu *iommu;
1949 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1950 devid = calc_devid(dev->bus->number, dev->devfn);
1951 if (devid > amd_iommu_last_bdf)
1953 devid = amd_iommu_alias_table[devid];
1954 if (domain_for_device(devid))
1956 iommu = amd_iommu_rlookup_table[devid];
1959 dma_dom = dma_ops_domain_alloc(iommu);
1962 init_unity_mappings_for_device(dma_dom, devid);
1963 dma_dom->target_dev = devid;
1965 list_add_tail(&dma_dom->list, &iommu_pd_list);
1969 static struct dma_map_ops amd_iommu_dma_ops = {
1970 .alloc_coherent = alloc_coherent,
1971 .free_coherent = free_coherent,
1972 .map_page = map_page,
1973 .unmap_page = unmap_page,
1975 .unmap_sg = unmap_sg,
1976 .dma_supported = amd_iommu_dma_supported,
1980 * The function which clues the AMD IOMMU driver into dma_ops.
1982 int __init amd_iommu_init_dma_ops(void)
1984 struct amd_iommu *iommu;
1988 * first allocate a default protection domain for every IOMMU we
1989 * found in the system. Devices not assigned to any other
1990 * protection domain will be assigned to the default one.
1992 for_each_iommu(iommu) {
1993 iommu->default_dom = dma_ops_domain_alloc(iommu);
1994 if (iommu->default_dom == NULL)
1996 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1997 ret = iommu_init_unity_mappings(iommu);
2003 * If device isolation is enabled, pre-allocate the protection
2004 * domains for each device.
2006 if (amd_iommu_isolate)
2007 prealloc_protection_domains();
2011 bad_dma_address = 0;
2012 #ifdef CONFIG_GART_IOMMU
2013 gart_iommu_aperture_disabled = 1;
2014 gart_iommu_aperture = 0;
2017 /* Make the driver finally visible to the drivers */
2018 dma_ops = &amd_iommu_dma_ops;
2020 register_iommu(&amd_iommu_ops);
2022 bus_register_notifier(&pci_bus_type, &device_nb);
2024 amd_iommu_stats_init();
2030 for_each_iommu(iommu) {
2031 if (iommu->default_dom)
2032 dma_ops_domain_free(iommu->default_dom);
2038 /*****************************************************************************
2040 * The following functions belong to the exported interface of AMD IOMMU
2042 * This interface allows access to lower level functions of the IOMMU
2043 * like protection domain handling and assignement of devices to domains
2044 * which is not possible with the dma_ops interface.
2046 *****************************************************************************/
2048 static void cleanup_domain(struct protection_domain *domain)
2050 unsigned long flags;
2053 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2055 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2056 if (amd_iommu_pd_table[devid] == domain)
2057 __detach_device(domain, devid);
2059 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2062 static int amd_iommu_domain_init(struct iommu_domain *dom)
2064 struct protection_domain *domain;
2066 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2070 spin_lock_init(&domain->lock);
2071 domain->mode = PAGE_MODE_3_LEVEL;
2072 domain->id = domain_id_alloc();
2075 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2076 if (!domain->pt_root)
2089 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2091 struct protection_domain *domain = dom->priv;
2096 if (domain->dev_cnt > 0)
2097 cleanup_domain(domain);
2099 BUG_ON(domain->dev_cnt != 0);
2101 free_pagetable(domain);
2103 domain_id_free(domain->id);
2110 static void amd_iommu_detach_device(struct iommu_domain *dom,
2113 struct protection_domain *domain = dom->priv;
2114 struct amd_iommu *iommu;
2115 struct pci_dev *pdev;
2118 if (dev->bus != &pci_bus_type)
2121 pdev = to_pci_dev(dev);
2123 devid = calc_devid(pdev->bus->number, pdev->devfn);
2126 detach_device(domain, devid);
2128 iommu = amd_iommu_rlookup_table[devid];
2132 iommu_queue_inv_dev_entry(iommu, devid);
2133 iommu_completion_wait(iommu);
2136 static int amd_iommu_attach_device(struct iommu_domain *dom,
2139 struct protection_domain *domain = dom->priv;
2140 struct protection_domain *old_domain;
2141 struct amd_iommu *iommu;
2142 struct pci_dev *pdev;
2145 if (dev->bus != &pci_bus_type)
2148 pdev = to_pci_dev(dev);
2150 devid = calc_devid(pdev->bus->number, pdev->devfn);
2152 if (devid >= amd_iommu_last_bdf ||
2153 devid != amd_iommu_alias_table[devid])
2156 iommu = amd_iommu_rlookup_table[devid];
2160 old_domain = domain_for_device(devid);
2162 detach_device(old_domain, devid);
2164 attach_device(iommu, domain, devid);
2166 iommu_completion_wait(iommu);
2171 static int amd_iommu_map_range(struct iommu_domain *dom,
2172 unsigned long iova, phys_addr_t paddr,
2173 size_t size, int iommu_prot)
2175 struct protection_domain *domain = dom->priv;
2176 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2180 if (iommu_prot & IOMMU_READ)
2181 prot |= IOMMU_PROT_IR;
2182 if (iommu_prot & IOMMU_WRITE)
2183 prot |= IOMMU_PROT_IW;
2188 for (i = 0; i < npages; ++i) {
2189 ret = iommu_map_page(domain, iova, paddr, prot);
2200 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2201 unsigned long iova, size_t size)
2204 struct protection_domain *domain = dom->priv;
2205 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2209 for (i = 0; i < npages; ++i) {
2210 iommu_unmap_page(domain, iova);
2214 iommu_flush_domain(domain->id);
2217 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2220 struct protection_domain *domain = dom->priv;
2221 unsigned long offset = iova & ~PAGE_MASK;
2225 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2227 if (!IOMMU_PTE_PRESENT(*pte))
2230 pte = IOMMU_PTE_PAGE(*pte);
2231 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2233 if (!IOMMU_PTE_PRESENT(*pte))
2236 pte = IOMMU_PTE_PAGE(*pte);
2237 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2239 if (!IOMMU_PTE_PRESENT(*pte))
2242 paddr = *pte & IOMMU_PAGE_MASK;
2248 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2254 static struct iommu_ops amd_iommu_ops = {
2255 .domain_init = amd_iommu_domain_init,
2256 .domain_destroy = amd_iommu_domain_destroy,
2257 .attach_dev = amd_iommu_attach_device,
2258 .detach_dev = amd_iommu_detach_device,
2259 .map = amd_iommu_map_range,
2260 .unmap = amd_iommu_unmap_range,
2261 .iova_to_phys = amd_iommu_iova_to_phys,
2262 .domain_has_cap = amd_iommu_domain_has_cap,