arch/x86/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4 #include <asm/io.h>
   5 #include <asm/processor.h>
   6 #include <asm/apic.h>
   7
   8 #include <mach_apic.h>
   9 #include "../setup.h"
  10 #include "cpu.h"
  11
  12 /*
  13  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  14  *      misexecution of code under Linux. Owners of such processors should
  15  *      contact AMD for precise details and a CPU swap.
  16  *
  17  *      See     http://www.multimania.com/poulot/k6bug.html
  18  *              http://www.amd.com/K6/k6docs/revgd.html
  19  *
  20  *      The following test is erm.. interesting. AMD neglected to up
  21  *      the chip setting when fixing the bug but they also tweaked some
  22  *      performance at the same time..
  23  */
  24
  25 extern void vide(void);
  26 __asm__(".align 4\nvide: ret");
  27
  28 #ifdef CONFIG_X86_LOCAL_APIC
  29 #define ENABLE_C1E_MASK         0x18000000
  30 #define CPUID_PROCESSOR_SIGNATURE       1
  31 #define CPUID_XFAM              0x0ff00000
  32 #define CPUID_XFAM_K8           0x00000000
  33 #define CPUID_XFAM_10H          0x00100000
  34 #define CPUID_XFAM_11H          0x00200000
  35 #define CPUID_XMOD              0x000f0000
  36 #define CPUID_XMOD_REV_F        0x00040000
  37
  38 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
  39 static __cpuinit int amd_apic_timer_broken(void)
  40 {
  41         u32 lo, hi;
  42         u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
  43         switch (eax & CPUID_XFAM) {
  44         case CPUID_XFAM_K8:
  45                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
  46                         break;
  47         case CPUID_XFAM_10H:
  48         case CPUID_XFAM_11H:
  49                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
  50                 if (lo & ENABLE_C1E_MASK) {
  51                         if (smp_processor_id() != boot_cpu_physical_apicid)
  52                                 printk(KERN_INFO "AMD C1E detected late. "
  53                                        "        Force timer broadcast.\n");
  54                         return 1;
  55                 }
  56                 break;
  57         default:
  58                 /* err on the side of caution */
  59                 return 1;
  60         }
  61         return 0;
  62 }
  63 #endif
  64
  65 int force_mwait __cpuinitdata;
  66
  67 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  68 {
  69         if (cpuid_eax(0x80000000) >= 0x80000007) {
  70                 c->x86_power = cpuid_edx(0x80000007);
  71                 if (c->x86_power & (1<<8))
  72                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  73         }
  74 }
  75
  76 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  77 {
  78         u32 l, h;
  79         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  80         int r;
  81
  82 #ifdef CONFIG_SMP
  83         unsigned long long value;
  84
  85         /*
  86          * Disable TLB flush filter by setting HWCR.FFDIS on K8
  87          * bit 6 of msr C001_0015
  88          *
  89          * Errata 63 for SH-B3 steppings
  90          * Errata 122 for all steppings (F+ have it disabled by default)
  91          */
  92         if (c->x86 == 15) {
  93                 rdmsrl(MSR_K7_HWCR, value);
  94                 value |= 1 << 6;
  95                 wrmsrl(MSR_K7_HWCR, value);
  96         }
  97 #endif
  98
  99         early_init_amd(c);
 100
 101         /*
 102          *      FIXME: We should handle the K5 here. Set up the write
 103          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
 104          *      no bus pipeline)
 105          */
 106
 107         /*
 108          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 109          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 110          */
 111         clear_cpu_cap(c, 0*32+31);
 112
 113         r = get_model_name(c);
 114
 115         switch (c->x86) {
 116         case 4:
 117                 /*
 118                  * General Systems BIOSen alias the cpu frequency registers
 119                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
 120                  * drivers subsequently pokes it, and changes the CPU speed.
 121                  * Workaround : Remove the unneeded alias.
 122                  */
 123 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
 124 #define CBAR_ENB        (0x80000000)
 125 #define CBAR_KEY        (0X000000CB)
 126                         if (c->x86_model == 9 || c->x86_model == 10) {
 127                                 if (inl (CBAR) & CBAR_ENB)
 128                                         outl (0 | CBAR_KEY, CBAR);
 129                         }
 130                         break;
 131         case 5:
 132                         if (c->x86_model < 6) {
 133                                 /* Based on AMD doc 20734R - June 2000 */
 134                                 if (c->x86_model == 0) {
 135                                         clear_cpu_cap(c, X86_FEATURE_APIC);
 136                                         set_cpu_cap(c, X86_FEATURE_PGE);
 137                                 }
 138                                 break;
 139                         }
 140
 141                         if (c->x86_model == 6 && c->x86_mask == 1) {
 142                                 const int K6_BUG_LOOP = 1000000;
 143                                 int n;
 144                                 void (*f_vide)(void);
 145                                 unsigned long d, d2;
 146
 147                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
 148
 149                                 /*
 150                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
 151                                  * calls at the same time.
 152                                  */
 153
 154                                 n = K6_BUG_LOOP;
 155                                 f_vide = vide;
 156                                 rdtscl(d);
 157                                 while (n--)
 158                                         f_vide();
 159                                 rdtscl(d2);
 160                                 d = d2-d;
 161
 162                                 if (d > 20*K6_BUG_LOOP)
 163                                         printk("system stability may be impaired when more than 32 MB are used.\n");
 164                                 else
 165                                         printk("probably OK (after B9730xxxx).\n");
 166                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
 167                         }
 168
 169                         /* K6 with old style WHCR */
 170                         if (c->x86_model < 8 ||
 171                            (c->x86_model == 8 && c->x86_mask < 8)) {
 172                                 /* We can only write allocate on the low 508Mb */
 173                                 if (mbytes > 508)
 174                                         mbytes = 508;
 175
 176                                 rdmsr(MSR_K6_WHCR, l, h);
 177                                 if ((l&0x0000FFFF) == 0) {
 178                                         unsigned long flags;
 179                                         l = (1<<0)|((mbytes/4)<<1);
 180                                         local_irq_save(flags);
 181                                         wbinvd();
 182                                         wrmsr(MSR_K6_WHCR, l, h);
 183                                         local_irq_restore(flags);
 184                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 185                                                 mbytes);
 186                                 }
 187                                 break;
 188                         }
 189
 190                         if ((c->x86_model == 8 && c->x86_mask > 7) ||
 191                              c->x86_model == 9 || c->x86_model == 13) {
 192                                 /* The more serious chips .. */
 193
 194                                 if (mbytes > 4092)
 195                                         mbytes = 4092;
 196
 197                                 rdmsr(MSR_K6_WHCR, l, h);
 198                                 if ((l&0xFFFF0000) == 0) {
 199                                         unsigned long flags;
 200                                         l = ((mbytes>>2)<<22)|(1<<16);
 201                                         local_irq_save(flags);
 202                                         wbinvd();
 203                                         wrmsr(MSR_K6_WHCR, l, h);
 204                                         local_irq_restore(flags);
 205                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 206                                                 mbytes);
 207                                 }
 208
 209                                 /*  Set MTRR capability flag if appropriate */
 210                                 if (c->x86_model == 13 || c->x86_model == 9 ||
 211                                    (c->x86_model == 8 && c->x86_mask >= 8))
 212                                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 213                                 break;
 214                         }
 215
 216                         if (c->x86_model == 10) {
 217                                 /* AMD Geode LX is model 10 */
 218                                 /* placeholder for any needed mods */
 219                                 break;
 220                         }
 221                         break;
 222         case 6: /* An Athlon/Duron */
 223
 224                         /*
 225                          * Bit 15 of Athlon specific MSR 15, needs to be 0
 226                          * to enable SSE on Palomino/Morgan/Barton CPU's.
 227                          * If the BIOS didn't enable it already, enable it here.
 228                          */
 229                         if (c->x86_model >= 6 && c->x86_model <= 10) {
 230                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 231                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 232                                         rdmsr(MSR_K7_HWCR, l, h);
 233                                         l &= ~0x00008000;
 234                                         wrmsr(MSR_K7_HWCR, l, h);
 235                                         set_cpu_cap(c, X86_FEATURE_XMM);
 236                                 }
 237                         }
 238
 239                         /*
 240                          * It's been determined by AMD that Athlons since model 8 stepping 1
 241                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 242                          * As per AMD technical note 27212 0.2
 243                          */
 244                         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
 245                                 rdmsr(MSR_K7_CLK_CTL, l, h);
 246                                 if ((l & 0xfff00000) != 0x20000000) {
 247                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 248                                                 ((l & 0x000fffff)|0x20000000));
 249                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 250                                 }
 251                         }
 252                         break;
 253         }
 254
 255         switch (c->x86) {
 256         case 15:
 257         /* Use K8 tuning for Fam10h and Fam11h */
 258         case 0x10:
 259         case 0x11:
 260                 set_cpu_cap(c, X86_FEATURE_K8);
 261                 break;
 262         case 6:
 263                 set_cpu_cap(c, X86_FEATURE_K7);
 264                 break;
 265         }
 266         if (c->x86 >= 6)
 267                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 268
 269         display_cacheinfo(c);
 270
 271         if (cpuid_eax(0x80000000) >= 0x80000008)
 272                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 273
 274 #ifdef CONFIG_X86_HT
 275         /*
 276          * On a AMD multi core setup the lower bits of the APIC id
 277          * distinguish the cores.
 278          */
 279         if (c->x86_max_cores > 1) {
 280                 int cpu = smp_processor_id();
 281                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
 282
 283                 if (bits == 0) {
 284                         while ((1 << bits) < c->x86_max_cores)
 285                                 bits++;
 286                 }
 287                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
 288                 c->phys_proc_id >>= bits;
 289                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
 290                        cpu, c->x86_max_cores, c->cpu_core_id);
 291         }
 292 #endif
 293
 294         if (cpuid_eax(0x80000000) >= 0x80000006) {
 295                 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
 296                         num_cache_leaves = 4;
 297                 else
 298                         num_cache_leaves = 3;
 299         }
 300
 301 #ifdef CONFIG_X86_LOCAL_APIC
 302         if (amd_apic_timer_broken())
 303                 local_apic_timer_disabled = 1;
 304 #endif
 305
 306         /* K6s reports MCEs but don't actually have all the MSRs */
 307         if (c->x86 < 6)
 308                 clear_cpu_cap(c, X86_FEATURE_MCE);
 309
 310         if (cpu_has_xmm2)
 311                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 312
 313         if (c->x86 == 0x10)
 314                 amd_enable_pci_ext_cfg(c);
 315 }
 316
 317 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 318 {
 319         /* AMD errata T13 (order #21922) */
 320         if ((c->x86 == 6)) {
 321                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 322                         size = 64;
 323                 if (c->x86_model == 4 &&
 324                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
 325                         size = 256;
 326         }
 327         return size;
 328 }
 329
 330 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 331         .c_vendor       = "AMD",
 332         .c_ident        = { "AuthenticAMD" },
 333         .c_models = {
 334                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 335                   {
 336                           [3] = "486 DX/2",
 337                           [7] = "486 DX/2-WB",
 338                           [8] = "486 DX/4",
 339                           [9] = "486 DX/4-WB",
 340                           [14] = "Am5x86-WT",
 341                           [15] = "Am5x86-WB"
 342                   }
 343                 },
 344         },
 345         .c_early_init   = early_init_amd,
 346         .c_init         = init_amd,
 347         .c_size_cache   = amd_size_cache,
 348 };
 349
 350 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);