2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
45 #include <asm/processor.h>
49 #include "mce-internal.h"
51 static DEFINE_MUTEX(mce_chrdev_read_mutex);
53 #define rcu_dereference_check_mce(p) \
54 rcu_dereference_index_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_chrdev_read_mutex))
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
98 static DEFINE_PER_CPU(struct mce, mces_seen);
99 static int cpu_missing;
101 /* MCA banks polled by the period polling timer for corrected events */
102 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
103 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
106 static DEFINE_PER_CPU(struct work_struct, mce_work);
108 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
111 * CPU/chipset specific EDAC code can register a notifier call here to print
112 * MCE errors in a human-readable form.
114 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
116 /* Do initial initialization of a struct mce */
117 void mce_setup(struct mce *m)
119 memset(m, 0, sizeof(struct mce));
120 m->cpu = m->extcpu = smp_processor_id();
122 /* We hope get_seconds stays lockless */
123 m->time = get_seconds();
124 m->cpuvendor = boot_cpu_data.x86_vendor;
125 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
131 DEFINE_PER_CPU(struct mce, injectm);
132 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
135 * Lockless MCE logging infrastructure.
136 * This avoids deadlocks on printk locks without having to break locks. Also
137 * separate MCEs from kernel messages to avoid bogus bug reports.
140 static struct mce_log mcelog = {
141 .signature = MCE_LOG_SIGNATURE,
143 .recordlen = sizeof(struct mce),
146 void mce_log(struct mce *mce)
148 unsigned next, entry;
151 /* Emit the trace record: */
152 trace_mce_record(mce);
154 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
155 if (ret == NOTIFY_STOP)
161 entry = rcu_dereference_check_mce(mcelog.next);
165 * When the buffer fills up discard new entries.
166 * Assume that the earlier errors are the more
169 if (entry >= MCE_LOG_LEN) {
170 set_bit(MCE_OVERFLOW,
171 (unsigned long *)&mcelog.flags);
174 /* Old left over entry. Skip: */
175 if (mcelog.entry[entry].finished) {
183 if (cmpxchg(&mcelog.next, entry, next) == entry)
186 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
188 mcelog.entry[entry].finished = 1;
192 set_bit(0, &mce_need_notify);
195 static void drain_mcelog_buffer(void)
197 unsigned int next, i, prev = 0;
199 next = ACCESS_ONCE(mcelog.next);
204 /* drain what was logged during boot */
205 for (i = prev; i < next; i++) {
206 unsigned long start = jiffies;
207 unsigned retries = 1;
209 m = &mcelog.entry[i];
211 while (!m->finished) {
212 if (time_after_eq(jiffies, start + 2*retries))
217 if (!m->finished && retries >= 4) {
218 pr_err("skipping error being logged currently!\n");
223 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
226 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
228 next = cmpxchg(&mcelog.next, prev, 0);
229 } while (next != prev);
233 void mce_register_decode_chain(struct notifier_block *nb)
235 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
236 drain_mcelog_buffer();
238 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
240 void mce_unregister_decode_chain(struct notifier_block *nb)
242 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
244 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
246 static void print_mce(struct mce *m)
250 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
251 m->extcpu, m->mcgstatus, m->bank, m->status);
254 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
255 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
258 if (m->cs == __KERNEL_CS)
259 print_symbol("{%s}", m->ip);
263 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
265 pr_cont("ADDR %llx ", m->addr);
267 pr_cont("MISC %llx ", m->misc);
271 * Note this output is parsed by external tools and old fields
272 * should not be changed.
274 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
275 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
276 cpu_data(m->extcpu).microcode);
279 * Print out human-readable details about the MCE error,
280 * (if the CPU has an implementation for that)
282 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
283 if (ret == NOTIFY_STOP)
286 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
289 #define PANIC_TIMEOUT 5 /* 5 seconds */
291 static atomic_t mce_paniced;
293 static int fake_panic;
294 static atomic_t mce_fake_paniced;
296 /* Panic in progress. Enable interrupts and wait for final IPI */
297 static void wait_for_panic(void)
299 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
303 while (timeout-- > 0)
305 if (panic_timeout == 0)
306 panic_timeout = mce_panic_timeout;
307 panic("Panicing machine check CPU died");
310 static void mce_panic(char *msg, struct mce *final, char *exp)
316 * Make sure only one CPU runs in machine check panic
318 if (atomic_inc_return(&mce_paniced) > 1)
325 /* Don't log too much for fake panic */
326 if (atomic_inc_return(&mce_fake_paniced) > 1)
329 /* First print corrected ones that are still unlogged */
330 for (i = 0; i < MCE_LOG_LEN; i++) {
331 struct mce *m = &mcelog.entry[i];
332 if (!(m->status & MCI_STATUS_VAL))
334 if (!(m->status & MCI_STATUS_UC)) {
337 apei_err = apei_write_mce(m);
340 /* Now print uncorrected but with the final one last */
341 for (i = 0; i < MCE_LOG_LEN; i++) {
342 struct mce *m = &mcelog.entry[i];
343 if (!(m->status & MCI_STATUS_VAL))
345 if (!(m->status & MCI_STATUS_UC))
347 if (!final || memcmp(m, final, sizeof(struct mce))) {
350 apei_err = apei_write_mce(m);
356 apei_err = apei_write_mce(final);
359 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
361 pr_emerg(HW_ERR "Machine check: %s\n", exp);
363 if (panic_timeout == 0)
364 panic_timeout = mce_panic_timeout;
367 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
370 /* Support code for software error injection */
372 static int msr_to_offset(u32 msr)
374 unsigned bank = __this_cpu_read(injectm.bank);
377 return offsetof(struct mce, ip);
378 if (msr == MSR_IA32_MCx_STATUS(bank))
379 return offsetof(struct mce, status);
380 if (msr == MSR_IA32_MCx_ADDR(bank))
381 return offsetof(struct mce, addr);
382 if (msr == MSR_IA32_MCx_MISC(bank))
383 return offsetof(struct mce, misc);
384 if (msr == MSR_IA32_MCG_STATUS)
385 return offsetof(struct mce, mcgstatus);
389 /* MSR access wrappers used for error injection */
390 static u64 mce_rdmsrl(u32 msr)
394 if (__this_cpu_read(injectm.finished)) {
395 int offset = msr_to_offset(msr);
399 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
402 if (rdmsrl_safe(msr, &v)) {
403 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
405 * Return zero in case the access faulted. This should
406 * not happen normally but can happen if the CPU does
407 * something weird, or if the code is buggy.
415 static void mce_wrmsrl(u32 msr, u64 v)
417 if (__this_cpu_read(injectm.finished)) {
418 int offset = msr_to_offset(msr);
421 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
428 * Collect all global (w.r.t. this processor) status about this machine
429 * check into our "mce" struct so that we can use it later to assess
430 * the severity of the problem as we read per-bank specific details.
432 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
436 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
439 * Get the address of the instruction at the time of
440 * the machine check error.
442 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
447 * When in VM86 mode make the cs look like ring 3
448 * always. This is a lie, but it's better than passing
449 * the additional vm86 bit around everywhere.
451 if (v8086_mode(regs))
454 /* Use accurate RIP reporting if available. */
456 m->ip = mce_rdmsrl(rip_msr);
461 * Simple lockless ring to communicate PFNs from the exception handler with the
462 * process context work function. This is vastly simplified because there's
463 * only a single reader and a single writer.
465 #define MCE_RING_SIZE 16 /* we use one entry less */
468 unsigned short start;
470 unsigned long ring[MCE_RING_SIZE];
472 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
474 /* Runs with CPU affinity in workqueue */
475 static int mce_ring_empty(void)
477 struct mce_ring *r = &__get_cpu_var(mce_ring);
479 return r->start == r->end;
482 static int mce_ring_get(unsigned long *pfn)
489 r = &__get_cpu_var(mce_ring);
490 if (r->start == r->end)
492 *pfn = r->ring[r->start];
493 r->start = (r->start + 1) % MCE_RING_SIZE;
500 /* Always runs in MCE context with preempt off */
501 static int mce_ring_add(unsigned long pfn)
503 struct mce_ring *r = &__get_cpu_var(mce_ring);
506 next = (r->end + 1) % MCE_RING_SIZE;
507 if (next == r->start)
509 r->ring[r->end] = pfn;
515 int mce_available(struct cpuinfo_x86 *c)
519 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
522 static void mce_schedule_work(void)
524 if (!mce_ring_empty()) {
525 struct work_struct *work = &__get_cpu_var(mce_work);
526 if (!work_pending(work))
531 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
533 static void mce_irq_work_cb(struct irq_work *entry)
539 static void mce_report_event(struct pt_regs *regs)
541 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
544 * Triggering the work queue here is just an insurance
545 * policy in case the syscall exit notify handler
546 * doesn't run soon enough or ends up running on the
547 * wrong CPU (can happen when audit sleeps)
553 irq_work_queue(&__get_cpu_var(mce_irq_work));
557 * Read ADDR and MISC registers.
559 static void mce_read_aux(struct mce *m, int i)
561 if (m->status & MCI_STATUS_MISCV)
562 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
563 if (m->status & MCI_STATUS_ADDRV) {
564 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
567 * Mask the reported address by the reported granularity.
569 if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
570 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
577 DEFINE_PER_CPU(unsigned, mce_poll_count);
580 * Poll for corrected events or events that happened before reset.
581 * Those are just logged through /dev/mcelog.
583 * This is executed in standard interrupt context.
585 * Note: spec recommends to panic for fatal unsignalled
586 * errors here. However this would be quite problematic --
587 * we would need to reimplement the Monarch handling and
588 * it would mess up the exclusion between exception handler
589 * and poll hander -- * so we skip this for now.
590 * These cases should not happen anyways, or only when the CPU
591 * is already totally * confused. In this case it's likely it will
592 * not fully execute the machine check handler either.
594 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
599 this_cpu_inc(mce_poll_count);
601 mce_gather_info(&m, NULL);
603 for (i = 0; i < banks; i++) {
604 if (!mce_banks[i].ctl || !test_bit(i, *b))
613 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
614 if (!(m.status & MCI_STATUS_VAL))
618 * Uncorrected or signalled events are handled by the exception
619 * handler when it is enabled, so don't process those here.
621 * TBD do the same check for MCI_STATUS_EN here?
623 if (!(flags & MCP_UC) &&
624 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
629 if (!(flags & MCP_TIMESTAMP))
632 * Don't get the IP here because it's unlikely to
633 * have anything to do with the actual error location.
635 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
639 * Clear state for this bank.
641 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
645 * Don't clear MCG_STATUS here because it's only defined for
651 EXPORT_SYMBOL_GPL(machine_check_poll);
654 * Do a quick check if any of the events requires a panic.
655 * This decides if we keep the events around or clear them.
657 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
658 struct pt_regs *regs)
662 for (i = 0; i < banks; i++) {
663 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
664 if (m->status & MCI_STATUS_VAL) {
665 __set_bit(i, validp);
666 if (quirk_no_way_out)
667 quirk_no_way_out(i, m, regs);
669 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
676 * Variable to establish order between CPUs while scanning.
677 * Each CPU spins initially until executing is equal its number.
679 static atomic_t mce_executing;
682 * Defines order of CPUs on entry. First CPU becomes Monarch.
684 static atomic_t mce_callin;
687 * Check if a timeout waiting for other CPUs happened.
689 static int mce_timed_out(u64 *t)
692 * The others already did panic for some reason.
693 * Bail out like in a timeout.
694 * rmb() to tell the compiler that system_state
695 * might have been modified by someone else.
698 if (atomic_read(&mce_paniced))
700 if (!monarch_timeout)
702 if ((s64)*t < SPINUNIT) {
703 /* CHECKME: Make panic default for 1 too? */
705 mce_panic("Timeout synchronizing machine check over CPUs",
712 touch_nmi_watchdog();
717 * The Monarch's reign. The Monarch is the CPU who entered
718 * the machine check handler first. It waits for the others to
719 * raise the exception too and then grades them. When any
720 * error is fatal panic. Only then let the others continue.
722 * The other CPUs entering the MCE handler will be controlled by the
723 * Monarch. They are called Subjects.
725 * This way we prevent any potential data corruption in a unrecoverable case
726 * and also makes sure always all CPU's errors are examined.
728 * Also this detects the case of a machine check event coming from outer
729 * space (not detected by any CPUs) In this case some external agent wants
730 * us to shut down, so panic too.
732 * The other CPUs might still decide to panic if the handler happens
733 * in a unrecoverable place, but in this case the system is in a semi-stable
734 * state and won't corrupt anything by itself. It's ok to let the others
735 * continue for a bit first.
737 * All the spin loops have timeouts; when a timeout happens a CPU
738 * typically elects itself to be Monarch.
740 static void mce_reign(void)
743 struct mce *m = NULL;
744 int global_worst = 0;
749 * This CPU is the Monarch and the other CPUs have run
750 * through their handlers.
751 * Grade the severity of the errors of all the CPUs.
753 for_each_possible_cpu(cpu) {
754 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
756 if (severity > global_worst) {
758 global_worst = severity;
759 m = &per_cpu(mces_seen, cpu);
764 * Cannot recover? Panic here then.
765 * This dumps all the mces in the log buffer and stops the
768 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
769 mce_panic("Fatal Machine check", m, msg);
772 * For UC somewhere we let the CPU who detects it handle it.
773 * Also must let continue the others, otherwise the handling
774 * CPU could deadlock on a lock.
778 * No machine check event found. Must be some external
779 * source or one CPU is hung. Panic.
781 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
782 mce_panic("Machine check from unknown source", NULL, NULL);
785 * Now clear all the mces_seen so that they don't reappear on
788 for_each_possible_cpu(cpu)
789 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
792 static atomic_t global_nwo;
795 * Start of Monarch synchronization. This waits until all CPUs have
796 * entered the exception handler and then determines if any of them
797 * saw a fatal event that requires panic. Then it executes them
798 * in the entry order.
799 * TBD double check parallel CPU hotunplug
801 static int mce_start(int *no_way_out)
804 int cpus = num_online_cpus();
805 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
810 atomic_add(*no_way_out, &global_nwo);
812 * global_nwo should be updated before mce_callin
815 order = atomic_inc_return(&mce_callin);
820 while (atomic_read(&mce_callin) != cpus) {
821 if (mce_timed_out(&timeout)) {
822 atomic_set(&global_nwo, 0);
829 * mce_callin should be read before global_nwo
835 * Monarch: Starts executing now, the others wait.
837 atomic_set(&mce_executing, 1);
840 * Subject: Now start the scanning loop one by one in
841 * the original callin order.
842 * This way when there are any shared banks it will be
843 * only seen by one CPU before cleared, avoiding duplicates.
845 while (atomic_read(&mce_executing) < order) {
846 if (mce_timed_out(&timeout)) {
847 atomic_set(&global_nwo, 0);
855 * Cache the global no_way_out state.
857 *no_way_out = atomic_read(&global_nwo);
863 * Synchronize between CPUs after main scanning loop.
864 * This invokes the bulk of the Monarch processing.
866 static int mce_end(int order)
869 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
877 * Allow others to run.
879 atomic_inc(&mce_executing);
882 /* CHECKME: Can this race with a parallel hotplug? */
883 int cpus = num_online_cpus();
886 * Monarch: Wait for everyone to go through their scanning
889 while (atomic_read(&mce_executing) <= cpus) {
890 if (mce_timed_out(&timeout))
900 * Subject: Wait for Monarch to finish.
902 while (atomic_read(&mce_executing) != 0) {
903 if (mce_timed_out(&timeout))
909 * Don't reset anything. That's done by the Monarch.
915 * Reset all global state.
918 atomic_set(&global_nwo, 0);
919 atomic_set(&mce_callin, 0);
923 * Let others run again.
925 atomic_set(&mce_executing, 0);
930 * Check if the address reported by the CPU is in a format we can parse.
931 * It would be possible to add code for most other cases, but all would
932 * be somewhat complicated (e.g. segment offset would require an instruction
933 * parser). So only support physical addresses up to page granuality for now.
935 static int mce_usable_address(struct mce *m)
937 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
939 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
941 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
946 static void mce_clear_state(unsigned long *toclear)
950 for (i = 0; i < banks; i++) {
951 if (test_bit(i, toclear))
952 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
957 * Need to save faulting physical address associated with a process
958 * in the machine check handler some place where we can grab it back
959 * later in mce_notify_process()
961 #define MCE_INFO_MAX 16
965 struct task_struct *t;
968 } mce_info[MCE_INFO_MAX];
970 static void mce_save_info(__u64 addr, int c)
974 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
975 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
983 mce_panic("Too many concurrent recoverable errors", NULL, NULL);
986 static struct mce_info *mce_find_info(void)
990 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
991 if (atomic_read(&mi->inuse) && mi->t == current)
996 static void mce_clear_info(struct mce_info *mi)
998 atomic_set(&mi->inuse, 0);
1002 * The actual machine check handler. This only handles real
1003 * exceptions when something got corrupted coming in through int 18.
1005 * This is executed in NMI context not subject to normal locking rules. This
1006 * implies that most kernel services cannot be safely used. Don't even
1007 * think about putting a printk in there!
1009 * On Intel systems this is entered on all CPUs in parallel through
1010 * MCE broadcast. However some CPUs might be broken beyond repair,
1011 * so be always careful when synchronizing with others.
1013 void do_machine_check(struct pt_regs *regs, long error_code)
1015 struct mce m, *final;
1020 * Establish sequential order between the CPUs entering the machine
1025 * If no_way_out gets set, there is no safe way to recover from this
1026 * MCE. If tolerant is cranked up, we'll try anyway.
1030 * If kill_it gets set, there might be a way to recover from this
1034 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1035 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1036 char *msg = "Unknown";
1038 atomic_inc(&mce_entry);
1040 this_cpu_inc(mce_exception_count);
1045 mce_gather_info(&m, regs);
1047 final = &__get_cpu_var(mces_seen);
1050 memset(valid_banks, 0, sizeof(valid_banks));
1051 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1056 * When no restart IP might need to kill or panic.
1057 * Assume the worst for now, but if we find the
1058 * severity is MCE_AR_SEVERITY we have other options.
1060 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1064 * Go through all the banks in exclusion of the other CPUs.
1065 * This way we don't report duplicated events on shared banks
1066 * because the first one to see it will clear it.
1068 order = mce_start(&no_way_out);
1069 for (i = 0; i < banks; i++) {
1070 __clear_bit(i, toclear);
1071 if (!test_bit(i, valid_banks))
1073 if (!mce_banks[i].ctl)
1080 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
1081 if ((m.status & MCI_STATUS_VAL) == 0)
1085 * Non uncorrected or non signaled errors are handled by
1086 * machine_check_poll. Leave them alone, unless this panics.
1088 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1093 * Set taint even when machine check was not enabled.
1095 add_taint(TAINT_MACHINE_CHECK);
1097 severity = mce_severity(&m, tolerant, NULL);
1100 * When machine check was for corrected handler don't touch,
1101 * unless we're panicing.
1103 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1105 __set_bit(i, toclear);
1106 if (severity == MCE_NO_SEVERITY) {
1108 * Machine check event was not enabled. Clear, but
1114 mce_read_aux(&m, i);
1117 * Action optional error. Queue address for later processing.
1118 * When the ring overflows we just ignore the AO error.
1119 * RED-PEN add some logging mechanism when
1120 * usable_address or mce_add_ring fails.
1121 * RED-PEN don't ignore overflow for tolerant == 0
1123 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1124 mce_ring_add(m.addr >> PAGE_SHIFT);
1128 if (severity > worst) {
1134 /* mce_clear_state will clear *final, save locally for use later */
1138 mce_clear_state(toclear);
1141 * Do most of the synchronization with other CPUs.
1142 * When there's any problem use only local no_way_out state.
1144 if (mce_end(order) < 0)
1145 no_way_out = worst >= MCE_PANIC_SEVERITY;
1148 * At insane "tolerant" levels we take no action. Otherwise
1149 * we only die if we have no other choice. For less serious
1150 * issues we try to recover, or limit damage to the current
1155 mce_panic("Fatal machine check on current CPU", &m, msg);
1156 if (worst == MCE_AR_SEVERITY) {
1157 /* schedule action before return to userland */
1158 mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV);
1159 set_thread_flag(TIF_MCE_NOTIFY);
1160 } else if (kill_it) {
1161 force_sig(SIGBUS, current);
1166 mce_report_event(regs);
1167 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1169 atomic_dec(&mce_entry);
1172 EXPORT_SYMBOL_GPL(do_machine_check);
1174 #ifndef CONFIG_MEMORY_FAILURE
1175 int memory_failure(unsigned long pfn, int vector, int flags)
1177 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1178 BUG_ON(flags & MF_ACTION_REQUIRED);
1179 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1180 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1188 * Called in process context that interrupted by MCE and marked with
1189 * TIF_MCE_NOTIFY, just before returning to erroneous userland.
1190 * This code is allowed to sleep.
1191 * Attempt possible recovery such as calling the high level VM handler to
1192 * process any corrupted pages, and kill/signal current process if required.
1193 * Action required errors are handled here.
1195 void mce_notify_process(void)
1198 struct mce_info *mi = mce_find_info();
1201 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
1202 pfn = mi->paddr >> PAGE_SHIFT;
1204 clear_thread_flag(TIF_MCE_NOTIFY);
1206 pr_err("Uncorrected hardware memory error in user-access at %llx",
1209 * We must call memory_failure() here even if the current process is
1210 * doomed. We still need to mark the page as poisoned and alert any
1211 * other users of the page.
1213 if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 ||
1214 mi->restartable == 0) {
1215 pr_err("Memory error not recovered");
1216 force_sig(SIGBUS, current);
1222 * Action optional processing happens here (picking up
1223 * from the list of faulting pages that do_machine_check()
1224 * placed into the "ring").
1226 static void mce_process_work(struct work_struct *dummy)
1230 while (mce_ring_get(&pfn))
1231 memory_failure(pfn, MCE_VECTOR, 0);
1234 #ifdef CONFIG_X86_MCE_INTEL
1236 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1237 * @cpu: The CPU on which the event occurred.
1238 * @status: Event status information
1240 * This function should be called by the thermal interrupt after the
1241 * event has been processed and the decision was made to log the event
1244 * The status parameter will be saved to the 'status' field of 'struct mce'
1245 * and historically has been the register value of the
1246 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1248 void mce_log_therm_throt_event(__u64 status)
1253 m.bank = MCE_THERMAL_BANK;
1257 #endif /* CONFIG_X86_MCE_INTEL */
1260 * Periodic polling timer for "silent" machine check errors. If the
1261 * poller finds an MCE, poll 2x faster. When the poller finds no more
1262 * errors, poll 2x slower (up to check_interval seconds).
1264 static unsigned long check_interval = 5 * 60; /* 5 minutes */
1266 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1267 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1269 static void mce_timer_fn(unsigned long data)
1271 struct timer_list *t = &__get_cpu_var(mce_timer);
1274 WARN_ON(smp_processor_id() != data);
1276 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1277 machine_check_poll(MCP_TIMESTAMP,
1278 &__get_cpu_var(mce_poll_banks));
1282 * Alert userspace if needed. If we logged an MCE, reduce the
1283 * polling interval, otherwise increase the polling interval.
1285 iv = __this_cpu_read(mce_next_interval);
1286 if (mce_notify_irq())
1287 iv = max(iv / 2, (unsigned long) HZ/100);
1289 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1290 __this_cpu_write(mce_next_interval, iv);
1292 t->expires = jiffies + iv;
1293 add_timer_on(t, smp_processor_id());
1296 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1297 static void mce_timer_delete_all(void)
1301 for_each_online_cpu(cpu)
1302 del_timer_sync(&per_cpu(mce_timer, cpu));
1305 static void mce_do_trigger(struct work_struct *work)
1307 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1310 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1313 * Notify the user(s) about new machine check events.
1314 * Can be called from interrupt context, but not from machine check/NMI
1317 int mce_notify_irq(void)
1319 /* Not more than two messages every minute */
1320 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1322 if (test_and_clear_bit(0, &mce_need_notify)) {
1323 /* wake processes polling /dev/mcelog */
1324 wake_up_interruptible(&mce_chrdev_wait);
1327 * There is no risk of missing notifications because
1328 * work_pending is always cleared before the function is
1331 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1332 schedule_work(&mce_trigger_work);
1334 if (__ratelimit(&ratelimit))
1335 pr_info(HW_ERR "Machine check events logged\n");
1341 EXPORT_SYMBOL_GPL(mce_notify_irq);
1343 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1347 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1350 for (i = 0; i < banks; i++) {
1351 struct mce_bank *b = &mce_banks[i];
1360 * Initialize Machine Checks for a CPU.
1362 static int __cpuinit __mcheck_cpu_cap_init(void)
1367 rdmsrl(MSR_IA32_MCG_CAP, cap);
1369 b = cap & MCG_BANKCNT_MASK;
1371 pr_info("CPU supports %d MCE banks\n", b);
1373 if (b > MAX_NR_BANKS) {
1374 pr_warn("Using only %u machine check banks out of %u\n",
1379 /* Don't support asymmetric configurations today */
1380 WARN_ON(banks != 0 && b != banks);
1383 int err = __mcheck_cpu_mce_banks_init();
1389 /* Use accurate RIP reporting if available. */
1390 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1391 rip_msr = MSR_IA32_MCG_EIP;
1393 if (cap & MCG_SER_P)
1399 static void __mcheck_cpu_init_generic(void)
1401 mce_banks_t all_banks;
1406 * Log the machine checks left over from the previous reset.
1408 bitmap_fill(all_banks, MAX_NR_BANKS);
1409 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1411 set_in_cr4(X86_CR4_MCE);
1413 rdmsrl(MSR_IA32_MCG_CAP, cap);
1414 if (cap & MCG_CTL_P)
1415 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1417 for (i = 0; i < banks; i++) {
1418 struct mce_bank *b = &mce_banks[i];
1422 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1423 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1428 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1429 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1430 * Vol 3B Table 15-20). But this confuses both the code that determines
1431 * whether the machine check occurred in kernel or user mode, and also
1432 * the severity assessment code. Pretend that EIPV was set, and take the
1433 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1435 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1439 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1441 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1442 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1443 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1445 (MCI_STATUS_UC|MCI_STATUS_EN|
1446 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1447 MCI_STATUS_AR|MCACOD_INSTR))
1450 m->mcgstatus |= MCG_STATUS_EIPV;
1455 /* Add per CPU specific workarounds here */
1456 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1458 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1459 pr_info("unknown CPU type - not enabling MCE support\n");
1463 /* This should be disabled by the BIOS, but isn't always */
1464 if (c->x86_vendor == X86_VENDOR_AMD) {
1465 if (c->x86 == 15 && banks > 4) {
1467 * disable GART TBL walk error reporting, which
1468 * trips off incorrectly with the IOMMU & 3ware
1471 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1473 if (c->x86 <= 17 && mce_bootlog < 0) {
1475 * Lots of broken BIOS around that don't clear them
1476 * by default and leave crap in there. Don't log:
1481 * Various K7s with broken bank 0 around. Always disable
1484 if (c->x86 == 6 && banks > 0)
1485 mce_banks[0].ctl = 0;
1488 * Turn off MC4_MISC thresholding banks on those models since
1489 * they're not supported there.
1491 if (c->x86 == 0x15 &&
1492 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1497 0x00000413, /* MC4_MISC0 */
1498 0xc0000408, /* MC4_MISC1 */
1501 rdmsrl(MSR_K7_HWCR, hwcr);
1503 /* McStatusWrEn has to be set */
1504 need_toggle = !(hwcr & BIT(18));
1507 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1509 for (i = 0; i < ARRAY_SIZE(msrs); i++) {
1510 rdmsrl(msrs[i], val);
1513 if (val & BIT_64(62)) {
1515 wrmsrl(msrs[i], val);
1519 /* restore old settings */
1521 wrmsrl(MSR_K7_HWCR, hwcr);
1525 if (c->x86_vendor == X86_VENDOR_INTEL) {
1527 * SDM documents that on family 6 bank 0 should not be written
1528 * because it aliases to another special BIOS controlled
1530 * But it's not aliased anymore on model 0x1a+
1531 * Don't ignore bank 0 completely because there could be a
1532 * valid event later, merely don't write CTL0.
1535 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1536 mce_banks[0].init = 0;
1539 * All newer Intel systems support MCE broadcasting. Enable
1540 * synchronization with a one second timeout.
1542 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1543 monarch_timeout < 0)
1544 monarch_timeout = USEC_PER_SEC;
1547 * There are also broken BIOSes on some Pentium M and
1550 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1553 if (c->x86 == 6 && c->x86_model == 45)
1554 quirk_no_way_out = quirk_sandybridge_ifu;
1556 if (monarch_timeout < 0)
1557 monarch_timeout = 0;
1558 if (mce_bootlog != 0)
1559 mce_panic_timeout = 30;
1564 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1569 switch (c->x86_vendor) {
1570 case X86_VENDOR_INTEL:
1571 intel_p5_mcheck_init(c);
1574 case X86_VENDOR_CENTAUR:
1575 winchip_mcheck_init(c);
1583 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1585 switch (c->x86_vendor) {
1586 case X86_VENDOR_INTEL:
1587 mce_intel_feature_init(c);
1589 case X86_VENDOR_AMD:
1590 mce_amd_feature_init(c);
1597 static void __mcheck_cpu_init_timer(void)
1599 struct timer_list *t = &__get_cpu_var(mce_timer);
1600 unsigned long iv = check_interval * HZ;
1602 setup_timer(t, mce_timer_fn, smp_processor_id());
1607 __this_cpu_write(mce_next_interval, iv);
1610 t->expires = round_jiffies(jiffies + iv);
1611 add_timer_on(t, smp_processor_id());
1614 /* Handle unconfigured int18 (should never happen) */
1615 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1617 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1618 smp_processor_id());
1621 /* Call the installed machine check handler for this CPU setup. */
1622 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1623 unexpected_machine_check;
1626 * Called for each booted CPU to set up machine checks.
1627 * Must be called with preempt off:
1629 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1634 if (__mcheck_cpu_ancient_init(c))
1637 if (!mce_available(c))
1640 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1645 machine_check_vector = do_machine_check;
1647 __mcheck_cpu_init_generic();
1648 __mcheck_cpu_init_vendor(c);
1649 __mcheck_cpu_init_timer();
1650 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1651 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1655 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1658 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1659 static int mce_chrdev_open_count; /* #times opened */
1660 static int mce_chrdev_open_exclu; /* already open exclusive? */
1662 static int mce_chrdev_open(struct inode *inode, struct file *file)
1664 spin_lock(&mce_chrdev_state_lock);
1666 if (mce_chrdev_open_exclu ||
1667 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1668 spin_unlock(&mce_chrdev_state_lock);
1673 if (file->f_flags & O_EXCL)
1674 mce_chrdev_open_exclu = 1;
1675 mce_chrdev_open_count++;
1677 spin_unlock(&mce_chrdev_state_lock);
1679 return nonseekable_open(inode, file);
1682 static int mce_chrdev_release(struct inode *inode, struct file *file)
1684 spin_lock(&mce_chrdev_state_lock);
1686 mce_chrdev_open_count--;
1687 mce_chrdev_open_exclu = 0;
1689 spin_unlock(&mce_chrdev_state_lock);
1694 static void collect_tscs(void *data)
1696 unsigned long *cpu_tsc = (unsigned long *)data;
1698 rdtscll(cpu_tsc[smp_processor_id()]);
1701 static int mce_apei_read_done;
1703 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1704 static int __mce_read_apei(char __user **ubuf, size_t usize)
1710 if (usize < sizeof(struct mce))
1713 rc = apei_read_mce(&m, &record_id);
1714 /* Error or no more MCE record */
1716 mce_apei_read_done = 1;
1718 * When ERST is disabled, mce_chrdev_read() should return
1719 * "no record" instead of "no device."
1726 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1729 * In fact, we should have cleared the record after that has
1730 * been flushed to the disk or sent to network in
1731 * /sbin/mcelog, but we have no interface to support that now,
1732 * so just clear it to avoid duplication.
1734 rc = apei_clear_mce(record_id);
1736 mce_apei_read_done = 1;
1739 *ubuf += sizeof(struct mce);
1744 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1745 size_t usize, loff_t *off)
1747 char __user *buf = ubuf;
1748 unsigned long *cpu_tsc;
1749 unsigned prev, next;
1752 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1756 mutex_lock(&mce_chrdev_read_mutex);
1758 if (!mce_apei_read_done) {
1759 err = __mce_read_apei(&buf, usize);
1760 if (err || buf != ubuf)
1764 next = rcu_dereference_check_mce(mcelog.next);
1766 /* Only supports full reads right now */
1768 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1774 for (i = prev; i < next; i++) {
1775 unsigned long start = jiffies;
1776 struct mce *m = &mcelog.entry[i];
1778 while (!m->finished) {
1779 if (time_after_eq(jiffies, start + 2)) {
1780 memset(m, 0, sizeof(*m));
1786 err |= copy_to_user(buf, m, sizeof(*m));
1792 memset(mcelog.entry + prev, 0,
1793 (next - prev) * sizeof(struct mce));
1795 next = cmpxchg(&mcelog.next, prev, 0);
1796 } while (next != prev);
1798 synchronize_sched();
1801 * Collect entries that were still getting written before the
1804 on_each_cpu(collect_tscs, cpu_tsc, 1);
1806 for (i = next; i < MCE_LOG_LEN; i++) {
1807 struct mce *m = &mcelog.entry[i];
1809 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1810 err |= copy_to_user(buf, m, sizeof(*m));
1813 memset(m, 0, sizeof(*m));
1821 mutex_unlock(&mce_chrdev_read_mutex);
1824 return err ? err : buf - ubuf;
1827 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1829 poll_wait(file, &mce_chrdev_wait, wait);
1830 if (rcu_access_index(mcelog.next))
1831 return POLLIN | POLLRDNORM;
1832 if (!mce_apei_read_done && apei_check_mce())
1833 return POLLIN | POLLRDNORM;
1837 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1840 int __user *p = (int __user *)arg;
1842 if (!capable(CAP_SYS_ADMIN))
1846 case MCE_GET_RECORD_LEN:
1847 return put_user(sizeof(struct mce), p);
1848 case MCE_GET_LOG_LEN:
1849 return put_user(MCE_LOG_LEN, p);
1850 case MCE_GETCLEAR_FLAGS: {
1854 flags = mcelog.flags;
1855 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1857 return put_user(flags, p);
1864 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1865 size_t usize, loff_t *off);
1867 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1868 const char __user *ubuf,
1869 size_t usize, loff_t *off))
1873 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1875 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1876 size_t usize, loff_t *off)
1879 return mce_write(filp, ubuf, usize, off);
1884 static const struct file_operations mce_chrdev_ops = {
1885 .open = mce_chrdev_open,
1886 .release = mce_chrdev_release,
1887 .read = mce_chrdev_read,
1888 .write = mce_chrdev_write,
1889 .poll = mce_chrdev_poll,
1890 .unlocked_ioctl = mce_chrdev_ioctl,
1891 .llseek = no_llseek,
1894 static struct miscdevice mce_chrdev_device = {
1901 * mce=off Disables machine check
1902 * mce=no_cmci Disables CMCI
1903 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1904 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1905 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1906 * monarchtimeout is how long to wait for other CPUs on machine
1907 * check, or 0 to not wait
1908 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1909 * mce=nobootlog Don't log MCEs from before booting.
1911 static int __init mcheck_enable(char *str)
1919 if (!strcmp(str, "off"))
1921 else if (!strcmp(str, "no_cmci"))
1922 mce_cmci_disabled = 1;
1923 else if (!strcmp(str, "dont_log_ce"))
1924 mce_dont_log_ce = 1;
1925 else if (!strcmp(str, "ignore_ce"))
1927 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1928 mce_bootlog = (str[0] == 'b');
1929 else if (isdigit(str[0])) {
1930 get_option(&str, &tolerant);
1933 get_option(&str, &monarch_timeout);
1936 pr_info("mce argument %s ignored. Please use /sys\n", str);
1941 __setup("mce", mcheck_enable);
1943 int __init mcheck_init(void)
1945 mcheck_intel_therm_init();
1951 * mce_syscore: PM support
1955 * Disable machine checks on suspend and shutdown. We can't really handle
1958 static int mce_disable_error_reporting(void)
1962 for (i = 0; i < banks; i++) {
1963 struct mce_bank *b = &mce_banks[i];
1966 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1971 static int mce_syscore_suspend(void)
1973 return mce_disable_error_reporting();
1976 static void mce_syscore_shutdown(void)
1978 mce_disable_error_reporting();
1982 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1983 * Only one CPU is active at this time, the others get re-added later using
1986 static void mce_syscore_resume(void)
1988 __mcheck_cpu_init_generic();
1989 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1992 static struct syscore_ops mce_syscore_ops = {
1993 .suspend = mce_syscore_suspend,
1994 .shutdown = mce_syscore_shutdown,
1995 .resume = mce_syscore_resume,
1999 * mce_device: Sysfs support
2002 static void mce_cpu_restart(void *data)
2004 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2006 __mcheck_cpu_init_generic();
2007 __mcheck_cpu_init_timer();
2010 /* Reinit MCEs after user configuration changes */
2011 static void mce_restart(void)
2013 mce_timer_delete_all();
2014 on_each_cpu(mce_cpu_restart, NULL, 1);
2017 /* Toggle features for corrected errors */
2018 static void mce_disable_cmci(void *data)
2020 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2025 static void mce_enable_ce(void *all)
2027 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2032 __mcheck_cpu_init_timer();
2035 static struct bus_type mce_subsys = {
2036 .name = "machinecheck",
2037 .dev_name = "machinecheck",
2040 DEFINE_PER_CPU(struct device *, mce_device);
2043 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
2045 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2047 return container_of(attr, struct mce_bank, attr);
2050 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2053 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2056 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2057 const char *buf, size_t size)
2061 if (strict_strtoull(buf, 0, &new) < 0)
2064 attr_to_bank(attr)->ctl = new;
2071 show_trigger(struct device *s, struct device_attribute *attr, char *buf)
2073 strcpy(buf, mce_helper);
2075 return strlen(mce_helper) + 1;
2078 static ssize_t set_trigger(struct device *s, struct device_attribute *attr,
2079 const char *buf, size_t siz)
2083 strncpy(mce_helper, buf, sizeof(mce_helper));
2084 mce_helper[sizeof(mce_helper)-1] = 0;
2085 p = strchr(mce_helper, '\n');
2090 return strlen(mce_helper) + !!p;
2093 static ssize_t set_ignore_ce(struct device *s,
2094 struct device_attribute *attr,
2095 const char *buf, size_t size)
2099 if (strict_strtoull(buf, 0, &new) < 0)
2102 if (mce_ignore_ce ^ !!new) {
2104 /* disable ce features */
2105 mce_timer_delete_all();
2106 on_each_cpu(mce_disable_cmci, NULL, 1);
2109 /* enable ce features */
2111 on_each_cpu(mce_enable_ce, (void *)1, 1);
2117 static ssize_t set_cmci_disabled(struct device *s,
2118 struct device_attribute *attr,
2119 const char *buf, size_t size)
2123 if (strict_strtoull(buf, 0, &new) < 0)
2126 if (mce_cmci_disabled ^ !!new) {
2129 on_each_cpu(mce_disable_cmci, NULL, 1);
2130 mce_cmci_disabled = 1;
2133 mce_cmci_disabled = 0;
2134 on_each_cpu(mce_enable_ce, NULL, 1);
2140 static ssize_t store_int_with_restart(struct device *s,
2141 struct device_attribute *attr,
2142 const char *buf, size_t size)
2144 ssize_t ret = device_store_int(s, attr, buf, size);
2149 static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger);
2150 static DEVICE_INT_ATTR(tolerant, 0644, tolerant);
2151 static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
2152 static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
2154 static struct dev_ext_attribute dev_attr_check_interval = {
2155 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2159 static struct dev_ext_attribute dev_attr_ignore_ce = {
2160 __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce),
2164 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2165 __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled),
2169 static struct device_attribute *mce_device_attrs[] = {
2170 &dev_attr_tolerant.attr,
2171 &dev_attr_check_interval.attr,
2173 &dev_attr_monarch_timeout.attr,
2174 &dev_attr_dont_log_ce.attr,
2175 &dev_attr_ignore_ce.attr,
2176 &dev_attr_cmci_disabled.attr,
2180 static cpumask_var_t mce_device_initialized;
2182 static void mce_device_release(struct device *dev)
2187 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2188 static __cpuinit int mce_device_create(unsigned int cpu)
2194 if (!mce_available(&boot_cpu_data))
2197 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2201 dev->bus = &mce_subsys;
2202 dev->release = &mce_device_release;
2204 err = device_register(dev);
2208 for (i = 0; mce_device_attrs[i]; i++) {
2209 err = device_create_file(dev, mce_device_attrs[i]);
2213 for (j = 0; j < banks; j++) {
2214 err = device_create_file(dev, &mce_banks[j].attr);
2218 cpumask_set_cpu(cpu, mce_device_initialized);
2219 per_cpu(mce_device, cpu) = dev;
2224 device_remove_file(dev, &mce_banks[j].attr);
2227 device_remove_file(dev, mce_device_attrs[i]);
2229 device_unregister(dev);
2234 static __cpuinit void mce_device_remove(unsigned int cpu)
2236 struct device *dev = per_cpu(mce_device, cpu);
2239 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2242 for (i = 0; mce_device_attrs[i]; i++)
2243 device_remove_file(dev, mce_device_attrs[i]);
2245 for (i = 0; i < banks; i++)
2246 device_remove_file(dev, &mce_banks[i].attr);
2248 device_unregister(dev);
2249 cpumask_clear_cpu(cpu, mce_device_initialized);
2250 per_cpu(mce_device, cpu) = NULL;
2253 /* Make sure there are no machine checks on offlined CPUs. */
2254 static void __cpuinit mce_disable_cpu(void *h)
2256 unsigned long action = *(unsigned long *)h;
2259 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2262 if (!(action & CPU_TASKS_FROZEN))
2264 for (i = 0; i < banks; i++) {
2265 struct mce_bank *b = &mce_banks[i];
2268 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2272 static void __cpuinit mce_reenable_cpu(void *h)
2274 unsigned long action = *(unsigned long *)h;
2277 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2280 if (!(action & CPU_TASKS_FROZEN))
2282 for (i = 0; i < banks; i++) {
2283 struct mce_bank *b = &mce_banks[i];
2286 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2290 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2291 static int __cpuinit
2292 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2294 unsigned int cpu = (unsigned long)hcpu;
2295 struct timer_list *t = &per_cpu(mce_timer, cpu);
2299 case CPU_ONLINE_FROZEN:
2300 mce_device_create(cpu);
2301 if (threshold_cpu_callback)
2302 threshold_cpu_callback(action, cpu);
2305 case CPU_DEAD_FROZEN:
2306 if (threshold_cpu_callback)
2307 threshold_cpu_callback(action, cpu);
2308 mce_device_remove(cpu);
2310 case CPU_DOWN_PREPARE:
2311 case CPU_DOWN_PREPARE_FROZEN:
2313 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2315 case CPU_DOWN_FAILED:
2316 case CPU_DOWN_FAILED_FROZEN:
2317 if (!mce_ignore_ce && check_interval) {
2318 t->expires = round_jiffies(jiffies +
2319 per_cpu(mce_next_interval, cpu));
2320 add_timer_on(t, cpu);
2322 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2325 /* intentionally ignoring frozen here */
2326 cmci_rediscover(cpu);
2332 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2333 .notifier_call = mce_cpu_callback,
2336 static __init void mce_init_banks(void)
2340 for (i = 0; i < banks; i++) {
2341 struct mce_bank *b = &mce_banks[i];
2342 struct device_attribute *a = &b->attr;
2344 sysfs_attr_init(&a->attr);
2345 a->attr.name = b->attrname;
2346 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2348 a->attr.mode = 0644;
2349 a->show = show_bank;
2350 a->store = set_bank;
2354 static __init int mcheck_init_device(void)
2359 if (!mce_available(&boot_cpu_data))
2362 zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL);
2366 err = subsys_system_register(&mce_subsys, NULL);
2370 for_each_online_cpu(i) {
2371 err = mce_device_create(i);
2376 register_syscore_ops(&mce_syscore_ops);
2377 register_hotcpu_notifier(&mce_cpu_notifier);
2379 /* register character device /dev/mcelog */
2380 misc_register(&mce_chrdev_device);
2384 device_initcall(mcheck_init_device);
2387 * Old style boot options parsing. Only for compatibility.
2389 static int __init mcheck_disable(char *str)
2394 __setup("nomce", mcheck_disable);
2396 #ifdef CONFIG_DEBUG_FS
2397 struct dentry *mce_get_debugfs_dir(void)
2399 static struct dentry *dmce;
2402 dmce = debugfs_create_dir("mce", NULL);
2407 static void mce_reset(void)
2410 atomic_set(&mce_fake_paniced, 0);
2411 atomic_set(&mce_executing, 0);
2412 atomic_set(&mce_callin, 0);
2413 atomic_set(&global_nwo, 0);
2416 static int fake_panic_get(void *data, u64 *val)
2422 static int fake_panic_set(void *data, u64 val)
2429 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2430 fake_panic_set, "%llu\n");
2432 static int __init mcheck_debugfs_init(void)
2434 struct dentry *dmce, *ffake_panic;
2436 dmce = mce_get_debugfs_dir();
2439 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2446 late_initcall(mcheck_debugfs_init);