2 * AMD CPU Microcode Update Driver for Linux
4 * This driver allows to upgrade microcode on F10h AMD
7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * Author: Peter Oruba <peter.oruba@amd.com>
12 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
15 * Copyright (C) 2013 Advanced Micro Devices, Inc.
17 * Author: Jacob Shin <jacob.shin@amd.com>
18 * Fixes: Borislav Petkov <bp@suse.de>
20 * Licensed under the terms of the GNU General Public
21 * License version 2. See file COPYING for details.
23 #define pr_fmt(fmt) "microcode: " fmt
25 #include <linux/earlycpio.h>
26 #include <linux/firmware.h>
27 #include <linux/uaccess.h>
28 #include <linux/vmalloc.h>
29 #include <linux/initrd.h>
30 #include <linux/kernel.h>
31 #include <linux/pci.h>
33 #include <asm/microcode_amd.h>
34 #include <asm/microcode.h>
35 #include <asm/processor.h>
36 #include <asm/setup.h>
40 static struct equiv_cpu_entry *equiv_cpu_table;
43 struct list_head plist;
49 static LIST_HEAD(pcache);
52 * This points to the current valid container of microcode patches which we will
53 * save from the initrd before jettisoning its contents.
56 static size_t container_size;
58 static u32 ucode_new_rev;
59 u8 amd_ucode_patch[PATCH_MAX_SIZE];
60 static u16 this_equiv_id;
62 static struct cpio_data ucode_cpio;
65 * Microcode patch container file is prepended to the initrd in cpio format.
66 * See Documentation/x86/early-microcode.txt
68 static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
70 static struct cpio_data __init find_ucode_in_initrd(void)
78 struct boot_params *p;
81 * On 32-bit, early load occurs before paging is turned on so we need
82 * to use physical addresses.
84 p = (struct boot_params *)__pa_nodebug(&boot_params);
85 path = (char *)__pa_nodebug(ucode_path);
86 start = (void *)p->hdr.ramdisk_image;
87 size = p->hdr.ramdisk_size;
90 start = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
91 size = boot_params.hdr.ramdisk_size;
94 return find_cpio_data(path, start, size, &offset);
97 static size_t compute_container_size(u8 *data, u32 total_size)
100 u32 *header = (u32 *)data;
102 if (header[0] != UCODE_MAGIC ||
103 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
104 header[2] == 0) /* size */
107 size = header[2] + CONTAINER_HDR_SZ;
114 header = (u32 *)data;
116 if (header[0] != UCODE_UCODE_TYPE)
120 * Sanity-check patch size.
122 patch_size = header[1];
123 if (patch_size > PATCH_MAX_SIZE)
126 size += patch_size + SECTION_HDR_SIZE;
127 data += patch_size + SECTION_HDR_SIZE;
128 total_size -= patch_size + SECTION_HDR_SIZE;
135 * Early load occurs before we can vmalloc(). So we look for the microcode
136 * patch container file in initrd, traverse equivalent cpu table, look for a
137 * matching microcode patch, and update, all in initrd memory in place.
138 * When vmalloc() is available for use later -- on 64-bit during first AP load,
139 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
140 * load_microcode_amd() to save equivalent cpu table and microcode patches in
141 * kernel heap memory.
143 static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
145 struct equiv_cpu_entry *eq;
149 u8 (*patch)[PATCH_MAX_SIZE];
152 u32 rev, eax, ebx, ecx, edx;
156 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
157 cont_sz = (size_t *)__pa_nodebug(&container_size);
158 cont = (u8 **)__pa_nodebug(&container);
159 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
161 new_rev = &ucode_new_rev;
162 cont_sz = &container_size;
164 patch = &amd_ucode_patch;
169 header = (u32 *)data;
171 /* find equiv cpu table */
172 if (header[0] != UCODE_MAGIC ||
173 header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
174 header[2] == 0) /* size */
179 native_cpuid(&eax, &ebx, &ecx, &edx);
182 eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
186 /* Advance past the container header */
187 offset = header[2] + CONTAINER_HDR_SZ;
191 eq_id = find_equiv_id(eq, eax);
193 this_equiv_id = eq_id;
194 *cont_sz = compute_container_size(*cont, left + offset);
197 * truncate how much we need to iterate over in the
198 * ucode update loop below
200 left = *cont_sz - offset;
205 * support multiple container files appended together. if this
206 * one does not have a matching equivalent cpu entry, we fast
207 * forward to the next container file.
210 header = (u32 *)data;
211 if (header[0] == UCODE_MAGIC &&
212 header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
215 offset = header[1] + SECTION_HDR_SIZE;
220 /* mark where the next microcode container file starts */
221 offset = data - (u8 *)ucode;
231 if (check_current_patch_level(&rev, true))
235 struct microcode_amd *mc;
237 header = (u32 *)data;
238 if (header[0] != UCODE_UCODE_TYPE || /* type */
239 header[1] == 0) /* size */
242 mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
244 if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
246 if (!__apply_microcode_amd(mc)) {
247 rev = mc->hdr.patch_id;
252 min_t(u32, header[1], PATCH_MAX_SIZE));
256 offset = header[1] + SECTION_HDR_SIZE;
262 static bool __init load_builtin_amd_microcode(struct cpio_data *cp,
266 char fw_name[36] = "amd-ucode/microcode_amd.bin";
269 snprintf(fw_name, sizeof(fw_name),
270 "amd-ucode/microcode_amd_fam%.2xh.bin", family);
272 return get_builtin_firmware(cp, fw_name);
278 void __init load_ucode_amd_bsp(unsigned int family)
285 data = (void **)__pa_nodebug(&ucode_cpio.data);
286 size = (size_t *)__pa_nodebug(&ucode_cpio.size);
288 data = &ucode_cpio.data;
289 size = &ucode_cpio.size;
292 cp = find_ucode_in_initrd();
294 if (!load_builtin_amd_microcode(&cp, family))
301 apply_ucode_in_initrd(cp.data, cp.size, true);
306 * On 32-bit, since AP's early load occurs before paging is turned on, we
307 * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
308 * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
309 * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
310 * which is used upon resume from suspend.
312 void load_ucode_amd_ap(void)
314 struct microcode_amd *mc;
318 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
319 if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
320 __apply_microcode_amd(mc);
324 ucode = (void *)__pa_nodebug(&container);
325 usize = (size_t *)__pa_nodebug(&container_size);
327 if (!*ucode || !*usize)
330 apply_ucode_in_initrd(*ucode, *usize, false);
333 static void __init collect_cpu_sig_on_bsp(void *arg)
335 unsigned int cpu = smp_processor_id();
336 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
338 uci->cpu_sig.sig = cpuid_eax(0x00000001);
341 static void __init get_bsp_sig(void)
343 unsigned int bsp = boot_cpu_data.cpu_index;
344 struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
346 if (!uci->cpu_sig.sig)
347 smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
350 void load_ucode_amd_ap(void)
352 unsigned int cpu = smp_processor_id();
353 struct equiv_cpu_entry *eq;
354 struct microcode_amd *mc;
358 /* Exit if called on the BSP. */
366 * 64-bit runs with paging enabled, thus early==false.
368 if (check_current_patch_level(&rev, false))
371 eax = cpuid_eax(0x00000001);
372 eq = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
374 eq_id = find_equiv_id(eq, eax);
378 if (eq_id == this_equiv_id) {
379 mc = (struct microcode_amd *)amd_ucode_patch;
381 if (mc && rev < mc->hdr.patch_id) {
382 if (!__apply_microcode_amd(mc))
383 ucode_new_rev = mc->hdr.patch_id;
387 if (!ucode_cpio.data)
391 * AP has a different equivalence ID than BSP, looks like
392 * mixed-steppings silicon so go through the ucode blob anew.
394 apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
399 int __init save_microcode_in_initrd_amd(void)
403 enum ucode_state ret;
412 cont = (unsigned long)container;
413 cont_va = __va(container);
416 * We need the physical address of the container for both bitness since
417 * boot_params.hdr.ramdisk_image is a physical address.
419 cont = __pa(container);
424 * Take into account the fact that the ramdisk might get relocated and
425 * therefore we need to recompute the container's position in virtual
428 if (relocated_ramdisk)
429 container = (u8 *)(__va(relocated_ramdisk) +
430 (cont - boot_params.hdr.ramdisk_image));
435 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
438 eax = cpuid_eax(0x00000001);
439 eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
441 ret = load_microcode_amd(smp_processor_id(), eax, container, container_size);
446 * This will be freed any msec now, stash patches for the current
447 * family and switch to patch cache for cpu hotplug, etc later.
455 void reload_ucode_amd(void)
457 struct microcode_amd *mc;
461 * early==false because this is a syscore ->resume path and by
462 * that time paging is long enabled.
464 if (check_current_patch_level(&rev, false))
467 mc = (struct microcode_amd *)amd_ucode_patch;
469 if (mc && rev < mc->hdr.patch_id) {
470 if (!__apply_microcode_amd(mc)) {
471 ucode_new_rev = mc->hdr.patch_id;
472 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
476 static u16 __find_equiv_id(unsigned int cpu)
478 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
479 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
482 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
486 BUG_ON(!equiv_cpu_table);
488 while (equiv_cpu_table[i].equiv_cpu != 0) {
489 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
490 return equiv_cpu_table[i].installed_cpu;
497 * a small, trivial cache of per-family ucode patches
499 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
501 struct ucode_patch *p;
503 list_for_each_entry(p, &pcache, plist)
504 if (p->equiv_cpu == equiv_cpu)
509 static void update_cache(struct ucode_patch *new_patch)
511 struct ucode_patch *p;
513 list_for_each_entry(p, &pcache, plist) {
514 if (p->equiv_cpu == new_patch->equiv_cpu) {
515 if (p->patch_id >= new_patch->patch_id)
516 /* we already have the latest patch */
519 list_replace(&p->plist, &new_patch->plist);
525 /* no patch found, add it */
526 list_add_tail(&new_patch->plist, &pcache);
529 static void free_cache(void)
531 struct ucode_patch *p, *tmp;
533 list_for_each_entry_safe(p, tmp, &pcache, plist) {
534 __list_del(p->plist.prev, p->plist.next);
540 static struct ucode_patch *find_patch(unsigned int cpu)
544 equiv_id = __find_equiv_id(cpu);
548 return cache_find_patch(equiv_id);
551 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
553 struct cpuinfo_x86 *c = &cpu_data(cpu);
554 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
555 struct ucode_patch *p;
557 csig->sig = cpuid_eax(0x00000001);
558 csig->rev = c->microcode;
561 * a patch could have been loaded early, set uci->mc so that
562 * mc_bp_resume() can call apply_microcode()
565 if (p && (p->patch_id == csig->rev))
568 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
573 static unsigned int verify_patch_size(u8 family, u32 patch_size,
578 #define F1XH_MPB_MAX_SIZE 2048
579 #define F14H_MPB_MAX_SIZE 1824
580 #define F15H_MPB_MAX_SIZE 4096
581 #define F16H_MPB_MAX_SIZE 3458
585 max_size = F14H_MPB_MAX_SIZE;
588 max_size = F15H_MPB_MAX_SIZE;
591 max_size = F16H_MPB_MAX_SIZE;
594 max_size = F1XH_MPB_MAX_SIZE;
598 if (patch_size > min_t(u32, size, max_size)) {
599 pr_err("patch size mismatch\n");
607 * Those patch levels cannot be updated to newer ones and thus should be final.
609 static u32 final_levels[] = {
613 0, /* T-101 terminator */
617 * Check the current patch level on this CPU.
619 * @rev: Use it to return the patch level. It is set to 0 in the case of
623 * - true: if update should stop
626 bool check_current_patch_level(u32 *rev, bool early)
632 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
634 if (IS_ENABLED(CONFIG_X86_32) && early)
635 levels = (u32 *)__pa_nodebug(&final_levels);
637 levels = final_levels;
639 for (i = 0; levels[i]; i++) {
640 if (lvl == levels[i]) {
653 int __apply_microcode_amd(struct microcode_amd *mc_amd)
657 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
659 /* verify patch application was successful */
660 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
661 if (rev != mc_amd->hdr.patch_id)
667 int apply_microcode_amd(int cpu)
669 struct cpuinfo_x86 *c = &cpu_data(cpu);
670 struct microcode_amd *mc_amd;
671 struct ucode_cpu_info *uci;
672 struct ucode_patch *p;
675 BUG_ON(raw_smp_processor_id() != cpu);
677 uci = ucode_cpu_info + cpu;
686 if (check_current_patch_level(&rev, false))
689 /* need to apply patch? */
690 if (rev >= mc_amd->hdr.patch_id) {
692 uci->cpu_sig.rev = rev;
696 if (__apply_microcode_amd(mc_amd)) {
697 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
698 cpu, mc_amd->hdr.patch_id);
701 pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
702 mc_amd->hdr.patch_id);
704 uci->cpu_sig.rev = mc_amd->hdr.patch_id;
705 c->microcode = mc_amd->hdr.patch_id;
710 static int install_equiv_cpu_table(const u8 *buf)
712 unsigned int *ibuf = (unsigned int *)buf;
713 unsigned int type = ibuf[1];
714 unsigned int size = ibuf[2];
716 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
717 pr_err("empty section/"
718 "invalid type field in container file section header\n");
722 equiv_cpu_table = vmalloc(size);
723 if (!equiv_cpu_table) {
724 pr_err("failed to allocate equivalent CPU table\n");
728 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
730 /* add header length */
731 return size + CONTAINER_HDR_SZ;
734 static void free_equiv_cpu_table(void)
736 vfree(equiv_cpu_table);
737 equiv_cpu_table = NULL;
740 static void cleanup(void)
742 free_equiv_cpu_table();
747 * We return the current size even if some of the checks failed so that
748 * we can skip over the next patch. If we return a negative value, we
749 * signal a grave error like a memory allocation has failed and the
750 * driver cannot continue functioning normally. In such cases, we tear
751 * down everything we've used up so far and exit.
753 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
755 struct microcode_header_amd *mc_hdr;
756 struct ucode_patch *patch;
757 unsigned int patch_size, crnt_size, ret;
761 patch_size = *(u32 *)(fw + 4);
762 crnt_size = patch_size + SECTION_HDR_SIZE;
763 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
764 proc_id = mc_hdr->processor_rev_id;
766 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
768 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
772 /* check if patch is for the current family */
773 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
774 if (proc_fam != family)
777 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
778 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
783 ret = verify_patch_size(family, patch_size, leftover);
785 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
789 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
791 pr_err("Patch allocation failure.\n");
795 patch->data = kzalloc(patch_size, GFP_KERNEL);
797 pr_err("Patch data allocation failure.\n");
802 /* All looks ok, copy patch... */
803 memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
804 INIT_LIST_HEAD(&patch->plist);
805 patch->patch_id = mc_hdr->patch_id;
806 patch->equiv_cpu = proc_id;
808 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
809 __func__, patch->patch_id, proc_id);
811 /* ... and add to cache. */
817 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
820 enum ucode_state ret = UCODE_ERROR;
821 unsigned int leftover;
826 offset = install_equiv_cpu_table(data);
828 pr_err("failed to create equivalent cpu table\n");
832 leftover = size - offset;
834 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
835 pr_err("invalid type field in container file section header\n");
836 free_equiv_cpu_table();
841 crnt_size = verify_and_add_patch(family, fw, leftover);
846 leftover -= crnt_size;
852 enum ucode_state load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
854 enum ucode_state ret;
856 /* free old equiv table */
857 free_equiv_cpu_table();
859 ret = __load_microcode_amd(family, data, size);
865 /* save BSP's matching patch for early load */
866 if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
867 struct ucode_patch *p = find_patch(cpu);
869 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
870 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
879 * AMD microcode firmware naming convention, up to family 15h they are in
882 * amd-ucode/microcode_amd.bin
884 * This legacy file is always smaller than 2K in size.
886 * Beginning with family 15h, they are in family-specific firmware files:
888 * amd-ucode/microcode_amd_fam15h.bin
889 * amd-ucode/microcode_amd_fam16h.bin
892 * These might be larger than 2K.
894 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
897 char fw_name[36] = "amd-ucode/microcode_amd.bin";
898 struct cpuinfo_x86 *c = &cpu_data(cpu);
899 enum ucode_state ret = UCODE_NFOUND;
900 const struct firmware *fw;
902 /* reload ucode container only on the boot cpu */
903 if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
907 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
909 if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
910 pr_debug("failed to load file %s\n", fw_name);
915 if (*(u32 *)fw->data != UCODE_MAGIC) {
916 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
920 ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
923 release_firmware(fw);
929 static enum ucode_state
930 request_microcode_user(int cpu, const void __user *buf, size_t size)
935 static void microcode_fini_cpu_amd(int cpu)
937 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
942 static struct microcode_ops microcode_amd_ops = {
943 .request_microcode_user = request_microcode_user,
944 .request_microcode_fw = request_microcode_amd,
945 .collect_cpu_info = collect_cpu_info_amd,
946 .apply_microcode = apply_microcode_amd,
947 .microcode_fini_cpu = microcode_fini_cpu_amd,
950 struct microcode_ops * __init init_amd_microcode(void)
952 struct cpuinfo_x86 *c = &boot_cpu_data;
954 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
955 pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
959 return µcode_amd_ops;
962 void __exit exit_amd_microcode(void)