1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
36 #include <linux/types.h> /* FIXME: kvm_para.h needs this */
38 #include <linux/stop_machine.h>
39 #include <linux/kvm_para.h>
40 #include <linux/uaccess.h>
41 #include <linux/module.h>
42 #include <linux/mutex.h>
43 #include <linux/init.h>
44 #include <linux/sort.h>
45 #include <linux/cpu.h>
46 #include <linux/pci.h>
47 #include <linux/smp.h>
48 #include <linux/syscore_ops.h>
50 #include <asm/processor.h>
58 /* arch_phys_wc_add returns an MTRR register index plus this offset. */
59 #define MTRR_TO_PHYS_WC_OFFSET 1000
62 static bool __mtrr_enabled;
64 static bool mtrr_enabled(void)
66 return __mtrr_enabled;
69 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
70 static DEFINE_MUTEX(mtrr_mutex);
72 u64 size_or_mask, size_and_mask;
73 static bool mtrr_aps_delayed_init;
75 static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
77 const struct mtrr_ops *mtrr_if;
79 static void set_mtrr(unsigned int reg, unsigned long base,
80 unsigned long size, mtrr_type type);
82 void set_mtrr_ops(const struct mtrr_ops *ops)
84 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
85 mtrr_ops[ops->vendor] = ops;
88 /* Returns non-zero if we have the write-combining memory type */
89 static int have_wrcomb(void)
93 dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
96 * ServerWorks LE chipsets < rev 6 have problems with
97 * write-combining. Don't allow it and leave room for other
98 * chipsets to be tagged
100 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
101 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
102 dev->revision <= 5) {
103 pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
108 * Intel 450NX errata # 23. Non ascending cacheline evictions to
109 * write combining memory may resulting in data corruption
111 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
112 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
113 pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
119 return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
122 /* This function returns the number of variable MTRRs */
123 static void __init set_num_var_ranges(void)
125 unsigned long config = 0, dummy;
128 rdmsr(MSR_MTRRcap, config, dummy);
129 else if (is_cpu(AMD))
131 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
134 num_var_ranges = config & 0xff;
137 static void __init init_table(void)
141 max = num_var_ranges;
142 for (i = 0; i < max; i++)
143 mtrr_usage_table[i] = 1;
146 struct set_mtrr_data {
147 unsigned long smp_base;
148 unsigned long smp_size;
149 unsigned int smp_reg;
154 * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
156 * @info: pointer to mtrr configuration data
160 static int mtrr_rendezvous_handler(void *info)
162 struct set_mtrr_data *data = info;
165 * We use this same function to initialize the mtrrs during boot,
166 * resume, runtime cpu online and on an explicit request to set a
169 * During boot or suspend, the state of the boot cpu's mtrrs has been
170 * saved, and we want to replicate that across all the cpus that come
171 * online (either at the end of boot or resume or during a runtime cpu
172 * online). If we're doing that, @reg is set to something special and on
173 * all the cpu's we do mtrr_if->set_all() (On the logical cpu that
174 * started the boot/resume sequence, this might be a duplicate
177 if (data->smp_reg != ~0U) {
178 mtrr_if->set(data->smp_reg, data->smp_base,
179 data->smp_size, data->smp_type);
180 } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
186 static inline int types_compatible(mtrr_type type1, mtrr_type type2)
188 return type1 == MTRR_TYPE_UNCACHABLE ||
189 type2 == MTRR_TYPE_UNCACHABLE ||
190 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
191 (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
195 * set_mtrr - update mtrrs on all processors
196 * @reg: mtrr in question
201 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
203 * 1. Queue work to do the following on all processors:
204 * 2. Disable Interrupts
205 * 3. Wait for all procs to do so
206 * 4. Enter no-fill cache mode
210 * 8. Disable all range registers
211 * 9. Update the MTRRs
212 * 10. Enable all range registers
213 * 11. Flush all TLBs and caches again
214 * 12. Enter normal cache mode and reenable caching
216 * 14. Wait for buddies to catch up
217 * 15. Enable interrupts.
219 * What does that mean for us? Well, stop_machine() will ensure that
220 * the rendezvous handler is started on each CPU. And in lockstep they
221 * do the state transition of disabling interrupts, updating MTRR's
222 * (the CPU vendors may each do it differently, so we call mtrr_if->set()
223 * callback and let them take care of it.) and enabling interrupts.
225 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
229 set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
231 struct set_mtrr_data data = { .smp_reg = reg,
237 stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask);
240 static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base,
241 unsigned long size, mtrr_type type)
243 struct set_mtrr_data data = { .smp_reg = reg,
249 stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data,
254 * mtrr_add_page - Add a memory type region
255 * @base: Physical base address of region in pages (in units of 4 kB!)
256 * @size: Physical size of region in pages (4 kB)
257 * @type: Type of MTRR desired
258 * @increment: If this is true do usage counting on the region
260 * Memory type region registers control the caching on newer Intel and
261 * non Intel processors. This function allows drivers to request an
262 * MTRR is added. The details and hardware specifics of each processor's
263 * implementation are hidden from the caller, but nevertheless the
264 * caller should expect to need to provide a power of two size on an
265 * equivalent power of two boundary.
267 * If the region cannot be added either because all regions are in use
268 * or the CPU cannot support it a negative value is returned. On success
269 * the register number for this entry is returned, but should be treated
272 * On a multiprocessor machine the changes are made to all processors.
273 * This is required on x86 by the Intel processors.
275 * The available types are
277 * %MTRR_TYPE_UNCACHABLE - No caching
279 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
281 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
283 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
285 * BUGS: Needs a quiet flag for the cases where drivers do not mind
286 * failures and do not wish system log messages to be sent.
288 int mtrr_add_page(unsigned long base, unsigned long size,
289 unsigned int type, bool increment)
291 unsigned long lbase, lsize;
292 int i, replace, error;
298 error = mtrr_if->validate_add_page(base, size, type);
302 if (type >= MTRR_NUM_TYPES) {
303 pr_warning("mtrr: type: %u invalid\n", type);
307 /* If the type is WC, check that this processor supports it */
308 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
309 pr_warning("mtrr: your processor doesn't support write-combining\n");
314 pr_warning("mtrr: zero sized request\n");
318 if ((base | (base + size - 1)) >>
319 (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
320 pr_warning("mtrr: base or size exceeds the MTRR width\n");
327 /* No CPU hotplug when we change MTRR entries */
330 /* Search for existing MTRR */
331 mutex_lock(&mtrr_mutex);
332 for (i = 0; i < num_var_ranges; ++i) {
333 mtrr_if->get(i, &lbase, &lsize, <ype);
334 if (!lsize || base > lbase + lsize - 1 ||
335 base + size - 1 < lbase)
338 * At this point we know there is some kind of
341 if (base < lbase || base + size - 1 > lbase + lsize - 1) {
343 base + size - 1 >= lbase + lsize - 1) {
344 /* New region encloses an existing region */
346 replace = replace == -1 ? i : -2;
348 } else if (types_compatible(type, ltype))
351 pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing"
352 " 0x%lx000,0x%lx000\n", base, size, lbase,
356 /* New region is enclosed by an existing region */
358 if (types_compatible(type, ltype))
360 pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
361 base, size, mtrr_attrib_to_str(ltype),
362 mtrr_attrib_to_str(type));
366 ++mtrr_usage_table[i];
370 /* Search for an empty MTRR */
371 i = mtrr_if->get_free_region(base, size, replace);
373 set_mtrr(i, base, size, type);
374 if (likely(replace < 0)) {
375 mtrr_usage_table[i] = 1;
377 mtrr_usage_table[i] = mtrr_usage_table[replace];
379 mtrr_usage_table[i]++;
380 if (unlikely(replace != i)) {
381 set_mtrr(replace, 0, 0, 0);
382 mtrr_usage_table[replace] = 0;
386 pr_info("mtrr: no more MTRRs available\n");
390 mutex_unlock(&mtrr_mutex);
395 static int mtrr_check(unsigned long base, unsigned long size)
397 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
398 pr_warning("mtrr: size and base must be multiples of 4 kiB\n");
399 pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
407 * mtrr_add - Add a memory type region
408 * @base: Physical base address of region
409 * @size: Physical size of region
410 * @type: Type of MTRR desired
411 * @increment: If this is true do usage counting on the region
413 * Memory type region registers control the caching on newer Intel and
414 * non Intel processors. This function allows drivers to request an
415 * MTRR is added. The details and hardware specifics of each processor's
416 * implementation are hidden from the caller, but nevertheless the
417 * caller should expect to need to provide a power of two size on an
418 * equivalent power of two boundary.
420 * If the region cannot be added either because all regions are in use
421 * or the CPU cannot support it a negative value is returned. On success
422 * the register number for this entry is returned, but should be treated
425 * On a multiprocessor machine the changes are made to all processors.
426 * This is required on x86 by the Intel processors.
428 * The available types are
430 * %MTRR_TYPE_UNCACHABLE - No caching
432 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
434 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
436 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
438 * BUGS: Needs a quiet flag for the cases where drivers do not mind
439 * failures and do not wish system log messages to be sent.
441 int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
446 if (mtrr_check(base, size))
448 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
451 EXPORT_SYMBOL(mtrr_add);
454 * mtrr_del_page - delete a memory type region
455 * @reg: Register returned by mtrr_add
456 * @base: Physical base address
457 * @size: Size of region
459 * If register is supplied then base and size are ignored. This is
460 * how drivers should call it.
462 * Releases an MTRR region. If the usage count drops to zero the
463 * register is freed and the region returns to default state.
464 * On success the register is returned, on failure a negative error
467 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
471 unsigned long lbase, lsize;
477 max = num_var_ranges;
478 /* No CPU hotplug when we change MTRR entries */
480 mutex_lock(&mtrr_mutex);
482 /* Search for existing MTRR */
483 for (i = 0; i < max; ++i) {
484 mtrr_if->get(i, &lbase, &lsize, <ype);
485 if (lbase == base && lsize == size) {
491 pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
497 pr_warning("mtrr: register: %d too big\n", reg);
500 mtrr_if->get(reg, &lbase, &lsize, <ype);
502 pr_warning("mtrr: MTRR %d not used\n", reg);
505 if (mtrr_usage_table[reg] < 1) {
506 pr_warning("mtrr: reg: %d has count=0\n", reg);
509 if (--mtrr_usage_table[reg] < 1)
510 set_mtrr(reg, 0, 0, 0);
513 mutex_unlock(&mtrr_mutex);
519 * mtrr_del - delete a memory type region
520 * @reg: Register returned by mtrr_add
521 * @base: Physical base address
522 * @size: Size of region
524 * If register is supplied then base and size are ignored. This is
525 * how drivers should call it.
527 * Releases an MTRR region. If the usage count drops to zero the
528 * register is freed and the region returns to default state.
529 * On success the register is returned, on failure a negative error
532 int mtrr_del(int reg, unsigned long base, unsigned long size)
536 if (mtrr_check(base, size))
538 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
540 EXPORT_SYMBOL(mtrr_del);
543 * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable
544 * @base: Physical base address
545 * @size: Size of region
547 * If PAT is available, this does nothing. If PAT is unavailable, it
548 * attempts to add a WC MTRR covering size bytes starting at base and
549 * logs an error if this fails.
551 * The called should provide a power of two size on an equivalent
552 * power of two boundary.
554 * Drivers must store the return value to pass to mtrr_del_wc_if_needed,
555 * but drivers should not try to interpret that return value.
557 int arch_phys_wc_add(unsigned long base, unsigned long size)
561 if (pat_enabled() || !mtrr_enabled())
562 return 0; /* Success! (We don't need to do anything.) */
564 ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true);
566 pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.",
567 (void *)base, (void *)(base + size - 1));
570 return ret + MTRR_TO_PHYS_WC_OFFSET;
572 EXPORT_SYMBOL(arch_phys_wc_add);
575 * arch_phys_wc_del - undoes arch_phys_wc_add
576 * @handle: Return value from arch_phys_wc_add
578 * This cleans up after mtrr_add_wc_if_needed.
580 * The API guarantees that mtrr_del_wc_if_needed(error code) and
581 * mtrr_del_wc_if_needed(0) do nothing.
583 void arch_phys_wc_del(int handle)
586 WARN_ON(handle < MTRR_TO_PHYS_WC_OFFSET);
587 mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0);
590 EXPORT_SYMBOL(arch_phys_wc_del);
593 * arch_phys_wc_index - translates arch_phys_wc_add's return value
594 * @handle: Return value from arch_phys_wc_add
596 * This will turn the return value from arch_phys_wc_add into an mtrr
597 * index suitable for debugging.
599 * Note: There is no legitimate use for this function, except possibly
600 * in printk line. Alas there is an illegitimate use in some ancient
603 int arch_phys_wc_index(int handle)
605 if (handle < MTRR_TO_PHYS_WC_OFFSET)
608 return handle - MTRR_TO_PHYS_WC_OFFSET;
610 EXPORT_SYMBOL_GPL(arch_phys_wc_index);
614 * These should be called implicitly, but we can't yet until all the initcall
617 static void __init init_ifs(void)
619 #ifndef CONFIG_X86_64
626 /* The suspend/resume methods are only for CPU without MTRR. CPU using generic
627 * MTRR driver doesn't require this
635 static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
637 static int mtrr_save(void)
641 for (i = 0; i < num_var_ranges; i++) {
642 mtrr_if->get(i, &mtrr_value[i].lbase,
643 &mtrr_value[i].lsize,
644 &mtrr_value[i].ltype);
649 static void mtrr_restore(void)
653 for (i = 0; i < num_var_ranges; i++) {
654 if (mtrr_value[i].lsize) {
655 set_mtrr(i, mtrr_value[i].lbase,
657 mtrr_value[i].ltype);
664 static struct syscore_ops mtrr_syscore_ops = {
665 .suspend = mtrr_save,
666 .resume = mtrr_restore,
669 int __initdata changed_by_mtrr_cleanup;
671 #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
673 * mtrr_bp_init - initialize mtrrs on the boot CPU
675 * This needs to be called early; before any of the other CPUs are
676 * initialized (i.e. before smp_init()).
679 void __init mtrr_bp_init(void)
688 mtrr_if = &generic_mtrr_ops;
689 size_or_mask = SIZE_OR_MASK_BITS(36);
690 size_and_mask = 0x00f00000;
694 * This is an AMD specific MSR, but we assume(hope?) that
695 * Intel will implement it too when they extend the address
698 if (cpuid_eax(0x80000000) >= 0x80000008) {
699 phys_addr = cpuid_eax(0x80000008) & 0xff;
700 /* CPUID workaround for Intel 0F33/0F34 CPU */
701 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
702 boot_cpu_data.x86 == 0xF &&
703 boot_cpu_data.x86_model == 0x3 &&
704 (boot_cpu_data.x86_mask == 0x3 ||
705 boot_cpu_data.x86_mask == 0x4))
708 size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
709 size_and_mask = ~size_or_mask & 0xfffff00000ULL;
710 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
711 boot_cpu_data.x86 == 6) {
713 * VIA C* family have Intel style MTRRs,
714 * but don't support PAE
716 size_or_mask = SIZE_OR_MASK_BITS(32);
721 switch (boot_cpu_data.x86_vendor) {
723 if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) {
724 /* Pre-Athlon (K6) AMD CPU MTRRs */
725 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
726 size_or_mask = SIZE_OR_MASK_BITS(32);
730 case X86_VENDOR_CENTAUR:
731 if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) {
732 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
733 size_or_mask = SIZE_OR_MASK_BITS(32);
737 case X86_VENDOR_CYRIX:
738 if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) {
739 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
740 size_or_mask = SIZE_OR_MASK_BITS(32);
750 __mtrr_enabled = true;
751 set_num_var_ranges();
754 /* BIOS may override */
755 __mtrr_enabled = get_mtrr_state();
757 if (mtrr_cleanup(phys_addr)) {
758 changed_by_mtrr_cleanup = 1;
765 pr_info("MTRR: Disabled\n");
768 void mtrr_ap_init(void)
773 if (!use_intel() || mtrr_aps_delayed_init)
776 * Ideally we should hold mtrr_mutex here to avoid mtrr entries
777 * changed, but this routine will be called in cpu boot time,
778 * holding the lock breaks it.
780 * This routine is called in two cases:
782 * 1. very earily time of software resume, when there absolutely
783 * isn't mtrr entry changes;
785 * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
786 * lock to prevent mtrr entry changes
788 set_mtrr_from_inactive_cpu(~0U, 0, 0, 0);
792 * Save current fixed-range MTRR state of the first cpu in cpu_online_mask.
794 void mtrr_save_state(void)
802 first_cpu = cpumask_first(cpu_online_mask);
803 smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1);
807 void set_mtrr_aps_delayed_init(void)
814 mtrr_aps_delayed_init = true;
818 * Delayed MTRR initialization for all AP's
820 void mtrr_aps_init(void)
822 if (!use_intel() || !mtrr_enabled())
826 * Check if someone has requested the delay of AP MTRR initialization,
827 * by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
830 if (!mtrr_aps_delayed_init)
833 set_mtrr(~0U, 0, 0, 0);
834 mtrr_aps_delayed_init = false;
837 void mtrr_bp_restore(void)
839 if (!use_intel() || !mtrr_enabled())
845 static int __init mtrr_init_finialize(void)
851 if (!changed_by_mtrr_cleanup)
857 * The CPU has no MTRR and seems to not support SMP. They have
858 * specific drivers, we use a tricky method to support
859 * suspend/resume for them.
861 * TBD: is there any system with such CPU which supports
862 * suspend/resume? If no, we should remove the code.
864 register_syscore_ops(&mtrr_syscore_ops);
868 subsys_initcall(mtrr_init_finialize);