arch/x86/kernel/cpu/perf_event_amd.c

   1 #include <linux/perf_event.h>
   2 #include <linux/export.h>
   3 #include <linux/types.h>
   4 #include <linux/init.h>
   5 #include <linux/slab.h>
   6 #include <asm/apicdef.h>
   7
   8 #include "perf_event.h"
   9
  10 static __initconst const u64 amd_hw_cache_event_ids
  11                                 [PERF_COUNT_HW_CACHE_MAX]
  12                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  13                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  14 {
  15  [ C(L1D) ] = {
  16         [ C(OP_READ) ] = {
  17                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
  18                 [ C(RESULT_MISS)   ] = 0x0141, /* Data Cache Misses          */
  19         },
  20         [ C(OP_WRITE) ] = {
  21                 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
  22                 [ C(RESULT_MISS)   ] = 0,
  23         },
  24         [ C(OP_PREFETCH) ] = {
  25                 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
  26                 [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
  27         },
  28  },
  29  [ C(L1I ) ] = {
  30         [ C(OP_READ) ] = {
  31                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
  32                 [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
  33         },
  34         [ C(OP_WRITE) ] = {
  35                 [ C(RESULT_ACCESS) ] = -1,
  36                 [ C(RESULT_MISS)   ] = -1,
  37         },
  38         [ C(OP_PREFETCH) ] = {
  39                 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
  40                 [ C(RESULT_MISS)   ] = 0,
  41         },
  42  },
  43  [ C(LL  ) ] = {
  44         [ C(OP_READ) ] = {
  45                 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
  46                 [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
  47         },
  48         [ C(OP_WRITE) ] = {
  49                 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
  50                 [ C(RESULT_MISS)   ] = 0,
  51         },
  52         [ C(OP_PREFETCH) ] = {
  53                 [ C(RESULT_ACCESS) ] = 0,
  54                 [ C(RESULT_MISS)   ] = 0,
  55         },
  56  },
  57  [ C(DTLB) ] = {
  58         [ C(OP_READ) ] = {
  59                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
  60                 [ C(RESULT_MISS)   ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
  61         },
  62         [ C(OP_WRITE) ] = {
  63                 [ C(RESULT_ACCESS) ] = 0,
  64                 [ C(RESULT_MISS)   ] = 0,
  65         },
  66         [ C(OP_PREFETCH) ] = {
  67                 [ C(RESULT_ACCESS) ] = 0,
  68                 [ C(RESULT_MISS)   ] = 0,
  69         },
  70  },
  71  [ C(ITLB) ] = {
  72         [ C(OP_READ) ] = {
  73                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
  74                 [ C(RESULT_MISS)   ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
  75         },
  76         [ C(OP_WRITE) ] = {
  77                 [ C(RESULT_ACCESS) ] = -1,
  78                 [ C(RESULT_MISS)   ] = -1,
  79         },
  80         [ C(OP_PREFETCH) ] = {
  81                 [ C(RESULT_ACCESS) ] = -1,
  82                 [ C(RESULT_MISS)   ] = -1,
  83         },
  84  },
  85  [ C(BPU ) ] = {
  86         [ C(OP_READ) ] = {
  87                 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
  88                 [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
  89         },
  90         [ C(OP_WRITE) ] = {
  91                 [ C(RESULT_ACCESS) ] = -1,
  92                 [ C(RESULT_MISS)   ] = -1,
  93         },
  94         [ C(OP_PREFETCH) ] = {
  95                 [ C(RESULT_ACCESS) ] = -1,
  96                 [ C(RESULT_MISS)   ] = -1,
  97         },
  98  },
  99  [ C(NODE) ] = {
 100         [ C(OP_READ) ] = {
 101                 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
 102                 [ C(RESULT_MISS)   ] = 0x98e9, /* CPU Request to Memory, r   */
 103         },
 104         [ C(OP_WRITE) ] = {
 105                 [ C(RESULT_ACCESS) ] = -1,
 106                 [ C(RESULT_MISS)   ] = -1,
 107         },
 108         [ C(OP_PREFETCH) ] = {
 109                 [ C(RESULT_ACCESS) ] = -1,
 110                 [ C(RESULT_MISS)   ] = -1,
 111         },
 112  },
 113 };
 114
 115 /*
 116  * AMD Performance Monitor K7 and later.
 117  */
 118 static const u64 amd_perfmon_event_map[] =
 119 {
 120   [PERF_COUNT_HW_CPU_CYCLES]                    = 0x0076,
 121   [PERF_COUNT_HW_INSTRUCTIONS]                  = 0x00c0,
 122   [PERF_COUNT_HW_CACHE_REFERENCES]              = 0x0080,
 123   [PERF_COUNT_HW_CACHE_MISSES]                  = 0x0081,
 124   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]           = 0x00c2,
 125   [PERF_COUNT_HW_BRANCH_MISSES]                 = 0x00c3,
 126   [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]       = 0x00d0, /* "Decoder empty" event */
 127   [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]        = 0x00d1, /* "Dispatch stalls" event */
 128 };
 129
 130 static u64 amd_pmu_event_map(int hw_event)
 131 {
 132         return amd_perfmon_event_map[hw_event];
 133 }
 134
 135 static int amd_pmu_hw_config(struct perf_event *event)
 136 {
 137         int ret;
 138
 139         /* pass precise event sampling to ibs: */
 140         if (event->attr.precise_ip && get_ibs_caps())
 141                 return -ENOENT;
 142
 143         ret = x86_pmu_hw_config(event);
 144         if (ret)
 145                 return ret;
 146
 147         if (has_branch_stack(event))
 148                 return -EOPNOTSUPP;
 149
 150         if (event->attr.exclude_host && event->attr.exclude_guest)
 151                 /*
 152                  * When HO == GO == 1 the hardware treats that as GO == HO == 0
 153                  * and will count in both modes. We don't want to count in that
 154                  * case so we emulate no-counting by setting US = OS = 0.
 155                  */
 156                 event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
 157                                       ARCH_PERFMON_EVENTSEL_OS);
 158         else if (event->attr.exclude_host)
 159                 event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
 160         else if (event->attr.exclude_guest)
 161                 event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
 162
 163         if (event->attr.type != PERF_TYPE_RAW)
 164                 return 0;
 165
 166         event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
 167
 168         return 0;
 169 }
 170
 171 /*
 172  * AMD64 events are detected based on their event codes.
 173  */
 174 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
 175 {
 176         return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff);
 177 }
 178
 179 static inline int amd_is_nb_event(struct hw_perf_event *hwc)
 180 {
 181         return (hwc->config & 0xe0) == 0xe0;
 182 }
 183
 184 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 185 {
 186         struct amd_nb *nb = cpuc->amd_nb;
 187
 188         return nb && nb->nb_id != -1;
 189 }
 190
 191 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
 192                                            struct perf_event *event)
 193 {
 194         struct amd_nb *nb = cpuc->amd_nb;
 195         int i;
 196
 197         /*
 198          * need to scan whole list because event may not have
 199          * been assigned during scheduling
 200          *
 201          * no race condition possible because event can only
 202          * be removed on one CPU at a time AND PMU is disabled
 203          * when we come here
 204          */
 205         for (i = 0; i < x86_pmu.num_counters; i++) {
 206                 if (cmpxchg(nb->owners + i, event, NULL) == event)
 207                         break;
 208         }
 209 }
 210
 211  /*
 212   * AMD64 NorthBridge events need special treatment because
 213   * counter access needs to be synchronized across all cores
 214   * of a package. Refer to BKDG section 3.12
 215   *
 216   * NB events are events measuring L3 cache, Hypertransport
 217   * traffic. They are identified by an event code >= 0xe00.
 218   * They measure events on the NorthBride which is shared
 219   * by all cores on a package. NB events are counted on a
 220   * shared set of counters. When a NB event is programmed
 221   * in a counter, the data actually comes from a shared
 222   * counter. Thus, access to those counters needs to be
 223   * synchronized.
 224   *
 225   * We implement the synchronization such that no two cores
 226   * can be measuring NB events using the same counters. Thus,
 227   * we maintain a per-NB allocation table. The available slot
 228   * is propagated using the event_constraint structure.
 229   *
 230   * We provide only one choice for each NB event based on
 231   * the fact that only NB events have restrictions. Consequently,
 232   * if a counter is available, there is a guarantee the NB event
 233   * will be assigned to it. If no slot is available, an empty
 234   * constraint is returned and scheduling will eventually fail
 235   * for this event.
 236   *
 237   * Note that all cores attached the same NB compete for the same
 238   * counters to host NB events, this is why we use atomic ops. Some
 239   * multi-chip CPUs may have more than one NB.
 240   *
 241   * Given that resources are allocated (cmpxchg), they must be
 242   * eventually freed for others to use. This is accomplished by
 243   * calling __amd_put_nb_event_constraints()
 244   *
 245   * Non NB events are not impacted by this restriction.
 246   */
 247 static struct event_constraint *
 248 __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
 249                                struct event_constraint *c)
 250 {
 251         struct hw_perf_event *hwc = &event->hw;
 252         struct amd_nb *nb = cpuc->amd_nb;
 253         struct perf_event *old;
 254         int idx, new = -1;
 255
 256         /*
 257          * detect if already present, if so reuse
 258          *
 259          * cannot merge with actual allocation
 260          * because of possible holes
 261          *
 262          * event can already be present yet not assigned (in hwc->idx)
 263          * because of successive calls to x86_schedule_events() from
 264          * hw_perf_group_sched_in() without hw_perf_enable()
 265          */
 266         for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) {
 267                 if (new == -1 || hwc->idx == idx)
 268                         /* assign free slot, prefer hwc->idx */
 269                         old = cmpxchg(nb->owners + idx, NULL, event);
 270                 else if (nb->owners[idx] == event)
 271                         /* event already present */
 272                         old = event;
 273                 else
 274                         continue;
 275
 276                 if (old && old != event)
 277                         continue;
 278
 279                 /* reassign to this slot */
 280                 if (new != -1)
 281                         cmpxchg(nb->owners + new, event, NULL);
 282                 new = idx;
 283
 284                 /* already present, reuse */
 285                 if (old == event)
 286                         break;
 287         }
 288
 289         if (new == -1)
 290                 return &emptyconstraint;
 291
 292         return &nb->event_constraints[new];
 293 }
 294
 295 static struct amd_nb *amd_alloc_nb(int cpu)
 296 {
 297         struct amd_nb *nb;
 298         int i;
 299
 300         nb = kmalloc_node(sizeof(struct amd_nb), GFP_KERNEL | __GFP_ZERO,
 301                           cpu_to_node(cpu));
 302         if (!nb)
 303                 return NULL;
 304
 305         nb->nb_id = -1;
 306
 307         /*
 308          * initialize all possible NB constraints
 309          */
 310         for (i = 0; i < x86_pmu.num_counters; i++) {
 311                 __set_bit(i, nb->event_constraints[i].idxmsk);
 312                 nb->event_constraints[i].weight = 1;
 313         }
 314         return nb;
 315 }
 316
 317 static int amd_pmu_cpu_prepare(int cpu)
 318 {
 319         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 320
 321         WARN_ON_ONCE(cpuc->amd_nb);
 322
 323         if (boot_cpu_data.x86_max_cores < 2)
 324                 return NOTIFY_OK;
 325
 326         cpuc->amd_nb = amd_alloc_nb(cpu);
 327         if (!cpuc->amd_nb)
 328                 return NOTIFY_BAD;
 329
 330         return NOTIFY_OK;
 331 }
 332
 333 static void amd_pmu_cpu_starting(int cpu)
 334 {
 335         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
 336         struct amd_nb *nb;
 337         int i, nb_id;
 338
 339         cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
 340
 341         if (boot_cpu_data.x86_max_cores < 2)
 342                 return;
 343
 344         nb_id = amd_get_nb_id(cpu);
 345         WARN_ON_ONCE(nb_id == BAD_APICID);
 346
 347         for_each_online_cpu(i) {
 348                 nb = per_cpu(cpu_hw_events, i).amd_nb;
 349                 if (WARN_ON_ONCE(!nb))
 350                         continue;
 351
 352                 if (nb->nb_id == nb_id) {
 353                         cpuc->kfree_on_online = cpuc->amd_nb;
 354                         cpuc->amd_nb = nb;
 355                         break;
 356                 }
 357         }
 358
 359         cpuc->amd_nb->nb_id = nb_id;
 360         cpuc->amd_nb->refcnt++;
 361 }
 362
 363 static void amd_pmu_cpu_dead(int cpu)
 364 {
 365         struct cpu_hw_events *cpuhw;
 366
 367         if (boot_cpu_data.x86_max_cores < 2)
 368                 return;
 369
 370         cpuhw = &per_cpu(cpu_hw_events, cpu);
 371
 372         if (cpuhw->amd_nb) {
 373                 struct amd_nb *nb = cpuhw->amd_nb;
 374
 375                 if (nb->nb_id == -1 || --nb->refcnt == 0)
 376                         kfree(nb);
 377
 378                 cpuhw->amd_nb = NULL;
 379         }
 380 }
 381
 382 static struct event_constraint *
 383 amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 384 {
 385         /*
 386          * if not NB event or no NB, then no constraints
 387          */
 388         if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
 389                 return &unconstrained;
 390
 391         return __amd_get_nb_event_constraints(cpuc, event, &unconstrained);
 392 }
 393
 394 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
 395                                       struct perf_event *event)
 396 {
 397         if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))
 398                 __amd_put_nb_event_constraints(cpuc, event);
 399 }
 400
 401 PMU_FORMAT_ATTR(event,  "config:0-7,32-35");
 402 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
 403 PMU_FORMAT_ATTR(edge,   "config:18"     );
 404 PMU_FORMAT_ATTR(inv,    "config:23"     );
 405 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
 406
 407 static struct attribute *amd_format_attr[] = {
 408         &format_attr_event.attr,
 409         &format_attr_umask.attr,
 410         &format_attr_edge.attr,
 411         &format_attr_inv.attr,
 412         &format_attr_cmask.attr,
 413         NULL,
 414 };
 415
 416 /* AMD Family 15h */
 417
 418 #define AMD_EVENT_TYPE_MASK     0x000000F0ULL
 419
 420 #define AMD_EVENT_FP            0x00000000ULL ... 0x00000010ULL
 421 #define AMD_EVENT_LS            0x00000020ULL ... 0x00000030ULL
 422 #define AMD_EVENT_DC            0x00000040ULL ... 0x00000050ULL
 423 #define AMD_EVENT_CU            0x00000060ULL ... 0x00000070ULL
 424 #define AMD_EVENT_IC_DE         0x00000080ULL ... 0x00000090ULL
 425 #define AMD_EVENT_EX_LS         0x000000C0ULL
 426 #define AMD_EVENT_DE            0x000000D0ULL
 427 #define AMD_EVENT_NB            0x000000E0ULL ... 0x000000F0ULL
 428
 429 /*
 430  * AMD family 15h event code/PMC mappings:
 431  *
 432  * type = event_code & 0x0F0:
 433  *
 434  * 0x000        FP      PERF_CTL[5:3]
 435  * 0x010        FP      PERF_CTL[5:3]
 436  * 0x020        LS      PERF_CTL[5:0]
 437  * 0x030        LS      PERF_CTL[5:0]
 438  * 0x040        DC      PERF_CTL[5:0]
 439  * 0x050        DC      PERF_CTL[5:0]
 440  * 0x060        CU      PERF_CTL[2:0]
 441  * 0x070        CU      PERF_CTL[2:0]
 442  * 0x080        IC/DE   PERF_CTL[2:0]
 443  * 0x090        IC/DE   PERF_CTL[2:0]
 444  * 0x0A0        ---
 445  * 0x0B0        ---
 446  * 0x0C0        EX/LS   PERF_CTL[5:0]
 447  * 0x0D0        DE      PERF_CTL[2:0]
 448  * 0x0E0        NB      NB_PERF_CTL[3:0]
 449  * 0x0F0        NB      NB_PERF_CTL[3:0]
 450  *
 451  * Exceptions:
 452  *
 453  * 0x000        FP      PERF_CTL[3], PERF_CTL[5:3] (*)
 454  * 0x003        FP      PERF_CTL[3]
 455  * 0x004        FP      PERF_CTL[3], PERF_CTL[5:3] (*)
 456  * 0x00B        FP      PERF_CTL[3]
 457  * 0x00D        FP      PERF_CTL[3]
 458  * 0x023        DE      PERF_CTL[2:0]
 459  * 0x02D        LS      PERF_CTL[3]
 460  * 0x02E        LS      PERF_CTL[3,0]
 461  * 0x031        LS      PERF_CTL[2:0] (**)
 462  * 0x043        CU      PERF_CTL[2:0]
 463  * 0x045        CU      PERF_CTL[2:0]
 464  * 0x046        CU      PERF_CTL[2:0]
 465  * 0x054        CU      PERF_CTL[2:0]
 466  * 0x055        CU      PERF_CTL[2:0]
 467  * 0x08F        IC      PERF_CTL[0]
 468  * 0x187        DE      PERF_CTL[0]
 469  * 0x188        DE      PERF_CTL[0]
 470  * 0x0DB        EX      PERF_CTL[5:0]
 471  * 0x0DC        LS      PERF_CTL[5:0]
 472  * 0x0DD        LS      PERF_CTL[5:0]
 473  * 0x0DE        LS      PERF_CTL[5:0]
 474  * 0x0DF        LS      PERF_CTL[5:0]
 475  * 0x1C0        EX      PERF_CTL[5:3]
 476  * 0x1D6        EX      PERF_CTL[5:0]
 477  * 0x1D8        EX      PERF_CTL[5:0]
 478  *
 479  * (*)  depending on the umask all FPU counters may be used
 480  * (**) only one unitmask enabled at a time
 481  */
 482
 483 static struct event_constraint amd_f15_PMC0  = EVENT_CONSTRAINT(0, 0x01, 0);
 484 static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0);
 485 static struct event_constraint amd_f15_PMC3  = EVENT_CONSTRAINT(0, 0x08, 0);
 486 static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
 487 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 488 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
 489
 490 static struct event_constraint *
 491 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 492 {
 493         struct hw_perf_event *hwc = &event->hw;
 494         unsigned int event_code = amd_get_event_code(hwc);
 495
 496         switch (event_code & AMD_EVENT_TYPE_MASK) {
 497         case AMD_EVENT_FP:
 498                 switch (event_code) {
 499                 case 0x000:
 500                         if (!(hwc->config & 0x0000F000ULL))
 501                                 break;
 502                         if (!(hwc->config & 0x00000F00ULL))
 503                                 break;
 504                         return &amd_f15_PMC3;
 505                 case 0x004:
 506                         if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
 507                                 break;
 508                         return &amd_f15_PMC3;
 509                 case 0x003:
 510                 case 0x00B:
 511                 case 0x00D:
 512                         return &amd_f15_PMC3;
 513                 }
 514                 return &amd_f15_PMC53;
 515         case AMD_EVENT_LS:
 516         case AMD_EVENT_DC:
 517         case AMD_EVENT_EX_LS:
 518                 switch (event_code) {
 519                 case 0x023:
 520                 case 0x043:
 521                 case 0x045:
 522                 case 0x046:
 523                 case 0x054:
 524                 case 0x055:
 525                         return &amd_f15_PMC20;
 526                 case 0x02D:
 527                         return &amd_f15_PMC3;
 528                 case 0x02E:
 529                         return &amd_f15_PMC30;
 530                 case 0x031:
 531                         if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)
 532                                 return &amd_f15_PMC20;
 533                         return &emptyconstraint;
 534                 case 0x1C0:
 535                         return &amd_f15_PMC53;
 536                 default:
 537                         return &amd_f15_PMC50;
 538                 }
 539         case AMD_EVENT_CU:
 540         case AMD_EVENT_IC_DE:
 541         case AMD_EVENT_DE:
 542                 switch (event_code) {
 543                 case 0x08F:
 544                 case 0x187:
 545                 case 0x188:
 546                         return &amd_f15_PMC0;
 547                 case 0x0DB ... 0x0DF:
 548                 case 0x1D6:
 549                 case 0x1D8:
 550                         return &amd_f15_PMC50;
 551                 default:
 552                         return &amd_f15_PMC20;
 553                 }
 554         case AMD_EVENT_NB:
 555                 /* not yet implemented */
 556                 return &emptyconstraint;
 557         default:
 558                 return &emptyconstraint;
 559         }
 560 }
 561
 562 static ssize_t amd_event_sysfs_show(char *page, u64 config)
 563 {
 564         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT) |
 565                     (config & AMD64_EVENTSEL_EVENT) >> 24;
 566
 567         return x86_event_sysfs_show(page, config, event);
 568 }
 569
 570 static __initconst const struct x86_pmu amd_pmu = {
 571         .name                   = "AMD",
 572         .handle_irq             = x86_pmu_handle_irq,
 573         .disable_all            = x86_pmu_disable_all,
 574         .enable_all             = x86_pmu_enable_all,
 575         .enable                 = x86_pmu_enable_event,
 576         .disable                = x86_pmu_disable_event,
 577         .hw_config              = amd_pmu_hw_config,
 578         .schedule_events        = x86_schedule_events,
 579         .eventsel               = MSR_K7_EVNTSEL0,
 580         .perfctr                = MSR_K7_PERFCTR0,
 581         .event_map              = amd_pmu_event_map,
 582         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
 583         .num_counters           = AMD64_NUM_COUNTERS,
 584         .cntval_bits            = 48,
 585         .cntval_mask            = (1ULL << 48) - 1,
 586         .apic                   = 1,
 587         /* use highest bit to detect overflow */
 588         .max_period             = (1ULL << 47) - 1,
 589         .get_event_constraints  = amd_get_event_constraints,
 590         .put_event_constraints  = amd_put_event_constraints,
 591
 592         .format_attrs           = amd_format_attr,
 593         .events_sysfs_show      = amd_event_sysfs_show,
 594
 595         .cpu_prepare            = amd_pmu_cpu_prepare,
 596         .cpu_starting           = amd_pmu_cpu_starting,
 597         .cpu_dead               = amd_pmu_cpu_dead,
 598 };
 599
 600 static int setup_event_constraints(void)
 601 {
 602         if (boot_cpu_data.x86 >= 0x15)
 603                 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
 604         return 0;
 605 }
 606
 607 static int setup_perfctr_core(void)
 608 {
 609         if (!cpu_has_perfctr_core) {
 610                 WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h,
 611                      KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!");
 612                 return -ENODEV;
 613         }
 614
 615         WARN(x86_pmu.get_event_constraints == amd_get_event_constraints,
 616              KERN_ERR "hw perf events core counters need constraints handler!");
 617
 618         /*
 619          * If core performance counter extensions exists, we must use
 620          * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
 621          * x86_pmu_addr_offset().
 622          */
 623         x86_pmu.eventsel        = MSR_F15H_PERF_CTL;
 624         x86_pmu.perfctr         = MSR_F15H_PERF_CTR;
 625         x86_pmu.num_counters    = AMD64_NUM_COUNTERS_CORE;
 626
 627         printk(KERN_INFO "perf: AMD core performance counters detected\n");
 628
 629         return 0;
 630 }
 631
 632 __init int amd_pmu_init(void)
 633 {
 634         /* Performance-monitoring supported from K7 and later: */
 635         if (boot_cpu_data.x86 < 6)
 636                 return -ENODEV;
 637
 638         x86_pmu = amd_pmu;
 639
 640         setup_event_constraints();
 641         setup_perfctr_core();
 642
 643         /* Events are common for all AMDs */
 644         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
 645                sizeof(hw_cache_event_ids));
 646
 647         return 0;
 648 }
 649
 650 void amd_pmu_enable_virt(void)
 651 {
 652         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 653
 654         cpuc->perf_ctr_virt_mask = 0;
 655
 656         /* Reload all events */
 657         x86_pmu_disable_all();
 658         x86_pmu_enable_all(0);
 659 }
 660 EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
 661
 662 void amd_pmu_disable_virt(void)
 663 {
 664         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 665
 666         /*
 667          * We only mask out the Host-only bit so that host-only counting works
 668          * when SVM is disabled. If someone sets up a guest-only counter when
 669          * SVM is disabled the Guest-only bits still gets set and the counter
 670          * will not count anything.
 671          */
 672         cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
 673
 674         /* Reload all events */
 675         x86_pmu_disable_all();
 676         x86_pmu_enable_all(0);
 677 }
 678 EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);