4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/watchdog.h>
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
21 #include "perf_event.h"
24 * Intel PerfMon, used on Core and later.
26 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
38 static struct event_constraint intel_core_event_constraints[] __read_mostly =
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
49 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
67 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
83 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
91 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
103 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
126 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
150 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
159 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
164 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
172 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
180 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
181 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
182 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
183 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
184 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
188 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
192 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
196 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
197 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
198 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
200 struct attribute *nhm_events_attrs[] = {
201 EVENT_PTR(mem_ld_nhm),
205 struct attribute *snb_events_attrs[] = {
206 EVENT_PTR(mem_ld_snb),
207 EVENT_PTR(mem_st_snb),
211 static struct event_constraint intel_hsw_event_constraints[] = {
212 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
213 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
214 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
215 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
216 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
217 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
218 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
219 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
220 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
221 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
222 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
223 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
225 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
226 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
227 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
228 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
233 struct event_constraint intel_bdw_event_constraints[] = {
234 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
235 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
236 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
237 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
238 INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
242 static u64 intel_pmu_event_map(int hw_event)
244 return intel_perfmon_event_map[hw_event];
247 #define SNB_DMND_DATA_RD (1ULL << 0)
248 #define SNB_DMND_RFO (1ULL << 1)
249 #define SNB_DMND_IFETCH (1ULL << 2)
250 #define SNB_DMND_WB (1ULL << 3)
251 #define SNB_PF_DATA_RD (1ULL << 4)
252 #define SNB_PF_RFO (1ULL << 5)
253 #define SNB_PF_IFETCH (1ULL << 6)
254 #define SNB_LLC_DATA_RD (1ULL << 7)
255 #define SNB_LLC_RFO (1ULL << 8)
256 #define SNB_LLC_IFETCH (1ULL << 9)
257 #define SNB_BUS_LOCKS (1ULL << 10)
258 #define SNB_STRM_ST (1ULL << 11)
259 #define SNB_OTHER (1ULL << 15)
260 #define SNB_RESP_ANY (1ULL << 16)
261 #define SNB_NO_SUPP (1ULL << 17)
262 #define SNB_LLC_HITM (1ULL << 18)
263 #define SNB_LLC_HITE (1ULL << 19)
264 #define SNB_LLC_HITS (1ULL << 20)
265 #define SNB_LLC_HITF (1ULL << 21)
266 #define SNB_LOCAL (1ULL << 22)
267 #define SNB_REMOTE (0xffULL << 23)
268 #define SNB_SNP_NONE (1ULL << 31)
269 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
270 #define SNB_SNP_MISS (1ULL << 33)
271 #define SNB_NO_FWD (1ULL << 34)
272 #define SNB_SNP_FWD (1ULL << 35)
273 #define SNB_HITM (1ULL << 36)
274 #define SNB_NON_DRAM (1ULL << 37)
276 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
277 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
278 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
280 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
281 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
284 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
285 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
287 #define SNB_L3_ACCESS SNB_RESP_ANY
288 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
290 static __initconst const u64 snb_hw_cache_extra_regs
291 [PERF_COUNT_HW_CACHE_MAX]
292 [PERF_COUNT_HW_CACHE_OP_MAX]
293 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
297 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
298 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
301 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
302 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
304 [ C(OP_PREFETCH) ] = {
305 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
306 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
311 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
312 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
315 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
316 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
318 [ C(OP_PREFETCH) ] = {
319 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
320 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
325 static __initconst const u64 snb_hw_cache_event_ids
326 [PERF_COUNT_HW_CACHE_MAX]
327 [PERF_COUNT_HW_CACHE_OP_MAX]
328 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
332 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
333 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
336 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
337 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
339 [ C(OP_PREFETCH) ] = {
340 [ C(RESULT_ACCESS) ] = 0x0,
341 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
346 [ C(RESULT_ACCESS) ] = 0x0,
347 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
350 [ C(RESULT_ACCESS) ] = -1,
351 [ C(RESULT_MISS) ] = -1,
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = 0x0,
355 [ C(RESULT_MISS) ] = 0x0,
360 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
361 [ C(RESULT_ACCESS) ] = 0x01b7,
362 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
363 [ C(RESULT_MISS) ] = 0x01b7,
366 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
367 [ C(RESULT_ACCESS) ] = 0x01b7,
368 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
369 [ C(RESULT_MISS) ] = 0x01b7,
371 [ C(OP_PREFETCH) ] = {
372 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
373 [ C(RESULT_ACCESS) ] = 0x01b7,
374 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
375 [ C(RESULT_MISS) ] = 0x01b7,
380 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
381 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
384 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
385 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
387 [ C(OP_PREFETCH) ] = {
388 [ C(RESULT_ACCESS) ] = 0x0,
389 [ C(RESULT_MISS) ] = 0x0,
394 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
395 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
398 [ C(RESULT_ACCESS) ] = -1,
399 [ C(RESULT_MISS) ] = -1,
401 [ C(OP_PREFETCH) ] = {
402 [ C(RESULT_ACCESS) ] = -1,
403 [ C(RESULT_MISS) ] = -1,
408 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
409 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
412 [ C(RESULT_ACCESS) ] = -1,
413 [ C(RESULT_MISS) ] = -1,
415 [ C(OP_PREFETCH) ] = {
416 [ C(RESULT_ACCESS) ] = -1,
417 [ C(RESULT_MISS) ] = -1,
422 [ C(RESULT_ACCESS) ] = 0x01b7,
423 [ C(RESULT_MISS) ] = 0x01b7,
426 [ C(RESULT_ACCESS) ] = 0x01b7,
427 [ C(RESULT_MISS) ] = 0x01b7,
429 [ C(OP_PREFETCH) ] = {
430 [ C(RESULT_ACCESS) ] = 0x01b7,
431 [ C(RESULT_MISS) ] = 0x01b7,
438 * Notes on the events:
439 * - data reads do not include code reads (comparable to earlier tables)
440 * - data counts include speculative execution (except L1 write, dtlb, bpu)
441 * - remote node access includes remote memory, remote cache, remote mmio.
442 * - prefetches are not included in the counts because they are not
446 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
447 #define HSW_DEMAND_RFO BIT_ULL(1)
448 #define HSW_ANY_RESPONSE BIT_ULL(16)
449 #define HSW_SUPPLIER_NONE BIT_ULL(17)
450 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
451 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
452 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
453 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
454 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
455 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
456 HSW_L3_MISS_REMOTE_HOP2P)
457 #define HSW_SNOOP_NONE BIT_ULL(31)
458 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
459 #define HSW_SNOOP_MISS BIT_ULL(33)
460 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
461 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
462 #define HSW_SNOOP_HITM BIT_ULL(36)
463 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
464 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
465 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
466 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
467 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
468 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
469 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
470 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
471 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
472 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
473 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
475 #define BDW_L3_MISS_LOCAL BIT(26)
476 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
477 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
478 HSW_L3_MISS_REMOTE_HOP2P)
481 static __initconst const u64 hsw_hw_cache_event_ids
482 [PERF_COUNT_HW_CACHE_MAX]
483 [PERF_COUNT_HW_CACHE_OP_MAX]
484 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
488 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
489 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
492 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
493 [ C(RESULT_MISS) ] = 0x0,
495 [ C(OP_PREFETCH) ] = {
496 [ C(RESULT_ACCESS) ] = 0x0,
497 [ C(RESULT_MISS) ] = 0x0,
502 [ C(RESULT_ACCESS) ] = 0x0,
503 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
506 [ C(RESULT_ACCESS) ] = -1,
507 [ C(RESULT_MISS) ] = -1,
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
516 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
517 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
520 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
521 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
523 [ C(OP_PREFETCH) ] = {
524 [ C(RESULT_ACCESS) ] = 0x0,
525 [ C(RESULT_MISS) ] = 0x0,
530 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
531 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
534 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
535 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
537 [ C(OP_PREFETCH) ] = {
538 [ C(RESULT_ACCESS) ] = 0x0,
539 [ C(RESULT_MISS) ] = 0x0,
544 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
545 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
548 [ C(RESULT_ACCESS) ] = -1,
549 [ C(RESULT_MISS) ] = -1,
551 [ C(OP_PREFETCH) ] = {
552 [ C(RESULT_ACCESS) ] = -1,
553 [ C(RESULT_MISS) ] = -1,
558 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
559 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
562 [ C(RESULT_ACCESS) ] = -1,
563 [ C(RESULT_MISS) ] = -1,
565 [ C(OP_PREFETCH) ] = {
566 [ C(RESULT_ACCESS) ] = -1,
567 [ C(RESULT_MISS) ] = -1,
572 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
573 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
576 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
577 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
579 [ C(OP_PREFETCH) ] = {
580 [ C(RESULT_ACCESS) ] = 0x0,
581 [ C(RESULT_MISS) ] = 0x0,
586 static __initconst const u64 hsw_hw_cache_extra_regs
587 [PERF_COUNT_HW_CACHE_MAX]
588 [PERF_COUNT_HW_CACHE_OP_MAX]
589 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
593 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
595 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
596 HSW_L3_MISS|HSW_ANY_SNOOP,
599 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
601 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
602 HSW_L3_MISS|HSW_ANY_SNOOP,
604 [ C(OP_PREFETCH) ] = {
605 [ C(RESULT_ACCESS) ] = 0x0,
606 [ C(RESULT_MISS) ] = 0x0,
611 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
612 HSW_L3_MISS_LOCAL_DRAM|
614 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
619 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
620 HSW_L3_MISS_LOCAL_DRAM|
622 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x0,
633 static __initconst const u64 westmere_hw_cache_event_ids
634 [PERF_COUNT_HW_CACHE_MAX]
635 [PERF_COUNT_HW_CACHE_OP_MAX]
636 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
640 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
641 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
644 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
645 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
647 [ C(OP_PREFETCH) ] = {
648 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
649 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
654 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
655 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
658 [ C(RESULT_ACCESS) ] = -1,
659 [ C(RESULT_MISS) ] = -1,
661 [ C(OP_PREFETCH) ] = {
662 [ C(RESULT_ACCESS) ] = 0x0,
663 [ C(RESULT_MISS) ] = 0x0,
668 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
669 [ C(RESULT_ACCESS) ] = 0x01b7,
670 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
671 [ C(RESULT_MISS) ] = 0x01b7,
674 * Use RFO, not WRITEBACK, because a write miss would typically occur
678 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
679 [ C(RESULT_ACCESS) ] = 0x01b7,
680 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
681 [ C(RESULT_MISS) ] = 0x01b7,
683 [ C(OP_PREFETCH) ] = {
684 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
685 [ C(RESULT_ACCESS) ] = 0x01b7,
686 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
687 [ C(RESULT_MISS) ] = 0x01b7,
692 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
693 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
696 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
697 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
699 [ C(OP_PREFETCH) ] = {
700 [ C(RESULT_ACCESS) ] = 0x0,
701 [ C(RESULT_MISS) ] = 0x0,
706 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
707 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
710 [ C(RESULT_ACCESS) ] = -1,
711 [ C(RESULT_MISS) ] = -1,
713 [ C(OP_PREFETCH) ] = {
714 [ C(RESULT_ACCESS) ] = -1,
715 [ C(RESULT_MISS) ] = -1,
720 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
721 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
724 [ C(RESULT_ACCESS) ] = -1,
725 [ C(RESULT_MISS) ] = -1,
727 [ C(OP_PREFETCH) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
734 [ C(RESULT_ACCESS) ] = 0x01b7,
735 [ C(RESULT_MISS) ] = 0x01b7,
738 [ C(RESULT_ACCESS) ] = 0x01b7,
739 [ C(RESULT_MISS) ] = 0x01b7,
741 [ C(OP_PREFETCH) ] = {
742 [ C(RESULT_ACCESS) ] = 0x01b7,
743 [ C(RESULT_MISS) ] = 0x01b7,
749 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
750 * See IA32 SDM Vol 3B 30.6.1.3
753 #define NHM_DMND_DATA_RD (1 << 0)
754 #define NHM_DMND_RFO (1 << 1)
755 #define NHM_DMND_IFETCH (1 << 2)
756 #define NHM_DMND_WB (1 << 3)
757 #define NHM_PF_DATA_RD (1 << 4)
758 #define NHM_PF_DATA_RFO (1 << 5)
759 #define NHM_PF_IFETCH (1 << 6)
760 #define NHM_OFFCORE_OTHER (1 << 7)
761 #define NHM_UNCORE_HIT (1 << 8)
762 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
763 #define NHM_OTHER_CORE_HITM (1 << 10)
765 #define NHM_REMOTE_CACHE_FWD (1 << 12)
766 #define NHM_REMOTE_DRAM (1 << 13)
767 #define NHM_LOCAL_DRAM (1 << 14)
768 #define NHM_NON_DRAM (1 << 15)
770 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
771 #define NHM_REMOTE (NHM_REMOTE_DRAM)
773 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
774 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
775 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
777 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
778 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
779 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
781 static __initconst const u64 nehalem_hw_cache_extra_regs
782 [PERF_COUNT_HW_CACHE_MAX]
783 [PERF_COUNT_HW_CACHE_OP_MAX]
784 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
788 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
789 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
792 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
793 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
795 [ C(OP_PREFETCH) ] = {
796 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
797 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
802 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
803 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
806 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
807 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
809 [ C(OP_PREFETCH) ] = {
810 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
811 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
816 static __initconst const u64 nehalem_hw_cache_event_ids
817 [PERF_COUNT_HW_CACHE_MAX]
818 [PERF_COUNT_HW_CACHE_OP_MAX]
819 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
823 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
824 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
827 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
828 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
830 [ C(OP_PREFETCH) ] = {
831 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
832 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
837 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
838 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
841 [ C(RESULT_ACCESS) ] = -1,
842 [ C(RESULT_MISS) ] = -1,
844 [ C(OP_PREFETCH) ] = {
845 [ C(RESULT_ACCESS) ] = 0x0,
846 [ C(RESULT_MISS) ] = 0x0,
851 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
852 [ C(RESULT_ACCESS) ] = 0x01b7,
853 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
854 [ C(RESULT_MISS) ] = 0x01b7,
857 * Use RFO, not WRITEBACK, because a write miss would typically occur
861 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
862 [ C(RESULT_ACCESS) ] = 0x01b7,
863 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
864 [ C(RESULT_MISS) ] = 0x01b7,
866 [ C(OP_PREFETCH) ] = {
867 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
868 [ C(RESULT_ACCESS) ] = 0x01b7,
869 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
870 [ C(RESULT_MISS) ] = 0x01b7,
875 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
876 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
879 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
880 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
882 [ C(OP_PREFETCH) ] = {
883 [ C(RESULT_ACCESS) ] = 0x0,
884 [ C(RESULT_MISS) ] = 0x0,
889 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
890 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
893 [ C(RESULT_ACCESS) ] = -1,
894 [ C(RESULT_MISS) ] = -1,
896 [ C(OP_PREFETCH) ] = {
897 [ C(RESULT_ACCESS) ] = -1,
898 [ C(RESULT_MISS) ] = -1,
903 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
904 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
907 [ C(RESULT_ACCESS) ] = -1,
908 [ C(RESULT_MISS) ] = -1,
910 [ C(OP_PREFETCH) ] = {
911 [ C(RESULT_ACCESS) ] = -1,
912 [ C(RESULT_MISS) ] = -1,
917 [ C(RESULT_ACCESS) ] = 0x01b7,
918 [ C(RESULT_MISS) ] = 0x01b7,
921 [ C(RESULT_ACCESS) ] = 0x01b7,
922 [ C(RESULT_MISS) ] = 0x01b7,
924 [ C(OP_PREFETCH) ] = {
925 [ C(RESULT_ACCESS) ] = 0x01b7,
926 [ C(RESULT_MISS) ] = 0x01b7,
931 static __initconst const u64 core2_hw_cache_event_ids
932 [PERF_COUNT_HW_CACHE_MAX]
933 [PERF_COUNT_HW_CACHE_OP_MAX]
934 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
938 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
939 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
942 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
943 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
945 [ C(OP_PREFETCH) ] = {
946 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
947 [ C(RESULT_MISS) ] = 0,
952 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
953 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
956 [ C(RESULT_ACCESS) ] = -1,
957 [ C(RESULT_MISS) ] = -1,
959 [ C(OP_PREFETCH) ] = {
960 [ C(RESULT_ACCESS) ] = 0,
961 [ C(RESULT_MISS) ] = 0,
966 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
967 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
970 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
971 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
973 [ C(OP_PREFETCH) ] = {
974 [ C(RESULT_ACCESS) ] = 0,
975 [ C(RESULT_MISS) ] = 0,
980 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
981 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
984 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
985 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
987 [ C(OP_PREFETCH) ] = {
988 [ C(RESULT_ACCESS) ] = 0,
989 [ C(RESULT_MISS) ] = 0,
994 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
995 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
998 [ C(RESULT_ACCESS) ] = -1,
999 [ C(RESULT_MISS) ] = -1,
1001 [ C(OP_PREFETCH) ] = {
1002 [ C(RESULT_ACCESS) ] = -1,
1003 [ C(RESULT_MISS) ] = -1,
1008 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1009 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1012 [ C(RESULT_ACCESS) ] = -1,
1013 [ C(RESULT_MISS) ] = -1,
1015 [ C(OP_PREFETCH) ] = {
1016 [ C(RESULT_ACCESS) ] = -1,
1017 [ C(RESULT_MISS) ] = -1,
1022 static __initconst const u64 atom_hw_cache_event_ids
1023 [PERF_COUNT_HW_CACHE_MAX]
1024 [PERF_COUNT_HW_CACHE_OP_MAX]
1025 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1029 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1030 [ C(RESULT_MISS) ] = 0,
1033 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1034 [ C(RESULT_MISS) ] = 0,
1036 [ C(OP_PREFETCH) ] = {
1037 [ C(RESULT_ACCESS) ] = 0x0,
1038 [ C(RESULT_MISS) ] = 0,
1043 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1044 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1050 [ C(OP_PREFETCH) ] = {
1051 [ C(RESULT_ACCESS) ] = 0,
1052 [ C(RESULT_MISS) ] = 0,
1057 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1058 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1061 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1062 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1064 [ C(OP_PREFETCH) ] = {
1065 [ C(RESULT_ACCESS) ] = 0,
1066 [ C(RESULT_MISS) ] = 0,
1071 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1072 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1075 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1076 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1078 [ C(OP_PREFETCH) ] = {
1079 [ C(RESULT_ACCESS) ] = 0,
1080 [ C(RESULT_MISS) ] = 0,
1085 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1086 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1089 [ C(RESULT_ACCESS) ] = -1,
1090 [ C(RESULT_MISS) ] = -1,
1092 [ C(OP_PREFETCH) ] = {
1093 [ C(RESULT_ACCESS) ] = -1,
1094 [ C(RESULT_MISS) ] = -1,
1099 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1100 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1103 [ C(RESULT_ACCESS) ] = -1,
1104 [ C(RESULT_MISS) ] = -1,
1106 [ C(OP_PREFETCH) ] = {
1107 [ C(RESULT_ACCESS) ] = -1,
1108 [ C(RESULT_MISS) ] = -1,
1113 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1115 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1116 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1117 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1121 #define SLM_DMND_READ SNB_DMND_DATA_RD
1122 #define SLM_DMND_WRITE SNB_DMND_RFO
1123 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1125 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1126 #define SLM_LLC_ACCESS SNB_RESP_ANY
1127 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1129 static __initconst const u64 slm_hw_cache_extra_regs
1130 [PERF_COUNT_HW_CACHE_MAX]
1131 [PERF_COUNT_HW_CACHE_OP_MAX]
1132 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1136 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1137 [ C(RESULT_MISS) ] = 0,
1140 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1141 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1143 [ C(OP_PREFETCH) ] = {
1144 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1145 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1150 static __initconst const u64 slm_hw_cache_event_ids
1151 [PERF_COUNT_HW_CACHE_MAX]
1152 [PERF_COUNT_HW_CACHE_OP_MAX]
1153 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1157 [ C(RESULT_ACCESS) ] = 0,
1158 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1161 [ C(RESULT_ACCESS) ] = 0,
1162 [ C(RESULT_MISS) ] = 0,
1164 [ C(OP_PREFETCH) ] = {
1165 [ C(RESULT_ACCESS) ] = 0,
1166 [ C(RESULT_MISS) ] = 0,
1171 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1172 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1175 [ C(RESULT_ACCESS) ] = -1,
1176 [ C(RESULT_MISS) ] = -1,
1178 [ C(OP_PREFETCH) ] = {
1179 [ C(RESULT_ACCESS) ] = 0,
1180 [ C(RESULT_MISS) ] = 0,
1185 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1186 [ C(RESULT_ACCESS) ] = 0x01b7,
1187 [ C(RESULT_MISS) ] = 0,
1190 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1191 [ C(RESULT_ACCESS) ] = 0x01b7,
1192 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1193 [ C(RESULT_MISS) ] = 0x01b7,
1195 [ C(OP_PREFETCH) ] = {
1196 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1197 [ C(RESULT_ACCESS) ] = 0x01b7,
1198 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1199 [ C(RESULT_MISS) ] = 0x01b7,
1204 [ C(RESULT_ACCESS) ] = 0,
1205 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1208 [ C(RESULT_ACCESS) ] = 0,
1209 [ C(RESULT_MISS) ] = 0,
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0,
1213 [ C(RESULT_MISS) ] = 0,
1218 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1219 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1222 [ C(RESULT_ACCESS) ] = -1,
1223 [ C(RESULT_MISS) ] = -1,
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1232 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1233 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1236 [ C(RESULT_ACCESS) ] = -1,
1237 [ C(RESULT_MISS) ] = -1,
1239 [ C(OP_PREFETCH) ] = {
1240 [ C(RESULT_ACCESS) ] = -1,
1241 [ C(RESULT_MISS) ] = -1,
1247 * Use from PMIs where the LBRs are already disabled.
1249 static void __intel_pmu_disable_all(void)
1251 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1253 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1255 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1256 intel_pmu_disable_bts();
1258 intel_bts_disable_local();
1260 intel_pmu_pebs_disable_all();
1263 static void intel_pmu_disable_all(void)
1265 __intel_pmu_disable_all();
1266 intel_pmu_lbr_disable_all();
1269 static void __intel_pmu_enable_all(int added, bool pmi)
1271 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1273 intel_pmu_pebs_enable_all();
1274 intel_pmu_lbr_enable_all(pmi);
1275 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1276 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1278 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1279 struct perf_event *event =
1280 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1282 if (WARN_ON_ONCE(!event))
1285 intel_pmu_enable_bts(event->hw.config);
1287 intel_bts_enable_local();
1290 static void intel_pmu_enable_all(int added)
1292 __intel_pmu_enable_all(added, false);
1297 * Intel Errata AAK100 (model 26)
1298 * Intel Errata AAP53 (model 30)
1299 * Intel Errata BD53 (model 44)
1301 * The official story:
1302 * These chips need to be 'reset' when adding counters by programming the
1303 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1304 * in sequence on the same PMC or on different PMCs.
1306 * In practise it appears some of these events do in fact count, and
1307 * we need to programm all 4 events.
1309 static void intel_pmu_nhm_workaround(void)
1311 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1312 static const unsigned long nhm_magic[4] = {
1318 struct perf_event *event;
1322 * The Errata requires below steps:
1323 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1324 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1325 * the corresponding PMCx;
1326 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1327 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1328 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1332 * The real steps we choose are a little different from above.
1333 * A) To reduce MSR operations, we don't run step 1) as they
1334 * are already cleared before this function is called;
1335 * B) Call x86_perf_event_update to save PMCx before configuring
1336 * PERFEVTSELx with magic number;
1337 * C) With step 5), we do clear only when the PERFEVTSELx is
1338 * not used currently.
1339 * D) Call x86_perf_event_set_period to restore PMCx;
1342 /* We always operate 4 pairs of PERF Counters */
1343 for (i = 0; i < 4; i++) {
1344 event = cpuc->events[i];
1346 x86_perf_event_update(event);
1349 for (i = 0; i < 4; i++) {
1350 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1351 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1354 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1355 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1357 for (i = 0; i < 4; i++) {
1358 event = cpuc->events[i];
1361 x86_perf_event_set_period(event);
1362 __x86_pmu_enable_event(&event->hw,
1363 ARCH_PERFMON_EVENTSEL_ENABLE);
1365 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1369 static void intel_pmu_nhm_enable_all(int added)
1372 intel_pmu_nhm_workaround();
1373 intel_pmu_enable_all(added);
1376 static inline u64 intel_pmu_get_status(void)
1380 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1385 static inline void intel_pmu_ack_status(u64 ack)
1387 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1390 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1392 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1395 mask = 0xfULL << (idx * 4);
1397 rdmsrl(hwc->config_base, ctrl_val);
1399 wrmsrl(hwc->config_base, ctrl_val);
1402 static inline bool event_is_checkpointed(struct perf_event *event)
1404 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1407 static void intel_pmu_disable_event(struct perf_event *event)
1409 struct hw_perf_event *hwc = &event->hw;
1410 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1412 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1413 intel_pmu_disable_bts();
1414 intel_pmu_drain_bts_buffer();
1418 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1419 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1420 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1423 * must disable before any actual event
1424 * because any event may be combined with LBR
1426 if (needs_branch_stack(event))
1427 intel_pmu_lbr_disable(event);
1429 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1430 intel_pmu_disable_fixed(hwc);
1434 x86_pmu_disable_event(event);
1436 if (unlikely(event->attr.precise_ip))
1437 intel_pmu_pebs_disable(event);
1440 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1442 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1443 u64 ctrl_val, bits, mask;
1446 * Enable IRQ generation (0x8),
1447 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1451 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1453 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1457 * ANY bit is supported in v3 and up
1459 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1463 mask = 0xfULL << (idx * 4);
1465 rdmsrl(hwc->config_base, ctrl_val);
1468 wrmsrl(hwc->config_base, ctrl_val);
1471 static void intel_pmu_enable_event(struct perf_event *event)
1473 struct hw_perf_event *hwc = &event->hw;
1474 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1476 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1477 if (!__this_cpu_read(cpu_hw_events.enabled))
1480 intel_pmu_enable_bts(hwc->config);
1484 * must enabled before any actual event
1485 * because any event may be combined with LBR
1487 if (needs_branch_stack(event))
1488 intel_pmu_lbr_enable(event);
1490 if (event->attr.exclude_host)
1491 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1492 if (event->attr.exclude_guest)
1493 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1495 if (unlikely(event_is_checkpointed(event)))
1496 cpuc->intel_cp_status |= (1ull << hwc->idx);
1498 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1499 intel_pmu_enable_fixed(hwc);
1503 if (unlikely(event->attr.precise_ip))
1504 intel_pmu_pebs_enable(event);
1506 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1510 * Save and restart an expired event. Called by NMI contexts,
1511 * so it has to be careful about preempting normal event ops:
1513 int intel_pmu_save_and_restart(struct perf_event *event)
1515 x86_perf_event_update(event);
1517 * For a checkpointed counter always reset back to 0. This
1518 * avoids a situation where the counter overflows, aborts the
1519 * transaction and is then set back to shortly before the
1520 * overflow, and overflows and aborts again.
1522 if (unlikely(event_is_checkpointed(event))) {
1523 /* No race with NMIs because the counter should not be armed */
1524 wrmsrl(event->hw.event_base, 0);
1525 local64_set(&event->hw.prev_count, 0);
1527 return x86_perf_event_set_period(event);
1530 static void intel_pmu_reset(void)
1532 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1533 unsigned long flags;
1536 if (!x86_pmu.num_counters)
1539 local_irq_save(flags);
1541 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1543 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1544 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1545 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
1547 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1548 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1551 ds->bts_index = ds->bts_buffer_base;
1553 /* Ack all overflows and disable fixed counters */
1554 if (x86_pmu.version >= 2) {
1555 intel_pmu_ack_status(intel_pmu_get_status());
1556 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1559 /* Reset LBRs and LBR freezing */
1560 if (x86_pmu.lbr_nr) {
1561 update_debugctlmsr(get_debugctlmsr() &
1562 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1565 local_irq_restore(flags);
1569 * This handler is triggered by the local APIC, so the APIC IRQ handling
1572 static int intel_pmu_handle_irq(struct pt_regs *regs)
1574 struct perf_sample_data data;
1575 struct cpu_hw_events *cpuc;
1580 cpuc = this_cpu_ptr(&cpu_hw_events);
1583 * No known reason to not always do late ACK,
1584 * but just in case do it opt-in.
1586 if (!x86_pmu.late_ack)
1587 apic_write(APIC_LVTPC, APIC_DM_NMI);
1588 __intel_pmu_disable_all();
1589 handled = intel_pmu_drain_bts_buffer();
1590 handled += intel_bts_interrupt();
1591 status = intel_pmu_get_status();
1597 intel_pmu_ack_status(status);
1598 if (++loops > 100) {
1599 static bool warned = false;
1601 WARN(1, "perfevents: irq loop stuck!\n");
1602 perf_event_print_debug();
1609 inc_irq_stat(apic_perf_irqs);
1611 intel_pmu_lbr_read();
1614 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1615 * and clear the bit.
1617 if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1623 * PEBS overflow sets bit 62 in the global status register
1625 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1627 x86_pmu.drain_pebs(regs);
1633 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1635 intel_pt_interrupt();
1639 * Checkpointed counters can lead to 'spurious' PMIs because the
1640 * rollback caused by the PMI will have cleared the overflow status
1641 * bit. Therefore always force probe these counters.
1643 status |= cpuc->intel_cp_status;
1645 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1646 struct perf_event *event = cpuc->events[bit];
1650 if (!test_bit(bit, cpuc->active_mask))
1653 if (!intel_pmu_save_and_restart(event))
1656 perf_sample_data_init(&data, 0, event->hw.last_period);
1658 if (has_branch_stack(event))
1659 data.br_stack = &cpuc->lbr_stack;
1661 if (perf_event_overflow(event, &data, regs))
1662 x86_pmu_stop(event, 0);
1666 * Repeat if there is more work to be done:
1668 status = intel_pmu_get_status();
1673 __intel_pmu_enable_all(0, true);
1675 * Only unmask the NMI after the overflow counters
1676 * have been reset. This avoids spurious NMIs on
1679 if (x86_pmu.late_ack)
1680 apic_write(APIC_LVTPC, APIC_DM_NMI);
1684 static struct event_constraint *
1685 intel_bts_constraints(struct perf_event *event)
1687 struct hw_perf_event *hwc = &event->hw;
1688 unsigned int hw_event, bts_event;
1690 if (event->attr.freq)
1693 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1694 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1696 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1697 return &bts_constraint;
1702 static int intel_alt_er(int idx)
1704 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
1707 if (idx == EXTRA_REG_RSP_0)
1708 return EXTRA_REG_RSP_1;
1710 if (idx == EXTRA_REG_RSP_1)
1711 return EXTRA_REG_RSP_0;
1716 static void intel_fixup_er(struct perf_event *event, int idx)
1718 event->hw.extra_reg.idx = idx;
1720 if (idx == EXTRA_REG_RSP_0) {
1721 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1722 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1723 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1724 } else if (idx == EXTRA_REG_RSP_1) {
1725 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1726 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1727 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1732 * manage allocation of shared extra msr for certain events
1735 * per-cpu: to be shared between the various events on a single PMU
1736 * per-core: per-cpu + shared by HT threads
1738 static struct event_constraint *
1739 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1740 struct perf_event *event,
1741 struct hw_perf_event_extra *reg)
1743 struct event_constraint *c = &emptyconstraint;
1744 struct er_account *era;
1745 unsigned long flags;
1749 * reg->alloc can be set due to existing state, so for fake cpuc we
1750 * need to ignore this, otherwise we might fail to allocate proper fake
1751 * state for this extra reg constraint. Also see the comment below.
1753 if (reg->alloc && !cpuc->is_fake)
1754 return NULL; /* call x86_get_event_constraint() */
1757 era = &cpuc->shared_regs->regs[idx];
1759 * we use spin_lock_irqsave() to avoid lockdep issues when
1760 * passing a fake cpuc
1762 raw_spin_lock_irqsave(&era->lock, flags);
1764 if (!atomic_read(&era->ref) || era->config == reg->config) {
1767 * If its a fake cpuc -- as per validate_{group,event}() we
1768 * shouldn't touch event state and we can avoid doing so
1769 * since both will only call get_event_constraints() once
1770 * on each event, this avoids the need for reg->alloc.
1772 * Not doing the ER fixup will only result in era->reg being
1773 * wrong, but since we won't actually try and program hardware
1774 * this isn't a problem either.
1776 if (!cpuc->is_fake) {
1777 if (idx != reg->idx)
1778 intel_fixup_er(event, idx);
1781 * x86_schedule_events() can call get_event_constraints()
1782 * multiple times on events in the case of incremental
1783 * scheduling(). reg->alloc ensures we only do the ER
1789 /* lock in msr value */
1790 era->config = reg->config;
1791 era->reg = reg->reg;
1794 atomic_inc(&era->ref);
1797 * need to call x86_get_event_constraint()
1798 * to check if associated event has constraints
1802 idx = intel_alt_er(idx);
1803 if (idx != reg->idx) {
1804 raw_spin_unlock_irqrestore(&era->lock, flags);
1808 raw_spin_unlock_irqrestore(&era->lock, flags);
1814 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1815 struct hw_perf_event_extra *reg)
1817 struct er_account *era;
1820 * Only put constraint if extra reg was actually allocated. Also takes
1821 * care of event which do not use an extra shared reg.
1823 * Also, if this is a fake cpuc we shouldn't touch any event state
1824 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1825 * either since it'll be thrown out.
1827 if (!reg->alloc || cpuc->is_fake)
1830 era = &cpuc->shared_regs->regs[reg->idx];
1832 /* one fewer user */
1833 atomic_dec(&era->ref);
1835 /* allocate again next time */
1839 static struct event_constraint *
1840 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1841 struct perf_event *event)
1843 struct event_constraint *c = NULL, *d;
1844 struct hw_perf_event_extra *xreg, *breg;
1846 xreg = &event->hw.extra_reg;
1847 if (xreg->idx != EXTRA_REG_NONE) {
1848 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1849 if (c == &emptyconstraint)
1852 breg = &event->hw.branch_reg;
1853 if (breg->idx != EXTRA_REG_NONE) {
1854 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1855 if (d == &emptyconstraint) {
1856 __intel_shared_reg_put_constraints(cpuc, xreg);
1863 struct event_constraint *
1864 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1865 struct perf_event *event)
1867 struct event_constraint *c;
1869 if (x86_pmu.event_constraints) {
1870 for_each_event_constraint(c, x86_pmu.event_constraints) {
1871 if ((event->hw.config & c->cmask) == c->code) {
1872 event->hw.flags |= c->flags;
1878 return &unconstrained;
1881 static struct event_constraint *
1882 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1883 struct perf_event *event)
1885 struct event_constraint *c;
1887 c = intel_bts_constraints(event);
1891 c = intel_shared_regs_constraints(cpuc, event);
1895 c = intel_pebs_constraints(event);
1899 return x86_get_event_constraints(cpuc, idx, event);
1903 intel_start_scheduling(struct cpu_hw_events *cpuc)
1905 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1906 struct intel_excl_states *xl;
1907 int tid = cpuc->excl_thread_id;
1910 * nothing needed if in group validation mode
1912 if (cpuc->is_fake || !is_ht_workaround_enabled())
1916 * no exclusion needed
1918 if (WARN_ON_ONCE(!excl_cntrs))
1921 xl = &excl_cntrs->states[tid];
1923 xl->sched_started = true;
1925 * lock shared state until we are done scheduling
1926 * in stop_event_scheduling()
1927 * makes scheduling appear as a transaction
1929 raw_spin_lock(&excl_cntrs->lock);
1932 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
1934 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1935 struct event_constraint *c = cpuc->event_constraint[idx];
1936 struct intel_excl_states *xl;
1937 int tid = cpuc->excl_thread_id;
1939 if (cpuc->is_fake || !is_ht_workaround_enabled())
1942 if (WARN_ON_ONCE(!excl_cntrs))
1945 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
1948 xl = &excl_cntrs->states[tid];
1950 lockdep_assert_held(&excl_cntrs->lock);
1952 if (c->flags & PERF_X86_EVENT_EXCL)
1953 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1955 xl->state[cntr] = INTEL_EXCL_SHARED;
1959 intel_stop_scheduling(struct cpu_hw_events *cpuc)
1961 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1962 struct intel_excl_states *xl;
1963 int tid = cpuc->excl_thread_id;
1966 * nothing needed if in group validation mode
1968 if (cpuc->is_fake || !is_ht_workaround_enabled())
1971 * no exclusion needed
1973 if (WARN_ON_ONCE(!excl_cntrs))
1976 xl = &excl_cntrs->states[tid];
1978 xl->sched_started = false;
1980 * release shared state lock (acquired in intel_start_scheduling())
1982 raw_spin_unlock(&excl_cntrs->lock);
1985 static struct event_constraint *
1986 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
1987 int idx, struct event_constraint *c)
1989 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1990 struct intel_excl_states *xlo;
1991 int tid = cpuc->excl_thread_id;
1995 * validating a group does not require
1996 * enforcing cross-thread exclusion
1998 if (cpuc->is_fake || !is_ht_workaround_enabled())
2002 * no exclusion needed
2004 if (WARN_ON_ONCE(!excl_cntrs))
2008 * because we modify the constraint, we need
2009 * to make a copy. Static constraints come
2010 * from static const tables.
2012 * only needed when constraint has not yet
2013 * been cloned (marked dynamic)
2015 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2016 struct event_constraint *cx;
2019 * grab pre-allocated constraint entry
2021 cx = &cpuc->constraint_list[idx];
2024 * initialize dynamic constraint
2025 * with static constraint
2030 * mark constraint as dynamic, so we
2031 * can free it later on
2033 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2038 * From here on, the constraint is dynamic.
2039 * Either it was just allocated above, or it
2040 * was allocated during a earlier invocation
2045 * state of sibling HT
2047 xlo = &excl_cntrs->states[tid ^ 1];
2050 * event requires exclusive counter access
2053 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2054 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2055 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2056 if (!cpuc->n_excl++)
2057 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2061 * Modify static constraint with current dynamic
2064 * EXCLUSIVE: sibling counter measuring exclusive event
2065 * SHARED : sibling counter measuring non-exclusive event
2066 * UNUSED : sibling counter unused
2068 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2070 * exclusive event in sibling counter
2071 * our corresponding counter cannot be used
2072 * regardless of our event
2074 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2075 __clear_bit(i, c->idxmsk);
2077 * if measuring an exclusive event, sibling
2078 * measuring non-exclusive, then counter cannot
2081 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2082 __clear_bit(i, c->idxmsk);
2086 * recompute actual bit weight for scheduling algorithm
2088 c->weight = hweight64(c->idxmsk64);
2091 * if we return an empty mask, then switch
2092 * back to static empty constraint to avoid
2093 * the cost of freeing later on
2096 c = &emptyconstraint;
2101 static struct event_constraint *
2102 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2103 struct perf_event *event)
2105 struct event_constraint *c1 = cpuc->event_constraint[idx];
2106 struct event_constraint *c2;
2110 * - static constraint: no change across incremental scheduling calls
2111 * - dynamic constraint: handled by intel_get_excl_constraints()
2113 c2 = __intel_get_event_constraints(cpuc, idx, event);
2114 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2115 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2116 c1->weight = c2->weight;
2120 if (cpuc->excl_cntrs)
2121 return intel_get_excl_constraints(cpuc, event, idx, c2);
2126 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2127 struct perf_event *event)
2129 struct hw_perf_event *hwc = &event->hw;
2130 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2131 int tid = cpuc->excl_thread_id;
2132 struct intel_excl_states *xl;
2133 unsigned long flags = 0; /* keep compiler happy */
2136 * nothing needed if in group validation mode
2141 if (WARN_ON_ONCE(!excl_cntrs))
2144 xl = &excl_cntrs->states[tid];
2145 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2146 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2147 if (!--cpuc->n_excl)
2148 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2152 * put_constraint may be called from x86_schedule_events()
2153 * which already has the lock held so here make locking
2156 if (!xl->sched_started)
2157 raw_spin_lock_irqsave(&excl_cntrs->lock, flags);
2160 * if event was actually assigned, then mark the
2161 * counter state as unused now
2164 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2166 if (!xl->sched_started)
2167 raw_spin_unlock_irqrestore(&excl_cntrs->lock, flags);
2171 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2172 struct perf_event *event)
2174 struct hw_perf_event_extra *reg;
2176 reg = &event->hw.extra_reg;
2177 if (reg->idx != EXTRA_REG_NONE)
2178 __intel_shared_reg_put_constraints(cpuc, reg);
2180 reg = &event->hw.branch_reg;
2181 if (reg->idx != EXTRA_REG_NONE)
2182 __intel_shared_reg_put_constraints(cpuc, reg);
2185 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2186 struct perf_event *event)
2188 intel_put_shared_regs_event_constraints(cpuc, event);
2191 * is PMU has exclusive counter restrictions, then
2192 * all events are subject to and must call the
2193 * put_excl_constraints() routine
2195 if (cpuc->excl_cntrs)
2196 intel_put_excl_constraints(cpuc, event);
2199 static void intel_pebs_aliases_core2(struct perf_event *event)
2201 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2203 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2204 * (0x003c) so that we can use it with PEBS.
2206 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2207 * PEBS capable. However we can use INST_RETIRED.ANY_P
2208 * (0x00c0), which is a PEBS capable event, to get the same
2211 * INST_RETIRED.ANY_P counts the number of cycles that retires
2212 * CNTMASK instructions. By setting CNTMASK to a value (16)
2213 * larger than the maximum number of instructions that can be
2214 * retired per cycle (4) and then inverting the condition, we
2215 * count all cycles that retire 16 or less instructions, which
2218 * Thereby we gain a PEBS capable cycle counter.
2220 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2222 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2223 event->hw.config = alt_config;
2227 static void intel_pebs_aliases_snb(struct perf_event *event)
2229 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2231 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2232 * (0x003c) so that we can use it with PEBS.
2234 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2235 * PEBS capable. However we can use UOPS_RETIRED.ALL
2236 * (0x01c2), which is a PEBS capable event, to get the same
2239 * UOPS_RETIRED.ALL counts the number of cycles that retires
2240 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2241 * larger than the maximum number of micro-ops that can be
2242 * retired per cycle (4) and then inverting the condition, we
2243 * count all cycles that retire 16 or less micro-ops, which
2246 * Thereby we gain a PEBS capable cycle counter.
2248 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2250 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2251 event->hw.config = alt_config;
2255 static int intel_pmu_hw_config(struct perf_event *event)
2257 int ret = x86_pmu_hw_config(event);
2262 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
2263 x86_pmu.pebs_aliases(event);
2265 if (needs_branch_stack(event)) {
2266 ret = intel_pmu_setup_lbr_filter(event);
2271 * BTS is set up earlier in this path, so don't account twice
2273 if (!intel_pmu_has_bts(event)) {
2274 /* disallow lbr if conflicting events are present */
2275 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2278 event->destroy = hw_perf_lbr_event_destroy;
2282 if (event->attr.type != PERF_TYPE_RAW)
2285 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2288 if (x86_pmu.version < 3)
2291 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2294 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2299 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2301 if (x86_pmu.guest_get_msrs)
2302 return x86_pmu.guest_get_msrs(nr);
2306 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2308 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2310 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2311 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2313 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2314 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2315 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
2317 * If PMU counter has PEBS enabled it is not enough to disable counter
2318 * on a guest entry since PEBS memory write can overshoot guest entry
2319 * and corrupt guest memory. Disabling PEBS solves the problem.
2321 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2322 arr[1].host = cpuc->pebs_enabled;
2329 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2331 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2332 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2335 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2336 struct perf_event *event = cpuc->events[idx];
2338 arr[idx].msr = x86_pmu_config_addr(idx);
2339 arr[idx].host = arr[idx].guest = 0;
2341 if (!test_bit(idx, cpuc->active_mask))
2344 arr[idx].host = arr[idx].guest =
2345 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2347 if (event->attr.exclude_host)
2348 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2349 else if (event->attr.exclude_guest)
2350 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2353 *nr = x86_pmu.num_counters;
2357 static void core_pmu_enable_event(struct perf_event *event)
2359 if (!event->attr.exclude_host)
2360 x86_pmu_enable_event(event);
2363 static void core_pmu_enable_all(int added)
2365 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2368 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2369 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2371 if (!test_bit(idx, cpuc->active_mask) ||
2372 cpuc->events[idx]->attr.exclude_host)
2375 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2379 static int hsw_hw_config(struct perf_event *event)
2381 int ret = intel_pmu_hw_config(event);
2385 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2387 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2390 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2391 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2394 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2395 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2396 event->attr.precise_ip > 0))
2399 if (event_is_checkpointed(event)) {
2401 * Sampling of checkpointed events can cause situations where
2402 * the CPU constantly aborts because of a overflow, which is
2403 * then checkpointed back and ignored. Forbid checkpointing
2406 * But still allow a long sampling period, so that perf stat
2409 if (event->attr.sample_period > 0 &&
2410 event->attr.sample_period < 0x7fffffff)
2416 static struct event_constraint counter2_constraint =
2417 EVENT_CONSTRAINT(0, 0x4, 0);
2419 static struct event_constraint *
2420 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2421 struct perf_event *event)
2423 struct event_constraint *c;
2425 c = intel_get_event_constraints(cpuc, idx, event);
2427 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2428 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2429 if (c->idxmsk64 & (1U << 2))
2430 return &counter2_constraint;
2431 return &emptyconstraint;
2440 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2441 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2442 * the two to enforce a minimum period of 128 (the smallest value that has bits
2443 * 0-5 cleared and >= 100).
2445 * Because of how the code in x86_perf_event_set_period() works, the truncation
2446 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2447 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2449 * Therefore the effective (average) period matches the requested period,
2450 * despite coarser hardware granularity.
2452 static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2454 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2455 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2463 PMU_FORMAT_ATTR(event, "config:0-7" );
2464 PMU_FORMAT_ATTR(umask, "config:8-15" );
2465 PMU_FORMAT_ATTR(edge, "config:18" );
2466 PMU_FORMAT_ATTR(pc, "config:19" );
2467 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2468 PMU_FORMAT_ATTR(inv, "config:23" );
2469 PMU_FORMAT_ATTR(cmask, "config:24-31" );
2470 PMU_FORMAT_ATTR(in_tx, "config:32");
2471 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
2473 static struct attribute *intel_arch_formats_attr[] = {
2474 &format_attr_event.attr,
2475 &format_attr_umask.attr,
2476 &format_attr_edge.attr,
2477 &format_attr_pc.attr,
2478 &format_attr_inv.attr,
2479 &format_attr_cmask.attr,
2483 ssize_t intel_event_sysfs_show(char *page, u64 config)
2485 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2487 return x86_event_sysfs_show(page, config, event);
2490 struct intel_shared_regs *allocate_shared_regs(int cpu)
2492 struct intel_shared_regs *regs;
2495 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2496 GFP_KERNEL, cpu_to_node(cpu));
2499 * initialize the locks to keep lockdep happy
2501 for (i = 0; i < EXTRA_REG_MAX; i++)
2502 raw_spin_lock_init(®s->regs[i].lock);
2509 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2511 struct intel_excl_cntrs *c;
2513 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2514 GFP_KERNEL, cpu_to_node(cpu));
2516 raw_spin_lock_init(&c->lock);
2522 static int intel_pmu_cpu_prepare(int cpu)
2524 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2526 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2527 cpuc->shared_regs = allocate_shared_regs(cpu);
2528 if (!cpuc->shared_regs)
2532 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2533 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2535 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2536 if (!cpuc->constraint_list)
2539 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2540 if (!cpuc->excl_cntrs) {
2541 kfree(cpuc->constraint_list);
2542 kfree(cpuc->shared_regs);
2545 cpuc->excl_thread_id = 0;
2551 static void intel_pmu_cpu_starting(int cpu)
2553 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2554 int core_id = topology_core_id(cpu);
2557 init_debug_store_on_cpu(cpu);
2559 * Deal with CPUs that don't clear their LBRs on power-up.
2561 intel_pmu_lbr_reset();
2563 cpuc->lbr_sel = NULL;
2565 if (!cpuc->shared_regs)
2568 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
2569 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2571 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2572 struct intel_shared_regs *pc;
2574 pc = per_cpu(cpu_hw_events, i).shared_regs;
2575 if (pc && pc->core_id == core_id) {
2576 *onln = cpuc->shared_regs;
2577 cpuc->shared_regs = pc;
2581 cpuc->shared_regs->core_id = core_id;
2582 cpuc->shared_regs->refcnt++;
2585 if (x86_pmu.lbr_sel_map)
2586 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2588 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2589 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2590 struct intel_excl_cntrs *c;
2592 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2593 if (c && c->core_id == core_id) {
2594 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2595 cpuc->excl_cntrs = c;
2596 cpuc->excl_thread_id = 1;
2600 cpuc->excl_cntrs->core_id = core_id;
2601 cpuc->excl_cntrs->refcnt++;
2605 static void free_excl_cntrs(int cpu)
2607 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2608 struct intel_excl_cntrs *c;
2610 c = cpuc->excl_cntrs;
2612 if (c->core_id == -1 || --c->refcnt == 0)
2614 cpuc->excl_cntrs = NULL;
2615 kfree(cpuc->constraint_list);
2616 cpuc->constraint_list = NULL;
2620 static void intel_pmu_cpu_dying(int cpu)
2622 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2623 struct intel_shared_regs *pc;
2625 pc = cpuc->shared_regs;
2627 if (pc->core_id == -1 || --pc->refcnt == 0)
2629 cpuc->shared_regs = NULL;
2632 free_excl_cntrs(cpu);
2634 fini_debug_store_on_cpu(cpu);
2637 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2639 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2641 static struct attribute *intel_arch3_formats_attr[] = {
2642 &format_attr_event.attr,
2643 &format_attr_umask.attr,
2644 &format_attr_edge.attr,
2645 &format_attr_pc.attr,
2646 &format_attr_any.attr,
2647 &format_attr_inv.attr,
2648 &format_attr_cmask.attr,
2649 &format_attr_in_tx.attr,
2650 &format_attr_in_tx_cp.attr,
2652 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2653 &format_attr_ldlat.attr, /* PEBS load latency */
2657 static __initconst const struct x86_pmu core_pmu = {
2659 .handle_irq = x86_pmu_handle_irq,
2660 .disable_all = x86_pmu_disable_all,
2661 .enable_all = core_pmu_enable_all,
2662 .enable = core_pmu_enable_event,
2663 .disable = x86_pmu_disable_event,
2664 .hw_config = x86_pmu_hw_config,
2665 .schedule_events = x86_schedule_events,
2666 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2667 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2668 .event_map = intel_pmu_event_map,
2669 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2672 * Intel PMCs cannot be accessed sanely above 32-bit width,
2673 * so we install an artificial 1<<31 period regardless of
2674 * the generic event period:
2676 .max_period = (1ULL<<31) - 1,
2677 .get_event_constraints = intel_get_event_constraints,
2678 .put_event_constraints = intel_put_event_constraints,
2679 .event_constraints = intel_core_event_constraints,
2680 .guest_get_msrs = core_guest_get_msrs,
2681 .format_attrs = intel_arch_formats_attr,
2682 .events_sysfs_show = intel_event_sysfs_show,
2685 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
2686 * together with PMU version 1 and thus be using core_pmu with
2687 * shared_regs. We need following callbacks here to allocate
2690 .cpu_prepare = intel_pmu_cpu_prepare,
2691 .cpu_starting = intel_pmu_cpu_starting,
2692 .cpu_dying = intel_pmu_cpu_dying,
2695 static __initconst const struct x86_pmu intel_pmu = {
2697 .handle_irq = intel_pmu_handle_irq,
2698 .disable_all = intel_pmu_disable_all,
2699 .enable_all = intel_pmu_enable_all,
2700 .enable = intel_pmu_enable_event,
2701 .disable = intel_pmu_disable_event,
2702 .hw_config = intel_pmu_hw_config,
2703 .schedule_events = x86_schedule_events,
2704 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2705 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2706 .event_map = intel_pmu_event_map,
2707 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2710 * Intel PMCs cannot be accessed sanely above 32 bit width,
2711 * so we install an artificial 1<<31 period regardless of
2712 * the generic event period:
2714 .max_period = (1ULL << 31) - 1,
2715 .get_event_constraints = intel_get_event_constraints,
2716 .put_event_constraints = intel_put_event_constraints,
2717 .pebs_aliases = intel_pebs_aliases_core2,
2719 .format_attrs = intel_arch3_formats_attr,
2720 .events_sysfs_show = intel_event_sysfs_show,
2722 .cpu_prepare = intel_pmu_cpu_prepare,
2723 .cpu_starting = intel_pmu_cpu_starting,
2724 .cpu_dying = intel_pmu_cpu_dying,
2725 .guest_get_msrs = intel_guest_get_msrs,
2726 .sched_task = intel_pmu_lbr_sched_task,
2729 static __init void intel_clovertown_quirk(void)
2732 * PEBS is unreliable due to:
2734 * AJ67 - PEBS may experience CPL leaks
2735 * AJ68 - PEBS PMI may be delayed by one event
2736 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2737 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2739 * AJ67 could be worked around by restricting the OS/USR flags.
2740 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2742 * AJ106 could possibly be worked around by not allowing LBR
2743 * usage from PEBS, including the fixup.
2744 * AJ68 could possibly be worked around by always programming
2745 * a pebs_event_reset[0] value and coping with the lost events.
2747 * But taken together it might just make sense to not enable PEBS on
2750 pr_warn("PEBS disabled due to CPU errata\n");
2752 x86_pmu.pebs_constraints = NULL;
2755 static int intel_snb_pebs_broken(int cpu)
2757 u32 rev = UINT_MAX; /* default to broken for unknown models */
2759 switch (cpu_data(cpu).x86_model) {
2764 case 45: /* SNB-EP */
2765 switch (cpu_data(cpu).x86_mask) {
2766 case 6: rev = 0x618; break;
2767 case 7: rev = 0x70c; break;
2771 return (cpu_data(cpu).microcode < rev);
2774 static void intel_snb_check_microcode(void)
2776 int pebs_broken = 0;
2780 for_each_online_cpu(cpu) {
2781 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2786 if (pebs_broken == x86_pmu.pebs_broken)
2790 * Serialized by the microcode lock..
2792 if (x86_pmu.pebs_broken) {
2793 pr_info("PEBS enabled due to microcode update\n");
2794 x86_pmu.pebs_broken = 0;
2796 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2797 x86_pmu.pebs_broken = 1;
2802 * Under certain circumstances, access certain MSR may cause #GP.
2803 * The function tests if the input MSR can be safely accessed.
2805 static bool check_msr(unsigned long msr, u64 mask)
2807 u64 val_old, val_new, val_tmp;
2810 * Read the current value, change it and read it back to see if it
2811 * matches, this is needed to detect certain hardware emulators
2812 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2814 if (rdmsrl_safe(msr, &val_old))
2818 * Only change the bits which can be updated by wrmsrl.
2820 val_tmp = val_old ^ mask;
2821 if (wrmsrl_safe(msr, val_tmp) ||
2822 rdmsrl_safe(msr, &val_new))
2825 if (val_new != val_tmp)
2828 /* Here it's sure that the MSR can be safely accessed.
2829 * Restore the old value and return.
2831 wrmsrl(msr, val_old);
2836 static __init void intel_sandybridge_quirk(void)
2838 x86_pmu.check_microcode = intel_snb_check_microcode;
2839 intel_snb_check_microcode();
2842 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2843 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2844 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2845 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2846 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2847 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2848 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2849 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2852 static __init void intel_arch_events_quirk(void)
2856 /* disable event that reported as not presend by cpuid */
2857 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2858 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2859 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2860 intel_arch_events_map[bit].name);
2864 static __init void intel_nehalem_quirk(void)
2866 union cpuid10_ebx ebx;
2868 ebx.full = x86_pmu.events_maskl;
2869 if (ebx.split.no_branch_misses_retired) {
2871 * Erratum AAJ80 detected, we work it around by using
2872 * the BR_MISP_EXEC.ANY event. This will over-count
2873 * branch-misses, but it's still much better than the
2874 * architectural event which is often completely bogus:
2876 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2877 ebx.split.no_branch_misses_retired = 0;
2878 x86_pmu.events_maskl = ebx.full;
2879 pr_info("CPU erratum AAJ80 worked around\n");
2884 * enable software workaround for errata:
2889 * Only needed when HT is enabled. However detecting
2890 * if HT is enabled is difficult (model specific). So instead,
2891 * we enable the workaround in the early boot, and verify if
2892 * it is needed in a later initcall phase once we have valid
2893 * topology information to check if HT is actually enabled
2895 static __init void intel_ht_bug(void)
2897 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
2899 x86_pmu.start_scheduling = intel_start_scheduling;
2900 x86_pmu.commit_scheduling = intel_commit_scheduling;
2901 x86_pmu.stop_scheduling = intel_stop_scheduling;
2904 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2905 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2907 /* Haswell special events */
2908 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
2909 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
2910 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
2911 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
2912 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
2913 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
2914 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
2915 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
2916 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
2917 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
2918 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
2919 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
2921 static struct attribute *hsw_events_attrs[] = {
2922 EVENT_PTR(tx_start),
2923 EVENT_PTR(tx_commit),
2924 EVENT_PTR(tx_abort),
2925 EVENT_PTR(tx_capacity),
2926 EVENT_PTR(tx_conflict),
2927 EVENT_PTR(el_start),
2928 EVENT_PTR(el_commit),
2929 EVENT_PTR(el_abort),
2930 EVENT_PTR(el_capacity),
2931 EVENT_PTR(el_conflict),
2932 EVENT_PTR(cycles_t),
2933 EVENT_PTR(cycles_ct),
2934 EVENT_PTR(mem_ld_hsw),
2935 EVENT_PTR(mem_st_hsw),
2939 __init int intel_pmu_init(void)
2941 union cpuid10_edx edx;
2942 union cpuid10_eax eax;
2943 union cpuid10_ebx ebx;
2944 struct event_constraint *c;
2945 unsigned int unused;
2946 struct extra_reg *er;
2949 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2950 switch (boot_cpu_data.x86) {
2952 return p6_pmu_init();
2954 return knc_pmu_init();
2956 return p4_pmu_init();
2962 * Check whether the Architectural PerfMon supports
2963 * Branch Misses Retired hw_event or not.
2965 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2966 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2969 version = eax.split.version_id;
2973 x86_pmu = intel_pmu;
2975 x86_pmu.version = version;
2976 x86_pmu.num_counters = eax.split.num_counters;
2977 x86_pmu.cntval_bits = eax.split.bit_width;
2978 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
2980 x86_pmu.events_maskl = ebx.full;
2981 x86_pmu.events_mask_len = eax.split.mask_length;
2983 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2986 * Quirk: v2 perfmon does not report fixed-purpose events, so
2987 * assume at least 3 events:
2990 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2992 if (boot_cpu_has(X86_FEATURE_PDCM)) {
2995 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2996 x86_pmu.intel_cap.capabilities = capabilities;
3001 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3004 * Install the hw-cache-events table:
3006 switch (boot_cpu_data.x86_model) {
3007 case 14: /* 65nm Core "Yonah" */
3008 pr_cont("Core events, ");
3011 case 15: /* 65nm Core2 "Merom" */
3012 x86_add_quirk(intel_clovertown_quirk);
3013 case 22: /* 65nm Core2 "Merom-L" */
3014 case 23: /* 45nm Core2 "Penryn" */
3015 case 29: /* 45nm Core2 "Dunnington (MP) */
3016 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3017 sizeof(hw_cache_event_ids));
3019 intel_pmu_lbr_init_core();
3021 x86_pmu.event_constraints = intel_core2_event_constraints;
3022 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3023 pr_cont("Core2 events, ");
3026 case 30: /* 45nm Nehalem */
3027 case 26: /* 45nm Nehalem-EP */
3028 case 46: /* 45nm Nehalem-EX */
3029 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3030 sizeof(hw_cache_event_ids));
3031 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3032 sizeof(hw_cache_extra_regs));
3034 intel_pmu_lbr_init_nhm();
3036 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3037 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3038 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3039 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3041 x86_pmu.cpu_events = nhm_events_attrs;
3043 /* UOPS_ISSUED.STALLED_CYCLES */
3044 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3045 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3046 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3047 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3048 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3050 x86_add_quirk(intel_nehalem_quirk);
3052 pr_cont("Nehalem events, ");
3055 case 28: /* 45nm Atom "Pineview" */
3056 case 38: /* 45nm Atom "Lincroft" */
3057 case 39: /* 32nm Atom "Penwell" */
3058 case 53: /* 32nm Atom "Cloverview" */
3059 case 54: /* 32nm Atom "Cedarview" */
3060 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3061 sizeof(hw_cache_event_ids));
3063 intel_pmu_lbr_init_atom();
3065 x86_pmu.event_constraints = intel_gen_event_constraints;
3066 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
3067 pr_cont("Atom events, ");
3070 case 55: /* 22nm Atom "Silvermont" */
3071 case 76: /* 14nm Atom "Airmont" */
3072 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
3073 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3074 sizeof(hw_cache_event_ids));
3075 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3076 sizeof(hw_cache_extra_regs));
3078 intel_pmu_lbr_init_atom();
3080 x86_pmu.event_constraints = intel_slm_event_constraints;
3081 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3082 x86_pmu.extra_regs = intel_slm_extra_regs;
3083 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3084 pr_cont("Silvermont events, ");
3087 case 37: /* 32nm Westmere */
3088 case 44: /* 32nm Westmere-EP */
3089 case 47: /* 32nm Westmere-EX */
3090 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3091 sizeof(hw_cache_event_ids));
3092 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3093 sizeof(hw_cache_extra_regs));
3095 intel_pmu_lbr_init_nhm();
3097 x86_pmu.event_constraints = intel_westmere_event_constraints;
3098 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3099 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
3100 x86_pmu.extra_regs = intel_westmere_extra_regs;
3101 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3103 x86_pmu.cpu_events = nhm_events_attrs;
3105 /* UOPS_ISSUED.STALLED_CYCLES */
3106 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3107 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3108 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3109 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3110 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3112 pr_cont("Westmere events, ");
3115 case 42: /* 32nm SandyBridge */
3116 case 45: /* 32nm SandyBridge-E/EN/EP */
3117 x86_add_quirk(intel_sandybridge_quirk);
3118 x86_add_quirk(intel_ht_bug);
3119 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3120 sizeof(hw_cache_event_ids));
3121 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3122 sizeof(hw_cache_extra_regs));
3124 intel_pmu_lbr_init_snb();
3126 x86_pmu.event_constraints = intel_snb_event_constraints;
3127 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
3128 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3129 if (boot_cpu_data.x86_model == 45)
3130 x86_pmu.extra_regs = intel_snbep_extra_regs;
3132 x86_pmu.extra_regs = intel_snb_extra_regs;
3135 /* all extra regs are per-cpu when HT is on */
3136 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3137 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3139 x86_pmu.cpu_events = snb_events_attrs;
3141 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3142 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3143 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3144 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3145 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3146 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
3148 pr_cont("SandyBridge events, ");
3151 case 58: /* 22nm IvyBridge */
3152 case 62: /* 22nm IvyBridge-EP/EX */
3153 x86_add_quirk(intel_ht_bug);
3154 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3155 sizeof(hw_cache_event_ids));
3156 /* dTLB-load-misses on IVB is different than SNB */
3157 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3159 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3160 sizeof(hw_cache_extra_regs));
3162 intel_pmu_lbr_init_snb();
3164 x86_pmu.event_constraints = intel_ivb_event_constraints;
3165 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3166 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3167 if (boot_cpu_data.x86_model == 62)
3168 x86_pmu.extra_regs = intel_snbep_extra_regs;
3170 x86_pmu.extra_regs = intel_snb_extra_regs;
3171 /* all extra regs are per-cpu when HT is on */
3172 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3173 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3175 x86_pmu.cpu_events = snb_events_attrs;
3177 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3178 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3179 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3181 pr_cont("IvyBridge events, ");
3185 case 60: /* 22nm Haswell Core */
3186 case 63: /* 22nm Haswell Server */
3187 case 69: /* 22nm Haswell ULT */
3188 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
3189 x86_add_quirk(intel_ht_bug);
3190 x86_pmu.late_ack = true;
3191 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3192 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3194 intel_pmu_lbr_init_hsw();
3196 x86_pmu.event_constraints = intel_hsw_event_constraints;
3197 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3198 x86_pmu.extra_regs = intel_snbep_extra_regs;
3199 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3200 /* all extra regs are per-cpu when HT is on */
3201 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3202 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3204 x86_pmu.hw_config = hsw_hw_config;
3205 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3206 x86_pmu.cpu_events = hsw_events_attrs;
3207 x86_pmu.lbr_double_abort = true;
3208 pr_cont("Haswell events, ");
3211 case 61: /* 14nm Broadwell Core-M */
3212 case 86: /* 14nm Broadwell Xeon D */
3213 x86_pmu.late_ack = true;
3214 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3215 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3217 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3218 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3219 BDW_L3_MISS|HSW_SNOOP_DRAM;
3220 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3222 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3223 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3224 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3225 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3227 intel_pmu_lbr_init_hsw();
3229 x86_pmu.event_constraints = intel_bdw_event_constraints;
3230 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3231 x86_pmu.extra_regs = intel_snbep_extra_regs;
3232 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3233 /* all extra regs are per-cpu when HT is on */
3234 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3235 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3237 x86_pmu.hw_config = hsw_hw_config;
3238 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3239 x86_pmu.cpu_events = hsw_events_attrs;
3240 x86_pmu.limit_period = bdw_limit_period;
3241 pr_cont("Broadwell events, ");
3245 switch (x86_pmu.version) {
3247 x86_pmu.event_constraints = intel_v1_event_constraints;
3248 pr_cont("generic architected perfmon v1, ");
3252 * default constraints for v2 and up
3254 x86_pmu.event_constraints = intel_gen_event_constraints;
3255 pr_cont("generic architected perfmon, ");
3260 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3261 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3262 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3263 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3265 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3267 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3268 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3269 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3270 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3273 x86_pmu.intel_ctrl |=
3274 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3276 if (x86_pmu.event_constraints) {
3278 * event on fixed counter2 (REF_CYCLES) only works on this
3279 * counter, so do not extend mask to generic counters
3281 for_each_event_constraint(c, x86_pmu.event_constraints) {
3282 if (c->cmask != FIXED_EVENT_FLAGS
3283 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3287 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3288 c->weight += x86_pmu.num_counters;
3293 * Access LBR MSR may cause #GP under certain circumstances.
3294 * E.g. KVM doesn't support LBR MSR
3295 * Check all LBT MSR here.
3296 * Disable LBR access if any LBR MSRs can not be accessed.
3298 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3300 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3301 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3302 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3307 * Access extra MSR may cause #GP under certain circumstances.
3308 * E.g. KVM doesn't support offcore event
3309 * Check all extra_regs here.
3311 if (x86_pmu.extra_regs) {
3312 for (er = x86_pmu.extra_regs; er->msr; er++) {
3313 er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
3314 /* Disable LBR select mapping */
3315 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3316 x86_pmu.lbr_sel_map = NULL;
3320 /* Support full width counters using alternative MSR range */
3321 if (x86_pmu.intel_cap.full_width_write) {
3322 x86_pmu.max_period = x86_pmu.cntval_mask;
3323 x86_pmu.perfctr = MSR_IA32_PMC0;
3324 pr_cont("full-width counters, ");
3331 * HT bug: phase 2 init
3332 * Called once we have valid topology information to check
3333 * whether or not HT is enabled
3334 * If HT is off, then we disable the workaround
3336 static __init int fixup_ht_bug(void)
3338 int cpu = smp_processor_id();
3341 * problem not present on this CPU model, nothing to do
3343 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3346 w = cpumask_weight(topology_thread_cpumask(cpu));
3348 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3352 watchdog_nmi_disable_all();
3354 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3356 x86_pmu.start_scheduling = NULL;
3357 x86_pmu.commit_scheduling = NULL;
3358 x86_pmu.stop_scheduling = NULL;
3360 watchdog_nmi_enable_all();
3364 for_each_online_cpu(c) {
3369 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3372 subsys_initcall(fixup_ht_bug)