arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  15
  16 /*
  17  * pebs_record_32 for p4 and core not supported
  18
  19 struct pebs_record_32 {
  20         u32 flags, ip;
  21         u32 ax, bc, cx, dx;
  22         u32 si, di, bp, sp;
  23 };
  24
  25  */
  26
  27 union intel_x86_pebs_dse {
  28         u64 val;
  29         struct {
  30                 unsigned int ld_dse:4;
  31                 unsigned int ld_stlb_miss:1;
  32                 unsigned int ld_locked:1;
  33                 unsigned int ld_reserved:26;
  34         };
  35         struct {
  36                 unsigned int st_l1d_hit:1;
  37                 unsigned int st_reserved1:3;
  38                 unsigned int st_stlb_miss:1;
  39                 unsigned int st_locked:1;
  40                 unsigned int st_reserved2:26;
  41         };
  42 };
  43
  44
  45 /*
  46  * Map PEBS Load Latency Data Source encodings to generic
  47  * memory data source information
  48  */
  49 #define P(a, b) PERF_MEM_S(a, b)
  50 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  51 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  52
  53 static const u64 pebs_data_source[] = {
  54         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  55         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  56         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  57         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  58         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  62         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  64         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  65         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  66         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  67         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  68         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  69         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  70 };
  71
  72 static u64 precise_store_data(u64 status)
  73 {
  74         union intel_x86_pebs_dse dse;
  75         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  76
  77         dse.val = status;
  78
  79         /*
  80          * bit 4: TLB access
  81          * 1 = stored missed 2nd level TLB
  82          *
  83          * so it either hit the walker or the OS
  84          * otherwise hit 2nd level TLB
  85          */
  86         if (dse.st_stlb_miss)
  87                 val |= P(TLB, MISS);
  88         else
  89                 val |= P(TLB, HIT);
  90
  91         /*
  92          * bit 0: hit L1 data cache
  93          * if not set, then all we know is that
  94          * it missed L1D
  95          */
  96         if (dse.st_l1d_hit)
  97                 val |= P(LVL, HIT);
  98         else
  99                 val |= P(LVL, MISS);
 100
 101         /*
 102          * bit 5: Locked prefix
 103          */
 104         if (dse.st_locked)
 105                 val |= P(LOCK, LOCKED);
 106
 107         return val;
 108 }
 109
 110 static u64 precise_store_data_hsw(u64 status)
 111 {
 112         union perf_mem_data_src dse;
 113
 114         dse.val = 0;
 115         dse.mem_op = PERF_MEM_OP_STORE;
 116         dse.mem_lvl = PERF_MEM_LVL_NA;
 117         if (status & 1)
 118                 dse.mem_lvl = PERF_MEM_LVL_L1;
 119         /* Nothing else supported. Sorry. */
 120         return dse.val;
 121 }
 122
 123 static u64 load_latency_data(u64 status)
 124 {
 125         union intel_x86_pebs_dse dse;
 126         u64 val;
 127         int model = boot_cpu_data.x86_model;
 128         int fam = boot_cpu_data.x86;
 129
 130         dse.val = status;
 131
 132         /*
 133          * use the mapping table for bit 0-3
 134          */
 135         val = pebs_data_source[dse.ld_dse];
 136
 137         /*
 138          * Nehalem models do not support TLB, Lock infos
 139          */
 140         if (fam == 0x6 && (model == 26 || model == 30
 141             || model == 31 || model == 46)) {
 142                 val |= P(TLB, NA) | P(LOCK, NA);
 143                 return val;
 144         }
 145         /*
 146          * bit 4: TLB access
 147          * 0 = did not miss 2nd level TLB
 148          * 1 = missed 2nd level TLB
 149          */
 150         if (dse.ld_stlb_miss)
 151                 val |= P(TLB, MISS) | P(TLB, L2);
 152         else
 153                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 154
 155         /*
 156          * bit 5: locked prefix
 157          */
 158         if (dse.ld_locked)
 159                 val |= P(LOCK, LOCKED);
 160
 161         return val;
 162 }
 163
 164 struct pebs_record_core {
 165         u64 flags, ip;
 166         u64 ax, bx, cx, dx;
 167         u64 si, di, bp, sp;
 168         u64 r8,  r9,  r10, r11;
 169         u64 r12, r13, r14, r15;
 170 };
 171
 172 struct pebs_record_nhm {
 173         u64 flags, ip;
 174         u64 ax, bx, cx, dx;
 175         u64 si, di, bp, sp;
 176         u64 r8,  r9,  r10, r11;
 177         u64 r12, r13, r14, r15;
 178         u64 status, dla, dse, lat;
 179 };
 180
 181 /*
 182  * Same as pebs_record_nhm, with two additional fields.
 183  */
 184 struct pebs_record_hsw {
 185         struct pebs_record_nhm nhm;
 186         /*
 187          * Real IP of the event. In the Intel documentation this
 188          * is called eventingrip.
 189          */
 190         u64 real_ip;
 191         /*
 192          * TSX tuning information field: abort cycles and abort flags.
 193          */
 194         u64 tsx_tuning;
 195 };
 196
 197 void init_debug_store_on_cpu(int cpu)
 198 {
 199         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 200
 201         if (!ds)
 202                 return;
 203
 204         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 205                      (u32)((u64)(unsigned long)ds),
 206                      (u32)((u64)(unsigned long)ds >> 32));
 207 }
 208
 209 void fini_debug_store_on_cpu(int cpu)
 210 {
 211         if (!per_cpu(cpu_hw_events, cpu).ds)
 212                 return;
 213
 214         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 215 }
 216
 217 static int alloc_pebs_buffer(int cpu)
 218 {
 219         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 220         int node = cpu_to_node(cpu);
 221         int max, thresh = 1; /* always use a single PEBS record */
 222         void *buffer;
 223
 224         if (!x86_pmu.pebs)
 225                 return 0;
 226
 227         buffer = kmalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL | __GFP_ZERO, node);
 228         if (unlikely(!buffer))
 229                 return -ENOMEM;
 230
 231         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 232
 233         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 234         ds->pebs_index = ds->pebs_buffer_base;
 235         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 236                 max * x86_pmu.pebs_record_size;
 237
 238         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 239                 thresh * x86_pmu.pebs_record_size;
 240
 241         return 0;
 242 }
 243
 244 static void release_pebs_buffer(int cpu)
 245 {
 246         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 247
 248         if (!ds || !x86_pmu.pebs)
 249                 return;
 250
 251         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 252         ds->pebs_buffer_base = 0;
 253 }
 254
 255 static int alloc_bts_buffer(int cpu)
 256 {
 257         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 258         int node = cpu_to_node(cpu);
 259         int max, thresh;
 260         void *buffer;
 261
 262         if (!x86_pmu.bts)
 263                 return 0;
 264
 265         buffer = kmalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_ZERO, node);
 266         if (unlikely(!buffer))
 267                 return -ENOMEM;
 268
 269         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 270         thresh = max / 16;
 271
 272         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 273         ds->bts_index = ds->bts_buffer_base;
 274         ds->bts_absolute_maximum = ds->bts_buffer_base +
 275                 max * BTS_RECORD_SIZE;
 276         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 277                 thresh * BTS_RECORD_SIZE;
 278
 279         return 0;
 280 }
 281
 282 static void release_bts_buffer(int cpu)
 283 {
 284         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 285
 286         if (!ds || !x86_pmu.bts)
 287                 return;
 288
 289         kfree((void *)(unsigned long)ds->bts_buffer_base);
 290         ds->bts_buffer_base = 0;
 291 }
 292
 293 static int alloc_ds_buffer(int cpu)
 294 {
 295         int node = cpu_to_node(cpu);
 296         struct debug_store *ds;
 297
 298         ds = kmalloc_node(sizeof(*ds), GFP_KERNEL | __GFP_ZERO, node);
 299         if (unlikely(!ds))
 300                 return -ENOMEM;
 301
 302         per_cpu(cpu_hw_events, cpu).ds = ds;
 303
 304         return 0;
 305 }
 306
 307 static void release_ds_buffer(int cpu)
 308 {
 309         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 310
 311         if (!ds)
 312                 return;
 313
 314         per_cpu(cpu_hw_events, cpu).ds = NULL;
 315         kfree(ds);
 316 }
 317
 318 void release_ds_buffers(void)
 319 {
 320         int cpu;
 321
 322         if (!x86_pmu.bts && !x86_pmu.pebs)
 323                 return;
 324
 325         get_online_cpus();
 326         for_each_online_cpu(cpu)
 327                 fini_debug_store_on_cpu(cpu);
 328
 329         for_each_possible_cpu(cpu) {
 330                 release_pebs_buffer(cpu);
 331                 release_bts_buffer(cpu);
 332                 release_ds_buffer(cpu);
 333         }
 334         put_online_cpus();
 335 }
 336
 337 void reserve_ds_buffers(void)
 338 {
 339         int bts_err = 0, pebs_err = 0;
 340         int cpu;
 341
 342         x86_pmu.bts_active = 0;
 343         x86_pmu.pebs_active = 0;
 344
 345         if (!x86_pmu.bts && !x86_pmu.pebs)
 346                 return;
 347
 348         if (!x86_pmu.bts)
 349                 bts_err = 1;
 350
 351         if (!x86_pmu.pebs)
 352                 pebs_err = 1;
 353
 354         get_online_cpus();
 355
 356         for_each_possible_cpu(cpu) {
 357                 if (alloc_ds_buffer(cpu)) {
 358                         bts_err = 1;
 359                         pebs_err = 1;
 360                 }
 361
 362                 if (!bts_err && alloc_bts_buffer(cpu))
 363                         bts_err = 1;
 364
 365                 if (!pebs_err && alloc_pebs_buffer(cpu))
 366                         pebs_err = 1;
 367
 368                 if (bts_err && pebs_err)
 369                         break;
 370         }
 371
 372         if (bts_err) {
 373                 for_each_possible_cpu(cpu)
 374                         release_bts_buffer(cpu);
 375         }
 376
 377         if (pebs_err) {
 378                 for_each_possible_cpu(cpu)
 379                         release_pebs_buffer(cpu);
 380         }
 381
 382         if (bts_err && pebs_err) {
 383                 for_each_possible_cpu(cpu)
 384                         release_ds_buffer(cpu);
 385         } else {
 386                 if (x86_pmu.bts && !bts_err)
 387                         x86_pmu.bts_active = 1;
 388
 389                 if (x86_pmu.pebs && !pebs_err)
 390                         x86_pmu.pebs_active = 1;
 391
 392                 for_each_online_cpu(cpu)
 393                         init_debug_store_on_cpu(cpu);
 394         }
 395
 396         put_online_cpus();
 397 }
 398
 399 /*
 400  * BTS
 401  */
 402
 403 struct event_constraint bts_constraint =
 404         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 405
 406 void intel_pmu_enable_bts(u64 config)
 407 {
 408         unsigned long debugctlmsr;
 409
 410         debugctlmsr = get_debugctlmsr();
 411
 412         debugctlmsr |= DEBUGCTLMSR_TR;
 413         debugctlmsr |= DEBUGCTLMSR_BTS;
 414         debugctlmsr |= DEBUGCTLMSR_BTINT;
 415
 416         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 417                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 418
 419         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 420                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 421
 422         update_debugctlmsr(debugctlmsr);
 423 }
 424
 425 void intel_pmu_disable_bts(void)
 426 {
 427         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 428         unsigned long debugctlmsr;
 429
 430         if (!cpuc->ds)
 431                 return;
 432
 433         debugctlmsr = get_debugctlmsr();
 434
 435         debugctlmsr &=
 436                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 437                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 438
 439         update_debugctlmsr(debugctlmsr);
 440 }
 441
 442 int intel_pmu_drain_bts_buffer(void)
 443 {
 444         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 445         struct debug_store *ds = cpuc->ds;
 446         struct bts_record {
 447                 u64     from;
 448                 u64     to;
 449                 u64     flags;
 450         };
 451         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 452         struct bts_record *at, *top;
 453         struct perf_output_handle handle;
 454         struct perf_event_header header;
 455         struct perf_sample_data data;
 456         struct pt_regs regs;
 457
 458         if (!event)
 459                 return 0;
 460
 461         if (!x86_pmu.bts_active)
 462                 return 0;
 463
 464         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 465         top = (struct bts_record *)(unsigned long)ds->bts_index;
 466
 467         if (top <= at)
 468                 return 0;
 469
 470         memset(&regs, 0, sizeof(regs));
 471
 472         ds->bts_index = ds->bts_buffer_base;
 473
 474         perf_sample_data_init(&data, 0, event->hw.last_period);
 475
 476         /*
 477          * Prepare a generic sample, i.e. fill in the invariant fields.
 478          * We will overwrite the from and to address before we output
 479          * the sample.
 480          */
 481         perf_prepare_sample(&header, &data, event, &regs);
 482
 483         if (perf_output_begin(&handle, event, header.size * (top - at)))
 484                 return 1;
 485
 486         for (; at < top; at++) {
 487                 data.ip         = at->from;
 488                 data.addr       = at->to;
 489
 490                 perf_output_sample(&handle, &header, &data, event);
 491         }
 492
 493         perf_output_end(&handle);
 494
 495         /* There's new data available. */
 496         event->hw.interrupts++;
 497         event->pending_kill = POLL_IN;
 498         return 1;
 499 }
 500
 501 /*
 502  * PEBS
 503  */
 504 struct event_constraint intel_core2_pebs_event_constraints[] = {
 505         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 506         INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 507         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 508         INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 509         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 510         EVENT_CONSTRAINT_END
 511 };
 512
 513 struct event_constraint intel_atom_pebs_event_constraints[] = {
 514         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 515         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 516         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 517         EVENT_CONSTRAINT_END
 518 };
 519
 520 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 521         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 522         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 523         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 524         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 525         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 526         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 527         INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 528         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 529         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 530         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 531         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 532         EVENT_CONSTRAINT_END
 533 };
 534
 535 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 536         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 537         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 538         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 539         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 540         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 541         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 542         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 543         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 544         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 545         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 546         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 547         EVENT_CONSTRAINT_END
 548 };
 549
 550 struct event_constraint intel_snb_pebs_event_constraints[] = {
 551         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 552         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 553         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 554         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 555         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 556         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 557         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 558         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 559         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 560         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 561         INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
 562         EVENT_CONSTRAINT_END
 563 };
 564
 565 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 566         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 567         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 568         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 569         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 570         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 571         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 572         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 573         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 574         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 575         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 576         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 577         EVENT_CONSTRAINT_END
 578 };
 579
 580 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 581         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 582         INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 583         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 584         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 585         INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
 586         INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
 587         INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
 588         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
 589         /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 590         INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
 591         /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 592         INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
 593         INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 594         INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 595         /* MEM_UOPS_RETIRED.SPLIT_STORES */
 596         INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
 597         INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 598         INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 599         INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
 600         INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
 601         INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
 602         /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
 603         INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
 604         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
 605         INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
 606         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
 607         INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
 608         /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
 609         INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
 610         INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
 611         INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
 612
 613         EVENT_CONSTRAINT_END
 614 };
 615
 616 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 617 {
 618         struct event_constraint *c;
 619
 620         if (!event->attr.precise_ip)
 621                 return NULL;
 622
 623         if (x86_pmu.pebs_constraints) {
 624                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 625                         if ((event->hw.config & c->cmask) == c->code) {
 626                                 event->hw.flags |= c->flags;
 627                                 return c;
 628                         }
 629                 }
 630         }
 631
 632         return &emptyconstraint;
 633 }
 634
 635 void intel_pmu_pebs_enable(struct perf_event *event)
 636 {
 637         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 638         struct hw_perf_event *hwc = &event->hw;
 639
 640         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 641
 642         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 643
 644         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 645                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 646         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 647                 cpuc->pebs_enabled |= 1ULL << 63;
 648 }
 649
 650 void intel_pmu_pebs_disable(struct perf_event *event)
 651 {
 652         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 653         struct hw_perf_event *hwc = &event->hw;
 654
 655         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 656
 657         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
 658                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 659         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
 660                 cpuc->pebs_enabled &= ~(1ULL << 63);
 661
 662         if (cpuc->enabled)
 663                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 664
 665         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 666 }
 667
 668 void intel_pmu_pebs_enable_all(void)
 669 {
 670         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 671
 672         if (cpuc->pebs_enabled)
 673                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 674 }
 675
 676 void intel_pmu_pebs_disable_all(void)
 677 {
 678         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 679
 680         if (cpuc->pebs_enabled)
 681                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 682 }
 683
 684 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 685 {
 686         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 687         unsigned long from = cpuc->lbr_entries[0].from;
 688         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 689         unsigned long ip = regs->ip;
 690         int is_64bit = 0;
 691
 692         /*
 693          * We don't need to fixup if the PEBS assist is fault like
 694          */
 695         if (!x86_pmu.intel_cap.pebs_trap)
 696                 return 1;
 697
 698         /*
 699          * No LBR entry, no basic block, no rewinding
 700          */
 701         if (!cpuc->lbr_stack.nr || !from || !to)
 702                 return 0;
 703
 704         /*
 705          * Basic blocks should never cross user/kernel boundaries
 706          */
 707         if (kernel_ip(ip) != kernel_ip(to))
 708                 return 0;
 709
 710         /*
 711          * unsigned math, either ip is before the start (impossible) or
 712          * the basic block is larger than 1 page (sanity)
 713          */
 714         if ((ip - to) > PAGE_SIZE)
 715                 return 0;
 716
 717         /*
 718          * We sampled a branch insn, rewind using the LBR stack
 719          */
 720         if (ip == to) {
 721                 set_linear_ip(regs, from);
 722                 return 1;
 723         }
 724
 725         do {
 726                 struct insn insn;
 727                 u8 buf[MAX_INSN_SIZE];
 728                 void *kaddr;
 729
 730                 old_to = to;
 731                 if (!kernel_ip(ip)) {
 732                         int bytes, size = MAX_INSN_SIZE;
 733
 734                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 735                         if (bytes != size)
 736                                 return 0;
 737
 738                         kaddr = buf;
 739                 } else
 740                         kaddr = (void *)to;
 741
 742 #ifdef CONFIG_X86_64
 743                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 744 #endif
 745                 insn_init(&insn, kaddr, is_64bit);
 746                 insn_get_length(&insn);
 747                 to += insn.length;
 748         } while (to < ip);
 749
 750         if (to == ip) {
 751                 set_linear_ip(regs, old_to);
 752                 return 1;
 753         }
 754
 755         /*
 756          * Even though we decoded the basic block, the instruction stream
 757          * never matched the given IP, either the TO or the IP got corrupted.
 758          */
 759         return 0;
 760 }
 761
 762 static void __intel_pmu_pebs_event(struct perf_event *event,
 763                                    struct pt_regs *iregs, void *__pebs)
 764 {
 765         /*
 766          * We cast to pebs_record_nhm to get the load latency data
 767          * if extra_reg MSR_PEBS_LD_LAT_THRESHOLD used
 768          */
 769         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 770         struct pebs_record_nhm *pebs = __pebs;
 771         struct pebs_record_hsw *pebs_hsw = __pebs;
 772         struct perf_sample_data data;
 773         struct pt_regs regs;
 774         u64 sample_type;
 775         int fll, fst;
 776
 777         if (!intel_pmu_save_and_restart(event))
 778                 return;
 779
 780         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
 781         fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
 782                                  PERF_X86_EVENT_PEBS_ST_HSW);
 783
 784         perf_sample_data_init(&data, 0, event->hw.last_period);
 785
 786         data.period = event->hw.last_period;
 787         sample_type = event->attr.sample_type;
 788
 789         /*
 790          * if PEBS-LL or PreciseStore
 791          */
 792         if (fll || fst) {
 793                 /*
 794                  * Use latency for weight (only avail with PEBS-LL)
 795                  */
 796                 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 797                         data.weight = pebs->lat;
 798
 799                 /*
 800                  * data.data_src encodes the data source
 801                  */
 802                 if (sample_type & PERF_SAMPLE_DATA_SRC) {
 803                         if (fll)
 804                                 data.data_src.val = load_latency_data(pebs->dse);
 805                         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 806                                 data.data_src.val =
 807                                         precise_store_data_hsw(pebs->dse);
 808                         else
 809                                 data.data_src.val = precise_store_data(pebs->dse);
 810                 }
 811         }
 812
 813         /*
 814          * We use the interrupt regs as a base because the PEBS record
 815          * does not contain a full regs set, specifically it seems to
 816          * lack segment descriptors, which get used by things like
 817          * user_mode().
 818          *
 819          * In the simple case fix up only the IP and BP,SP regs, for
 820          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 821          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 822          */
 823         regs = *iregs;
 824         regs.flags = pebs->flags;
 825         set_linear_ip(&regs, pebs->ip);
 826         regs.bp = pebs->bp;
 827         regs.sp = pebs->sp;
 828
 829         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
 830                 regs.ip = pebs_hsw->real_ip;
 831                 regs.flags |= PERF_EFLAGS_EXACT;
 832         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 833                 regs.flags |= PERF_EFLAGS_EXACT;
 834         else
 835                 regs.flags &= ~PERF_EFLAGS_EXACT;
 836
 837         if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
 838                 x86_pmu.intel_cap.pebs_format >= 1)
 839                 data.addr = pebs->dla;
 840
 841         if (has_branch_stack(event))
 842                 data.br_stack = &cpuc->lbr_stack;
 843
 844         if (perf_event_overflow(event, &data, &regs))
 845                 x86_pmu_stop(event, 0);
 846 }
 847
 848 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 849 {
 850         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 851         struct debug_store *ds = cpuc->ds;
 852         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 853         struct pebs_record_core *at, *top;
 854         int n;
 855
 856         if (!x86_pmu.pebs_active)
 857                 return;
 858
 859         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 860         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 861
 862         /*
 863          * Whatever else happens, drain the thing
 864          */
 865         ds->pebs_index = ds->pebs_buffer_base;
 866
 867         if (!test_bit(0, cpuc->active_mask))
 868                 return;
 869
 870         WARN_ON_ONCE(!event);
 871
 872         if (!event->attr.precise_ip)
 873                 return;
 874
 875         n = top - at;
 876         if (n <= 0)
 877                 return;
 878
 879         /*
 880          * Should not happen, we program the threshold at 1 and do not
 881          * set a reset value.
 882          */
 883         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
 884         at += n - 1;
 885
 886         __intel_pmu_pebs_event(event, iregs, at);
 887 }
 888
 889 static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
 890                                         void *top)
 891 {
 892         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 893         struct debug_store *ds = cpuc->ds;
 894         struct perf_event *event = NULL;
 895         u64 status = 0;
 896         int bit;
 897
 898         ds->pebs_index = ds->pebs_buffer_base;
 899
 900         for (; at < top; at += x86_pmu.pebs_record_size) {
 901                 struct pebs_record_nhm *p = at;
 902
 903                 for_each_set_bit(bit, (unsigned long *)&p->status,
 904                                  x86_pmu.max_pebs_events) {
 905                         event = cpuc->events[bit];
 906                         if (!test_bit(bit, cpuc->active_mask))
 907                                 continue;
 908
 909                         WARN_ON_ONCE(!event);
 910
 911                         if (!event->attr.precise_ip)
 912                                 continue;
 913
 914                         if (__test_and_set_bit(bit, (unsigned long *)&status))
 915                                 continue;
 916
 917                         break;
 918                 }
 919
 920                 if (!event || bit >= x86_pmu.max_pebs_events)
 921                         continue;
 922
 923                 __intel_pmu_pebs_event(event, iregs, at);
 924         }
 925 }
 926
 927 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 928 {
 929         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 930         struct debug_store *ds = cpuc->ds;
 931         struct pebs_record_nhm *at, *top;
 932         int n;
 933
 934         if (!x86_pmu.pebs_active)
 935                 return;
 936
 937         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
 938         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
 939
 940         ds->pebs_index = ds->pebs_buffer_base;
 941
 942         n = top - at;
 943         if (n <= 0)
 944                 return;
 945
 946         /*
 947          * Should not happen, we program the threshold at 1 and do not
 948          * set a reset value.
 949          */
 950         WARN_ONCE(n > x86_pmu.max_pebs_events,
 951                   "Unexpected number of pebs records %d\n", n);
 952
 953         return __intel_pmu_drain_pebs_nhm(iregs, at, top);
 954 }
 955
 956 static void intel_pmu_drain_pebs_hsw(struct pt_regs *iregs)
 957 {
 958         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 959         struct debug_store *ds = cpuc->ds;
 960         struct pebs_record_hsw *at, *top;
 961         int n;
 962
 963         if (!x86_pmu.pebs_active)
 964                 return;
 965
 966         at  = (struct pebs_record_hsw *)(unsigned long)ds->pebs_buffer_base;
 967         top = (struct pebs_record_hsw *)(unsigned long)ds->pebs_index;
 968
 969         n = top - at;
 970         if (n <= 0)
 971                 return;
 972         /*
 973          * Should not happen, we program the threshold at 1 and do not
 974          * set a reset value.
 975          */
 976         WARN_ONCE(n > x86_pmu.max_pebs_events,
 977                   "Unexpected number of pebs records %d\n", n);
 978
 979         return __intel_pmu_drain_pebs_nhm(iregs, at, top);
 980 }
 981
 982 /*
 983  * BTS, PEBS probe and setup
 984  */
 985
 986 void intel_ds_init(void)
 987 {
 988         /*
 989          * No support for 32bit formats
 990          */
 991         if (!boot_cpu_has(X86_FEATURE_DTES64))
 992                 return;
 993
 994         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
 995         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
 996         if (x86_pmu.pebs) {
 997                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
 998                 int format = x86_pmu.intel_cap.pebs_format;
 999
1000                 switch (format) {
1001                 case 0:
1002                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1003                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1004                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1005                         break;
1006
1007                 case 1:
1008                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1009                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1010                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1011                         break;
1012
1013                 case 2:
1014                         pr_cont("PEBS fmt2%c, ", pebs_type);
1015                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1016                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_hsw;
1017                         break;
1018
1019                 default:
1020                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1021                         x86_pmu.pebs = 0;
1022                 }
1023         }
1024 }
1025
1026 void perf_restore_debug_store(void)
1027 {
1028         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1029
1030         if (!x86_pmu.bts && !x86_pmu.pebs)
1031                 return;
1032
1033         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1034 }