arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  15 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  16
  17 /*
  18  * pebs_record_32 for p4 and core not supported
  19
  20 struct pebs_record_32 {
  21         u32 flags, ip;
  22         u32 ax, bc, cx, dx;
  23         u32 si, di, bp, sp;
  24 };
  25
  26  */
  27
  28 union intel_x86_pebs_dse {
  29         u64 val;
  30         struct {
  31                 unsigned int ld_dse:4;
  32                 unsigned int ld_stlb_miss:1;
  33                 unsigned int ld_locked:1;
  34                 unsigned int ld_reserved:26;
  35         };
  36         struct {
  37                 unsigned int st_l1d_hit:1;
  38                 unsigned int st_reserved1:3;
  39                 unsigned int st_stlb_miss:1;
  40                 unsigned int st_locked:1;
  41                 unsigned int st_reserved2:26;
  42         };
  43 };
  44
  45
  46 /*
  47  * Map PEBS Load Latency Data Source encodings to generic
  48  * memory data source information
  49  */
  50 #define P(a, b) PERF_MEM_S(a, b)
  51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  53
  54 static const u64 pebs_data_source[] = {
  55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  71 };
  72
  73 static u64 precise_store_data(u64 status)
  74 {
  75         union intel_x86_pebs_dse dse;
  76         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  77
  78         dse.val = status;
  79
  80         /*
  81          * bit 4: TLB access
  82          * 1 = stored missed 2nd level TLB
  83          *
  84          * so it either hit the walker or the OS
  85          * otherwise hit 2nd level TLB
  86          */
  87         if (dse.st_stlb_miss)
  88                 val |= P(TLB, MISS);
  89         else
  90                 val |= P(TLB, HIT);
  91
  92         /*
  93          * bit 0: hit L1 data cache
  94          * if not set, then all we know is that
  95          * it missed L1D
  96          */
  97         if (dse.st_l1d_hit)
  98                 val |= P(LVL, HIT);
  99         else
 100                 val |= P(LVL, MISS);
 101
 102         /*
 103          * bit 5: Locked prefix
 104          */
 105         if (dse.st_locked)
 106                 val |= P(LOCK, LOCKED);
 107
 108         return val;
 109 }
 110
 111 static u64 precise_store_data_hsw(struct perf_event *event, u64 status)
 112 {
 113         union perf_mem_data_src dse;
 114         u64 cfg = event->hw.config & INTEL_ARCH_EVENT_MASK;
 115
 116         dse.val = 0;
 117         dse.mem_op = PERF_MEM_OP_STORE;
 118         dse.mem_lvl = PERF_MEM_LVL_NA;
 119
 120         /*
 121          * L1 info only valid for following events:
 122          *
 123          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 124          * MEM_UOPS_RETIRED.LOCK_STORES
 125          * MEM_UOPS_RETIRED.SPLIT_STORES
 126          * MEM_UOPS_RETIRED.ALL_STORES
 127          */
 128         if (cfg != 0x12d0 && cfg != 0x22d0 && cfg != 0x42d0 && cfg != 0x82d0)
 129                 return dse.mem_lvl;
 130
 131         if (status & 1)
 132                 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 133         else
 134                 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 135
 136         /* Nothing else supported. Sorry. */
 137         return dse.val;
 138 }
 139
 140 static u64 load_latency_data(u64 status)
 141 {
 142         union intel_x86_pebs_dse dse;
 143         u64 val;
 144         int model = boot_cpu_data.x86_model;
 145         int fam = boot_cpu_data.x86;
 146
 147         dse.val = status;
 148
 149         /*
 150          * use the mapping table for bit 0-3
 151          */
 152         val = pebs_data_source[dse.ld_dse];
 153
 154         /*
 155          * Nehalem models do not support TLB, Lock infos
 156          */
 157         if (fam == 0x6 && (model == 26 || model == 30
 158             || model == 31 || model == 46)) {
 159                 val |= P(TLB, NA) | P(LOCK, NA);
 160                 return val;
 161         }
 162         /*
 163          * bit 4: TLB access
 164          * 0 = did not miss 2nd level TLB
 165          * 1 = missed 2nd level TLB
 166          */
 167         if (dse.ld_stlb_miss)
 168                 val |= P(TLB, MISS) | P(TLB, L2);
 169         else
 170                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 171
 172         /*
 173          * bit 5: locked prefix
 174          */
 175         if (dse.ld_locked)
 176                 val |= P(LOCK, LOCKED);
 177
 178         return val;
 179 }
 180
 181 struct pebs_record_core {
 182         u64 flags, ip;
 183         u64 ax, bx, cx, dx;
 184         u64 si, di, bp, sp;
 185         u64 r8,  r9,  r10, r11;
 186         u64 r12, r13, r14, r15;
 187 };
 188
 189 struct pebs_record_nhm {
 190         u64 flags, ip;
 191         u64 ax, bx, cx, dx;
 192         u64 si, di, bp, sp;
 193         u64 r8,  r9,  r10, r11;
 194         u64 r12, r13, r14, r15;
 195         u64 status, dla, dse, lat;
 196 };
 197
 198 /*
 199  * Same as pebs_record_nhm, with two additional fields.
 200  */
 201 struct pebs_record_hsw {
 202         u64 flags, ip;
 203         u64 ax, bx, cx, dx;
 204         u64 si, di, bp, sp;
 205         u64 r8,  r9,  r10, r11;
 206         u64 r12, r13, r14, r15;
 207         u64 status, dla, dse, lat;
 208         u64 real_ip, tsx_tuning;
 209 };
 210
 211 union hsw_tsx_tuning {
 212         struct {
 213                 u32 cycles_last_block     : 32,
 214                     hle_abort             : 1,
 215                     rtm_abort             : 1,
 216                     instruction_abort     : 1,
 217                     non_instruction_abort : 1,
 218                     retry                 : 1,
 219                     data_conflict         : 1,
 220                     capacity_writes       : 1,
 221                     capacity_reads        : 1;
 222         };
 223         u64         value;
 224 };
 225
 226 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 227
 228 void init_debug_store_on_cpu(int cpu)
 229 {
 230         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 231
 232         if (!ds)
 233                 return;
 234
 235         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 236                      (u32)((u64)(unsigned long)ds),
 237                      (u32)((u64)(unsigned long)ds >> 32));
 238 }
 239
 240 void fini_debug_store_on_cpu(int cpu)
 241 {
 242         if (!per_cpu(cpu_hw_events, cpu).ds)
 243                 return;
 244
 245         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 246 }
 247
 248 static DEFINE_PER_CPU(void *, insn_buffer);
 249
 250 static int alloc_pebs_buffer(int cpu)
 251 {
 252         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 253         int node = cpu_to_node(cpu);
 254         int max, thresh = 1; /* always use a single PEBS record */
 255         void *buffer, *ibuffer;
 256
 257         if (!x86_pmu.pebs)
 258                 return 0;
 259
 260         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 261         if (unlikely(!buffer))
 262                 return -ENOMEM;
 263
 264         /*
 265          * HSW+ already provides us the eventing ip; no need to allocate this
 266          * buffer then.
 267          */
 268         if (x86_pmu.intel_cap.pebs_format < 2) {
 269                 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 270                 if (!ibuffer) {
 271                         kfree(buffer);
 272                         return -ENOMEM;
 273                 }
 274                 per_cpu(insn_buffer, cpu) = ibuffer;
 275         }
 276
 277         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 278
 279         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 280         ds->pebs_index = ds->pebs_buffer_base;
 281         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 282                 max * x86_pmu.pebs_record_size;
 283
 284         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 285                 thresh * x86_pmu.pebs_record_size;
 286
 287         return 0;
 288 }
 289
 290 static void release_pebs_buffer(int cpu)
 291 {
 292         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 293
 294         if (!ds || !x86_pmu.pebs)
 295                 return;
 296
 297         kfree(per_cpu(insn_buffer, cpu));
 298         per_cpu(insn_buffer, cpu) = NULL;
 299
 300         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 301         ds->pebs_buffer_base = 0;
 302 }
 303
 304 static int alloc_bts_buffer(int cpu)
 305 {
 306         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 307         int node = cpu_to_node(cpu);
 308         int max, thresh;
 309         void *buffer;
 310
 311         if (!x86_pmu.bts)
 312                 return 0;
 313
 314         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
 315         if (unlikely(!buffer)) {
 316                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 317                 return -ENOMEM;
 318         }
 319
 320         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 321         thresh = max / 16;
 322
 323         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 324         ds->bts_index = ds->bts_buffer_base;
 325         ds->bts_absolute_maximum = ds->bts_buffer_base +
 326                 max * BTS_RECORD_SIZE;
 327         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 328                 thresh * BTS_RECORD_SIZE;
 329
 330         return 0;
 331 }
 332
 333 static void release_bts_buffer(int cpu)
 334 {
 335         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 336
 337         if (!ds || !x86_pmu.bts)
 338                 return;
 339
 340         kfree((void *)(unsigned long)ds->bts_buffer_base);
 341         ds->bts_buffer_base = 0;
 342 }
 343
 344 static int alloc_ds_buffer(int cpu)
 345 {
 346         int node = cpu_to_node(cpu);
 347         struct debug_store *ds;
 348
 349         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 350         if (unlikely(!ds))
 351                 return -ENOMEM;
 352
 353         per_cpu(cpu_hw_events, cpu).ds = ds;
 354
 355         return 0;
 356 }
 357
 358 static void release_ds_buffer(int cpu)
 359 {
 360         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 361
 362         if (!ds)
 363                 return;
 364
 365         per_cpu(cpu_hw_events, cpu).ds = NULL;
 366         kfree(ds);
 367 }
 368
 369 void release_ds_buffers(void)
 370 {
 371         int cpu;
 372
 373         if (!x86_pmu.bts && !x86_pmu.pebs)
 374                 return;
 375
 376         get_online_cpus();
 377         for_each_online_cpu(cpu)
 378                 fini_debug_store_on_cpu(cpu);
 379
 380         for_each_possible_cpu(cpu) {
 381                 release_pebs_buffer(cpu);
 382                 release_bts_buffer(cpu);
 383                 release_ds_buffer(cpu);
 384         }
 385         put_online_cpus();
 386 }
 387
 388 void reserve_ds_buffers(void)
 389 {
 390         int bts_err = 0, pebs_err = 0;
 391         int cpu;
 392
 393         x86_pmu.bts_active = 0;
 394         x86_pmu.pebs_active = 0;
 395
 396         if (!x86_pmu.bts && !x86_pmu.pebs)
 397                 return;
 398
 399         if (!x86_pmu.bts)
 400                 bts_err = 1;
 401
 402         if (!x86_pmu.pebs)
 403                 pebs_err = 1;
 404
 405         get_online_cpus();
 406
 407         for_each_possible_cpu(cpu) {
 408                 if (alloc_ds_buffer(cpu)) {
 409                         bts_err = 1;
 410                         pebs_err = 1;
 411                 }
 412
 413                 if (!bts_err && alloc_bts_buffer(cpu))
 414                         bts_err = 1;
 415
 416                 if (!pebs_err && alloc_pebs_buffer(cpu))
 417                         pebs_err = 1;
 418
 419                 if (bts_err && pebs_err)
 420                         break;
 421         }
 422
 423         if (bts_err) {
 424                 for_each_possible_cpu(cpu)
 425                         release_bts_buffer(cpu);
 426         }
 427
 428         if (pebs_err) {
 429                 for_each_possible_cpu(cpu)
 430                         release_pebs_buffer(cpu);
 431         }
 432
 433         if (bts_err && pebs_err) {
 434                 for_each_possible_cpu(cpu)
 435                         release_ds_buffer(cpu);
 436         } else {
 437                 if (x86_pmu.bts && !bts_err)
 438                         x86_pmu.bts_active = 1;
 439
 440                 if (x86_pmu.pebs && !pebs_err)
 441                         x86_pmu.pebs_active = 1;
 442
 443                 for_each_online_cpu(cpu)
 444                         init_debug_store_on_cpu(cpu);
 445         }
 446
 447         put_online_cpus();
 448 }
 449
 450 /*
 451  * BTS
 452  */
 453
 454 struct event_constraint bts_constraint =
 455         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 456
 457 void intel_pmu_enable_bts(u64 config)
 458 {
 459         unsigned long debugctlmsr;
 460
 461         debugctlmsr = get_debugctlmsr();
 462
 463         debugctlmsr |= DEBUGCTLMSR_TR;
 464         debugctlmsr |= DEBUGCTLMSR_BTS;
 465         debugctlmsr |= DEBUGCTLMSR_BTINT;
 466
 467         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 468                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 469
 470         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 471                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 472
 473         update_debugctlmsr(debugctlmsr);
 474 }
 475
 476 void intel_pmu_disable_bts(void)
 477 {
 478         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 479         unsigned long debugctlmsr;
 480
 481         if (!cpuc->ds)
 482                 return;
 483
 484         debugctlmsr = get_debugctlmsr();
 485
 486         debugctlmsr &=
 487                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 488                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 489
 490         update_debugctlmsr(debugctlmsr);
 491 }
 492
 493 int intel_pmu_drain_bts_buffer(void)
 494 {
 495         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 496         struct debug_store *ds = cpuc->ds;
 497         struct bts_record {
 498                 u64     from;
 499                 u64     to;
 500                 u64     flags;
 501         };
 502         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 503         struct bts_record *at, *top;
 504         struct perf_output_handle handle;
 505         struct perf_event_header header;
 506         struct perf_sample_data data;
 507         struct pt_regs regs;
 508
 509         if (!event)
 510                 return 0;
 511
 512         if (!x86_pmu.bts_active)
 513                 return 0;
 514
 515         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 516         top = (struct bts_record *)(unsigned long)ds->bts_index;
 517
 518         if (top <= at)
 519                 return 0;
 520
 521         memset(&regs, 0, sizeof(regs));
 522
 523         ds->bts_index = ds->bts_buffer_base;
 524
 525         perf_sample_data_init(&data, 0, event->hw.last_period);
 526
 527         /*
 528          * Prepare a generic sample, i.e. fill in the invariant fields.
 529          * We will overwrite the from and to address before we output
 530          * the sample.
 531          */
 532         perf_prepare_sample(&header, &data, event, &regs);
 533
 534         if (perf_output_begin(&handle, event, header.size * (top - at)))
 535                 return 1;
 536
 537         for (; at < top; at++) {
 538                 data.ip         = at->from;
 539                 data.addr       = at->to;
 540
 541                 perf_output_sample(&handle, &header, &data, event);
 542         }
 543
 544         perf_output_end(&handle);
 545
 546         /* There's new data available. */
 547         event->hw.interrupts++;
 548         event->pending_kill = POLL_IN;
 549         return 1;
 550 }
 551
 552 /*
 553  * PEBS
 554  */
 555 struct event_constraint intel_core2_pebs_event_constraints[] = {
 556         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 557         INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 558         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 559         INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 560         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 561         EVENT_CONSTRAINT_END
 562 };
 563
 564 struct event_constraint intel_atom_pebs_event_constraints[] = {
 565         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 566         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 567         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 568         EVENT_CONSTRAINT_END
 569 };
 570
 571 struct event_constraint intel_slm_pebs_event_constraints[] = {
 572         INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
 573         INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
 574         INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
 575         INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
 576         INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
 577         INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
 578         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
 579         INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
 580         INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
 581         INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
 582         INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
 583         INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
 584         INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
 585         INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
 586         INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
 587         INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
 588         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
 589         INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
 590         INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
 591         INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
 592         INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
 593         INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
 594         EVENT_CONSTRAINT_END
 595 };
 596
 597 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 598         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 599         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 600         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 601         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 602         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 603         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 604         INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 605         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 606         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 607         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 608         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 609         EVENT_CONSTRAINT_END
 610 };
 611
 612 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 613         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 614         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 615         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 616         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 617         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 618         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 619         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 620         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 621         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 622         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 623         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 624         EVENT_CONSTRAINT_END
 625 };
 626
 627 struct event_constraint intel_snb_pebs_event_constraints[] = {
 628         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 629         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 630         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 631         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 632         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 633         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 634         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 635         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 636         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 637         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 638         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 639         INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
 640         EVENT_CONSTRAINT_END
 641 };
 642
 643 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 644         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 645         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 646         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 647         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 648         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 649         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 650         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 651         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 652         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 653         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 654         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 655         EVENT_CONSTRAINT_END
 656 };
 657
 658 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 659         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 660         INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 661         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
 662         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 663         INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
 664         INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
 665         INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
 666         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
 667         /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 668         INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
 669         /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 670         INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
 671         INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 672         INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 673         /* MEM_UOPS_RETIRED.SPLIT_STORES */
 674         INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
 675         INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 676         INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 677         INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
 678         INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
 679         INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
 680         /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
 681         INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
 682         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
 683         INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
 684         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
 685         INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
 686         /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
 687         INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
 688         INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
 689         INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
 690
 691         EVENT_CONSTRAINT_END
 692 };
 693
 694 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 695 {
 696         struct event_constraint *c;
 697
 698         if (!event->attr.precise_ip)
 699                 return NULL;
 700
 701         if (x86_pmu.pebs_constraints) {
 702                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 703                         if ((event->hw.config & c->cmask) == c->code) {
 704                                 event->hw.flags |= c->flags;
 705                                 return c;
 706                         }
 707                 }
 708         }
 709
 710         return &emptyconstraint;
 711 }
 712
 713 void intel_pmu_pebs_enable(struct perf_event *event)
 714 {
 715         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 716         struct hw_perf_event *hwc = &event->hw;
 717
 718         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 719
 720         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 721
 722         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 723                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 724         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 725                 cpuc->pebs_enabled |= 1ULL << 63;
 726 }
 727
 728 void intel_pmu_pebs_disable(struct perf_event *event)
 729 {
 730         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 731         struct hw_perf_event *hwc = &event->hw;
 732
 733         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 734
 735         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
 736                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 737         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
 738                 cpuc->pebs_enabled &= ~(1ULL << 63);
 739
 740         if (cpuc->enabled)
 741                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 742
 743         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 744 }
 745
 746 void intel_pmu_pebs_enable_all(void)
 747 {
 748         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 749
 750         if (cpuc->pebs_enabled)
 751                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 752 }
 753
 754 void intel_pmu_pebs_disable_all(void)
 755 {
 756         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 757
 758         if (cpuc->pebs_enabled)
 759                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 760 }
 761
 762 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 763 {
 764         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 765         unsigned long from = cpuc->lbr_entries[0].from;
 766         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 767         unsigned long ip = regs->ip;
 768         int is_64bit = 0;
 769         void *kaddr;
 770
 771         /*
 772          * We don't need to fixup if the PEBS assist is fault like
 773          */
 774         if (!x86_pmu.intel_cap.pebs_trap)
 775                 return 1;
 776
 777         /*
 778          * No LBR entry, no basic block, no rewinding
 779          */
 780         if (!cpuc->lbr_stack.nr || !from || !to)
 781                 return 0;
 782
 783         /*
 784          * Basic blocks should never cross user/kernel boundaries
 785          */
 786         if (kernel_ip(ip) != kernel_ip(to))
 787                 return 0;
 788
 789         /*
 790          * unsigned math, either ip is before the start (impossible) or
 791          * the basic block is larger than 1 page (sanity)
 792          */
 793         if ((ip - to) > PEBS_FIXUP_SIZE)
 794                 return 0;
 795
 796         /*
 797          * We sampled a branch insn, rewind using the LBR stack
 798          */
 799         if (ip == to) {
 800                 set_linear_ip(regs, from);
 801                 return 1;
 802         }
 803
 804         if (!kernel_ip(ip)) {
 805                 int size, bytes;
 806                 u8 *buf = this_cpu_read(insn_buffer);
 807
 808                 size = ip - to; /* Must fit our buffer, see above */
 809                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 810                 if (bytes != 0)
 811                         return 0;
 812
 813                 kaddr = buf;
 814         } else {
 815                 kaddr = (void *)to;
 816         }
 817
 818         do {
 819                 struct insn insn;
 820
 821                 old_to = to;
 822
 823 #ifdef CONFIG_X86_64
 824                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 825 #endif
 826                 insn_init(&insn, kaddr, is_64bit);
 827                 insn_get_length(&insn);
 828
 829                 to += insn.length;
 830                 kaddr += insn.length;
 831         } while (to < ip);
 832
 833         if (to == ip) {
 834                 set_linear_ip(regs, old_to);
 835                 return 1;
 836         }
 837
 838         /*
 839          * Even though we decoded the basic block, the instruction stream
 840          * never matched the given IP, either the TO or the IP got corrupted.
 841          */
 842         return 0;
 843 }
 844
 845 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
 846 {
 847         if (pebs->tsx_tuning) {
 848                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 849                 return tsx.cycles_last_block;
 850         }
 851         return 0;
 852 }
 853
 854 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
 855 {
 856         u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
 857
 858         /* For RTM XABORTs also log the abort code from AX */
 859         if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
 860                 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
 861         return txn;
 862 }
 863
 864 static void __intel_pmu_pebs_event(struct perf_event *event,
 865                                    struct pt_regs *iregs, void *__pebs)
 866 {
 867         /*
 868          * We cast to the biggest pebs_record but are careful not to
 869          * unconditionally access the 'extra' entries.
 870          */
 871         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 872         struct pebs_record_hsw *pebs = __pebs;
 873         struct perf_sample_data data;
 874         struct pt_regs regs;
 875         u64 sample_type;
 876         int fll, fst;
 877
 878         if (!intel_pmu_save_and_restart(event))
 879                 return;
 880
 881         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
 882         fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
 883                                  PERF_X86_EVENT_PEBS_ST_HSW);
 884
 885         perf_sample_data_init(&data, 0, event->hw.last_period);
 886
 887         data.period = event->hw.last_period;
 888         sample_type = event->attr.sample_type;
 889
 890         /*
 891          * if PEBS-LL or PreciseStore
 892          */
 893         if (fll || fst) {
 894                 /*
 895                  * Use latency for weight (only avail with PEBS-LL)
 896                  */
 897                 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 898                         data.weight = pebs->lat;
 899
 900                 /*
 901                  * data.data_src encodes the data source
 902                  */
 903                 if (sample_type & PERF_SAMPLE_DATA_SRC) {
 904                         if (fll)
 905                                 data.data_src.val = load_latency_data(pebs->dse);
 906                         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 907                                 data.data_src.val =
 908                                         precise_store_data_hsw(event, pebs->dse);
 909                         else
 910                                 data.data_src.val = precise_store_data(pebs->dse);
 911                 }
 912         }
 913
 914         /*
 915          * We use the interrupt regs as a base because the PEBS record
 916          * does not contain a full regs set, specifically it seems to
 917          * lack segment descriptors, which get used by things like
 918          * user_mode().
 919          *
 920          * In the simple case fix up only the IP and BP,SP regs, for
 921          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 922          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 923          */
 924         regs = *iregs;
 925         regs.flags = pebs->flags;
 926         set_linear_ip(&regs, pebs->ip);
 927         regs.bp = pebs->bp;
 928         regs.sp = pebs->sp;
 929
 930         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
 931                 regs.ip = pebs->real_ip;
 932                 regs.flags |= PERF_EFLAGS_EXACT;
 933         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 934                 regs.flags |= PERF_EFLAGS_EXACT;
 935         else
 936                 regs.flags &= ~PERF_EFLAGS_EXACT;
 937
 938         if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
 939             x86_pmu.intel_cap.pebs_format >= 1)
 940                 data.addr = pebs->dla;
 941
 942         if (x86_pmu.intel_cap.pebs_format >= 2) {
 943                 /* Only set the TSX weight when no memory weight. */
 944                 if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)
 945                         data.weight = intel_hsw_weight(pebs);
 946
 947                 if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)
 948                         data.txn = intel_hsw_transaction(pebs);
 949         }
 950
 951         if (has_branch_stack(event))
 952                 data.br_stack = &cpuc->lbr_stack;
 953
 954         if (perf_event_overflow(event, &data, &regs))
 955                 x86_pmu_stop(event, 0);
 956 }
 957
 958 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 959 {
 960         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 961         struct debug_store *ds = cpuc->ds;
 962         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 963         struct pebs_record_core *at, *top;
 964         int n;
 965
 966         if (!x86_pmu.pebs_active)
 967                 return;
 968
 969         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 970         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 971
 972         /*
 973          * Whatever else happens, drain the thing
 974          */
 975         ds->pebs_index = ds->pebs_buffer_base;
 976
 977         if (!test_bit(0, cpuc->active_mask))
 978                 return;
 979
 980         WARN_ON_ONCE(!event);
 981
 982         if (!event->attr.precise_ip)
 983                 return;
 984
 985         n = top - at;
 986         if (n <= 0)
 987                 return;
 988
 989         /*
 990          * Should not happen, we program the threshold at 1 and do not
 991          * set a reset value.
 992          */
 993         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
 994         at += n - 1;
 995
 996         __intel_pmu_pebs_event(event, iregs, at);
 997 }
 998
 999 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1000 {
1001         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1002         struct debug_store *ds = cpuc->ds;
1003         struct perf_event *event = NULL;
1004         void *at, *top;
1005         u64 status = 0;
1006         int bit;
1007
1008         if (!x86_pmu.pebs_active)
1009                 return;
1010
1011         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1012         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1013
1014         ds->pebs_index = ds->pebs_buffer_base;
1015
1016         if (unlikely(at > top))
1017                 return;
1018
1019         /*
1020          * Should not happen, we program the threshold at 1 and do not
1021          * set a reset value.
1022          */
1023         WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
1024                   "Unexpected number of pebs records %ld\n",
1025                   (long)(top - at) / x86_pmu.pebs_record_size);
1026
1027         for (; at < top; at += x86_pmu.pebs_record_size) {
1028                 struct pebs_record_nhm *p = at;
1029
1030                 for_each_set_bit(bit, (unsigned long *)&p->status,
1031                                  x86_pmu.max_pebs_events) {
1032                         event = cpuc->events[bit];
1033                         if (!test_bit(bit, cpuc->active_mask))
1034                                 continue;
1035
1036                         WARN_ON_ONCE(!event);
1037
1038                         if (!event->attr.precise_ip)
1039                                 continue;
1040
1041                         if (__test_and_set_bit(bit, (unsigned long *)&status))
1042                                 continue;
1043
1044                         break;
1045                 }
1046
1047                 if (!event || bit >= x86_pmu.max_pebs_events)
1048                         continue;
1049
1050                 __intel_pmu_pebs_event(event, iregs, at);
1051         }
1052 }
1053
1054 /*
1055  * BTS, PEBS probe and setup
1056  */
1057
1058 void intel_ds_init(void)
1059 {
1060         /*
1061          * No support for 32bit formats
1062          */
1063         if (!boot_cpu_has(X86_FEATURE_DTES64))
1064                 return;
1065
1066         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1067         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1068         if (x86_pmu.pebs) {
1069                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1070                 int format = x86_pmu.intel_cap.pebs_format;
1071
1072                 switch (format) {
1073                 case 0:
1074                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1075                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1076                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1077                         break;
1078
1079                 case 1:
1080                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1081                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1082                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1083                         break;
1084
1085                 case 2:
1086                         pr_cont("PEBS fmt2%c, ", pebs_type);
1087                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1088                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1089                         break;
1090
1091                 default:
1092                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1093                         x86_pmu.pebs = 0;
1094                 }
1095         }
1096 }
1097
1098 void perf_restore_debug_store(void)
1099 {
1100         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1101
1102         if (!x86_pmu.bts && !x86_pmu.pebs)
1103                 return;
1104
1105         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1106 }