1 #include <linux/perf_event.h>
2 #include <linux/types.h>
4 #include <asm/perf_event.h>
8 #include "perf_event.h"
12 LBR_FORMAT_LIP = 0x01,
13 LBR_FORMAT_EIP = 0x02,
14 LBR_FORMAT_EIP_FLAGS = 0x03,
15 LBR_FORMAT_EIP_FLAGS2 = 0x04,
16 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_EIP_FLAGS2,
22 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
23 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
24 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
28 * Intel LBR_SELECT bits
29 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
31 * Hardware branch filter (not available on all CPUs)
33 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
34 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
35 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
36 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
37 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
38 #define LBR_RETURN_BIT 5 /* do not capture near returns */
39 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
40 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
41 #define LBR_FAR_BIT 8 /* do not capture far branches */
43 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
44 #define LBR_USER (1 << LBR_USER_BIT)
45 #define LBR_JCC (1 << LBR_JCC_BIT)
46 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
47 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
48 #define LBR_RETURN (1 << LBR_RETURN_BIT)
49 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
50 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
51 #define LBR_FAR (1 << LBR_FAR_BIT)
53 #define LBR_PLM (LBR_KERNEL | LBR_USER)
55 #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
56 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
57 #define LBR_IGN 0 /* ignored */
68 #define LBR_FROM_FLAG_MISPRED (1ULL << 63)
69 #define LBR_FROM_FLAG_IN_TX (1ULL << 62)
70 #define LBR_FROM_FLAG_ABORT (1ULL << 61)
72 #define for_each_branch_sample_type(x) \
73 for ((x) = PERF_SAMPLE_BRANCH_USER; \
74 (x) < PERF_SAMPLE_BRANCH_MAX; (x) <<= 1)
77 * x86control flow change classification
78 * x86control flow changes include branches, interrupts, traps, faults
81 X86_BR_NONE = 0, /* unknown */
83 X86_BR_USER = 1 << 0, /* branch target is user */
84 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
86 X86_BR_CALL = 1 << 2, /* call */
87 X86_BR_RET = 1 << 3, /* return */
88 X86_BR_SYSCALL = 1 << 4, /* syscall */
89 X86_BR_SYSRET = 1 << 5, /* syscall return */
90 X86_BR_INT = 1 << 6, /* sw interrupt */
91 X86_BR_IRET = 1 << 7, /* return from interrupt */
92 X86_BR_JCC = 1 << 8, /* conditional */
93 X86_BR_JMP = 1 << 9, /* jump */
94 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
95 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
96 X86_BR_ABORT = 1 << 12,/* transaction abort */
97 X86_BR_IN_TX = 1 << 13,/* in transaction */
98 X86_BR_NO_TX = 1 << 14,/* not in transaction */
101 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
102 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
117 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
119 #define X86_BR_ANY_CALL \
126 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
129 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
130 * otherwise it becomes near impossible to get a reliable stack.
133 static void __intel_pmu_lbr_enable(void)
136 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
139 wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config);
141 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
142 debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
143 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
146 static void __intel_pmu_lbr_disable(void)
150 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
151 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
152 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
155 static void intel_pmu_lbr_reset_32(void)
159 for (i = 0; i < x86_pmu.lbr_nr; i++)
160 wrmsrl(x86_pmu.lbr_from + i, 0);
163 static void intel_pmu_lbr_reset_64(void)
167 for (i = 0; i < x86_pmu.lbr_nr; i++) {
168 wrmsrl(x86_pmu.lbr_from + i, 0);
169 wrmsrl(x86_pmu.lbr_to + i, 0);
173 void intel_pmu_lbr_reset(void)
178 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
179 intel_pmu_lbr_reset_32();
181 intel_pmu_lbr_reset_64();
184 void intel_pmu_lbr_enable(struct perf_event *event)
186 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
192 * Reset the LBR stack if we changed task context to
195 if (event->ctx->task && cpuc->lbr_context != event->ctx) {
196 intel_pmu_lbr_reset();
197 cpuc->lbr_context = event->ctx;
199 cpuc->br_sel = event->hw.branch_reg.reg;
204 void intel_pmu_lbr_disable(struct perf_event *event)
206 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
212 WARN_ON_ONCE(cpuc->lbr_users < 0);
214 if (cpuc->enabled && !cpuc->lbr_users) {
215 __intel_pmu_lbr_disable();
216 /* avoid stale pointer */
217 cpuc->lbr_context = NULL;
221 void intel_pmu_lbr_enable_all(void)
223 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
226 __intel_pmu_lbr_enable();
229 void intel_pmu_lbr_disable_all(void)
231 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
234 __intel_pmu_lbr_disable();
238 * TOS = most recently recorded branch
240 static inline u64 intel_pmu_lbr_tos(void)
244 rdmsrl(x86_pmu.lbr_tos, tos);
249 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
251 unsigned long mask = x86_pmu.lbr_nr - 1;
252 u64 tos = intel_pmu_lbr_tos();
255 for (i = 0; i < x86_pmu.lbr_nr; i++) {
256 unsigned long lbr_idx = (tos - i) & mask;
265 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
267 cpuc->lbr_entries[i].from = msr_lastbranch.from;
268 cpuc->lbr_entries[i].to = msr_lastbranch.to;
269 cpuc->lbr_entries[i].mispred = 0;
270 cpuc->lbr_entries[i].predicted = 0;
271 cpuc->lbr_entries[i].reserved = 0;
273 cpuc->lbr_stack.nr = i;
277 * Due to lack of segmentation in Linux the effective address (offset)
278 * is the same as the linear address, allowing us to merge the LIP and EIP
281 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
283 unsigned long mask = x86_pmu.lbr_nr - 1;
284 int lbr_format = x86_pmu.intel_cap.lbr_format;
285 u64 tos = intel_pmu_lbr_tos();
289 for (i = 0; i < x86_pmu.lbr_nr; i++) {
290 unsigned long lbr_idx = (tos - i) & mask;
291 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
293 int lbr_flags = lbr_desc[lbr_format];
295 rdmsrl(x86_pmu.lbr_from + lbr_idx, from);
296 rdmsrl(x86_pmu.lbr_to + lbr_idx, to);
298 if (lbr_flags & LBR_EIP_FLAGS) {
299 mis = !!(from & LBR_FROM_FLAG_MISPRED);
303 if (lbr_flags & LBR_TSX) {
304 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
305 abort = !!(from & LBR_FROM_FLAG_ABORT);
308 from = (u64)((((s64)from) << skip) >> skip);
311 * Some CPUs report duplicated abort records,
312 * with the second entry not having an abort bit set.
313 * Skip them here. This loop runs backwards,
314 * so we need to undo the previous record.
315 * If the abort just happened outside the window
316 * the extra entry cannot be removed.
318 if (abort && x86_pmu.lbr_double_abort && out > 0)
321 cpuc->lbr_entries[out].from = from;
322 cpuc->lbr_entries[out].to = to;
323 cpuc->lbr_entries[out].mispred = mis;
324 cpuc->lbr_entries[out].predicted = pred;
325 cpuc->lbr_entries[out].in_tx = in_tx;
326 cpuc->lbr_entries[out].abort = abort;
327 cpuc->lbr_entries[out].reserved = 0;
330 cpuc->lbr_stack.nr = out;
333 void intel_pmu_lbr_read(void)
335 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
337 if (!cpuc->lbr_users)
340 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
341 intel_pmu_lbr_read_32(cpuc);
343 intel_pmu_lbr_read_64(cpuc);
345 intel_pmu_lbr_filter(cpuc);
350 * - in case there is no HW filter
351 * - in case the HW filter has errata or limitations
353 static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
355 u64 br_type = event->attr.branch_sample_type;
358 if (br_type & PERF_SAMPLE_BRANCH_USER)
361 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
362 mask |= X86_BR_KERNEL;
364 /* we ignore BRANCH_HV here */
366 if (br_type & PERF_SAMPLE_BRANCH_ANY)
369 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
370 mask |= X86_BR_ANY_CALL;
372 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
373 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
375 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
376 mask |= X86_BR_IND_CALL;
378 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
379 mask |= X86_BR_ABORT;
381 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
382 mask |= X86_BR_IN_TX;
384 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
385 mask |= X86_BR_NO_TX;
387 if (br_type & PERF_SAMPLE_BRANCH_COND)
391 * stash actual user request into reg, it may
392 * be used by fixup code for some CPU
394 event->hw.branch_reg.reg = mask;
398 * setup the HW LBR filter
399 * Used only when available, may not be enough to disambiguate
400 * all branches, may need the help of the SW filter
402 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
404 struct hw_perf_event_extra *reg;
405 u64 br_type = event->attr.branch_sample_type;
409 for_each_branch_sample_type(m) {
413 v = x86_pmu.lbr_sel_map[m];
414 if (v == LBR_NOT_SUPP)
420 reg = &event->hw.branch_reg;
421 reg->idx = EXTRA_REG_LBR;
423 /* LBR_SELECT operates in suppress mode so invert mask */
424 reg->config = ~mask & x86_pmu.lbr_sel_mask;
429 int intel_pmu_setup_lbr_filter(struct perf_event *event)
440 * setup SW LBR filter
442 intel_pmu_setup_sw_lbr_filter(event);
445 * setup HW LBR filter, if any
447 if (x86_pmu.lbr_sel_map)
448 ret = intel_pmu_setup_hw_lbr_filter(event);
454 * return the type of control flow change at address "from"
455 * intruction is not necessarily a branch (in case of interrupt).
457 * The branch type returned also includes the priv level of the
458 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
460 * If a branch type is unknown OR the instruction cannot be
461 * decoded (e.g., text page not present), then X86_BR_NONE is
464 static int branch_type(unsigned long from, unsigned long to, int abort)
468 int bytes, size = MAX_INSN_SIZE;
469 int ret = X86_BR_NONE;
470 int ext, to_plm, from_plm;
471 u8 buf[MAX_INSN_SIZE];
474 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
475 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
478 * maybe zero if lbr did not fill up after a reset by the time
479 * we get a PMU interrupt
481 if (from == 0 || to == 0)
485 return X86_BR_ABORT | to_plm;
487 if (from_plm == X86_BR_USER) {
489 * can happen if measuring at the user level only
490 * and we interrupt in a kernel thread, e.g., idle.
495 /* may fail if text not present */
496 bytes = copy_from_user_nmi(buf, (void __user *)from, size);
503 * The LBR logs any address in the IP, even if the IP just
504 * faulted. This means userspace can control the from address.
505 * Ensure we don't blindy read any address by validating it is
506 * a known text address.
508 if (kernel_text_address(from))
515 * decoder needs to know the ABI especially
516 * on 64-bit systems running 32-bit apps
519 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
521 insn_init(&insn, addr, is64);
522 insn_get_opcode(&insn);
524 switch (insn.opcode.bytes[0]) {
526 switch (insn.opcode.bytes[1]) {
527 case 0x05: /* syscall */
528 case 0x34: /* sysenter */
529 ret = X86_BR_SYSCALL;
531 case 0x07: /* sysret */
532 case 0x35: /* sysexit */
535 case 0x80 ... 0x8f: /* conditional */
542 case 0x70 ... 0x7f: /* conditional */
545 case 0xc2: /* near ret */
546 case 0xc3: /* near ret */
547 case 0xca: /* far ret */
548 case 0xcb: /* far ret */
551 case 0xcf: /* iret */
554 case 0xcc ... 0xce: /* int */
557 case 0xe8: /* call near rel */
558 case 0x9a: /* call far absolute */
561 case 0xe0 ... 0xe3: /* loop jmp */
564 case 0xe9 ... 0xeb: /* jmp */
567 case 0xff: /* call near absolute, call far absolute ind */
568 insn_get_modrm(&insn);
569 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
571 case 2: /* near ind call */
572 case 3: /* far ind call */
573 ret = X86_BR_IND_CALL;
585 * interrupts, traps, faults (and thus ring transition) may
586 * occur on any instructions. Thus, to classify them correctly,
587 * we need to first look at the from and to priv levels. If they
588 * are different and to is in the kernel, then it indicates
589 * a ring transition. If the from instruction is not a ring
590 * transition instr (syscall, systenter, int), then it means
591 * it was a irq, trap or fault.
593 * we have no way of detecting kernel to kernel faults.
595 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
596 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
600 * branch priv level determined by target as
601 * is done by HW when LBR_SELECT is implemented
603 if (ret != X86_BR_NONE)
610 * implement actual branch filter based on user demand.
611 * Hardware may not exactly satisfy that request, thus
612 * we need to inspect opcodes. Mismatched branches are
613 * discarded. Therefore, the number of branches returned
614 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
617 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
620 int br_sel = cpuc->br_sel;
622 bool compress = false;
624 /* if sampling all branches, then nothing to filter */
625 if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
628 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
630 from = cpuc->lbr_entries[i].from;
631 to = cpuc->lbr_entries[i].to;
633 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
634 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
635 if (cpuc->lbr_entries[i].in_tx)
636 type |= X86_BR_IN_TX;
638 type |= X86_BR_NO_TX;
641 /* if type does not correspond, then discard */
642 if (type == X86_BR_NONE || (br_sel & type) != type) {
643 cpuc->lbr_entries[i].from = 0;
651 /* remove all entries with from=0 */
652 for (i = 0; i < cpuc->lbr_stack.nr; ) {
653 if (!cpuc->lbr_entries[i].from) {
655 while (++j < cpuc->lbr_stack.nr)
656 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
657 cpuc->lbr_stack.nr--;
658 if (!cpuc->lbr_entries[i].from)
666 * Map interface branch filters onto LBR filters
668 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
669 [PERF_SAMPLE_BRANCH_ANY] = LBR_ANY,
670 [PERF_SAMPLE_BRANCH_USER] = LBR_USER,
671 [PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL,
672 [PERF_SAMPLE_BRANCH_HV] = LBR_IGN,
673 [PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_REL_JMP
674 | LBR_IND_JMP | LBR_FAR,
676 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
678 [PERF_SAMPLE_BRANCH_ANY_CALL] =
679 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
681 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
683 [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP,
684 [PERF_SAMPLE_BRANCH_COND] = LBR_JCC,
687 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
688 [PERF_SAMPLE_BRANCH_ANY] = LBR_ANY,
689 [PERF_SAMPLE_BRANCH_USER] = LBR_USER,
690 [PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL,
691 [PERF_SAMPLE_BRANCH_HV] = LBR_IGN,
692 [PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_FAR,
693 [PERF_SAMPLE_BRANCH_ANY_CALL] = LBR_REL_CALL | LBR_IND_CALL
695 [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL,
696 [PERF_SAMPLE_BRANCH_COND] = LBR_JCC,
700 void __init intel_pmu_lbr_init_core(void)
703 x86_pmu.lbr_tos = MSR_LBR_TOS;
704 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
705 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
708 * SW branch filter usage:
709 * - compensate for lack of HW filter
711 pr_cont("4-deep LBR, ");
714 /* nehalem/westmere */
715 void __init intel_pmu_lbr_init_nhm(void)
718 x86_pmu.lbr_tos = MSR_LBR_TOS;
719 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
720 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
722 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
723 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
726 * SW branch filter usage:
727 * - workaround LBR_SEL errata (see above)
728 * - support syscall, sysret capture.
729 * That requires LBR_FAR but that means far
730 * jmp need to be filtered out
732 pr_cont("16-deep LBR, ");
736 void __init intel_pmu_lbr_init_snb(void)
739 x86_pmu.lbr_tos = MSR_LBR_TOS;
740 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
741 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
743 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
744 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
747 * SW branch filter usage:
748 * - support syscall, sysret capture.
749 * That requires LBR_FAR but that means far
750 * jmp need to be filtered out
752 pr_cont("16-deep LBR, ");
756 void __init intel_pmu_lbr_init_atom(void)
759 * only models starting at stepping 10 seems
760 * to have an operational LBR which can freeze
763 if (boot_cpu_data.x86_model == 28
764 && boot_cpu_data.x86_mask < 10) {
765 pr_cont("LBR disabled due to erratum");
770 x86_pmu.lbr_tos = MSR_LBR_TOS;
771 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
772 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
775 * SW branch filter usage:
776 * - compensate for lack of HW filter
778 pr_cont("8-deep LBR, ");