1 #include "perf_event_intel_uncore.h"
3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
4 static struct intel_uncore_type **msr_uncores = empty_uncore;
5 static struct intel_uncore_type **pci_uncores = empty_uncore;
6 /* pci bus to socket mapping */
7 static int pcibus_to_physid[256] = { [0 ... 255] = -1, };
9 static struct pci_dev *extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
11 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
13 /* mask of cpus that collect uncore events */
14 static cpumask_t uncore_cpu_mask;
16 /* constraint for the fixed counter */
17 static struct event_constraint constraint_fixed =
18 EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
19 static struct event_constraint constraint_empty =
20 EVENT_CONSTRAINT(0, 0, 0);
22 #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
25 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
26 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
27 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
28 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
29 DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
30 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
31 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
32 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
33 DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
34 DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
35 DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
36 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
37 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
38 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
39 DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
40 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
41 DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
42 DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
43 DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
44 DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
45 DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
46 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
47 DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
48 DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
49 DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
50 DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51");
51 DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35");
52 DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31");
53 DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17");
54 DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12");
55 DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8");
56 DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4");
57 DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31");
58 DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63");
59 DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51");
60 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35");
61 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31");
62 DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17");
63 DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12");
64 DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8");
65 DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4");
66 DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");
67 DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63");
69 static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
70 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
71 static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
72 static void uncore_pmu_event_read(struct perf_event *event);
74 static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
76 return container_of(event->pmu, struct intel_uncore_pmu, pmu);
79 static struct intel_uncore_box *
80 uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
82 struct intel_uncore_box *box;
84 box = *per_cpu_ptr(pmu->box, cpu);
88 raw_spin_lock(&uncore_box_lock);
89 list_for_each_entry(box, &pmu->box_list, list) {
90 if (box->phys_id == topology_physical_package_id(cpu)) {
91 atomic_inc(&box->refcnt);
92 *per_cpu_ptr(pmu->box, cpu) = box;
96 raw_spin_unlock(&uncore_box_lock);
98 return *per_cpu_ptr(pmu->box, cpu);
101 static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
104 * perf core schedules event on the basis of cpu, uncore events are
105 * collected by one of the cpus inside a physical package.
107 return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
110 static u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
114 rdmsrl(event->hw.event_base, count);
120 * generic get constraint function for shared match/mask registers.
122 static struct event_constraint *
123 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
125 struct intel_uncore_extra_reg *er;
126 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
127 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
132 * reg->alloc can be set due to existing state, so for fake box we
133 * need to ignore this, otherwise we might fail to allocate proper
134 * fake state for this extra reg constraint.
136 if (reg1->idx == EXTRA_REG_NONE ||
137 (!uncore_box_is_fake(box) && reg1->alloc))
140 er = &box->shared_regs[reg1->idx];
141 raw_spin_lock_irqsave(&er->lock, flags);
142 if (!atomic_read(&er->ref) ||
143 (er->config1 == reg1->config && er->config2 == reg2->config)) {
144 atomic_inc(&er->ref);
145 er->config1 = reg1->config;
146 er->config2 = reg2->config;
149 raw_spin_unlock_irqrestore(&er->lock, flags);
152 if (!uncore_box_is_fake(box))
157 return &constraint_empty;
160 static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
162 struct intel_uncore_extra_reg *er;
163 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
166 * Only put constraint if extra reg was actually allocated. Also
167 * takes care of event which do not use an extra shared reg.
169 * Also, if this is a fake box we shouldn't touch any event state
170 * (reg->alloc) and we don't care about leaving inconsistent box
171 * state either since it will be thrown out.
173 if (uncore_box_is_fake(box) || !reg1->alloc)
176 er = &box->shared_regs[reg1->idx];
177 atomic_dec(&er->ref);
181 static u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
183 struct intel_uncore_extra_reg *er;
187 er = &box->shared_regs[idx];
189 raw_spin_lock_irqsave(&er->lock, flags);
191 raw_spin_unlock_irqrestore(&er->lock, flags);
196 /* Sandy Bridge-EP uncore support */
197 static struct intel_uncore_type snbep_uncore_cbox;
198 static struct intel_uncore_type snbep_uncore_pcu;
200 static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
202 struct pci_dev *pdev = box->pci_dev;
203 int box_ctl = uncore_pci_box_ctl(box);
206 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
207 config |= SNBEP_PMON_BOX_CTL_FRZ;
208 pci_write_config_dword(pdev, box_ctl, config);
212 static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
214 struct pci_dev *pdev = box->pci_dev;
215 int box_ctl = uncore_pci_box_ctl(box);
218 if (!pci_read_config_dword(pdev, box_ctl, &config)) {
219 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
220 pci_write_config_dword(pdev, box_ctl, config);
224 static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
226 struct pci_dev *pdev = box->pci_dev;
227 struct hw_perf_event *hwc = &event->hw;
229 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
232 static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
234 struct pci_dev *pdev = box->pci_dev;
235 struct hw_perf_event *hwc = &event->hw;
237 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
240 static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
242 struct pci_dev *pdev = box->pci_dev;
243 struct hw_perf_event *hwc = &event->hw;
246 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
247 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
252 static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
254 struct pci_dev *pdev = box->pci_dev;
256 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
259 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
264 msr = uncore_msr_box_ctl(box);
267 config |= SNBEP_PMON_BOX_CTL_FRZ;
272 static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
277 msr = uncore_msr_box_ctl(box);
280 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
285 static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
287 struct hw_perf_event *hwc = &event->hw;
288 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
290 if (reg1->idx != EXTRA_REG_NONE)
291 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
293 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
296 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
297 struct perf_event *event)
299 struct hw_perf_event *hwc = &event->hw;
301 wrmsrl(hwc->config_base, hwc->config);
304 static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
306 unsigned msr = uncore_msr_box_ctl(box);
309 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
312 static struct attribute *snbep_uncore_formats_attr[] = {
313 &format_attr_event.attr,
314 &format_attr_umask.attr,
315 &format_attr_edge.attr,
316 &format_attr_inv.attr,
317 &format_attr_thresh8.attr,
321 static struct attribute *snbep_uncore_ubox_formats_attr[] = {
322 &format_attr_event.attr,
323 &format_attr_umask.attr,
324 &format_attr_edge.attr,
325 &format_attr_inv.attr,
326 &format_attr_thresh5.attr,
330 static struct attribute *snbep_uncore_cbox_formats_attr[] = {
331 &format_attr_event.attr,
332 &format_attr_umask.attr,
333 &format_attr_edge.attr,
334 &format_attr_tid_en.attr,
335 &format_attr_inv.attr,
336 &format_attr_thresh8.attr,
337 &format_attr_filter_tid.attr,
338 &format_attr_filter_nid.attr,
339 &format_attr_filter_state.attr,
340 &format_attr_filter_opc.attr,
344 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
345 &format_attr_event_ext.attr,
346 &format_attr_occ_sel.attr,
347 &format_attr_edge.attr,
348 &format_attr_inv.attr,
349 &format_attr_thresh5.attr,
350 &format_attr_occ_invert.attr,
351 &format_attr_occ_edge.attr,
352 &format_attr_filter_band0.attr,
353 &format_attr_filter_band1.attr,
354 &format_attr_filter_band2.attr,
355 &format_attr_filter_band3.attr,
359 static struct attribute *snbep_uncore_qpi_formats_attr[] = {
360 &format_attr_event_ext.attr,
361 &format_attr_umask.attr,
362 &format_attr_edge.attr,
363 &format_attr_inv.attr,
364 &format_attr_thresh8.attr,
365 &format_attr_match_rds.attr,
366 &format_attr_match_rnid30.attr,
367 &format_attr_match_rnid4.attr,
368 &format_attr_match_dnid.attr,
369 &format_attr_match_mc.attr,
370 &format_attr_match_opc.attr,
371 &format_attr_match_vnw.attr,
372 &format_attr_match0.attr,
373 &format_attr_match1.attr,
374 &format_attr_mask_rds.attr,
375 &format_attr_mask_rnid30.attr,
376 &format_attr_mask_rnid4.attr,
377 &format_attr_mask_dnid.attr,
378 &format_attr_mask_mc.attr,
379 &format_attr_mask_opc.attr,
380 &format_attr_mask_vnw.attr,
381 &format_attr_mask0.attr,
382 &format_attr_mask1.attr,
386 static struct uncore_event_desc snbep_uncore_imc_events[] = {
387 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
388 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
389 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
390 { /* end: all zeroes */ },
393 static struct uncore_event_desc snbep_uncore_qpi_events[] = {
394 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"),
395 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
396 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"),
397 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"),
398 { /* end: all zeroes */ },
401 static struct attribute_group snbep_uncore_format_group = {
403 .attrs = snbep_uncore_formats_attr,
406 static struct attribute_group snbep_uncore_ubox_format_group = {
408 .attrs = snbep_uncore_ubox_formats_attr,
411 static struct attribute_group snbep_uncore_cbox_format_group = {
413 .attrs = snbep_uncore_cbox_formats_attr,
416 static struct attribute_group snbep_uncore_pcu_format_group = {
418 .attrs = snbep_uncore_pcu_formats_attr,
421 static struct attribute_group snbep_uncore_qpi_format_group = {
423 .attrs = snbep_uncore_qpi_formats_attr,
426 #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
427 .init_box = snbep_uncore_msr_init_box, \
428 .disable_box = snbep_uncore_msr_disable_box, \
429 .enable_box = snbep_uncore_msr_enable_box, \
430 .disable_event = snbep_uncore_msr_disable_event, \
431 .enable_event = snbep_uncore_msr_enable_event, \
432 .read_counter = uncore_msr_read_counter
434 static struct intel_uncore_ops snbep_uncore_msr_ops = {
435 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
438 #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \
439 .init_box = snbep_uncore_pci_init_box, \
440 .disable_box = snbep_uncore_pci_disable_box, \
441 .enable_box = snbep_uncore_pci_enable_box, \
442 .disable_event = snbep_uncore_pci_disable_event, \
443 .read_counter = snbep_uncore_pci_read_counter
445 static struct intel_uncore_ops snbep_uncore_pci_ops = {
446 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
447 .enable_event = snbep_uncore_pci_enable_event, \
450 static struct event_constraint snbep_uncore_cbox_constraints[] = {
451 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
452 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
453 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
454 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
455 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
456 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
457 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
458 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
459 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
460 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
461 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
462 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
463 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
464 EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
465 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
466 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
467 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
468 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
469 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
470 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
471 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
472 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
473 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
474 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
475 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
476 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
480 static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
481 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
482 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
483 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
484 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
485 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
486 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
487 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
488 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
489 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
490 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
494 static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
495 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
496 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
497 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
498 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
499 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
500 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
501 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
502 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
503 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
504 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
505 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
506 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
507 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
508 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
509 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
510 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
511 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
512 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
513 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
514 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
515 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
516 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
517 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
518 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
519 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
520 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
521 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
522 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
526 static struct intel_uncore_type snbep_uncore_ubox = {
531 .fixed_ctr_bits = 48,
532 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
533 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
534 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
535 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
536 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
537 .ops = &snbep_uncore_msr_ops,
538 .format_group = &snbep_uncore_ubox_format_group,
541 static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
542 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
543 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
544 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
545 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
546 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
547 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
548 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
549 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
550 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
551 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
552 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
553 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa),
554 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa),
555 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
556 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
557 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
558 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
559 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
560 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
561 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa),
562 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa),
563 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
564 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
565 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
566 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
570 static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
572 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
573 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
576 if (uncore_box_is_fake(box))
579 for (i = 0; i < 5; i++) {
580 if (reg1->alloc & (0x1 << i))
581 atomic_sub(1 << (i * 6), &er->ref);
586 static struct event_constraint *
587 __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event,
588 u64 (*cbox_filter_mask)(int fields))
590 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
591 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
596 if (reg1->idx == EXTRA_REG_NONE)
599 raw_spin_lock_irqsave(&er->lock, flags);
600 for (i = 0; i < 5; i++) {
601 if (!(reg1->idx & (0x1 << i)))
603 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
606 mask = cbox_filter_mask(0x1 << i);
607 if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) ||
608 !((reg1->config ^ er->config) & mask)) {
609 atomic_add(1 << (i * 6), &er->ref);
611 er->config |= reg1->config & mask;
617 raw_spin_unlock_irqrestore(&er->lock, flags);
621 if (!uncore_box_is_fake(box))
622 reg1->alloc |= alloc;
626 for (; i >= 0; i--) {
627 if (alloc & (0x1 << i))
628 atomic_sub(1 << (i * 6), &er->ref);
630 return &constraint_empty;
633 static u64 snbep_cbox_filter_mask(int fields)
638 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID;
640 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID;
642 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
644 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
649 static struct event_constraint *
650 snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
652 return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask);
655 static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
657 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
658 struct extra_reg *er;
661 for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) {
662 if (er->event != (event->hw.config & er->config_mask))
668 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
669 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
670 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx);
676 static struct intel_uncore_ops snbep_uncore_cbox_ops = {
677 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
678 .hw_config = snbep_cbox_hw_config,
679 .get_constraint = snbep_cbox_get_constraint,
680 .put_constraint = snbep_cbox_put_constraint,
683 static struct intel_uncore_type snbep_uncore_cbox = {
688 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
689 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
690 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
691 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
692 .msr_offset = SNBEP_CBO_MSR_OFFSET,
693 .num_shared_regs = 1,
694 .constraints = snbep_uncore_cbox_constraints,
695 .ops = &snbep_uncore_cbox_ops,
696 .format_group = &snbep_uncore_cbox_format_group,
699 static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify)
701 struct hw_perf_event *hwc = &event->hw;
702 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
703 u64 config = reg1->config;
705 if (new_idx > reg1->idx)
706 config <<= 8 * (new_idx - reg1->idx);
708 config >>= 8 * (reg1->idx - new_idx);
711 hwc->config += new_idx - reg1->idx;
712 reg1->config = config;
718 static struct event_constraint *
719 snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
721 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
722 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
725 u64 mask, config1 = reg1->config;
728 if (reg1->idx == EXTRA_REG_NONE ||
729 (!uncore_box_is_fake(box) && reg1->alloc))
732 mask = 0xffULL << (idx * 8);
733 raw_spin_lock_irqsave(&er->lock, flags);
734 if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
735 !((config1 ^ er->config) & mask)) {
736 atomic_add(1 << (idx * 8), &er->ref);
738 er->config |= config1 & mask;
741 raw_spin_unlock_irqrestore(&er->lock, flags);
745 if (idx != reg1->idx) {
746 config1 = snbep_pcu_alter_er(event, idx, false);
749 return &constraint_empty;
752 if (!uncore_box_is_fake(box)) {
753 if (idx != reg1->idx)
754 snbep_pcu_alter_er(event, idx, true);
760 static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
762 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
763 struct intel_uncore_extra_reg *er = &box->shared_regs[0];
765 if (uncore_box_is_fake(box) || !reg1->alloc)
768 atomic_sub(1 << (reg1->idx * 8), &er->ref);
772 static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
774 struct hw_perf_event *hwc = &event->hw;
775 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
776 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
778 if (ev_sel >= 0xb && ev_sel <= 0xe) {
779 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
780 reg1->idx = ev_sel - 0xb;
781 reg1->config = event->attr.config1 & (0xff << reg1->idx);
786 static struct intel_uncore_ops snbep_uncore_pcu_ops = {
787 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
788 .hw_config = snbep_pcu_hw_config,
789 .get_constraint = snbep_pcu_get_constraint,
790 .put_constraint = snbep_pcu_put_constraint,
793 static struct intel_uncore_type snbep_uncore_pcu = {
798 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
799 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
800 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
801 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
802 .num_shared_regs = 1,
803 .ops = &snbep_uncore_pcu_ops,
804 .format_group = &snbep_uncore_pcu_format_group,
807 static struct intel_uncore_type *snbep_msr_uncores[] = {
815 SNBEP_PCI_QPI_PORT0_FILTER,
816 SNBEP_PCI_QPI_PORT1_FILTER,
819 static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event)
821 struct hw_perf_event *hwc = &event->hw;
822 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
823 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
825 if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) {
827 reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0;
828 reg1->config = event->attr.config1;
829 reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0;
830 reg2->config = event->attr.config2;
835 static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event)
837 struct pci_dev *pdev = box->pci_dev;
838 struct hw_perf_event *hwc = &event->hw;
839 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
840 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
842 if (reg1->idx != EXTRA_REG_NONE) {
843 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER;
844 struct pci_dev *filter_pdev = extra_pci_dev[box->phys_id][idx];
845 WARN_ON_ONCE(!filter_pdev);
847 pci_write_config_dword(filter_pdev, reg1->reg,
849 pci_write_config_dword(filter_pdev, reg1->reg + 4,
850 (u32)(reg1->config >> 32));
851 pci_write_config_dword(filter_pdev, reg2->reg,
853 pci_write_config_dword(filter_pdev, reg2->reg + 4,
854 (u32)(reg2->config >> 32));
858 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
861 static struct intel_uncore_ops snbep_uncore_qpi_ops = {
862 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
863 .enable_event = snbep_qpi_enable_event,
864 .hw_config = snbep_qpi_hw_config,
865 .get_constraint = uncore_get_constraint,
866 .put_constraint = uncore_put_constraint,
869 #define SNBEP_UNCORE_PCI_COMMON_INIT() \
870 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
871 .event_ctl = SNBEP_PCI_PMON_CTL0, \
872 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
873 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
874 .ops = &snbep_uncore_pci_ops, \
875 .format_group = &snbep_uncore_format_group
877 static struct intel_uncore_type snbep_uncore_ha = {
882 SNBEP_UNCORE_PCI_COMMON_INIT(),
885 static struct intel_uncore_type snbep_uncore_imc = {
890 .fixed_ctr_bits = 48,
891 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
892 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
893 .event_descs = snbep_uncore_imc_events,
894 SNBEP_UNCORE_PCI_COMMON_INIT(),
897 static struct intel_uncore_type snbep_uncore_qpi = {
902 .perf_ctr = SNBEP_PCI_PMON_CTR0,
903 .event_ctl = SNBEP_PCI_PMON_CTL0,
904 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
905 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
906 .num_shared_regs = 1,
907 .ops = &snbep_uncore_qpi_ops,
908 .event_descs = snbep_uncore_qpi_events,
909 .format_group = &snbep_uncore_qpi_format_group,
913 static struct intel_uncore_type snbep_uncore_r2pcie = {
918 .constraints = snbep_uncore_r2pcie_constraints,
919 SNBEP_UNCORE_PCI_COMMON_INIT(),
922 static struct intel_uncore_type snbep_uncore_r3qpi = {
927 .constraints = snbep_uncore_r3qpi_constraints,
928 SNBEP_UNCORE_PCI_COMMON_INIT(),
933 SNBEP_PCI_UNCORE_IMC,
934 SNBEP_PCI_UNCORE_QPI,
935 SNBEP_PCI_UNCORE_R2PCIE,
936 SNBEP_PCI_UNCORE_R3QPI,
939 static struct intel_uncore_type *snbep_pci_uncores[] = {
940 [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha,
941 [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc,
942 [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi,
943 [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie,
944 [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi,
948 static const struct pci_device_id snbep_uncore_pci_ids[] = {
950 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
951 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0),
954 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
955 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0),
958 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
959 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1),
962 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
963 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2),
966 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
967 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3),
970 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
971 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0),
974 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
975 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1),
978 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
979 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0),
982 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
983 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0),
986 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
987 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1),
989 { /* QPI Port 0 filter */
990 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86),
991 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
992 SNBEP_PCI_QPI_PORT0_FILTER),
994 { /* QPI Port 0 filter */
995 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96),
996 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
997 SNBEP_PCI_QPI_PORT1_FILTER),
999 { /* end: all zeroes */ }
1002 static struct pci_driver snbep_uncore_pci_driver = {
1003 .name = "snbep_uncore",
1004 .id_table = snbep_uncore_pci_ids,
1008 * build pci bus to socket mapping
1010 static int snbep_pci2phy_map_init(int devid)
1012 struct pci_dev *ubox_dev = NULL;
1018 /* find the UBOX device */
1019 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
1022 bus = ubox_dev->bus->number;
1023 /* get the Node ID of the local register */
1024 err = pci_read_config_dword(ubox_dev, 0x40, &config);
1028 /* get the Node ID mapping */
1029 err = pci_read_config_dword(ubox_dev, 0x54, &config);
1033 * every three bits in the Node ID mapping register maps
1034 * to a particular node.
1036 for (i = 0; i < 8; i++) {
1037 if (nodeid == ((config >> (3 * i)) & 0x7)) {
1038 pcibus_to_physid[bus] = i;
1046 * For PCI bus with no UBOX device, find the next bus
1047 * that has UBOX device and use its mapping.
1050 for (bus = 255; bus >= 0; bus--) {
1051 if (pcibus_to_physid[bus] >= 0)
1052 i = pcibus_to_physid[bus];
1054 pcibus_to_physid[bus] = i;
1059 pci_dev_put(ubox_dev);
1061 return err ? pcibios_err_to_errno(err) : 0;
1063 /* end of Sandy Bridge-EP uncore support */
1065 /* IvyTown uncore support */
1066 static void ivt_uncore_msr_init_box(struct intel_uncore_box *box)
1068 unsigned msr = uncore_msr_box_ctl(box);
1070 wrmsrl(msr, IVT_PMON_BOX_CTL_INT);
1073 static void ivt_uncore_pci_init_box(struct intel_uncore_box *box)
1075 struct pci_dev *pdev = box->pci_dev;
1077 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVT_PMON_BOX_CTL_INT);
1080 #define IVT_UNCORE_MSR_OPS_COMMON_INIT() \
1081 .init_box = ivt_uncore_msr_init_box, \
1082 .disable_box = snbep_uncore_msr_disable_box, \
1083 .enable_box = snbep_uncore_msr_enable_box, \
1084 .disable_event = snbep_uncore_msr_disable_event, \
1085 .enable_event = snbep_uncore_msr_enable_event, \
1086 .read_counter = uncore_msr_read_counter
1088 static struct intel_uncore_ops ivt_uncore_msr_ops = {
1089 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1092 static struct intel_uncore_ops ivt_uncore_pci_ops = {
1093 .init_box = ivt_uncore_pci_init_box,
1094 .disable_box = snbep_uncore_pci_disable_box,
1095 .enable_box = snbep_uncore_pci_enable_box,
1096 .disable_event = snbep_uncore_pci_disable_event,
1097 .enable_event = snbep_uncore_pci_enable_event,
1098 .read_counter = snbep_uncore_pci_read_counter,
1101 #define IVT_UNCORE_PCI_COMMON_INIT() \
1102 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1103 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1104 .event_mask = IVT_PMON_RAW_EVENT_MASK, \
1105 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1106 .ops = &ivt_uncore_pci_ops, \
1107 .format_group = &ivt_uncore_format_group
1109 static struct attribute *ivt_uncore_formats_attr[] = {
1110 &format_attr_event.attr,
1111 &format_attr_umask.attr,
1112 &format_attr_edge.attr,
1113 &format_attr_inv.attr,
1114 &format_attr_thresh8.attr,
1118 static struct attribute *ivt_uncore_ubox_formats_attr[] = {
1119 &format_attr_event.attr,
1120 &format_attr_umask.attr,
1121 &format_attr_edge.attr,
1122 &format_attr_inv.attr,
1123 &format_attr_thresh5.attr,
1127 static struct attribute *ivt_uncore_cbox_formats_attr[] = {
1128 &format_attr_event.attr,
1129 &format_attr_umask.attr,
1130 &format_attr_edge.attr,
1131 &format_attr_tid_en.attr,
1132 &format_attr_thresh8.attr,
1133 &format_attr_filter_tid.attr,
1134 &format_attr_filter_link.attr,
1135 &format_attr_filter_state2.attr,
1136 &format_attr_filter_nid2.attr,
1137 &format_attr_filter_opc2.attr,
1141 static struct attribute *ivt_uncore_pcu_formats_attr[] = {
1142 &format_attr_event_ext.attr,
1143 &format_attr_occ_sel.attr,
1144 &format_attr_edge.attr,
1145 &format_attr_thresh5.attr,
1146 &format_attr_occ_invert.attr,
1147 &format_attr_occ_edge.attr,
1148 &format_attr_filter_band0.attr,
1149 &format_attr_filter_band1.attr,
1150 &format_attr_filter_band2.attr,
1151 &format_attr_filter_band3.attr,
1155 static struct attribute *ivt_uncore_qpi_formats_attr[] = {
1156 &format_attr_event_ext.attr,
1157 &format_attr_umask.attr,
1158 &format_attr_edge.attr,
1159 &format_attr_thresh8.attr,
1160 &format_attr_match_rds.attr,
1161 &format_attr_match_rnid30.attr,
1162 &format_attr_match_rnid4.attr,
1163 &format_attr_match_dnid.attr,
1164 &format_attr_match_mc.attr,
1165 &format_attr_match_opc.attr,
1166 &format_attr_match_vnw.attr,
1167 &format_attr_match0.attr,
1168 &format_attr_match1.attr,
1169 &format_attr_mask_rds.attr,
1170 &format_attr_mask_rnid30.attr,
1171 &format_attr_mask_rnid4.attr,
1172 &format_attr_mask_dnid.attr,
1173 &format_attr_mask_mc.attr,
1174 &format_attr_mask_opc.attr,
1175 &format_attr_mask_vnw.attr,
1176 &format_attr_mask0.attr,
1177 &format_attr_mask1.attr,
1181 static struct attribute_group ivt_uncore_format_group = {
1183 .attrs = ivt_uncore_formats_attr,
1186 static struct attribute_group ivt_uncore_ubox_format_group = {
1188 .attrs = ivt_uncore_ubox_formats_attr,
1191 static struct attribute_group ivt_uncore_cbox_format_group = {
1193 .attrs = ivt_uncore_cbox_formats_attr,
1196 static struct attribute_group ivt_uncore_pcu_format_group = {
1198 .attrs = ivt_uncore_pcu_formats_attr,
1201 static struct attribute_group ivt_uncore_qpi_format_group = {
1203 .attrs = ivt_uncore_qpi_formats_attr,
1206 static struct intel_uncore_type ivt_uncore_ubox = {
1210 .perf_ctr_bits = 44,
1211 .fixed_ctr_bits = 48,
1212 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
1213 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
1214 .event_mask = IVT_U_MSR_PMON_RAW_EVENT_MASK,
1215 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
1216 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
1217 .ops = &ivt_uncore_msr_ops,
1218 .format_group = &ivt_uncore_ubox_format_group,
1221 static struct extra_reg ivt_uncore_cbox_extra_regs[] = {
1222 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1223 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1224 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1226 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
1227 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1228 SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
1229 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1230 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
1231 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1232 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
1233 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1234 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
1235 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1236 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1237 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1238 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1239 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1240 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1241 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1242 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1243 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1244 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1245 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1246 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1247 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1248 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1249 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
1250 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1251 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1252 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1253 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1254 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1255 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1256 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1257 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1258 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1259 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1263 static u64 ivt_cbox_filter_mask(int fields)
1268 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_TID;
1270 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_LINK;
1272 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_STATE;
1274 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_NID;
1276 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_OPC;
1281 static struct event_constraint *
1282 ivt_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1284 return __snbep_cbox_get_constraint(box, event, ivt_cbox_filter_mask);
1287 static int ivt_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1289 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1290 struct extra_reg *er;
1293 for (er = ivt_uncore_cbox_extra_regs; er->msr; er++) {
1294 if (er->event != (event->hw.config & er->config_mask))
1300 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
1301 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1302 reg1->config = event->attr.config1 & ivt_cbox_filter_mask(idx);
1308 static void ivt_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1310 struct hw_perf_event *hwc = &event->hw;
1311 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1313 if (reg1->idx != EXTRA_REG_NONE) {
1314 u64 filter = uncore_shared_reg_config(box, 0);
1315 wrmsrl(reg1->reg, filter & 0xffffffff);
1316 wrmsrl(reg1->reg + 6, filter >> 32);
1319 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1322 static struct intel_uncore_ops ivt_uncore_cbox_ops = {
1323 .init_box = ivt_uncore_msr_init_box,
1324 .disable_box = snbep_uncore_msr_disable_box,
1325 .enable_box = snbep_uncore_msr_enable_box,
1326 .disable_event = snbep_uncore_msr_disable_event,
1327 .enable_event = ivt_cbox_enable_event,
1328 .read_counter = uncore_msr_read_counter,
1329 .hw_config = ivt_cbox_hw_config,
1330 .get_constraint = ivt_cbox_get_constraint,
1331 .put_constraint = snbep_cbox_put_constraint,
1334 static struct intel_uncore_type ivt_uncore_cbox = {
1338 .perf_ctr_bits = 44,
1339 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
1340 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
1341 .event_mask = IVT_CBO_MSR_PMON_RAW_EVENT_MASK,
1342 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
1343 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1344 .num_shared_regs = 1,
1345 .constraints = snbep_uncore_cbox_constraints,
1346 .ops = &ivt_uncore_cbox_ops,
1347 .format_group = &ivt_uncore_cbox_format_group,
1350 static struct intel_uncore_ops ivt_uncore_pcu_ops = {
1351 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1352 .hw_config = snbep_pcu_hw_config,
1353 .get_constraint = snbep_pcu_get_constraint,
1354 .put_constraint = snbep_pcu_put_constraint,
1357 static struct intel_uncore_type ivt_uncore_pcu = {
1361 .perf_ctr_bits = 48,
1362 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
1363 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
1364 .event_mask = IVT_PCU_MSR_PMON_RAW_EVENT_MASK,
1365 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
1366 .num_shared_regs = 1,
1367 .ops = &ivt_uncore_pcu_ops,
1368 .format_group = &ivt_uncore_pcu_format_group,
1371 static struct intel_uncore_type *ivt_msr_uncores[] = {
1378 static struct intel_uncore_type ivt_uncore_ha = {
1382 .perf_ctr_bits = 48,
1383 IVT_UNCORE_PCI_COMMON_INIT(),
1386 static struct intel_uncore_type ivt_uncore_imc = {
1390 .perf_ctr_bits = 48,
1391 .fixed_ctr_bits = 48,
1392 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1393 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1394 IVT_UNCORE_PCI_COMMON_INIT(),
1397 /* registers in IRP boxes are not properly aligned */
1398 static unsigned ivt_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4};
1399 static unsigned ivt_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0};
1401 static void ivt_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1403 struct pci_dev *pdev = box->pci_dev;
1404 struct hw_perf_event *hwc = &event->hw;
1406 pci_write_config_dword(pdev, ivt_uncore_irp_ctls[hwc->idx],
1407 hwc->config | SNBEP_PMON_CTL_EN);
1410 static void ivt_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1412 struct pci_dev *pdev = box->pci_dev;
1413 struct hw_perf_event *hwc = &event->hw;
1415 pci_write_config_dword(pdev, ivt_uncore_irp_ctls[hwc->idx], hwc->config);
1418 static u64 ivt_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
1420 struct pci_dev *pdev = box->pci_dev;
1421 struct hw_perf_event *hwc = &event->hw;
1424 pci_read_config_dword(pdev, ivt_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
1425 pci_read_config_dword(pdev, ivt_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
1430 static struct intel_uncore_ops ivt_uncore_irp_ops = {
1431 .init_box = ivt_uncore_pci_init_box,
1432 .disable_box = snbep_uncore_pci_disable_box,
1433 .enable_box = snbep_uncore_pci_enable_box,
1434 .disable_event = ivt_uncore_irp_disable_event,
1435 .enable_event = ivt_uncore_irp_enable_event,
1436 .read_counter = ivt_uncore_irp_read_counter,
1439 static struct intel_uncore_type ivt_uncore_irp = {
1443 .perf_ctr_bits = 48,
1444 .event_mask = IVT_PMON_RAW_EVENT_MASK,
1445 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1446 .ops = &ivt_uncore_irp_ops,
1447 .format_group = &ivt_uncore_format_group,
1450 static struct intel_uncore_ops ivt_uncore_qpi_ops = {
1451 .init_box = ivt_uncore_pci_init_box,
1452 .disable_box = snbep_uncore_pci_disable_box,
1453 .enable_box = snbep_uncore_pci_enable_box,
1454 .disable_event = snbep_uncore_pci_disable_event,
1455 .enable_event = snbep_qpi_enable_event,
1456 .read_counter = snbep_uncore_pci_read_counter,
1457 .hw_config = snbep_qpi_hw_config,
1458 .get_constraint = uncore_get_constraint,
1459 .put_constraint = uncore_put_constraint,
1462 static struct intel_uncore_type ivt_uncore_qpi = {
1466 .perf_ctr_bits = 48,
1467 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1468 .event_ctl = SNBEP_PCI_PMON_CTL0,
1469 .event_mask = IVT_QPI_PCI_PMON_RAW_EVENT_MASK,
1470 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1471 .num_shared_regs = 1,
1472 .ops = &ivt_uncore_qpi_ops,
1473 .format_group = &ivt_uncore_qpi_format_group,
1476 static struct intel_uncore_type ivt_uncore_r2pcie = {
1480 .perf_ctr_bits = 44,
1481 .constraints = snbep_uncore_r2pcie_constraints,
1482 IVT_UNCORE_PCI_COMMON_INIT(),
1485 static struct intel_uncore_type ivt_uncore_r3qpi = {
1489 .perf_ctr_bits = 44,
1490 .constraints = snbep_uncore_r3qpi_constraints,
1491 IVT_UNCORE_PCI_COMMON_INIT(),
1499 IVT_PCI_UNCORE_R2PCIE,
1500 IVT_PCI_UNCORE_R3QPI,
1503 static struct intel_uncore_type *ivt_pci_uncores[] = {
1504 [IVT_PCI_UNCORE_HA] = &ivt_uncore_ha,
1505 [IVT_PCI_UNCORE_IMC] = &ivt_uncore_imc,
1506 [IVT_PCI_UNCORE_IRP] = &ivt_uncore_irp,
1507 [IVT_PCI_UNCORE_QPI] = &ivt_uncore_qpi,
1508 [IVT_PCI_UNCORE_R2PCIE] = &ivt_uncore_r2pcie,
1509 [IVT_PCI_UNCORE_R3QPI] = &ivt_uncore_r3qpi,
1513 static const struct pci_device_id ivt_uncore_pci_ids[] = {
1514 { /* Home Agent 0 */
1515 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
1516 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_HA, 0),
1518 { /* Home Agent 1 */
1519 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
1520 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_HA, 1),
1522 { /* MC0 Channel 0 */
1523 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
1524 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 0),
1526 { /* MC0 Channel 1 */
1527 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
1528 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 1),
1530 { /* MC0 Channel 3 */
1531 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
1532 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 2),
1534 { /* MC0 Channel 4 */
1535 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
1536 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 3),
1538 { /* MC1 Channel 0 */
1539 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
1540 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 4),
1542 { /* MC1 Channel 1 */
1543 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
1544 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 5),
1546 { /* MC1 Channel 3 */
1547 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
1548 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 6),
1550 { /* MC1 Channel 4 */
1551 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
1552 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 7),
1555 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39),
1556 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IRP, 0),
1559 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
1560 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 0),
1563 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
1564 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 1),
1567 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
1568 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 2),
1571 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
1572 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R2PCIE, 0),
1574 { /* R3QPI0 Link 0 */
1575 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
1576 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 0),
1578 { /* R3QPI0 Link 1 */
1579 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
1580 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 1),
1582 { /* R3QPI1 Link 2 */
1583 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
1584 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 2),
1586 { /* QPI Port 0 filter */
1587 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86),
1588 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1589 SNBEP_PCI_QPI_PORT0_FILTER),
1591 { /* QPI Port 0 filter */
1592 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96),
1593 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
1594 SNBEP_PCI_QPI_PORT1_FILTER),
1596 { /* end: all zeroes */ }
1599 static struct pci_driver ivt_uncore_pci_driver = {
1600 .name = "ivt_uncore",
1601 .id_table = ivt_uncore_pci_ids,
1603 /* end of IvyTown uncore support */
1605 /* Sandy Bridge uncore support */
1606 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1608 struct hw_perf_event *hwc = &event->hw;
1610 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
1611 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
1613 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
1616 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1618 wrmsrl(event->hw.config_base, 0);
1621 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
1623 if (box->pmu->pmu_idx == 0) {
1624 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
1625 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
1629 static struct uncore_event_desc snb_uncore_events[] = {
1630 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
1631 { /* end: all zeroes */ },
1634 static struct attribute *snb_uncore_formats_attr[] = {
1635 &format_attr_event.attr,
1636 &format_attr_umask.attr,
1637 &format_attr_edge.attr,
1638 &format_attr_inv.attr,
1639 &format_attr_cmask5.attr,
1643 static struct attribute_group snb_uncore_format_group = {
1645 .attrs = snb_uncore_formats_attr,
1648 static struct intel_uncore_ops snb_uncore_msr_ops = {
1649 .init_box = snb_uncore_msr_init_box,
1650 .disable_event = snb_uncore_msr_disable_event,
1651 .enable_event = snb_uncore_msr_enable_event,
1652 .read_counter = uncore_msr_read_counter,
1655 static struct event_constraint snb_uncore_cbox_constraints[] = {
1656 UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
1657 UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
1658 EVENT_CONSTRAINT_END
1661 static struct intel_uncore_type snb_uncore_cbox = {
1665 .perf_ctr_bits = 44,
1666 .fixed_ctr_bits = 48,
1667 .perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
1668 .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
1669 .fixed_ctr = SNB_UNC_FIXED_CTR,
1670 .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
1672 .event_mask = SNB_UNC_RAW_EVENT_MASK,
1673 .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
1674 .constraints = snb_uncore_cbox_constraints,
1675 .ops = &snb_uncore_msr_ops,
1676 .format_group = &snb_uncore_format_group,
1677 .event_descs = snb_uncore_events,
1680 static struct intel_uncore_type *snb_msr_uncores[] = {
1689 static struct uncore_event_desc snb_uncore_imc_events[] = {
1690 INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"),
1691 INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
1692 INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
1694 INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
1695 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
1696 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
1698 { /* end: all zeroes */ },
1701 #define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff
1702 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48
1704 /* page size multiple covering all config regs */
1705 #define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000
1707 #define SNB_UNCORE_PCI_IMC_DATA_READS 0x1
1708 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050
1709 #define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2
1710 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
1711 #define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
1713 static struct attribute *snb_uncore_imc_formats_attr[] = {
1714 &format_attr_event.attr,
1718 static struct attribute_group snb_uncore_imc_format_group = {
1720 .attrs = snb_uncore_imc_formats_attr,
1723 static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
1725 struct pci_dev *pdev = box->pci_dev;
1726 int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
1727 resource_size_t addr;
1730 pci_read_config_dword(pdev, where, &pci_dword);
1733 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1734 pci_read_config_dword(pdev, where + 4, &pci_dword);
1735 addr |= ((resource_size_t)pci_dword << 32);
1738 addr &= ~(PAGE_SIZE - 1);
1740 box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
1741 box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
1744 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
1747 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
1750 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1753 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
1756 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
1758 struct hw_perf_event *hwc = &event->hw;
1760 return (u64)*(unsigned int *)(box->io_addr + hwc->event_base);
1764 * custom event_init() function because we define our own fixed, free
1765 * running counters, so we do not want to conflict with generic uncore
1766 * logic. Also simplifies processing
1768 static int snb_uncore_imc_event_init(struct perf_event *event)
1770 struct intel_uncore_pmu *pmu;
1771 struct intel_uncore_box *box;
1772 struct hw_perf_event *hwc = &event->hw;
1773 u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
1776 if (event->attr.type != event->pmu->type)
1779 pmu = uncore_event_to_pmu(event);
1780 /* no device found for this pmu */
1781 if (pmu->func_id < 0)
1784 /* Sampling not supported yet */
1785 if (hwc->sample_period)
1788 /* unsupported modes and filters */
1789 if (event->attr.exclude_user ||
1790 event->attr.exclude_kernel ||
1791 event->attr.exclude_hv ||
1792 event->attr.exclude_idle ||
1793 event->attr.exclude_host ||
1794 event->attr.exclude_guest ||
1795 event->attr.sample_period) /* no sampling */
1799 * Place all uncore events for a particular physical package
1805 /* check only supported bits are set */
1806 if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
1809 box = uncore_pmu_to_box(pmu, event->cpu);
1810 if (!box || box->cpu < 0)
1813 event->cpu = box->cpu;
1816 event->hw.last_tag = ~0ULL;
1817 event->hw.extra_reg.idx = EXTRA_REG_NONE;
1818 event->hw.branch_reg.idx = EXTRA_REG_NONE;
1820 * check event is known (whitelist, determines counter)
1823 case SNB_UNCORE_PCI_IMC_DATA_READS:
1824 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
1825 idx = UNCORE_PMC_IDX_FIXED;
1827 case SNB_UNCORE_PCI_IMC_DATA_WRITES:
1828 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
1829 idx = UNCORE_PMC_IDX_FIXED + 1;
1835 /* must be done before validate_group */
1836 event->hw.event_base = base;
1837 event->hw.config = cfg;
1838 event->hw.idx = idx;
1840 /* no group validation needed, we have free running counters */
1845 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1850 static void snb_uncore_imc_event_start(struct perf_event *event, int flags)
1852 struct intel_uncore_box *box = uncore_event_to_box(event);
1855 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1858 event->hw.state = 0;
1861 list_add_tail(&event->active_entry, &box->active_list);
1863 count = snb_uncore_imc_read_counter(box, event);
1864 local64_set(&event->hw.prev_count, count);
1866 if (box->n_active == 1)
1867 uncore_pmu_start_hrtimer(box);
1870 static void snb_uncore_imc_event_stop(struct perf_event *event, int flags)
1872 struct intel_uncore_box *box = uncore_event_to_box(event);
1873 struct hw_perf_event *hwc = &event->hw;
1875 if (!(hwc->state & PERF_HES_STOPPED)) {
1878 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1879 hwc->state |= PERF_HES_STOPPED;
1881 list_del(&event->active_entry);
1883 if (box->n_active == 0)
1884 uncore_pmu_cancel_hrtimer(box);
1887 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1889 * Drain the remaining delta count out of a event
1890 * that we are disabling:
1892 uncore_perf_event_update(box, event);
1893 hwc->state |= PERF_HES_UPTODATE;
1897 static int snb_uncore_imc_event_add(struct perf_event *event, int flags)
1899 struct intel_uncore_box *box = uncore_event_to_box(event);
1900 struct hw_perf_event *hwc = &event->hw;
1905 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1906 if (!(flags & PERF_EF_START))
1907 hwc->state |= PERF_HES_ARCH;
1909 snb_uncore_imc_event_start(event, 0);
1916 static void snb_uncore_imc_event_del(struct perf_event *event, int flags)
1918 struct intel_uncore_box *box = uncore_event_to_box(event);
1921 snb_uncore_imc_event_stop(event, PERF_EF_UPDATE);
1923 for (i = 0; i < box->n_events; i++) {
1924 if (event == box->event_list[i]) {
1931 static int snb_pci2phy_map_init(int devid)
1933 struct pci_dev *dev = NULL;
1936 dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
1940 bus = dev->bus->number;
1942 pcibus_to_physid[bus] = 0;
1949 static struct pmu snb_uncore_imc_pmu = {
1950 .task_ctx_nr = perf_invalid_context,
1951 .event_init = snb_uncore_imc_event_init,
1952 .add = snb_uncore_imc_event_add,
1953 .del = snb_uncore_imc_event_del,
1954 .start = snb_uncore_imc_event_start,
1955 .stop = snb_uncore_imc_event_stop,
1956 .read = uncore_pmu_event_read,
1959 static struct intel_uncore_ops snb_uncore_imc_ops = {
1960 .init_box = snb_uncore_imc_init_box,
1961 .enable_box = snb_uncore_imc_enable_box,
1962 .disable_box = snb_uncore_imc_disable_box,
1963 .disable_event = snb_uncore_imc_disable_event,
1964 .enable_event = snb_uncore_imc_enable_event,
1965 .hw_config = snb_uncore_imc_hw_config,
1966 .read_counter = snb_uncore_imc_read_counter,
1969 static struct intel_uncore_type snb_uncore_imc = {
1973 .fixed_ctr_bits = 32,
1974 .fixed_ctr = SNB_UNCORE_PCI_IMC_CTR_BASE,
1975 .event_descs = snb_uncore_imc_events,
1976 .format_group = &snb_uncore_imc_format_group,
1977 .perf_ctr = SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
1978 .event_mask = SNB_UNCORE_PCI_IMC_EVENT_MASK,
1979 .ops = &snb_uncore_imc_ops,
1980 .pmu = &snb_uncore_imc_pmu,
1983 static struct intel_uncore_type *snb_pci_uncores[] = {
1984 [SNB_PCI_UNCORE_IMC] = &snb_uncore_imc,
1988 static const struct pci_device_id snb_uncore_pci_ids[] = {
1990 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
1991 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1993 { /* end: all zeroes */ },
1996 static const struct pci_device_id ivb_uncore_pci_ids[] = {
1998 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
1999 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
2001 { /* end: all zeroes */ },
2004 static const struct pci_device_id hsw_uncore_pci_ids[] = {
2006 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
2007 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
2009 { /* end: all zeroes */ },
2012 static struct pci_driver snb_uncore_pci_driver = {
2013 .name = "snb_uncore",
2014 .id_table = snb_uncore_pci_ids,
2017 static struct pci_driver ivb_uncore_pci_driver = {
2018 .name = "ivb_uncore",
2019 .id_table = ivb_uncore_pci_ids,
2022 static struct pci_driver hsw_uncore_pci_driver = {
2023 .name = "hsw_uncore",
2024 .id_table = hsw_uncore_pci_ids,
2027 /* end of Sandy Bridge uncore support */
2029 /* Nehalem uncore support */
2030 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
2032 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
2035 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
2037 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
2040 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2042 struct hw_perf_event *hwc = &event->hw;
2044 if (hwc->idx < UNCORE_PMC_IDX_FIXED)
2045 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
2047 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
2050 static struct attribute *nhm_uncore_formats_attr[] = {
2051 &format_attr_event.attr,
2052 &format_attr_umask.attr,
2053 &format_attr_edge.attr,
2054 &format_attr_inv.attr,
2055 &format_attr_cmask8.attr,
2059 static struct attribute_group nhm_uncore_format_group = {
2061 .attrs = nhm_uncore_formats_attr,
2064 static struct uncore_event_desc nhm_uncore_events[] = {
2065 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
2066 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"),
2067 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"),
2068 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"),
2069 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"),
2070 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"),
2071 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
2072 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"),
2073 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"),
2074 { /* end: all zeroes */ },
2077 static struct intel_uncore_ops nhm_uncore_msr_ops = {
2078 .disable_box = nhm_uncore_msr_disable_box,
2079 .enable_box = nhm_uncore_msr_enable_box,
2080 .disable_event = snb_uncore_msr_disable_event,
2081 .enable_event = nhm_uncore_msr_enable_event,
2082 .read_counter = uncore_msr_read_counter,
2085 static struct intel_uncore_type nhm_uncore = {
2089 .perf_ctr_bits = 48,
2090 .fixed_ctr_bits = 48,
2091 .event_ctl = NHM_UNC_PERFEVTSEL0,
2092 .perf_ctr = NHM_UNC_UNCORE_PMC0,
2093 .fixed_ctr = NHM_UNC_FIXED_CTR,
2094 .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL,
2095 .event_mask = NHM_UNC_RAW_EVENT_MASK,
2096 .event_descs = nhm_uncore_events,
2097 .ops = &nhm_uncore_msr_ops,
2098 .format_group = &nhm_uncore_format_group,
2101 static struct intel_uncore_type *nhm_msr_uncores[] = {
2105 /* end of Nehalem uncore support */
2107 /* Nehalem-EX uncore support */
2108 DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
2109 DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
2110 DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
2111 DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
2113 static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)
2115 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);
2118 static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
2120 unsigned msr = uncore_msr_box_ctl(box);
2124 rdmsrl(msr, config);
2125 config &= ~((1ULL << uncore_num_counters(box)) - 1);
2126 /* WBox has a fixed counter */
2127 if (uncore_msr_fixed_ctl(box))
2128 config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN;
2129 wrmsrl(msr, config);
2133 static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
2135 unsigned msr = uncore_msr_box_ctl(box);
2139 rdmsrl(msr, config);
2140 config |= (1ULL << uncore_num_counters(box)) - 1;
2141 /* WBox has a fixed counter */
2142 if (uncore_msr_fixed_ctl(box))
2143 config |= NHMEX_W_PMON_GLOBAL_FIXED_EN;
2144 wrmsrl(msr, config);
2148 static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
2150 wrmsrl(event->hw.config_base, 0);
2153 static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2155 struct hw_perf_event *hwc = &event->hw;
2157 if (hwc->idx >= UNCORE_PMC_IDX_FIXED)
2158 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
2159 else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)
2160 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
2162 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
2165 #define NHMEX_UNCORE_OPS_COMMON_INIT() \
2166 .init_box = nhmex_uncore_msr_init_box, \
2167 .disable_box = nhmex_uncore_msr_disable_box, \
2168 .enable_box = nhmex_uncore_msr_enable_box, \
2169 .disable_event = nhmex_uncore_msr_disable_event, \
2170 .read_counter = uncore_msr_read_counter
2172 static struct intel_uncore_ops nhmex_uncore_ops = {
2173 NHMEX_UNCORE_OPS_COMMON_INIT(),
2174 .enable_event = nhmex_uncore_msr_enable_event,
2177 static struct attribute *nhmex_uncore_ubox_formats_attr[] = {
2178 &format_attr_event.attr,
2179 &format_attr_edge.attr,
2183 static struct attribute_group nhmex_uncore_ubox_format_group = {
2185 .attrs = nhmex_uncore_ubox_formats_attr,
2188 static struct intel_uncore_type nhmex_uncore_ubox = {
2192 .perf_ctr_bits = 48,
2193 .event_ctl = NHMEX_U_MSR_PMON_EV_SEL,
2194 .perf_ctr = NHMEX_U_MSR_PMON_CTR,
2195 .event_mask = NHMEX_U_PMON_RAW_EVENT_MASK,
2196 .box_ctl = NHMEX_U_MSR_PMON_GLOBAL_CTL,
2197 .ops = &nhmex_uncore_ops,
2198 .format_group = &nhmex_uncore_ubox_format_group
2201 static struct attribute *nhmex_uncore_cbox_formats_attr[] = {
2202 &format_attr_event.attr,
2203 &format_attr_umask.attr,
2204 &format_attr_edge.attr,
2205 &format_attr_inv.attr,
2206 &format_attr_thresh8.attr,
2210 static struct attribute_group nhmex_uncore_cbox_format_group = {
2212 .attrs = nhmex_uncore_cbox_formats_attr,
2215 /* msr offset for each instance of cbox */
2216 static unsigned nhmex_cbox_msr_offsets[] = {
2217 0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
2220 static struct intel_uncore_type nhmex_uncore_cbox = {
2224 .perf_ctr_bits = 48,
2225 .event_ctl = NHMEX_C0_MSR_PMON_EV_SEL0,
2226 .perf_ctr = NHMEX_C0_MSR_PMON_CTR0,
2227 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
2228 .box_ctl = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
2229 .msr_offsets = nhmex_cbox_msr_offsets,
2231 .ops = &nhmex_uncore_ops,
2232 .format_group = &nhmex_uncore_cbox_format_group
2235 static struct uncore_event_desc nhmex_uncore_wbox_events[] = {
2236 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0"),
2237 { /* end: all zeroes */ },
2240 static struct intel_uncore_type nhmex_uncore_wbox = {
2244 .perf_ctr_bits = 48,
2245 .event_ctl = NHMEX_W_MSR_PMON_CNT0,
2246 .perf_ctr = NHMEX_W_MSR_PMON_EVT_SEL0,
2247 .fixed_ctr = NHMEX_W_MSR_PMON_FIXED_CTR,
2248 .fixed_ctl = NHMEX_W_MSR_PMON_FIXED_CTL,
2249 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
2250 .box_ctl = NHMEX_W_MSR_GLOBAL_CTL,
2252 .event_descs = nhmex_uncore_wbox_events,
2253 .ops = &nhmex_uncore_ops,
2254 .format_group = &nhmex_uncore_cbox_format_group
2257 static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2259 struct hw_perf_event *hwc = &event->hw;
2260 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2261 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2264 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >>
2265 NHMEX_B_PMON_CTR_SHIFT;
2266 ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >>
2267 NHMEX_B_PMON_CTL_EV_SEL_SHIFT;
2269 /* events that do not use the match/mask registers */
2270 if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) ||
2271 (ctr == 2 && ev_sel != 0x4) || ctr == 3)
2274 if (box->pmu->pmu_idx == 0)
2275 reg1->reg = NHMEX_B0_MSR_MATCH;
2277 reg1->reg = NHMEX_B1_MSR_MATCH;
2279 reg1->config = event->attr.config1;
2280 reg2->config = event->attr.config2;
2284 static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2286 struct hw_perf_event *hwc = &event->hw;
2287 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2288 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2290 if (reg1->idx != EXTRA_REG_NONE) {
2291 wrmsrl(reg1->reg, reg1->config);
2292 wrmsrl(reg1->reg + 1, reg2->config);
2294 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
2295 (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK));
2299 * The Bbox has 4 counters, but each counter monitors different events.
2300 * Use bits 6-7 in the event config to select counter.
2302 static struct event_constraint nhmex_uncore_bbox_constraints[] = {
2303 EVENT_CONSTRAINT(0 , 1, 0xc0),
2304 EVENT_CONSTRAINT(0x40, 2, 0xc0),
2305 EVENT_CONSTRAINT(0x80, 4, 0xc0),
2306 EVENT_CONSTRAINT(0xc0, 8, 0xc0),
2307 EVENT_CONSTRAINT_END,
2310 static struct attribute *nhmex_uncore_bbox_formats_attr[] = {
2311 &format_attr_event5.attr,
2312 &format_attr_counter.attr,
2313 &format_attr_match.attr,
2314 &format_attr_mask.attr,
2318 static struct attribute_group nhmex_uncore_bbox_format_group = {
2320 .attrs = nhmex_uncore_bbox_formats_attr,
2323 static struct intel_uncore_ops nhmex_uncore_bbox_ops = {
2324 NHMEX_UNCORE_OPS_COMMON_INIT(),
2325 .enable_event = nhmex_bbox_msr_enable_event,
2326 .hw_config = nhmex_bbox_hw_config,
2327 .get_constraint = uncore_get_constraint,
2328 .put_constraint = uncore_put_constraint,
2331 static struct intel_uncore_type nhmex_uncore_bbox = {
2335 .perf_ctr_bits = 48,
2336 .event_ctl = NHMEX_B0_MSR_PMON_CTL0,
2337 .perf_ctr = NHMEX_B0_MSR_PMON_CTR0,
2338 .event_mask = NHMEX_B_PMON_RAW_EVENT_MASK,
2339 .box_ctl = NHMEX_B0_MSR_PMON_GLOBAL_CTL,
2340 .msr_offset = NHMEX_B_MSR_OFFSET,
2342 .num_shared_regs = 1,
2343 .constraints = nhmex_uncore_bbox_constraints,
2344 .ops = &nhmex_uncore_bbox_ops,
2345 .format_group = &nhmex_uncore_bbox_format_group
2348 static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2350 struct hw_perf_event *hwc = &event->hw;
2351 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2352 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2354 /* only TO_R_PROG_EV event uses the match/mask register */
2355 if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=
2356 NHMEX_S_EVENT_TO_R_PROG_EV)
2359 if (box->pmu->pmu_idx == 0)
2360 reg1->reg = NHMEX_S0_MSR_MM_CFG;
2362 reg1->reg = NHMEX_S1_MSR_MM_CFG;
2364 reg1->config = event->attr.config1;
2365 reg2->config = event->attr.config2;
2369 static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2371 struct hw_perf_event *hwc = &event->hw;
2372 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2373 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2375 if (reg1->idx != EXTRA_REG_NONE) {
2376 wrmsrl(reg1->reg, 0);
2377 wrmsrl(reg1->reg + 1, reg1->config);
2378 wrmsrl(reg1->reg + 2, reg2->config);
2379 wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
2381 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
2384 static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
2385 &format_attr_event.attr,
2386 &format_attr_umask.attr,
2387 &format_attr_edge.attr,
2388 &format_attr_inv.attr,
2389 &format_attr_thresh8.attr,
2390 &format_attr_match.attr,
2391 &format_attr_mask.attr,
2395 static struct attribute_group nhmex_uncore_sbox_format_group = {
2397 .attrs = nhmex_uncore_sbox_formats_attr,
2400 static struct intel_uncore_ops nhmex_uncore_sbox_ops = {
2401 NHMEX_UNCORE_OPS_COMMON_INIT(),
2402 .enable_event = nhmex_sbox_msr_enable_event,
2403 .hw_config = nhmex_sbox_hw_config,
2404 .get_constraint = uncore_get_constraint,
2405 .put_constraint = uncore_put_constraint,
2408 static struct intel_uncore_type nhmex_uncore_sbox = {
2412 .perf_ctr_bits = 48,
2413 .event_ctl = NHMEX_S0_MSR_PMON_CTL0,
2414 .perf_ctr = NHMEX_S0_MSR_PMON_CTR0,
2415 .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
2416 .box_ctl = NHMEX_S0_MSR_PMON_GLOBAL_CTL,
2417 .msr_offset = NHMEX_S_MSR_OFFSET,
2419 .num_shared_regs = 1,
2420 .ops = &nhmex_uncore_sbox_ops,
2421 .format_group = &nhmex_uncore_sbox_format_group
2425 EXTRA_REG_NHMEX_M_FILTER,
2426 EXTRA_REG_NHMEX_M_DSP,
2427 EXTRA_REG_NHMEX_M_ISS,
2428 EXTRA_REG_NHMEX_M_MAP,
2429 EXTRA_REG_NHMEX_M_MSC_THR,
2430 EXTRA_REG_NHMEX_M_PGT,
2431 EXTRA_REG_NHMEX_M_PLD,
2432 EXTRA_REG_NHMEX_M_ZDP_CTL_FVC,
2435 static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
2436 MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
2437 MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
2438 MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
2439 MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
2440 /* event 0xa uses two extra registers */
2441 MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
2442 MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
2443 MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
2444 /* events 0xd ~ 0x10 use the same extra register */
2445 MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
2446 MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
2447 MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
2448 MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
2449 MBOX_INC_SEL_EXTAR_REG(0x16, PGT),
2450 MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP),
2451 MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS),
2452 MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT),
2453 MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP),
2457 /* Nehalem-EX or Westmere-EX ? */
2458 static bool uncore_nhmex;
2460 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
2462 struct intel_uncore_extra_reg *er;
2463 unsigned long flags;
2467 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
2468 er = &box->shared_regs[idx];
2469 raw_spin_lock_irqsave(&er->lock, flags);
2470 if (!atomic_read(&er->ref) || er->config == config) {
2471 atomic_inc(&er->ref);
2472 er->config = config;
2475 raw_spin_unlock_irqrestore(&er->lock, flags);
2480 * The ZDP_CTL_FVC MSR has 4 fields which are used to control
2481 * events 0xd ~ 0x10. Besides these 4 fields, there are additional
2482 * fields which are shared.
2484 idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2485 if (WARN_ON_ONCE(idx >= 4))
2488 /* mask of the shared fields */
2490 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
2492 mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK;
2493 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
2495 raw_spin_lock_irqsave(&er->lock, flags);
2496 /* add mask of the non-shared field if it's in use */
2497 if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
2499 mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2501 mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2504 if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
2505 atomic_add(1 << (idx * 8), &er->ref);
2507 mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
2508 NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2510 mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK |
2511 WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2512 er->config &= ~mask;
2513 er->config |= (config & mask);
2516 raw_spin_unlock_irqrestore(&er->lock, flags);
2521 static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
2523 struct intel_uncore_extra_reg *er;
2525 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
2526 er = &box->shared_regs[idx];
2527 atomic_dec(&er->ref);
2531 idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2532 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
2533 atomic_sub(1 << (idx * 8), &er->ref);
2536 static u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
2538 struct hw_perf_event *hwc = &event->hw;
2539 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2540 u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
2541 u64 config = reg1->config;
2543 /* get the non-shared control bits and shift them */
2544 idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2546 config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2548 config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
2549 if (new_idx > orig_idx) {
2550 idx = new_idx - orig_idx;
2553 idx = orig_idx - new_idx;
2557 /* add the shared control bits back */
2559 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
2561 config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
2562 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
2564 /* adjust the main event selector */
2565 if (new_idx > orig_idx)
2566 hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
2568 hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
2569 reg1->config = config;
2570 reg1->idx = ~0xff | new_idx;
2575 static struct event_constraint *
2576 nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2578 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2579 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2580 int i, idx[2], alloc = 0;
2581 u64 config1 = reg1->config;
2583 idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
2584 idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
2586 for (i = 0; i < 2; i++) {
2587 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
2593 if (!nhmex_mbox_get_shared_reg(box, idx[i],
2594 __BITS_VALUE(config1, i, 32)))
2596 alloc |= (0x1 << i);
2599 /* for the match/mask registers */
2600 if (reg2->idx != EXTRA_REG_NONE &&
2601 (uncore_box_is_fake(box) || !reg2->alloc) &&
2602 !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
2606 * If it's a fake box -- as per validate_{group,event}() we
2607 * shouldn't touch event state and we can avoid doing so
2608 * since both will only call get_event_constraints() once
2609 * on each event, this avoids the need for reg->alloc.
2611 if (!uncore_box_is_fake(box)) {
2612 if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
2613 nhmex_mbox_alter_er(event, idx[0], true);
2614 reg1->alloc |= alloc;
2615 if (reg2->idx != EXTRA_REG_NONE)
2620 if (idx[0] != 0xff && !(alloc & 0x1) &&
2621 idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
2623 * events 0xd ~ 0x10 are functional identical, but are
2624 * controlled by different fields in the ZDP_CTL_FVC
2625 * register. If we failed to take one field, try the
2628 BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
2629 idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2630 idx[0] = (idx[0] + 1) % 4;
2631 idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
2632 if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
2633 config1 = nhmex_mbox_alter_er(event, idx[0], false);
2639 nhmex_mbox_put_shared_reg(box, idx[0]);
2641 nhmex_mbox_put_shared_reg(box, idx[1]);
2642 return &constraint_empty;
2645 static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
2647 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2648 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2650 if (uncore_box_is_fake(box))
2653 if (reg1->alloc & 0x1)
2654 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
2655 if (reg1->alloc & 0x2)
2656 nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
2660 nhmex_mbox_put_shared_reg(box, reg2->idx);
2665 static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
2667 if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
2669 return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
2672 static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2674 struct intel_uncore_type *type = box->pmu->type;
2675 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2676 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
2677 struct extra_reg *er;
2681 * The mbox events may require 2 extra MSRs at the most. But only
2682 * the lower 32 bits in these MSRs are significant, so we can use
2683 * config1 to pass two MSRs' config.
2685 for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
2686 if (er->event != (event->hw.config & er->config_mask))
2688 if (event->attr.config1 & ~er->valid_mask)
2691 msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
2692 if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
2695 /* always use the 32~63 bits to pass the PLD config */
2696 if (er->idx == EXTRA_REG_NHMEX_M_PLD)
2698 else if (WARN_ON_ONCE(reg_idx > 0))
2701 reg1->idx &= ~(0xff << (reg_idx * 8));
2702 reg1->reg &= ~(0xffff << (reg_idx * 16));
2703 reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
2704 reg1->reg |= msr << (reg_idx * 16);
2705 reg1->config = event->attr.config1;
2709 * The mbox only provides ability to perform address matching
2710 * for the PLD events.
2713 reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
2714 if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
2715 reg2->config = event->attr.config2;
2717 reg2->config = ~0ULL;
2718 if (box->pmu->pmu_idx == 0)
2719 reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
2721 reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
2726 static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)
2728 struct intel_uncore_extra_reg *er;
2729 unsigned long flags;
2732 if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
2733 return box->shared_regs[idx].config;
2735 er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
2736 raw_spin_lock_irqsave(&er->lock, flags);
2737 config = er->config;
2738 raw_spin_unlock_irqrestore(&er->lock, flags);
2742 static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
2744 struct hw_perf_event *hwc = &event->hw;
2745 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2746 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2749 idx = __BITS_VALUE(reg1->idx, 0, 8);
2751 wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
2752 nhmex_mbox_shared_reg_config(box, idx));
2753 idx = __BITS_VALUE(reg1->idx, 1, 8);
2755 wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
2756 nhmex_mbox_shared_reg_config(box, idx));
2758 if (reg2->idx != EXTRA_REG_NONE) {
2759 wrmsrl(reg2->reg, 0);
2760 if (reg2->config != ~0ULL) {
2761 wrmsrl(reg2->reg + 1,
2762 reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
2763 wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
2764 (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
2765 wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
2769 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
2772 DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3");
2773 DEFINE_UNCORE_FORMAT_ATTR(storage_mode, storage_mode, "config:4-5");
2774 DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6");
2775 DEFINE_UNCORE_FORMAT_ATTR(flag_mode, flag_mode, "config:7");
2776 DEFINE_UNCORE_FORMAT_ATTR(inc_sel, inc_sel, "config:9-13");
2777 DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel, set_flag_sel, "config:19-21");
2778 DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en, filter_cfg_en, "config2:63");
2779 DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
2780 DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
2781 DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
2782 DEFINE_UNCORE_FORMAT_ATTR(thr, thr, "config1:0-31");
2783 DEFINE_UNCORE_FORMAT_ATTR(fvc, fvc, "config1:0-31");
2784 DEFINE_UNCORE_FORMAT_ATTR(pgt, pgt, "config1:0-31");
2785 DEFINE_UNCORE_FORMAT_ATTR(map, map, "config1:0-31");
2786 DEFINE_UNCORE_FORMAT_ATTR(iss, iss, "config1:0-31");
2787 DEFINE_UNCORE_FORMAT_ATTR(pld, pld, "config1:32-63");
2789 static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
2790 &format_attr_count_mode.attr,
2791 &format_attr_storage_mode.attr,
2792 &format_attr_wrap_mode.attr,
2793 &format_attr_flag_mode.attr,
2794 &format_attr_inc_sel.attr,
2795 &format_attr_set_flag_sel.attr,
2796 &format_attr_filter_cfg_en.attr,
2797 &format_attr_filter_match.attr,
2798 &format_attr_filter_mask.attr,
2799 &format_attr_dsp.attr,
2800 &format_attr_thr.attr,
2801 &format_attr_fvc.attr,
2802 &format_attr_pgt.attr,
2803 &format_attr_map.attr,
2804 &format_attr_iss.attr,
2805 &format_attr_pld.attr,
2809 static struct attribute_group nhmex_uncore_mbox_format_group = {
2811 .attrs = nhmex_uncore_mbox_formats_attr,
2814 static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
2815 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x2800"),
2816 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x2820"),
2817 { /* end: all zeroes */ },
2820 static struct uncore_event_desc wsmex_uncore_mbox_events[] = {
2821 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x5000"),
2822 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x5040"),
2823 { /* end: all zeroes */ },
2826 static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
2827 NHMEX_UNCORE_OPS_COMMON_INIT(),
2828 .enable_event = nhmex_mbox_msr_enable_event,
2829 .hw_config = nhmex_mbox_hw_config,
2830 .get_constraint = nhmex_mbox_get_constraint,
2831 .put_constraint = nhmex_mbox_put_constraint,
2834 static struct intel_uncore_type nhmex_uncore_mbox = {
2838 .perf_ctr_bits = 48,
2839 .event_ctl = NHMEX_M0_MSR_PMU_CTL0,
2840 .perf_ctr = NHMEX_M0_MSR_PMU_CNT0,
2841 .event_mask = NHMEX_M_PMON_RAW_EVENT_MASK,
2842 .box_ctl = NHMEX_M0_MSR_GLOBAL_CTL,
2843 .msr_offset = NHMEX_M_MSR_OFFSET,
2845 .num_shared_regs = 8,
2846 .event_descs = nhmex_uncore_mbox_events,
2847 .ops = &nhmex_uncore_mbox_ops,
2848 .format_group = &nhmex_uncore_mbox_format_group,
2851 static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
2853 struct hw_perf_event *hwc = &event->hw;
2854 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2856 /* adjust the main event selector and extra register index */
2857 if (reg1->idx % 2) {
2859 hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
2862 hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
2865 /* adjust extra register config */
2866 switch (reg1->idx % 6) {
2868 /* shift the 8~15 bits to the 0~7 bits */
2872 /* shift the 0~7 bits to the 8~15 bits */
2879 * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
2880 * An event set consists of 6 events, the 3rd and 4th events in
2881 * an event set use the same extra register. So an event set uses
2882 * 5 extra registers.
2884 static struct event_constraint *
2885 nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
2887 struct hw_perf_event *hwc = &event->hw;
2888 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
2889 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
2890 struct intel_uncore_extra_reg *er;
2891 unsigned long flags;
2896 if (!uncore_box_is_fake(box) && reg1->alloc)
2899 idx = reg1->idx % 6;
2900 config1 = reg1->config;
2903 /* the 3rd and 4th events use the same extra register */
2906 er_idx += (reg1->idx / 6) * 5;
2908 er = &box->shared_regs[er_idx];
2909 raw_spin_lock_irqsave(&er->lock, flags);
2911 if (!atomic_read(&er->ref) || er->config == reg1->config) {
2912 atomic_inc(&er->ref);
2913 er->config = reg1->config;
2916 } else if (idx == 2 || idx == 3) {
2918 * these two events use different fields in a extra register,
2919 * the 0~7 bits and the 8~15 bits respectively.
2921 u64 mask = 0xff << ((idx - 2) * 8);
2922 if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
2923 !((er->config ^ config1) & mask)) {
2924 atomic_add(1 << ((idx - 2) * 8), &er->ref);
2925 er->config &= ~mask;
2926 er->config |= config1 & mask;
2930 if (!atomic_read(&er->ref) ||
2931 (er->config == (hwc->config >> 32) &&
2932 er->config1 == reg1->config &&
2933 er->config2 == reg2->config)) {
2934 atomic_inc(&er->ref);
2935 er->config = (hwc->config >> 32);
2936 er->config1 = reg1->config;
2937 er->config2 = reg2->config;
2941 raw_spin_unlock_irqrestore(&er->lock, flags);
2945 * The Rbox events are always in pairs. The paired
2946 * events are functional identical, but use different
2947 * extra registers. If we failed to take an extra
2948 * register, try the alternative.
2951 if (idx != reg1->idx % 6) {
2959 if (!uncore_box_is_fake(box)) {
2960 if (idx != reg1->idx % 6)
2961 nhmex_rbox_alter_er(box, event);
2966 return &constraint_empty;
2969 static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
2971 struct intel_uncore_extra_reg *er;
2972 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2975 if (uncore_box_is_fake(box) || !reg1->alloc)
2978 idx = reg1->idx % 6;
2982 er_idx += (reg1->idx / 6) * 5;
2984 er = &box->shared_regs[er_idx];
2985 if (idx == 2 || idx == 3)
2986 atomic_sub(1 << ((idx - 2) * 8), &er->ref);
2988 atomic_dec(&er->ref);
2993 static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
2995 struct hw_perf_event *hwc = &event->hw;
2996 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
2997 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
3000 idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
3001 NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
3006 reg1->config = event->attr.config1;
3011 hwc->config |= event->attr.config & (~0ULL << 32);
3012 reg2->config = event->attr.config2;
3018 static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
3020 struct hw_perf_event *hwc = &event->hw;
3021 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
3022 struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
3026 port = idx / 6 + box->pmu->pmu_idx * 4;
3030 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
3033 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
3037 wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
3038 uncore_shared_reg_config(box, 2 + (idx / 6) * 5));
3041 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
3043 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
3044 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);
3047 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),
3049 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
3050 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
3054 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
3055 (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
3058 DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");
3059 DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");
3060 DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
3061 DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
3062 DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
3064 static struct attribute *nhmex_uncore_rbox_formats_attr[] = {
3065 &format_attr_event5.attr,
3066 &format_attr_xbr_mm_cfg.attr,
3067 &format_attr_xbr_match.attr,
3068 &format_attr_xbr_mask.attr,
3069 &format_attr_qlx_cfg.attr,
3070 &format_attr_iperf_cfg.attr,
3074 static struct attribute_group nhmex_uncore_rbox_format_group = {
3076 .attrs = nhmex_uncore_rbox_formats_attr,
3079 static struct uncore_event_desc nhmex_uncore_rbox_events[] = {
3080 INTEL_UNCORE_EVENT_DESC(qpi0_flit_send, "event=0x0,iperf_cfg=0x80000000"),
3081 INTEL_UNCORE_EVENT_DESC(qpi1_filt_send, "event=0x6,iperf_cfg=0x80000000"),
3082 INTEL_UNCORE_EVENT_DESC(qpi0_idle_filt, "event=0x0,iperf_cfg=0x40000000"),
3083 INTEL_UNCORE_EVENT_DESC(qpi1_idle_filt, "event=0x6,iperf_cfg=0x40000000"),
3084 INTEL_UNCORE_EVENT_DESC(qpi0_date_response, "event=0x0,iperf_cfg=0xc4"),
3085 INTEL_UNCORE_EVENT_DESC(qpi1_date_response, "event=0x6,iperf_cfg=0xc4"),
3086 { /* end: all zeroes */ },
3089 static struct intel_uncore_ops nhmex_uncore_rbox_ops = {
3090 NHMEX_UNCORE_OPS_COMMON_INIT(),
3091 .enable_event = nhmex_rbox_msr_enable_event,
3092 .hw_config = nhmex_rbox_hw_config,
3093 .get_constraint = nhmex_rbox_get_constraint,
3094 .put_constraint = nhmex_rbox_put_constraint,
3097 static struct intel_uncore_type nhmex_uncore_rbox = {
3101 .perf_ctr_bits = 48,
3102 .event_ctl = NHMEX_R_MSR_PMON_CTL0,
3103 .perf_ctr = NHMEX_R_MSR_PMON_CNT0,
3104 .event_mask = NHMEX_R_PMON_RAW_EVENT_MASK,
3105 .box_ctl = NHMEX_R_MSR_GLOBAL_CTL,
3106 .msr_offset = NHMEX_R_MSR_OFFSET,
3108 .num_shared_regs = 20,
3109 .event_descs = nhmex_uncore_rbox_events,
3110 .ops = &nhmex_uncore_rbox_ops,
3111 .format_group = &nhmex_uncore_rbox_format_group
3114 static struct intel_uncore_type *nhmex_msr_uncores[] = {
3124 /* end of Nehalem-EX uncore support */
3126 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
3128 struct hw_perf_event *hwc = &event->hw;
3131 hwc->last_tag = ++box->tags[idx];
3133 if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
3134 hwc->event_base = uncore_fixed_ctr(box);
3135 hwc->config_base = uncore_fixed_ctl(box);
3139 hwc->config_base = uncore_event_ctl(box, hwc->idx);
3140 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
3143 static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
3145 u64 prev_count, new_count, delta;
3148 if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
3149 shift = 64 - uncore_fixed_ctr_bits(box);
3151 shift = 64 - uncore_perf_ctr_bits(box);
3153 /* the hrtimer might modify the previous event value */
3155 prev_count = local64_read(&event->hw.prev_count);
3156 new_count = uncore_read_counter(box, event);
3157 if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
3160 delta = (new_count << shift) - (prev_count << shift);
3163 local64_add(delta, &event->count);
3167 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
3168 * for SandyBridge. So we use hrtimer to periodically poll the counter
3169 * to avoid overflow.
3171 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
3173 struct intel_uncore_box *box;
3174 struct perf_event *event;
3175 unsigned long flags;
3178 box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
3179 if (!box->n_active || box->cpu != smp_processor_id())
3180 return HRTIMER_NORESTART;
3182 * disable local interrupt to prevent uncore_pmu_event_start/stop
3183 * to interrupt the update process
3185 local_irq_save(flags);
3188 * handle boxes with an active event list as opposed to active
3191 list_for_each_entry(event, &box->active_list, active_entry) {
3192 uncore_perf_event_update(box, event);
3195 for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
3196 uncore_perf_event_update(box, box->events[bit]);
3198 local_irq_restore(flags);
3200 hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
3201 return HRTIMER_RESTART;
3204 static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
3206 __hrtimer_start_range_ns(&box->hrtimer,
3207 ns_to_ktime(box->hrtimer_duration), 0,
3208 HRTIMER_MODE_REL_PINNED, 0);
3211 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
3213 hrtimer_cancel(&box->hrtimer);
3216 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
3218 hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3219 box->hrtimer.function = uncore_pmu_hrtimer;
3222 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node)
3224 struct intel_uncore_box *box;
3227 size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
3229 box = kzalloc_node(size, GFP_KERNEL, node);
3233 for (i = 0; i < type->num_shared_regs; i++)
3234 raw_spin_lock_init(&box->shared_regs[i].lock);
3236 uncore_pmu_init_hrtimer(box);
3237 atomic_set(&box->refcnt, 1);
3241 /* set default hrtimer timeout */
3242 box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
3244 INIT_LIST_HEAD(&box->active_list);
3250 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
3252 struct perf_event *event;
3255 max_count = box->pmu->type->num_counters;
3256 if (box->pmu->type->fixed_ctl)
3259 if (box->n_events >= max_count)
3263 box->event_list[n] = leader;
3268 list_for_each_entry(event, &leader->sibling_list, group_entry) {
3269 if (event->state <= PERF_EVENT_STATE_OFF)
3275 box->event_list[n] = event;
3281 static struct event_constraint *
3282 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
3284 struct intel_uncore_type *type = box->pmu->type;
3285 struct event_constraint *c;
3287 if (type->ops->get_constraint) {
3288 c = type->ops->get_constraint(box, event);
3293 if (event->attr.config == UNCORE_FIXED_EVENT)
3294 return &constraint_fixed;
3296 if (type->constraints) {
3297 for_each_event_constraint(c, type->constraints) {
3298 if ((event->hw.config & c->cmask) == c->code)
3303 return &type->unconstrainted;
3306 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
3308 if (box->pmu->type->ops->put_constraint)
3309 box->pmu->type->ops->put_constraint(box, event);
3312 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
3314 unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
3315 struct event_constraint *c;
3316 int i, wmin, wmax, ret = 0;
3317 struct hw_perf_event *hwc;
3319 bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
3321 for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
3322 hwc = &box->event_list[i]->hw;
3323 c = uncore_get_event_constraint(box, box->event_list[i]);
3324 hwc->constraint = c;
3325 wmin = min(wmin, c->weight);
3326 wmax = max(wmax, c->weight);
3329 /* fastpath, try to reuse previous register */
3330 for (i = 0; i < n; i++) {
3331 hwc = &box->event_list[i]->hw;
3332 c = hwc->constraint;
3334 /* never assigned */
3338 /* constraint still honored */
3339 if (!test_bit(hwc->idx, c->idxmsk))
3342 /* not already used */
3343 if (test_bit(hwc->idx, used_mask))
3346 __set_bit(hwc->idx, used_mask);
3348 assign[i] = hwc->idx;
3352 ret = perf_assign_events(box->event_list, n,
3353 wmin, wmax, assign);
3355 if (!assign || ret) {
3356 for (i = 0; i < n; i++)
3357 uncore_put_event_constraint(box, box->event_list[i]);
3359 return ret ? -EINVAL : 0;
3362 static void uncore_pmu_event_start(struct perf_event *event, int flags)
3364 struct intel_uncore_box *box = uncore_event_to_box(event);
3365 int idx = event->hw.idx;
3367 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
3370 if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
3373 event->hw.state = 0;
3374 box->events[idx] = event;
3376 __set_bit(idx, box->active_mask);
3378 local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
3379 uncore_enable_event(box, event);
3381 if (box->n_active == 1) {
3382 uncore_enable_box(box);
3383 uncore_pmu_start_hrtimer(box);
3387 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
3389 struct intel_uncore_box *box = uncore_event_to_box(event);
3390 struct hw_perf_event *hwc = &event->hw;
3392 if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
3393 uncore_disable_event(box, event);
3395 box->events[hwc->idx] = NULL;
3396 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
3397 hwc->state |= PERF_HES_STOPPED;
3399 if (box->n_active == 0) {
3400 uncore_disable_box(box);
3401 uncore_pmu_cancel_hrtimer(box);
3405 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
3407 * Drain the remaining delta count out of a event
3408 * that we are disabling:
3410 uncore_perf_event_update(box, event);
3411 hwc->state |= PERF_HES_UPTODATE;
3415 static int uncore_pmu_event_add(struct perf_event *event, int flags)
3417 struct intel_uncore_box *box = uncore_event_to_box(event);
3418 struct hw_perf_event *hwc = &event->hw;
3419 int assign[UNCORE_PMC_IDX_MAX];
3425 ret = n = uncore_collect_events(box, event, false);
3429 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
3430 if (!(flags & PERF_EF_START))
3431 hwc->state |= PERF_HES_ARCH;
3433 ret = uncore_assign_events(box, assign, n);
3437 /* save events moving to new counters */
3438 for (i = 0; i < box->n_events; i++) {
3439 event = box->event_list[i];
3442 if (hwc->idx == assign[i] &&
3443 hwc->last_tag == box->tags[assign[i]])
3446 * Ensure we don't accidentally enable a stopped
3447 * counter simply because we rescheduled.
3449 if (hwc->state & PERF_HES_STOPPED)
3450 hwc->state |= PERF_HES_ARCH;
3452 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
3455 /* reprogram moved events into new counters */
3456 for (i = 0; i < n; i++) {
3457 event = box->event_list[i];
3460 if (hwc->idx != assign[i] ||
3461 hwc->last_tag != box->tags[assign[i]])
3462 uncore_assign_hw_event(box, event, assign[i]);
3463 else if (i < box->n_events)
3466 if (hwc->state & PERF_HES_ARCH)
3469 uncore_pmu_event_start(event, 0);
3476 static void uncore_pmu_event_del(struct perf_event *event, int flags)
3478 struct intel_uncore_box *box = uncore_event_to_box(event);
3481 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
3483 for (i = 0; i < box->n_events; i++) {
3484 if (event == box->event_list[i]) {
3485 uncore_put_event_constraint(box, event);
3487 while (++i < box->n_events)
3488 box->event_list[i - 1] = box->event_list[i];
3496 event->hw.last_tag = ~0ULL;
3499 static void uncore_pmu_event_read(struct perf_event *event)
3501 struct intel_uncore_box *box = uncore_event_to_box(event);
3502 uncore_perf_event_update(box, event);
3506 * validation ensures the group can be loaded onto the
3507 * PMU if it was the only group available.
3509 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
3510 struct perf_event *event)
3512 struct perf_event *leader = event->group_leader;
3513 struct intel_uncore_box *fake_box;
3514 int ret = -EINVAL, n;
3516 fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
3520 fake_box->pmu = pmu;
3522 * the event is not yet connected with its
3523 * siblings therefore we must first collect
3524 * existing siblings, then add the new event
3525 * before we can simulate the scheduling
3527 n = uncore_collect_events(fake_box, leader, true);
3531 fake_box->n_events = n;
3532 n = uncore_collect_events(fake_box, event, false);
3536 fake_box->n_events = n;
3538 ret = uncore_assign_events(fake_box, NULL, n);
3544 static int uncore_pmu_event_init(struct perf_event *event)
3546 struct intel_uncore_pmu *pmu;
3547 struct intel_uncore_box *box;
3548 struct hw_perf_event *hwc = &event->hw;
3551 if (event->attr.type != event->pmu->type)
3554 pmu = uncore_event_to_pmu(event);
3555 /* no device found for this pmu */
3556 if (pmu->func_id < 0)
3560 * Uncore PMU does measure at all privilege level all the time.
3561 * So it doesn't make sense to specify any exclude bits.
3563 if (event->attr.exclude_user || event->attr.exclude_kernel ||
3564 event->attr.exclude_hv || event->attr.exclude_idle)
3567 /* Sampling not supported yet */
3568 if (hwc->sample_period)
3572 * Place all uncore events for a particular physical package
3577 box = uncore_pmu_to_box(pmu, event->cpu);
3578 if (!box || box->cpu < 0)
3580 event->cpu = box->cpu;
3583 event->hw.last_tag = ~0ULL;
3584 event->hw.extra_reg.idx = EXTRA_REG_NONE;
3585 event->hw.branch_reg.idx = EXTRA_REG_NONE;
3587 if (event->attr.config == UNCORE_FIXED_EVENT) {
3588 /* no fixed counter */
3589 if (!pmu->type->fixed_ctl)
3592 * if there is only one fixed counter, only the first pmu
3593 * can access the fixed counter
3595 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
3598 /* fixed counters have event field hardcoded to zero */
3601 hwc->config = event->attr.config & pmu->type->event_mask;
3602 if (pmu->type->ops->hw_config) {
3603 ret = pmu->type->ops->hw_config(box, event);
3609 if (event->group_leader != event)
3610 ret = uncore_validate_group(pmu, event);
3617 static ssize_t uncore_get_attr_cpumask(struct device *dev,
3618 struct device_attribute *attr, char *buf)
3620 int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &uncore_cpu_mask);
3627 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
3629 static struct attribute *uncore_pmu_attrs[] = {
3630 &dev_attr_cpumask.attr,
3634 static struct attribute_group uncore_pmu_attr_group = {
3635 .attrs = uncore_pmu_attrs,
3638 static int __init uncore_pmu_register(struct intel_uncore_pmu *pmu)
3642 if (!pmu->type->pmu) {
3643 pmu->pmu = (struct pmu) {
3644 .attr_groups = pmu->type->attr_groups,
3645 .task_ctx_nr = perf_invalid_context,
3646 .event_init = uncore_pmu_event_init,
3647 .add = uncore_pmu_event_add,
3648 .del = uncore_pmu_event_del,
3649 .start = uncore_pmu_event_start,
3650 .stop = uncore_pmu_event_stop,
3651 .read = uncore_pmu_event_read,
3654 pmu->pmu = *pmu->type->pmu;
3655 pmu->pmu.attr_groups = pmu->type->attr_groups;
3658 if (pmu->type->num_boxes == 1) {
3659 if (strlen(pmu->type->name) > 0)
3660 sprintf(pmu->name, "uncore_%s", pmu->type->name);
3662 sprintf(pmu->name, "uncore");
3664 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
3668 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
3672 static void __init uncore_type_exit(struct intel_uncore_type *type)
3676 for (i = 0; i < type->num_boxes; i++)
3677 free_percpu(type->pmus[i].box);
3680 kfree(type->events_group);
3681 type->events_group = NULL;
3684 static void __init uncore_types_exit(struct intel_uncore_type **types)
3687 for (i = 0; types[i]; i++)
3688 uncore_type_exit(types[i]);
3691 static int __init uncore_type_init(struct intel_uncore_type *type)
3693 struct intel_uncore_pmu *pmus;
3694 struct attribute_group *attr_group;
3695 struct attribute **attrs;
3698 pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
3704 type->unconstrainted = (struct event_constraint)
3705 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
3706 0, type->num_counters, 0, 0);
3708 for (i = 0; i < type->num_boxes; i++) {
3709 pmus[i].func_id = -1;
3710 pmus[i].pmu_idx = i;
3711 pmus[i].type = type;
3712 INIT_LIST_HEAD(&pmus[i].box_list);
3713 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
3718 if (type->event_descs) {
3720 while (type->event_descs[i].attr.attr.name)
3723 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
3724 sizeof(*attr_group), GFP_KERNEL);
3728 attrs = (struct attribute **)(attr_group + 1);
3729 attr_group->name = "events";
3730 attr_group->attrs = attrs;
3732 for (j = 0; j < i; j++)
3733 attrs[j] = &type->event_descs[j].attr.attr;
3735 type->events_group = attr_group;
3738 type->pmu_group = &uncore_pmu_attr_group;
3741 uncore_type_exit(type);
3745 static int __init uncore_types_init(struct intel_uncore_type **types)
3749 for (i = 0; types[i]; i++) {
3750 ret = uncore_type_init(types[i]);
3757 uncore_type_exit(types[i]);
3761 static struct pci_driver *uncore_pci_driver;
3762 static bool pcidrv_registered;
3765 * add a pci uncore device
3767 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3769 struct intel_uncore_pmu *pmu;
3770 struct intel_uncore_box *box;
3771 struct intel_uncore_type *type;
3774 phys_id = pcibus_to_physid[pdev->bus->number];
3778 if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
3779 extra_pci_dev[phys_id][UNCORE_PCI_DEV_IDX(id->driver_data)] = pdev;
3780 pci_set_drvdata(pdev, NULL);
3784 type = pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
3785 box = uncore_alloc_box(type, NUMA_NO_NODE);
3790 * for performance monitoring unit with multiple boxes,
3791 * each box has a different function id.
3793 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
3794 if (pmu->func_id < 0)
3795 pmu->func_id = pdev->devfn;
3797 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
3799 box->phys_id = phys_id;
3800 box->pci_dev = pdev;
3802 uncore_box_init(box);
3803 pci_set_drvdata(pdev, box);
3805 raw_spin_lock(&uncore_box_lock);
3806 list_add_tail(&box->list, &pmu->box_list);
3807 raw_spin_unlock(&uncore_box_lock);
3812 static void uncore_pci_remove(struct pci_dev *pdev)
3814 struct intel_uncore_box *box = pci_get_drvdata(pdev);
3815 struct intel_uncore_pmu *pmu;
3816 int i, cpu, phys_id = pcibus_to_physid[pdev->bus->number];
3818 box = pci_get_drvdata(pdev);
3820 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
3821 if (extra_pci_dev[phys_id][i] == pdev) {
3822 extra_pci_dev[phys_id][i] = NULL;
3826 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
3831 if (WARN_ON_ONCE(phys_id != box->phys_id))
3834 pci_set_drvdata(pdev, NULL);
3836 raw_spin_lock(&uncore_box_lock);
3837 list_del(&box->list);
3838 raw_spin_unlock(&uncore_box_lock);
3840 for_each_possible_cpu(cpu) {
3841 if (*per_cpu_ptr(pmu->box, cpu) == box) {
3842 *per_cpu_ptr(pmu->box, cpu) = NULL;
3843 atomic_dec(&box->refcnt);
3847 WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
3851 static int __init uncore_pci_init(void)
3855 switch (boot_cpu_data.x86_model) {
3856 case 45: /* Sandy Bridge-EP */
3857 ret = snbep_pci2phy_map_init(0x3ce0);
3860 pci_uncores = snbep_pci_uncores;
3861 uncore_pci_driver = &snbep_uncore_pci_driver;
3863 case 62: /* IvyTown */
3864 ret = snbep_pci2phy_map_init(0x0e1e);
3867 pci_uncores = ivt_pci_uncores;
3868 uncore_pci_driver = &ivt_uncore_pci_driver;
3870 case 42: /* Sandy Bridge */
3871 ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_SNB_IMC);
3874 pci_uncores = snb_pci_uncores;
3875 uncore_pci_driver = &snb_uncore_pci_driver;
3877 case 58: /* Ivy Bridge */
3878 ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_IVB_IMC);
3881 pci_uncores = snb_pci_uncores;
3882 uncore_pci_driver = &ivb_uncore_pci_driver;
3884 case 60: /* Haswell */
3885 case 69: /* Haswell Celeron */
3886 ret = snb_pci2phy_map_init(PCI_DEVICE_ID_INTEL_HSW_IMC);
3889 pci_uncores = snb_pci_uncores;
3890 uncore_pci_driver = &hsw_uncore_pci_driver;
3896 ret = uncore_types_init(pci_uncores);
3900 uncore_pci_driver->probe = uncore_pci_probe;
3901 uncore_pci_driver->remove = uncore_pci_remove;
3903 ret = pci_register_driver(uncore_pci_driver);
3905 pcidrv_registered = true;
3907 uncore_types_exit(pci_uncores);
3912 static void __init uncore_pci_exit(void)
3914 if (pcidrv_registered) {
3915 pcidrv_registered = false;
3916 pci_unregister_driver(uncore_pci_driver);
3917 uncore_types_exit(pci_uncores);
3921 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
3922 static LIST_HEAD(boxes_to_free);
3924 static void uncore_kfree_boxes(void)
3926 struct intel_uncore_box *box;
3928 while (!list_empty(&boxes_to_free)) {
3929 box = list_entry(boxes_to_free.next,
3930 struct intel_uncore_box, list);
3931 list_del(&box->list);
3936 static void uncore_cpu_dying(int cpu)
3938 struct intel_uncore_type *type;
3939 struct intel_uncore_pmu *pmu;
3940 struct intel_uncore_box *box;
3943 for (i = 0; msr_uncores[i]; i++) {
3944 type = msr_uncores[i];
3945 for (j = 0; j < type->num_boxes; j++) {
3946 pmu = &type->pmus[j];
3947 box = *per_cpu_ptr(pmu->box, cpu);
3948 *per_cpu_ptr(pmu->box, cpu) = NULL;
3949 if (box && atomic_dec_and_test(&box->refcnt))
3950 list_add(&box->list, &boxes_to_free);
3955 static int uncore_cpu_starting(int cpu)
3957 struct intel_uncore_type *type;
3958 struct intel_uncore_pmu *pmu;
3959 struct intel_uncore_box *box, *exist;
3960 int i, j, k, phys_id;
3962 phys_id = topology_physical_package_id(cpu);
3964 for (i = 0; msr_uncores[i]; i++) {
3965 type = msr_uncores[i];
3966 for (j = 0; j < type->num_boxes; j++) {
3967 pmu = &type->pmus[j];
3968 box = *per_cpu_ptr(pmu->box, cpu);
3969 /* called by uncore_cpu_init? */
3970 if (box && box->phys_id >= 0) {
3971 uncore_box_init(box);
3975 for_each_online_cpu(k) {
3976 exist = *per_cpu_ptr(pmu->box, k);
3977 if (exist && exist->phys_id == phys_id) {
3978 atomic_inc(&exist->refcnt);
3979 *per_cpu_ptr(pmu->box, cpu) = exist;
3981 list_add(&box->list,
3990 box->phys_id = phys_id;
3991 uncore_box_init(box);
3998 static int uncore_cpu_prepare(int cpu, int phys_id)
4000 struct intel_uncore_type *type;
4001 struct intel_uncore_pmu *pmu;
4002 struct intel_uncore_box *box;
4005 for (i = 0; msr_uncores[i]; i++) {
4006 type = msr_uncores[i];
4007 for (j = 0; j < type->num_boxes; j++) {
4008 pmu = &type->pmus[j];
4009 if (pmu->func_id < 0)
4012 box = uncore_alloc_box(type, cpu_to_node(cpu));
4017 box->phys_id = phys_id;
4018 *per_cpu_ptr(pmu->box, cpu) = box;
4025 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
4027 struct intel_uncore_type *type;
4028 struct intel_uncore_pmu *pmu;
4029 struct intel_uncore_box *box;
4032 for (i = 0; uncores[i]; i++) {
4034 for (j = 0; j < type->num_boxes; j++) {
4035 pmu = &type->pmus[j];
4037 box = uncore_pmu_to_box(pmu, new_cpu);
4039 box = uncore_pmu_to_box(pmu, old_cpu);
4044 WARN_ON_ONCE(box->cpu != -1);
4049 WARN_ON_ONCE(box->cpu != old_cpu);
4051 uncore_pmu_cancel_hrtimer(box);
4052 perf_pmu_migrate_context(&pmu->pmu,
4062 static void uncore_event_exit_cpu(int cpu)
4064 int i, phys_id, target;
4066 /* if exiting cpu is used for collecting uncore events */
4067 if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
4070 /* find a new cpu to collect uncore events */
4071 phys_id = topology_physical_package_id(cpu);
4073 for_each_online_cpu(i) {
4076 if (phys_id == topology_physical_package_id(i)) {
4082 /* migrate uncore events to the new cpu */
4084 cpumask_set_cpu(target, &uncore_cpu_mask);
4086 uncore_change_context(msr_uncores, cpu, target);
4087 uncore_change_context(pci_uncores, cpu, target);
4090 static void uncore_event_init_cpu(int cpu)
4094 phys_id = topology_physical_package_id(cpu);
4095 for_each_cpu(i, &uncore_cpu_mask) {
4096 if (phys_id == topology_physical_package_id(i))
4100 cpumask_set_cpu(cpu, &uncore_cpu_mask);
4102 uncore_change_context(msr_uncores, -1, cpu);
4103 uncore_change_context(pci_uncores, -1, cpu);
4106 static int uncore_cpu_notifier(struct notifier_block *self,
4107 unsigned long action, void *hcpu)
4109 unsigned int cpu = (long)hcpu;
4111 /* allocate/free data structure for uncore box */
4112 switch (action & ~CPU_TASKS_FROZEN) {
4113 case CPU_UP_PREPARE:
4114 uncore_cpu_prepare(cpu, -1);
4117 uncore_cpu_starting(cpu);
4119 case CPU_UP_CANCELED:
4121 uncore_cpu_dying(cpu);
4125 uncore_kfree_boxes();
4131 /* select the cpu that collects uncore events */
4132 switch (action & ~CPU_TASKS_FROZEN) {
4133 case CPU_DOWN_FAILED:
4135 uncore_event_init_cpu(cpu);
4137 case CPU_DOWN_PREPARE:
4138 uncore_event_exit_cpu(cpu);
4147 static struct notifier_block uncore_cpu_nb = {
4148 .notifier_call = uncore_cpu_notifier,
4150 * to migrate uncore events, our notifier should be executed
4151 * before perf core's notifier.
4153 .priority = CPU_PRI_PERF + 1,
4156 static void __init uncore_cpu_setup(void *dummy)
4158 uncore_cpu_starting(smp_processor_id());
4161 static int __init uncore_cpu_init(void)
4165 max_cores = boot_cpu_data.x86_max_cores;
4166 switch (boot_cpu_data.x86_model) {
4167 case 26: /* Nehalem */
4169 case 37: /* Westmere */
4171 msr_uncores = nhm_msr_uncores;
4173 case 42: /* Sandy Bridge */
4174 case 58: /* Ivy Bridge */
4175 if (snb_uncore_cbox.num_boxes > max_cores)
4176 snb_uncore_cbox.num_boxes = max_cores;
4177 msr_uncores = snb_msr_uncores;
4179 case 45: /* Sandy Bridge-EP */
4180 if (snbep_uncore_cbox.num_boxes > max_cores)
4181 snbep_uncore_cbox.num_boxes = max_cores;
4182 msr_uncores = snbep_msr_uncores;
4184 case 46: /* Nehalem-EX */
4185 uncore_nhmex = true;
4186 case 47: /* Westmere-EX aka. Xeon E7 */
4188 nhmex_uncore_mbox.event_descs = wsmex_uncore_mbox_events;
4189 if (nhmex_uncore_cbox.num_boxes > max_cores)
4190 nhmex_uncore_cbox.num_boxes = max_cores;
4191 msr_uncores = nhmex_msr_uncores;
4193 case 62: /* IvyTown */
4194 if (ivt_uncore_cbox.num_boxes > max_cores)
4195 ivt_uncore_cbox.num_boxes = max_cores;
4196 msr_uncores = ivt_msr_uncores;
4203 ret = uncore_types_init(msr_uncores);
4210 static int __init uncore_pmus_register(void)
4212 struct intel_uncore_pmu *pmu;
4213 struct intel_uncore_type *type;
4216 for (i = 0; msr_uncores[i]; i++) {
4217 type = msr_uncores[i];
4218 for (j = 0; j < type->num_boxes; j++) {
4219 pmu = &type->pmus[j];
4220 uncore_pmu_register(pmu);
4224 for (i = 0; pci_uncores[i]; i++) {
4225 type = pci_uncores[i];
4226 for (j = 0; j < type->num_boxes; j++) {
4227 pmu = &type->pmus[j];
4228 uncore_pmu_register(pmu);
4235 static void __init uncore_cpumask_init(void)
4240 * ony invoke once from msr or pci init code
4242 if (!cpumask_empty(&uncore_cpu_mask))
4245 cpu_notifier_register_begin();
4247 for_each_online_cpu(cpu) {
4248 int i, phys_id = topology_physical_package_id(cpu);
4250 for_each_cpu(i, &uncore_cpu_mask) {
4251 if (phys_id == topology_physical_package_id(i)) {
4259 uncore_cpu_prepare(cpu, phys_id);
4260 uncore_event_init_cpu(cpu);
4262 on_each_cpu(uncore_cpu_setup, NULL, 1);
4264 __register_cpu_notifier(&uncore_cpu_nb);
4266 cpu_notifier_register_done();
4270 static int __init intel_uncore_init(void)
4274 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
4277 if (cpu_has_hypervisor)
4280 ret = uncore_pci_init();
4283 ret = uncore_cpu_init();
4288 uncore_cpumask_init();
4290 uncore_pmus_register();
4295 device_initcall(intel_uncore_init);