arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/mc146818rtc.h>
  29 #include <linux/compiler.h>
  30 #include <linux/acpi.h>
  31 #include <linux/module.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/pci.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/timer.h>
  44 #include <asm/i8259.h>
  45 #include <asm/nmi.h>
  46 #include <asm/msidef.h>
  47 #include <asm/hypertransport.h>
  48
  49 #include <mach_apic.h>
  50 #include <mach_apicdef.h>
  51
  52 int (*ioapic_renumber_irq)(int ioapic, int irq);
  53 atomic_t irq_mis_count;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 int timer_through_8259 __initdata;
  62
  63 /*
  64  *      Is the SiS APIC rmw bug present ?
  65  *      -1 = don't know, 0 = no, 1 = yes
  66  */
  67 int sis_apic_bug = -1;
  68
  69 /*
  70  * # of IRQ routing registers
  71  */
  72 int nr_ioapic_registers[MAX_IO_APICS];
  73
  74 /* I/O APIC entries */
  75 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
  76 int nr_ioapics;
  77
  78 /* MP IRQ source entries */
  79 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  80
  81 /* # of MP IRQ source entries */
  82 int mp_irq_entries;
  83
  84 static int disable_timer_pin_1 __initdata;
  85
  86 /*
  87  * Rough estimation of how many shared IRQs there are, can
  88  * be changed anytime.
  89  */
  90 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  91 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  92
  93 /*
  94  * This is performance-critical, we want to do it O(1)
  95  *
  96  * the indexing order of this array favors 1:1 mappings
  97  * between pins and IRQs.
  98  */
  99
 100 static struct irq_pin_list {
 101         int apic, pin, next;
 102 } irq_2_pin[PIN_MAP_SIZE];
 103
 104 struct io_apic {
 105         unsigned int index;
 106         unsigned int unused[3];
 107         unsigned int data;
 108 };
 109
 110 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 111 {
 112         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 113                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 114 }
 115
 116 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 117 {
 118         struct io_apic __iomem *io_apic = io_apic_base(apic);
 119         writel(reg, &io_apic->index);
 120         return readl(&io_apic->data);
 121 }
 122
 123 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 124 {
 125         struct io_apic __iomem *io_apic = io_apic_base(apic);
 126         writel(reg, &io_apic->index);
 127         writel(value, &io_apic->data);
 128 }
 129
 130 /*
 131  * Re-write a value: to be used for read-modify-write
 132  * cycles where the read already set up the index register.
 133  *
 134  * Older SiS APIC requires we rewrite the index register
 135  */
 136 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 137 {
 138         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 139         if (sis_apic_bug)
 140                 writel(reg, &io_apic->index);
 141         writel(value, &io_apic->data);
 142 }
 143
 144 union entry_union {
 145         struct { u32 w1, w2; };
 146         struct IO_APIC_route_entry entry;
 147 };
 148
 149 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 150 {
 151         union entry_union eu;
 152         unsigned long flags;
 153         spin_lock_irqsave(&ioapic_lock, flags);
 154         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 155         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 156         spin_unlock_irqrestore(&ioapic_lock, flags);
 157         return eu.entry;
 158 }
 159
 160 /*
 161  * When we write a new IO APIC routing entry, we need to write the high
 162  * word first! If the mask bit in the low word is clear, we will enable
 163  * the interrupt, and we need to make sure the entry is fully populated
 164  * before that happens.
 165  */
 166 static void
 167 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 168 {
 169         union entry_union eu;
 170         eu.entry = e;
 171         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 172         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 173 }
 174
 175 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 176 {
 177         unsigned long flags;
 178         spin_lock_irqsave(&ioapic_lock, flags);
 179         __ioapic_write_entry(apic, pin, e);
 180         spin_unlock_irqrestore(&ioapic_lock, flags);
 181 }
 182
 183 /*
 184  * When we mask an IO APIC routing entry, we need to write the low
 185  * word first, in order to set the mask bit before we change the
 186  * high bits!
 187  */
 188 static void ioapic_mask_entry(int apic, int pin)
 189 {
 190         unsigned long flags;
 191         union entry_union eu = { .entry.mask = 1 };
 192
 193         spin_lock_irqsave(&ioapic_lock, flags);
 194         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 195         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 196         spin_unlock_irqrestore(&ioapic_lock, flags);
 197 }
 198
 199 /*
 200  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 201  * shared ISA-space IRQs, so we have to support them. We are super
 202  * fast in the common case, and fast for shared ISA-space IRQs.
 203  */
 204 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 205 {
 206         static int first_free_entry = NR_IRQS;
 207         struct irq_pin_list *entry = irq_2_pin + irq;
 208
 209         while (entry->next)
 210                 entry = irq_2_pin + entry->next;
 211
 212         if (entry->pin != -1) {
 213                 entry->next = first_free_entry;
 214                 entry = irq_2_pin + entry->next;
 215                 if (++first_free_entry >= PIN_MAP_SIZE)
 216                         panic("io_apic.c: whoops");
 217         }
 218         entry->apic = apic;
 219         entry->pin = pin;
 220 }
 221
 222 /*
 223  * Reroute an IRQ to a different pin.
 224  */
 225 static void __init replace_pin_at_irq(unsigned int irq,
 226                                       int oldapic, int oldpin,
 227                                       int newapic, int newpin)
 228 {
 229         struct irq_pin_list *entry = irq_2_pin + irq;
 230
 231         while (1) {
 232                 if (entry->apic == oldapic && entry->pin == oldpin) {
 233                         entry->apic = newapic;
 234                         entry->pin = newpin;
 235                 }
 236                 if (!entry->next)
 237                         break;
 238                 entry = irq_2_pin + entry->next;
 239         }
 240 }
 241
 242 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
 243 {
 244         struct irq_pin_list *entry = irq_2_pin + irq;
 245         unsigned int pin, reg;
 246
 247         for (;;) {
 248                 pin = entry->pin;
 249                 if (pin == -1)
 250                         break;
 251                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 252                 reg &= ~disable;
 253                 reg |= enable;
 254                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 255                 if (!entry->next)
 256                         break;
 257                 entry = irq_2_pin + entry->next;
 258         }
 259 }
 260
 261 /* mask = 1 */
 262 static void __mask_IO_APIC_irq(unsigned int irq)
 263 {
 264         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
 265 }
 266
 267 /* mask = 0 */
 268 static void __unmask_IO_APIC_irq(unsigned int irq)
 269 {
 270         __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
 271 }
 272
 273 /* mask = 1, trigger = 0 */
 274 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
 275 {
 276         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
 277                                 IO_APIC_REDIR_LEVEL_TRIGGER);
 278 }
 279
 280 /* mask = 0, trigger = 1 */
 281 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
 282 {
 283         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
 284                                 IO_APIC_REDIR_MASKED);
 285 }
 286
 287 static void mask_IO_APIC_irq(unsigned int irq)
 288 {
 289         unsigned long flags;
 290
 291         spin_lock_irqsave(&ioapic_lock, flags);
 292         __mask_IO_APIC_irq(irq);
 293         spin_unlock_irqrestore(&ioapic_lock, flags);
 294 }
 295
 296 static void unmask_IO_APIC_irq(unsigned int irq)
 297 {
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&ioapic_lock, flags);
 301         __unmask_IO_APIC_irq(irq);
 302         spin_unlock_irqrestore(&ioapic_lock, flags);
 303 }
 304
 305 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 306 {
 307         struct IO_APIC_route_entry entry;
 308
 309         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 310         entry = ioapic_read_entry(apic, pin);
 311         if (entry.delivery_mode == dest_SMI)
 312                 return;
 313
 314         /*
 315          * Disable it in the IO-APIC irq-routing table:
 316          */
 317         ioapic_mask_entry(apic, pin);
 318 }
 319
 320 static void clear_IO_APIC(void)
 321 {
 322         int apic, pin;
 323
 324         for (apic = 0; apic < nr_ioapics; apic++)
 325                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 326                         clear_IO_APIC_pin(apic, pin);
 327 }
 328
 329 #ifdef CONFIG_SMP
 330 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 331 {
 332         unsigned long flags;
 333         int pin;
 334         struct irq_pin_list *entry = irq_2_pin + irq;
 335         unsigned int apicid_value;
 336         cpumask_t tmp;
 337
 338         cpus_and(tmp, cpumask, cpu_online_map);
 339         if (cpus_empty(tmp))
 340                 tmp = TARGET_CPUS;
 341
 342         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 343
 344         apicid_value = cpu_mask_to_apicid(cpumask);
 345         /* Prepare to do the io_apic_write */
 346         apicid_value = apicid_value << 24;
 347         spin_lock_irqsave(&ioapic_lock, flags);
 348         for (;;) {
 349                 pin = entry->pin;
 350                 if (pin == -1)
 351                         break;
 352                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 353                 if (!entry->next)
 354                         break;
 355                 entry = irq_2_pin + entry->next;
 356         }
 357         irq_desc[irq].affinity = cpumask;
 358         spin_unlock_irqrestore(&ioapic_lock, flags);
 359 }
 360
 361 #if defined(CONFIG_IRQBALANCE)
 362 # include <asm/processor.h>     /* kernel_thread() */
 363 # include <linux/kernel_stat.h> /* kstat */
 364 # include <linux/slab.h>                /* kmalloc() */
 365 # include <linux/timer.h>
 366
 367 #define IRQBALANCE_CHECK_ARCH -999
 368 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 369 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 370 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 371 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 372
 373 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 374 static int physical_balance __read_mostly;
 375 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 376
 377 static struct irq_cpu_info {
 378         unsigned long *last_irq;
 379         unsigned long *irq_delta;
 380         unsigned long irq;
 381 } irq_cpu_data[NR_CPUS];
 382
 383 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 384 #define LAST_CPU_IRQ(cpu, irq)   (irq_cpu_data[cpu].last_irq[irq])
 385 #define IRQ_DELTA(cpu, irq)     (irq_cpu_data[cpu].irq_delta[irq])
 386
 387 #define IDLE_ENOUGH(cpu,now) \
 388         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 389
 390 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 391
 392 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 393
 394 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 395         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 396 };
 397
 398 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 399 {
 400         balance_irq_affinity[irq] = mask;
 401 }
 402
 403 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 404                         unsigned long now, int direction)
 405 {
 406         int search_idle = 1;
 407         int cpu = curr_cpu;
 408
 409         goto inside;
 410
 411         do {
 412                 if (unlikely(cpu == curr_cpu))
 413                         search_idle = 0;
 414 inside:
 415                 if (direction == 1) {
 416                         cpu++;
 417                         if (cpu >= NR_CPUS)
 418                                 cpu = 0;
 419                 } else {
 420                         cpu--;
 421                         if (cpu == -1)
 422                                 cpu = NR_CPUS-1;
 423                 }
 424         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
 425                         (search_idle && !IDLE_ENOUGH(cpu, now)));
 426
 427         return cpu;
 428 }
 429
 430 static inline void balance_irq(int cpu, int irq)
 431 {
 432         unsigned long now = jiffies;
 433         cpumask_t allowed_mask;
 434         unsigned int new_cpu;
 435
 436         if (irqbalance_disabled)
 437                 return;
 438
 439         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 440         new_cpu = move(cpu, allowed_mask, now, 1);
 441         if (cpu != new_cpu)
 442                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 443 }
 444
 445 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 446 {
 447         int i, j;
 448
 449         for_each_online_cpu(i) {
 450                 for (j = 0; j < NR_IRQS; j++) {
 451                         if (!irq_desc[j].action)
 452                                 continue;
 453                         /* Is it a significant load ?  */
 454                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
 455                                                 useful_load_threshold)
 456                                 continue;
 457                         balance_irq(i, j);
 458                 }
 459         }
 460         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 461                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 462         return;
 463 }
 464
 465 static void do_irq_balance(void)
 466 {
 467         int i, j;
 468         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 469         unsigned long move_this_load = 0;
 470         int max_loaded = 0, min_loaded = 0;
 471         int load;
 472         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 473         int selected_irq;
 474         int tmp_loaded, first_attempt = 1;
 475         unsigned long tmp_cpu_irq;
 476         unsigned long imbalance = 0;
 477         cpumask_t allowed_mask, target_cpu_mask, tmp;
 478
 479         for_each_possible_cpu(i) {
 480                 int package_index;
 481                 CPU_IRQ(i) = 0;
 482                 if (!cpu_online(i))
 483                         continue;
 484                 package_index = CPU_TO_PACKAGEINDEX(i);
 485                 for (j = 0; j < NR_IRQS; j++) {
 486                         unsigned long value_now, delta;
 487                         /* Is this an active IRQ or balancing disabled ? */
 488                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 489                                 continue;
 490                         if (package_index == i)
 491                                 IRQ_DELTA(package_index, j) = 0;
 492                         /* Determine the total count per processor per IRQ */
 493                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 494
 495                         /* Determine the activity per processor per IRQ */
 496                         delta = value_now - LAST_CPU_IRQ(i, j);
 497
 498                         /* Update last_cpu_irq[][] for the next time */
 499                         LAST_CPU_IRQ(i, j) = value_now;
 500
 501                         /* Ignore IRQs whose rate is less than the clock */
 502                         if (delta < useful_load_threshold)
 503                                 continue;
 504                         /* update the load for the processor or package total */
 505                         IRQ_DELTA(package_index, j) += delta;
 506
 507                         /* Keep track of the higher numbered sibling as well */
 508                         if (i != package_index)
 509                                 CPU_IRQ(i) += delta;
 510                         /*
 511                          * We have sibling A and sibling B in the package
 512                          *
 513                          * cpu_irq[A] = load for cpu A + load for cpu B
 514                          * cpu_irq[B] = load for cpu B
 515                          */
 516                         CPU_IRQ(package_index) += delta;
 517                 }
 518         }
 519         /* Find the least loaded processor package */
 520         for_each_online_cpu(i) {
 521                 if (i != CPU_TO_PACKAGEINDEX(i))
 522                         continue;
 523                 if (min_cpu_irq > CPU_IRQ(i)) {
 524                         min_cpu_irq = CPU_IRQ(i);
 525                         min_loaded = i;
 526                 }
 527         }
 528         max_cpu_irq = ULONG_MAX;
 529
 530 tryanothercpu:
 531         /*
 532          * Look for heaviest loaded processor.
 533          * We may come back to get the next heaviest loaded processor.
 534          * Skip processors with trivial loads.
 535          */
 536         tmp_cpu_irq = 0;
 537         tmp_loaded = -1;
 538         for_each_online_cpu(i) {
 539                 if (i != CPU_TO_PACKAGEINDEX(i))
 540                         continue;
 541                 if (max_cpu_irq <= CPU_IRQ(i))
 542                         continue;
 543                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 544                         tmp_cpu_irq = CPU_IRQ(i);
 545                         tmp_loaded = i;
 546                 }
 547         }
 548
 549         if (tmp_loaded == -1) {
 550          /*
 551           * In the case of small number of heavy interrupt sources,
 552           * loading some of the cpus too much. We use Ingo's original
 553           * approach to rotate them around.
 554           */
 555                 if (!first_attempt && imbalance >= useful_load_threshold) {
 556                         rotate_irqs_among_cpus(useful_load_threshold);
 557                         return;
 558                 }
 559                 goto not_worth_the_effort;
 560         }
 561
 562         first_attempt = 0;              /* heaviest search */
 563         max_cpu_irq = tmp_cpu_irq;      /* load */
 564         max_loaded = tmp_loaded;        /* processor */
 565         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 566
 567         /*
 568          * if imbalance is less than approx 10% of max load, then
 569          * observe diminishing returns action. - quit
 570          */
 571         if (imbalance < (max_cpu_irq >> 3))
 572                 goto not_worth_the_effort;
 573
 574 tryanotherirq:
 575         /* if we select an IRQ to move that can't go where we want, then
 576          * see if there is another one to try.
 577          */
 578         move_this_load = 0;
 579         selected_irq = -1;
 580         for (j = 0; j < NR_IRQS; j++) {
 581                 /* Is this an active IRQ? */
 582                 if (!irq_desc[j].action)
 583                         continue;
 584                 if (imbalance <= IRQ_DELTA(max_loaded, j))
 585                         continue;
 586                 /* Try to find the IRQ that is closest to the imbalance
 587                  * without going over.
 588                  */
 589                 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
 590                         move_this_load = IRQ_DELTA(max_loaded, j);
 591                         selected_irq = j;
 592                 }
 593         }
 594         if (selected_irq == -1)
 595                 goto tryanothercpu;
 596
 597         imbalance = move_this_load;
 598
 599         /* For physical_balance case, we accumulated both load
 600          * values in the one of the siblings cpu_irq[],
 601          * to use the same code for physical and logical processors
 602          * as much as possible.
 603          *
 604          * NOTE: the cpu_irq[] array holds the sum of the load for
 605          * sibling A and sibling B in the slot for the lowest numbered
 606          * sibling (A), _AND_ the load for sibling B in the slot for
 607          * the higher numbered sibling.
 608          *
 609          * We seek the least loaded sibling by making the comparison
 610          * (A+B)/2 vs B
 611          */
 612         load = CPU_IRQ(min_loaded) >> 1;
 613         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 614                 if (load > CPU_IRQ(j)) {
 615                         /* This won't change cpu_sibling_map[min_loaded] */
 616                         load = CPU_IRQ(j);
 617                         min_loaded = j;
 618                 }
 619         }
 620
 621         cpus_and(allowed_mask,
 622                 cpu_online_map,
 623                 balance_irq_affinity[selected_irq]);
 624         target_cpu_mask = cpumask_of_cpu(min_loaded);
 625         cpus_and(tmp, target_cpu_mask, allowed_mask);
 626
 627         if (!cpus_empty(tmp)) {
 628                 /* mark for change destination */
 629                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 630
 631                 /* Since we made a change, come back sooner to
 632                  * check for more variation.
 633                  */
 634                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 635                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 636                 return;
 637         }
 638         goto tryanotherirq;
 639
 640 not_worth_the_effort:
 641         /*
 642          * if we did not find an IRQ to move, then adjust the time interval
 643          * upward
 644          */
 645         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 646                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 647         return;
 648 }
 649
 650 static int balanced_irq(void *unused)
 651 {
 652         int i;
 653         unsigned long prev_balance_time = jiffies;
 654         long time_remaining = balanced_irq_interval;
 655
 656         /* push everything to CPU 0 to give us a starting point.  */
 657         for (i = 0 ; i < NR_IRQS ; i++) {
 658                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 659                 set_pending_irq(i, cpumask_of_cpu(0));
 660         }
 661
 662         set_freezable();
 663         for ( ; ; ) {
 664                 time_remaining = schedule_timeout_interruptible(time_remaining);
 665                 try_to_freeze();
 666                 if (time_after(jiffies,
 667                                 prev_balance_time+balanced_irq_interval)) {
 668                         preempt_disable();
 669                         do_irq_balance();
 670                         prev_balance_time = jiffies;
 671                         time_remaining = balanced_irq_interval;
 672                         preempt_enable();
 673                 }
 674         }
 675         return 0;
 676 }
 677
 678 static int __init balanced_irq_init(void)
 679 {
 680         int i;
 681         struct cpuinfo_x86 *c;
 682         cpumask_t tmp;
 683
 684         cpus_shift_right(tmp, cpu_online_map, 2);
 685         c = &boot_cpu_data;
 686         /* When not overwritten by the command line ask subarchitecture. */
 687         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 688                 irqbalance_disabled = NO_BALANCE_IRQ;
 689         if (irqbalance_disabled)
 690                 return 0;
 691
 692          /* disable irqbalance completely if there is only one processor online */
 693         if (num_online_cpus() < 2) {
 694                 irqbalance_disabled = 1;
 695                 return 0;
 696         }
 697         /*
 698          * Enable physical balance only if more than 1 physical processor
 699          * is present
 700          */
 701         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 702                 physical_balance = 1;
 703
 704         for_each_online_cpu(i) {
 705                 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 706                 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 707                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 708                         printk(KERN_ERR "balanced_irq_init: out of memory");
 709                         goto failed;
 710                 }
 711         }
 712
 713         printk(KERN_INFO "Starting balanced_irq\n");
 714         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 715                 return 0;
 716         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 717 failed:
 718         for_each_possible_cpu(i) {
 719                 kfree(irq_cpu_data[i].irq_delta);
 720                 irq_cpu_data[i].irq_delta = NULL;
 721                 kfree(irq_cpu_data[i].last_irq);
 722                 irq_cpu_data[i].last_irq = NULL;
 723         }
 724         return 0;
 725 }
 726
 727 int __devinit irqbalance_disable(char *str)
 728 {
 729         irqbalance_disabled = 1;
 730         return 1;
 731 }
 732
 733 __setup("noirqbalance", irqbalance_disable);
 734
 735 late_initcall(balanced_irq_init);
 736 #endif /* CONFIG_IRQBALANCE */
 737 #endif /* CONFIG_SMP */
 738
 739 #ifndef CONFIG_SMP
 740 void send_IPI_self(int vector)
 741 {
 742         unsigned int cfg;
 743
 744         /*
 745          * Wait for idle.
 746          */
 747         apic_wait_icr_idle();
 748         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 749         /*
 750          * Send the IPI. The write to APIC_ICR fires this off.
 751          */
 752         apic_write_around(APIC_ICR, cfg);
 753 }
 754 #endif /* !CONFIG_SMP */
 755
 756
 757 /*
 758  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 759  * specific CPU-side IRQs.
 760  */
 761
 762 #define MAX_PIRQS 8
 763 static int pirq_entries [MAX_PIRQS];
 764 static int pirqs_enabled;
 765 int skip_ioapic_setup;
 766
 767 static int __init ioapic_pirq_setup(char *str)
 768 {
 769         int i, max;
 770         int ints[MAX_PIRQS+1];
 771
 772         get_options(str, ARRAY_SIZE(ints), ints);
 773
 774         for (i = 0; i < MAX_PIRQS; i++)
 775                 pirq_entries[i] = -1;
 776
 777         pirqs_enabled = 1;
 778         apic_printk(APIC_VERBOSE, KERN_INFO
 779                         "PIRQ redirection, working around broken MP-BIOS.\n");
 780         max = MAX_PIRQS;
 781         if (ints[0] < MAX_PIRQS)
 782                 max = ints[0];
 783
 784         for (i = 0; i < max; i++) {
 785                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 786                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 787                 /*
 788                  * PIRQs are mapped upside down, usually.
 789                  */
 790                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 791         }
 792         return 1;
 793 }
 794
 795 __setup("pirq=", ioapic_pirq_setup);
 796
 797 /*
 798  * Find the IRQ entry number of a certain pin.
 799  */
 800 static int find_irq_entry(int apic, int pin, int type)
 801 {
 802         int i;
 803
 804         for (i = 0; i < mp_irq_entries; i++)
 805                 if (mp_irqs[i].mpc_irqtype == type &&
 806                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 807                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 808                     mp_irqs[i].mpc_dstirq == pin)
 809                         return i;
 810
 811         return -1;
 812 }
 813
 814 /*
 815  * Find the pin to which IRQ[irq] (ISA) is connected
 816  */
 817 static int __init find_isa_irq_pin(int irq, int type)
 818 {
 819         int i;
 820
 821         for (i = 0; i < mp_irq_entries; i++) {
 822                 int lbus = mp_irqs[i].mpc_srcbus;
 823
 824                 if (test_bit(lbus, mp_bus_not_pci) &&
 825                     (mp_irqs[i].mpc_irqtype == type) &&
 826                     (mp_irqs[i].mpc_srcbusirq == irq))
 827
 828                         return mp_irqs[i].mpc_dstirq;
 829         }
 830         return -1;
 831 }
 832
 833 static int __init find_isa_irq_apic(int irq, int type)
 834 {
 835         int i;
 836
 837         for (i = 0; i < mp_irq_entries; i++) {
 838                 int lbus = mp_irqs[i].mpc_srcbus;
 839
 840                 if (test_bit(lbus, mp_bus_not_pci) &&
 841                     (mp_irqs[i].mpc_irqtype == type) &&
 842                     (mp_irqs[i].mpc_srcbusirq == irq))
 843                         break;
 844         }
 845         if (i < mp_irq_entries) {
 846                 int apic;
 847                 for (apic = 0; apic < nr_ioapics; apic++) {
 848                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 849                                 return apic;
 850                 }
 851         }
 852
 853         return -1;
 854 }
 855
 856 /*
 857  * Find a specific PCI IRQ entry.
 858  * Not an __init, possibly needed by modules
 859  */
 860 static int pin_2_irq(int idx, int apic, int pin);
 861
 862 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 863 {
 864         int apic, i, best_guess = -1;
 865
 866         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 867                 "slot:%d, pin:%d.\n", bus, slot, pin);
 868         if (mp_bus_id_to_pci_bus[bus] == -1) {
 869                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 870                 return -1;
 871         }
 872         for (i = 0; i < mp_irq_entries; i++) {
 873                 int lbus = mp_irqs[i].mpc_srcbus;
 874
 875                 for (apic = 0; apic < nr_ioapics; apic++)
 876                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 877                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 878                                 break;
 879
 880                 if (!test_bit(lbus, mp_bus_not_pci) &&
 881                     !mp_irqs[i].mpc_irqtype &&
 882                     (bus == lbus) &&
 883                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 884                         int irq = pin_2_irq(i, apic, mp_irqs[i].mpc_dstirq);
 885
 886                         if (!(apic || IO_APIC_IRQ(irq)))
 887                                 continue;
 888
 889                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 890                                 return irq;
 891                         /*
 892                          * Use the first all-but-pin matching entry as a
 893                          * best-guess fuzzy result for broken mptables.
 894                          */
 895                         if (best_guess < 0)
 896                                 best_guess = irq;
 897                 }
 898         }
 899         return best_guess;
 900 }
 901 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 902
 903 /*
 904  * This function currently is only a helper for the i386 smp boot process where
 905  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 906  * so mask in all cases should simply be TARGET_CPUS
 907  */
 908 #ifdef CONFIG_SMP
 909 void __init setup_ioapic_dest(void)
 910 {
 911         int pin, ioapic, irq, irq_entry;
 912
 913         if (skip_ioapic_setup == 1)
 914                 return;
 915
 916         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 917                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 918                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 919                         if (irq_entry == -1)
 920                                 continue;
 921                         irq = pin_2_irq(irq_entry, ioapic, pin);
 922                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 923                 }
 924
 925         }
 926 }
 927 #endif
 928
 929 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 930 /*
 931  * EISA Edge/Level control register, ELCR
 932  */
 933 static int EISA_ELCR(unsigned int irq)
 934 {
 935         if (irq < 16) {
 936                 unsigned int port = 0x4d0 + (irq >> 3);
 937                 return (inb(port) >> (irq & 7)) & 1;
 938         }
 939         apic_printk(APIC_VERBOSE, KERN_INFO
 940                         "Broken MPtable reports ISA irq %d\n", irq);
 941         return 0;
 942 }
 943 #endif
 944
 945 /* ISA interrupts are always polarity zero edge triggered,
 946  * when listed as conforming in the MP table. */
 947
 948 #define default_ISA_trigger(idx)        (0)
 949 #define default_ISA_polarity(idx)       (0)
 950
 951 /* EISA interrupts are always polarity zero and can be edge or level
 952  * trigger depending on the ELCR value.  If an interrupt is listed as
 953  * EISA conforming in the MP table, that means its trigger type must
 954  * be read in from the ELCR */
 955
 956 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 957 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 958
 959 /* PCI interrupts are always polarity one level triggered,
 960  * when listed as conforming in the MP table. */
 961
 962 #define default_PCI_trigger(idx)        (1)
 963 #define default_PCI_polarity(idx)       (1)
 964
 965 /* MCA interrupts are always polarity zero level triggered,
 966  * when listed as conforming in the MP table. */
 967
 968 #define default_MCA_trigger(idx)        (1)
 969 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 970
 971 static int MPBIOS_polarity(int idx)
 972 {
 973         int bus = mp_irqs[idx].mpc_srcbus;
 974         int polarity;
 975
 976         /*
 977          * Determine IRQ line polarity (high active or low active):
 978          */
 979         switch (mp_irqs[idx].mpc_irqflag & 3) {
 980         case 0: /* conforms, ie. bus-type dependent polarity */
 981         {
 982                 polarity = test_bit(bus, mp_bus_not_pci)?
 983                         default_ISA_polarity(idx):
 984                         default_PCI_polarity(idx);
 985                 break;
 986         }
 987         case 1: /* high active */
 988         {
 989                 polarity = 0;
 990                 break;
 991         }
 992         case 2: /* reserved */
 993         {
 994                 printk(KERN_WARNING "broken BIOS!!\n");
 995                 polarity = 1;
 996                 break;
 997         }
 998         case 3: /* low active */
 999         {
1000                 polarity = 1;
1001                 break;
1002         }
1003         default: /* invalid */
1004         {
1005                 printk(KERN_WARNING "broken BIOS!!\n");
1006                 polarity = 1;
1007                 break;
1008         }
1009         }
1010         return polarity;
1011 }
1012
1013 static int MPBIOS_trigger(int idx)
1014 {
1015         int bus = mp_irqs[idx].mpc_srcbus;
1016         int trigger;
1017
1018         /*
1019          * Determine IRQ trigger mode (edge or level sensitive):
1020          */
1021         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) {
1022         case 0: /* conforms, ie. bus-type dependent */
1023         {
1024                 trigger = test_bit(bus, mp_bus_not_pci)?
1025                                 default_ISA_trigger(idx):
1026                                 default_PCI_trigger(idx);
1027 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1028                 switch (mp_bus_id_to_type[bus]) {
1029                 case MP_BUS_ISA: /* ISA pin */
1030                 {
1031                         /* set before the switch */
1032                         break;
1033                 }
1034                 case MP_BUS_EISA: /* EISA pin */
1035                 {
1036                         trigger = default_EISA_trigger(idx);
1037                         break;
1038                 }
1039                 case MP_BUS_PCI: /* PCI pin */
1040                 {
1041                         /* set before the switch */
1042                         break;
1043                 }
1044                 case MP_BUS_MCA: /* MCA pin */
1045                 {
1046                         trigger = default_MCA_trigger(idx);
1047                         break;
1048                 }
1049                 default:
1050                 {
1051                         printk(KERN_WARNING "broken BIOS!!\n");
1052                         trigger = 1;
1053                         break;
1054                 }
1055         }
1056 #endif
1057                 break;
1058         }
1059         case 1: /* edge */
1060         {
1061                 trigger = 0;
1062                 break;
1063         }
1064         case 2: /* reserved */
1065         {
1066                 printk(KERN_WARNING "broken BIOS!!\n");
1067                 trigger = 1;
1068                 break;
1069         }
1070         case 3: /* level */
1071         {
1072                 trigger = 1;
1073                 break;
1074         }
1075         default: /* invalid */
1076         {
1077                 printk(KERN_WARNING "broken BIOS!!\n");
1078                 trigger = 0;
1079                 break;
1080         }
1081         }
1082         return trigger;
1083 }
1084
1085 static inline int irq_polarity(int idx)
1086 {
1087         return MPBIOS_polarity(idx);
1088 }
1089
1090 static inline int irq_trigger(int idx)
1091 {
1092         return MPBIOS_trigger(idx);
1093 }
1094
1095 static int pin_2_irq(int idx, int apic, int pin)
1096 {
1097         int irq, i;
1098         int bus = mp_irqs[idx].mpc_srcbus;
1099
1100         /*
1101          * Debugging check, we are in big trouble if this message pops up!
1102          */
1103         if (mp_irqs[idx].mpc_dstirq != pin)
1104                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1105
1106         if (test_bit(bus, mp_bus_not_pci))
1107                 irq = mp_irqs[idx].mpc_srcbusirq;
1108         else {
1109                 /*
1110                  * PCI IRQs are mapped in order
1111                  */
1112                 i = irq = 0;
1113                 while (i < apic)
1114                         irq += nr_ioapic_registers[i++];
1115                 irq += pin;
1116
1117                 /*
1118                  * For MPS mode, so far only needed by ES7000 platform
1119                  */
1120                 if (ioapic_renumber_irq)
1121                         irq = ioapic_renumber_irq(apic, irq);
1122         }
1123
1124         /*
1125          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1126          */
1127         if ((pin >= 16) && (pin <= 23)) {
1128                 if (pirq_entries[pin-16] != -1) {
1129                         if (!pirq_entries[pin-16]) {
1130                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1131                                                 "disabling PIRQ%d\n", pin-16);
1132                         } else {
1133                                 irq = pirq_entries[pin-16];
1134                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1135                                                 "using PIRQ%d -> IRQ %d\n",
1136                                                 pin-16, irq);
1137                         }
1138                 }
1139         }
1140         return irq;
1141 }
1142
1143 static inline int IO_APIC_irq_trigger(int irq)
1144 {
1145         int apic, idx, pin;
1146
1147         for (apic = 0; apic < nr_ioapics; apic++) {
1148                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1149                         idx = find_irq_entry(apic, pin, mp_INT);
1150                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1151                                 return irq_trigger(idx);
1152                 }
1153         }
1154         /*
1155          * nonexistent IRQs are edge default
1156          */
1157         return 0;
1158 }
1159
1160 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1161 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1162
1163 static int __assign_irq_vector(int irq)
1164 {
1165         static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1166         int vector, offset;
1167
1168         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1169
1170         if (irq_vector[irq] > 0)
1171                 return irq_vector[irq];
1172
1173         vector = current_vector;
1174         offset = current_offset;
1175 next:
1176         vector += 8;
1177         if (vector >= FIRST_SYSTEM_VECTOR) {
1178                 offset = (offset + 1) % 8;
1179                 vector = FIRST_DEVICE_VECTOR + offset;
1180         }
1181         if (vector == current_vector)
1182                 return -ENOSPC;
1183         if (test_and_set_bit(vector, used_vectors))
1184                 goto next;
1185
1186         current_vector = vector;
1187         current_offset = offset;
1188         irq_vector[irq] = vector;
1189
1190         return vector;
1191 }
1192
1193 static int assign_irq_vector(int irq)
1194 {
1195         unsigned long flags;
1196         int vector;
1197
1198         spin_lock_irqsave(&vector_lock, flags);
1199         vector = __assign_irq_vector(irq);
1200         spin_unlock_irqrestore(&vector_lock, flags);
1201
1202         return vector;
1203 }
1204 static struct irq_chip ioapic_chip;
1205
1206 #define IOAPIC_AUTO     -1
1207 #define IOAPIC_EDGE     0
1208 #define IOAPIC_LEVEL    1
1209
1210 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1211 {
1212         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1213             trigger == IOAPIC_LEVEL) {
1214                 irq_desc[irq].status |= IRQ_LEVEL;
1215                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1216                                          handle_fasteoi_irq, "fasteoi");
1217         } else {
1218                 irq_desc[irq].status &= ~IRQ_LEVEL;
1219                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1220                                          handle_edge_irq, "edge");
1221         }
1222         set_intr_gate(vector, interrupt[irq]);
1223 }
1224
1225 static void __init setup_IO_APIC_irqs(void)
1226 {
1227         struct IO_APIC_route_entry entry;
1228         int apic, pin, idx, irq, first_notcon = 1, vector;
1229
1230         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1231
1232         for (apic = 0; apic < nr_ioapics; apic++) {
1233         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1234
1235                 /*
1236                  * add it to the IO-APIC irq-routing table:
1237                  */
1238                 memset(&entry, 0, sizeof(entry));
1239
1240                 entry.delivery_mode = INT_DELIVERY_MODE;
1241                 entry.dest_mode = INT_DEST_MODE;
1242                 entry.mask = 0;                         /* enable IRQ */
1243                 entry.dest.logical.logical_dest =
1244                                         cpu_mask_to_apicid(TARGET_CPUS);
1245
1246                 idx = find_irq_entry(apic, pin, mp_INT);
1247                 if (idx == -1) {
1248                         if (first_notcon) {
1249                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1250                                                 " IO-APIC (apicid-pin) %d-%d",
1251                                                 mp_ioapics[apic].mpc_apicid,
1252                                                 pin);
1253                                 first_notcon = 0;
1254                         } else
1255                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1256                                         mp_ioapics[apic].mpc_apicid, pin);
1257                         continue;
1258                 }
1259
1260                 if (!first_notcon) {
1261                         apic_printk(APIC_VERBOSE, " not connected.\n");
1262                         first_notcon = 1;
1263                 }
1264
1265                 entry.trigger = irq_trigger(idx);
1266                 entry.polarity = irq_polarity(idx);
1267
1268                 if (irq_trigger(idx)) {
1269                         entry.trigger = 1;
1270                         entry.mask = 1;
1271                 }
1272
1273                 irq = pin_2_irq(idx, apic, pin);
1274                 /*
1275                  * skip adding the timer int on secondary nodes, which causes
1276                  * a small but painful rift in the time-space continuum
1277                  */
1278                 if (multi_timer_check(apic, irq))
1279                         continue;
1280                 else
1281                         add_pin_to_irq(irq, apic, pin);
1282
1283                 if (!apic && !IO_APIC_IRQ(irq))
1284                         continue;
1285
1286                 if (IO_APIC_IRQ(irq)) {
1287                         vector = assign_irq_vector(irq);
1288                         entry.vector = vector;
1289                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1290
1291                         if (!apic && (irq < 16))
1292                                 disable_8259A_irq(irq);
1293                 }
1294                 ioapic_write_entry(apic, pin, entry);
1295         }
1296         }
1297
1298         if (!first_notcon)
1299                 apic_printk(APIC_VERBOSE, " not connected.\n");
1300 }
1301
1302 /*
1303  * Set up the timer pin, possibly with the 8259A-master behind.
1304  */
1305 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1306                                         int vector)
1307 {
1308         struct IO_APIC_route_entry entry;
1309
1310         memset(&entry, 0, sizeof(entry));
1311
1312         /*
1313          * We use logical delivery to get the timer IRQ
1314          * to the first CPU.
1315          */
1316         entry.dest_mode = INT_DEST_MODE;
1317         entry.mask = 1;                                 /* mask IRQ now */
1318         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1319         entry.delivery_mode = INT_DELIVERY_MODE;
1320         entry.polarity = 0;
1321         entry.trigger = 0;
1322         entry.vector = vector;
1323
1324         /*
1325          * The timer IRQ doesn't have to know that behind the
1326          * scene we may have a 8259A-master in AEOI mode ...
1327          */
1328         ioapic_register_intr(0, vector, IOAPIC_EDGE);
1329
1330         /*
1331          * Add it to the IO-APIC irq-routing table:
1332          */
1333         ioapic_write_entry(apic, pin, entry);
1334 }
1335
1336 void __init print_IO_APIC(void)
1337 {
1338         int apic, i;
1339         union IO_APIC_reg_00 reg_00;
1340         union IO_APIC_reg_01 reg_01;
1341         union IO_APIC_reg_02 reg_02;
1342         union IO_APIC_reg_03 reg_03;
1343         unsigned long flags;
1344
1345         if (apic_verbosity == APIC_QUIET)
1346                 return;
1347
1348         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1349         for (i = 0; i < nr_ioapics; i++)
1350                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1351                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1352
1353         /*
1354          * We are a bit conservative about what we expect.  We have to
1355          * know about every hardware change ASAP.
1356          */
1357         printk(KERN_INFO "testing the IO APIC.......................\n");
1358
1359         for (apic = 0; apic < nr_ioapics; apic++) {
1360
1361         spin_lock_irqsave(&ioapic_lock, flags);
1362         reg_00.raw = io_apic_read(apic, 0);
1363         reg_01.raw = io_apic_read(apic, 1);
1364         if (reg_01.bits.version >= 0x10)
1365                 reg_02.raw = io_apic_read(apic, 2);
1366         if (reg_01.bits.version >= 0x20)
1367                 reg_03.raw = io_apic_read(apic, 3);
1368         spin_unlock_irqrestore(&ioapic_lock, flags);
1369
1370         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1371         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1372         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1373         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1374         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1375
1376         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1377         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1378
1379         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1380         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1381
1382         /*
1383          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1384          * but the value of reg_02 is read as the previous read register
1385          * value, so ignore it if reg_02 == reg_01.
1386          */
1387         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1388                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1389                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1390         }
1391
1392         /*
1393          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1394          * or reg_03, but the value of reg_0[23] is read as the previous read
1395          * register value, so ignore it if reg_03 == reg_0[12].
1396          */
1397         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1398             reg_03.raw != reg_01.raw) {
1399                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1400                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1401         }
1402
1403         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1404
1405         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1406                           " Stat Dest Deli Vect:   \n");
1407
1408         for (i = 0; i <= reg_01.bits.entries; i++) {
1409                 struct IO_APIC_route_entry entry;
1410
1411                 entry = ioapic_read_entry(apic, i);
1412
1413                 printk(KERN_DEBUG " %02x %03X %02X  ",
1414                         i,
1415                         entry.dest.logical.logical_dest,
1416                         entry.dest.physical.physical_dest
1417                 );
1418
1419                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1420                         entry.mask,
1421                         entry.trigger,
1422                         entry.irr,
1423                         entry.polarity,
1424                         entry.delivery_status,
1425                         entry.dest_mode,
1426                         entry.delivery_mode,
1427                         entry.vector
1428                 );
1429         }
1430         }
1431         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1432         for (i = 0; i < NR_IRQS; i++) {
1433                 struct irq_pin_list *entry = irq_2_pin + i;
1434                 if (entry->pin < 0)
1435                         continue;
1436                 printk(KERN_DEBUG "IRQ%d ", i);
1437                 for (;;) {
1438                         printk("-> %d:%d", entry->apic, entry->pin);
1439                         if (!entry->next)
1440                                 break;
1441                         entry = irq_2_pin + entry->next;
1442                 }
1443                 printk("\n");
1444         }
1445
1446         printk(KERN_INFO ".................................... done.\n");
1447
1448         return;
1449 }
1450
1451 #if 0
1452
1453 static void print_APIC_bitfield(int base)
1454 {
1455         unsigned int v;
1456         int i, j;
1457
1458         if (apic_verbosity == APIC_QUIET)
1459                 return;
1460
1461         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1462         for (i = 0; i < 8; i++) {
1463                 v = apic_read(base + i*0x10);
1464                 for (j = 0; j < 32; j++) {
1465                         if (v & (1<<j))
1466                                 printk("1");
1467                         else
1468                                 printk("0");
1469                 }
1470                 printk("\n");
1471         }
1472 }
1473
1474 void /*__init*/ print_local_APIC(void *dummy)
1475 {
1476         unsigned int v, ver, maxlvt;
1477
1478         if (apic_verbosity == APIC_QUIET)
1479                 return;
1480
1481         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1482                 smp_processor_id(), hard_smp_processor_id());
1483         v = apic_read(APIC_ID);
1484         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1485                         GET_APIC_ID(read_apic_id()));
1486         v = apic_read(APIC_LVR);
1487         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1488         ver = GET_APIC_VERSION(v);
1489         maxlvt = lapic_get_maxlvt();
1490
1491         v = apic_read(APIC_TASKPRI);
1492         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1493
1494         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1495                 v = apic_read(APIC_ARBPRI);
1496                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1497                         v & APIC_ARBPRI_MASK);
1498                 v = apic_read(APIC_PROCPRI);
1499                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1500         }
1501
1502         v = apic_read(APIC_EOI);
1503         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1504         v = apic_read(APIC_RRR);
1505         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1506         v = apic_read(APIC_LDR);
1507         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1508         v = apic_read(APIC_DFR);
1509         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1510         v = apic_read(APIC_SPIV);
1511         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1512
1513         printk(KERN_DEBUG "... APIC ISR field:\n");
1514         print_APIC_bitfield(APIC_ISR);
1515         printk(KERN_DEBUG "... APIC TMR field:\n");
1516         print_APIC_bitfield(APIC_TMR);
1517         printk(KERN_DEBUG "... APIC IRR field:\n");
1518         print_APIC_bitfield(APIC_IRR);
1519
1520         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1521                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1522                         apic_write(APIC_ESR, 0);
1523                 v = apic_read(APIC_ESR);
1524                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1525         }
1526
1527         v = apic_read(APIC_ICR);
1528         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1529         v = apic_read(APIC_ICR2);
1530         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1531
1532         v = apic_read(APIC_LVTT);
1533         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1534
1535         if (maxlvt > 3) {                       /* PC is LVT#4. */
1536                 v = apic_read(APIC_LVTPC);
1537                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1538         }
1539         v = apic_read(APIC_LVT0);
1540         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1541         v = apic_read(APIC_LVT1);
1542         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1543
1544         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1545                 v = apic_read(APIC_LVTERR);
1546                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1547         }
1548
1549         v = apic_read(APIC_TMICT);
1550         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1551         v = apic_read(APIC_TMCCT);
1552         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1553         v = apic_read(APIC_TDCR);
1554         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1555         printk("\n");
1556 }
1557
1558 void print_all_local_APICs(void)
1559 {
1560         on_each_cpu(print_local_APIC, NULL, 1, 1);
1561 }
1562
1563 void /*__init*/ print_PIC(void)
1564 {
1565         unsigned int v;
1566         unsigned long flags;
1567
1568         if (apic_verbosity == APIC_QUIET)
1569                 return;
1570
1571         printk(KERN_DEBUG "\nprinting PIC contents\n");
1572
1573         spin_lock_irqsave(&i8259A_lock, flags);
1574
1575         v = inb(0xa1) << 8 | inb(0x21);
1576         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1577
1578         v = inb(0xa0) << 8 | inb(0x20);
1579         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1580
1581         outb(0x0b, 0xa0);
1582         outb(0x0b, 0x20);
1583         v = inb(0xa0) << 8 | inb(0x20);
1584         outb(0x0a, 0xa0);
1585         outb(0x0a, 0x20);
1586
1587         spin_unlock_irqrestore(&i8259A_lock, flags);
1588
1589         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1590
1591         v = inb(0x4d1) << 8 | inb(0x4d0);
1592         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1593 }
1594
1595 #endif  /*  0  */
1596
1597 static void __init enable_IO_APIC(void)
1598 {
1599         union IO_APIC_reg_01 reg_01;
1600         int i8259_apic, i8259_pin;
1601         int i, apic;
1602         unsigned long flags;
1603
1604         for (i = 0; i < PIN_MAP_SIZE; i++) {
1605                 irq_2_pin[i].pin = -1;
1606                 irq_2_pin[i].next = 0;
1607         }
1608         if (!pirqs_enabled)
1609                 for (i = 0; i < MAX_PIRQS; i++)
1610                         pirq_entries[i] = -1;
1611
1612         /*
1613          * The number of IO-APIC IRQ registers (== #pins):
1614          */
1615         for (apic = 0; apic < nr_ioapics; apic++) {
1616                 spin_lock_irqsave(&ioapic_lock, flags);
1617                 reg_01.raw = io_apic_read(apic, 1);
1618                 spin_unlock_irqrestore(&ioapic_lock, flags);
1619                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1620         }
1621         for (apic = 0; apic < nr_ioapics; apic++) {
1622                 int pin;
1623                 /* See if any of the pins is in ExtINT mode */
1624                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1625                         struct IO_APIC_route_entry entry;
1626                         entry = ioapic_read_entry(apic, pin);
1627
1628
1629                         /* If the interrupt line is enabled and in ExtInt mode
1630                          * I have found the pin where the i8259 is connected.
1631                          */
1632                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1633                                 ioapic_i8259.apic = apic;
1634                                 ioapic_i8259.pin  = pin;
1635                                 goto found_i8259;
1636                         }
1637                 }
1638         }
1639  found_i8259:
1640         /* Look to see what if the MP table has reported the ExtINT */
1641         /* If we could not find the appropriate pin by looking at the ioapic
1642          * the i8259 probably is not connected the ioapic but give the
1643          * mptable a chance anyway.
1644          */
1645         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1646         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1647         /* Trust the MP table if nothing is setup in the hardware */
1648         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1649                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1650                 ioapic_i8259.pin  = i8259_pin;
1651                 ioapic_i8259.apic = i8259_apic;
1652         }
1653         /* Complain if the MP table and the hardware disagree */
1654         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1655                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1656         {
1657                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1658         }
1659
1660         /*
1661          * Do not trust the IO-APIC being empty at bootup
1662          */
1663         clear_IO_APIC();
1664 }
1665
1666 /*
1667  * Not an __init, needed by the reboot code
1668  */
1669 void disable_IO_APIC(void)
1670 {
1671         /*
1672          * Clear the IO-APIC before rebooting:
1673          */
1674         clear_IO_APIC();
1675
1676         /*
1677          * If the i8259 is routed through an IOAPIC
1678          * Put that IOAPIC in virtual wire mode
1679          * so legacy interrupts can be delivered.
1680          */
1681         if (ioapic_i8259.pin != -1) {
1682                 struct IO_APIC_route_entry entry;
1683
1684                 memset(&entry, 0, sizeof(entry));
1685                 entry.mask            = 0; /* Enabled */
1686                 entry.trigger         = 0; /* Edge */
1687                 entry.irr             = 0;
1688                 entry.polarity        = 0; /* High */
1689                 entry.delivery_status = 0;
1690                 entry.dest_mode       = 0; /* Physical */
1691                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1692                 entry.vector          = 0;
1693                 entry.dest.physical.physical_dest =
1694                                         GET_APIC_ID(read_apic_id());
1695
1696                 /*
1697                  * Add it to the IO-APIC irq-routing table:
1698                  */
1699                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1700         }
1701         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1702 }
1703
1704 /*
1705  * function to set the IO-APIC physical IDs based on the
1706  * values stored in the MPC table.
1707  *
1708  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1709  */
1710
1711 #ifndef CONFIG_X86_NUMAQ
1712 static void __init setup_ioapic_ids_from_mpc(void)
1713 {
1714         union IO_APIC_reg_00 reg_00;
1715         physid_mask_t phys_id_present_map;
1716         int apic;
1717         int i;
1718         unsigned char old_id;
1719         unsigned long flags;
1720
1721         /*
1722          * Don't check I/O APIC IDs for xAPIC systems.  They have
1723          * no meaning without the serial APIC bus.
1724          */
1725         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1726                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1727                 return;
1728         /*
1729          * This is broken; anything with a real cpu count has to
1730          * circumvent this idiocy regardless.
1731          */
1732         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1733
1734         /*
1735          * Set the IOAPIC ID to the value stored in the MPC table.
1736          */
1737         for (apic = 0; apic < nr_ioapics; apic++) {
1738
1739                 /* Read the register 0 value */
1740                 spin_lock_irqsave(&ioapic_lock, flags);
1741                 reg_00.raw = io_apic_read(apic, 0);
1742                 spin_unlock_irqrestore(&ioapic_lock, flags);
1743
1744                 old_id = mp_ioapics[apic].mpc_apicid;
1745
1746                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1747                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1748                                 apic, mp_ioapics[apic].mpc_apicid);
1749                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1750                                 reg_00.bits.ID);
1751                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1752                 }
1753
1754                 /*
1755                  * Sanity check, is the ID really free? Every APIC in a
1756                  * system must have a unique ID or we get lots of nice
1757                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1758                  */
1759                 if (check_apicid_used(phys_id_present_map,
1760                                         mp_ioapics[apic].mpc_apicid)) {
1761                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1762                                 apic, mp_ioapics[apic].mpc_apicid);
1763                         for (i = 0; i < get_physical_broadcast(); i++)
1764                                 if (!physid_isset(i, phys_id_present_map))
1765                                         break;
1766                         if (i >= get_physical_broadcast())
1767                                 panic("Max APIC ID exceeded!\n");
1768                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1769                                 i);
1770                         physid_set(i, phys_id_present_map);
1771                         mp_ioapics[apic].mpc_apicid = i;
1772                 } else {
1773                         physid_mask_t tmp;
1774                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1775                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1776                                         "phys_id_present_map\n",
1777                                         mp_ioapics[apic].mpc_apicid);
1778                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1779                 }
1780
1781
1782                 /*
1783                  * We need to adjust the IRQ routing table
1784                  * if the ID changed.
1785                  */
1786                 if (old_id != mp_ioapics[apic].mpc_apicid)
1787                         for (i = 0; i < mp_irq_entries; i++)
1788                                 if (mp_irqs[i].mpc_dstapic == old_id)
1789                                         mp_irqs[i].mpc_dstapic
1790                                                 = mp_ioapics[apic].mpc_apicid;
1791
1792                 /*
1793                  * Read the right value from the MPC table and
1794                  * write it into the ID register.
1795                  */
1796                 apic_printk(APIC_VERBOSE, KERN_INFO
1797                         "...changing IO-APIC physical APIC ID to %d ...",
1798                         mp_ioapics[apic].mpc_apicid);
1799
1800                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1801                 spin_lock_irqsave(&ioapic_lock, flags);
1802                 io_apic_write(apic, 0, reg_00.raw);
1803                 spin_unlock_irqrestore(&ioapic_lock, flags);
1804
1805                 /*
1806                  * Sanity check
1807                  */
1808                 spin_lock_irqsave(&ioapic_lock, flags);
1809                 reg_00.raw = io_apic_read(apic, 0);
1810                 spin_unlock_irqrestore(&ioapic_lock, flags);
1811                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1812                         printk("could not set ID!\n");
1813                 else
1814                         apic_printk(APIC_VERBOSE, " ok.\n");
1815         }
1816 }
1817 #else
1818 static void __init setup_ioapic_ids_from_mpc(void) { }
1819 #endif
1820
1821 int no_timer_check __initdata;
1822
1823 static int __init notimercheck(char *s)
1824 {
1825         no_timer_check = 1;
1826         return 1;
1827 }
1828 __setup("no_timer_check", notimercheck);
1829
1830 /*
1831  * There is a nasty bug in some older SMP boards, their mptable lies
1832  * about the timer IRQ. We do the following to work around the situation:
1833  *
1834  *      - timer IRQ defaults to IO-APIC IRQ
1835  *      - if this function detects that timer IRQs are defunct, then we fall
1836  *        back to ISA timer IRQs
1837  */
1838 static int __init timer_irq_works(void)
1839 {
1840         unsigned long t1 = jiffies;
1841         unsigned long flags;
1842
1843         if (no_timer_check)
1844                 return 1;
1845
1846         local_save_flags(flags);
1847         local_irq_enable();
1848         /* Let ten ticks pass... */
1849         mdelay((10 * 1000) / HZ);
1850         local_irq_restore(flags);
1851
1852         /*
1853          * Expect a few ticks at least, to be sure some possible
1854          * glue logic does not lock up after one or two first
1855          * ticks in a non-ExtINT mode.  Also the local APIC
1856          * might have cached one ExtINT interrupt.  Finally, at
1857          * least one tick may be lost due to delays.
1858          */
1859         if (time_after(jiffies, t1 + 4))
1860                 return 1;
1861
1862         return 0;
1863 }
1864
1865 /*
1866  * In the SMP+IOAPIC case it might happen that there are an unspecified
1867  * number of pending IRQ events unhandled. These cases are very rare,
1868  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1869  * better to do it this way as thus we do not have to be aware of
1870  * 'pending' interrupts in the IRQ path, except at this point.
1871  */
1872 /*
1873  * Edge triggered needs to resend any interrupt
1874  * that was delayed but this is now handled in the device
1875  * independent code.
1876  */
1877
1878 /*
1879  * Startup quirk:
1880  *
1881  * Starting up a edge-triggered IO-APIC interrupt is
1882  * nasty - we need to make sure that we get the edge.
1883  * If it is already asserted for some reason, we need
1884  * return 1 to indicate that is was pending.
1885  *
1886  * This is not complete - we should be able to fake
1887  * an edge even if it isn't on the 8259A...
1888  *
1889  * (We do this for level-triggered IRQs too - it cannot hurt.)
1890  */
1891 static unsigned int startup_ioapic_irq(unsigned int irq)
1892 {
1893         int was_pending = 0;
1894         unsigned long flags;
1895
1896         spin_lock_irqsave(&ioapic_lock, flags);
1897         if (irq < 16) {
1898                 disable_8259A_irq(irq);
1899                 if (i8259A_irq_pending(irq))
1900                         was_pending = 1;
1901         }
1902         __unmask_IO_APIC_irq(irq);
1903         spin_unlock_irqrestore(&ioapic_lock, flags);
1904
1905         return was_pending;
1906 }
1907
1908 static void ack_ioapic_irq(unsigned int irq)
1909 {
1910         move_native_irq(irq);
1911         ack_APIC_irq();
1912 }
1913
1914 static void ack_ioapic_quirk_irq(unsigned int irq)
1915 {
1916         unsigned long v;
1917         int i;
1918
1919         move_native_irq(irq);
1920 /*
1921  * It appears there is an erratum which affects at least version 0x11
1922  * of I/O APIC (that's the 82093AA and cores integrated into various
1923  * chipsets).  Under certain conditions a level-triggered interrupt is
1924  * erroneously delivered as edge-triggered one but the respective IRR
1925  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1926  * message but it will never arrive and further interrupts are blocked
1927  * from the source.  The exact reason is so far unknown, but the
1928  * phenomenon was observed when two consecutive interrupt requests
1929  * from a given source get delivered to the same CPU and the source is
1930  * temporarily disabled in between.
1931  *
1932  * A workaround is to simulate an EOI message manually.  We achieve it
1933  * by setting the trigger mode to edge and then to level when the edge
1934  * trigger mode gets detected in the TMR of a local APIC for a
1935  * level-triggered interrupt.  We mask the source for the time of the
1936  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1937  * The idea is from Manfred Spraul.  --macro
1938  */
1939         i = irq_vector[irq];
1940
1941         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1942
1943         ack_APIC_irq();
1944
1945         if (!(v & (1 << (i & 0x1f)))) {
1946                 atomic_inc(&irq_mis_count);
1947                 spin_lock(&ioapic_lock);
1948                 __mask_and_edge_IO_APIC_irq(irq);
1949                 __unmask_and_level_IO_APIC_irq(irq);
1950                 spin_unlock(&ioapic_lock);
1951         }
1952 }
1953
1954 static int ioapic_retrigger_irq(unsigned int irq)
1955 {
1956         send_IPI_self(irq_vector[irq]);
1957
1958         return 1;
1959 }
1960
1961 static struct irq_chip ioapic_chip __read_mostly = {
1962         .name           = "IO-APIC",
1963         .startup        = startup_ioapic_irq,
1964         .mask           = mask_IO_APIC_irq,
1965         .unmask         = unmask_IO_APIC_irq,
1966         .ack            = ack_ioapic_irq,
1967         .eoi            = ack_ioapic_quirk_irq,
1968 #ifdef CONFIG_SMP
1969         .set_affinity   = set_ioapic_affinity_irq,
1970 #endif
1971         .retrigger      = ioapic_retrigger_irq,
1972 };
1973
1974
1975 static inline void init_IO_APIC_traps(void)
1976 {
1977         int irq;
1978
1979         /*
1980          * NOTE! The local APIC isn't very good at handling
1981          * multiple interrupts at the same interrupt level.
1982          * As the interrupt level is determined by taking the
1983          * vector number and shifting that right by 4, we
1984          * want to spread these out a bit so that they don't
1985          * all fall in the same interrupt level.
1986          *
1987          * Also, we've got to be careful not to trash gate
1988          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1989          */
1990         for (irq = 0; irq < NR_IRQS ; irq++) {
1991                 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
1992                         /*
1993                          * Hmm.. We don't have an entry for this,
1994                          * so default to an old-fashioned 8259
1995                          * interrupt if we can..
1996                          */
1997                         if (irq < 16)
1998                                 make_8259A_irq(irq);
1999                         else
2000                                 /* Strange. Oh, well.. */
2001                                 irq_desc[irq].chip = &no_irq_chip;
2002                 }
2003         }
2004 }
2005
2006 /*
2007  * The local APIC irq-chip implementation:
2008  */
2009
2010 static void ack_apic(unsigned int irq)
2011 {
2012         ack_APIC_irq();
2013 }
2014
2015 static void mask_lapic_irq(unsigned int irq)
2016 {
2017         unsigned long v;
2018
2019         v = apic_read(APIC_LVT0);
2020         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2021 }
2022
2023 static void unmask_lapic_irq(unsigned int irq)
2024 {
2025         unsigned long v;
2026
2027         v = apic_read(APIC_LVT0);
2028         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2029 }
2030
2031 static struct irq_chip lapic_chip __read_mostly = {
2032         .name           = "local-APIC",
2033         .mask           = mask_lapic_irq,
2034         .unmask         = unmask_lapic_irq,
2035         .eoi            = ack_apic,
2036 };
2037
2038 static void __init setup_nmi(void)
2039 {
2040         /*
2041          * Dirty trick to enable the NMI watchdog ...
2042          * We put the 8259A master into AEOI mode and
2043          * unmask on all local APICs LVT0 as NMI.
2044          *
2045          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2046          * is from Maciej W. Rozycki - so we do not have to EOI from
2047          * the NMI handler or the timer interrupt.
2048          */
2049         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2050
2051         enable_NMI_through_LVT0();
2052
2053         apic_printk(APIC_VERBOSE, " done.\n");
2054 }
2055
2056 /*
2057  * This looks a bit hackish but it's about the only one way of sending
2058  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2059  * not support the ExtINT mode, unfortunately.  We need to send these
2060  * cycles as some i82489DX-based boards have glue logic that keeps the
2061  * 8259A interrupt line asserted until INTA.  --macro
2062  */
2063 static inline void __init unlock_ExtINT_logic(void)
2064 {
2065         int apic, pin, i;
2066         struct IO_APIC_route_entry entry0, entry1;
2067         unsigned char save_control, save_freq_select;
2068
2069         pin  = find_isa_irq_pin(8, mp_INT);
2070         if (pin == -1) {
2071                 WARN_ON_ONCE(1);
2072                 return;
2073         }
2074         apic = find_isa_irq_apic(8, mp_INT);
2075         if (apic == -1) {
2076                 WARN_ON_ONCE(1);
2077                 return;
2078         }
2079
2080         entry0 = ioapic_read_entry(apic, pin);
2081         clear_IO_APIC_pin(apic, pin);
2082
2083         memset(&entry1, 0, sizeof(entry1));
2084
2085         entry1.dest_mode = 0;                   /* physical delivery */
2086         entry1.mask = 0;                        /* unmask IRQ now */
2087         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2088         entry1.delivery_mode = dest_ExtINT;
2089         entry1.polarity = entry0.polarity;
2090         entry1.trigger = 0;
2091         entry1.vector = 0;
2092
2093         ioapic_write_entry(apic, pin, entry1);
2094
2095         save_control = CMOS_READ(RTC_CONTROL);
2096         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2097         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2098                    RTC_FREQ_SELECT);
2099         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2100
2101         i = 100;
2102         while (i-- > 0) {
2103                 mdelay(10);
2104                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2105                         i -= 10;
2106         }
2107
2108         CMOS_WRITE(save_control, RTC_CONTROL);
2109         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2110         clear_IO_APIC_pin(apic, pin);
2111
2112         ioapic_write_entry(apic, pin, entry0);
2113 }
2114
2115 /*
2116  * This code may look a bit paranoid, but it's supposed to cooperate with
2117  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2118  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2119  * fanatically on his truly buggy board.
2120  */
2121 static inline void __init check_timer(void)
2122 {
2123         int apic1, pin1, apic2, pin2;
2124         int no_pin1 = 0;
2125         int vector;
2126         unsigned int ver;
2127         unsigned long flags;
2128
2129         local_irq_save(flags);
2130
2131         ver = apic_read(APIC_LVR);
2132         ver = GET_APIC_VERSION(ver);
2133
2134         /*
2135          * get/set the timer IRQ vector:
2136          */
2137         disable_8259A_irq(0);
2138         vector = assign_irq_vector(0);
2139         set_intr_gate(vector, interrupt[0]);
2140
2141         /*
2142          * As IRQ0 is to be enabled in the 8259A, the virtual
2143          * wire has to be disabled in the local APIC.  Also
2144          * timer interrupts need to be acknowledged manually in
2145          * the 8259A for the i82489DX when using the NMI
2146          * watchdog as that APIC treats NMIs as level-triggered.
2147          * The AEOI mode will finish them in the 8259A
2148          * automatically.
2149          */
2150         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2151         init_8259A(1);
2152         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2153
2154         pin1  = find_isa_irq_pin(0, mp_INT);
2155         apic1 = find_isa_irq_apic(0, mp_INT);
2156         pin2  = ioapic_i8259.pin;
2157         apic2 = ioapic_i8259.apic;
2158
2159         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2160                 vector, apic1, pin1, apic2, pin2);
2161
2162         /*
2163          * Some BIOS writers are clueless and report the ExtINTA
2164          * I/O APIC input from the cascaded 8259A as the timer
2165          * interrupt input.  So just in case, if only one pin
2166          * was found above, try it both directly and through the
2167          * 8259A.
2168          */
2169         if (pin1 == -1) {
2170                 pin1 = pin2;
2171                 apic1 = apic2;
2172                 no_pin1 = 1;
2173         } else if (pin2 == -1) {
2174                 pin2 = pin1;
2175                 apic2 = apic1;
2176         }
2177
2178         if (pin1 != -1) {
2179                 /*
2180                  * Ok, does IRQ0 through the IOAPIC work?
2181                  */
2182                 if (no_pin1) {
2183                         add_pin_to_irq(0, apic1, pin1);
2184                         setup_timer_IRQ0_pin(apic1, pin1, vector);
2185                 }
2186                 unmask_IO_APIC_irq(0);
2187                 if (timer_irq_works()) {
2188                         if (nmi_watchdog == NMI_IO_APIC) {
2189                                 setup_nmi();
2190                                 enable_8259A_irq(0);
2191                         }
2192                         if (disable_timer_pin_1 > 0)
2193                                 clear_IO_APIC_pin(0, pin1);
2194                         goto out;
2195                 }
2196                 clear_IO_APIC_pin(apic1, pin1);
2197                 if (!no_pin1)
2198                         printk(KERN_ERR "..MP-BIOS bug: "
2199                                "8254 timer not connected to IO-APIC\n");
2200
2201                 printk(KERN_INFO "...trying to set up timer (IRQ0) "
2202                        "through the 8259A ... ");
2203                 printk("\n..... (found pin %d) ...", pin2);
2204                 /*
2205                  * legacy devices should be connected to IO APIC #0
2206                  */
2207                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2208                 setup_timer_IRQ0_pin(apic2, pin2, vector);
2209                 unmask_IO_APIC_irq(0);
2210                 enable_8259A_irq(0);
2211                 if (timer_irq_works()) {
2212                         printk("works.\n");
2213                         timer_through_8259 = 1;
2214                         if (nmi_watchdog == NMI_IO_APIC) {
2215                                 disable_8259A_irq(0);
2216                                 setup_nmi();
2217                                 enable_8259A_irq(0);
2218                         }
2219                         goto out;
2220                 }
2221                 /*
2222                  * Cleanup, just in case ...
2223                  */
2224                 disable_8259A_irq(0);
2225                 clear_IO_APIC_pin(apic2, pin2);
2226                 printk(" failed.\n");
2227         }
2228
2229         if (nmi_watchdog == NMI_IO_APIC) {
2230                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2231                 nmi_watchdog = NMI_NONE;
2232         }
2233         timer_ack = 0;
2234
2235         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2236
2237         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2238                                       "fasteoi");
2239         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2240         enable_8259A_irq(0);
2241
2242         if (timer_irq_works()) {
2243                 printk(" works.\n");
2244                 goto out;
2245         }
2246         disable_8259A_irq(0);
2247         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2248         printk(" failed.\n");
2249
2250         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2251
2252         init_8259A(0);
2253         make_8259A_irq(0);
2254         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2255
2256         unlock_ExtINT_logic();
2257
2258         if (timer_irq_works()) {
2259                 printk(" works.\n");
2260                 goto out;
2261         }
2262         printk(" failed :(.\n");
2263         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2264                 "report.  Then try booting with the 'noapic' option");
2265 out:
2266         local_irq_restore(flags);
2267 }
2268
2269 /*
2270  *
2271  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2272  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2273  *   Linux doesn't really care, as it's not actually used
2274  *   for any interrupt handling anyway.
2275  */
2276 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2277
2278 void __init setup_IO_APIC(void)
2279 {
2280         int i;
2281
2282         /* Reserve all the system vectors. */
2283         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2284                 set_bit(i, used_vectors);
2285
2286         enable_IO_APIC();
2287
2288         if (acpi_ioapic)
2289                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2290         else
2291                 io_apic_irqs = ~PIC_IRQS;
2292
2293         printk("ENABLING IO-APIC IRQs\n");
2294
2295         /*
2296          * Set up IO-APIC IRQ routing.
2297          */
2298         if (!acpi_ioapic)
2299                 setup_ioapic_ids_from_mpc();
2300         sync_Arb_IDs();
2301         setup_IO_APIC_irqs();
2302         init_IO_APIC_traps();
2303         check_timer();
2304         if (!acpi_ioapic)
2305                 print_IO_APIC();
2306 }
2307
2308 /*
2309  *      Called after all the initialization is done. If we didnt find any
2310  *      APIC bugs then we can allow the modify fast path
2311  */
2312
2313 static int __init io_apic_bug_finalize(void)
2314 {
2315         if (sis_apic_bug == -1)
2316                 sis_apic_bug = 0;
2317         return 0;
2318 }
2319
2320 late_initcall(io_apic_bug_finalize);
2321
2322 struct sysfs_ioapic_data {
2323         struct sys_device dev;
2324         struct IO_APIC_route_entry entry[0];
2325 };
2326 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2327
2328 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2329 {
2330         struct IO_APIC_route_entry *entry;
2331         struct sysfs_ioapic_data *data;
2332         int i;
2333
2334         data = container_of(dev, struct sysfs_ioapic_data, dev);
2335         entry = data->entry;
2336         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2337                 entry[i] = ioapic_read_entry(dev->id, i);
2338
2339         return 0;
2340 }
2341
2342 static int ioapic_resume(struct sys_device *dev)
2343 {
2344         struct IO_APIC_route_entry *entry;
2345         struct sysfs_ioapic_data *data;
2346         unsigned long flags;
2347         union IO_APIC_reg_00 reg_00;
2348         int i;
2349
2350         data = container_of(dev, struct sysfs_ioapic_data, dev);
2351         entry = data->entry;
2352
2353         spin_lock_irqsave(&ioapic_lock, flags);
2354         reg_00.raw = io_apic_read(dev->id, 0);
2355         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2356                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2357                 io_apic_write(dev->id, 0, reg_00.raw);
2358         }
2359         spin_unlock_irqrestore(&ioapic_lock, flags);
2360         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2361                 ioapic_write_entry(dev->id, i, entry[i]);
2362
2363         return 0;
2364 }
2365
2366 static struct sysdev_class ioapic_sysdev_class = {
2367         .name = "ioapic",
2368         .suspend = ioapic_suspend,
2369         .resume = ioapic_resume,
2370 };
2371
2372 static int __init ioapic_init_sysfs(void)
2373 {
2374         struct sys_device *dev;
2375         int i, size, error = 0;
2376
2377         error = sysdev_class_register(&ioapic_sysdev_class);
2378         if (error)
2379                 return error;
2380
2381         for (i = 0; i < nr_ioapics; i++) {
2382                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2383                         * sizeof(struct IO_APIC_route_entry);
2384                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2385                 if (!mp_ioapic_data[i]) {
2386                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2387                         continue;
2388                 }
2389                 dev = &mp_ioapic_data[i]->dev;
2390                 dev->id = i;
2391                 dev->cls = &ioapic_sysdev_class;
2392                 error = sysdev_register(dev);
2393                 if (error) {
2394                         kfree(mp_ioapic_data[i]);
2395                         mp_ioapic_data[i] = NULL;
2396                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2397                         continue;
2398                 }
2399         }
2400
2401         return 0;
2402 }
2403
2404 device_initcall(ioapic_init_sysfs);
2405
2406 /*
2407  * Dynamic irq allocate and deallocation
2408  */
2409 int create_irq(void)
2410 {
2411         /* Allocate an unused irq */
2412         int irq, new, vector = 0;
2413         unsigned long flags;
2414
2415         irq = -ENOSPC;
2416         spin_lock_irqsave(&vector_lock, flags);
2417         for (new = (NR_IRQS - 1); new >= 0; new--) {
2418                 if (platform_legacy_irq(new))
2419                         continue;
2420                 if (irq_vector[new] != 0)
2421                         continue;
2422                 vector = __assign_irq_vector(new);
2423                 if (likely(vector > 0))
2424                         irq = new;
2425                 break;
2426         }
2427         spin_unlock_irqrestore(&vector_lock, flags);
2428
2429         if (irq >= 0) {
2430                 set_intr_gate(vector, interrupt[irq]);
2431                 dynamic_irq_init(irq);
2432         }
2433         return irq;
2434 }
2435
2436 void destroy_irq(unsigned int irq)
2437 {
2438         unsigned long flags;
2439
2440         dynamic_irq_cleanup(irq);
2441
2442         spin_lock_irqsave(&vector_lock, flags);
2443         clear_bit(irq_vector[irq], used_vectors);
2444         irq_vector[irq] = 0;
2445         spin_unlock_irqrestore(&vector_lock, flags);
2446 }
2447
2448 /*
2449  * MSI message composition
2450  */
2451 #ifdef CONFIG_PCI_MSI
2452 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2453 {
2454         int vector;
2455         unsigned dest;
2456
2457         vector = assign_irq_vector(irq);
2458         if (vector >= 0) {
2459                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2460
2461                 msg->address_hi = MSI_ADDR_BASE_HI;
2462                 msg->address_lo =
2463                         MSI_ADDR_BASE_LO |
2464                         ((INT_DEST_MODE == 0) ?
2465 MSI_ADDR_DEST_MODE_PHYSICAL:
2466                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2467                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2468                                 MSI_ADDR_REDIRECTION_CPU:
2469                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2470                         MSI_ADDR_DEST_ID(dest);
2471
2472                 msg->data =
2473                         MSI_DATA_TRIGGER_EDGE |
2474                         MSI_DATA_LEVEL_ASSERT |
2475                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2476 MSI_DATA_DELIVERY_FIXED:
2477                                 MSI_DATA_DELIVERY_LOWPRI) |
2478                         MSI_DATA_VECTOR(vector);
2479         }
2480         return vector;
2481 }
2482
2483 #ifdef CONFIG_SMP
2484 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2485 {
2486         struct msi_msg msg;
2487         unsigned int dest;
2488         cpumask_t tmp;
2489         int vector;
2490
2491         cpus_and(tmp, mask, cpu_online_map);
2492         if (cpus_empty(tmp))
2493                 tmp = TARGET_CPUS;
2494
2495         vector = assign_irq_vector(irq);
2496         if (vector < 0)
2497                 return;
2498
2499         dest = cpu_mask_to_apicid(mask);
2500
2501         read_msi_msg(irq, &msg);
2502
2503         msg.data &= ~MSI_DATA_VECTOR_MASK;
2504         msg.data |= MSI_DATA_VECTOR(vector);
2505         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2506         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2507
2508         write_msi_msg(irq, &msg);
2509         irq_desc[irq].affinity = mask;
2510 }
2511 #endif /* CONFIG_SMP */
2512
2513 /*
2514  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2515  * which implement the MSI or MSI-X Capability Structure.
2516  */
2517 static struct irq_chip msi_chip = {
2518         .name           = "PCI-MSI",
2519         .unmask         = unmask_msi_irq,
2520         .mask           = mask_msi_irq,
2521         .ack            = ack_ioapic_irq,
2522 #ifdef CONFIG_SMP
2523         .set_affinity   = set_msi_irq_affinity,
2524 #endif
2525         .retrigger      = ioapic_retrigger_irq,
2526 };
2527
2528 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2529 {
2530         struct msi_msg msg;
2531         int irq, ret;
2532         irq = create_irq();
2533         if (irq < 0)
2534                 return irq;
2535
2536         ret = msi_compose_msg(dev, irq, &msg);
2537         if (ret < 0) {
2538                 destroy_irq(irq);
2539                 return ret;
2540         }
2541
2542         set_irq_msi(irq, desc);
2543         write_msi_msg(irq, &msg);
2544
2545         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2546                                       "edge");
2547
2548         return 0;
2549 }
2550
2551 void arch_teardown_msi_irq(unsigned int irq)
2552 {
2553         destroy_irq(irq);
2554 }
2555
2556 #endif /* CONFIG_PCI_MSI */
2557
2558 /*
2559  * Hypertransport interrupt support
2560  */
2561 #ifdef CONFIG_HT_IRQ
2562
2563 #ifdef CONFIG_SMP
2564
2565 static void target_ht_irq(unsigned int irq, unsigned int dest)
2566 {
2567         struct ht_irq_msg msg;
2568         fetch_ht_irq_msg(irq, &msg);
2569
2570         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2571         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2572
2573         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2574         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2575
2576         write_ht_irq_msg(irq, &msg);
2577 }
2578
2579 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2580 {
2581         unsigned int dest;
2582         cpumask_t tmp;
2583
2584         cpus_and(tmp, mask, cpu_online_map);
2585         if (cpus_empty(tmp))
2586                 tmp = TARGET_CPUS;
2587
2588         cpus_and(mask, tmp, CPU_MASK_ALL);
2589
2590         dest = cpu_mask_to_apicid(mask);
2591
2592         target_ht_irq(irq, dest);
2593         irq_desc[irq].affinity = mask;
2594 }
2595 #endif
2596
2597 static struct irq_chip ht_irq_chip = {
2598         .name           = "PCI-HT",
2599         .mask           = mask_ht_irq,
2600         .unmask         = unmask_ht_irq,
2601         .ack            = ack_ioapic_irq,
2602 #ifdef CONFIG_SMP
2603         .set_affinity   = set_ht_irq_affinity,
2604 #endif
2605         .retrigger      = ioapic_retrigger_irq,
2606 };
2607
2608 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2609 {
2610         int vector;
2611
2612         vector = assign_irq_vector(irq);
2613         if (vector >= 0) {
2614                 struct ht_irq_msg msg;
2615                 unsigned dest;
2616                 cpumask_t tmp;
2617
2618                 cpus_clear(tmp);
2619                 cpu_set(vector >> 8, tmp);
2620                 dest = cpu_mask_to_apicid(tmp);
2621
2622                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2623
2624                 msg.address_lo =
2625                         HT_IRQ_LOW_BASE |
2626                         HT_IRQ_LOW_DEST_ID(dest) |
2627                         HT_IRQ_LOW_VECTOR(vector) |
2628                         ((INT_DEST_MODE == 0) ?
2629                                 HT_IRQ_LOW_DM_PHYSICAL :
2630                                 HT_IRQ_LOW_DM_LOGICAL) |
2631                         HT_IRQ_LOW_RQEOI_EDGE |
2632                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2633                                 HT_IRQ_LOW_MT_FIXED :
2634                                 HT_IRQ_LOW_MT_ARBITRATED) |
2635                         HT_IRQ_LOW_IRQ_MASKED;
2636
2637                 write_ht_irq_msg(irq, &msg);
2638
2639                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2640                                               handle_edge_irq, "edge");
2641         }
2642         return vector;
2643 }
2644 #endif /* CONFIG_HT_IRQ */
2645
2646 /* --------------------------------------------------------------------------
2647                         ACPI-based IOAPIC Configuration
2648    -------------------------------------------------------------------------- */
2649
2650 #ifdef CONFIG_ACPI
2651
2652 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2653 {
2654         union IO_APIC_reg_00 reg_00;
2655         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2656         physid_mask_t tmp;
2657         unsigned long flags;
2658         int i = 0;
2659
2660         /*
2661          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2662          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2663          * supports up to 16 on one shared APIC bus.
2664          *
2665          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2666          *      advantage of new APIC bus architecture.
2667          */
2668
2669         if (physids_empty(apic_id_map))
2670                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2671
2672         spin_lock_irqsave(&ioapic_lock, flags);
2673         reg_00.raw = io_apic_read(ioapic, 0);
2674         spin_unlock_irqrestore(&ioapic_lock, flags);
2675
2676         if (apic_id >= get_physical_broadcast()) {
2677                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2678                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2679                 apic_id = reg_00.bits.ID;
2680         }
2681
2682         /*
2683          * Every APIC in a system must have a unique ID or we get lots of nice
2684          * 'stuck on smp_invalidate_needed IPI wait' messages.
2685          */
2686         if (check_apicid_used(apic_id_map, apic_id)) {
2687
2688                 for (i = 0; i < get_physical_broadcast(); i++) {
2689                         if (!check_apicid_used(apic_id_map, i))
2690                                 break;
2691                 }
2692
2693                 if (i == get_physical_broadcast())
2694                         panic("Max apic_id exceeded!\n");
2695
2696                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2697                         "trying %d\n", ioapic, apic_id, i);
2698
2699                 apic_id = i;
2700         }
2701
2702         tmp = apicid_to_cpu_present(apic_id);
2703         physids_or(apic_id_map, apic_id_map, tmp);
2704
2705         if (reg_00.bits.ID != apic_id) {
2706                 reg_00.bits.ID = apic_id;
2707
2708                 spin_lock_irqsave(&ioapic_lock, flags);
2709                 io_apic_write(ioapic, 0, reg_00.raw);
2710                 reg_00.raw = io_apic_read(ioapic, 0);
2711                 spin_unlock_irqrestore(&ioapic_lock, flags);
2712
2713                 /* Sanity check */
2714                 if (reg_00.bits.ID != apic_id) {
2715                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2716                         return -1;
2717                 }
2718         }
2719
2720         apic_printk(APIC_VERBOSE, KERN_INFO
2721                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2722
2723         return apic_id;
2724 }
2725
2726
2727 int __init io_apic_get_version(int ioapic)
2728 {
2729         union IO_APIC_reg_01    reg_01;
2730         unsigned long flags;
2731
2732         spin_lock_irqsave(&ioapic_lock, flags);
2733         reg_01.raw = io_apic_read(ioapic, 1);
2734         spin_unlock_irqrestore(&ioapic_lock, flags);
2735
2736         return reg_01.bits.version;
2737 }
2738
2739
2740 int __init io_apic_get_redir_entries(int ioapic)
2741 {
2742         union IO_APIC_reg_01    reg_01;
2743         unsigned long flags;
2744
2745         spin_lock_irqsave(&ioapic_lock, flags);
2746         reg_01.raw = io_apic_read(ioapic, 1);
2747         spin_unlock_irqrestore(&ioapic_lock, flags);
2748
2749         return reg_01.bits.entries;
2750 }
2751
2752
2753 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2754 {
2755         struct IO_APIC_route_entry entry;
2756
2757         if (!IO_APIC_IRQ(irq)) {
2758                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2759                         ioapic);
2760                 return -EINVAL;
2761         }
2762
2763         /*
2764          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2765          * Note that we mask (disable) IRQs now -- these get enabled when the
2766          * corresponding device driver registers for this IRQ.
2767          */
2768
2769         memset(&entry, 0, sizeof(entry));
2770
2771         entry.delivery_mode = INT_DELIVERY_MODE;
2772         entry.dest_mode = INT_DEST_MODE;
2773         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2774         entry.trigger = edge_level;
2775         entry.polarity = active_high_low;
2776         entry.mask  = 1;
2777
2778         /*
2779          * IRQs < 16 are already in the irq_2_pin[] map
2780          */
2781         if (irq >= 16)
2782                 add_pin_to_irq(irq, ioapic, pin);
2783
2784         entry.vector = assign_irq_vector(irq);
2785
2786         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2787                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2788                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2789                 edge_level, active_high_low);
2790
2791         ioapic_register_intr(irq, entry.vector, edge_level);
2792
2793         if (!ioapic && (irq < 16))
2794                 disable_8259A_irq(irq);
2795
2796         ioapic_write_entry(ioapic, pin, entry);
2797
2798         return 0;
2799 }
2800
2801 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2802 {
2803         int i;
2804
2805         if (skip_ioapic_setup)
2806                 return -1;
2807
2808         for (i = 0; i < mp_irq_entries; i++)
2809                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2810                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2811                         break;
2812         if (i >= mp_irq_entries)
2813                 return -1;
2814
2815         *trigger = irq_trigger(i);
2816         *polarity = irq_polarity(i);
2817         return 0;
2818 }
2819
2820 #endif /* CONFIG_ACPI */
2821
2822 static int __init parse_disable_timer_pin_1(char *arg)
2823 {
2824         disable_timer_pin_1 = 1;
2825         return 0;
2826 }
2827 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2828
2829 static int __init parse_enable_timer_pin_1(char *arg)
2830 {
2831         disable_timer_pin_1 = -1;
2832         return 0;
2833 }
2834 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2835
2836 static int __init parse_noapic(char *arg)
2837 {
2838         /* disable IO-APIC */
2839         disable_ioapic_setup();
2840         return 0;
2841 }
2842 early_param("noapic", parse_noapic);