2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count;
60 u8 move_in_progress : 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
83 static int assign_irq_vector(int irq, cpumask_t mask);
85 #define __apicdebuginit __init
87 int sis_apic_bug; /* not actually supported, dummy for compile */
89 static int no_timer_check;
91 static int disable_timer_pin_1 __initdata;
93 int timer_over_8254 __initdata = 1;
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
102 * # of IRQ routing registers
104 int nr_ioapic_registers[MAX_IO_APICS];
107 * Rough estimation of how many shared IRQs there are, can
108 * be changed anytime.
110 #define MAX_PLUS_SHARED_IRQS NR_IRQS
111 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
114 * This is performance-critical, we want to do it O(1)
116 * the indexing order of this array favors 1:1 mappings
117 * between pins and IRQs.
120 static struct irq_pin_list {
121 short apic, pin, next;
122 } irq_2_pin[PIN_MAP_SIZE];
126 unsigned int unused[3];
130 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
132 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
133 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
136 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
138 struct io_apic __iomem *io_apic = io_apic_base(apic);
139 writel(reg, &io_apic->index);
140 return readl(&io_apic->data);
143 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
145 struct io_apic __iomem *io_apic = io_apic_base(apic);
146 writel(reg, &io_apic->index);
147 writel(value, &io_apic->data);
151 * Re-write a value: to be used for read-modify-write
152 * cycles where the read already set up the index register.
154 static inline void io_apic_modify(unsigned int apic, unsigned int value)
156 struct io_apic __iomem *io_apic = io_apic_base(apic);
157 writel(value, &io_apic->data);
160 static int io_apic_level_ack_pending(unsigned int irq)
162 struct irq_pin_list *entry;
166 spin_lock_irqsave(&ioapic_lock, flags);
167 entry = irq_2_pin + irq;
175 reg = io_apic_read(entry->apic, 0x10 + pin*2);
176 /* Is the remote IRR bit set? */
177 pending |= (reg >> 14) & 1;
180 entry = irq_2_pin + entry->next;
182 spin_unlock_irqrestore(&ioapic_lock, flags);
187 * Synchronize the IO-APIC and the CPU by doing
188 * a dummy read from the IO-APIC
190 static inline void io_apic_sync(unsigned int apic)
192 struct io_apic __iomem *io_apic = io_apic_base(apic);
193 readl(&io_apic->data);
196 #define __DO_ACTION(R, ACTION, FINAL) \
200 struct irq_pin_list *entry = irq_2_pin + irq; \
202 BUG_ON(irq >= NR_IRQS); \
208 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
210 io_apic_modify(entry->apic, reg); \
214 entry = irq_2_pin + entry->next; \
219 struct { u32 w1, w2; };
220 struct IO_APIC_route_entry entry;
223 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
225 union entry_union eu;
227 spin_lock_irqsave(&ioapic_lock, flags);
228 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
229 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
230 spin_unlock_irqrestore(&ioapic_lock, flags);
235 * When we write a new IO APIC routing entry, we need to write the high
236 * word first! If the mask bit in the low word is clear, we will enable
237 * the interrupt, and we need to make sure the entry is fully populated
238 * before that happens.
241 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
243 union entry_union eu;
245 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
246 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
249 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
252 spin_lock_irqsave(&ioapic_lock, flags);
253 __ioapic_write_entry(apic, pin, e);
254 spin_unlock_irqrestore(&ioapic_lock, flags);
258 * When we mask an IO APIC routing entry, we need to write the low
259 * word first, in order to set the mask bit before we change the
262 static void ioapic_mask_entry(int apic, int pin)
265 union entry_union eu = { .entry.mask = 1 };
267 spin_lock_irqsave(&ioapic_lock, flags);
268 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
269 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
270 spin_unlock_irqrestore(&ioapic_lock, flags);
274 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
277 struct irq_pin_list *entry = irq_2_pin + irq;
279 BUG_ON(irq >= NR_IRQS);
286 io_apic_write(apic, 0x11 + pin*2, dest);
287 reg = io_apic_read(apic, 0x10 + pin*2);
290 io_apic_modify(apic, reg);
293 entry = irq_2_pin + entry->next;
297 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
299 struct irq_cfg *cfg = irq_cfg + irq;
304 cpus_and(tmp, mask, cpu_online_map);
308 if (assign_irq_vector(irq, mask))
311 cpus_and(tmp, cfg->domain, mask);
312 dest = cpu_mask_to_apicid(tmp);
315 * Only the high 8 bits are valid.
317 dest = SET_APIC_LOGICAL_ID(dest);
319 spin_lock_irqsave(&ioapic_lock, flags);
320 __target_IO_APIC_irq(irq, dest, cfg->vector);
321 irq_desc[irq].affinity = mask;
322 spin_unlock_irqrestore(&ioapic_lock, flags);
327 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
328 * shared ISA-space IRQs, so we have to support them. We are super
329 * fast in the common case, and fast for shared ISA-space IRQs.
331 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
333 static int first_free_entry = NR_IRQS;
334 struct irq_pin_list *entry = irq_2_pin + irq;
336 BUG_ON(irq >= NR_IRQS);
338 entry = irq_2_pin + entry->next;
340 if (entry->pin != -1) {
341 entry->next = first_free_entry;
342 entry = irq_2_pin + entry->next;
343 if (++first_free_entry >= PIN_MAP_SIZE)
344 panic("io_apic.c: ran out of irq_2_pin entries!");
351 #define DO_ACTION(name,R,ACTION, FINAL) \
353 static void name##_IO_APIC_irq (unsigned int irq) \
354 __DO_ACTION(R, ACTION, FINAL)
356 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
358 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
361 static void mask_IO_APIC_irq (unsigned int irq)
365 spin_lock_irqsave(&ioapic_lock, flags);
366 __mask_IO_APIC_irq(irq);
367 spin_unlock_irqrestore(&ioapic_lock, flags);
370 static void unmask_IO_APIC_irq (unsigned int irq)
374 spin_lock_irqsave(&ioapic_lock, flags);
375 __unmask_IO_APIC_irq(irq);
376 spin_unlock_irqrestore(&ioapic_lock, flags);
379 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
381 struct IO_APIC_route_entry entry;
383 /* Check delivery_mode to be sure we're not clearing an SMI pin */
384 entry = ioapic_read_entry(apic, pin);
385 if (entry.delivery_mode == dest_SMI)
388 * Disable it in the IO-APIC irq-routing table:
390 ioapic_mask_entry(apic, pin);
393 static void clear_IO_APIC (void)
397 for (apic = 0; apic < nr_ioapics; apic++)
398 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
399 clear_IO_APIC_pin(apic, pin);
402 int skip_ioapic_setup;
405 static int __init parse_noapic(char *str)
407 disable_ioapic_setup();
410 early_param("noapic", parse_noapic);
412 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
413 static int __init disable_timer_pin_setup(char *arg)
415 disable_timer_pin_1 = 1;
418 __setup("disable_timer_pin_1", disable_timer_pin_setup);
420 static int __init setup_disable_8254_timer(char *s)
422 timer_over_8254 = -1;
425 static int __init setup_enable_8254_timer(char *s)
431 __setup("disable_8254_timer", setup_disable_8254_timer);
432 __setup("enable_8254_timer", setup_enable_8254_timer);
436 * Find the IRQ entry number of a certain pin.
438 static int find_irq_entry(int apic, int pin, int type)
442 for (i = 0; i < mp_irq_entries; i++)
443 if (mp_irqs[i].mpc_irqtype == type &&
444 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
445 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
446 mp_irqs[i].mpc_dstirq == pin)
453 * Find the pin to which IRQ[irq] (ISA) is connected
455 static int __init find_isa_irq_pin(int irq, int type)
459 for (i = 0; i < mp_irq_entries; i++) {
460 int lbus = mp_irqs[i].mpc_srcbus;
462 if (test_bit(lbus, mp_bus_not_pci) &&
463 (mp_irqs[i].mpc_irqtype == type) &&
464 (mp_irqs[i].mpc_srcbusirq == irq))
466 return mp_irqs[i].mpc_dstirq;
471 static int __init find_isa_irq_apic(int irq, int type)
475 for (i = 0; i < mp_irq_entries; i++) {
476 int lbus = mp_irqs[i].mpc_srcbus;
478 if (test_bit(lbus, mp_bus_not_pci) &&
479 (mp_irqs[i].mpc_irqtype == type) &&
480 (mp_irqs[i].mpc_srcbusirq == irq))
483 if (i < mp_irq_entries) {
485 for(apic = 0; apic < nr_ioapics; apic++) {
486 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
495 * Find a specific PCI IRQ entry.
496 * Not an __init, possibly needed by modules
498 static int pin_2_irq(int idx, int apic, int pin);
500 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
502 int apic, i, best_guess = -1;
504 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
506 if (mp_bus_id_to_pci_bus[bus] == -1) {
507 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
510 for (i = 0; i < mp_irq_entries; i++) {
511 int lbus = mp_irqs[i].mpc_srcbus;
513 for (apic = 0; apic < nr_ioapics; apic++)
514 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
515 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
518 if (!test_bit(lbus, mp_bus_not_pci) &&
519 !mp_irqs[i].mpc_irqtype &&
521 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
522 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
524 if (!(apic || IO_APIC_IRQ(irq)))
527 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
530 * Use the first all-but-pin matching entry as a
531 * best-guess fuzzy result for broken mptables.
537 BUG_ON(best_guess >= NR_IRQS);
541 /* ISA interrupts are always polarity zero edge triggered,
542 * when listed as conforming in the MP table. */
544 #define default_ISA_trigger(idx) (0)
545 #define default_ISA_polarity(idx) (0)
547 /* PCI interrupts are always polarity one level triggered,
548 * when listed as conforming in the MP table. */
550 #define default_PCI_trigger(idx) (1)
551 #define default_PCI_polarity(idx) (1)
553 static int MPBIOS_polarity(int idx)
555 int bus = mp_irqs[idx].mpc_srcbus;
559 * Determine IRQ line polarity (high active or low active):
561 switch (mp_irqs[idx].mpc_irqflag & 3)
563 case 0: /* conforms, ie. bus-type dependent polarity */
564 if (test_bit(bus, mp_bus_not_pci))
565 polarity = default_ISA_polarity(idx);
567 polarity = default_PCI_polarity(idx);
569 case 1: /* high active */
574 case 2: /* reserved */
576 printk(KERN_WARNING "broken BIOS!!\n");
580 case 3: /* low active */
585 default: /* invalid */
587 printk(KERN_WARNING "broken BIOS!!\n");
595 static int MPBIOS_trigger(int idx)
597 int bus = mp_irqs[idx].mpc_srcbus;
601 * Determine IRQ trigger mode (edge or level sensitive):
603 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
605 case 0: /* conforms, ie. bus-type dependent */
606 if (test_bit(bus, mp_bus_not_pci))
607 trigger = default_ISA_trigger(idx);
609 trigger = default_PCI_trigger(idx);
616 case 2: /* reserved */
618 printk(KERN_WARNING "broken BIOS!!\n");
627 default: /* invalid */
629 printk(KERN_WARNING "broken BIOS!!\n");
637 static inline int irq_polarity(int idx)
639 return MPBIOS_polarity(idx);
642 static inline int irq_trigger(int idx)
644 return MPBIOS_trigger(idx);
647 static int pin_2_irq(int idx, int apic, int pin)
650 int bus = mp_irqs[idx].mpc_srcbus;
653 * Debugging check, we are in big trouble if this message pops up!
655 if (mp_irqs[idx].mpc_dstirq != pin)
656 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
658 if (test_bit(bus, mp_bus_not_pci)) {
659 irq = mp_irqs[idx].mpc_srcbusirq;
662 * PCI IRQs are mapped in order
666 irq += nr_ioapic_registers[i++];
669 BUG_ON(irq >= NR_IRQS);
673 static int __assign_irq_vector(int irq, cpumask_t mask)
676 * NOTE! The local APIC isn't very good at handling
677 * multiple interrupts at the same interrupt level.
678 * As the interrupt level is determined by taking the
679 * vector number and shifting that right by 4, we
680 * want to spread these out a bit so that they don't
681 * all fall in the same interrupt level.
683 * Also, we've got to be careful not to trash gate
684 * 0x80, because int 0x80 is hm, kind of importantish. ;)
686 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
687 unsigned int old_vector;
691 BUG_ON((unsigned)irq >= NR_IRQS);
694 /* Only try and allocate irqs on cpus that are present */
695 cpus_and(mask, mask, cpu_online_map);
697 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
700 old_vector = cfg->vector;
703 cpus_and(tmp, cfg->domain, mask);
704 if (!cpus_empty(tmp))
708 for_each_cpu_mask(cpu, mask) {
709 cpumask_t domain, new_mask;
713 domain = vector_allocation_domain(cpu);
714 cpus_and(new_mask, domain, cpu_online_map);
716 vector = current_vector;
717 offset = current_offset;
720 if (vector >= FIRST_SYSTEM_VECTOR) {
721 /* If we run out of vectors on large boxen, must share them. */
722 offset = (offset + 1) % 8;
723 vector = FIRST_DEVICE_VECTOR + offset;
725 if (unlikely(current_vector == vector))
727 if (vector == IA32_SYSCALL_VECTOR)
729 for_each_cpu_mask(new_cpu, new_mask)
730 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
733 current_vector = vector;
734 current_offset = offset;
736 cfg->move_in_progress = 1;
737 cfg->old_domain = cfg->domain;
739 for_each_cpu_mask(new_cpu, new_mask)
740 per_cpu(vector_irq, new_cpu)[vector] = irq;
741 cfg->vector = vector;
742 cfg->domain = domain;
748 static int assign_irq_vector(int irq, cpumask_t mask)
753 spin_lock_irqsave(&vector_lock, flags);
754 err = __assign_irq_vector(irq, mask);
755 spin_unlock_irqrestore(&vector_lock, flags);
759 static void __clear_irq_vector(int irq)
765 BUG_ON((unsigned)irq >= NR_IRQS);
767 BUG_ON(!cfg->vector);
769 vector = cfg->vector;
770 cpus_and(mask, cfg->domain, cpu_online_map);
771 for_each_cpu_mask(cpu, mask)
772 per_cpu(vector_irq, cpu)[vector] = -1;
775 cfg->domain = CPU_MASK_NONE;
778 void __setup_vector_irq(int cpu)
780 /* Initialize vector_irq on a new cpu */
781 /* This function must be called with vector_lock held */
784 /* Mark the inuse vectors */
785 for (irq = 0; irq < NR_IRQS; ++irq) {
786 if (!cpu_isset(cpu, irq_cfg[irq].domain))
788 vector = irq_cfg[irq].vector;
789 per_cpu(vector_irq, cpu)[vector] = irq;
791 /* Mark the free vectors */
792 for (vector = 0; vector < NR_VECTORS; ++vector) {
793 irq = per_cpu(vector_irq, cpu)[vector];
796 if (!cpu_isset(cpu, irq_cfg[irq].domain))
797 per_cpu(vector_irq, cpu)[vector] = -1;
802 static struct irq_chip ioapic_chip;
804 static void ioapic_register_intr(int irq, unsigned long trigger)
807 irq_desc[irq].status |= IRQ_LEVEL;
808 set_irq_chip_and_handler_name(irq, &ioapic_chip,
809 handle_fasteoi_irq, "fasteoi");
811 irq_desc[irq].status &= ~IRQ_LEVEL;
812 set_irq_chip_and_handler_name(irq, &ioapic_chip,
813 handle_edge_irq, "edge");
817 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
818 int trigger, int polarity)
820 struct irq_cfg *cfg = irq_cfg + irq;
821 struct IO_APIC_route_entry entry;
824 if (!IO_APIC_IRQ(irq))
828 if (assign_irq_vector(irq, mask))
831 cpus_and(mask, cfg->domain, mask);
833 apic_printk(APIC_VERBOSE,KERN_DEBUG
834 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
835 "IRQ %d Mode:%i Active:%i)\n",
836 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
837 irq, trigger, polarity);
840 * add it to the IO-APIC irq-routing table:
842 memset(&entry,0,sizeof(entry));
844 entry.delivery_mode = INT_DELIVERY_MODE;
845 entry.dest_mode = INT_DEST_MODE;
846 entry.dest = cpu_mask_to_apicid(mask);
847 entry.mask = 0; /* enable IRQ */
848 entry.trigger = trigger;
849 entry.polarity = polarity;
850 entry.vector = cfg->vector;
852 /* Mask level triggered irqs.
853 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
858 ioapic_register_intr(irq, trigger);
860 disable_8259A_irq(irq);
862 ioapic_write_entry(apic, pin, entry);
865 static void __init setup_IO_APIC_irqs(void)
867 int apic, pin, idx, irq, first_notcon = 1;
869 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
871 for (apic = 0; apic < nr_ioapics; apic++) {
872 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
874 idx = find_irq_entry(apic,pin,mp_INT);
877 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
880 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
884 apic_printk(APIC_VERBOSE, " not connected.\n");
888 irq = pin_2_irq(idx, apic, pin);
889 add_pin_to_irq(irq, apic, pin);
891 setup_IO_APIC_irq(apic, pin, irq,
892 irq_trigger(idx), irq_polarity(idx));
897 apic_printk(APIC_VERBOSE, " not connected.\n");
901 * Set up the 8259A-master output pin as broadcast to all
904 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
906 struct IO_APIC_route_entry entry;
909 memset(&entry,0,sizeof(entry));
911 disable_8259A_irq(0);
914 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
917 * We use logical delivery to get the timer IRQ
920 entry.dest_mode = INT_DEST_MODE;
921 entry.mask = 0; /* unmask IRQ now */
922 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
923 entry.delivery_mode = INT_DELIVERY_MODE;
926 entry.vector = vector;
929 * The timer IRQ doesn't have to know that behind the
930 * scene we have a 8259A-master in AEOI mode ...
932 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
935 * Add it to the IO-APIC irq-routing table:
937 spin_lock_irqsave(&ioapic_lock, flags);
938 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
939 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
940 spin_unlock_irqrestore(&ioapic_lock, flags);
945 void __apicdebuginit print_IO_APIC(void)
948 union IO_APIC_reg_00 reg_00;
949 union IO_APIC_reg_01 reg_01;
950 union IO_APIC_reg_02 reg_02;
953 if (apic_verbosity == APIC_QUIET)
956 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
957 for (i = 0; i < nr_ioapics; i++)
958 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
959 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
962 * We are a bit conservative about what we expect. We have to
963 * know about every hardware change ASAP.
965 printk(KERN_INFO "testing the IO APIC.......................\n");
967 for (apic = 0; apic < nr_ioapics; apic++) {
969 spin_lock_irqsave(&ioapic_lock, flags);
970 reg_00.raw = io_apic_read(apic, 0);
971 reg_01.raw = io_apic_read(apic, 1);
972 if (reg_01.bits.version >= 0x10)
973 reg_02.raw = io_apic_read(apic, 2);
974 spin_unlock_irqrestore(&ioapic_lock, flags);
977 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
978 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
979 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
981 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
982 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
984 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
985 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
987 if (reg_01.bits.version >= 0x10) {
988 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
989 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
992 printk(KERN_DEBUG ".... IRQ redirection table:\n");
994 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
995 " Stat Dmod Deli Vect: \n");
997 for (i = 0; i <= reg_01.bits.entries; i++) {
998 struct IO_APIC_route_entry entry;
1000 entry = ioapic_read_entry(apic, i);
1002 printk(KERN_DEBUG " %02x %03X ",
1007 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1012 entry.delivery_status,
1014 entry.delivery_mode,
1019 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1020 for (i = 0; i < NR_IRQS; i++) {
1021 struct irq_pin_list *entry = irq_2_pin + i;
1024 printk(KERN_DEBUG "IRQ%d ", i);
1026 printk("-> %d:%d", entry->apic, entry->pin);
1029 entry = irq_2_pin + entry->next;
1034 printk(KERN_INFO ".................................... done.\n");
1041 static __apicdebuginit void print_APIC_bitfield (int base)
1046 if (apic_verbosity == APIC_QUIET)
1049 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1050 for (i = 0; i < 8; i++) {
1051 v = apic_read(base + i*0x10);
1052 for (j = 0; j < 32; j++) {
1062 void __apicdebuginit print_local_APIC(void * dummy)
1064 unsigned int v, ver, maxlvt;
1066 if (apic_verbosity == APIC_QUIET)
1069 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1070 smp_processor_id(), hard_smp_processor_id());
1071 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1072 v = apic_read(APIC_LVR);
1073 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1074 ver = GET_APIC_VERSION(v);
1075 maxlvt = lapic_get_maxlvt();
1077 v = apic_read(APIC_TASKPRI);
1078 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1080 v = apic_read(APIC_ARBPRI);
1081 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1082 v & APIC_ARBPRI_MASK);
1083 v = apic_read(APIC_PROCPRI);
1084 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1086 v = apic_read(APIC_EOI);
1087 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1088 v = apic_read(APIC_RRR);
1089 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1090 v = apic_read(APIC_LDR);
1091 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1092 v = apic_read(APIC_DFR);
1093 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1094 v = apic_read(APIC_SPIV);
1095 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1097 printk(KERN_DEBUG "... APIC ISR field:\n");
1098 print_APIC_bitfield(APIC_ISR);
1099 printk(KERN_DEBUG "... APIC TMR field:\n");
1100 print_APIC_bitfield(APIC_TMR);
1101 printk(KERN_DEBUG "... APIC IRR field:\n");
1102 print_APIC_bitfield(APIC_IRR);
1104 v = apic_read(APIC_ESR);
1105 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1107 v = apic_read(APIC_ICR);
1108 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1109 v = apic_read(APIC_ICR2);
1110 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1112 v = apic_read(APIC_LVTT);
1113 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1115 if (maxlvt > 3) { /* PC is LVT#4. */
1116 v = apic_read(APIC_LVTPC);
1117 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1119 v = apic_read(APIC_LVT0);
1120 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1121 v = apic_read(APIC_LVT1);
1122 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1124 if (maxlvt > 2) { /* ERR is LVT#3. */
1125 v = apic_read(APIC_LVTERR);
1126 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1129 v = apic_read(APIC_TMICT);
1130 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1131 v = apic_read(APIC_TMCCT);
1132 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1133 v = apic_read(APIC_TDCR);
1134 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1138 void print_all_local_APICs (void)
1140 on_each_cpu(print_local_APIC, NULL, 1, 1);
1143 void __apicdebuginit print_PIC(void)
1146 unsigned long flags;
1148 if (apic_verbosity == APIC_QUIET)
1151 printk(KERN_DEBUG "\nprinting PIC contents\n");
1153 spin_lock_irqsave(&i8259A_lock, flags);
1155 v = inb(0xa1) << 8 | inb(0x21);
1156 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1158 v = inb(0xa0) << 8 | inb(0x20);
1159 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1163 v = inb(0xa0) << 8 | inb(0x20);
1167 spin_unlock_irqrestore(&i8259A_lock, flags);
1169 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1171 v = inb(0x4d1) << 8 | inb(0x4d0);
1172 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1177 void __init enable_IO_APIC(void)
1179 union IO_APIC_reg_01 reg_01;
1180 int i8259_apic, i8259_pin;
1182 unsigned long flags;
1184 for (i = 0; i < PIN_MAP_SIZE; i++) {
1185 irq_2_pin[i].pin = -1;
1186 irq_2_pin[i].next = 0;
1190 * The number of IO-APIC IRQ registers (== #pins):
1192 for (apic = 0; apic < nr_ioapics; apic++) {
1193 spin_lock_irqsave(&ioapic_lock, flags);
1194 reg_01.raw = io_apic_read(apic, 1);
1195 spin_unlock_irqrestore(&ioapic_lock, flags);
1196 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1198 for(apic = 0; apic < nr_ioapics; apic++) {
1200 /* See if any of the pins is in ExtINT mode */
1201 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1202 struct IO_APIC_route_entry entry;
1203 entry = ioapic_read_entry(apic, pin);
1205 /* If the interrupt line is enabled and in ExtInt mode
1206 * I have found the pin where the i8259 is connected.
1208 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1209 ioapic_i8259.apic = apic;
1210 ioapic_i8259.pin = pin;
1216 /* Look to see what if the MP table has reported the ExtINT */
1217 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1218 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1219 /* Trust the MP table if nothing is setup in the hardware */
1220 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1221 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1222 ioapic_i8259.pin = i8259_pin;
1223 ioapic_i8259.apic = i8259_apic;
1225 /* Complain if the MP table and the hardware disagree */
1226 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1227 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1229 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1233 * Do not trust the IO-APIC being empty at bootup
1239 * Not an __init, needed by the reboot code
1241 void disable_IO_APIC(void)
1244 * Clear the IO-APIC before rebooting:
1249 * If the i8259 is routed through an IOAPIC
1250 * Put that IOAPIC in virtual wire mode
1251 * so legacy interrupts can be delivered.
1253 if (ioapic_i8259.pin != -1) {
1254 struct IO_APIC_route_entry entry;
1256 memset(&entry, 0, sizeof(entry));
1257 entry.mask = 0; /* Enabled */
1258 entry.trigger = 0; /* Edge */
1260 entry.polarity = 0; /* High */
1261 entry.delivery_status = 0;
1262 entry.dest_mode = 0; /* Physical */
1263 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1265 entry.dest = GET_APIC_ID(read_apic_id());
1268 * Add it to the IO-APIC irq-routing table:
1270 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1273 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1277 * There is a nasty bug in some older SMP boards, their mptable lies
1278 * about the timer IRQ. We do the following to work around the situation:
1280 * - timer IRQ defaults to IO-APIC IRQ
1281 * - if this function detects that timer IRQs are defunct, then we fall
1282 * back to ISA timer IRQs
1284 static int __init timer_irq_works(void)
1286 unsigned long t1 = jiffies;
1287 unsigned long flags;
1289 local_save_flags(flags);
1291 /* Let ten ticks pass... */
1292 mdelay((10 * 1000) / HZ);
1293 local_irq_restore(flags);
1296 * Expect a few ticks at least, to be sure some possible
1297 * glue logic does not lock up after one or two first
1298 * ticks in a non-ExtINT mode. Also the local APIC
1299 * might have cached one ExtINT interrupt. Finally, at
1300 * least one tick may be lost due to delays.
1304 if (time_after(jiffies, t1 + 4))
1310 * In the SMP+IOAPIC case it might happen that there are an unspecified
1311 * number of pending IRQ events unhandled. These cases are very rare,
1312 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1313 * better to do it this way as thus we do not have to be aware of
1314 * 'pending' interrupts in the IRQ path, except at this point.
1317 * Edge triggered needs to resend any interrupt
1318 * that was delayed but this is now handled in the device
1323 * Starting up a edge-triggered IO-APIC interrupt is
1324 * nasty - we need to make sure that we get the edge.
1325 * If it is already asserted for some reason, we need
1326 * return 1 to indicate that is was pending.
1328 * This is not complete - we should be able to fake
1329 * an edge even if it isn't on the 8259A...
1332 static unsigned int startup_ioapic_irq(unsigned int irq)
1334 int was_pending = 0;
1335 unsigned long flags;
1337 spin_lock_irqsave(&ioapic_lock, flags);
1339 disable_8259A_irq(irq);
1340 if (i8259A_irq_pending(irq))
1343 __unmask_IO_APIC_irq(irq);
1344 spin_unlock_irqrestore(&ioapic_lock, flags);
1349 static int ioapic_retrigger_irq(unsigned int irq)
1351 struct irq_cfg *cfg = &irq_cfg[irq];
1353 unsigned long flags;
1355 spin_lock_irqsave(&vector_lock, flags);
1357 cpu_set(first_cpu(cfg->domain), mask);
1359 send_IPI_mask(mask, cfg->vector);
1360 spin_unlock_irqrestore(&vector_lock, flags);
1366 * Level and edge triggered IO-APIC interrupts need different handling,
1367 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1368 * handled with the level-triggered descriptor, but that one has slightly
1369 * more overhead. Level-triggered interrupts cannot be handled with the
1370 * edge-triggered handler, without risking IRQ storms and other ugly
1375 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1377 unsigned vector, me;
1382 me = smp_processor_id();
1383 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1385 struct irq_desc *desc;
1386 struct irq_cfg *cfg;
1387 irq = __get_cpu_var(vector_irq)[vector];
1391 desc = irq_desc + irq;
1392 cfg = irq_cfg + irq;
1393 spin_lock(&desc->lock);
1394 if (!cfg->move_cleanup_count)
1397 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1400 __get_cpu_var(vector_irq)[vector] = -1;
1401 cfg->move_cleanup_count--;
1403 spin_unlock(&desc->lock);
1409 static void irq_complete_move(unsigned int irq)
1411 struct irq_cfg *cfg = irq_cfg + irq;
1412 unsigned vector, me;
1414 if (likely(!cfg->move_in_progress))
1417 vector = ~get_irq_regs()->orig_ax;
1418 me = smp_processor_id();
1419 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1420 cpumask_t cleanup_mask;
1422 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1423 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1424 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1425 cfg->move_in_progress = 0;
1429 static inline void irq_complete_move(unsigned int irq) {}
1432 static void ack_apic_edge(unsigned int irq)
1434 irq_complete_move(irq);
1435 move_native_irq(irq);
1439 static void ack_apic_level(unsigned int irq)
1441 int do_unmask_irq = 0;
1443 irq_complete_move(irq);
1444 #ifdef CONFIG_GENERIC_PENDING_IRQ
1445 /* If we are moving the irq we need to mask it */
1446 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1448 mask_IO_APIC_irq(irq);
1453 * We must acknowledge the irq before we move it or the acknowledge will
1454 * not propagate properly.
1458 /* Now we can move and renable the irq */
1459 if (unlikely(do_unmask_irq)) {
1460 /* Only migrate the irq if the ack has been received.
1462 * On rare occasions the broadcast level triggered ack gets
1463 * delayed going to ioapics, and if we reprogram the
1464 * vector while Remote IRR is still set the irq will never
1467 * To prevent this scenario we read the Remote IRR bit
1468 * of the ioapic. This has two effects.
1469 * - On any sane system the read of the ioapic will
1470 * flush writes (and acks) going to the ioapic from
1472 * - We get to see if the ACK has actually been delivered.
1474 * Based on failed experiments of reprogramming the
1475 * ioapic entry from outside of irq context starting
1476 * with masking the ioapic entry and then polling until
1477 * Remote IRR was clear before reprogramming the
1478 * ioapic I don't trust the Remote IRR bit to be
1479 * completey accurate.
1481 * However there appears to be no other way to plug
1482 * this race, so if the Remote IRR bit is not
1483 * accurate and is causing problems then it is a hardware bug
1484 * and you can go talk to the chipset vendor about it.
1486 if (!io_apic_level_ack_pending(irq))
1487 move_masked_irq(irq);
1488 unmask_IO_APIC_irq(irq);
1492 static struct irq_chip ioapic_chip __read_mostly = {
1494 .startup = startup_ioapic_irq,
1495 .mask = mask_IO_APIC_irq,
1496 .unmask = unmask_IO_APIC_irq,
1497 .ack = ack_apic_edge,
1498 .eoi = ack_apic_level,
1500 .set_affinity = set_ioapic_affinity_irq,
1502 .retrigger = ioapic_retrigger_irq,
1505 static inline void init_IO_APIC_traps(void)
1510 * NOTE! The local APIC isn't very good at handling
1511 * multiple interrupts at the same interrupt level.
1512 * As the interrupt level is determined by taking the
1513 * vector number and shifting that right by 4, we
1514 * want to spread these out a bit so that they don't
1515 * all fall in the same interrupt level.
1517 * Also, we've got to be careful not to trash gate
1518 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1520 for (irq = 0; irq < NR_IRQS ; irq++) {
1522 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1524 * Hmm.. We don't have an entry for this,
1525 * so default to an old-fashioned 8259
1526 * interrupt if we can..
1529 make_8259A_irq(irq);
1531 /* Strange. Oh, well.. */
1532 irq_desc[irq].chip = &no_irq_chip;
1537 static void enable_lapic_irq (unsigned int irq)
1541 v = apic_read(APIC_LVT0);
1542 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1545 static void disable_lapic_irq (unsigned int irq)
1549 v = apic_read(APIC_LVT0);
1550 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1553 static void ack_lapic_irq (unsigned int irq)
1558 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1560 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1561 .name = "local-APIC",
1562 .typename = "local-APIC-edge",
1563 .startup = NULL, /* startup_irq() not used for IRQ0 */
1564 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1565 .enable = enable_lapic_irq,
1566 .disable = disable_lapic_irq,
1567 .ack = ack_lapic_irq,
1568 .end = end_lapic_irq,
1571 static void __init setup_nmi(void)
1574 * Dirty trick to enable the NMI watchdog ...
1575 * We put the 8259A master into AEOI mode and
1576 * unmask on all local APICs LVT0 as NMI.
1578 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1579 * is from Maciej W. Rozycki - so we do not have to EOI from
1580 * the NMI handler or the timer interrupt.
1582 printk(KERN_INFO "activating NMI Watchdog ...");
1584 enable_NMI_through_LVT0();
1590 * This looks a bit hackish but it's about the only one way of sending
1591 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1592 * not support the ExtINT mode, unfortunately. We need to send these
1593 * cycles as some i82489DX-based boards have glue logic that keeps the
1594 * 8259A interrupt line asserted until INTA. --macro
1596 static inline void unlock_ExtINT_logic(void)
1599 struct IO_APIC_route_entry entry0, entry1;
1600 unsigned char save_control, save_freq_select;
1601 unsigned long flags;
1603 pin = find_isa_irq_pin(8, mp_INT);
1604 apic = find_isa_irq_apic(8, mp_INT);
1608 spin_lock_irqsave(&ioapic_lock, flags);
1609 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1610 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1611 spin_unlock_irqrestore(&ioapic_lock, flags);
1612 clear_IO_APIC_pin(apic, pin);
1614 memset(&entry1, 0, sizeof(entry1));
1616 entry1.dest_mode = 0; /* physical delivery */
1617 entry1.mask = 0; /* unmask IRQ now */
1618 entry1.dest = hard_smp_processor_id();
1619 entry1.delivery_mode = dest_ExtINT;
1620 entry1.polarity = entry0.polarity;
1624 spin_lock_irqsave(&ioapic_lock, flags);
1625 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1626 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1627 spin_unlock_irqrestore(&ioapic_lock, flags);
1629 save_control = CMOS_READ(RTC_CONTROL);
1630 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1631 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1633 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1638 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1642 CMOS_WRITE(save_control, RTC_CONTROL);
1643 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1644 clear_IO_APIC_pin(apic, pin);
1646 spin_lock_irqsave(&ioapic_lock, flags);
1647 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1648 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1649 spin_unlock_irqrestore(&ioapic_lock, flags);
1653 * This code may look a bit paranoid, but it's supposed to cooperate with
1654 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1655 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1656 * fanatically on his truly buggy board.
1658 * FIXME: really need to revamp this for modern platforms only.
1660 static inline void __init check_timer(void)
1662 struct irq_cfg *cfg = irq_cfg + 0;
1663 int apic1, pin1, apic2, pin2;
1664 unsigned long flags;
1666 local_irq_save(flags);
1669 * get/set the timer IRQ vector:
1671 disable_8259A_irq(0);
1672 assign_irq_vector(0, TARGET_CPUS);
1675 * Subtle, code in do_timer_interrupt() expects an AEOI
1676 * mode for the 8259A whenever interrupts are routed
1677 * through I/O APICs. Also IRQ0 has to be enabled in
1678 * the 8259A which implies the virtual wire has to be
1679 * disabled in the local APIC.
1681 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1683 if (timer_over_8254 > 0)
1684 enable_8259A_irq(0);
1686 pin1 = find_isa_irq_pin(0, mp_INT);
1687 apic1 = find_isa_irq_apic(0, mp_INT);
1688 pin2 = ioapic_i8259.pin;
1689 apic2 = ioapic_i8259.apic;
1691 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1692 cfg->vector, apic1, pin1, apic2, pin2);
1696 * Ok, does IRQ0 through the IOAPIC work?
1698 unmask_IO_APIC_irq(0);
1699 if (!no_timer_check && timer_irq_works()) {
1700 nmi_watchdog_default();
1701 if (nmi_watchdog == NMI_IO_APIC) {
1702 disable_8259A_irq(0);
1704 enable_8259A_irq(0);
1706 if (disable_timer_pin_1 > 0)
1707 clear_IO_APIC_pin(0, pin1);
1710 clear_IO_APIC_pin(apic1, pin1);
1711 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1712 "connected to IO-APIC\n");
1715 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1716 "through the 8259A ... ");
1718 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1721 * legacy devices should be connected to IO APIC #0
1723 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1724 if (timer_irq_works()) {
1725 apic_printk(APIC_VERBOSE," works.\n");
1726 nmi_watchdog_default();
1727 if (nmi_watchdog == NMI_IO_APIC) {
1733 * Cleanup, just in case ...
1735 clear_IO_APIC_pin(apic2, pin2);
1737 apic_printk(APIC_VERBOSE," failed.\n");
1739 if (nmi_watchdog == NMI_IO_APIC) {
1740 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1744 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1746 disable_8259A_irq(0);
1747 irq_desc[0].chip = &lapic_irq_type;
1748 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1749 enable_8259A_irq(0);
1751 if (timer_irq_works()) {
1752 apic_printk(APIC_VERBOSE," works.\n");
1755 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1756 apic_printk(APIC_VERBOSE," failed.\n");
1758 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1762 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1764 unlock_ExtINT_logic();
1766 if (timer_irq_works()) {
1767 apic_printk(APIC_VERBOSE," works.\n");
1770 apic_printk(APIC_VERBOSE," failed :(.\n");
1771 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1773 local_irq_restore(flags);
1776 static int __init notimercheck(char *s)
1781 __setup("no_timer_check", notimercheck);
1785 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1786 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1787 * Linux doesn't really care, as it's not actually used
1788 * for any interrupt handling anyway.
1790 #define PIC_IRQS (1<<2)
1792 void __init setup_IO_APIC(void)
1796 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1800 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1802 io_apic_irqs = ~PIC_IRQS;
1804 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1807 setup_IO_APIC_irqs();
1808 init_IO_APIC_traps();
1814 struct sysfs_ioapic_data {
1815 struct sys_device dev;
1816 struct IO_APIC_route_entry entry[0];
1818 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1820 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1822 struct IO_APIC_route_entry *entry;
1823 struct sysfs_ioapic_data *data;
1826 data = container_of(dev, struct sysfs_ioapic_data, dev);
1827 entry = data->entry;
1828 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1829 *entry = ioapic_read_entry(dev->id, i);
1834 static int ioapic_resume(struct sys_device *dev)
1836 struct IO_APIC_route_entry *entry;
1837 struct sysfs_ioapic_data *data;
1838 unsigned long flags;
1839 union IO_APIC_reg_00 reg_00;
1842 data = container_of(dev, struct sysfs_ioapic_data, dev);
1843 entry = data->entry;
1845 spin_lock_irqsave(&ioapic_lock, flags);
1846 reg_00.raw = io_apic_read(dev->id, 0);
1847 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1848 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1849 io_apic_write(dev->id, 0, reg_00.raw);
1851 spin_unlock_irqrestore(&ioapic_lock, flags);
1852 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1853 ioapic_write_entry(dev->id, i, entry[i]);
1858 static struct sysdev_class ioapic_sysdev_class = {
1860 .suspend = ioapic_suspend,
1861 .resume = ioapic_resume,
1864 static int __init ioapic_init_sysfs(void)
1866 struct sys_device * dev;
1869 error = sysdev_class_register(&ioapic_sysdev_class);
1873 for (i = 0; i < nr_ioapics; i++ ) {
1874 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1875 * sizeof(struct IO_APIC_route_entry);
1876 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1877 if (!mp_ioapic_data[i]) {
1878 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1881 dev = &mp_ioapic_data[i]->dev;
1883 dev->cls = &ioapic_sysdev_class;
1884 error = sysdev_register(dev);
1886 kfree(mp_ioapic_data[i]);
1887 mp_ioapic_data[i] = NULL;
1888 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1896 device_initcall(ioapic_init_sysfs);
1899 * Dynamic irq allocate and deallocation
1901 int create_irq(void)
1903 /* Allocate an unused irq */
1906 unsigned long flags;
1909 spin_lock_irqsave(&vector_lock, flags);
1910 for (new = (NR_IRQS - 1); new >= 0; new--) {
1911 if (platform_legacy_irq(new))
1913 if (irq_cfg[new].vector != 0)
1915 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1919 spin_unlock_irqrestore(&vector_lock, flags);
1922 dynamic_irq_init(irq);
1927 void destroy_irq(unsigned int irq)
1929 unsigned long flags;
1931 dynamic_irq_cleanup(irq);
1933 spin_lock_irqsave(&vector_lock, flags);
1934 __clear_irq_vector(irq);
1935 spin_unlock_irqrestore(&vector_lock, flags);
1939 * MSI message composition
1941 #ifdef CONFIG_PCI_MSI
1942 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1944 struct irq_cfg *cfg = irq_cfg + irq;
1950 err = assign_irq_vector(irq, tmp);
1952 cpus_and(tmp, cfg->domain, tmp);
1953 dest = cpu_mask_to_apicid(tmp);
1955 msg->address_hi = MSI_ADDR_BASE_HI;
1958 ((INT_DEST_MODE == 0) ?
1959 MSI_ADDR_DEST_MODE_PHYSICAL:
1960 MSI_ADDR_DEST_MODE_LOGICAL) |
1961 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1962 MSI_ADDR_REDIRECTION_CPU:
1963 MSI_ADDR_REDIRECTION_LOWPRI) |
1964 MSI_ADDR_DEST_ID(dest);
1967 MSI_DATA_TRIGGER_EDGE |
1968 MSI_DATA_LEVEL_ASSERT |
1969 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1970 MSI_DATA_DELIVERY_FIXED:
1971 MSI_DATA_DELIVERY_LOWPRI) |
1972 MSI_DATA_VECTOR(cfg->vector);
1978 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1980 struct irq_cfg *cfg = irq_cfg + irq;
1985 cpus_and(tmp, mask, cpu_online_map);
1986 if (cpus_empty(tmp))
1989 if (assign_irq_vector(irq, mask))
1992 cpus_and(tmp, cfg->domain, mask);
1993 dest = cpu_mask_to_apicid(tmp);
1995 read_msi_msg(irq, &msg);
1997 msg.data &= ~MSI_DATA_VECTOR_MASK;
1998 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1999 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2000 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2002 write_msi_msg(irq, &msg);
2003 irq_desc[irq].affinity = mask;
2005 #endif /* CONFIG_SMP */
2008 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2009 * which implement the MSI or MSI-X Capability Structure.
2011 static struct irq_chip msi_chip = {
2013 .unmask = unmask_msi_irq,
2014 .mask = mask_msi_irq,
2015 .ack = ack_apic_edge,
2017 .set_affinity = set_msi_irq_affinity,
2019 .retrigger = ioapic_retrigger_irq,
2022 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2030 ret = msi_compose_msg(dev, irq, &msg);
2036 set_irq_msi(irq, desc);
2037 write_msi_msg(irq, &msg);
2039 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2044 void arch_teardown_msi_irq(unsigned int irq)
2051 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2053 struct irq_cfg *cfg = irq_cfg + irq;
2058 cpus_and(tmp, mask, cpu_online_map);
2059 if (cpus_empty(tmp))
2062 if (assign_irq_vector(irq, mask))
2065 cpus_and(tmp, cfg->domain, mask);
2066 dest = cpu_mask_to_apicid(tmp);
2068 dmar_msi_read(irq, &msg);
2070 msg.data &= ~MSI_DATA_VECTOR_MASK;
2071 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2072 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2073 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2075 dmar_msi_write(irq, &msg);
2076 irq_desc[irq].affinity = mask;
2078 #endif /* CONFIG_SMP */
2080 struct irq_chip dmar_msi_type = {
2082 .unmask = dmar_msi_unmask,
2083 .mask = dmar_msi_mask,
2084 .ack = ack_apic_edge,
2086 .set_affinity = dmar_msi_set_affinity,
2088 .retrigger = ioapic_retrigger_irq,
2091 int arch_setup_dmar_msi(unsigned int irq)
2096 ret = msi_compose_msg(NULL, irq, &msg);
2099 dmar_msi_write(irq, &msg);
2100 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2106 #endif /* CONFIG_PCI_MSI */
2108 * Hypertransport interrupt support
2110 #ifdef CONFIG_HT_IRQ
2114 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2116 struct ht_irq_msg msg;
2117 fetch_ht_irq_msg(irq, &msg);
2119 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2120 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2122 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2123 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2125 write_ht_irq_msg(irq, &msg);
2128 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2130 struct irq_cfg *cfg = irq_cfg + irq;
2134 cpus_and(tmp, mask, cpu_online_map);
2135 if (cpus_empty(tmp))
2138 if (assign_irq_vector(irq, mask))
2141 cpus_and(tmp, cfg->domain, mask);
2142 dest = cpu_mask_to_apicid(tmp);
2144 target_ht_irq(irq, dest, cfg->vector);
2145 irq_desc[irq].affinity = mask;
2149 static struct irq_chip ht_irq_chip = {
2151 .mask = mask_ht_irq,
2152 .unmask = unmask_ht_irq,
2153 .ack = ack_apic_edge,
2155 .set_affinity = set_ht_irq_affinity,
2157 .retrigger = ioapic_retrigger_irq,
2160 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2162 struct irq_cfg *cfg = irq_cfg + irq;
2167 err = assign_irq_vector(irq, tmp);
2169 struct ht_irq_msg msg;
2172 cpus_and(tmp, cfg->domain, tmp);
2173 dest = cpu_mask_to_apicid(tmp);
2175 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2179 HT_IRQ_LOW_DEST_ID(dest) |
2180 HT_IRQ_LOW_VECTOR(cfg->vector) |
2181 ((INT_DEST_MODE == 0) ?
2182 HT_IRQ_LOW_DM_PHYSICAL :
2183 HT_IRQ_LOW_DM_LOGICAL) |
2184 HT_IRQ_LOW_RQEOI_EDGE |
2185 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2186 HT_IRQ_LOW_MT_FIXED :
2187 HT_IRQ_LOW_MT_ARBITRATED) |
2188 HT_IRQ_LOW_IRQ_MASKED;
2190 write_ht_irq_msg(irq, &msg);
2192 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2193 handle_edge_irq, "edge");
2197 #endif /* CONFIG_HT_IRQ */
2199 /* --------------------------------------------------------------------------
2200 ACPI-based IOAPIC Configuration
2201 -------------------------------------------------------------------------- */
2205 #define IO_APIC_MAX_ID 0xFE
2207 int __init io_apic_get_redir_entries (int ioapic)
2209 union IO_APIC_reg_01 reg_01;
2210 unsigned long flags;
2212 spin_lock_irqsave(&ioapic_lock, flags);
2213 reg_01.raw = io_apic_read(ioapic, 1);
2214 spin_unlock_irqrestore(&ioapic_lock, flags);
2216 return reg_01.bits.entries;
2220 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2222 if (!IO_APIC_IRQ(irq)) {
2223 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2229 * IRQs < 16 are already in the irq_2_pin[] map
2232 add_pin_to_irq(irq, ioapic, pin);
2234 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2240 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2244 if (skip_ioapic_setup)
2247 for (i = 0; i < mp_irq_entries; i++)
2248 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2249 mp_irqs[i].mpc_srcbusirq == bus_irq)
2251 if (i >= mp_irq_entries)
2254 *trigger = irq_trigger(i);
2255 *polarity = irq_polarity(i);
2259 #endif /* CONFIG_ACPI */
2262 * This function currently is only a helper for the i386 smp boot process where
2263 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2264 * so mask in all cases should simply be TARGET_CPUS
2267 void __init setup_ioapic_dest(void)
2269 int pin, ioapic, irq, irq_entry;
2271 if (skip_ioapic_setup == 1)
2274 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2275 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2276 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2277 if (irq_entry == -1)
2279 irq = pin_2_irq(irq_entry, ioapic, pin);
2281 /* setup_IO_APIC_irqs could fail to get vector for some device
2282 * when you have too many devices, because at that time only boot
2285 if (!irq_cfg[irq].vector)
2286 setup_IO_APIC_irq(ioapic, pin, irq,
2287 irq_trigger(irq_entry),
2288 irq_polarity(irq_entry));
2290 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2297 #define IOAPIC_RESOURCE_NAME_SIZE 11
2299 static struct resource *ioapic_resources;
2301 static struct resource * __init ioapic_setup_resources(void)
2304 struct resource *res;
2308 if (nr_ioapics <= 0)
2311 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2314 mem = alloc_bootmem(n);
2319 mem += sizeof(struct resource) * nr_ioapics;
2321 for (i = 0; i < nr_ioapics; i++) {
2323 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2324 sprintf(mem, "IOAPIC %u", i);
2325 mem += IOAPIC_RESOURCE_NAME_SIZE;
2329 ioapic_resources = res;
2334 void __init ioapic_init_mappings(void)
2336 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2337 struct resource *ioapic_res;
2340 ioapic_res = ioapic_setup_resources();
2341 for (i = 0; i < nr_ioapics; i++) {
2342 if (smp_found_config) {
2343 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2345 ioapic_phys = (unsigned long)
2346 alloc_bootmem_pages(PAGE_SIZE);
2347 ioapic_phys = __pa(ioapic_phys);
2349 set_fixmap_nocache(idx, ioapic_phys);
2350 apic_printk(APIC_VERBOSE,
2351 "mapped IOAPIC to %016lx (%016lx)\n",
2352 __fix_to_virt(idx), ioapic_phys);
2355 if (ioapic_res != NULL) {
2356 ioapic_res->start = ioapic_phys;
2357 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2363 static int __init ioapic_insert_resources(void)
2366 struct resource *r = ioapic_resources;
2370 "IO APIC resources could be not be allocated.\n");
2374 for (i = 0; i < nr_ioapics; i++) {
2375 insert_resource(&iomem_resource, r);
2382 /* Insert the IO APIC resources after PCI initialization has occured to handle
2383 * IO APICS that are mapped in on a BAR in PCI space. */
2384 late_initcall(ioapic_insert_resources);