2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * CPU hotplug support - ashok.raj@intel.com
14 * This file handles the architecture-dependent parts of process handling..
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
21 #include <linux/kernel.h>
23 #include <linux/elfcore.h>
24 #include <linux/smp.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/export.h>
30 #include <linux/ptrace.h>
31 #include <linux/notifier.h>
32 #include <linux/kprobes.h>
33 #include <linux/kdebug.h>
34 #include <linux/prctl.h>
35 #include <linux/uaccess.h>
37 #include <linux/ftrace.h>
39 #include <asm/pgtable.h>
40 #include <asm/processor.h>
41 #include <asm/fpu/internal.h>
42 #include <asm/mmu_context.h>
43 #include <asm/prctl.h>
45 #include <asm/proto.h>
48 #include <asm/syscalls.h>
49 #include <asm/debugreg.h>
50 #include <asm/switch_to.h>
51 #include <asm/xen/hypervisor.h>
53 asmlinkage extern void ret_from_fork(void);
55 __visible DEFINE_PER_CPU(unsigned long, rsp_scratch);
57 /* Prints also some state that isn't saved in the pt_regs */
58 void __show_regs(struct pt_regs *regs, int all)
60 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
61 unsigned long d0, d1, d2, d3, d6, d7;
62 unsigned int fsindex, gsindex;
63 unsigned int ds, cs, es;
65 printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
66 printk_address(regs->ip);
67 printk(KERN_DEFAULT "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss,
68 regs->sp, regs->flags);
69 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n",
70 regs->ax, regs->bx, regs->cx);
71 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n",
72 regs->dx, regs->si, regs->di);
73 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n",
74 regs->bp, regs->r8, regs->r9);
75 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n",
76 regs->r10, regs->r11, regs->r12);
77 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n",
78 regs->r13, regs->r14, regs->r15);
80 asm("movl %%ds,%0" : "=r" (ds));
81 asm("movl %%cs,%0" : "=r" (cs));
82 asm("movl %%es,%0" : "=r" (es));
83 asm("movl %%fs,%0" : "=r" (fsindex));
84 asm("movl %%gs,%0" : "=r" (gsindex));
86 rdmsrl(MSR_FS_BASE, fs);
87 rdmsrl(MSR_GS_BASE, gs);
88 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
98 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
99 fs, fsindex, gs, gsindex, shadowgs);
100 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
102 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
112 /* Only print out debug registers if they are in their non-default state. */
113 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
114 (d6 == DR6_RESERVED) && (d7 == 0x400))
117 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
118 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
120 if (boot_cpu_has(X86_FEATURE_OSPKE))
121 printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru());
124 void release_thread(struct task_struct *dead_task)
127 #ifdef CONFIG_MODIFY_LDT_SYSCALL
128 if (dead_task->mm->context.ldt) {
129 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
131 dead_task->mm->context.ldt->entries,
132 dead_task->mm->context.ldt->size);
139 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
140 unsigned long arg, struct task_struct *p, unsigned long tls)
143 struct pt_regs *childregs;
144 struct fork_frame *fork_frame;
145 struct inactive_task_frame *frame;
146 struct task_struct *me = current;
148 p->thread.sp0 = (unsigned long)task_stack_page(p) + THREAD_SIZE;
149 childregs = task_pt_regs(p);
150 fork_frame = container_of(childregs, struct fork_frame, regs);
151 frame = &fork_frame->frame;
153 frame->ret_addr = (unsigned long) ret_from_fork;
154 p->thread.sp = (unsigned long) fork_frame;
155 p->thread.io_bitmap_ptr = NULL;
157 savesegment(gs, p->thread.gsindex);
158 p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase;
159 savesegment(fs, p->thread.fsindex);
160 p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase;
161 savesegment(es, p->thread.es);
162 savesegment(ds, p->thread.ds);
163 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
165 if (unlikely(p->flags & PF_KTHREAD)) {
167 memset(childregs, 0, sizeof(struct pt_regs));
168 childregs->sp = (unsigned long)childregs;
169 childregs->ss = __KERNEL_DS;
170 childregs->bx = sp; /* function */
172 childregs->orig_ax = -1;
173 childregs->cs = __KERNEL_CS | get_kernel_rpl();
174 childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED;
177 *childregs = *current_pt_regs();
184 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
185 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr,
186 IO_BITMAP_BYTES, GFP_KERNEL);
187 if (!p->thread.io_bitmap_ptr) {
188 p->thread.io_bitmap_max = 0;
191 set_tsk_thread_flag(p, TIF_IO_BITMAP);
195 * Set a new TLS for the child thread?
197 if (clone_flags & CLONE_SETTLS) {
198 #ifdef CONFIG_IA32_EMULATION
199 if (in_ia32_syscall())
200 err = do_set_thread_area(p, -1,
201 (struct user_desc __user *)tls, 0);
204 err = do_arch_prctl(p, ARCH_SET_FS, tls);
210 if (err && p->thread.io_bitmap_ptr) {
211 kfree(p->thread.io_bitmap_ptr);
212 p->thread.io_bitmap_max = 0;
219 start_thread_common(struct pt_regs *regs, unsigned long new_ip,
220 unsigned long new_sp,
221 unsigned int _cs, unsigned int _ss, unsigned int _ds)
224 loadsegment(es, _ds);
225 loadsegment(ds, _ds);
231 regs->flags = X86_EFLAGS_IF;
236 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
238 start_thread_common(regs, new_ip, new_sp,
239 __USER_CS, __USER_DS, 0);
243 void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp)
245 start_thread_common(regs, new_ip, new_sp,
246 test_thread_flag(TIF_X32)
247 ? __USER_CS : __USER32_CS,
248 __USER_DS, __USER_DS);
253 * switch_to(x,y) should switch tasks from x to y.
255 * This could still be optimized:
256 * - fold all the options into a flag word and test it with a single test.
257 * - could test fs/gs bitsliced
259 * Kprobes not supported here. Set the probe on schedule instead.
260 * Function graph tracer not supported too.
262 __visible __notrace_funcgraph struct task_struct *
263 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
265 struct thread_struct *prev = &prev_p->thread;
266 struct thread_struct *next = &next_p->thread;
267 struct fpu *prev_fpu = &prev->fpu;
268 struct fpu *next_fpu = &next->fpu;
269 int cpu = smp_processor_id();
270 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
271 unsigned prev_fsindex, prev_gsindex;
272 fpu_switch_t fpu_switch;
274 fpu_switch = switch_fpu_prepare(prev_fpu, next_fpu, cpu);
276 /* We must save %fs and %gs before load_TLS() because
277 * %fs and %gs may be cleared by load_TLS().
279 * (e.g. xen_load_tls())
281 savesegment(fs, prev_fsindex);
282 savesegment(gs, prev_gsindex);
285 * Load TLS before restoring any segments so that segment loads
286 * reference the correct GDT entries.
291 * Leave lazy mode, flushing any hypercalls made here. This
292 * must be done after loading TLS entries in the GDT but before
293 * loading segments that might reference them, and and it must
294 * be done before fpu__restore(), so the TS bit is up to
297 arch_end_context_switch(next_p);
301 * Reading them only returns the selectors, but writing them (if
302 * nonzero) loads the full descriptor from the GDT or LDT. The
303 * LDT for next is loaded in switch_mm, and the GDT is loaded
306 * We therefore need to write new values to the segment
307 * registers on every context switch unless both the new and old
310 * Note that we don't need to do anything for CS and SS, as
311 * those are saved and restored as part of pt_regs.
313 savesegment(es, prev->es);
314 if (unlikely(next->es | prev->es))
315 loadsegment(es, next->es);
317 savesegment(ds, prev->ds);
318 if (unlikely(next->ds | prev->ds))
319 loadsegment(ds, next->ds);
324 * These are even more complicated than DS and ES: they have
325 * 64-bit bases are that controlled by arch_prctl. The bases
326 * don't necessarily match the selectors, as user code can do
327 * any number of things to cause them to be inconsistent.
329 * We don't promise to preserve the bases if the selectors are
330 * nonzero. We also don't promise to preserve the base if the
331 * selector is zero and the base doesn't match whatever was
332 * most recently passed to ARCH_SET_FS/GS. (If/when the
333 * FSGSBASE instructions are enabled, we'll need to offer
334 * stronger guarantees.)
337 * (fsbase != 0 && fsindex != 0) || (gsbase != 0 && gsindex != 0) is
341 /* Loading a nonzero value into FS sets the index and base. */
342 loadsegment(fs, next->fsindex);
345 /* Next index is zero but next base is nonzero. */
348 wrmsrl(MSR_FS_BASE, next->fsbase);
350 /* Next base and index are both zero. */
351 if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
353 * We don't know the previous base and can't
354 * find out without RDMSR. Forcibly clear it.
356 loadsegment(fs, __USER_DS);
360 * If the previous index is zero and ARCH_SET_FS
361 * didn't change the base, then the base is
362 * also zero and we don't need to do anything.
364 if (prev->fsbase || prev_fsindex)
370 * Save the old state and preserve the invariant.
371 * NB: if prev_fsindex == 0, then we can't reliably learn the base
372 * without RDMSR because Intel user code can zero it without telling
373 * us and AMD user code can program any 32-bit value without telling
378 prev->fsindex = prev_fsindex;
381 /* Loading a nonzero value into GS sets the index and base. */
382 load_gs_index(next->gsindex);
385 /* Next index is zero but next base is nonzero. */
388 wrmsrl(MSR_KERNEL_GS_BASE, next->gsbase);
390 /* Next base and index are both zero. */
391 if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
393 * We don't know the previous base and can't
394 * find out without RDMSR. Forcibly clear it.
396 * This contains a pointless SWAPGS pair.
397 * Fixing it would involve an explicit check
398 * for Xen or a new pvop.
400 load_gs_index(__USER_DS);
404 * If the previous index is zero and ARCH_SET_GS
405 * didn't change the base, then the base is
406 * also zero and we don't need to do anything.
408 if (prev->gsbase || prev_gsindex)
414 * Save the old state and preserve the invariant.
415 * NB: if prev_gsindex == 0, then we can't reliably learn the base
416 * without RDMSR because Intel user code can zero it without telling
417 * us and AMD user code can program any 32-bit value without telling
422 prev->gsindex = prev_gsindex;
424 switch_fpu_finish(next_fpu, fpu_switch);
427 * Switch the PDA and FPU contexts.
429 this_cpu_write(current_task, next_p);
431 /* Reload esp0 and ss1. This changes current_thread_info(). */
435 * Now maybe reload the debug registers and handle I/O bitmaps
437 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
438 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
439 __switch_to_xtra(prev_p, next_p, tss);
443 * On Xen PV, IOPL bits in pt_regs->flags have no effect, and
444 * current_pt_regs()->flags may not match the current task's
445 * intended IOPL. We need to switch it manually.
447 if (unlikely(static_cpu_has(X86_FEATURE_XENPV) &&
448 prev->iopl != next->iopl))
449 xen_set_iopl_mask(next->iopl);
452 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) {
454 * AMD CPUs have a misfeature: SYSRET sets the SS selector but
455 * does not update the cached descriptor. As a result, if we
456 * do SYSRET while SS is NULL, we'll end up in user mode with
457 * SS apparently equal to __USER_DS but actually unusable.
459 * The straightforward workaround would be to fix it up just
460 * before SYSRET, but that would slow down the system call
461 * fast paths. Instead, we ensure that SS is never NULL in
462 * system call context. We do this by replacing NULL SS
463 * selectors at every context switch. SYSCALL sets up a valid
464 * SS, so the only way to get NULL is to re-enter the kernel
465 * from CPL 3 through an interrupt. Since that can't happen
466 * in the same task as a running syscall, we are guaranteed to
467 * context switch between every interrupt vector entry and a
470 * We read SS first because SS reads are much faster than
471 * writes. Out of caution, we force SS to __KERNEL_DS even if
472 * it previously had a different non-NULL value.
474 unsigned short ss_sel;
475 savesegment(ss, ss_sel);
476 if (ss_sel != __KERNEL_DS)
477 loadsegment(ss, __KERNEL_DS);
483 void set_personality_64bit(void)
485 /* inherit personality from parent */
487 /* Make sure to be in 64bit mode */
488 clear_thread_flag(TIF_IA32);
489 clear_thread_flag(TIF_ADDR32);
490 clear_thread_flag(TIF_X32);
492 /* Ensure the corresponding mm is not marked. */
494 current->mm->context.ia32_compat = 0;
496 /* TBD: overwrites user setup. Should have two bits.
497 But 64bit processes have always behaved this way,
498 so it's not too bad. The main problem is just that
499 32bit childs are affected again. */
500 current->personality &= ~READ_IMPLIES_EXEC;
503 void set_personality_ia32(bool x32)
505 /* inherit personality from parent */
507 /* Make sure to be in 32bit mode */
508 set_thread_flag(TIF_ADDR32);
510 /* Mark the associated mm as containing 32-bit tasks. */
512 clear_thread_flag(TIF_IA32);
513 set_thread_flag(TIF_X32);
515 current->mm->context.ia32_compat = TIF_X32;
516 current->personality &= ~READ_IMPLIES_EXEC;
517 /* in_compat_syscall() uses the presence of the x32
518 syscall bit flag to determine compat status */
519 current_thread_info()->status &= ~TS_COMPAT;
521 set_thread_flag(TIF_IA32);
522 clear_thread_flag(TIF_X32);
524 current->mm->context.ia32_compat = TIF_IA32;
525 current->personality |= force_personality32;
526 /* Prepare the first "return" to user space */
527 current_thread_info()->status |= TS_COMPAT;
530 EXPORT_SYMBOL_GPL(set_personality_ia32);
532 long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
535 int doit = task == current;
540 if (addr >= TASK_SIZE_MAX)
543 task->thread.gsindex = 0;
544 task->thread.gsbase = addr;
547 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
552 /* Not strictly needed for fs, but do it for symmetry
554 if (addr >= TASK_SIZE_MAX)
557 task->thread.fsindex = 0;
558 task->thread.fsbase = addr;
560 /* set the selector to 0 to not confuse __switch_to */
562 ret = wrmsrl_safe(MSR_FS_BASE, addr);
569 rdmsrl(MSR_FS_BASE, base);
571 base = task->thread.fsbase;
572 ret = put_user(base, (unsigned long __user *)addr);
578 rdmsrl(MSR_KERNEL_GS_BASE, base);
580 base = task->thread.gsbase;
581 ret = put_user(base, (unsigned long __user *)addr);
593 long sys_arch_prctl(int code, unsigned long addr)
595 return do_arch_prctl(current, code, addr);
598 unsigned long KSTK_ESP(struct task_struct *task)
600 return task_pt_regs(task)->sp;