2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
68 #include <asm/setup.h>
69 #include <asm/uv/uv.h>
70 #include <linux/mc146818rtc.h>
72 #include <asm/smpboot_hooks.h>
73 #include <asm/i8259.h>
76 u8 apicid_2_node[MAX_APICID];
79 /* State of each CPU */
80 DEFINE_PER_CPU(int, cpu_state) = { 0 };
82 /* Store all idle threads, this can be reused instead of creating
83 * a new thread. Also avoids complicated thread destroy functionality
86 #ifdef CONFIG_HOTPLUG_CPU
88 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
89 * removed after init for !CONFIG_HOTPLUG_CPU.
91 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
92 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
93 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
96 * We need this for trampoline_base protection from concurrent accesses when
97 * off- and onlining cores wildly.
99 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
101 void cpu_hotplug_driver_lock()
103 mutex_lock(&x86_cpu_hotplug_driver_mutex);
106 void cpu_hotplug_driver_unlock()
108 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
111 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
112 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
114 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
115 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
116 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
119 /* Number of siblings per CPU package */
120 int smp_num_siblings = 1;
121 EXPORT_SYMBOL(smp_num_siblings);
123 /* Last level cache ID of each logical CPU */
124 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
126 /* representing HT siblings of each logical CPU */
127 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
128 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
130 /* representing HT and core siblings of each logical CPU */
131 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
132 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
134 /* Per CPU bogomips and other parameters */
135 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
136 EXPORT_PER_CPU_SYMBOL(cpu_info);
138 atomic_t init_deasserted;
140 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
141 /* which node each logical CPU is on */
142 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
143 EXPORT_SYMBOL(cpu_to_node_map);
145 /* set up a mapping between cpu and node. */
146 static void map_cpu_to_node(int cpu, int node)
148 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
149 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
150 cpu_to_node_map[cpu] = node;
153 /* undo a mapping between cpu and node. */
154 static void unmap_cpu_to_node(int cpu)
158 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
159 for (node = 0; node < MAX_NUMNODES; node++)
160 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
161 cpu_to_node_map[cpu] = 0;
163 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
164 #define map_cpu_to_node(cpu, node) ({})
165 #define unmap_cpu_to_node(cpu) ({})
169 static int boot_cpu_logical_apicid;
171 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
172 { [0 ... NR_CPUS-1] = BAD_APICID };
174 static void map_cpu_to_logical_apicid(void)
176 int cpu = smp_processor_id();
177 int apicid = logical_smp_processor_id();
178 int node = apic->apicid_to_node(apicid);
180 if (!node_online(node))
181 node = first_online_node;
183 cpu_2_logical_apicid[cpu] = apicid;
184 map_cpu_to_node(cpu, node);
187 void numa_remove_cpu(int cpu)
189 cpu_2_logical_apicid[cpu] = BAD_APICID;
190 unmap_cpu_to_node(cpu);
193 #define map_cpu_to_logical_apicid() do {} while (0)
197 * Report back to the Boot Processor.
200 static void __cpuinit smp_callin(void)
203 unsigned long timeout;
206 * If waken up by an INIT in an 82489DX configuration
207 * we may get here before an INIT-deassert IPI reaches
208 * our local APIC. We have to wait for the IPI or we'll
209 * lock up on an APIC access.
211 if (apic->wait_for_init_deassert)
212 apic->wait_for_init_deassert(&init_deasserted);
215 * (This works even if the APIC is not enabled.)
217 phys_id = read_apic_id();
218 cpuid = smp_processor_id();
219 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
220 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
223 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
226 * STARTUP IPIs are fragile beasts as they might sometimes
227 * trigger some glue motherboard logic. Complete APIC bus
228 * silence for 1 second, this overestimates the time the
229 * boot CPU is spending to send the up to 2 STARTUP IPIs
230 * by a factor of two. This should be enough.
234 * Waiting 2s total for startup (udelay is not yet working)
236 timeout = jiffies + 2*HZ;
237 while (time_before(jiffies, timeout)) {
239 * Has the boot CPU finished it's STARTUP sequence?
241 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
246 if (!time_before(jiffies, timeout)) {
247 panic("%s: CPU%d started up but did not get a callout!\n",
252 * the boot CPU has finished the init stage and is spinning
253 * on callin_map until we finish. We are free to set up this
254 * CPU, first the APIC. (this is probably redundant on most
258 pr_debug("CALLIN, before setup_local_APIC().\n");
259 if (apic->smp_callin_clear_local_apic)
260 apic->smp_callin_clear_local_apic();
262 end_local_APIC_setup();
263 map_cpu_to_logical_apicid();
266 * Need to setup vector mappings before we enable interrupts.
268 setup_vector_irq(smp_processor_id());
272 * Need to enable IRQs because it can take longer and then
273 * the NMI watchdog might kill us.
278 pr_debug("Stack at about %p\n", &cpuid);
281 * Save our processor parameters
283 smp_store_cpu_info(cpuid);
285 notify_cpu_starting(cpuid);
288 * Allow the master to continue.
290 cpumask_set_cpu(cpuid, cpu_callin_mask);
294 * Activate a secondary processor.
296 notrace static void __cpuinit start_secondary(void *unused)
299 * Don't put *anything* before cpu_init(), SMP booting is too
300 * fragile that we want to limit the things done here to the
301 * most necessary things.
306 * Switch away from the trampoline page-table
308 * Do this before cpu_init() because it needs to access per-cpu
309 * data which may not be mapped in the trampoline page-table.
311 load_cr3(swapper_pg_dir);
320 /* otherwise gcc will move up smp_processor_id before the cpu_init */
323 * Check TSC synchronization with the BP:
325 check_tsc_sync_target();
327 if (nmi_watchdog == NMI_IO_APIC) {
328 legacy_pic->chip->mask(0);
329 enable_NMI_through_LVT0();
330 legacy_pic->chip->unmask(0);
333 /* This must be done before setting cpu_online_mask */
334 set_cpu_sibling_map(raw_smp_processor_id());
338 * We need to hold call_lock, so there is no inconsistency
339 * between the time smp_call_function() determines number of
340 * IPI recipients, and the time when the determination is made
341 * for which cpus receive the IPI. Holding this
342 * lock helps us to not include this cpu in a currently in progress
343 * smp_call_function().
345 * We need to hold vector_lock so there the set of online cpus
346 * does not change while we are assigning vectors to cpus. Holding
347 * this lock ensures we don't half assign or remove an irq from a cpu.
351 set_cpu_online(smp_processor_id(), true);
352 unlock_vector_lock();
354 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
355 x86_platform.nmi_init();
357 /* enable local interrupts */
360 /* to prevent fake stack check failure in clock setup */
361 boot_init_stack_canary();
363 x86_cpuinit.setup_percpu_clockev();
369 #ifdef CONFIG_CPUMASK_OFFSTACK
370 /* In this case, llc_shared_map is a pointer to a cpumask. */
371 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
372 const struct cpuinfo_x86 *src)
374 struct cpumask *llc = dst->llc_shared_map;
376 dst->llc_shared_map = llc;
379 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
380 const struct cpuinfo_x86 *src)
384 #endif /* CONFIG_CPUMASK_OFFSTACK */
387 * The bootstrap kernel entry code has set these up. Save them for
391 void __cpuinit smp_store_cpu_info(int id)
393 struct cpuinfo_x86 *c = &cpu_data(id);
395 copy_cpuinfo_x86(c, &boot_cpu_data);
398 identify_secondary_cpu(c);
402 void __cpuinit set_cpu_sibling_map(int cpu)
405 struct cpuinfo_x86 *c = &cpu_data(cpu);
407 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
409 if (smp_num_siblings > 1) {
410 for_each_cpu(i, cpu_sibling_setup_mask) {
411 struct cpuinfo_x86 *o = &cpu_data(i);
413 if (c->phys_proc_id == o->phys_proc_id &&
414 c->cpu_core_id == o->cpu_core_id) {
415 cpumask_set_cpu(i, cpu_sibling_mask(cpu));
416 cpumask_set_cpu(cpu, cpu_sibling_mask(i));
417 cpumask_set_cpu(i, cpu_core_mask(cpu));
418 cpumask_set_cpu(cpu, cpu_core_mask(i));
419 cpumask_set_cpu(i, c->llc_shared_map);
420 cpumask_set_cpu(cpu, o->llc_shared_map);
424 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
427 cpumask_set_cpu(cpu, c->llc_shared_map);
429 if (current_cpu_data.x86_max_cores == 1) {
430 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
435 for_each_cpu(i, cpu_sibling_setup_mask) {
436 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
437 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
438 cpumask_set_cpu(i, c->llc_shared_map);
439 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
441 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
442 cpumask_set_cpu(i, cpu_core_mask(cpu));
443 cpumask_set_cpu(cpu, cpu_core_mask(i));
445 * Does this new cpu bringup a new core?
447 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
449 * for each core in package, increment
450 * the booted_cores for this new cpu
452 if (cpumask_first(cpu_sibling_mask(i)) == i)
455 * increment the core count for all
456 * the other cpus in this package
459 cpu_data(i).booted_cores++;
460 } else if (i != cpu && !c->booted_cores)
461 c->booted_cores = cpu_data(i).booted_cores;
466 /* maps the cpu to the sched domain representing multi-core */
467 const struct cpumask *cpu_coregroup_mask(int cpu)
469 struct cpuinfo_x86 *c = &cpu_data(cpu);
471 * For perf, we return last level cache shared map.
472 * And for power savings, we return cpu_core_map
474 if ((sched_mc_power_savings || sched_smt_power_savings) &&
475 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
476 return cpu_core_mask(cpu);
478 return c->llc_shared_map;
481 static void impress_friends(void)
484 unsigned long bogosum = 0;
486 * Allow the user to impress friends.
488 pr_debug("Before bogomips.\n");
489 for_each_possible_cpu(cpu)
490 if (cpumask_test_cpu(cpu, cpu_callout_mask))
491 bogosum += cpu_data(cpu).loops_per_jiffy;
493 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
496 (bogosum/(5000/HZ))%100);
498 pr_debug("Before bogocount - setting activated=1.\n");
501 void __inquire_remote_apic(int apicid)
503 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
504 char *names[] = { "ID", "VERSION", "SPIV" };
508 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
510 for (i = 0; i < ARRAY_SIZE(regs); i++) {
511 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
516 status = safe_apic_wait_icr_idle();
519 "a previous APIC delivery may have failed\n");
521 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
526 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
527 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
530 case APIC_ICR_RR_VALID:
531 status = apic_read(APIC_RRR);
532 printk(KERN_CONT "%08x\n", status);
535 printk(KERN_CONT "failed\n");
541 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
542 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
543 * won't ... remember to clear down the APIC, etc later.
546 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
548 unsigned long send_status, accept_status = 0;
552 /* Boot on the stack */
553 /* Kick the second */
554 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
556 pr_debug("Waiting for send to finish...\n");
557 send_status = safe_apic_wait_icr_idle();
560 * Give the other CPU some time to accept the IPI.
563 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
564 maxlvt = lapic_get_maxlvt();
565 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
566 apic_write(APIC_ESR, 0);
567 accept_status = (apic_read(APIC_ESR) & 0xEF);
569 pr_debug("NMI sent.\n");
572 printk(KERN_ERR "APIC never delivered???\n");
574 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
576 return (send_status | accept_status);
580 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
582 unsigned long send_status, accept_status = 0;
583 int maxlvt, num_starts, j;
585 maxlvt = lapic_get_maxlvt();
588 * Be paranoid about clearing APIC errors.
590 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
591 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
592 apic_write(APIC_ESR, 0);
596 pr_debug("Asserting INIT.\n");
599 * Turn INIT on target chip
604 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
607 pr_debug("Waiting for send to finish...\n");
608 send_status = safe_apic_wait_icr_idle();
612 pr_debug("Deasserting INIT.\n");
616 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
618 pr_debug("Waiting for send to finish...\n");
619 send_status = safe_apic_wait_icr_idle();
622 atomic_set(&init_deasserted, 1);
625 * Should we send STARTUP IPIs ?
627 * Determine this based on the APIC version.
628 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
630 if (APIC_INTEGRATED(apic_version[phys_apicid]))
636 * Paravirt / VMI wants a startup IPI hook here to set up the
637 * target processor state.
639 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
640 (unsigned long)stack_start.sp);
643 * Run STARTUP IPI loop.
645 pr_debug("#startup loops: %d.\n", num_starts);
647 for (j = 1; j <= num_starts; j++) {
648 pr_debug("Sending STARTUP #%d.\n", j);
649 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
650 apic_write(APIC_ESR, 0);
652 pr_debug("After apic_write.\n");
659 /* Boot on the stack */
660 /* Kick the second */
661 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
665 * Give the other CPU some time to accept the IPI.
669 pr_debug("Startup point 1.\n");
671 pr_debug("Waiting for send to finish...\n");
672 send_status = safe_apic_wait_icr_idle();
675 * Give the other CPU some time to accept the IPI.
678 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
679 apic_write(APIC_ESR, 0);
680 accept_status = (apic_read(APIC_ESR) & 0xEF);
681 if (send_status || accept_status)
684 pr_debug("After Startup.\n");
687 printk(KERN_ERR "APIC never delivered???\n");
689 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
691 return (send_status | accept_status);
695 struct work_struct work;
696 struct task_struct *idle;
697 struct completion done;
701 static void __cpuinit do_fork_idle(struct work_struct *work)
703 struct create_idle *c_idle =
704 container_of(work, struct create_idle, work);
706 c_idle->idle = fork_idle(c_idle->cpu);
707 complete(&c_idle->done);
710 /* reduce the number of lines printed when booting a large cpu count system */
711 static void __cpuinit announce_cpu(int cpu, int apicid)
713 static int current_node = -1;
714 int node = early_cpu_to_node(cpu);
716 if (system_state == SYSTEM_BOOTING) {
717 if (node != current_node) {
718 if (current_node > (-1))
721 pr_info("Booting Node %3d, Processors ", node);
723 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
726 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
731 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
732 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
733 * Returns zero if CPU booted OK, else error code from
734 * ->wakeup_secondary_cpu.
736 static int __cpuinit do_boot_cpu(int apicid, int cpu)
738 unsigned long boot_error = 0;
739 unsigned long start_ip;
741 struct create_idle c_idle = {
743 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
746 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle);
748 alternatives_smp_switch(1);
750 c_idle.idle = get_idle_for_cpu(cpu);
753 * We can't use kernel_thread since we must avoid to
754 * reschedule the child.
757 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
758 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
759 init_idle(c_idle.idle, cpu);
763 schedule_work(&c_idle.work);
764 wait_for_completion(&c_idle.done);
766 if (IS_ERR(c_idle.idle)) {
767 printk("failed fork for CPU %d\n", cpu);
768 destroy_work_on_stack(&c_idle.work);
769 return PTR_ERR(c_idle.idle);
772 set_idle_for_cpu(cpu, c_idle.idle);
774 per_cpu(current_task, cpu) = c_idle.idle;
776 /* Stack for startup_32 can be just as for start_secondary onwards */
778 initial_page_table = __pa(&trampoline_pg_dir);
780 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
781 initial_gs = per_cpu_offset(cpu);
782 per_cpu(kernel_stack, cpu) =
783 (unsigned long)task_stack_page(c_idle.idle) -
784 KERNEL_STACK_OFFSET + THREAD_SIZE;
786 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
787 initial_code = (unsigned long)start_secondary;
788 stack_start.sp = (void *) c_idle.idle->thread.sp;
790 /* start_ip had better be page-aligned! */
791 start_ip = setup_trampoline();
793 /* So we see what's up */
794 announce_cpu(cpu, apicid);
797 * This grunge runs the startup process for
798 * the targeted processor.
801 atomic_set(&init_deasserted, 0);
803 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
805 pr_debug("Setting warm reset code and vector.\n");
807 smpboot_setup_warm_reset_vector(start_ip);
809 * Be paranoid about clearing APIC errors.
811 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
812 apic_write(APIC_ESR, 0);
818 * Kick the secondary CPU. Use the method in the APIC driver
819 * if it's defined - or use an INIT boot APIC message otherwise:
821 if (apic->wakeup_secondary_cpu)
822 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
824 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
828 * allow APs to start initializing.
830 pr_debug("Before Callout %d.\n", cpu);
831 cpumask_set_cpu(cpu, cpu_callout_mask);
832 pr_debug("After Callout %d.\n", cpu);
835 * Wait 5s total for a response
837 for (timeout = 0; timeout < 50000; timeout++) {
838 if (cpumask_test_cpu(cpu, cpu_callin_mask))
839 break; /* It has booted */
842 * Allow other tasks to run while we wait for the
843 * AP to come online. This also gives a chance
844 * for the MTRR work(triggered by the AP coming online)
845 * to be completed in the stop machine context.
850 if (cpumask_test_cpu(cpu, cpu_callin_mask))
851 pr_debug("CPU%d: has booted.\n", cpu);
854 if (*((volatile unsigned char *)trampoline_base)
856 /* trampoline started but...? */
857 pr_err("CPU%d: Stuck ??\n", cpu);
859 /* trampoline code not run */
860 pr_err("CPU%d: Not responding.\n", cpu);
861 if (apic->inquire_remote_apic)
862 apic->inquire_remote_apic(apicid);
867 /* Try to put things back the way they were before ... */
868 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
870 /* was set by do_boot_cpu() */
871 cpumask_clear_cpu(cpu, cpu_callout_mask);
873 /* was set by cpu_init() */
874 cpumask_clear_cpu(cpu, cpu_initialized_mask);
876 set_cpu_present(cpu, false);
877 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
880 /* mark "stuck" area as not stuck */
881 *((volatile unsigned long *)trampoline_base) = 0;
883 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
885 * Cleanup possible dangling ends...
887 smpboot_restore_warm_reset_vector();
890 destroy_work_on_stack(&c_idle.work);
894 int __cpuinit native_cpu_up(unsigned int cpu)
896 int apicid = apic->cpu_present_to_apicid(cpu);
900 WARN_ON(irqs_disabled());
902 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
904 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
905 !physid_isset(apicid, phys_cpu_present_map)) {
906 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
911 * Already booted CPU?
913 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
914 pr_debug("do_boot_cpu %d Already started\n", cpu);
919 * Save current MTRR state in case it was changed since early boot
920 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
924 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
926 err = do_boot_cpu(apicid, cpu);
929 pr_debug("do_boot_cpu failed %d\n", err);
934 * Check TSC synchronization with the AP (keep irqs disabled
937 local_irq_save(flags);
938 check_tsc_sync_source(cpu);
939 local_irq_restore(flags);
941 while (!cpu_online(cpu)) {
943 touch_nmi_watchdog();
950 * Fall back to non SMP mode after errors.
952 * RED-PEN audit/test this more. I bet there is more state messed up here.
954 static __init void disable_smp(void)
956 init_cpu_present(cpumask_of(0));
957 init_cpu_possible(cpumask_of(0));
958 smpboot_clear_io_apic_irqs();
960 if (smp_found_config)
961 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
963 physid_set_mask_of_physid(0, &phys_cpu_present_map);
964 map_cpu_to_logical_apicid();
965 cpumask_set_cpu(0, cpu_sibling_mask(0));
966 cpumask_set_cpu(0, cpu_core_mask(0));
970 * Various sanity checks.
972 static int __init smp_sanity_check(unsigned max_cpus)
976 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
977 if (def_to_bigsmp && nr_cpu_ids > 8) {
982 "More than 8 CPUs detected - skipping them.\n"
983 "Use CONFIG_X86_BIGSMP.\n");
986 for_each_present_cpu(cpu) {
988 set_cpu_present(cpu, false);
993 for_each_possible_cpu(cpu) {
995 set_cpu_possible(cpu, false);
1003 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1005 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1006 hard_smp_processor_id());
1008 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1012 * If we couldn't find an SMP configuration at boot time,
1013 * get out of here now!
1015 if (!smp_found_config && !acpi_lapic) {
1017 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1019 if (APIC_init_uniprocessor())
1020 printk(KERN_NOTICE "Local APIC not detected."
1021 " Using dummy APIC emulation.\n");
1026 * Should not be necessary because the MP table should list the boot
1027 * CPU too, but we do it for the sake of robustness anyway.
1029 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1031 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1032 boot_cpu_physical_apicid);
1033 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1038 * If we couldn't find a local APIC, then get out of here now!
1040 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1042 if (!disable_apic) {
1043 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1044 boot_cpu_physical_apicid);
1045 pr_err("... forcing use of dummy APIC emulation."
1046 "(tell your hw vendor)\n");
1048 smpboot_clear_io_apic();
1049 arch_disable_smp_support();
1053 verify_local_APIC();
1056 * If SMP should be disabled, then really disable it!
1059 printk(KERN_INFO "SMP mode deactivated.\n");
1060 smpboot_clear_io_apic();
1062 localise_nmi_watchdog();
1066 end_local_APIC_setup();
1073 static void __init smp_cpu_index_default(void)
1076 struct cpuinfo_x86 *c;
1078 for_each_possible_cpu(i) {
1080 /* mark all to hotplug */
1081 c->cpu_index = nr_cpu_ids;
1086 * Prepare for SMP bootup. The MP table or ACPI has been read
1087 * earlier. Just do some sanity checking here and enable APIC mode.
1089 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1094 smp_cpu_index_default();
1095 current_cpu_data = boot_cpu_data;
1096 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1099 * Setup boot CPU information
1101 smp_store_cpu_info(0); /* Final full version of the data */
1102 #ifdef CONFIG_X86_32
1103 boot_cpu_logical_apicid = logical_smp_processor_id();
1105 current_thread_info()->cpu = 0; /* needed? */
1106 for_each_possible_cpu(i) {
1107 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1108 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1109 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL);
1111 set_cpu_sibling_map(0);
1114 default_setup_apic_routing();
1116 if (smp_sanity_check(max_cpus) < 0) {
1117 printk(KERN_INFO "SMP disabled\n");
1123 if (read_apic_id() != boot_cpu_physical_apicid) {
1124 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1125 read_apic_id(), boot_cpu_physical_apicid);
1126 /* Or can we switch back to PIC here? */
1133 * Switch from PIC to APIC mode.
1138 * Enable IO APIC before setting up error vector
1140 if (!skip_ioapic_setup && nr_ioapics)
1143 end_local_APIC_setup();
1145 map_cpu_to_logical_apicid();
1147 if (apic->setup_portio_remap)
1148 apic->setup_portio_remap();
1150 smpboot_setup_io_apic();
1152 * Set up local APIC timer on boot CPU.
1155 printk(KERN_INFO "CPU%d: ", 0);
1156 print_cpu_info(&cpu_data(0));
1157 x86_init.timers.setup_percpu_clockev();
1162 set_mtrr_aps_delayed_init();
1167 void arch_enable_nonboot_cpus_begin(void)
1169 set_mtrr_aps_delayed_init();
1172 void arch_enable_nonboot_cpus_end(void)
1178 * Early setup to make printk work.
1180 void __init native_smp_prepare_boot_cpu(void)
1182 int me = smp_processor_id();
1183 switch_to_new_gdt(me);
1184 /* already set me in cpu_online_mask in boot_cpu_init() */
1185 cpumask_set_cpu(me, cpu_callout_mask);
1186 per_cpu(cpu_state, me) = CPU_ONLINE;
1189 void __init native_smp_cpus_done(unsigned int max_cpus)
1191 pr_debug("Boot done.\n");
1194 #ifdef CONFIG_X86_IO_APIC
1195 setup_ioapic_dest();
1197 check_nmi_watchdog();
1201 static int __initdata setup_possible_cpus = -1;
1202 static int __init _setup_possible_cpus(char *str)
1204 get_option(&str, &setup_possible_cpus);
1207 early_param("possible_cpus", _setup_possible_cpus);
1211 * cpu_possible_mask should be static, it cannot change as cpu's
1212 * are onlined, or offlined. The reason is per-cpu data-structures
1213 * are allocated by some modules at init time, and dont expect to
1214 * do this dynamically on cpu arrival/departure.
1215 * cpu_present_mask on the other hand can change dynamically.
1216 * In case when cpu_hotplug is not compiled, then we resort to current
1217 * behaviour, which is cpu_possible == cpu_present.
1220 * Three ways to find out the number of additional hotplug CPUs:
1221 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1222 * - The user can overwrite it with possible_cpus=NUM
1223 * - Otherwise don't reserve additional CPUs.
1224 * We do this because additional CPUs waste a lot of memory.
1227 __init void prefill_possible_map(void)
1231 /* no processor from mptable or madt */
1232 if (!num_processors)
1235 i = setup_max_cpus ?: 1;
1236 if (setup_possible_cpus == -1) {
1237 possible = num_processors;
1238 #ifdef CONFIG_HOTPLUG_CPU
1240 possible += disabled_cpus;
1246 possible = setup_possible_cpus;
1248 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1250 /* nr_cpu_ids could be reduced via nr_cpus= */
1251 if (possible > nr_cpu_ids) {
1253 "%d Processors exceeds NR_CPUS limit of %d\n",
1254 possible, nr_cpu_ids);
1255 possible = nr_cpu_ids;
1258 #ifdef CONFIG_HOTPLUG_CPU
1259 if (!setup_max_cpus)
1263 "%d Processors exceeds max_cpus limit of %u\n",
1264 possible, setup_max_cpus);
1268 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1269 possible, max_t(int, possible - num_processors, 0));
1271 for (i = 0; i < possible; i++)
1272 set_cpu_possible(i, true);
1273 for (; i < NR_CPUS; i++)
1274 set_cpu_possible(i, false);
1276 nr_cpu_ids = possible;
1279 #ifdef CONFIG_HOTPLUG_CPU
1281 static void remove_siblinginfo(int cpu)
1284 struct cpuinfo_x86 *c = &cpu_data(cpu);
1286 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1287 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1289 * last thread sibling in this cpu core going down
1291 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1292 cpu_data(sibling).booted_cores--;
1295 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1296 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1297 cpumask_clear(cpu_sibling_mask(cpu));
1298 cpumask_clear(cpu_core_mask(cpu));
1299 c->phys_proc_id = 0;
1301 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1304 static void __ref remove_cpu_from_maps(int cpu)
1306 set_cpu_online(cpu, false);
1307 cpumask_clear_cpu(cpu, cpu_callout_mask);
1308 cpumask_clear_cpu(cpu, cpu_callin_mask);
1309 /* was set by cpu_init() */
1310 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1311 numa_remove_cpu(cpu);
1314 void cpu_disable_common(void)
1316 int cpu = smp_processor_id();
1318 remove_siblinginfo(cpu);
1320 /* It's now safe to remove this processor from the online map */
1322 remove_cpu_from_maps(cpu);
1323 unlock_vector_lock();
1327 int native_cpu_disable(void)
1329 int cpu = smp_processor_id();
1332 * Perhaps use cpufreq to drop frequency, but that could go
1333 * into generic code.
1335 * We won't take down the boot processor on i386 due to some
1336 * interrupts only being able to be serviced by the BSP.
1337 * Especially so if we're not using an IOAPIC -zwane
1342 if (nmi_watchdog == NMI_LOCAL_APIC)
1343 stop_apic_nmi_watchdog(NULL);
1346 cpu_disable_common();
1350 void native_cpu_die(unsigned int cpu)
1352 /* We don't do anything here: idle task is faking death itself. */
1355 for (i = 0; i < 10; i++) {
1356 /* They ack this in play_dead by setting CPU_DEAD */
1357 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1358 if (system_state == SYSTEM_RUNNING)
1359 pr_info("CPU %u is now offline\n", cpu);
1361 if (1 == num_online_cpus())
1362 alternatives_smp_switch(0);
1367 pr_err("CPU %u didn't die...\n", cpu);
1370 void play_dead_common(void)
1373 reset_lazy_tlbstate();
1374 irq_ctx_exit(raw_smp_processor_id());
1375 c1e_remove_cpu(raw_smp_processor_id());
1379 __get_cpu_var(cpu_state) = CPU_DEAD;
1382 * With physical CPU hotplug, we should halt the cpu
1384 local_irq_disable();
1388 * We need to flush the caches before going to sleep, lest we have
1389 * dirty data in our caches when we come back up.
1391 static inline void mwait_play_dead(void)
1393 unsigned int eax, ebx, ecx, edx;
1394 unsigned int highest_cstate = 0;
1395 unsigned int highest_subcstate = 0;
1399 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT))
1401 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH))
1403 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1406 eax = CPUID_MWAIT_LEAF;
1408 native_cpuid(&eax, &ebx, &ecx, &edx);
1411 * eax will be 0 if EDX enumeration is not valid.
1412 * Initialized below to cstate, sub_cstate value when EDX is valid.
1414 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1417 edx >>= MWAIT_SUBSTATE_SIZE;
1418 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1419 if (edx & MWAIT_SUBSTATE_MASK) {
1421 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1424 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1425 (highest_subcstate - 1);
1429 * This should be a memory location in a cache line which is
1430 * unlikely to be touched by other processors. The actual
1431 * content is immaterial as it is not actually modified in any way.
1433 mwait_ptr = ¤t_thread_info()->flags;
1439 * The CLFLUSH is a workaround for erratum AAI65 for
1440 * the Xeon 7400 series. It's not clear it is actually
1441 * needed, but it should be harmless in either case.
1442 * The WBINVD is insufficient due to the spurious-wakeup
1443 * case where we return around the loop.
1446 __monitor(mwait_ptr, 0, 0);
1452 static inline void hlt_play_dead(void)
1454 if (current_cpu_data.x86 >= 4)
1462 void native_play_dead(void)
1465 tboot_shutdown(TB_SHUTDOWN_WFS);
1467 mwait_play_dead(); /* Only returns on failure */
1471 #else /* ... !CONFIG_HOTPLUG_CPU */
1472 int native_cpu_disable(void)
1477 void native_cpu_die(unsigned int cpu)
1479 /* We said "no" in __cpu_disable */
1483 void native_play_dead(void)