arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39
  40 #include <asm/apic.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/desc.h>
  44 #include <asm/debugreg.h>
  45 #include <asm/kvm_para.h>
  46 #include <asm/irq_remapping.h>
  47
  48 #include <asm/virtext.h>
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id svm_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  61
  62 #define IOPM_ALLOC_ORDER 2
  63 #define MSRPM_ALLOC_ORDER 1
  64
  65 #define SEG_TYPE_LDT 2
  66 #define SEG_TYPE_BUSY_TSS16 3
  67
  68 #define SVM_FEATURE_NPT            (1 <<  0)
  69 #define SVM_FEATURE_LBRV           (1 <<  1)
  70 #define SVM_FEATURE_SVML           (1 <<  2)
  71 #define SVM_FEATURE_NRIP           (1 <<  3)
  72 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  73 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  74 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  75 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  76 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  77
  78 #define SVM_AVIC_DOORBELL       0xc001011b
  79
  80 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  81 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  82 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  83
  84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  85
  86 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  87 #define TSC_RATIO_MIN           0x0000000000000001ULL
  88 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  89
  90 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  91
  92 /*
  93  * 0xff is broadcast, so the max index allowed for physical APIC ID
  94  * table is 0xfe.  APIC IDs above 0xff are reserved.
  95  */
  96 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  97
  98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
  99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 101
 102 /* AVIC GATAG is encoded using VM and VCPU IDs */
 103 #define AVIC_VCPU_ID_BITS               8
 104 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 105
 106 #define AVIC_VM_ID_BITS                 24
 107 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 108 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 109
 110 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 111                                                 (y & AVIC_VCPU_ID_MASK))
 112 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 113 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 114
 115 static bool erratum_383_found __read_mostly;
 116
 117 static const u32 host_save_user_msrs[] = {
 118 #ifdef CONFIG_X86_64
 119         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 120         MSR_FS_BASE,
 121 #endif
 122         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 123         MSR_TSC_AUX,
 124 };
 125
 126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 127
 128 struct kvm_vcpu;
 129
 130 struct nested_state {
 131         struct vmcb *hsave;
 132         u64 hsave_msr;
 133         u64 vm_cr_msr;
 134         u64 vmcb;
 135
 136         /* These are the merged vectors */
 137         u32 *msrpm;
 138
 139         /* gpa pointers to the real vectors */
 140         u64 vmcb_msrpm;
 141         u64 vmcb_iopm;
 142
 143         /* A VMEXIT is required but not yet emulated */
 144         bool exit_required;
 145
 146         /* cache for intercepts of the guest */
 147         u32 intercept_cr;
 148         u32 intercept_dr;
 149         u32 intercept_exceptions;
 150         u64 intercept;
 151
 152         /* Nested Paging related state */
 153         u64 nested_cr3;
 154 };
 155
 156 #define MSRPM_OFFSETS   16
 157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 158
 159 /*
 160  * Set osvw_len to higher value when updated Revision Guides
 161  * are published and we know what the new status bits are
 162  */
 163 static uint64_t osvw_len = 4, osvw_status;
 164
 165 struct vcpu_svm {
 166         struct kvm_vcpu vcpu;
 167         struct vmcb *vmcb;
 168         unsigned long vmcb_pa;
 169         struct svm_cpu_data *svm_data;
 170         uint64_t asid_generation;
 171         uint64_t sysenter_esp;
 172         uint64_t sysenter_eip;
 173         uint64_t tsc_aux;
 174
 175         u64 next_rip;
 176
 177         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 178         struct {
 179                 u16 fs;
 180                 u16 gs;
 181                 u16 ldt;
 182                 u64 gs_base;
 183         } host;
 184
 185         u32 *msrpm;
 186
 187         ulong nmi_iret_rip;
 188
 189         struct nested_state nested;
 190
 191         bool nmi_singlestep;
 192
 193         unsigned int3_injected;
 194         unsigned long int3_rip;
 195         u32 apf_reason;
 196
 197         /* cached guest cpuid flags for faster access */
 198         bool nrips_enabled      : 1;
 199
 200         u32 ldr_reg;
 201         struct page *avic_backing_page;
 202         u64 *avic_physical_id_cache;
 203         bool avic_is_running;
 204
 205         /*
 206          * Per-vcpu list of struct amd_svm_iommu_ir:
 207          * This is used mainly to store interrupt remapping information used
 208          * when update the vcpu affinity. This avoids the need to scan for
 209          * IRTE and try to match ga_tag in the IOMMU driver.
 210          */
 211         struct list_head ir_list;
 212         spinlock_t ir_list_lock;
 213 };
 214
 215 /*
 216  * This is a wrapper of struct amd_iommu_ir_data.
 217  */
 218 struct amd_svm_iommu_ir {
 219         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 220         void *data;             /* Storing pointer to struct amd_ir_data */
 221 };
 222
 223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 225
 226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 230
 231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 232 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 233
 234 #define MSR_INVALID                     0xffffffffU
 235
 236 static const struct svm_direct_access_msrs {
 237         u32 index;   /* Index of the MSR */
 238         bool always; /* True if intercept is always on */
 239 } direct_access_msrs[] = {
 240         { .index = MSR_STAR,                            .always = true  },
 241         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 242 #ifdef CONFIG_X86_64
 243         { .index = MSR_GS_BASE,                         .always = true  },
 244         { .index = MSR_FS_BASE,                         .always = true  },
 245         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 246         { .index = MSR_LSTAR,                           .always = true  },
 247         { .index = MSR_CSTAR,                           .always = true  },
 248         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 249 #endif
 250         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 251         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 252         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 253         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 254         { .index = MSR_INVALID,                         .always = false },
 255 };
 256
 257 /* enable NPT for AMD64 and X86 with PAE */
 258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 259 static bool npt_enabled = true;
 260 #else
 261 static bool npt_enabled;
 262 #endif
 263
 264 /* allow nested paging (virtualized MMU) for all guests */
 265 static int npt = true;
 266 module_param(npt, int, S_IRUGO);
 267
 268 /* allow nested virtualization in KVM/SVM */
 269 static int nested = true;
 270 module_param(nested, int, S_IRUGO);
 271
 272 /* enable / disable AVIC */
 273 static int avic;
 274 #ifdef CONFIG_X86_LOCAL_APIC
 275 module_param(avic, int, S_IRUGO);
 276 #endif
 277
 278 /* AVIC VM ID bit masks and lock */
 279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 280 static DEFINE_SPINLOCK(avic_vm_id_lock);
 281
 282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 284 static void svm_complete_interrupts(struct vcpu_svm *svm);
 285
 286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 287 static int nested_svm_intercept(struct vcpu_svm *svm);
 288 static int nested_svm_vmexit(struct vcpu_svm *svm);
 289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 290                                       bool has_error_code, u32 error_code);
 291
 292 enum {
 293         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 294                             pause filter count */
 295         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 296         VMCB_ASID,       /* ASID */
 297         VMCB_INTR,       /* int_ctl, int_vector */
 298         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 299         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 300         VMCB_DR,         /* DR6, DR7 */
 301         VMCB_DT,         /* GDT, IDT */
 302         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 303         VMCB_CR2,        /* CR2 only */
 304         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 305         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 306                           * AVIC PHYSICAL_TABLE pointer,
 307                           * AVIC LOGICAL_TABLE pointer
 308                           */
 309         VMCB_DIRTY_MAX,
 310 };
 311
 312 /* TPR and CR2 are always written before VMRUN */
 313 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 314
 315 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 316
 317 static inline void mark_all_dirty(struct vmcb *vmcb)
 318 {
 319         vmcb->control.clean = 0;
 320 }
 321
 322 static inline void mark_all_clean(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 325                                & ~VMCB_ALWAYS_DIRTY_MASK;
 326 }
 327
 328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 329 {
 330         vmcb->control.clean &= ~(1 << bit);
 331 }
 332
 333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 334 {
 335         return container_of(vcpu, struct vcpu_svm, vcpu);
 336 }
 337
 338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 339 {
 340         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 341         mark_dirty(svm->vmcb, VMCB_AVIC);
 342 }
 343
 344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347         u64 *entry = svm->avic_physical_id_cache;
 348
 349         if (!entry)
 350                 return false;
 351
 352         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 353 }
 354
 355 static void recalc_intercepts(struct vcpu_svm *svm)
 356 {
 357         struct vmcb_control_area *c, *h;
 358         struct nested_state *g;
 359
 360         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 361
 362         if (!is_guest_mode(&svm->vcpu))
 363                 return;
 364
 365         c = &svm->vmcb->control;
 366         h = &svm->nested.hsave->control;
 367         g = &svm->nested;
 368
 369         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 370         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 371         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 372         c->intercept = h->intercept | g->intercept;
 373 }
 374
 375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 376 {
 377         if (is_guest_mode(&svm->vcpu))
 378                 return svm->nested.hsave;
 379         else
 380                 return svm->vmcb;
 381 }
 382
 383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 384 {
 385         struct vmcb *vmcb = get_host_vmcb(svm);
 386
 387         vmcb->control.intercept_cr |= (1U << bit);
 388
 389         recalc_intercepts(svm);
 390 }
 391
 392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 393 {
 394         struct vmcb *vmcb = get_host_vmcb(svm);
 395
 396         vmcb->control.intercept_cr &= ~(1U << bit);
 397
 398         recalc_intercepts(svm);
 399 }
 400
 401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 402 {
 403         struct vmcb *vmcb = get_host_vmcb(svm);
 404
 405         return vmcb->control.intercept_cr & (1U << bit);
 406 }
 407
 408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 409 {
 410         struct vmcb *vmcb = get_host_vmcb(svm);
 411
 412         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 413                 | (1 << INTERCEPT_DR1_READ)
 414                 | (1 << INTERCEPT_DR2_READ)
 415                 | (1 << INTERCEPT_DR3_READ)
 416                 | (1 << INTERCEPT_DR4_READ)
 417                 | (1 << INTERCEPT_DR5_READ)
 418                 | (1 << INTERCEPT_DR6_READ)
 419                 | (1 << INTERCEPT_DR7_READ)
 420                 | (1 << INTERCEPT_DR0_WRITE)
 421                 | (1 << INTERCEPT_DR1_WRITE)
 422                 | (1 << INTERCEPT_DR2_WRITE)
 423                 | (1 << INTERCEPT_DR3_WRITE)
 424                 | (1 << INTERCEPT_DR4_WRITE)
 425                 | (1 << INTERCEPT_DR5_WRITE)
 426                 | (1 << INTERCEPT_DR6_WRITE)
 427                 | (1 << INTERCEPT_DR7_WRITE);
 428
 429         recalc_intercepts(svm);
 430 }
 431
 432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 433 {
 434         struct vmcb *vmcb = get_host_vmcb(svm);
 435
 436         vmcb->control.intercept_dr = 0;
 437
 438         recalc_intercepts(svm);
 439 }
 440
 441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 442 {
 443         struct vmcb *vmcb = get_host_vmcb(svm);
 444
 445         vmcb->control.intercept_exceptions |= (1U << bit);
 446
 447         recalc_intercepts(svm);
 448 }
 449
 450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 451 {
 452         struct vmcb *vmcb = get_host_vmcb(svm);
 453
 454         vmcb->control.intercept_exceptions &= ~(1U << bit);
 455
 456         recalc_intercepts(svm);
 457 }
 458
 459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 460 {
 461         struct vmcb *vmcb = get_host_vmcb(svm);
 462
 463         vmcb->control.intercept |= (1ULL << bit);
 464
 465         recalc_intercepts(svm);
 466 }
 467
 468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 469 {
 470         struct vmcb *vmcb = get_host_vmcb(svm);
 471
 472         vmcb->control.intercept &= ~(1ULL << bit);
 473
 474         recalc_intercepts(svm);
 475 }
 476
 477 static inline void enable_gif(struct vcpu_svm *svm)
 478 {
 479         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 480 }
 481
 482 static inline void disable_gif(struct vcpu_svm *svm)
 483 {
 484         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 485 }
 486
 487 static inline bool gif_set(struct vcpu_svm *svm)
 488 {
 489         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 490 }
 491
 492 static unsigned long iopm_base;
 493
 494 struct kvm_ldttss_desc {
 495         u16 limit0;
 496         u16 base0;
 497         unsigned base1:8, type:5, dpl:2, p:1;
 498         unsigned limit1:4, zero0:3, g:1, base2:8;
 499         u32 base3;
 500         u32 zero1;
 501 } __attribute__((packed));
 502
 503 struct svm_cpu_data {
 504         int cpu;
 505
 506         u64 asid_generation;
 507         u32 max_asid;
 508         u32 next_asid;
 509         struct kvm_ldttss_desc *tss_desc;
 510
 511         struct page *save_area;
 512 };
 513
 514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 515
 516 struct svm_init_data {
 517         int cpu;
 518         int r;
 519 };
 520
 521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 522
 523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 524 #define MSRS_RANGE_SIZE 2048
 525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 526
 527 static u32 svm_msrpm_offset(u32 msr)
 528 {
 529         u32 offset;
 530         int i;
 531
 532         for (i = 0; i < NUM_MSR_MAPS; i++) {
 533                 if (msr < msrpm_ranges[i] ||
 534                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 535                         continue;
 536
 537                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 538                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 539
 540                 /* Now we have the u8 offset - but need the u32 offset */
 541                 return offset / 4;
 542         }
 543
 544         /* MSR not in any range */
 545         return MSR_INVALID;
 546 }
 547
 548 #define MAX_INST_SIZE 15
 549
 550 static inline void clgi(void)
 551 {
 552         asm volatile (__ex(SVM_CLGI));
 553 }
 554
 555 static inline void stgi(void)
 556 {
 557         asm volatile (__ex(SVM_STGI));
 558 }
 559
 560 static inline void invlpga(unsigned long addr, u32 asid)
 561 {
 562         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 563 }
 564
 565 static int get_npt_level(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         return PT64_ROOT_LEVEL;
 569 #else
 570         return PT32E_ROOT_LEVEL;
 571 #endif
 572 }
 573
 574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 575 {
 576         vcpu->arch.efer = efer;
 577         if (!npt_enabled && !(efer & EFER_LMA))
 578                 efer &= ~EFER_LME;
 579
 580         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 581         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 582 }
 583
 584 static int is_external_interrupt(u32 info)
 585 {
 586         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 587         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 588 }
 589
 590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 591 {
 592         struct vcpu_svm *svm = to_svm(vcpu);
 593         u32 ret = 0;
 594
 595         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 596                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 597         return ret;
 598 }
 599
 600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         if (mask == 0)
 605                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 606         else
 607                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 608
 609 }
 610
 611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         if (svm->vmcb->control.next_rip != 0) {
 616                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 617                 svm->next_rip = svm->vmcb->control.next_rip;
 618         }
 619
 620         if (!svm->next_rip) {
 621                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 622                                 EMULATE_DONE)
 623                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 624                 return;
 625         }
 626         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 627                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 628                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 629
 630         kvm_rip_write(vcpu, svm->next_rip);
 631         svm_set_interrupt_shadow(vcpu, 0);
 632 }
 633
 634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 635                                 bool has_error_code, u32 error_code,
 636                                 bool reinject)
 637 {
 638         struct vcpu_svm *svm = to_svm(vcpu);
 639
 640         /*
 641          * If we are within a nested VM we'd better #VMEXIT and let the guest
 642          * handle the exception
 643          */
 644         if (!reinject &&
 645             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 646                 return;
 647
 648         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 649                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 650
 651                 /*
 652                  * For guest debugging where we have to reinject #BP if some
 653                  * INT3 is guest-owned:
 654                  * Emulate nRIP by moving RIP forward. Will fail if injection
 655                  * raises a fault that is not intercepted. Still better than
 656                  * failing in all cases.
 657                  */
 658                 skip_emulated_instruction(&svm->vcpu);
 659                 rip = kvm_rip_read(&svm->vcpu);
 660                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 661                 svm->int3_injected = rip - old_rip;
 662         }
 663
 664         svm->vmcb->control.event_inj = nr
 665                 | SVM_EVTINJ_VALID
 666                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 667                 | SVM_EVTINJ_TYPE_EXEPT;
 668         svm->vmcb->control.event_inj_err = error_code;
 669 }
 670
 671 static void svm_init_erratum_383(void)
 672 {
 673         u32 low, high;
 674         int err;
 675         u64 val;
 676
 677         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 678                 return;
 679
 680         /* Use _safe variants to not break nested virtualization */
 681         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 682         if (err)
 683                 return;
 684
 685         val |= (1ULL << 47);
 686
 687         low  = lower_32_bits(val);
 688         high = upper_32_bits(val);
 689
 690         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 691
 692         erratum_383_found = true;
 693 }
 694
 695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 696 {
 697         /*
 698          * Guests should see errata 400 and 415 as fixed (assuming that
 699          * HLT and IO instructions are intercepted).
 700          */
 701         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 702         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 703
 704         /*
 705          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 706          * all osvw.status bits inside that length, including bit 0 (which is
 707          * reserved for erratum 298), are valid. However, if host processor's
 708          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 709          * be conservative here and therefore we tell the guest that erratum 298
 710          * is present (because we really don't know).
 711          */
 712         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 713                 vcpu->arch.osvw.status |= 1;
 714 }
 715
 716 static int has_svm(void)
 717 {
 718         const char *msg;
 719
 720         if (!cpu_has_svm(&msg)) {
 721                 printk(KERN_INFO "has_svm: %s\n", msg);
 722                 return 0;
 723         }
 724
 725         return 1;
 726 }
 727
 728 static void svm_hardware_disable(void)
 729 {
 730         /* Make sure we clean up behind us */
 731         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 732                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 733
 734         cpu_svm_disable();
 735
 736         amd_pmu_disable_virt();
 737 }
 738
 739 static int svm_hardware_enable(void)
 740 {
 741
 742         struct svm_cpu_data *sd;
 743         uint64_t efer;
 744         struct desc_ptr gdt_descr;
 745         struct desc_struct *gdt;
 746         int me = raw_smp_processor_id();
 747
 748         rdmsrl(MSR_EFER, efer);
 749         if (efer & EFER_SVME)
 750                 return -EBUSY;
 751
 752         if (!has_svm()) {
 753                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 754                 return -EINVAL;
 755         }
 756         sd = per_cpu(svm_data, me);
 757         if (!sd) {
 758                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 759                 return -EINVAL;
 760         }
 761
 762         sd->asid_generation = 1;
 763         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 764         sd->next_asid = sd->max_asid + 1;
 765
 766         native_store_gdt(&gdt_descr);
 767         gdt = (struct desc_struct *)gdt_descr.address;
 768         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 769
 770         wrmsrl(MSR_EFER, efer | EFER_SVME);
 771
 772         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 773
 774         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 775                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 776                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 777         }
 778
 779
 780         /*
 781          * Get OSVW bits.
 782          *
 783          * Note that it is possible to have a system with mixed processor
 784          * revisions and therefore different OSVW bits. If bits are not the same
 785          * on different processors then choose the worst case (i.e. if erratum
 786          * is present on one processor and not on another then assume that the
 787          * erratum is present everywhere).
 788          */
 789         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 790                 uint64_t len, status = 0;
 791                 int err;
 792
 793                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 794                 if (!err)
 795                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 796                                                       &err);
 797
 798                 if (err)
 799                         osvw_status = osvw_len = 0;
 800                 else {
 801                         if (len < osvw_len)
 802                                 osvw_len = len;
 803                         osvw_status |= status;
 804                         osvw_status &= (1ULL << osvw_len) - 1;
 805                 }
 806         } else
 807                 osvw_status = osvw_len = 0;
 808
 809         svm_init_erratum_383();
 810
 811         amd_pmu_enable_virt();
 812
 813         return 0;
 814 }
 815
 816 static void svm_cpu_uninit(int cpu)
 817 {
 818         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 819
 820         if (!sd)
 821                 return;
 822
 823         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 824         __free_page(sd->save_area);
 825         kfree(sd);
 826 }
 827
 828 static int svm_cpu_init(int cpu)
 829 {
 830         struct svm_cpu_data *sd;
 831         int r;
 832
 833         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 834         if (!sd)
 835                 return -ENOMEM;
 836         sd->cpu = cpu;
 837         sd->save_area = alloc_page(GFP_KERNEL);
 838         r = -ENOMEM;
 839         if (!sd->save_area)
 840                 goto err_1;
 841
 842         per_cpu(svm_data, cpu) = sd;
 843
 844         return 0;
 845
 846 err_1:
 847         kfree(sd);
 848         return r;
 849
 850 }
 851
 852 static bool valid_msr_intercept(u32 index)
 853 {
 854         int i;
 855
 856         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 857                 if (direct_access_msrs[i].index == index)
 858                         return true;
 859
 860         return false;
 861 }
 862
 863 static void set_msr_interception(u32 *msrpm, unsigned msr,
 864                                  int read, int write)
 865 {
 866         u8 bit_read, bit_write;
 867         unsigned long tmp;
 868         u32 offset;
 869
 870         /*
 871          * If this warning triggers extend the direct_access_msrs list at the
 872          * beginning of the file
 873          */
 874         WARN_ON(!valid_msr_intercept(msr));
 875
 876         offset    = svm_msrpm_offset(msr);
 877         bit_read  = 2 * (msr & 0x0f);
 878         bit_write = 2 * (msr & 0x0f) + 1;
 879         tmp       = msrpm[offset];
 880
 881         BUG_ON(offset == MSR_INVALID);
 882
 883         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 884         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 885
 886         msrpm[offset] = tmp;
 887 }
 888
 889 static void svm_vcpu_init_msrpm(u32 *msrpm)
 890 {
 891         int i;
 892
 893         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 894
 895         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 896                 if (!direct_access_msrs[i].always)
 897                         continue;
 898
 899                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 900         }
 901 }
 902
 903 static void add_msr_offset(u32 offset)
 904 {
 905         int i;
 906
 907         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 908
 909                 /* Offset already in list? */
 910                 if (msrpm_offsets[i] == offset)
 911                         return;
 912
 913                 /* Slot used by another offset? */
 914                 if (msrpm_offsets[i] != MSR_INVALID)
 915                         continue;
 916
 917                 /* Add offset to list */
 918                 msrpm_offsets[i] = offset;
 919
 920                 return;
 921         }
 922
 923         /*
 924          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 925          * increase MSRPM_OFFSETS in this case.
 926          */
 927         BUG();
 928 }
 929
 930 static void init_msrpm_offsets(void)
 931 {
 932         int i;
 933
 934         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 935
 936         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 937                 u32 offset;
 938
 939                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 940                 BUG_ON(offset == MSR_INVALID);
 941
 942                 add_msr_offset(offset);
 943         }
 944 }
 945
 946 static void svm_enable_lbrv(struct vcpu_svm *svm)
 947 {
 948         u32 *msrpm = svm->msrpm;
 949
 950         svm->vmcb->control.lbr_ctl = 1;
 951         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 953         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 954         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 955 }
 956
 957 static void svm_disable_lbrv(struct vcpu_svm *svm)
 958 {
 959         u32 *msrpm = svm->msrpm;
 960
 961         svm->vmcb->control.lbr_ctl = 0;
 962         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 964         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 965         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 966 }
 967
 968 /* Note:
 969  * This hash table is used to map VM_ID to a struct kvm_arch,
 970  * when handling AMD IOMMU GALOG notification to schedule in
 971  * a particular vCPU.
 972  */
 973 #define SVM_VM_DATA_HASH_BITS   8
 974 DECLARE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 975 static spinlock_t svm_vm_data_hash_lock;
 976
 977 /* Note:
 978  * This function is called from IOMMU driver to notify
 979  * SVM to schedule in a particular vCPU of a particular VM.
 980  */
 981 static int avic_ga_log_notifier(u32 ga_tag)
 982 {
 983         unsigned long flags;
 984         struct kvm_arch *ka = NULL;
 985         struct kvm_vcpu *vcpu = NULL;
 986         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 987         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
 988
 989         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
 990
 991         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
 992         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
 993                 struct kvm *kvm = container_of(ka, struct kvm, arch);
 994                 struct kvm_arch *vm_data = &kvm->arch;
 995
 996                 if (vm_data->avic_vm_id != vm_id)
 997                         continue;
 998                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
 999                 break;
1000         }
1001         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1002
1003         if (!vcpu)
1004                 return 0;
1005
1006         /* Note:
1007          * At this point, the IOMMU should have already set the pending
1008          * bit in the vAPIC backing page. So, we just need to schedule
1009          * in the vcpu.
1010          */
1011         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1012                 kvm_vcpu_wake_up(vcpu);
1013
1014         return 0;
1015 }
1016
1017 static __init int svm_hardware_setup(void)
1018 {
1019         int cpu;
1020         struct page *iopm_pages;
1021         void *iopm_va;
1022         int r;
1023
1024         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1025
1026         if (!iopm_pages)
1027                 return -ENOMEM;
1028
1029         iopm_va = page_address(iopm_pages);
1030         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1031         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1032
1033         init_msrpm_offsets();
1034
1035         if (boot_cpu_has(X86_FEATURE_NX))
1036                 kvm_enable_efer_bits(EFER_NX);
1037
1038         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1039                 kvm_enable_efer_bits(EFER_FFXSR);
1040
1041         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1042                 kvm_has_tsc_control = true;
1043                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1044                 kvm_tsc_scaling_ratio_frac_bits = 32;
1045         }
1046
1047         if (nested) {
1048                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1049                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1050         }
1051
1052         for_each_possible_cpu(cpu) {
1053                 r = svm_cpu_init(cpu);
1054                 if (r)
1055                         goto err;
1056         }
1057
1058         if (!boot_cpu_has(X86_FEATURE_NPT))
1059                 npt_enabled = false;
1060
1061         if (npt_enabled && !npt) {
1062                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1063                 npt_enabled = false;
1064         }
1065
1066         if (npt_enabled) {
1067                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1068                 kvm_enable_tdp();
1069         } else
1070                 kvm_disable_tdp();
1071
1072         if (avic) {
1073                 if (!npt_enabled ||
1074                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1075                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1076                         avic = false;
1077                 } else {
1078                         pr_info("AVIC enabled\n");
1079
1080                         hash_init(svm_vm_data_hash);
1081                         spin_lock_init(&svm_vm_data_hash_lock);
1082                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1083                 }
1084         }
1085
1086         return 0;
1087
1088 err:
1089         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1090         iopm_base = 0;
1091         return r;
1092 }
1093
1094 static __exit void svm_hardware_unsetup(void)
1095 {
1096         int cpu;
1097
1098         for_each_possible_cpu(cpu)
1099                 svm_cpu_uninit(cpu);
1100
1101         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1102         iopm_base = 0;
1103 }
1104
1105 static void init_seg(struct vmcb_seg *seg)
1106 {
1107         seg->selector = 0;
1108         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1109                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1110         seg->limit = 0xffff;
1111         seg->base = 0;
1112 }
1113
1114 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1115 {
1116         seg->selector = 0;
1117         seg->attrib = SVM_SELECTOR_P_MASK | type;
1118         seg->limit = 0xffff;
1119         seg->base = 0;
1120 }
1121
1122 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1123 {
1124         struct vcpu_svm *svm = to_svm(vcpu);
1125
1126         return svm->vmcb->control.tsc_offset;
1127 }
1128
1129 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1130 {
1131         struct vcpu_svm *svm = to_svm(vcpu);
1132         u64 g_tsc_offset = 0;
1133
1134         if (is_guest_mode(vcpu)) {
1135                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1136                                svm->nested.hsave->control.tsc_offset;
1137                 svm->nested.hsave->control.tsc_offset = offset;
1138         } else
1139                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1140                                            svm->vmcb->control.tsc_offset,
1141                                            offset);
1142
1143         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1144
1145         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1146 }
1147
1148 static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
1149 {
1150         struct vcpu_svm *svm = to_svm(vcpu);
1151
1152         svm->vmcb->control.tsc_offset += adjustment;
1153         if (is_guest_mode(vcpu))
1154                 svm->nested.hsave->control.tsc_offset += adjustment;
1155         else
1156                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1157                                      svm->vmcb->control.tsc_offset - adjustment,
1158                                      svm->vmcb->control.tsc_offset);
1159
1160         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1161 }
1162
1163 static void avic_init_vmcb(struct vcpu_svm *svm)
1164 {
1165         struct vmcb *vmcb = svm->vmcb;
1166         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1167         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1168         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1169         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1170
1171         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1172         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1173         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1174         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1175         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1176         svm->vcpu.arch.apicv_active = true;
1177 }
1178
1179 static void init_vmcb(struct vcpu_svm *svm)
1180 {
1181         struct vmcb_control_area *control = &svm->vmcb->control;
1182         struct vmcb_save_area *save = &svm->vmcb->save;
1183
1184         svm->vcpu.fpu_active = 1;
1185         svm->vcpu.arch.hflags = 0;
1186
1187         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1188         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1189         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1190         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1191         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1192         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1193         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1194                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1195
1196         set_dr_intercepts(svm);
1197
1198         set_exception_intercept(svm, PF_VECTOR);
1199         set_exception_intercept(svm, UD_VECTOR);
1200         set_exception_intercept(svm, MC_VECTOR);
1201         set_exception_intercept(svm, AC_VECTOR);
1202         set_exception_intercept(svm, DB_VECTOR);
1203
1204         set_intercept(svm, INTERCEPT_INTR);
1205         set_intercept(svm, INTERCEPT_NMI);
1206         set_intercept(svm, INTERCEPT_SMI);
1207         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1208         set_intercept(svm, INTERCEPT_RDPMC);
1209         set_intercept(svm, INTERCEPT_CPUID);
1210         set_intercept(svm, INTERCEPT_INVD);
1211         set_intercept(svm, INTERCEPT_HLT);
1212         set_intercept(svm, INTERCEPT_INVLPG);
1213         set_intercept(svm, INTERCEPT_INVLPGA);
1214         set_intercept(svm, INTERCEPT_IOIO_PROT);
1215         set_intercept(svm, INTERCEPT_MSR_PROT);
1216         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1217         set_intercept(svm, INTERCEPT_SHUTDOWN);
1218         set_intercept(svm, INTERCEPT_VMRUN);
1219         set_intercept(svm, INTERCEPT_VMMCALL);
1220         set_intercept(svm, INTERCEPT_VMLOAD);
1221         set_intercept(svm, INTERCEPT_VMSAVE);
1222         set_intercept(svm, INTERCEPT_STGI);
1223         set_intercept(svm, INTERCEPT_CLGI);
1224         set_intercept(svm, INTERCEPT_SKINIT);
1225         set_intercept(svm, INTERCEPT_WBINVD);
1226         set_intercept(svm, INTERCEPT_MONITOR);
1227         set_intercept(svm, INTERCEPT_MWAIT);
1228         set_intercept(svm, INTERCEPT_XSETBV);
1229
1230         control->iopm_base_pa = iopm_base;
1231         control->msrpm_base_pa = __pa(svm->msrpm);
1232         control->int_ctl = V_INTR_MASKING_MASK;
1233
1234         init_seg(&save->es);
1235         init_seg(&save->ss);
1236         init_seg(&save->ds);
1237         init_seg(&save->fs);
1238         init_seg(&save->gs);
1239
1240         save->cs.selector = 0xf000;
1241         save->cs.base = 0xffff0000;
1242         /* Executable/Readable Code Segment */
1243         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1244                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1245         save->cs.limit = 0xffff;
1246
1247         save->gdtr.limit = 0xffff;
1248         save->idtr.limit = 0xffff;
1249
1250         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1251         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1252
1253         svm_set_efer(&svm->vcpu, 0);
1254         save->dr6 = 0xffff0ff0;
1255         kvm_set_rflags(&svm->vcpu, 2);
1256         save->rip = 0x0000fff0;
1257         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1258
1259         /*
1260          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1261          * It also updates the guest-visible cr0 value.
1262          */
1263         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1264         kvm_mmu_reset_context(&svm->vcpu);
1265
1266         save->cr4 = X86_CR4_PAE;
1267         /* rdx = ?? */
1268
1269         if (npt_enabled) {
1270                 /* Setup VMCB for Nested Paging */
1271                 control->nested_ctl = 1;
1272                 clr_intercept(svm, INTERCEPT_INVLPG);
1273                 clr_exception_intercept(svm, PF_VECTOR);
1274                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1275                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1276                 save->g_pat = svm->vcpu.arch.pat;
1277                 save->cr3 = 0;
1278                 save->cr4 = 0;
1279         }
1280         svm->asid_generation = 0;
1281
1282         svm->nested.vmcb = 0;
1283         svm->vcpu.arch.hflags = 0;
1284
1285         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1286                 control->pause_filter_count = 3000;
1287                 set_intercept(svm, INTERCEPT_PAUSE);
1288         }
1289
1290         if (avic)
1291                 avic_init_vmcb(svm);
1292
1293         mark_all_dirty(svm->vmcb);
1294
1295         enable_gif(svm);
1296
1297 }
1298
1299 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1300 {
1301         u64 *avic_physical_id_table;
1302         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1303
1304         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1305                 return NULL;
1306
1307         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1308
1309         return &avic_physical_id_table[index];
1310 }
1311
1312 /**
1313  * Note:
1314  * AVIC hardware walks the nested page table to check permissions,
1315  * but does not use the SPA address specified in the leaf page
1316  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1317  * field of the VMCB. Therefore, we set up the
1318  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1319  */
1320 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1321 {
1322         struct kvm *kvm = vcpu->kvm;
1323         int ret;
1324
1325         if (kvm->arch.apic_access_page_done)
1326                 return 0;
1327
1328         ret = x86_set_memory_region(kvm,
1329                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1330                                     APIC_DEFAULT_PHYS_BASE,
1331                                     PAGE_SIZE);
1332         if (ret)
1333                 return ret;
1334
1335         kvm->arch.apic_access_page_done = true;
1336         return 0;
1337 }
1338
1339 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1340 {
1341         int ret;
1342         u64 *entry, new_entry;
1343         int id = vcpu->vcpu_id;
1344         struct vcpu_svm *svm = to_svm(vcpu);
1345
1346         ret = avic_init_access_page(vcpu);
1347         if (ret)
1348                 return ret;
1349
1350         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1351                 return -EINVAL;
1352
1353         if (!svm->vcpu.arch.apic->regs)
1354                 return -EINVAL;
1355
1356         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1357
1358         /* Setting AVIC backing page address in the phy APIC ID table */
1359         entry = avic_get_physical_id_entry(vcpu, id);
1360         if (!entry)
1361                 return -EINVAL;
1362
1363         new_entry = READ_ONCE(*entry);
1364         new_entry = (page_to_phys(svm->avic_backing_page) &
1365                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1366                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1367         WRITE_ONCE(*entry, new_entry);
1368
1369         svm->avic_physical_id_cache = entry;
1370
1371         return 0;
1372 }
1373
1374 static inline int avic_get_next_vm_id(void)
1375 {
1376         int id;
1377
1378         spin_lock(&avic_vm_id_lock);
1379
1380         /* AVIC VM ID is one-based. */
1381         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1382         if (id <= AVIC_VM_ID_MASK)
1383                 __set_bit(id, avic_vm_id_bitmap);
1384         else
1385                 id = -EAGAIN;
1386
1387         spin_unlock(&avic_vm_id_lock);
1388         return id;
1389 }
1390
1391 static inline int avic_free_vm_id(int id)
1392 {
1393         if (id <= 0 || id > AVIC_VM_ID_MASK)
1394                 return -EINVAL;
1395
1396         spin_lock(&avic_vm_id_lock);
1397         __clear_bit(id, avic_vm_id_bitmap);
1398         spin_unlock(&avic_vm_id_lock);
1399         return 0;
1400 }
1401
1402 static void avic_vm_destroy(struct kvm *kvm)
1403 {
1404         unsigned long flags;
1405         struct kvm_arch *vm_data = &kvm->arch;
1406
1407         avic_free_vm_id(vm_data->avic_vm_id);
1408
1409         if (vm_data->avic_logical_id_table_page)
1410                 __free_page(vm_data->avic_logical_id_table_page);
1411         if (vm_data->avic_physical_id_table_page)
1412                 __free_page(vm_data->avic_physical_id_table_page);
1413
1414         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1415         hash_del(&vm_data->hnode);
1416         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1417 }
1418
1419 static int avic_vm_init(struct kvm *kvm)
1420 {
1421         unsigned long flags;
1422         int err = -ENOMEM;
1423         struct kvm_arch *vm_data = &kvm->arch;
1424         struct page *p_page;
1425         struct page *l_page;
1426
1427         if (!avic)
1428                 return 0;
1429
1430         vm_data->avic_vm_id = avic_get_next_vm_id();
1431         if (vm_data->avic_vm_id < 0)
1432                 return vm_data->avic_vm_id;
1433
1434         /* Allocating physical APIC ID table (4KB) */
1435         p_page = alloc_page(GFP_KERNEL);
1436         if (!p_page)
1437                 goto free_avic;
1438
1439         vm_data->avic_physical_id_table_page = p_page;
1440         clear_page(page_address(p_page));
1441
1442         /* Allocating logical APIC ID table (4KB) */
1443         l_page = alloc_page(GFP_KERNEL);
1444         if (!l_page)
1445                 goto free_avic;
1446
1447         vm_data->avic_logical_id_table_page = l_page;
1448         clear_page(page_address(l_page));
1449
1450         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1451         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1452         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1453
1454         return 0;
1455
1456 free_avic:
1457         avic_vm_destroy(kvm);
1458         return err;
1459 }
1460
1461 static inline int
1462 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1463 {
1464         int ret = 0;
1465         unsigned long flags;
1466         struct amd_svm_iommu_ir *ir;
1467         struct vcpu_svm *svm = to_svm(vcpu);
1468
1469         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1470                 return 0;
1471
1472         /*
1473          * Here, we go through the per-vcpu ir_list to update all existing
1474          * interrupt remapping table entry targeting this vcpu.
1475          */
1476         spin_lock_irqsave(&svm->ir_list_lock, flags);
1477
1478         if (list_empty(&svm->ir_list))
1479                 goto out;
1480
1481         list_for_each_entry(ir, &svm->ir_list, node) {
1482                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1483                 if (ret)
1484                         break;
1485         }
1486 out:
1487         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1488         return ret;
1489 }
1490
1491 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1492 {
1493         u64 entry;
1494         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1495         int h_physical_id = kvm_cpu_get_apicid(cpu);
1496         struct vcpu_svm *svm = to_svm(vcpu);
1497
1498         if (!kvm_vcpu_apicv_active(vcpu))
1499                 return;
1500
1501         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1502                 return;
1503
1504         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1505         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1506
1507         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1508         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1509
1510         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1511         if (svm->avic_is_running)
1512                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1513
1514         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1515         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1516                                         svm->avic_is_running);
1517 }
1518
1519 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1520 {
1521         u64 entry;
1522         struct vcpu_svm *svm = to_svm(vcpu);
1523
1524         if (!kvm_vcpu_apicv_active(vcpu))
1525                 return;
1526
1527         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1528         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1529                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1530
1531         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1532         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1533 }
1534
1535 /**
1536  * This function is called during VCPU halt/unhalt.
1537  */
1538 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1539 {
1540         struct vcpu_svm *svm = to_svm(vcpu);
1541
1542         svm->avic_is_running = is_run;
1543         if (is_run)
1544                 avic_vcpu_load(vcpu, vcpu->cpu);
1545         else
1546                 avic_vcpu_put(vcpu);
1547 }
1548
1549 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1550 {
1551         struct vcpu_svm *svm = to_svm(vcpu);
1552         u32 dummy;
1553         u32 eax = 1;
1554
1555         if (!init_event) {
1556                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1557                                            MSR_IA32_APICBASE_ENABLE;
1558                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1559                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1560         }
1561         init_vmcb(svm);
1562
1563         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1564         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1565
1566         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1567                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1568 }
1569
1570 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1571 {
1572         struct vcpu_svm *svm;
1573         struct page *page;
1574         struct page *msrpm_pages;
1575         struct page *hsave_page;
1576         struct page *nested_msrpm_pages;
1577         int err;
1578
1579         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1580         if (!svm) {
1581                 err = -ENOMEM;
1582                 goto out;
1583         }
1584
1585         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1586         if (err)
1587                 goto free_svm;
1588
1589         err = -ENOMEM;
1590         page = alloc_page(GFP_KERNEL);
1591         if (!page)
1592                 goto uninit;
1593
1594         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1595         if (!msrpm_pages)
1596                 goto free_page1;
1597
1598         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1599         if (!nested_msrpm_pages)
1600                 goto free_page2;
1601
1602         hsave_page = alloc_page(GFP_KERNEL);
1603         if (!hsave_page)
1604                 goto free_page3;
1605
1606         if (avic) {
1607                 err = avic_init_backing_page(&svm->vcpu);
1608                 if (err)
1609                         goto free_page4;
1610
1611                 INIT_LIST_HEAD(&svm->ir_list);
1612                 spin_lock_init(&svm->ir_list_lock);
1613         }
1614
1615         /* We initialize this flag to true to make sure that the is_running
1616          * bit would be set the first time the vcpu is loaded.
1617          */
1618         svm->avic_is_running = true;
1619
1620         svm->nested.hsave = page_address(hsave_page);
1621
1622         svm->msrpm = page_address(msrpm_pages);
1623         svm_vcpu_init_msrpm(svm->msrpm);
1624
1625         svm->nested.msrpm = page_address(nested_msrpm_pages);
1626         svm_vcpu_init_msrpm(svm->nested.msrpm);
1627
1628         svm->vmcb = page_address(page);
1629         clear_page(svm->vmcb);
1630         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1631         svm->asid_generation = 0;
1632         init_vmcb(svm);
1633
1634         svm_init_osvw(&svm->vcpu);
1635
1636         return &svm->vcpu;
1637
1638 free_page4:
1639         __free_page(hsave_page);
1640 free_page3:
1641         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1642 free_page2:
1643         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1644 free_page1:
1645         __free_page(page);
1646 uninit:
1647         kvm_vcpu_uninit(&svm->vcpu);
1648 free_svm:
1649         kmem_cache_free(kvm_vcpu_cache, svm);
1650 out:
1651         return ERR_PTR(err);
1652 }
1653
1654 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1655 {
1656         struct vcpu_svm *svm = to_svm(vcpu);
1657
1658         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1659         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1660         __free_page(virt_to_page(svm->nested.hsave));
1661         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1662         kvm_vcpu_uninit(vcpu);
1663         kmem_cache_free(kvm_vcpu_cache, svm);
1664 }
1665
1666 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1667 {
1668         struct vcpu_svm *svm = to_svm(vcpu);
1669         int i;
1670
1671         if (unlikely(cpu != vcpu->cpu)) {
1672                 svm->asid_generation = 0;
1673                 mark_all_dirty(svm->vmcb);
1674         }
1675
1676 #ifdef CONFIG_X86_64
1677         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1678 #endif
1679         savesegment(fs, svm->host.fs);
1680         savesegment(gs, svm->host.gs);
1681         svm->host.ldt = kvm_read_ldt();
1682
1683         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1684                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1685
1686         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1687                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1688                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1689                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1690                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1691                 }
1692         }
1693         /* This assumes that the kernel never uses MSR_TSC_AUX */
1694         if (static_cpu_has(X86_FEATURE_RDTSCP))
1695                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1696
1697         avic_vcpu_load(vcpu, cpu);
1698 }
1699
1700 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1701 {
1702         struct vcpu_svm *svm = to_svm(vcpu);
1703         int i;
1704
1705         avic_vcpu_put(vcpu);
1706
1707         ++vcpu->stat.host_state_reload;
1708         kvm_load_ldt(svm->host.ldt);
1709 #ifdef CONFIG_X86_64
1710         loadsegment(fs, svm->host.fs);
1711         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1712         load_gs_index(svm->host.gs);
1713 #else
1714 #ifdef CONFIG_X86_32_LAZY_GS
1715         loadsegment(gs, svm->host.gs);
1716 #endif
1717 #endif
1718         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1719                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1720 }
1721
1722 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1723 {
1724         avic_set_running(vcpu, false);
1725 }
1726
1727 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1728 {
1729         avic_set_running(vcpu, true);
1730 }
1731
1732 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1733 {
1734         return to_svm(vcpu)->vmcb->save.rflags;
1735 }
1736
1737 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1738 {
1739        /*
1740         * Any change of EFLAGS.VM is accompanied by a reload of SS
1741         * (caused by either a task switch or an inter-privilege IRET),
1742         * so we do not need to update the CPL here.
1743         */
1744         to_svm(vcpu)->vmcb->save.rflags = rflags;
1745 }
1746
1747 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1748 {
1749         return 0;
1750 }
1751
1752 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1753 {
1754         switch (reg) {
1755         case VCPU_EXREG_PDPTR:
1756                 BUG_ON(!npt_enabled);
1757                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1758                 break;
1759         default:
1760                 BUG();
1761         }
1762 }
1763
1764 static void svm_set_vintr(struct vcpu_svm *svm)
1765 {
1766         set_intercept(svm, INTERCEPT_VINTR);
1767 }
1768
1769 static void svm_clear_vintr(struct vcpu_svm *svm)
1770 {
1771         clr_intercept(svm, INTERCEPT_VINTR);
1772 }
1773
1774 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1775 {
1776         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1777
1778         switch (seg) {
1779         case VCPU_SREG_CS: return &save->cs;
1780         case VCPU_SREG_DS: return &save->ds;
1781         case VCPU_SREG_ES: return &save->es;
1782         case VCPU_SREG_FS: return &save->fs;
1783         case VCPU_SREG_GS: return &save->gs;
1784         case VCPU_SREG_SS: return &save->ss;
1785         case VCPU_SREG_TR: return &save->tr;
1786         case VCPU_SREG_LDTR: return &save->ldtr;
1787         }
1788         BUG();
1789         return NULL;
1790 }
1791
1792 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1793 {
1794         struct vmcb_seg *s = svm_seg(vcpu, seg);
1795
1796         return s->base;
1797 }
1798
1799 static void svm_get_segment(struct kvm_vcpu *vcpu,
1800                             struct kvm_segment *var, int seg)
1801 {
1802         struct vmcb_seg *s = svm_seg(vcpu, seg);
1803
1804         var->base = s->base;
1805         var->limit = s->limit;
1806         var->selector = s->selector;
1807         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1808         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1809         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1810         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1811         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1812         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1813         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1814
1815         /*
1816          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1817          * However, the SVM spec states that the G bit is not observed by the
1818          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1819          * So let's synthesize a legal G bit for all segments, this helps
1820          * running KVM nested. It also helps cross-vendor migration, because
1821          * Intel's vmentry has a check on the 'G' bit.
1822          */
1823         var->g = s->limit > 0xfffff;
1824
1825         /*
1826          * AMD's VMCB does not have an explicit unusable field, so emulate it
1827          * for cross vendor migration purposes by "not present"
1828          */
1829         var->unusable = !var->present || (var->type == 0);
1830
1831         switch (seg) {
1832         case VCPU_SREG_TR:
1833                 /*
1834                  * Work around a bug where the busy flag in the tr selector
1835                  * isn't exposed
1836                  */
1837                 var->type |= 0x2;
1838                 break;
1839         case VCPU_SREG_DS:
1840         case VCPU_SREG_ES:
1841         case VCPU_SREG_FS:
1842         case VCPU_SREG_GS:
1843                 /*
1844                  * The accessed bit must always be set in the segment
1845                  * descriptor cache, although it can be cleared in the
1846                  * descriptor, the cached bit always remains at 1. Since
1847                  * Intel has a check on this, set it here to support
1848                  * cross-vendor migration.
1849                  */
1850                 if (!var->unusable)
1851                         var->type |= 0x1;
1852                 break;
1853         case VCPU_SREG_SS:
1854                 /*
1855                  * On AMD CPUs sometimes the DB bit in the segment
1856                  * descriptor is left as 1, although the whole segment has
1857                  * been made unusable. Clear it here to pass an Intel VMX
1858                  * entry check when cross vendor migrating.
1859                  */
1860                 if (var->unusable)
1861                         var->db = 0;
1862                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1863                 break;
1864         }
1865 }
1866
1867 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1868 {
1869         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1870
1871         return save->cpl;
1872 }
1873
1874 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1875 {
1876         struct vcpu_svm *svm = to_svm(vcpu);
1877
1878         dt->size = svm->vmcb->save.idtr.limit;
1879         dt->address = svm->vmcb->save.idtr.base;
1880 }
1881
1882 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1883 {
1884         struct vcpu_svm *svm = to_svm(vcpu);
1885
1886         svm->vmcb->save.idtr.limit = dt->size;
1887         svm->vmcb->save.idtr.base = dt->address ;
1888         mark_dirty(svm->vmcb, VMCB_DT);
1889 }
1890
1891 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1892 {
1893         struct vcpu_svm *svm = to_svm(vcpu);
1894
1895         dt->size = svm->vmcb->save.gdtr.limit;
1896         dt->address = svm->vmcb->save.gdtr.base;
1897 }
1898
1899 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1900 {
1901         struct vcpu_svm *svm = to_svm(vcpu);
1902
1903         svm->vmcb->save.gdtr.limit = dt->size;
1904         svm->vmcb->save.gdtr.base = dt->address ;
1905         mark_dirty(svm->vmcb, VMCB_DT);
1906 }
1907
1908 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1909 {
1910 }
1911
1912 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1913 {
1914 }
1915
1916 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1917 {
1918 }
1919
1920 static void update_cr0_intercept(struct vcpu_svm *svm)
1921 {
1922         ulong gcr0 = svm->vcpu.arch.cr0;
1923         u64 *hcr0 = &svm->vmcb->save.cr0;
1924
1925         if (!svm->vcpu.fpu_active)
1926                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1927         else
1928                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1929                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1930
1931         mark_dirty(svm->vmcb, VMCB_CR);
1932
1933         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1934                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1935                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1936         } else {
1937                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1938                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1939         }
1940 }
1941
1942 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1943 {
1944         struct vcpu_svm *svm = to_svm(vcpu);
1945
1946 #ifdef CONFIG_X86_64
1947         if (vcpu->arch.efer & EFER_LME) {
1948                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1949                         vcpu->arch.efer |= EFER_LMA;
1950                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1951                 }
1952
1953                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1954                         vcpu->arch.efer &= ~EFER_LMA;
1955                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1956                 }
1957         }
1958 #endif
1959         vcpu->arch.cr0 = cr0;
1960
1961         if (!npt_enabled)
1962                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1963
1964         if (!vcpu->fpu_active)
1965                 cr0 |= X86_CR0_TS;
1966         /*
1967          * re-enable caching here because the QEMU bios
1968          * does not do it - this results in some delay at
1969          * reboot
1970          */
1971         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1972                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1973         svm->vmcb->save.cr0 = cr0;
1974         mark_dirty(svm->vmcb, VMCB_CR);
1975         update_cr0_intercept(svm);
1976 }
1977
1978 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1979 {
1980         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1981         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1982
1983         if (cr4 & X86_CR4_VMXE)
1984                 return 1;
1985
1986         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1987                 svm_flush_tlb(vcpu);
1988
1989         vcpu->arch.cr4 = cr4;
1990         if (!npt_enabled)
1991                 cr4 |= X86_CR4_PAE;
1992         cr4 |= host_cr4_mce;
1993         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1994         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1995         return 0;
1996 }
1997
1998 static void svm_set_segment(struct kvm_vcpu *vcpu,
1999                             struct kvm_segment *var, int seg)
2000 {
2001         struct vcpu_svm *svm = to_svm(vcpu);
2002         struct vmcb_seg *s = svm_seg(vcpu, seg);
2003
2004         s->base = var->base;
2005         s->limit = var->limit;
2006         s->selector = var->selector;
2007         if (var->unusable)
2008                 s->attrib = 0;
2009         else {
2010                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2011                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2012                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2013                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
2014                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2015                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2016                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2017                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2018         }
2019
2020         /*
2021          * This is always accurate, except if SYSRET returned to a segment
2022          * with SS.DPL != 3.  Intel does not have this quirk, and always
2023          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2024          * would entail passing the CPL to userspace and back.
2025          */
2026         if (seg == VCPU_SREG_SS)
2027                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2028
2029         mark_dirty(svm->vmcb, VMCB_SEG);
2030 }
2031
2032 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2033 {
2034         struct vcpu_svm *svm = to_svm(vcpu);
2035
2036         clr_exception_intercept(svm, BP_VECTOR);
2037
2038         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2039                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2040                         set_exception_intercept(svm, BP_VECTOR);
2041         } else
2042                 vcpu->guest_debug = 0;
2043 }
2044
2045 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2046 {
2047         if (sd->next_asid > sd->max_asid) {
2048                 ++sd->asid_generation;
2049                 sd->next_asid = 1;
2050                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2051         }
2052
2053         svm->asid_generation = sd->asid_generation;
2054         svm->vmcb->control.asid = sd->next_asid++;
2055
2056         mark_dirty(svm->vmcb, VMCB_ASID);
2057 }
2058
2059 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2060 {
2061         return to_svm(vcpu)->vmcb->save.dr6;
2062 }
2063
2064 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2065 {
2066         struct vcpu_svm *svm = to_svm(vcpu);
2067
2068         svm->vmcb->save.dr6 = value;
2069         mark_dirty(svm->vmcb, VMCB_DR);
2070 }
2071
2072 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2073 {
2074         struct vcpu_svm *svm = to_svm(vcpu);
2075
2076         get_debugreg(vcpu->arch.db[0], 0);
2077         get_debugreg(vcpu->arch.db[1], 1);
2078         get_debugreg(vcpu->arch.db[2], 2);
2079         get_debugreg(vcpu->arch.db[3], 3);
2080         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2081         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2082
2083         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2084         set_dr_intercepts(svm);
2085 }
2086
2087 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2088 {
2089         struct vcpu_svm *svm = to_svm(vcpu);
2090
2091         svm->vmcb->save.dr7 = value;
2092         mark_dirty(svm->vmcb, VMCB_DR);
2093 }
2094
2095 static int pf_interception(struct vcpu_svm *svm)
2096 {
2097         u64 fault_address = svm->vmcb->control.exit_info_2;
2098         u32 error_code;
2099         int r = 1;
2100
2101         switch (svm->apf_reason) {
2102         default:
2103                 error_code = svm->vmcb->control.exit_info_1;
2104
2105                 trace_kvm_page_fault(fault_address, error_code);
2106                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2107                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2108                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2109                         svm->vmcb->control.insn_bytes,
2110                         svm->vmcb->control.insn_len);
2111                 break;
2112         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2113                 svm->apf_reason = 0;
2114                 local_irq_disable();
2115                 kvm_async_pf_task_wait(fault_address);
2116                 local_irq_enable();
2117                 break;
2118         case KVM_PV_REASON_PAGE_READY:
2119                 svm->apf_reason = 0;
2120                 local_irq_disable();
2121                 kvm_async_pf_task_wake(fault_address);
2122                 local_irq_enable();
2123                 break;
2124         }
2125         return r;
2126 }
2127
2128 static int db_interception(struct vcpu_svm *svm)
2129 {
2130         struct kvm_run *kvm_run = svm->vcpu.run;
2131
2132         if (!(svm->vcpu.guest_debug &
2133               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2134                 !svm->nmi_singlestep) {
2135                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2136                 return 1;
2137         }
2138
2139         if (svm->nmi_singlestep) {
2140                 svm->nmi_singlestep = false;
2141                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2142                         svm->vmcb->save.rflags &=
2143                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2144         }
2145
2146         if (svm->vcpu.guest_debug &
2147             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2148                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2149                 kvm_run->debug.arch.pc =
2150                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2151                 kvm_run->debug.arch.exception = DB_VECTOR;
2152                 return 0;
2153         }
2154
2155         return 1;
2156 }
2157
2158 static int bp_interception(struct vcpu_svm *svm)
2159 {
2160         struct kvm_run *kvm_run = svm->vcpu.run;
2161
2162         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2163         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2164         kvm_run->debug.arch.exception = BP_VECTOR;
2165         return 0;
2166 }
2167
2168 static int ud_interception(struct vcpu_svm *svm)
2169 {
2170         int er;
2171
2172         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2173         if (er != EMULATE_DONE)
2174                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2175         return 1;
2176 }
2177
2178 static int ac_interception(struct vcpu_svm *svm)
2179 {
2180         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2181         return 1;
2182 }
2183
2184 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
2185 {
2186         struct vcpu_svm *svm = to_svm(vcpu);
2187
2188         clr_exception_intercept(svm, NM_VECTOR);
2189
2190         svm->vcpu.fpu_active = 1;
2191         update_cr0_intercept(svm);
2192 }
2193
2194 static int nm_interception(struct vcpu_svm *svm)
2195 {
2196         svm_fpu_activate(&svm->vcpu);
2197         return 1;
2198 }
2199
2200 static bool is_erratum_383(void)
2201 {
2202         int err, i;
2203         u64 value;
2204
2205         if (!erratum_383_found)
2206                 return false;
2207
2208         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2209         if (err)
2210                 return false;
2211
2212         /* Bit 62 may or may not be set for this mce */
2213         value &= ~(1ULL << 62);
2214
2215         if (value != 0xb600000000010015ULL)
2216                 return false;
2217
2218         /* Clear MCi_STATUS registers */
2219         for (i = 0; i < 6; ++i)
2220                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2221
2222         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2223         if (!err) {
2224                 u32 low, high;
2225
2226                 value &= ~(1ULL << 2);
2227                 low    = lower_32_bits(value);
2228                 high   = upper_32_bits(value);
2229
2230                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2231         }
2232
2233         /* Flush tlb to evict multi-match entries */
2234         __flush_tlb_all();
2235
2236         return true;
2237 }
2238
2239 static void svm_handle_mce(struct vcpu_svm *svm)
2240 {
2241         if (is_erratum_383()) {
2242                 /*
2243                  * Erratum 383 triggered. Guest state is corrupt so kill the
2244                  * guest.
2245                  */
2246                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2247
2248                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2249
2250                 return;
2251         }
2252
2253         /*
2254          * On an #MC intercept the MCE handler is not called automatically in
2255          * the host. So do it by hand here.
2256          */
2257         asm volatile (
2258                 "int $0x12\n");
2259         /* not sure if we ever come back to this point */
2260
2261         return;
2262 }
2263
2264 static int mc_interception(struct vcpu_svm *svm)
2265 {
2266         return 1;
2267 }
2268
2269 static int shutdown_interception(struct vcpu_svm *svm)
2270 {
2271         struct kvm_run *kvm_run = svm->vcpu.run;
2272
2273         /*
2274          * VMCB is undefined after a SHUTDOWN intercept
2275          * so reinitialize it.
2276          */
2277         clear_page(svm->vmcb);
2278         init_vmcb(svm);
2279
2280         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2281         return 0;
2282 }
2283
2284 static int io_interception(struct vcpu_svm *svm)
2285 {
2286         struct kvm_vcpu *vcpu = &svm->vcpu;
2287         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2288         int size, in, string;
2289         unsigned port;
2290
2291         ++svm->vcpu.stat.io_exits;
2292         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2293         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2294         if (string || in)
2295                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2296
2297         port = io_info >> 16;
2298         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2299         svm->next_rip = svm->vmcb->control.exit_info_2;
2300         skip_emulated_instruction(&svm->vcpu);
2301
2302         return kvm_fast_pio_out(vcpu, size, port);
2303 }
2304
2305 static int nmi_interception(struct vcpu_svm *svm)
2306 {
2307         return 1;
2308 }
2309
2310 static int intr_interception(struct vcpu_svm *svm)
2311 {
2312         ++svm->vcpu.stat.irq_exits;
2313         return 1;
2314 }
2315
2316 static int nop_on_interception(struct vcpu_svm *svm)
2317 {
2318         return 1;
2319 }
2320
2321 static int halt_interception(struct vcpu_svm *svm)
2322 {
2323         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2324         return kvm_emulate_halt(&svm->vcpu);
2325 }
2326
2327 static int vmmcall_interception(struct vcpu_svm *svm)
2328 {
2329         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2330         return kvm_emulate_hypercall(&svm->vcpu);
2331 }
2332
2333 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2334 {
2335         struct vcpu_svm *svm = to_svm(vcpu);
2336
2337         return svm->nested.nested_cr3;
2338 }
2339
2340 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2341 {
2342         struct vcpu_svm *svm = to_svm(vcpu);
2343         u64 cr3 = svm->nested.nested_cr3;
2344         u64 pdpte;
2345         int ret;
2346
2347         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2348                                        offset_in_page(cr3) + index * 8, 8);
2349         if (ret)
2350                 return 0;
2351         return pdpte;
2352 }
2353
2354 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2355                                    unsigned long root)
2356 {
2357         struct vcpu_svm *svm = to_svm(vcpu);
2358
2359         svm->vmcb->control.nested_cr3 = root;
2360         mark_dirty(svm->vmcb, VMCB_NPT);
2361         svm_flush_tlb(vcpu);
2362 }
2363
2364 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2365                                        struct x86_exception *fault)
2366 {
2367         struct vcpu_svm *svm = to_svm(vcpu);
2368
2369         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2370                 /*
2371                  * TODO: track the cause of the nested page fault, and
2372                  * correctly fill in the high bits of exit_info_1.
2373                  */
2374                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2375                 svm->vmcb->control.exit_code_hi = 0;
2376                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2377                 svm->vmcb->control.exit_info_2 = fault->address;
2378         }
2379
2380         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2381         svm->vmcb->control.exit_info_1 |= fault->error_code;
2382
2383         /*
2384          * The present bit is always zero for page structure faults on real
2385          * hardware.
2386          */
2387         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2388                 svm->vmcb->control.exit_info_1 &= ~1;
2389
2390         nested_svm_vmexit(svm);
2391 }
2392
2393 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2394 {
2395         WARN_ON(mmu_is_nested(vcpu));
2396         kvm_init_shadow_mmu(vcpu);
2397         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2398         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2399         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2400         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2401         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2402         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2403         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2404 }
2405
2406 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2407 {
2408         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2409 }
2410
2411 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2412 {
2413         if (!(svm->vcpu.arch.efer & EFER_SVME)
2414             || !is_paging(&svm->vcpu)) {
2415                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2416                 return 1;
2417         }
2418
2419         if (svm->vmcb->save.cpl) {
2420                 kvm_inject_gp(&svm->vcpu, 0);
2421                 return 1;
2422         }
2423
2424        return 0;
2425 }
2426
2427 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2428                                       bool has_error_code, u32 error_code)
2429 {
2430         int vmexit;
2431
2432         if (!is_guest_mode(&svm->vcpu))
2433                 return 0;
2434
2435         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2436         svm->vmcb->control.exit_code_hi = 0;
2437         svm->vmcb->control.exit_info_1 = error_code;
2438         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2439
2440         vmexit = nested_svm_intercept(svm);
2441         if (vmexit == NESTED_EXIT_DONE)
2442                 svm->nested.exit_required = true;
2443
2444         return vmexit;
2445 }
2446
2447 /* This function returns true if it is save to enable the irq window */
2448 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2449 {
2450         if (!is_guest_mode(&svm->vcpu))
2451                 return true;
2452
2453         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2454                 return true;
2455
2456         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2457                 return false;
2458
2459         /*
2460          * if vmexit was already requested (by intercepted exception
2461          * for instance) do not overwrite it with "external interrupt"
2462          * vmexit.
2463          */
2464         if (svm->nested.exit_required)
2465                 return false;
2466
2467         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2468         svm->vmcb->control.exit_info_1 = 0;
2469         svm->vmcb->control.exit_info_2 = 0;
2470
2471         if (svm->nested.intercept & 1ULL) {
2472                 /*
2473                  * The #vmexit can't be emulated here directly because this
2474                  * code path runs with irqs and preemption disabled. A
2475                  * #vmexit emulation might sleep. Only signal request for
2476                  * the #vmexit here.
2477                  */
2478                 svm->nested.exit_required = true;
2479                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2480                 return false;
2481         }
2482
2483         return true;
2484 }
2485
2486 /* This function returns true if it is save to enable the nmi window */
2487 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2488 {
2489         if (!is_guest_mode(&svm->vcpu))
2490                 return true;
2491
2492         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2493                 return true;
2494
2495         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2496         svm->nested.exit_required = true;
2497
2498         return false;
2499 }
2500
2501 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2502 {
2503         struct page *page;
2504
2505         might_sleep();
2506
2507         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2508         if (is_error_page(page))
2509                 goto error;
2510
2511         *_page = page;
2512
2513         return kmap(page);
2514
2515 error:
2516         kvm_inject_gp(&svm->vcpu, 0);
2517
2518         return NULL;
2519 }
2520
2521 static void nested_svm_unmap(struct page *page)
2522 {
2523         kunmap(page);
2524         kvm_release_page_dirty(page);
2525 }
2526
2527 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2528 {
2529         unsigned port, size, iopm_len;
2530         u16 val, mask;
2531         u8 start_bit;
2532         u64 gpa;
2533
2534         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2535                 return NESTED_EXIT_HOST;
2536
2537         port = svm->vmcb->control.exit_info_1 >> 16;
2538         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2539                 SVM_IOIO_SIZE_SHIFT;
2540         gpa  = svm->nested.vmcb_iopm + (port / 8);
2541         start_bit = port % 8;
2542         iopm_len = (start_bit + size > 8) ? 2 : 1;
2543         mask = (0xf >> (4 - size)) << start_bit;
2544         val = 0;
2545
2546         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2547                 return NESTED_EXIT_DONE;
2548
2549         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2550 }
2551
2552 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2553 {
2554         u32 offset, msr, value;
2555         int write, mask;
2556
2557         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2558                 return NESTED_EXIT_HOST;
2559
2560         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2561         offset = svm_msrpm_offset(msr);
2562         write  = svm->vmcb->control.exit_info_1 & 1;
2563         mask   = 1 << ((2 * (msr & 0xf)) + write);
2564
2565         if (offset == MSR_INVALID)
2566                 return NESTED_EXIT_DONE;
2567
2568         /* Offset is in 32 bit units but need in 8 bit units */
2569         offset *= 4;
2570
2571         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2572                 return NESTED_EXIT_DONE;
2573
2574         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2575 }
2576
2577 static int nested_svm_exit_special(struct vcpu_svm *svm)
2578 {
2579         u32 exit_code = svm->vmcb->control.exit_code;
2580
2581         switch (exit_code) {
2582         case SVM_EXIT_INTR:
2583         case SVM_EXIT_NMI:
2584         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2585                 return NESTED_EXIT_HOST;
2586         case SVM_EXIT_NPF:
2587                 /* For now we are always handling NPFs when using them */
2588                 if (npt_enabled)
2589                         return NESTED_EXIT_HOST;
2590                 break;
2591         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2592                 /* When we're shadowing, trap PFs, but not async PF */
2593                 if (!npt_enabled && svm->apf_reason == 0)
2594                         return NESTED_EXIT_HOST;
2595                 break;
2596         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2597                 nm_interception(svm);
2598                 break;
2599         default:
2600                 break;
2601         }
2602
2603         return NESTED_EXIT_CONTINUE;
2604 }
2605
2606 /*
2607  * If this function returns true, this #vmexit was already handled
2608  */
2609 static int nested_svm_intercept(struct vcpu_svm *svm)
2610 {
2611         u32 exit_code = svm->vmcb->control.exit_code;
2612         int vmexit = NESTED_EXIT_HOST;
2613
2614         switch (exit_code) {
2615         case SVM_EXIT_MSR:
2616                 vmexit = nested_svm_exit_handled_msr(svm);
2617                 break;
2618         case SVM_EXIT_IOIO:
2619                 vmexit = nested_svm_intercept_ioio(svm);
2620                 break;
2621         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2622                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2623                 if (svm->nested.intercept_cr & bit)
2624                         vmexit = NESTED_EXIT_DONE;
2625                 break;
2626         }
2627         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2628                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2629                 if (svm->nested.intercept_dr & bit)
2630                         vmexit = NESTED_EXIT_DONE;
2631                 break;
2632         }
2633         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2634                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2635                 if (svm->nested.intercept_exceptions & excp_bits)
2636                         vmexit = NESTED_EXIT_DONE;
2637                 /* async page fault always cause vmexit */
2638                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2639                          svm->apf_reason != 0)
2640                         vmexit = NESTED_EXIT_DONE;
2641                 break;
2642         }
2643         case SVM_EXIT_ERR: {
2644                 vmexit = NESTED_EXIT_DONE;
2645                 break;
2646         }
2647         default: {
2648                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2649                 if (svm->nested.intercept & exit_bits)
2650                         vmexit = NESTED_EXIT_DONE;
2651         }
2652         }
2653
2654         return vmexit;
2655 }
2656
2657 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2658 {
2659         int vmexit;
2660
2661         vmexit = nested_svm_intercept(svm);
2662
2663         if (vmexit == NESTED_EXIT_DONE)
2664                 nested_svm_vmexit(svm);
2665
2666         return vmexit;
2667 }
2668
2669 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2670 {
2671         struct vmcb_control_area *dst  = &dst_vmcb->control;
2672         struct vmcb_control_area *from = &from_vmcb->control;
2673
2674         dst->intercept_cr         = from->intercept_cr;
2675         dst->intercept_dr         = from->intercept_dr;
2676         dst->intercept_exceptions = from->intercept_exceptions;
2677         dst->intercept            = from->intercept;
2678         dst->iopm_base_pa         = from->iopm_base_pa;
2679         dst->msrpm_base_pa        = from->msrpm_base_pa;
2680         dst->tsc_offset           = from->tsc_offset;
2681         dst->asid                 = from->asid;
2682         dst->tlb_ctl              = from->tlb_ctl;
2683         dst->int_ctl              = from->int_ctl;
2684         dst->int_vector           = from->int_vector;
2685         dst->int_state            = from->int_state;
2686         dst->exit_code            = from->exit_code;
2687         dst->exit_code_hi         = from->exit_code_hi;
2688         dst->exit_info_1          = from->exit_info_1;
2689         dst->exit_info_2          = from->exit_info_2;
2690         dst->exit_int_info        = from->exit_int_info;
2691         dst->exit_int_info_err    = from->exit_int_info_err;
2692         dst->nested_ctl           = from->nested_ctl;
2693         dst->event_inj            = from->event_inj;
2694         dst->event_inj_err        = from->event_inj_err;
2695         dst->nested_cr3           = from->nested_cr3;
2696         dst->lbr_ctl              = from->lbr_ctl;
2697 }
2698
2699 static int nested_svm_vmexit(struct vcpu_svm *svm)
2700 {
2701         struct vmcb *nested_vmcb;
2702         struct vmcb *hsave = svm->nested.hsave;
2703         struct vmcb *vmcb = svm->vmcb;
2704         struct page *page;
2705
2706         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2707                                        vmcb->control.exit_info_1,
2708                                        vmcb->control.exit_info_2,
2709                                        vmcb->control.exit_int_info,
2710                                        vmcb->control.exit_int_info_err,
2711                                        KVM_ISA_SVM);
2712
2713         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2714         if (!nested_vmcb)
2715                 return 1;
2716
2717         /* Exit Guest-Mode */
2718         leave_guest_mode(&svm->vcpu);
2719         svm->nested.vmcb = 0;
2720
2721         /* Give the current vmcb to the guest */
2722         disable_gif(svm);
2723
2724         nested_vmcb->save.es     = vmcb->save.es;
2725         nested_vmcb->save.cs     = vmcb->save.cs;
2726         nested_vmcb->save.ss     = vmcb->save.ss;
2727         nested_vmcb->save.ds     = vmcb->save.ds;
2728         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2729         nested_vmcb->save.idtr   = vmcb->save.idtr;
2730         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2731         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2732         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2733         nested_vmcb->save.cr2    = vmcb->save.cr2;
2734         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2735         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2736         nested_vmcb->save.rip    = vmcb->save.rip;
2737         nested_vmcb->save.rsp    = vmcb->save.rsp;
2738         nested_vmcb->save.rax    = vmcb->save.rax;
2739         nested_vmcb->save.dr7    = vmcb->save.dr7;
2740         nested_vmcb->save.dr6    = vmcb->save.dr6;
2741         nested_vmcb->save.cpl    = vmcb->save.cpl;
2742
2743         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2744         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2745         nested_vmcb->control.int_state         = vmcb->control.int_state;
2746         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2747         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2748         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2749         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2750         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2751         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2752
2753         if (svm->nrips_enabled)
2754                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2755
2756         /*
2757          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2758          * to make sure that we do not lose injected events. So check event_inj
2759          * here and copy it to exit_int_info if it is valid.
2760          * Exit_int_info and event_inj can't be both valid because the case
2761          * below only happens on a VMRUN instruction intercept which has
2762          * no valid exit_int_info set.
2763          */
2764         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2765                 struct vmcb_control_area *nc = &nested_vmcb->control;
2766
2767                 nc->exit_int_info     = vmcb->control.event_inj;
2768                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2769         }
2770
2771         nested_vmcb->control.tlb_ctl           = 0;
2772         nested_vmcb->control.event_inj         = 0;
2773         nested_vmcb->control.event_inj_err     = 0;
2774
2775         /* We always set V_INTR_MASKING and remember the old value in hflags */
2776         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2777                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2778
2779         /* Restore the original control entries */
2780         copy_vmcb_control_area(vmcb, hsave);
2781
2782         kvm_clear_exception_queue(&svm->vcpu);
2783         kvm_clear_interrupt_queue(&svm->vcpu);
2784
2785         svm->nested.nested_cr3 = 0;
2786
2787         /* Restore selected save entries */
2788         svm->vmcb->save.es = hsave->save.es;
2789         svm->vmcb->save.cs = hsave->save.cs;
2790         svm->vmcb->save.ss = hsave->save.ss;
2791         svm->vmcb->save.ds = hsave->save.ds;
2792         svm->vmcb->save.gdtr = hsave->save.gdtr;
2793         svm->vmcb->save.idtr = hsave->save.idtr;
2794         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2795         svm_set_efer(&svm->vcpu, hsave->save.efer);
2796         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2797         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2798         if (npt_enabled) {
2799                 svm->vmcb->save.cr3 = hsave->save.cr3;
2800                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2801         } else {
2802                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2803         }
2804         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2805         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2806         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2807         svm->vmcb->save.dr7 = 0;
2808         svm->vmcb->save.cpl = 0;
2809         svm->vmcb->control.exit_int_info = 0;
2810
2811         mark_all_dirty(svm->vmcb);
2812
2813         nested_svm_unmap(page);
2814
2815         nested_svm_uninit_mmu_context(&svm->vcpu);
2816         kvm_mmu_reset_context(&svm->vcpu);
2817         kvm_mmu_load(&svm->vcpu);
2818
2819         return 0;
2820 }
2821
2822 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2823 {
2824         /*
2825          * This function merges the msr permission bitmaps of kvm and the
2826          * nested vmcb. It is optimized in that it only merges the parts where
2827          * the kvm msr permission bitmap may contain zero bits
2828          */
2829         int i;
2830
2831         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2832                 return true;
2833
2834         for (i = 0; i < MSRPM_OFFSETS; i++) {
2835                 u32 value, p;
2836                 u64 offset;
2837
2838                 if (msrpm_offsets[i] == 0xffffffff)
2839                         break;
2840
2841                 p      = msrpm_offsets[i];
2842                 offset = svm->nested.vmcb_msrpm + (p * 4);
2843
2844                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2845                         return false;
2846
2847                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2848         }
2849
2850         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2851
2852         return true;
2853 }
2854
2855 static bool nested_vmcb_checks(struct vmcb *vmcb)
2856 {
2857         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2858                 return false;
2859
2860         if (vmcb->control.asid == 0)
2861                 return false;
2862
2863         if (vmcb->control.nested_ctl && !npt_enabled)
2864                 return false;
2865
2866         return true;
2867 }
2868
2869 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2870 {
2871         struct vmcb *nested_vmcb;
2872         struct vmcb *hsave = svm->nested.hsave;
2873         struct vmcb *vmcb = svm->vmcb;
2874         struct page *page;
2875         u64 vmcb_gpa;
2876
2877         vmcb_gpa = svm->vmcb->save.rax;
2878
2879         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2880         if (!nested_vmcb)
2881                 return false;
2882
2883         if (!nested_vmcb_checks(nested_vmcb)) {
2884                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2885                 nested_vmcb->control.exit_code_hi = 0;
2886                 nested_vmcb->control.exit_info_1  = 0;
2887                 nested_vmcb->control.exit_info_2  = 0;
2888
2889                 nested_svm_unmap(page);
2890
2891                 return false;
2892         }
2893
2894         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2895                                nested_vmcb->save.rip,
2896                                nested_vmcb->control.int_ctl,
2897                                nested_vmcb->control.event_inj,
2898                                nested_vmcb->control.nested_ctl);
2899
2900         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2901                                     nested_vmcb->control.intercept_cr >> 16,
2902                                     nested_vmcb->control.intercept_exceptions,
2903                                     nested_vmcb->control.intercept);
2904
2905         /* Clear internal status */
2906         kvm_clear_exception_queue(&svm->vcpu);
2907         kvm_clear_interrupt_queue(&svm->vcpu);
2908
2909         /*
2910          * Save the old vmcb, so we don't need to pick what we save, but can
2911          * restore everything when a VMEXIT occurs
2912          */
2913         hsave->save.es     = vmcb->save.es;
2914         hsave->save.cs     = vmcb->save.cs;
2915         hsave->save.ss     = vmcb->save.ss;
2916         hsave->save.ds     = vmcb->save.ds;
2917         hsave->save.gdtr   = vmcb->save.gdtr;
2918         hsave->save.idtr   = vmcb->save.idtr;
2919         hsave->save.efer   = svm->vcpu.arch.efer;
2920         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2921         hsave->save.cr4    = svm->vcpu.arch.cr4;
2922         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2923         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2924         hsave->save.rsp    = vmcb->save.rsp;
2925         hsave->save.rax    = vmcb->save.rax;
2926         if (npt_enabled)
2927                 hsave->save.cr3    = vmcb->save.cr3;
2928         else
2929                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2930
2931         copy_vmcb_control_area(hsave, vmcb);
2932
2933         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2934                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2935         else
2936                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2937
2938         if (nested_vmcb->control.nested_ctl) {
2939                 kvm_mmu_unload(&svm->vcpu);
2940                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2941                 nested_svm_init_mmu_context(&svm->vcpu);
2942         }
2943
2944         /* Load the nested guest state */
2945         svm->vmcb->save.es = nested_vmcb->save.es;
2946         svm->vmcb->save.cs = nested_vmcb->save.cs;
2947         svm->vmcb->save.ss = nested_vmcb->save.ss;
2948         svm->vmcb->save.ds = nested_vmcb->save.ds;
2949         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2950         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2951         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2952         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2953         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2954         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2955         if (npt_enabled) {
2956                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2957                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2958         } else
2959                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2960
2961         /* Guest paging mode is active - reset mmu */
2962         kvm_mmu_reset_context(&svm->vcpu);
2963
2964         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2965         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2966         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2967         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2968
2969         /* In case we don't even reach vcpu_run, the fields are not updated */
2970         svm->vmcb->save.rax = nested_vmcb->save.rax;
2971         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2972         svm->vmcb->save.rip = nested_vmcb->save.rip;
2973         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2974         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2975         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2976
2977         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2978         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2979
2980         /* cache intercepts */
2981         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2982         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2983         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2984         svm->nested.intercept            = nested_vmcb->control.intercept;
2985
2986         svm_flush_tlb(&svm->vcpu);
2987         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2988         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2989                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2990         else
2991                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2992
2993         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2994                 /* We only want the cr8 intercept bits of the guest */
2995                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2996                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2997         }
2998
2999         /* We don't want to see VMMCALLs from a nested guest */
3000         clr_intercept(svm, INTERCEPT_VMMCALL);
3001
3002         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3003         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3004         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3005         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3006         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3007         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3008
3009         nested_svm_unmap(page);
3010
3011         /* Enter Guest-Mode */
3012         enter_guest_mode(&svm->vcpu);
3013
3014         /*
3015          * Merge guest and host intercepts - must be called  with vcpu in
3016          * guest-mode to take affect here
3017          */
3018         recalc_intercepts(svm);
3019
3020         svm->nested.vmcb = vmcb_gpa;
3021
3022         enable_gif(svm);
3023
3024         mark_all_dirty(svm->vmcb);
3025
3026         return true;
3027 }
3028
3029 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3030 {
3031         to_vmcb->save.fs = from_vmcb->save.fs;
3032         to_vmcb->save.gs = from_vmcb->save.gs;
3033         to_vmcb->save.tr = from_vmcb->save.tr;
3034         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3035         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3036         to_vmcb->save.star = from_vmcb->save.star;
3037         to_vmcb->save.lstar = from_vmcb->save.lstar;
3038         to_vmcb->save.cstar = from_vmcb->save.cstar;
3039         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3040         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3041         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3042         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3043 }
3044
3045 static int vmload_interception(struct vcpu_svm *svm)
3046 {
3047         struct vmcb *nested_vmcb;
3048         struct page *page;
3049
3050         if (nested_svm_check_permissions(svm))
3051                 return 1;
3052
3053         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3054         if (!nested_vmcb)
3055                 return 1;
3056
3057         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3058         skip_emulated_instruction(&svm->vcpu);
3059
3060         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3061         nested_svm_unmap(page);
3062
3063         return 1;
3064 }
3065
3066 static int vmsave_interception(struct vcpu_svm *svm)
3067 {
3068         struct vmcb *nested_vmcb;
3069         struct page *page;
3070
3071         if (nested_svm_check_permissions(svm))
3072                 return 1;
3073
3074         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3075         if (!nested_vmcb)
3076                 return 1;
3077
3078         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3079         skip_emulated_instruction(&svm->vcpu);
3080
3081         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3082         nested_svm_unmap(page);
3083
3084         return 1;
3085 }
3086
3087 static int vmrun_interception(struct vcpu_svm *svm)
3088 {
3089         if (nested_svm_check_permissions(svm))
3090                 return 1;
3091
3092         /* Save rip after vmrun instruction */
3093         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3094
3095         if (!nested_svm_vmrun(svm))
3096                 return 1;
3097
3098         if (!nested_svm_vmrun_msrpm(svm))
3099                 goto failed;
3100
3101         return 1;
3102
3103 failed:
3104
3105         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3106         svm->vmcb->control.exit_code_hi = 0;
3107         svm->vmcb->control.exit_info_1  = 0;
3108         svm->vmcb->control.exit_info_2  = 0;
3109
3110         nested_svm_vmexit(svm);
3111
3112         return 1;
3113 }
3114
3115 static int stgi_interception(struct vcpu_svm *svm)
3116 {
3117         if (nested_svm_check_permissions(svm))
3118                 return 1;
3119
3120         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3121         skip_emulated_instruction(&svm->vcpu);
3122         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3123
3124         enable_gif(svm);
3125
3126         return 1;
3127 }
3128
3129 static int clgi_interception(struct vcpu_svm *svm)
3130 {
3131         if (nested_svm_check_permissions(svm))
3132                 return 1;
3133
3134         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3135         skip_emulated_instruction(&svm->vcpu);
3136
3137         disable_gif(svm);
3138
3139         /* After a CLGI no interrupts should come */
3140         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3141                 svm_clear_vintr(svm);
3142                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3143                 mark_dirty(svm->vmcb, VMCB_INTR);
3144         }
3145
3146         return 1;
3147 }
3148
3149 static int invlpga_interception(struct vcpu_svm *svm)
3150 {
3151         struct kvm_vcpu *vcpu = &svm->vcpu;
3152
3153         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3154                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3155
3156         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3157         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3158
3159         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3160         skip_emulated_instruction(&svm->vcpu);
3161         return 1;
3162 }
3163
3164 static int skinit_interception(struct vcpu_svm *svm)
3165 {
3166         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3167
3168         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3169         return 1;
3170 }
3171
3172 static int wbinvd_interception(struct vcpu_svm *svm)
3173 {
3174         kvm_emulate_wbinvd(&svm->vcpu);
3175         return 1;
3176 }
3177
3178 static int xsetbv_interception(struct vcpu_svm *svm)
3179 {
3180         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3181         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3182
3183         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3184                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3185                 skip_emulated_instruction(&svm->vcpu);
3186         }
3187
3188         return 1;
3189 }
3190
3191 static int task_switch_interception(struct vcpu_svm *svm)
3192 {
3193         u16 tss_selector;
3194         int reason;
3195         int int_type = svm->vmcb->control.exit_int_info &
3196                 SVM_EXITINTINFO_TYPE_MASK;
3197         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3198         uint32_t type =
3199                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3200         uint32_t idt_v =
3201                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3202         bool has_error_code = false;
3203         u32 error_code = 0;
3204
3205         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3206
3207         if (svm->vmcb->control.exit_info_2 &
3208             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3209                 reason = TASK_SWITCH_IRET;
3210         else if (svm->vmcb->control.exit_info_2 &
3211                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3212                 reason = TASK_SWITCH_JMP;
3213         else if (idt_v)
3214                 reason = TASK_SWITCH_GATE;
3215         else
3216                 reason = TASK_SWITCH_CALL;
3217
3218         if (reason == TASK_SWITCH_GATE) {
3219                 switch (type) {
3220                 case SVM_EXITINTINFO_TYPE_NMI:
3221                         svm->vcpu.arch.nmi_injected = false;
3222                         break;
3223                 case SVM_EXITINTINFO_TYPE_EXEPT:
3224                         if (svm->vmcb->control.exit_info_2 &
3225                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3226                                 has_error_code = true;
3227                                 error_code =
3228                                         (u32)svm->vmcb->control.exit_info_2;
3229                         }
3230                         kvm_clear_exception_queue(&svm->vcpu);
3231                         break;
3232                 case SVM_EXITINTINFO_TYPE_INTR:
3233                         kvm_clear_interrupt_queue(&svm->vcpu);
3234                         break;
3235                 default:
3236                         break;
3237                 }
3238         }
3239
3240         if (reason != TASK_SWITCH_GATE ||
3241             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3242             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3243              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3244                 skip_emulated_instruction(&svm->vcpu);
3245
3246         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3247                 int_vec = -1;
3248
3249         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3250                                 has_error_code, error_code) == EMULATE_FAIL) {
3251                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3252                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3253                 svm->vcpu.run->internal.ndata = 0;
3254                 return 0;
3255         }
3256         return 1;
3257 }
3258
3259 static int cpuid_interception(struct vcpu_svm *svm)
3260 {
3261         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3262         kvm_emulate_cpuid(&svm->vcpu);
3263         return 1;
3264 }
3265
3266 static int iret_interception(struct vcpu_svm *svm)
3267 {
3268         ++svm->vcpu.stat.nmi_window_exits;
3269         clr_intercept(svm, INTERCEPT_IRET);
3270         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3271         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3272         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3273         return 1;
3274 }
3275
3276 static int invlpg_interception(struct vcpu_svm *svm)
3277 {
3278         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3279                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3280
3281         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3282         skip_emulated_instruction(&svm->vcpu);
3283         return 1;
3284 }
3285
3286 static int emulate_on_interception(struct vcpu_svm *svm)
3287 {
3288         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3289 }
3290
3291 static int rdpmc_interception(struct vcpu_svm *svm)
3292 {
3293         int err;
3294
3295         if (!static_cpu_has(X86_FEATURE_NRIPS))
3296                 return emulate_on_interception(svm);
3297
3298         err = kvm_rdpmc(&svm->vcpu);
3299         kvm_complete_insn_gp(&svm->vcpu, err);
3300
3301         return 1;
3302 }
3303
3304 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3305                                             unsigned long val)
3306 {
3307         unsigned long cr0 = svm->vcpu.arch.cr0;
3308         bool ret = false;
3309         u64 intercept;
3310
3311         intercept = svm->nested.intercept;
3312
3313         if (!is_guest_mode(&svm->vcpu) ||
3314             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3315                 return false;
3316
3317         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3318         val &= ~SVM_CR0_SELECTIVE_MASK;
3319
3320         if (cr0 ^ val) {
3321                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3322                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3323         }
3324
3325         return ret;
3326 }
3327
3328 #define CR_VALID (1ULL << 63)
3329
3330 static int cr_interception(struct vcpu_svm *svm)
3331 {
3332         int reg, cr;
3333         unsigned long val;
3334         int err;
3335
3336         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3337                 return emulate_on_interception(svm);
3338
3339         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3340                 return emulate_on_interception(svm);
3341
3342         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3343         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3344                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3345         else
3346                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3347
3348         err = 0;
3349         if (cr >= 16) { /* mov to cr */
3350                 cr -= 16;
3351                 val = kvm_register_read(&svm->vcpu, reg);
3352                 switch (cr) {
3353                 case 0:
3354                         if (!check_selective_cr0_intercepted(svm, val))
3355                                 err = kvm_set_cr0(&svm->vcpu, val);
3356                         else
3357                                 return 1;
3358
3359                         break;
3360                 case 3:
3361                         err = kvm_set_cr3(&svm->vcpu, val);
3362                         break;
3363                 case 4:
3364                         err = kvm_set_cr4(&svm->vcpu, val);
3365                         break;
3366                 case 8:
3367                         err = kvm_set_cr8(&svm->vcpu, val);
3368                         break;
3369                 default:
3370                         WARN(1, "unhandled write to CR%d", cr);
3371                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3372                         return 1;
3373                 }
3374         } else { /* mov from cr */
3375                 switch (cr) {
3376                 case 0:
3377                         val = kvm_read_cr0(&svm->vcpu);
3378                         break;
3379                 case 2:
3380                         val = svm->vcpu.arch.cr2;
3381                         break;
3382                 case 3:
3383                         val = kvm_read_cr3(&svm->vcpu);
3384                         break;
3385                 case 4:
3386                         val = kvm_read_cr4(&svm->vcpu);
3387                         break;
3388                 case 8:
3389                         val = kvm_get_cr8(&svm->vcpu);
3390                         break;
3391                 default:
3392                         WARN(1, "unhandled read from CR%d", cr);
3393                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3394                         return 1;
3395                 }
3396                 kvm_register_write(&svm->vcpu, reg, val);
3397         }
3398         kvm_complete_insn_gp(&svm->vcpu, err);
3399
3400         return 1;
3401 }
3402
3403 static int dr_interception(struct vcpu_svm *svm)
3404 {
3405         int reg, dr;
3406         unsigned long val;
3407
3408         if (svm->vcpu.guest_debug == 0) {
3409                 /*
3410                  * No more DR vmexits; force a reload of the debug registers
3411                  * and reenter on this instruction.  The next vmexit will
3412                  * retrieve the full state of the debug registers.
3413                  */
3414                 clr_dr_intercepts(svm);
3415                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3416                 return 1;
3417         }
3418
3419         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3420                 return emulate_on_interception(svm);
3421
3422         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3423         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3424
3425         if (dr >= 16) { /* mov to DRn */
3426                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3427                         return 1;
3428                 val = kvm_register_read(&svm->vcpu, reg);
3429                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3430         } else {
3431                 if (!kvm_require_dr(&svm->vcpu, dr))
3432                         return 1;
3433                 kvm_get_dr(&svm->vcpu, dr, &val);
3434                 kvm_register_write(&svm->vcpu, reg, val);
3435         }
3436
3437         skip_emulated_instruction(&svm->vcpu);
3438
3439         return 1;
3440 }
3441
3442 static int cr8_write_interception(struct vcpu_svm *svm)
3443 {
3444         struct kvm_run *kvm_run = svm->vcpu.run;
3445         int r;
3446
3447         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3448         /* instruction emulation calls kvm_set_cr8() */
3449         r = cr_interception(svm);
3450         if (lapic_in_kernel(&svm->vcpu))
3451                 return r;
3452         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3453                 return r;
3454         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3455         return 0;
3456 }
3457
3458 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3459 {
3460         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3461         return vmcb->control.tsc_offset + host_tsc;
3462 }
3463
3464 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3465 {
3466         struct vcpu_svm *svm = to_svm(vcpu);
3467
3468         switch (msr_info->index) {
3469         case MSR_IA32_TSC: {
3470                 msr_info->data = svm->vmcb->control.tsc_offset +
3471                         kvm_scale_tsc(vcpu, rdtsc());
3472
3473                 break;
3474         }
3475         case MSR_STAR:
3476                 msr_info->data = svm->vmcb->save.star;
3477                 break;
3478 #ifdef CONFIG_X86_64
3479         case MSR_LSTAR:
3480                 msr_info->data = svm->vmcb->save.lstar;
3481                 break;
3482         case MSR_CSTAR:
3483                 msr_info->data = svm->vmcb->save.cstar;
3484                 break;
3485         case MSR_KERNEL_GS_BASE:
3486                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3487                 break;
3488         case MSR_SYSCALL_MASK:
3489                 msr_info->data = svm->vmcb->save.sfmask;
3490                 break;
3491 #endif
3492         case MSR_IA32_SYSENTER_CS:
3493                 msr_info->data = svm->vmcb->save.sysenter_cs;
3494                 break;
3495         case MSR_IA32_SYSENTER_EIP:
3496                 msr_info->data = svm->sysenter_eip;
3497                 break;
3498         case MSR_IA32_SYSENTER_ESP:
3499                 msr_info->data = svm->sysenter_esp;
3500                 break;
3501         case MSR_TSC_AUX:
3502                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3503                         return 1;
3504                 msr_info->data = svm->tsc_aux;
3505                 break;
3506         /*
3507          * Nobody will change the following 5 values in the VMCB so we can
3508          * safely return them on rdmsr. They will always be 0 until LBRV is
3509          * implemented.
3510          */
3511         case MSR_IA32_DEBUGCTLMSR:
3512                 msr_info->data = svm->vmcb->save.dbgctl;
3513                 break;
3514         case MSR_IA32_LASTBRANCHFROMIP:
3515                 msr_info->data = svm->vmcb->save.br_from;
3516                 break;
3517         case MSR_IA32_LASTBRANCHTOIP:
3518                 msr_info->data = svm->vmcb->save.br_to;
3519                 break;
3520         case MSR_IA32_LASTINTFROMIP:
3521                 msr_info->data = svm->vmcb->save.last_excp_from;
3522                 break;
3523         case MSR_IA32_LASTINTTOIP:
3524                 msr_info->data = svm->vmcb->save.last_excp_to;
3525                 break;
3526         case MSR_VM_HSAVE_PA:
3527                 msr_info->data = svm->nested.hsave_msr;
3528                 break;
3529         case MSR_VM_CR:
3530                 msr_info->data = svm->nested.vm_cr_msr;
3531                 break;
3532         case MSR_IA32_UCODE_REV:
3533                 msr_info->data = 0x01000065;
3534                 break;
3535         case MSR_F15H_IC_CFG: {
3536
3537                 int family, model;
3538
3539                 family = guest_cpuid_family(vcpu);
3540                 model  = guest_cpuid_model(vcpu);
3541
3542                 if (family < 0 || model < 0)
3543                         return kvm_get_msr_common(vcpu, msr_info);
3544
3545                 msr_info->data = 0;
3546
3547                 if (family == 0x15 &&
3548                     (model >= 0x2 && model < 0x20))
3549                         msr_info->data = 0x1E;
3550                 }
3551                 break;
3552         default:
3553                 return kvm_get_msr_common(vcpu, msr_info);
3554         }
3555         return 0;
3556 }
3557
3558 static int rdmsr_interception(struct vcpu_svm *svm)
3559 {
3560         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3561         struct msr_data msr_info;
3562
3563         msr_info.index = ecx;
3564         msr_info.host_initiated = false;
3565         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3566                 trace_kvm_msr_read_ex(ecx);
3567                 kvm_inject_gp(&svm->vcpu, 0);
3568         } else {
3569                 trace_kvm_msr_read(ecx, msr_info.data);
3570
3571                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3572                                    msr_info.data & 0xffffffff);
3573                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3574                                    msr_info.data >> 32);
3575                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3576                 skip_emulated_instruction(&svm->vcpu);
3577         }
3578         return 1;
3579 }
3580
3581 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3582 {
3583         struct vcpu_svm *svm = to_svm(vcpu);
3584         int svm_dis, chg_mask;
3585
3586         if (data & ~SVM_VM_CR_VALID_MASK)
3587                 return 1;
3588
3589         chg_mask = SVM_VM_CR_VALID_MASK;
3590
3591         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3592                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3593
3594         svm->nested.vm_cr_msr &= ~chg_mask;
3595         svm->nested.vm_cr_msr |= (data & chg_mask);
3596
3597         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3598
3599         /* check for svm_disable while efer.svme is set */
3600         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3601                 return 1;
3602
3603         return 0;
3604 }
3605
3606 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3607 {
3608         struct vcpu_svm *svm = to_svm(vcpu);
3609
3610         u32 ecx = msr->index;
3611         u64 data = msr->data;
3612         switch (ecx) {
3613         case MSR_IA32_TSC:
3614                 kvm_write_tsc(vcpu, msr);
3615                 break;
3616         case MSR_STAR:
3617                 svm->vmcb->save.star = data;
3618                 break;
3619 #ifdef CONFIG_X86_64
3620         case MSR_LSTAR:
3621                 svm->vmcb->save.lstar = data;
3622                 break;
3623         case MSR_CSTAR:
3624                 svm->vmcb->save.cstar = data;
3625                 break;
3626         case MSR_KERNEL_GS_BASE:
3627                 svm->vmcb->save.kernel_gs_base = data;
3628                 break;
3629         case MSR_SYSCALL_MASK:
3630                 svm->vmcb->save.sfmask = data;
3631                 break;
3632 #endif
3633         case MSR_IA32_SYSENTER_CS:
3634                 svm->vmcb->save.sysenter_cs = data;
3635                 break;
3636         case MSR_IA32_SYSENTER_EIP:
3637                 svm->sysenter_eip = data;
3638                 svm->vmcb->save.sysenter_eip = data;
3639                 break;
3640         case MSR_IA32_SYSENTER_ESP:
3641                 svm->sysenter_esp = data;
3642                 svm->vmcb->save.sysenter_esp = data;
3643                 break;
3644         case MSR_TSC_AUX:
3645                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3646                         return 1;
3647
3648                 /*
3649                  * This is rare, so we update the MSR here instead of using
3650                  * direct_access_msrs.  Doing that would require a rdmsr in
3651                  * svm_vcpu_put.
3652                  */
3653                 svm->tsc_aux = data;
3654                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3655                 break;
3656         case MSR_IA32_DEBUGCTLMSR:
3657                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3658                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3659                                     __func__, data);
3660                         break;
3661                 }
3662                 if (data & DEBUGCTL_RESERVED_BITS)
3663                         return 1;
3664
3665                 svm->vmcb->save.dbgctl = data;
3666                 mark_dirty(svm->vmcb, VMCB_LBR);
3667                 if (data & (1ULL<<0))
3668                         svm_enable_lbrv(svm);
3669                 else
3670                         svm_disable_lbrv(svm);
3671                 break;
3672         case MSR_VM_HSAVE_PA:
3673                 svm->nested.hsave_msr = data;
3674                 break;
3675         case MSR_VM_CR:
3676                 return svm_set_vm_cr(vcpu, data);
3677         case MSR_VM_IGNNE:
3678                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3679                 break;
3680         case MSR_IA32_APICBASE:
3681                 if (kvm_vcpu_apicv_active(vcpu))
3682                         avic_update_vapic_bar(to_svm(vcpu), data);
3683                 /* Follow through */
3684         default:
3685                 return kvm_set_msr_common(vcpu, msr);
3686         }
3687         return 0;
3688 }
3689
3690 static int wrmsr_interception(struct vcpu_svm *svm)
3691 {
3692         struct msr_data msr;
3693         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3694         u64 data = kvm_read_edx_eax(&svm->vcpu);
3695
3696         msr.data = data;
3697         msr.index = ecx;
3698         msr.host_initiated = false;
3699
3700         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3701         if (kvm_set_msr(&svm->vcpu, &msr)) {
3702                 trace_kvm_msr_write_ex(ecx, data);
3703                 kvm_inject_gp(&svm->vcpu, 0);
3704         } else {
3705                 trace_kvm_msr_write(ecx, data);
3706                 skip_emulated_instruction(&svm->vcpu);
3707         }
3708         return 1;
3709 }
3710
3711 static int msr_interception(struct vcpu_svm *svm)
3712 {
3713         if (svm->vmcb->control.exit_info_1)
3714                 return wrmsr_interception(svm);
3715         else
3716                 return rdmsr_interception(svm);
3717 }
3718
3719 static int interrupt_window_interception(struct vcpu_svm *svm)
3720 {
3721         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3722         svm_clear_vintr(svm);
3723         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3724         mark_dirty(svm->vmcb, VMCB_INTR);
3725         ++svm->vcpu.stat.irq_window_exits;
3726         return 1;
3727 }
3728
3729 static int pause_interception(struct vcpu_svm *svm)
3730 {
3731         kvm_vcpu_on_spin(&(svm->vcpu));
3732         return 1;
3733 }
3734
3735 static int nop_interception(struct vcpu_svm *svm)
3736 {
3737         skip_emulated_instruction(&(svm->vcpu));
3738         return 1;
3739 }
3740
3741 static int monitor_interception(struct vcpu_svm *svm)
3742 {
3743         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3744         return nop_interception(svm);
3745 }
3746
3747 static int mwait_interception(struct vcpu_svm *svm)
3748 {
3749         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3750         return nop_interception(svm);
3751 }
3752
3753 enum avic_ipi_failure_cause {
3754         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3755         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3756         AVIC_IPI_FAILURE_INVALID_TARGET,
3757         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3758 };
3759
3760 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3761 {
3762         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3763         u32 icrl = svm->vmcb->control.exit_info_1;
3764         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3765         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3766         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3767
3768         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3769
3770         switch (id) {
3771         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3772                 /*
3773                  * AVIC hardware handles the generation of
3774                  * IPIs when the specified Message Type is Fixed
3775                  * (also known as fixed delivery mode) and
3776                  * the Trigger Mode is edge-triggered. The hardware
3777                  * also supports self and broadcast delivery modes
3778                  * specified via the Destination Shorthand(DSH)
3779                  * field of the ICRL. Logical and physical APIC ID
3780                  * formats are supported. All other IPI types cause
3781                  * a #VMEXIT, which needs to emulated.
3782                  */
3783                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3784                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3785                 break;
3786         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3787                 int i;
3788                 struct kvm_vcpu *vcpu;
3789                 struct kvm *kvm = svm->vcpu.kvm;
3790                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3791
3792                 /*
3793                  * At this point, we expect that the AVIC HW has already
3794                  * set the appropriate IRR bits on the valid target
3795                  * vcpus. So, we just need to kick the appropriate vcpu.
3796                  */
3797                 kvm_for_each_vcpu(i, vcpu, kvm) {
3798                         bool m = kvm_apic_match_dest(vcpu, apic,
3799                                                      icrl & KVM_APIC_SHORT_MASK,
3800                                                      GET_APIC_DEST_FIELD(icrh),
3801                                                      icrl & KVM_APIC_DEST_MASK);
3802
3803                         if (m && !avic_vcpu_is_running(vcpu))
3804                                 kvm_vcpu_wake_up(vcpu);
3805                 }
3806                 break;
3807         }
3808         case AVIC_IPI_FAILURE_INVALID_TARGET:
3809                 break;
3810         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3811                 WARN_ONCE(1, "Invalid backing page\n");
3812                 break;
3813         default:
3814                 pr_err("Unknown IPI interception\n");
3815         }
3816
3817         return 1;
3818 }
3819
3820 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3821 {
3822         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3823         int index;
3824         u32 *logical_apic_id_table;
3825         int dlid = GET_APIC_LOGICAL_ID(ldr);
3826
3827         if (!dlid)
3828                 return NULL;
3829
3830         if (flat) { /* flat */
3831                 index = ffs(dlid) - 1;
3832                 if (index > 7)
3833                         return NULL;
3834         } else { /* cluster */
3835                 int cluster = (dlid & 0xf0) >> 4;
3836                 int apic = ffs(dlid & 0x0f) - 1;
3837
3838                 if ((apic < 0) || (apic > 7) ||
3839                     (cluster >= 0xf))
3840                         return NULL;
3841                 index = (cluster << 2) + apic;
3842         }
3843
3844         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3845
3846         return &logical_apic_id_table[index];
3847 }
3848
3849 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3850                           bool valid)
3851 {
3852         bool flat;
3853         u32 *entry, new_entry;
3854
3855         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3856         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3857         if (!entry)
3858                 return -EINVAL;
3859
3860         new_entry = READ_ONCE(*entry);
3861         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3862         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3863         if (valid)
3864                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3865         else
3866                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3867         WRITE_ONCE(*entry, new_entry);
3868
3869         return 0;
3870 }
3871
3872 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3873 {
3874         int ret;
3875         struct vcpu_svm *svm = to_svm(vcpu);
3876         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3877
3878         if (!ldr)
3879                 return 1;
3880
3881         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3882         if (ret && svm->ldr_reg) {
3883                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3884                 svm->ldr_reg = 0;
3885         } else {
3886                 svm->ldr_reg = ldr;
3887         }
3888         return ret;
3889 }
3890
3891 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3892 {
3893         u64 *old, *new;
3894         struct vcpu_svm *svm = to_svm(vcpu);
3895         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3896         u32 id = (apic_id_reg >> 24) & 0xff;
3897
3898         if (vcpu->vcpu_id == id)
3899                 return 0;
3900
3901         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3902         new = avic_get_physical_id_entry(vcpu, id);
3903         if (!new || !old)
3904                 return 1;
3905
3906         /* We need to move physical_id_entry to new offset */
3907         *new = *old;
3908         *old = 0ULL;
3909         to_svm(vcpu)->avic_physical_id_cache = new;
3910
3911         /*
3912          * Also update the guest physical APIC ID in the logical
3913          * APIC ID table entry if already setup the LDR.
3914          */
3915         if (svm->ldr_reg)
3916                 avic_handle_ldr_update(vcpu);
3917
3918         return 0;
3919 }
3920
3921 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3922 {
3923         struct vcpu_svm *svm = to_svm(vcpu);
3924         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3925         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3926         u32 mod = (dfr >> 28) & 0xf;
3927
3928         /*
3929          * We assume that all local APICs are using the same type.
3930          * If this changes, we need to flush the AVIC logical
3931          * APID id table.
3932          */
3933         if (vm_data->ldr_mode == mod)
3934                 return 0;
3935
3936         clear_page(page_address(vm_data->avic_logical_id_table_page));
3937         vm_data->ldr_mode = mod;
3938
3939         if (svm->ldr_reg)
3940                 avic_handle_ldr_update(vcpu);
3941         return 0;
3942 }
3943
3944 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3945 {
3946         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3947         u32 offset = svm->vmcb->control.exit_info_1 &
3948                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3949
3950         switch (offset) {
3951         case APIC_ID:
3952                 if (avic_handle_apic_id_update(&svm->vcpu))
3953                         return 0;
3954                 break;
3955         case APIC_LDR:
3956                 if (avic_handle_ldr_update(&svm->vcpu))
3957                         return 0;
3958                 break;
3959         case APIC_DFR:
3960                 avic_handle_dfr_update(&svm->vcpu);
3961                 break;
3962         default:
3963                 break;
3964         }
3965
3966         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3967
3968         return 1;
3969 }
3970
3971 static bool is_avic_unaccelerated_access_trap(u32 offset)
3972 {
3973         bool ret = false;
3974
3975         switch (offset) {
3976         case APIC_ID:
3977         case APIC_EOI:
3978         case APIC_RRR:
3979         case APIC_LDR:
3980         case APIC_DFR:
3981         case APIC_SPIV:
3982         case APIC_ESR:
3983         case APIC_ICR:
3984         case APIC_LVTT:
3985         case APIC_LVTTHMR:
3986         case APIC_LVTPC:
3987         case APIC_LVT0:
3988         case APIC_LVT1:
3989         case APIC_LVTERR:
3990         case APIC_TMICT:
3991         case APIC_TDCR:
3992                 ret = true;
3993                 break;
3994         default:
3995                 break;
3996         }
3997         return ret;
3998 }
3999
4000 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4001 {
4002         int ret = 0;
4003         u32 offset = svm->vmcb->control.exit_info_1 &
4004                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4005         u32 vector = svm->vmcb->control.exit_info_2 &
4006                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4007         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4008                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4009         bool trap = is_avic_unaccelerated_access_trap(offset);
4010
4011         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4012                                             trap, write, vector);
4013         if (trap) {
4014                 /* Handling Trap */
4015                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4016                 ret = avic_unaccel_trap_write(svm);
4017         } else {
4018                 /* Handling Fault */
4019                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4020         }
4021
4022         return ret;
4023 }
4024
4025 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4026         [SVM_EXIT_READ_CR0]                     = cr_interception,
4027         [SVM_EXIT_READ_CR3]                     = cr_interception,
4028         [SVM_EXIT_READ_CR4]                     = cr_interception,
4029         [SVM_EXIT_READ_CR8]                     = cr_interception,
4030         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4031         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4032         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4033         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4034         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4035         [SVM_EXIT_READ_DR0]                     = dr_interception,
4036         [SVM_EXIT_READ_DR1]                     = dr_interception,
4037         [SVM_EXIT_READ_DR2]                     = dr_interception,
4038         [SVM_EXIT_READ_DR3]                     = dr_interception,
4039         [SVM_EXIT_READ_DR4]                     = dr_interception,
4040         [SVM_EXIT_READ_DR5]                     = dr_interception,
4041         [SVM_EXIT_READ_DR6]                     = dr_interception,
4042         [SVM_EXIT_READ_DR7]                     = dr_interception,
4043         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4044         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4045         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4046         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4047         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4048         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4049         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4050         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4051         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4052         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4053         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4054         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4055         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
4056         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4057         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4058         [SVM_EXIT_INTR]                         = intr_interception,
4059         [SVM_EXIT_NMI]                          = nmi_interception,
4060         [SVM_EXIT_SMI]                          = nop_on_interception,
4061         [SVM_EXIT_INIT]                         = nop_on_interception,
4062         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4063         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4064         [SVM_EXIT_CPUID]                        = cpuid_interception,
4065         [SVM_EXIT_IRET]                         = iret_interception,
4066         [SVM_EXIT_INVD]                         = emulate_on_interception,
4067         [SVM_EXIT_PAUSE]                        = pause_interception,
4068         [SVM_EXIT_HLT]                          = halt_interception,
4069         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4070         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4071         [SVM_EXIT_IOIO]                         = io_interception,
4072         [SVM_EXIT_MSR]                          = msr_interception,
4073         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4074         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4075         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4076         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4077         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4078         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4079         [SVM_EXIT_STGI]                         = stgi_interception,
4080         [SVM_EXIT_CLGI]                         = clgi_interception,
4081         [SVM_EXIT_SKINIT]                       = skinit_interception,
4082         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4083         [SVM_EXIT_MONITOR]                      = monitor_interception,
4084         [SVM_EXIT_MWAIT]                        = mwait_interception,
4085         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4086         [SVM_EXIT_NPF]                          = pf_interception,
4087         [SVM_EXIT_RSM]                          = emulate_on_interception,
4088         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4089         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4090 };
4091
4092 static void dump_vmcb(struct kvm_vcpu *vcpu)
4093 {
4094         struct vcpu_svm *svm = to_svm(vcpu);
4095         struct vmcb_control_area *control = &svm->vmcb->control;
4096         struct vmcb_save_area *save = &svm->vmcb->save;
4097
4098         pr_err("VMCB Control Area:\n");
4099         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4100         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4101         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4102         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4103         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4104         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4105         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4106         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4107         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4108         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4109         pr_err("%-20s%d\n", "asid:", control->asid);
4110         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4111         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4112         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4113         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4114         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4115         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4116         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4117         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4118         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4119         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4120         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4121         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4122         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4123         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4124         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4125         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4126         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4127         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4128         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4129         pr_err("VMCB State Save Area:\n");
4130         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4131                "es:",
4132                save->es.selector, save->es.attrib,
4133                save->es.limit, save->es.base);
4134         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4135                "cs:",
4136                save->cs.selector, save->cs.attrib,
4137                save->cs.limit, save->cs.base);
4138         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4139                "ss:",
4140                save->ss.selector, save->ss.attrib,
4141                save->ss.limit, save->ss.base);
4142         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4143                "ds:",
4144                save->ds.selector, save->ds.attrib,
4145                save->ds.limit, save->ds.base);
4146         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4147                "fs:",
4148                save->fs.selector, save->fs.attrib,
4149                save->fs.limit, save->fs.base);
4150         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4151                "gs:",
4152                save->gs.selector, save->gs.attrib,
4153                save->gs.limit, save->gs.base);
4154         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4155                "gdtr:",
4156                save->gdtr.selector, save->gdtr.attrib,
4157                save->gdtr.limit, save->gdtr.base);
4158         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4159                "ldtr:",
4160                save->ldtr.selector, save->ldtr.attrib,
4161                save->ldtr.limit, save->ldtr.base);
4162         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4163                "idtr:",
4164                save->idtr.selector, save->idtr.attrib,
4165                save->idtr.limit, save->idtr.base);
4166         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4167                "tr:",
4168                save->tr.selector, save->tr.attrib,
4169                save->tr.limit, save->tr.base);
4170         pr_err("cpl:            %d                efer:         %016llx\n",
4171                 save->cpl, save->efer);
4172         pr_err("%-15s %016llx %-13s %016llx\n",
4173                "cr0:", save->cr0, "cr2:", save->cr2);
4174         pr_err("%-15s %016llx %-13s %016llx\n",
4175                "cr3:", save->cr3, "cr4:", save->cr4);
4176         pr_err("%-15s %016llx %-13s %016llx\n",
4177                "dr6:", save->dr6, "dr7:", save->dr7);
4178         pr_err("%-15s %016llx %-13s %016llx\n",
4179                "rip:", save->rip, "rflags:", save->rflags);
4180         pr_err("%-15s %016llx %-13s %016llx\n",
4181                "rsp:", save->rsp, "rax:", save->rax);
4182         pr_err("%-15s %016llx %-13s %016llx\n",
4183                "star:", save->star, "lstar:", save->lstar);
4184         pr_err("%-15s %016llx %-13s %016llx\n",
4185                "cstar:", save->cstar, "sfmask:", save->sfmask);
4186         pr_err("%-15s %016llx %-13s %016llx\n",
4187                "kernel_gs_base:", save->kernel_gs_base,
4188                "sysenter_cs:", save->sysenter_cs);
4189         pr_err("%-15s %016llx %-13s %016llx\n",
4190                "sysenter_esp:", save->sysenter_esp,
4191                "sysenter_eip:", save->sysenter_eip);
4192         pr_err("%-15s %016llx %-13s %016llx\n",
4193                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4194         pr_err("%-15s %016llx %-13s %016llx\n",
4195                "br_from:", save->br_from, "br_to:", save->br_to);
4196         pr_err("%-15s %016llx %-13s %016llx\n",
4197                "excp_from:", save->last_excp_from,
4198                "excp_to:", save->last_excp_to);
4199 }
4200
4201 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4202 {
4203         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4204
4205         *info1 = control->exit_info_1;
4206         *info2 = control->exit_info_2;
4207 }
4208
4209 static int handle_exit(struct kvm_vcpu *vcpu)
4210 {
4211         struct vcpu_svm *svm = to_svm(vcpu);
4212         struct kvm_run *kvm_run = vcpu->run;
4213         u32 exit_code = svm->vmcb->control.exit_code;
4214
4215         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4216
4217         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4218                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4219         if (npt_enabled)
4220                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4221
4222         if (unlikely(svm->nested.exit_required)) {
4223                 nested_svm_vmexit(svm);
4224                 svm->nested.exit_required = false;
4225
4226                 return 1;
4227         }
4228
4229         if (is_guest_mode(vcpu)) {
4230                 int vmexit;
4231
4232                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4233                                         svm->vmcb->control.exit_info_1,
4234                                         svm->vmcb->control.exit_info_2,
4235                                         svm->vmcb->control.exit_int_info,
4236                                         svm->vmcb->control.exit_int_info_err,
4237                                         KVM_ISA_SVM);
4238
4239                 vmexit = nested_svm_exit_special(svm);
4240
4241                 if (vmexit == NESTED_EXIT_CONTINUE)
4242                         vmexit = nested_svm_exit_handled(svm);
4243
4244                 if (vmexit == NESTED_EXIT_DONE)
4245                         return 1;
4246         }
4247
4248         svm_complete_interrupts(svm);
4249
4250         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4251                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4252                 kvm_run->fail_entry.hardware_entry_failure_reason
4253                         = svm->vmcb->control.exit_code;
4254                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4255                 dump_vmcb(vcpu);
4256                 return 0;
4257         }
4258
4259         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4260             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4261             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4262             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4263                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4264                        "exit_code 0x%x\n",
4265                        __func__, svm->vmcb->control.exit_int_info,
4266                        exit_code);
4267
4268         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4269             || !svm_exit_handlers[exit_code]) {
4270                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4271                 kvm_queue_exception(vcpu, UD_VECTOR);
4272                 return 1;
4273         }
4274
4275         return svm_exit_handlers[exit_code](svm);
4276 }
4277
4278 static void reload_tss(struct kvm_vcpu *vcpu)
4279 {
4280         int cpu = raw_smp_processor_id();
4281
4282         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4283         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4284         load_TR_desc();
4285 }
4286
4287 static void pre_svm_run(struct vcpu_svm *svm)
4288 {
4289         int cpu = raw_smp_processor_id();
4290
4291         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4292
4293         /* FIXME: handle wraparound of asid_generation */
4294         if (svm->asid_generation != sd->asid_generation)
4295                 new_asid(svm, sd);
4296 }
4297
4298 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4299 {
4300         struct vcpu_svm *svm = to_svm(vcpu);
4301
4302         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4303         vcpu->arch.hflags |= HF_NMI_MASK;
4304         set_intercept(svm, INTERCEPT_IRET);
4305         ++vcpu->stat.nmi_injections;
4306 }
4307
4308 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4309 {
4310         struct vmcb_control_area *control;
4311
4312         /* The following fields are ignored when AVIC is enabled */
4313         control = &svm->vmcb->control;
4314         control->int_vector = irq;
4315         control->int_ctl &= ~V_INTR_PRIO_MASK;
4316         control->int_ctl |= V_IRQ_MASK |
4317                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4318         mark_dirty(svm->vmcb, VMCB_INTR);
4319 }
4320
4321 static void svm_set_irq(struct kvm_vcpu *vcpu)
4322 {
4323         struct vcpu_svm *svm = to_svm(vcpu);
4324
4325         BUG_ON(!(gif_set(svm)));
4326
4327         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4328         ++vcpu->stat.irq_injections;
4329
4330         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4331                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4332 }
4333
4334 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4335 {
4336         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4337 }
4338
4339 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4340 {
4341         struct vcpu_svm *svm = to_svm(vcpu);
4342
4343         if (svm_nested_virtualize_tpr(vcpu) ||
4344             kvm_vcpu_apicv_active(vcpu))
4345                 return;
4346
4347         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4348
4349         if (irr == -1)
4350                 return;
4351
4352         if (tpr >= irr)
4353                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4354 }
4355
4356 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4357 {
4358         return;
4359 }
4360
4361 static bool svm_get_enable_apicv(void)
4362 {
4363         return avic;
4364 }
4365
4366 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4367 {
4368 }
4369
4370 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4371 {
4372 }
4373
4374 /* Note: Currently only used by Hyper-V. */
4375 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4376 {
4377         struct vcpu_svm *svm = to_svm(vcpu);
4378         struct vmcb *vmcb = svm->vmcb;
4379
4380         if (!avic)
4381                 return;
4382
4383         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4384         mark_dirty(vmcb, VMCB_INTR);
4385 }
4386
4387 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4388 {
4389         return;
4390 }
4391
4392 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4393 {
4394         return;
4395 }
4396
4397 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4398 {
4399         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4400         smp_mb__after_atomic();
4401
4402         if (avic_vcpu_is_running(vcpu))
4403                 wrmsrl(SVM_AVIC_DOORBELL,
4404                        kvm_cpu_get_apicid(vcpu->cpu));
4405         else
4406                 kvm_vcpu_wake_up(vcpu);
4407 }
4408
4409 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4410 {
4411         unsigned long flags;
4412         struct amd_svm_iommu_ir *cur;
4413
4414         spin_lock_irqsave(&svm->ir_list_lock, flags);
4415         list_for_each_entry(cur, &svm->ir_list, node) {
4416                 if (cur->data != pi->ir_data)
4417                         continue;
4418                 list_del(&cur->node);
4419                 kfree(cur);
4420                 break;
4421         }
4422         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4423 }
4424
4425 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4426 {
4427         int ret = 0;
4428         unsigned long flags;
4429         struct amd_svm_iommu_ir *ir;
4430
4431         /**
4432          * In some cases, the existing irte is updaed and re-set,
4433          * so we need to check here if it's already been * added
4434          * to the ir_list.
4435          */
4436         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4437                 struct kvm *kvm = svm->vcpu.kvm;
4438                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4439                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4440                 struct vcpu_svm *prev_svm;
4441
4442                 if (!prev_vcpu) {
4443                         ret = -EINVAL;
4444                         goto out;
4445                 }
4446
4447                 prev_svm = to_svm(prev_vcpu);
4448                 svm_ir_list_del(prev_svm, pi);
4449         }
4450
4451         /**
4452          * Allocating new amd_iommu_pi_data, which will get
4453          * add to the per-vcpu ir_list.
4454          */
4455         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4456         if (!ir) {
4457                 ret = -ENOMEM;
4458                 goto out;
4459         }
4460         ir->data = pi->ir_data;
4461
4462         spin_lock_irqsave(&svm->ir_list_lock, flags);
4463         list_add(&ir->node, &svm->ir_list);
4464         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4465 out:
4466         return ret;
4467 }
4468
4469 /**
4470  * Note:
4471  * The HW cannot support posting multicast/broadcast
4472  * interrupts to a vCPU. So, we still use legacy interrupt
4473  * remapping for these kind of interrupts.
4474  *
4475  * For lowest-priority interrupts, we only support
4476  * those with single CPU as the destination, e.g. user
4477  * configures the interrupts via /proc/irq or uses
4478  * irqbalance to make the interrupts single-CPU.
4479  */
4480 static int
4481 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4482                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4483 {
4484         struct kvm_lapic_irq irq;
4485         struct kvm_vcpu *vcpu = NULL;
4486
4487         kvm_set_msi_irq(kvm, e, &irq);
4488
4489         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4490                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4491                          __func__, irq.vector);
4492                 return -1;
4493         }
4494
4495         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4496                  irq.vector);
4497         *svm = to_svm(vcpu);
4498         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4499         vcpu_info->vector = irq.vector;
4500
4501         return 0;
4502 }
4503
4504 /*
4505  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4506  *
4507  * @kvm: kvm
4508  * @host_irq: host irq of the interrupt
4509  * @guest_irq: gsi of the interrupt
4510  * @set: set or unset PI
4511  * returns 0 on success, < 0 on failure
4512  */
4513 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4514                               uint32_t guest_irq, bool set)
4515 {
4516         struct kvm_kernel_irq_routing_entry *e;
4517         struct kvm_irq_routing_table *irq_rt;
4518         int idx, ret = -EINVAL;
4519
4520         if (!kvm_arch_has_assigned_device(kvm) ||
4521             !irq_remapping_cap(IRQ_POSTING_CAP))
4522                 return 0;
4523
4524         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4525                  __func__, host_irq, guest_irq, set);
4526
4527         idx = srcu_read_lock(&kvm->irq_srcu);
4528         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4529         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4530
4531         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4532                 struct vcpu_data vcpu_info;
4533                 struct vcpu_svm *svm = NULL;
4534
4535                 if (e->type != KVM_IRQ_ROUTING_MSI)
4536                         continue;
4537
4538                 /**
4539                  * Here, we setup with legacy mode in the following cases:
4540                  * 1. When cannot target interrupt to a specific vcpu.
4541                  * 2. Unsetting posted interrupt.
4542                  * 3. APIC virtialization is disabled for the vcpu.
4543                  */
4544                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4545                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4546                         struct amd_iommu_pi_data pi;
4547
4548                         /* Try to enable guest_mode in IRTE */
4549                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4550                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4551                                                      svm->vcpu.vcpu_id);
4552                         pi.is_guest_mode = true;
4553                         pi.vcpu_data = &vcpu_info;
4554                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4555
4556                         /**
4557                          * Here, we successfully setting up vcpu affinity in
4558                          * IOMMU guest mode. Now, we need to store the posted
4559                          * interrupt information in a per-vcpu ir_list so that
4560                          * we can reference to them directly when we update vcpu
4561                          * scheduling information in IOMMU irte.
4562                          */
4563                         if (!ret && pi.is_guest_mode)
4564                                 svm_ir_list_add(svm, &pi);
4565                 } else {
4566                         /* Use legacy mode in IRTE */
4567                         struct amd_iommu_pi_data pi;
4568
4569                         /**
4570                          * Here, pi is used to:
4571                          * - Tell IOMMU to use legacy mode for this interrupt.
4572                          * - Retrieve ga_tag of prior interrupt remapping data.
4573                          */
4574                         pi.is_guest_mode = false;
4575                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4576
4577                         /**
4578                          * Check if the posted interrupt was previously
4579                          * setup with the guest_mode by checking if the ga_tag
4580                          * was cached. If so, we need to clean up the per-vcpu
4581                          * ir_list.
4582                          */
4583                         if (!ret && pi.prev_ga_tag) {
4584                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4585                                 struct kvm_vcpu *vcpu;
4586
4587                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4588                                 if (vcpu)
4589                                         svm_ir_list_del(to_svm(vcpu), &pi);
4590                         }
4591                 }
4592
4593                 if (!ret && svm) {
4594                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4595                                                  host_irq, e->gsi,
4596                                                  vcpu_info.vector,
4597                                                  vcpu_info.pi_desc_addr, set);
4598                 }
4599
4600                 if (ret < 0) {
4601                         pr_err("%s: failed to update PI IRTE\n", __func__);
4602                         goto out;
4603                 }
4604         }
4605
4606         ret = 0;
4607 out:
4608         srcu_read_unlock(&kvm->irq_srcu, idx);
4609         return ret;
4610 }
4611
4612 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4613 {
4614         struct vcpu_svm *svm = to_svm(vcpu);
4615         struct vmcb *vmcb = svm->vmcb;
4616         int ret;
4617         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4618               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4619         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4620
4621         return ret;
4622 }
4623
4624 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4625 {
4626         struct vcpu_svm *svm = to_svm(vcpu);
4627
4628         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4629 }
4630
4631 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4632 {
4633         struct vcpu_svm *svm = to_svm(vcpu);
4634
4635         if (masked) {
4636                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4637                 set_intercept(svm, INTERCEPT_IRET);
4638         } else {
4639                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4640                 clr_intercept(svm, INTERCEPT_IRET);
4641         }
4642 }
4643
4644 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4645 {
4646         struct vcpu_svm *svm = to_svm(vcpu);
4647         struct vmcb *vmcb = svm->vmcb;
4648         int ret;
4649
4650         if (!gif_set(svm) ||
4651              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4652                 return 0;
4653
4654         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4655
4656         if (is_guest_mode(vcpu))
4657                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4658
4659         return ret;
4660 }
4661
4662 static void enable_irq_window(struct kvm_vcpu *vcpu)
4663 {
4664         struct vcpu_svm *svm = to_svm(vcpu);
4665
4666         if (kvm_vcpu_apicv_active(vcpu))
4667                 return;
4668
4669         /*
4670          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4671          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4672          * get that intercept, this function will be called again though and
4673          * we'll get the vintr intercept.
4674          */
4675         if (gif_set(svm) && nested_svm_intr(svm)) {
4676                 svm_set_vintr(svm);
4677                 svm_inject_irq(svm, 0x0);
4678         }
4679 }
4680
4681 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4682 {
4683         struct vcpu_svm *svm = to_svm(vcpu);
4684
4685         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4686             == HF_NMI_MASK)
4687                 return; /* IRET will cause a vm exit */
4688
4689         /*
4690          * Something prevents NMI from been injected. Single step over possible
4691          * problem (IRET or exception injection or interrupt shadow)
4692          */
4693         svm->nmi_singlestep = true;
4694         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4695 }
4696
4697 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4698 {
4699         return 0;
4700 }
4701
4702 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4703 {
4704         struct vcpu_svm *svm = to_svm(vcpu);
4705
4706         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4707                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4708         else
4709                 svm->asid_generation--;
4710 }
4711
4712 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4713 {
4714 }
4715
4716 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4717 {
4718         struct vcpu_svm *svm = to_svm(vcpu);
4719
4720         if (svm_nested_virtualize_tpr(vcpu))
4721                 return;
4722
4723         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4724                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4725                 kvm_set_cr8(vcpu, cr8);
4726         }
4727 }
4728
4729 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4730 {
4731         struct vcpu_svm *svm = to_svm(vcpu);
4732         u64 cr8;
4733
4734         if (svm_nested_virtualize_tpr(vcpu) ||
4735             kvm_vcpu_apicv_active(vcpu))
4736                 return;
4737
4738         cr8 = kvm_get_cr8(vcpu);
4739         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4740         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4741 }
4742
4743 static void svm_complete_interrupts(struct vcpu_svm *svm)
4744 {
4745         u8 vector;
4746         int type;
4747         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4748         unsigned int3_injected = svm->int3_injected;
4749
4750         svm->int3_injected = 0;
4751
4752         /*
4753          * If we've made progress since setting HF_IRET_MASK, we've
4754          * executed an IRET and can allow NMI injection.
4755          */
4756         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4757             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4758                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4759                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4760         }
4761
4762         svm->vcpu.arch.nmi_injected = false;
4763         kvm_clear_exception_queue(&svm->vcpu);
4764         kvm_clear_interrupt_queue(&svm->vcpu);
4765
4766         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4767                 return;
4768
4769         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4770
4771         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4772         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4773
4774         switch (type) {
4775         case SVM_EXITINTINFO_TYPE_NMI:
4776                 svm->vcpu.arch.nmi_injected = true;
4777                 break;
4778         case SVM_EXITINTINFO_TYPE_EXEPT:
4779                 /*
4780                  * In case of software exceptions, do not reinject the vector,
4781                  * but re-execute the instruction instead. Rewind RIP first
4782                  * if we emulated INT3 before.
4783                  */
4784                 if (kvm_exception_is_soft(vector)) {
4785                         if (vector == BP_VECTOR && int3_injected &&
4786                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4787                                 kvm_rip_write(&svm->vcpu,
4788                                               kvm_rip_read(&svm->vcpu) -
4789                                               int3_injected);
4790                         break;
4791                 }
4792                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4793                         u32 err = svm->vmcb->control.exit_int_info_err;
4794                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4795
4796                 } else
4797                         kvm_requeue_exception(&svm->vcpu, vector);
4798                 break;
4799         case SVM_EXITINTINFO_TYPE_INTR:
4800                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4801                 break;
4802         default:
4803                 break;
4804         }
4805 }
4806
4807 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4808 {
4809         struct vcpu_svm *svm = to_svm(vcpu);
4810         struct vmcb_control_area *control = &svm->vmcb->control;
4811
4812         control->exit_int_info = control->event_inj;
4813         control->exit_int_info_err = control->event_inj_err;
4814         control->event_inj = 0;
4815         svm_complete_interrupts(svm);
4816 }
4817
4818 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4819 {
4820         struct vcpu_svm *svm = to_svm(vcpu);
4821
4822         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4823         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4824         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4825
4826         /*
4827          * A vmexit emulation is required before the vcpu can be executed
4828          * again.
4829          */
4830         if (unlikely(svm->nested.exit_required))
4831                 return;
4832
4833         pre_svm_run(svm);
4834
4835         sync_lapic_to_cr8(vcpu);
4836
4837         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4838
4839         clgi();
4840
4841         local_irq_enable();
4842
4843         asm volatile (
4844                 "push %%" _ASM_BP "; \n\t"
4845                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4846                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4847                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4848                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4849                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4850                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4851 #ifdef CONFIG_X86_64
4852                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4853                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4854                 "mov %c[r10](%[svm]), %%r10 \n\t"
4855                 "mov %c[r11](%[svm]), %%r11 \n\t"
4856                 "mov %c[r12](%[svm]), %%r12 \n\t"
4857                 "mov %c[r13](%[svm]), %%r13 \n\t"
4858                 "mov %c[r14](%[svm]), %%r14 \n\t"
4859                 "mov %c[r15](%[svm]), %%r15 \n\t"
4860 #endif
4861
4862                 /* Enter guest mode */
4863                 "push %%" _ASM_AX " \n\t"
4864                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4865                 __ex(SVM_VMLOAD) "\n\t"
4866                 __ex(SVM_VMRUN) "\n\t"
4867                 __ex(SVM_VMSAVE) "\n\t"
4868                 "pop %%" _ASM_AX " \n\t"
4869
4870                 /* Save guest registers, load host registers */
4871                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4872                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4873                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4874                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4875                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4876                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4877 #ifdef CONFIG_X86_64
4878                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4879                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4880                 "mov %%r10, %c[r10](%[svm]) \n\t"
4881                 "mov %%r11, %c[r11](%[svm]) \n\t"
4882                 "mov %%r12, %c[r12](%[svm]) \n\t"
4883                 "mov %%r13, %c[r13](%[svm]) \n\t"
4884                 "mov %%r14, %c[r14](%[svm]) \n\t"
4885                 "mov %%r15, %c[r15](%[svm]) \n\t"
4886 #endif
4887                 "pop %%" _ASM_BP
4888                 :
4889                 : [svm]"a"(svm),
4890                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4891                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4892                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4893                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4894                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4895                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4896                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4897 #ifdef CONFIG_X86_64
4898                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4899                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4900                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4901                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4902                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4903                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4904                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4905                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4906 #endif
4907                 : "cc", "memory"
4908 #ifdef CONFIG_X86_64
4909                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4910                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4911 #else
4912                 , "ebx", "ecx", "edx", "esi", "edi"
4913 #endif
4914                 );
4915
4916 #ifdef CONFIG_X86_64
4917         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4918 #else
4919         loadsegment(fs, svm->host.fs);
4920 #ifndef CONFIG_X86_32_LAZY_GS
4921         loadsegment(gs, svm->host.gs);
4922 #endif
4923 #endif
4924
4925         reload_tss(vcpu);
4926
4927         local_irq_disable();
4928
4929         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4930         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4931         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4932         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4933
4934         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4935                 kvm_before_handle_nmi(&svm->vcpu);
4936
4937         stgi();
4938
4939         /* Any pending NMI will happen here */
4940
4941         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4942                 kvm_after_handle_nmi(&svm->vcpu);
4943
4944         sync_cr8_to_lapic(vcpu);
4945
4946         svm->next_rip = 0;
4947
4948         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4949
4950         /* if exit due to PF check for async PF */
4951         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4952                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4953
4954         if (npt_enabled) {
4955                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4956                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4957         }
4958
4959         /*
4960          * We need to handle MC intercepts here before the vcpu has a chance to
4961          * change the physical cpu
4962          */
4963         if (unlikely(svm->vmcb->control.exit_code ==
4964                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4965                 svm_handle_mce(svm);
4966
4967         mark_all_clean(svm->vmcb);
4968 }
4969
4970 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4971 {
4972         struct vcpu_svm *svm = to_svm(vcpu);
4973
4974         svm->vmcb->save.cr3 = root;
4975         mark_dirty(svm->vmcb, VMCB_CR);
4976         svm_flush_tlb(vcpu);
4977 }
4978
4979 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4980 {
4981         struct vcpu_svm *svm = to_svm(vcpu);
4982
4983         svm->vmcb->control.nested_cr3 = root;
4984         mark_dirty(svm->vmcb, VMCB_NPT);
4985
4986         /* Also sync guest cr3 here in case we live migrate */
4987         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4988         mark_dirty(svm->vmcb, VMCB_CR);
4989
4990         svm_flush_tlb(vcpu);
4991 }
4992
4993 static int is_disabled(void)
4994 {
4995         u64 vm_cr;
4996
4997         rdmsrl(MSR_VM_CR, vm_cr);
4998         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4999                 return 1;
5000
5001         return 0;
5002 }
5003
5004 static void
5005 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5006 {
5007         /*
5008          * Patch in the VMMCALL instruction:
5009          */
5010         hypercall[0] = 0x0f;
5011         hypercall[1] = 0x01;
5012         hypercall[2] = 0xd9;
5013 }
5014
5015 static void svm_check_processor_compat(void *rtn)
5016 {
5017         *(int *)rtn = 0;
5018 }
5019
5020 static bool svm_cpu_has_accelerated_tpr(void)
5021 {
5022         return false;
5023 }
5024
5025 static bool svm_has_high_real_mode_segbase(void)
5026 {
5027         return true;
5028 }
5029
5030 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5031 {
5032         return 0;
5033 }
5034
5035 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5036 {
5037         struct vcpu_svm *svm = to_svm(vcpu);
5038         struct kvm_cpuid_entry2 *entry;
5039
5040         /* Update nrips enabled cache */
5041         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5042
5043         if (!kvm_vcpu_apicv_active(vcpu))
5044                 return;
5045
5046         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5047         if (entry)
5048                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5049 }
5050
5051 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5052 {
5053         switch (func) {
5054         case 0x1:
5055                 if (avic)
5056                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5057                 break;
5058         case 0x80000001:
5059                 if (nested)
5060                         entry->ecx |= (1 << 2); /* Set SVM bit */
5061                 break;
5062         case 0x8000000A:
5063                 entry->eax = 1; /* SVM revision 1 */
5064                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5065                                    ASID emulation to nested SVM */
5066                 entry->ecx = 0; /* Reserved */
5067                 entry->edx = 0; /* Per default do not support any
5068                                    additional features */
5069
5070                 /* Support next_rip if host supports it */
5071                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5072                         entry->edx |= SVM_FEATURE_NRIP;
5073
5074                 /* Support NPT for the guest if enabled */
5075                 if (npt_enabled)
5076                         entry->edx |= SVM_FEATURE_NPT;
5077
5078                 break;
5079         }
5080 }
5081
5082 static int svm_get_lpage_level(void)
5083 {
5084         return PT_PDPE_LEVEL;
5085 }
5086
5087 static bool svm_rdtscp_supported(void)
5088 {
5089         return boot_cpu_has(X86_FEATURE_RDTSCP);
5090 }
5091
5092 static bool svm_invpcid_supported(void)
5093 {
5094         return false;
5095 }
5096
5097 static bool svm_mpx_supported(void)
5098 {
5099         return false;
5100 }
5101
5102 static bool svm_xsaves_supported(void)
5103 {
5104         return false;
5105 }
5106
5107 static bool svm_has_wbinvd_exit(void)
5108 {
5109         return true;
5110 }
5111
5112 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
5113 {
5114         struct vcpu_svm *svm = to_svm(vcpu);
5115
5116         set_exception_intercept(svm, NM_VECTOR);
5117         update_cr0_intercept(svm);
5118 }
5119
5120 #define PRE_EX(exit)  { .exit_code = (exit), \
5121                         .stage = X86_ICPT_PRE_EXCEPT, }
5122 #define POST_EX(exit) { .exit_code = (exit), \
5123                         .stage = X86_ICPT_POST_EXCEPT, }
5124 #define POST_MEM(exit) { .exit_code = (exit), \
5125                         .stage = X86_ICPT_POST_MEMACCESS, }
5126
5127 static const struct __x86_intercept {
5128         u32 exit_code;
5129         enum x86_intercept_stage stage;
5130 } x86_intercept_map[] = {
5131         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5132         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5133         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5134         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5135         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5136         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5137         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5138         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5139         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5140         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5141         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5142         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5143         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5144         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5145         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5146         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5147         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5148         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5149         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5150         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5151         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5152         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5153         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5154         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5155         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5156         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5157         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5158         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5159         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5160         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5161         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5162         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5163         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5164         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5165         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5166         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5167         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5168         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5169         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5170         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5171         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5172         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5173         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5174         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5175         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5176         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5177 };
5178
5179 #undef PRE_EX
5180 #undef POST_EX
5181 #undef POST_MEM
5182
5183 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5184                                struct x86_instruction_info *info,
5185                                enum x86_intercept_stage stage)
5186 {
5187         struct vcpu_svm *svm = to_svm(vcpu);
5188         int vmexit, ret = X86EMUL_CONTINUE;
5189         struct __x86_intercept icpt_info;
5190         struct vmcb *vmcb = svm->vmcb;
5191
5192         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5193                 goto out;
5194
5195         icpt_info = x86_intercept_map[info->intercept];
5196
5197         if (stage != icpt_info.stage)
5198                 goto out;
5199
5200         switch (icpt_info.exit_code) {
5201         case SVM_EXIT_READ_CR0:
5202                 if (info->intercept == x86_intercept_cr_read)
5203                         icpt_info.exit_code += info->modrm_reg;
5204                 break;
5205         case SVM_EXIT_WRITE_CR0: {
5206                 unsigned long cr0, val;
5207                 u64 intercept;
5208
5209                 if (info->intercept == x86_intercept_cr_write)
5210                         icpt_info.exit_code += info->modrm_reg;
5211
5212                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5213                     info->intercept == x86_intercept_clts)
5214                         break;
5215
5216                 intercept = svm->nested.intercept;
5217
5218                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5219                         break;
5220
5221                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5222                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5223
5224                 if (info->intercept == x86_intercept_lmsw) {
5225                         cr0 &= 0xfUL;
5226                         val &= 0xfUL;
5227                         /* lmsw can't clear PE - catch this here */
5228                         if (cr0 & X86_CR0_PE)
5229                                 val |= X86_CR0_PE;
5230                 }
5231
5232                 if (cr0 ^ val)
5233                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5234
5235                 break;
5236         }
5237         case SVM_EXIT_READ_DR0:
5238         case SVM_EXIT_WRITE_DR0:
5239                 icpt_info.exit_code += info->modrm_reg;
5240                 break;
5241         case SVM_EXIT_MSR:
5242                 if (info->intercept == x86_intercept_wrmsr)
5243                         vmcb->control.exit_info_1 = 1;
5244                 else
5245                         vmcb->control.exit_info_1 = 0;
5246                 break;
5247         case SVM_EXIT_PAUSE:
5248                 /*
5249                  * We get this for NOP only, but pause
5250                  * is rep not, check this here
5251                  */
5252                 if (info->rep_prefix != REPE_PREFIX)
5253                         goto out;
5254         case SVM_EXIT_IOIO: {
5255                 u64 exit_info;
5256                 u32 bytes;
5257
5258                 if (info->intercept == x86_intercept_in ||
5259                     info->intercept == x86_intercept_ins) {
5260                         exit_info = ((info->src_val & 0xffff) << 16) |
5261                                 SVM_IOIO_TYPE_MASK;
5262                         bytes = info->dst_bytes;
5263                 } else {
5264                         exit_info = (info->dst_val & 0xffff) << 16;
5265                         bytes = info->src_bytes;
5266                 }
5267
5268                 if (info->intercept == x86_intercept_outs ||
5269                     info->intercept == x86_intercept_ins)
5270                         exit_info |= SVM_IOIO_STR_MASK;
5271
5272                 if (info->rep_prefix)
5273                         exit_info |= SVM_IOIO_REP_MASK;
5274
5275                 bytes = min(bytes, 4u);
5276
5277                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5278
5279                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5280
5281                 vmcb->control.exit_info_1 = exit_info;
5282                 vmcb->control.exit_info_2 = info->next_rip;
5283
5284                 break;
5285         }
5286         default:
5287                 break;
5288         }
5289
5290         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5291         if (static_cpu_has(X86_FEATURE_NRIPS))
5292                 vmcb->control.next_rip  = info->next_rip;
5293         vmcb->control.exit_code = icpt_info.exit_code;
5294         vmexit = nested_svm_exit_handled(svm);
5295
5296         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5297                                            : X86EMUL_CONTINUE;
5298
5299 out:
5300         return ret;
5301 }
5302
5303 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5304 {
5305         local_irq_enable();
5306         /*
5307          * We must have an instruction with interrupts enabled, so
5308          * the timer interrupt isn't delayed by the interrupt shadow.
5309          */
5310         asm("nop");
5311         local_irq_disable();
5312 }
5313
5314 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5315 {
5316 }
5317
5318 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5319 {
5320         if (avic_handle_apic_id_update(vcpu) != 0)
5321                 return;
5322         if (avic_handle_dfr_update(vcpu) != 0)
5323                 return;
5324         avic_handle_ldr_update(vcpu);
5325 }
5326
5327 static struct kvm_x86_ops svm_x86_ops = {
5328         .cpu_has_kvm_support = has_svm,
5329         .disabled_by_bios = is_disabled,
5330         .hardware_setup = svm_hardware_setup,
5331         .hardware_unsetup = svm_hardware_unsetup,
5332         .check_processor_compatibility = svm_check_processor_compat,
5333         .hardware_enable = svm_hardware_enable,
5334         .hardware_disable = svm_hardware_disable,
5335         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5336         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5337
5338         .vcpu_create = svm_create_vcpu,
5339         .vcpu_free = svm_free_vcpu,
5340         .vcpu_reset = svm_vcpu_reset,
5341
5342         .vm_init = avic_vm_init,
5343         .vm_destroy = avic_vm_destroy,
5344
5345         .prepare_guest_switch = svm_prepare_guest_switch,
5346         .vcpu_load = svm_vcpu_load,
5347         .vcpu_put = svm_vcpu_put,
5348         .vcpu_blocking = svm_vcpu_blocking,
5349         .vcpu_unblocking = svm_vcpu_unblocking,
5350
5351         .update_bp_intercept = update_bp_intercept,
5352         .get_msr = svm_get_msr,
5353         .set_msr = svm_set_msr,
5354         .get_segment_base = svm_get_segment_base,
5355         .get_segment = svm_get_segment,
5356         .set_segment = svm_set_segment,
5357         .get_cpl = svm_get_cpl,
5358         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5359         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5360         .decache_cr3 = svm_decache_cr3,
5361         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5362         .set_cr0 = svm_set_cr0,
5363         .set_cr3 = svm_set_cr3,
5364         .set_cr4 = svm_set_cr4,
5365         .set_efer = svm_set_efer,
5366         .get_idt = svm_get_idt,
5367         .set_idt = svm_set_idt,
5368         .get_gdt = svm_get_gdt,
5369         .set_gdt = svm_set_gdt,
5370         .get_dr6 = svm_get_dr6,
5371         .set_dr6 = svm_set_dr6,
5372         .set_dr7 = svm_set_dr7,
5373         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5374         .cache_reg = svm_cache_reg,
5375         .get_rflags = svm_get_rflags,
5376         .set_rflags = svm_set_rflags,
5377
5378         .get_pkru = svm_get_pkru,
5379
5380         .fpu_activate = svm_fpu_activate,
5381         .fpu_deactivate = svm_fpu_deactivate,
5382
5383         .tlb_flush = svm_flush_tlb,
5384
5385         .run = svm_vcpu_run,
5386         .handle_exit = handle_exit,
5387         .skip_emulated_instruction = skip_emulated_instruction,
5388         .set_interrupt_shadow = svm_set_interrupt_shadow,
5389         .get_interrupt_shadow = svm_get_interrupt_shadow,
5390         .patch_hypercall = svm_patch_hypercall,
5391         .set_irq = svm_set_irq,
5392         .set_nmi = svm_inject_nmi,
5393         .queue_exception = svm_queue_exception,
5394         .cancel_injection = svm_cancel_injection,
5395         .interrupt_allowed = svm_interrupt_allowed,
5396         .nmi_allowed = svm_nmi_allowed,
5397         .get_nmi_mask = svm_get_nmi_mask,
5398         .set_nmi_mask = svm_set_nmi_mask,
5399         .enable_nmi_window = enable_nmi_window,
5400         .enable_irq_window = enable_irq_window,
5401         .update_cr8_intercept = update_cr8_intercept,
5402         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5403         .get_enable_apicv = svm_get_enable_apicv,
5404         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5405         .load_eoi_exitmap = svm_load_eoi_exitmap,
5406         .sync_pir_to_irr = svm_sync_pir_to_irr,
5407         .hwapic_irr_update = svm_hwapic_irr_update,
5408         .hwapic_isr_update = svm_hwapic_isr_update,
5409         .apicv_post_state_restore = avic_post_state_restore,
5410
5411         .set_tss_addr = svm_set_tss_addr,
5412         .get_tdp_level = get_npt_level,
5413         .get_mt_mask = svm_get_mt_mask,
5414
5415         .get_exit_info = svm_get_exit_info,
5416
5417         .get_lpage_level = svm_get_lpage_level,
5418
5419         .cpuid_update = svm_cpuid_update,
5420
5421         .rdtscp_supported = svm_rdtscp_supported,
5422         .invpcid_supported = svm_invpcid_supported,
5423         .mpx_supported = svm_mpx_supported,
5424         .xsaves_supported = svm_xsaves_supported,
5425
5426         .set_supported_cpuid = svm_set_supported_cpuid,
5427
5428         .has_wbinvd_exit = svm_has_wbinvd_exit,
5429
5430         .read_tsc_offset = svm_read_tsc_offset,
5431         .write_tsc_offset = svm_write_tsc_offset,
5432         .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest,
5433         .read_l1_tsc = svm_read_l1_tsc,
5434
5435         .set_tdp_cr3 = set_tdp_cr3,
5436
5437         .check_intercept = svm_check_intercept,
5438         .handle_external_intr = svm_handle_external_intr,
5439
5440         .sched_in = svm_sched_in,
5441
5442         .pmu_ops = &amd_pmu_ops,
5443         .deliver_posted_interrupt = svm_deliver_avic_intr,
5444         .update_pi_irte = svm_update_pi_irte,
5445 };
5446
5447 static int __init svm_init(void)
5448 {
5449         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5450                         __alignof__(struct vcpu_svm), THIS_MODULE);
5451 }
5452
5453 static void __exit svm_exit(void)
5454 {
5455         kvm_exit();
5456 }
5457
5458 module_init(svm_init)
5459 module_exit(svm_exit)