arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39
  40 #include <asm/apic.h>
  41 #include <asm/perf_event.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/desc.h>
  44 #include <asm/debugreg.h>
  45 #include <asm/kvm_para.h>
  46 #include <asm/irq_remapping.h>
  47
  48 #include <asm/virtext.h>
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id svm_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  61
  62 #define IOPM_ALLOC_ORDER 2
  63 #define MSRPM_ALLOC_ORDER 1
  64
  65 #define SEG_TYPE_LDT 2
  66 #define SEG_TYPE_BUSY_TSS16 3
  67
  68 #define SVM_FEATURE_NPT            (1 <<  0)
  69 #define SVM_FEATURE_LBRV           (1 <<  1)
  70 #define SVM_FEATURE_SVML           (1 <<  2)
  71 #define SVM_FEATURE_NRIP           (1 <<  3)
  72 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  73 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  74 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  75 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  76 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  77
  78 #define SVM_AVIC_DOORBELL       0xc001011b
  79
  80 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  81 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  82 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  83
  84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  85
  86 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  87 #define TSC_RATIO_MIN           0x0000000000000001ULL
  88 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  89
  90 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  91
  92 /*
  93  * 0xff is broadcast, so the max index allowed for physical APIC ID
  94  * table is 0xfe.  APIC IDs above 0xff are reserved.
  95  */
  96 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
  97
  98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
  99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 101
 102 /* AVIC GATAG is encoded using VM and VCPU IDs */
 103 #define AVIC_VCPU_ID_BITS               8
 104 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 105
 106 #define AVIC_VM_ID_BITS                 24
 107 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 108 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 109
 110 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 111                                                 (y & AVIC_VCPU_ID_MASK))
 112 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 113 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 114
 115 static bool erratum_383_found __read_mostly;
 116
 117 static const u32 host_save_user_msrs[] = {
 118 #ifdef CONFIG_X86_64
 119         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 120         MSR_FS_BASE,
 121 #endif
 122         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 123         MSR_TSC_AUX,
 124 };
 125
 126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 127
 128 struct kvm_vcpu;
 129
 130 struct nested_state {
 131         struct vmcb *hsave;
 132         u64 hsave_msr;
 133         u64 vm_cr_msr;
 134         u64 vmcb;
 135
 136         /* These are the merged vectors */
 137         u32 *msrpm;
 138
 139         /* gpa pointers to the real vectors */
 140         u64 vmcb_msrpm;
 141         u64 vmcb_iopm;
 142
 143         /* A VMEXIT is required but not yet emulated */
 144         bool exit_required;
 145
 146         /* cache for intercepts of the guest */
 147         u32 intercept_cr;
 148         u32 intercept_dr;
 149         u32 intercept_exceptions;
 150         u64 intercept;
 151
 152         /* Nested Paging related state */
 153         u64 nested_cr3;
 154 };
 155
 156 #define MSRPM_OFFSETS   16
 157 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 158
 159 /*
 160  * Set osvw_len to higher value when updated Revision Guides
 161  * are published and we know what the new status bits are
 162  */
 163 static uint64_t osvw_len = 4, osvw_status;
 164
 165 struct vcpu_svm {
 166         struct kvm_vcpu vcpu;
 167         struct vmcb *vmcb;
 168         unsigned long vmcb_pa;
 169         struct svm_cpu_data *svm_data;
 170         uint64_t asid_generation;
 171         uint64_t sysenter_esp;
 172         uint64_t sysenter_eip;
 173         uint64_t tsc_aux;
 174
 175         u64 next_rip;
 176
 177         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 178         struct {
 179                 u16 fs;
 180                 u16 gs;
 181                 u16 ldt;
 182                 u64 gs_base;
 183         } host;
 184
 185         u32 *msrpm;
 186
 187         ulong nmi_iret_rip;
 188
 189         struct nested_state nested;
 190
 191         bool nmi_singlestep;
 192
 193         unsigned int3_injected;
 194         unsigned long int3_rip;
 195         u32 apf_reason;
 196
 197         /* cached guest cpuid flags for faster access */
 198         bool nrips_enabled      : 1;
 199
 200         u32 ldr_reg;
 201         struct page *avic_backing_page;
 202         u64 *avic_physical_id_cache;
 203         bool avic_is_running;
 204
 205         /*
 206          * Per-vcpu list of struct amd_svm_iommu_ir:
 207          * This is used mainly to store interrupt remapping information used
 208          * when update the vcpu affinity. This avoids the need to scan for
 209          * IRTE and try to match ga_tag in the IOMMU driver.
 210          */
 211         struct list_head ir_list;
 212         spinlock_t ir_list_lock;
 213 };
 214
 215 /*
 216  * This is a wrapper of struct amd_iommu_ir_data.
 217  */
 218 struct amd_svm_iommu_ir {
 219         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 220         void *data;             /* Storing pointer to struct amd_ir_data */
 221 };
 222
 223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 225
 226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 230
 231 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 232 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 233
 234 #define MSR_INVALID                     0xffffffffU
 235
 236 static const struct svm_direct_access_msrs {
 237         u32 index;   /* Index of the MSR */
 238         bool always; /* True if intercept is always on */
 239 } direct_access_msrs[] = {
 240         { .index = MSR_STAR,                            .always = true  },
 241         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 242 #ifdef CONFIG_X86_64
 243         { .index = MSR_GS_BASE,                         .always = true  },
 244         { .index = MSR_FS_BASE,                         .always = true  },
 245         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 246         { .index = MSR_LSTAR,                           .always = true  },
 247         { .index = MSR_CSTAR,                           .always = true  },
 248         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 249 #endif
 250         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 251         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 252         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 253         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 254         { .index = MSR_INVALID,                         .always = false },
 255 };
 256
 257 /* enable NPT for AMD64 and X86 with PAE */
 258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 259 static bool npt_enabled = true;
 260 #else
 261 static bool npt_enabled;
 262 #endif
 263
 264 /* allow nested paging (virtualized MMU) for all guests */
 265 static int npt = true;
 266 module_param(npt, int, S_IRUGO);
 267
 268 /* allow nested virtualization in KVM/SVM */
 269 static int nested = true;
 270 module_param(nested, int, S_IRUGO);
 271
 272 /* enable / disable AVIC */
 273 static int avic;
 274 #ifdef CONFIG_X86_LOCAL_APIC
 275 module_param(avic, int, S_IRUGO);
 276 #endif
 277
 278 /* AVIC VM ID bit masks and lock */
 279 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
 280 static DEFINE_SPINLOCK(avic_vm_id_lock);
 281
 282 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 283 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 284 static void svm_complete_interrupts(struct vcpu_svm *svm);
 285
 286 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 287 static int nested_svm_intercept(struct vcpu_svm *svm);
 288 static int nested_svm_vmexit(struct vcpu_svm *svm);
 289 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 290                                       bool has_error_code, u32 error_code);
 291
 292 enum {
 293         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 294                             pause filter count */
 295         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 296         VMCB_ASID,       /* ASID */
 297         VMCB_INTR,       /* int_ctl, int_vector */
 298         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 299         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 300         VMCB_DR,         /* DR6, DR7 */
 301         VMCB_DT,         /* GDT, IDT */
 302         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 303         VMCB_CR2,        /* CR2 only */
 304         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 305         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 306                           * AVIC PHYSICAL_TABLE pointer,
 307                           * AVIC LOGICAL_TABLE pointer
 308                           */
 309         VMCB_DIRTY_MAX,
 310 };
 311
 312 /* TPR and CR2 are always written before VMRUN */
 313 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 314
 315 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 316
 317 static inline void mark_all_dirty(struct vmcb *vmcb)
 318 {
 319         vmcb->control.clean = 0;
 320 }
 321
 322 static inline void mark_all_clean(struct vmcb *vmcb)
 323 {
 324         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 325                                & ~VMCB_ALWAYS_DIRTY_MASK;
 326 }
 327
 328 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 329 {
 330         vmcb->control.clean &= ~(1 << bit);
 331 }
 332
 333 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 334 {
 335         return container_of(vcpu, struct vcpu_svm, vcpu);
 336 }
 337
 338 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 339 {
 340         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 341         mark_dirty(svm->vmcb, VMCB_AVIC);
 342 }
 343
 344 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347         u64 *entry = svm->avic_physical_id_cache;
 348
 349         if (!entry)
 350                 return false;
 351
 352         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 353 }
 354
 355 static void recalc_intercepts(struct vcpu_svm *svm)
 356 {
 357         struct vmcb_control_area *c, *h;
 358         struct nested_state *g;
 359
 360         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 361
 362         if (!is_guest_mode(&svm->vcpu))
 363                 return;
 364
 365         c = &svm->vmcb->control;
 366         h = &svm->nested.hsave->control;
 367         g = &svm->nested;
 368
 369         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 370         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 371         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 372         c->intercept = h->intercept | g->intercept;
 373 }
 374
 375 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 376 {
 377         if (is_guest_mode(&svm->vcpu))
 378                 return svm->nested.hsave;
 379         else
 380                 return svm->vmcb;
 381 }
 382
 383 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 384 {
 385         struct vmcb *vmcb = get_host_vmcb(svm);
 386
 387         vmcb->control.intercept_cr |= (1U << bit);
 388
 389         recalc_intercepts(svm);
 390 }
 391
 392 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 393 {
 394         struct vmcb *vmcb = get_host_vmcb(svm);
 395
 396         vmcb->control.intercept_cr &= ~(1U << bit);
 397
 398         recalc_intercepts(svm);
 399 }
 400
 401 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 402 {
 403         struct vmcb *vmcb = get_host_vmcb(svm);
 404
 405         return vmcb->control.intercept_cr & (1U << bit);
 406 }
 407
 408 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 409 {
 410         struct vmcb *vmcb = get_host_vmcb(svm);
 411
 412         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 413                 | (1 << INTERCEPT_DR1_READ)
 414                 | (1 << INTERCEPT_DR2_READ)
 415                 | (1 << INTERCEPT_DR3_READ)
 416                 | (1 << INTERCEPT_DR4_READ)
 417                 | (1 << INTERCEPT_DR5_READ)
 418                 | (1 << INTERCEPT_DR6_READ)
 419                 | (1 << INTERCEPT_DR7_READ)
 420                 | (1 << INTERCEPT_DR0_WRITE)
 421                 | (1 << INTERCEPT_DR1_WRITE)
 422                 | (1 << INTERCEPT_DR2_WRITE)
 423                 | (1 << INTERCEPT_DR3_WRITE)
 424                 | (1 << INTERCEPT_DR4_WRITE)
 425                 | (1 << INTERCEPT_DR5_WRITE)
 426                 | (1 << INTERCEPT_DR6_WRITE)
 427                 | (1 << INTERCEPT_DR7_WRITE);
 428
 429         recalc_intercepts(svm);
 430 }
 431
 432 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 433 {
 434         struct vmcb *vmcb = get_host_vmcb(svm);
 435
 436         vmcb->control.intercept_dr = 0;
 437
 438         recalc_intercepts(svm);
 439 }
 440
 441 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 442 {
 443         struct vmcb *vmcb = get_host_vmcb(svm);
 444
 445         vmcb->control.intercept_exceptions |= (1U << bit);
 446
 447         recalc_intercepts(svm);
 448 }
 449
 450 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 451 {
 452         struct vmcb *vmcb = get_host_vmcb(svm);
 453
 454         vmcb->control.intercept_exceptions &= ~(1U << bit);
 455
 456         recalc_intercepts(svm);
 457 }
 458
 459 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 460 {
 461         struct vmcb *vmcb = get_host_vmcb(svm);
 462
 463         vmcb->control.intercept |= (1ULL << bit);
 464
 465         recalc_intercepts(svm);
 466 }
 467
 468 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 469 {
 470         struct vmcb *vmcb = get_host_vmcb(svm);
 471
 472         vmcb->control.intercept &= ~(1ULL << bit);
 473
 474         recalc_intercepts(svm);
 475 }
 476
 477 static inline void enable_gif(struct vcpu_svm *svm)
 478 {
 479         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 480 }
 481
 482 static inline void disable_gif(struct vcpu_svm *svm)
 483 {
 484         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 485 }
 486
 487 static inline bool gif_set(struct vcpu_svm *svm)
 488 {
 489         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 490 }
 491
 492 static unsigned long iopm_base;
 493
 494 struct kvm_ldttss_desc {
 495         u16 limit0;
 496         u16 base0;
 497         unsigned base1:8, type:5, dpl:2, p:1;
 498         unsigned limit1:4, zero0:3, g:1, base2:8;
 499         u32 base3;
 500         u32 zero1;
 501 } __attribute__((packed));
 502
 503 struct svm_cpu_data {
 504         int cpu;
 505
 506         u64 asid_generation;
 507         u32 max_asid;
 508         u32 next_asid;
 509         struct kvm_ldttss_desc *tss_desc;
 510
 511         struct page *save_area;
 512 };
 513
 514 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 515
 516 struct svm_init_data {
 517         int cpu;
 518         int r;
 519 };
 520
 521 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 522
 523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 524 #define MSRS_RANGE_SIZE 2048
 525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 526
 527 static u32 svm_msrpm_offset(u32 msr)
 528 {
 529         u32 offset;
 530         int i;
 531
 532         for (i = 0; i < NUM_MSR_MAPS; i++) {
 533                 if (msr < msrpm_ranges[i] ||
 534                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 535                         continue;
 536
 537                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 538                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 539
 540                 /* Now we have the u8 offset - but need the u32 offset */
 541                 return offset / 4;
 542         }
 543
 544         /* MSR not in any range */
 545         return MSR_INVALID;
 546 }
 547
 548 #define MAX_INST_SIZE 15
 549
 550 static inline void clgi(void)
 551 {
 552         asm volatile (__ex(SVM_CLGI));
 553 }
 554
 555 static inline void stgi(void)
 556 {
 557         asm volatile (__ex(SVM_STGI));
 558 }
 559
 560 static inline void invlpga(unsigned long addr, u32 asid)
 561 {
 562         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 563 }
 564
 565 static int get_npt_level(void)
 566 {
 567 #ifdef CONFIG_X86_64
 568         return PT64_ROOT_LEVEL;
 569 #else
 570         return PT32E_ROOT_LEVEL;
 571 #endif
 572 }
 573
 574 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 575 {
 576         vcpu->arch.efer = efer;
 577         if (!npt_enabled && !(efer & EFER_LMA))
 578                 efer &= ~EFER_LME;
 579
 580         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 581         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 582 }
 583
 584 static int is_external_interrupt(u32 info)
 585 {
 586         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 587         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 588 }
 589
 590 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 591 {
 592         struct vcpu_svm *svm = to_svm(vcpu);
 593         u32 ret = 0;
 594
 595         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 596                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 597         return ret;
 598 }
 599
 600 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         if (mask == 0)
 605                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 606         else
 607                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 608
 609 }
 610
 611 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         if (svm->vmcb->control.next_rip != 0) {
 616                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 617                 svm->next_rip = svm->vmcb->control.next_rip;
 618         }
 619
 620         if (!svm->next_rip) {
 621                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 622                                 EMULATE_DONE)
 623                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 624                 return;
 625         }
 626         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 627                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 628                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 629
 630         kvm_rip_write(vcpu, svm->next_rip);
 631         svm_set_interrupt_shadow(vcpu, 0);
 632 }
 633
 634 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 635                                 bool has_error_code, u32 error_code,
 636                                 bool reinject)
 637 {
 638         struct vcpu_svm *svm = to_svm(vcpu);
 639
 640         /*
 641          * If we are within a nested VM we'd better #VMEXIT and let the guest
 642          * handle the exception
 643          */
 644         if (!reinject &&
 645             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 646                 return;
 647
 648         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 649                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 650
 651                 /*
 652                  * For guest debugging where we have to reinject #BP if some
 653                  * INT3 is guest-owned:
 654                  * Emulate nRIP by moving RIP forward. Will fail if injection
 655                  * raises a fault that is not intercepted. Still better than
 656                  * failing in all cases.
 657                  */
 658                 skip_emulated_instruction(&svm->vcpu);
 659                 rip = kvm_rip_read(&svm->vcpu);
 660                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 661                 svm->int3_injected = rip - old_rip;
 662         }
 663
 664         svm->vmcb->control.event_inj = nr
 665                 | SVM_EVTINJ_VALID
 666                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 667                 | SVM_EVTINJ_TYPE_EXEPT;
 668         svm->vmcb->control.event_inj_err = error_code;
 669 }
 670
 671 static void svm_init_erratum_383(void)
 672 {
 673         u32 low, high;
 674         int err;
 675         u64 val;
 676
 677         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 678                 return;
 679
 680         /* Use _safe variants to not break nested virtualization */
 681         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 682         if (err)
 683                 return;
 684
 685         val |= (1ULL << 47);
 686
 687         low  = lower_32_bits(val);
 688         high = upper_32_bits(val);
 689
 690         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 691
 692         erratum_383_found = true;
 693 }
 694
 695 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 696 {
 697         /*
 698          * Guests should see errata 400 and 415 as fixed (assuming that
 699          * HLT and IO instructions are intercepted).
 700          */
 701         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 702         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 703
 704         /*
 705          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 706          * all osvw.status bits inside that length, including bit 0 (which is
 707          * reserved for erratum 298), are valid. However, if host processor's
 708          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 709          * be conservative here and therefore we tell the guest that erratum 298
 710          * is present (because we really don't know).
 711          */
 712         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 713                 vcpu->arch.osvw.status |= 1;
 714 }
 715
 716 static int has_svm(void)
 717 {
 718         const char *msg;
 719
 720         if (!cpu_has_svm(&msg)) {
 721                 printk(KERN_INFO "has_svm: %s\n", msg);
 722                 return 0;
 723         }
 724
 725         return 1;
 726 }
 727
 728 static void svm_hardware_disable(void)
 729 {
 730         /* Make sure we clean up behind us */
 731         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 732                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 733
 734         cpu_svm_disable();
 735
 736         amd_pmu_disable_virt();
 737 }
 738
 739 static int svm_hardware_enable(void)
 740 {
 741
 742         struct svm_cpu_data *sd;
 743         uint64_t efer;
 744         struct desc_ptr gdt_descr;
 745         struct desc_struct *gdt;
 746         int me = raw_smp_processor_id();
 747
 748         rdmsrl(MSR_EFER, efer);
 749         if (efer & EFER_SVME)
 750                 return -EBUSY;
 751
 752         if (!has_svm()) {
 753                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 754                 return -EINVAL;
 755         }
 756         sd = per_cpu(svm_data, me);
 757         if (!sd) {
 758                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 759                 return -EINVAL;
 760         }
 761
 762         sd->asid_generation = 1;
 763         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 764         sd->next_asid = sd->max_asid + 1;
 765
 766         native_store_gdt(&gdt_descr);
 767         gdt = (struct desc_struct *)gdt_descr.address;
 768         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 769
 770         wrmsrl(MSR_EFER, efer | EFER_SVME);
 771
 772         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 773
 774         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 775                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 776                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 777         }
 778
 779
 780         /*
 781          * Get OSVW bits.
 782          *
 783          * Note that it is possible to have a system with mixed processor
 784          * revisions and therefore different OSVW bits. If bits are not the same
 785          * on different processors then choose the worst case (i.e. if erratum
 786          * is present on one processor and not on another then assume that the
 787          * erratum is present everywhere).
 788          */
 789         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 790                 uint64_t len, status = 0;
 791                 int err;
 792
 793                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 794                 if (!err)
 795                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 796                                                       &err);
 797
 798                 if (err)
 799                         osvw_status = osvw_len = 0;
 800                 else {
 801                         if (len < osvw_len)
 802                                 osvw_len = len;
 803                         osvw_status |= status;
 804                         osvw_status &= (1ULL << osvw_len) - 1;
 805                 }
 806         } else
 807                 osvw_status = osvw_len = 0;
 808
 809         svm_init_erratum_383();
 810
 811         amd_pmu_enable_virt();
 812
 813         return 0;
 814 }
 815
 816 static void svm_cpu_uninit(int cpu)
 817 {
 818         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 819
 820         if (!sd)
 821                 return;
 822
 823         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 824         __free_page(sd->save_area);
 825         kfree(sd);
 826 }
 827
 828 static int svm_cpu_init(int cpu)
 829 {
 830         struct svm_cpu_data *sd;
 831         int r;
 832
 833         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 834         if (!sd)
 835                 return -ENOMEM;
 836         sd->cpu = cpu;
 837         sd->save_area = alloc_page(GFP_KERNEL);
 838         r = -ENOMEM;
 839         if (!sd->save_area)
 840                 goto err_1;
 841
 842         per_cpu(svm_data, cpu) = sd;
 843
 844         return 0;
 845
 846 err_1:
 847         kfree(sd);
 848         return r;
 849
 850 }
 851
 852 static bool valid_msr_intercept(u32 index)
 853 {
 854         int i;
 855
 856         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 857                 if (direct_access_msrs[i].index == index)
 858                         return true;
 859
 860         return false;
 861 }
 862
 863 static void set_msr_interception(u32 *msrpm, unsigned msr,
 864                                  int read, int write)
 865 {
 866         u8 bit_read, bit_write;
 867         unsigned long tmp;
 868         u32 offset;
 869
 870         /*
 871          * If this warning triggers extend the direct_access_msrs list at the
 872          * beginning of the file
 873          */
 874         WARN_ON(!valid_msr_intercept(msr));
 875
 876         offset    = svm_msrpm_offset(msr);
 877         bit_read  = 2 * (msr & 0x0f);
 878         bit_write = 2 * (msr & 0x0f) + 1;
 879         tmp       = msrpm[offset];
 880
 881         BUG_ON(offset == MSR_INVALID);
 882
 883         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 884         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 885
 886         msrpm[offset] = tmp;
 887 }
 888
 889 static void svm_vcpu_init_msrpm(u32 *msrpm)
 890 {
 891         int i;
 892
 893         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 894
 895         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 896                 if (!direct_access_msrs[i].always)
 897                         continue;
 898
 899                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 900         }
 901 }
 902
 903 static void add_msr_offset(u32 offset)
 904 {
 905         int i;
 906
 907         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 908
 909                 /* Offset already in list? */
 910                 if (msrpm_offsets[i] == offset)
 911                         return;
 912
 913                 /* Slot used by another offset? */
 914                 if (msrpm_offsets[i] != MSR_INVALID)
 915                         continue;
 916
 917                 /* Add offset to list */
 918                 msrpm_offsets[i] = offset;
 919
 920                 return;
 921         }
 922
 923         /*
 924          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 925          * increase MSRPM_OFFSETS in this case.
 926          */
 927         BUG();
 928 }
 929
 930 static void init_msrpm_offsets(void)
 931 {
 932         int i;
 933
 934         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 935
 936         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 937                 u32 offset;
 938
 939                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 940                 BUG_ON(offset == MSR_INVALID);
 941
 942                 add_msr_offset(offset);
 943         }
 944 }
 945
 946 static void svm_enable_lbrv(struct vcpu_svm *svm)
 947 {
 948         u32 *msrpm = svm->msrpm;
 949
 950         svm->vmcb->control.lbr_ctl = 1;
 951         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 952         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 953         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 954         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 955 }
 956
 957 static void svm_disable_lbrv(struct vcpu_svm *svm)
 958 {
 959         u32 *msrpm = svm->msrpm;
 960
 961         svm->vmcb->control.lbr_ctl = 0;
 962         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 963         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 964         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 965         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 966 }
 967
 968 /* Note:
 969  * This hash table is used to map VM_ID to a struct kvm_arch,
 970  * when handling AMD IOMMU GALOG notification to schedule in
 971  * a particular vCPU.
 972  */
 973 #define SVM_VM_DATA_HASH_BITS   8
 974 DECLARE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
 975 static spinlock_t svm_vm_data_hash_lock;
 976
 977 /* Note:
 978  * This function is called from IOMMU driver to notify
 979  * SVM to schedule in a particular vCPU of a particular VM.
 980  */
 981 static int avic_ga_log_notifier(u32 ga_tag)
 982 {
 983         unsigned long flags;
 984         struct kvm_arch *ka = NULL;
 985         struct kvm_vcpu *vcpu = NULL;
 986         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
 987         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
 988
 989         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
 990
 991         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
 992         hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
 993                 struct kvm *kvm = container_of(ka, struct kvm, arch);
 994                 struct kvm_arch *vm_data = &kvm->arch;
 995
 996                 if (vm_data->avic_vm_id != vm_id)
 997                         continue;
 998                 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
 999                 break;
1000         }
1001         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1002
1003         if (!vcpu)
1004                 return 0;
1005
1006         /* Note:
1007          * At this point, the IOMMU should have already set the pending
1008          * bit in the vAPIC backing page. So, we just need to schedule
1009          * in the vcpu.
1010          */
1011         if (vcpu->mode == OUTSIDE_GUEST_MODE)
1012                 kvm_vcpu_wake_up(vcpu);
1013
1014         return 0;
1015 }
1016
1017 static __init int svm_hardware_setup(void)
1018 {
1019         int cpu;
1020         struct page *iopm_pages;
1021         void *iopm_va;
1022         int r;
1023
1024         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1025
1026         if (!iopm_pages)
1027                 return -ENOMEM;
1028
1029         iopm_va = page_address(iopm_pages);
1030         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1031         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1032
1033         init_msrpm_offsets();
1034
1035         if (boot_cpu_has(X86_FEATURE_NX))
1036                 kvm_enable_efer_bits(EFER_NX);
1037
1038         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1039                 kvm_enable_efer_bits(EFER_FFXSR);
1040
1041         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1042                 kvm_has_tsc_control = true;
1043                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1044                 kvm_tsc_scaling_ratio_frac_bits = 32;
1045         }
1046
1047         if (nested) {
1048                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1049                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1050         }
1051
1052         for_each_possible_cpu(cpu) {
1053                 r = svm_cpu_init(cpu);
1054                 if (r)
1055                         goto err;
1056         }
1057
1058         if (!boot_cpu_has(X86_FEATURE_NPT))
1059                 npt_enabled = false;
1060
1061         if (npt_enabled && !npt) {
1062                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1063                 npt_enabled = false;
1064         }
1065
1066         if (npt_enabled) {
1067                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1068                 kvm_enable_tdp();
1069         } else
1070                 kvm_disable_tdp();
1071
1072         if (avic) {
1073                 if (!npt_enabled ||
1074                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1075                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1076                         avic = false;
1077                 } else {
1078                         pr_info("AVIC enabled\n");
1079
1080                         hash_init(svm_vm_data_hash);
1081                         spin_lock_init(&svm_vm_data_hash_lock);
1082                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1083                 }
1084         }
1085
1086         return 0;
1087
1088 err:
1089         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1090         iopm_base = 0;
1091         return r;
1092 }
1093
1094 static __exit void svm_hardware_unsetup(void)
1095 {
1096         int cpu;
1097
1098         for_each_possible_cpu(cpu)
1099                 svm_cpu_uninit(cpu);
1100
1101         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1102         iopm_base = 0;
1103 }
1104
1105 static void init_seg(struct vmcb_seg *seg)
1106 {
1107         seg->selector = 0;
1108         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1109                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1110         seg->limit = 0xffff;
1111         seg->base = 0;
1112 }
1113
1114 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1115 {
1116         seg->selector = 0;
1117         seg->attrib = SVM_SELECTOR_P_MASK | type;
1118         seg->limit = 0xffff;
1119         seg->base = 0;
1120 }
1121
1122 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1123 {
1124         struct vcpu_svm *svm = to_svm(vcpu);
1125         u64 g_tsc_offset = 0;
1126
1127         if (is_guest_mode(vcpu)) {
1128                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1129                                svm->nested.hsave->control.tsc_offset;
1130                 svm->nested.hsave->control.tsc_offset = offset;
1131         } else
1132                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1133                                            svm->vmcb->control.tsc_offset,
1134                                            offset);
1135
1136         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1137
1138         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1139 }
1140
1141 static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
1142 {
1143         struct vcpu_svm *svm = to_svm(vcpu);
1144
1145         svm->vmcb->control.tsc_offset += adjustment;
1146         if (is_guest_mode(vcpu))
1147                 svm->nested.hsave->control.tsc_offset += adjustment;
1148         else
1149                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1150                                      svm->vmcb->control.tsc_offset - adjustment,
1151                                      svm->vmcb->control.tsc_offset);
1152
1153         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1154 }
1155
1156 static void avic_init_vmcb(struct vcpu_svm *svm)
1157 {
1158         struct vmcb *vmcb = svm->vmcb;
1159         struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1160         phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1161         phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1162         phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1163
1164         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1165         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1166         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1167         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1168         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1169         svm->vcpu.arch.apicv_active = true;
1170 }
1171
1172 static void init_vmcb(struct vcpu_svm *svm)
1173 {
1174         struct vmcb_control_area *control = &svm->vmcb->control;
1175         struct vmcb_save_area *save = &svm->vmcb->save;
1176
1177         svm->vcpu.fpu_active = 1;
1178         svm->vcpu.arch.hflags = 0;
1179
1180         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1181         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1182         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1183         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1184         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1185         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1186         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1187                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1188
1189         set_dr_intercepts(svm);
1190
1191         set_exception_intercept(svm, PF_VECTOR);
1192         set_exception_intercept(svm, UD_VECTOR);
1193         set_exception_intercept(svm, MC_VECTOR);
1194         set_exception_intercept(svm, AC_VECTOR);
1195         set_exception_intercept(svm, DB_VECTOR);
1196
1197         set_intercept(svm, INTERCEPT_INTR);
1198         set_intercept(svm, INTERCEPT_NMI);
1199         set_intercept(svm, INTERCEPT_SMI);
1200         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1201         set_intercept(svm, INTERCEPT_RDPMC);
1202         set_intercept(svm, INTERCEPT_CPUID);
1203         set_intercept(svm, INTERCEPT_INVD);
1204         set_intercept(svm, INTERCEPT_HLT);
1205         set_intercept(svm, INTERCEPT_INVLPG);
1206         set_intercept(svm, INTERCEPT_INVLPGA);
1207         set_intercept(svm, INTERCEPT_IOIO_PROT);
1208         set_intercept(svm, INTERCEPT_MSR_PROT);
1209         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1210         set_intercept(svm, INTERCEPT_SHUTDOWN);
1211         set_intercept(svm, INTERCEPT_VMRUN);
1212         set_intercept(svm, INTERCEPT_VMMCALL);
1213         set_intercept(svm, INTERCEPT_VMLOAD);
1214         set_intercept(svm, INTERCEPT_VMSAVE);
1215         set_intercept(svm, INTERCEPT_STGI);
1216         set_intercept(svm, INTERCEPT_CLGI);
1217         set_intercept(svm, INTERCEPT_SKINIT);
1218         set_intercept(svm, INTERCEPT_WBINVD);
1219         set_intercept(svm, INTERCEPT_MONITOR);
1220         set_intercept(svm, INTERCEPT_MWAIT);
1221         set_intercept(svm, INTERCEPT_XSETBV);
1222
1223         control->iopm_base_pa = iopm_base;
1224         control->msrpm_base_pa = __pa(svm->msrpm);
1225         control->int_ctl = V_INTR_MASKING_MASK;
1226
1227         init_seg(&save->es);
1228         init_seg(&save->ss);
1229         init_seg(&save->ds);
1230         init_seg(&save->fs);
1231         init_seg(&save->gs);
1232
1233         save->cs.selector = 0xf000;
1234         save->cs.base = 0xffff0000;
1235         /* Executable/Readable Code Segment */
1236         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1237                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1238         save->cs.limit = 0xffff;
1239
1240         save->gdtr.limit = 0xffff;
1241         save->idtr.limit = 0xffff;
1242
1243         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1244         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1245
1246         svm_set_efer(&svm->vcpu, 0);
1247         save->dr6 = 0xffff0ff0;
1248         kvm_set_rflags(&svm->vcpu, 2);
1249         save->rip = 0x0000fff0;
1250         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1251
1252         /*
1253          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1254          * It also updates the guest-visible cr0 value.
1255          */
1256         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1257         kvm_mmu_reset_context(&svm->vcpu);
1258
1259         save->cr4 = X86_CR4_PAE;
1260         /* rdx = ?? */
1261
1262         if (npt_enabled) {
1263                 /* Setup VMCB for Nested Paging */
1264                 control->nested_ctl = 1;
1265                 clr_intercept(svm, INTERCEPT_INVLPG);
1266                 clr_exception_intercept(svm, PF_VECTOR);
1267                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1268                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1269                 save->g_pat = svm->vcpu.arch.pat;
1270                 save->cr3 = 0;
1271                 save->cr4 = 0;
1272         }
1273         svm->asid_generation = 0;
1274
1275         svm->nested.vmcb = 0;
1276         svm->vcpu.arch.hflags = 0;
1277
1278         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1279                 control->pause_filter_count = 3000;
1280                 set_intercept(svm, INTERCEPT_PAUSE);
1281         }
1282
1283         if (avic)
1284                 avic_init_vmcb(svm);
1285
1286         mark_all_dirty(svm->vmcb);
1287
1288         enable_gif(svm);
1289
1290 }
1291
1292 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1293 {
1294         u64 *avic_physical_id_table;
1295         struct kvm_arch *vm_data = &vcpu->kvm->arch;
1296
1297         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1298                 return NULL;
1299
1300         avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1301
1302         return &avic_physical_id_table[index];
1303 }
1304
1305 /**
1306  * Note:
1307  * AVIC hardware walks the nested page table to check permissions,
1308  * but does not use the SPA address specified in the leaf page
1309  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1310  * field of the VMCB. Therefore, we set up the
1311  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1312  */
1313 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1314 {
1315         struct kvm *kvm = vcpu->kvm;
1316         int ret;
1317
1318         if (kvm->arch.apic_access_page_done)
1319                 return 0;
1320
1321         ret = x86_set_memory_region(kvm,
1322                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1323                                     APIC_DEFAULT_PHYS_BASE,
1324                                     PAGE_SIZE);
1325         if (ret)
1326                 return ret;
1327
1328         kvm->arch.apic_access_page_done = true;
1329         return 0;
1330 }
1331
1332 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1333 {
1334         int ret;
1335         u64 *entry, new_entry;
1336         int id = vcpu->vcpu_id;
1337         struct vcpu_svm *svm = to_svm(vcpu);
1338
1339         ret = avic_init_access_page(vcpu);
1340         if (ret)
1341                 return ret;
1342
1343         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1344                 return -EINVAL;
1345
1346         if (!svm->vcpu.arch.apic->regs)
1347                 return -EINVAL;
1348
1349         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1350
1351         /* Setting AVIC backing page address in the phy APIC ID table */
1352         entry = avic_get_physical_id_entry(vcpu, id);
1353         if (!entry)
1354                 return -EINVAL;
1355
1356         new_entry = READ_ONCE(*entry);
1357         new_entry = (page_to_phys(svm->avic_backing_page) &
1358                      AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1359                      AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1360         WRITE_ONCE(*entry, new_entry);
1361
1362         svm->avic_physical_id_cache = entry;
1363
1364         return 0;
1365 }
1366
1367 static inline int avic_get_next_vm_id(void)
1368 {
1369         int id;
1370
1371         spin_lock(&avic_vm_id_lock);
1372
1373         /* AVIC VM ID is one-based. */
1374         id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1375         if (id <= AVIC_VM_ID_MASK)
1376                 __set_bit(id, avic_vm_id_bitmap);
1377         else
1378                 id = -EAGAIN;
1379
1380         spin_unlock(&avic_vm_id_lock);
1381         return id;
1382 }
1383
1384 static inline int avic_free_vm_id(int id)
1385 {
1386         if (id <= 0 || id > AVIC_VM_ID_MASK)
1387                 return -EINVAL;
1388
1389         spin_lock(&avic_vm_id_lock);
1390         __clear_bit(id, avic_vm_id_bitmap);
1391         spin_unlock(&avic_vm_id_lock);
1392         return 0;
1393 }
1394
1395 static void avic_vm_destroy(struct kvm *kvm)
1396 {
1397         unsigned long flags;
1398         struct kvm_arch *vm_data = &kvm->arch;
1399
1400         avic_free_vm_id(vm_data->avic_vm_id);
1401
1402         if (vm_data->avic_logical_id_table_page)
1403                 __free_page(vm_data->avic_logical_id_table_page);
1404         if (vm_data->avic_physical_id_table_page)
1405                 __free_page(vm_data->avic_physical_id_table_page);
1406
1407         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1408         hash_del(&vm_data->hnode);
1409         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1410 }
1411
1412 static int avic_vm_init(struct kvm *kvm)
1413 {
1414         unsigned long flags;
1415         int vm_id, err = -ENOMEM;
1416         struct kvm_arch *vm_data = &kvm->arch;
1417         struct page *p_page;
1418         struct page *l_page;
1419
1420         if (!avic)
1421                 return 0;
1422
1423         vm_id = avic_get_next_vm_id();
1424         if (vm_id < 0)
1425                 return vm_id;
1426         vm_data->avic_vm_id = (u32)vm_id;
1427
1428         /* Allocating physical APIC ID table (4KB) */
1429         p_page = alloc_page(GFP_KERNEL);
1430         if (!p_page)
1431                 goto free_avic;
1432
1433         vm_data->avic_physical_id_table_page = p_page;
1434         clear_page(page_address(p_page));
1435
1436         /* Allocating logical APIC ID table (4KB) */
1437         l_page = alloc_page(GFP_KERNEL);
1438         if (!l_page)
1439                 goto free_avic;
1440
1441         vm_data->avic_logical_id_table_page = l_page;
1442         clear_page(page_address(l_page));
1443
1444         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1445         hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1446         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1447
1448         return 0;
1449
1450 free_avic:
1451         avic_vm_destroy(kvm);
1452         return err;
1453 }
1454
1455 static inline int
1456 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1457 {
1458         int ret = 0;
1459         unsigned long flags;
1460         struct amd_svm_iommu_ir *ir;
1461         struct vcpu_svm *svm = to_svm(vcpu);
1462
1463         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1464                 return 0;
1465
1466         /*
1467          * Here, we go through the per-vcpu ir_list to update all existing
1468          * interrupt remapping table entry targeting this vcpu.
1469          */
1470         spin_lock_irqsave(&svm->ir_list_lock, flags);
1471
1472         if (list_empty(&svm->ir_list))
1473                 goto out;
1474
1475         list_for_each_entry(ir, &svm->ir_list, node) {
1476                 ret = amd_iommu_update_ga(cpu, r, ir->data);
1477                 if (ret)
1478                         break;
1479         }
1480 out:
1481         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1482         return ret;
1483 }
1484
1485 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1486 {
1487         u64 entry;
1488         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1489         int h_physical_id = kvm_cpu_get_apicid(cpu);
1490         struct vcpu_svm *svm = to_svm(vcpu);
1491
1492         if (!kvm_vcpu_apicv_active(vcpu))
1493                 return;
1494
1495         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1496                 return;
1497
1498         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1499         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1500
1501         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1502         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1503
1504         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1505         if (svm->avic_is_running)
1506                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1507
1508         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1509         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1510                                         svm->avic_is_running);
1511 }
1512
1513 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1514 {
1515         u64 entry;
1516         struct vcpu_svm *svm = to_svm(vcpu);
1517
1518         if (!kvm_vcpu_apicv_active(vcpu))
1519                 return;
1520
1521         entry = READ_ONCE(*(svm->avic_physical_id_cache));
1522         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1523                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1524
1525         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1526         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1527 }
1528
1529 /**
1530  * This function is called during VCPU halt/unhalt.
1531  */
1532 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1533 {
1534         struct vcpu_svm *svm = to_svm(vcpu);
1535
1536         svm->avic_is_running = is_run;
1537         if (is_run)
1538                 avic_vcpu_load(vcpu, vcpu->cpu);
1539         else
1540                 avic_vcpu_put(vcpu);
1541 }
1542
1543 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1544 {
1545         struct vcpu_svm *svm = to_svm(vcpu);
1546         u32 dummy;
1547         u32 eax = 1;
1548
1549         if (!init_event) {
1550                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1551                                            MSR_IA32_APICBASE_ENABLE;
1552                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1553                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1554         }
1555         init_vmcb(svm);
1556
1557         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1558         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1559
1560         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1561                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1562 }
1563
1564 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1565 {
1566         struct vcpu_svm *svm;
1567         struct page *page;
1568         struct page *msrpm_pages;
1569         struct page *hsave_page;
1570         struct page *nested_msrpm_pages;
1571         int err;
1572
1573         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1574         if (!svm) {
1575                 err = -ENOMEM;
1576                 goto out;
1577         }
1578
1579         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1580         if (err)
1581                 goto free_svm;
1582
1583         err = -ENOMEM;
1584         page = alloc_page(GFP_KERNEL);
1585         if (!page)
1586                 goto uninit;
1587
1588         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1589         if (!msrpm_pages)
1590                 goto free_page1;
1591
1592         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1593         if (!nested_msrpm_pages)
1594                 goto free_page2;
1595
1596         hsave_page = alloc_page(GFP_KERNEL);
1597         if (!hsave_page)
1598                 goto free_page3;
1599
1600         if (avic) {
1601                 err = avic_init_backing_page(&svm->vcpu);
1602                 if (err)
1603                         goto free_page4;
1604
1605                 INIT_LIST_HEAD(&svm->ir_list);
1606                 spin_lock_init(&svm->ir_list_lock);
1607         }
1608
1609         /* We initialize this flag to true to make sure that the is_running
1610          * bit would be set the first time the vcpu is loaded.
1611          */
1612         svm->avic_is_running = true;
1613
1614         svm->nested.hsave = page_address(hsave_page);
1615
1616         svm->msrpm = page_address(msrpm_pages);
1617         svm_vcpu_init_msrpm(svm->msrpm);
1618
1619         svm->nested.msrpm = page_address(nested_msrpm_pages);
1620         svm_vcpu_init_msrpm(svm->nested.msrpm);
1621
1622         svm->vmcb = page_address(page);
1623         clear_page(svm->vmcb);
1624         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1625         svm->asid_generation = 0;
1626         init_vmcb(svm);
1627
1628         svm_init_osvw(&svm->vcpu);
1629
1630         return &svm->vcpu;
1631
1632 free_page4:
1633         __free_page(hsave_page);
1634 free_page3:
1635         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1636 free_page2:
1637         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1638 free_page1:
1639         __free_page(page);
1640 uninit:
1641         kvm_vcpu_uninit(&svm->vcpu);
1642 free_svm:
1643         kmem_cache_free(kvm_vcpu_cache, svm);
1644 out:
1645         return ERR_PTR(err);
1646 }
1647
1648 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1649 {
1650         struct vcpu_svm *svm = to_svm(vcpu);
1651
1652         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1653         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1654         __free_page(virt_to_page(svm->nested.hsave));
1655         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1656         kvm_vcpu_uninit(vcpu);
1657         kmem_cache_free(kvm_vcpu_cache, svm);
1658 }
1659
1660 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1661 {
1662         struct vcpu_svm *svm = to_svm(vcpu);
1663         int i;
1664
1665         if (unlikely(cpu != vcpu->cpu)) {
1666                 svm->asid_generation = 0;
1667                 mark_all_dirty(svm->vmcb);
1668         }
1669
1670 #ifdef CONFIG_X86_64
1671         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1672 #endif
1673         savesegment(fs, svm->host.fs);
1674         savesegment(gs, svm->host.gs);
1675         svm->host.ldt = kvm_read_ldt();
1676
1677         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1678                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1679
1680         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1681                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1682                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1683                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1684                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1685                 }
1686         }
1687         /* This assumes that the kernel never uses MSR_TSC_AUX */
1688         if (static_cpu_has(X86_FEATURE_RDTSCP))
1689                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1690
1691         avic_vcpu_load(vcpu, cpu);
1692 }
1693
1694 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1695 {
1696         struct vcpu_svm *svm = to_svm(vcpu);
1697         int i;
1698
1699         avic_vcpu_put(vcpu);
1700
1701         ++vcpu->stat.host_state_reload;
1702         kvm_load_ldt(svm->host.ldt);
1703 #ifdef CONFIG_X86_64
1704         loadsegment(fs, svm->host.fs);
1705         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1706         load_gs_index(svm->host.gs);
1707 #else
1708 #ifdef CONFIG_X86_32_LAZY_GS
1709         loadsegment(gs, svm->host.gs);
1710 #endif
1711 #endif
1712         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1713                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1714 }
1715
1716 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1717 {
1718         avic_set_running(vcpu, false);
1719 }
1720
1721 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1722 {
1723         avic_set_running(vcpu, true);
1724 }
1725
1726 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1727 {
1728         return to_svm(vcpu)->vmcb->save.rflags;
1729 }
1730
1731 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1732 {
1733        /*
1734         * Any change of EFLAGS.VM is accompanied by a reload of SS
1735         * (caused by either a task switch or an inter-privilege IRET),
1736         * so we do not need to update the CPL here.
1737         */
1738         to_svm(vcpu)->vmcb->save.rflags = rflags;
1739 }
1740
1741 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1742 {
1743         return 0;
1744 }
1745
1746 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1747 {
1748         switch (reg) {
1749         case VCPU_EXREG_PDPTR:
1750                 BUG_ON(!npt_enabled);
1751                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1752                 break;
1753         default:
1754                 BUG();
1755         }
1756 }
1757
1758 static void svm_set_vintr(struct vcpu_svm *svm)
1759 {
1760         set_intercept(svm, INTERCEPT_VINTR);
1761 }
1762
1763 static void svm_clear_vintr(struct vcpu_svm *svm)
1764 {
1765         clr_intercept(svm, INTERCEPT_VINTR);
1766 }
1767
1768 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1769 {
1770         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1771
1772         switch (seg) {
1773         case VCPU_SREG_CS: return &save->cs;
1774         case VCPU_SREG_DS: return &save->ds;
1775         case VCPU_SREG_ES: return &save->es;
1776         case VCPU_SREG_FS: return &save->fs;
1777         case VCPU_SREG_GS: return &save->gs;
1778         case VCPU_SREG_SS: return &save->ss;
1779         case VCPU_SREG_TR: return &save->tr;
1780         case VCPU_SREG_LDTR: return &save->ldtr;
1781         }
1782         BUG();
1783         return NULL;
1784 }
1785
1786 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1787 {
1788         struct vmcb_seg *s = svm_seg(vcpu, seg);
1789
1790         return s->base;
1791 }
1792
1793 static void svm_get_segment(struct kvm_vcpu *vcpu,
1794                             struct kvm_segment *var, int seg)
1795 {
1796         struct vmcb_seg *s = svm_seg(vcpu, seg);
1797
1798         var->base = s->base;
1799         var->limit = s->limit;
1800         var->selector = s->selector;
1801         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1802         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1803         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1804         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1805         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1806         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1807         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1808
1809         /*
1810          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1811          * However, the SVM spec states that the G bit is not observed by the
1812          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1813          * So let's synthesize a legal G bit for all segments, this helps
1814          * running KVM nested. It also helps cross-vendor migration, because
1815          * Intel's vmentry has a check on the 'G' bit.
1816          */
1817         var->g = s->limit > 0xfffff;
1818
1819         /*
1820          * AMD's VMCB does not have an explicit unusable field, so emulate it
1821          * for cross vendor migration purposes by "not present"
1822          */
1823         var->unusable = !var->present || (var->type == 0);
1824
1825         switch (seg) {
1826         case VCPU_SREG_TR:
1827                 /*
1828                  * Work around a bug where the busy flag in the tr selector
1829                  * isn't exposed
1830                  */
1831                 var->type |= 0x2;
1832                 break;
1833         case VCPU_SREG_DS:
1834         case VCPU_SREG_ES:
1835         case VCPU_SREG_FS:
1836         case VCPU_SREG_GS:
1837                 /*
1838                  * The accessed bit must always be set in the segment
1839                  * descriptor cache, although it can be cleared in the
1840                  * descriptor, the cached bit always remains at 1. Since
1841                  * Intel has a check on this, set it here to support
1842                  * cross-vendor migration.
1843                  */
1844                 if (!var->unusable)
1845                         var->type |= 0x1;
1846                 break;
1847         case VCPU_SREG_SS:
1848                 /*
1849                  * On AMD CPUs sometimes the DB bit in the segment
1850                  * descriptor is left as 1, although the whole segment has
1851                  * been made unusable. Clear it here to pass an Intel VMX
1852                  * entry check when cross vendor migrating.
1853                  */
1854                 if (var->unusable)
1855                         var->db = 0;
1856                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1857                 break;
1858         }
1859 }
1860
1861 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1862 {
1863         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1864
1865         return save->cpl;
1866 }
1867
1868 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1869 {
1870         struct vcpu_svm *svm = to_svm(vcpu);
1871
1872         dt->size = svm->vmcb->save.idtr.limit;
1873         dt->address = svm->vmcb->save.idtr.base;
1874 }
1875
1876 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1877 {
1878         struct vcpu_svm *svm = to_svm(vcpu);
1879
1880         svm->vmcb->save.idtr.limit = dt->size;
1881         svm->vmcb->save.idtr.base = dt->address ;
1882         mark_dirty(svm->vmcb, VMCB_DT);
1883 }
1884
1885 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1886 {
1887         struct vcpu_svm *svm = to_svm(vcpu);
1888
1889         dt->size = svm->vmcb->save.gdtr.limit;
1890         dt->address = svm->vmcb->save.gdtr.base;
1891 }
1892
1893 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1894 {
1895         struct vcpu_svm *svm = to_svm(vcpu);
1896
1897         svm->vmcb->save.gdtr.limit = dt->size;
1898         svm->vmcb->save.gdtr.base = dt->address ;
1899         mark_dirty(svm->vmcb, VMCB_DT);
1900 }
1901
1902 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1903 {
1904 }
1905
1906 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1907 {
1908 }
1909
1910 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1911 {
1912 }
1913
1914 static void update_cr0_intercept(struct vcpu_svm *svm)
1915 {
1916         ulong gcr0 = svm->vcpu.arch.cr0;
1917         u64 *hcr0 = &svm->vmcb->save.cr0;
1918
1919         if (!svm->vcpu.fpu_active)
1920                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1921         else
1922                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1923                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1924
1925         mark_dirty(svm->vmcb, VMCB_CR);
1926
1927         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1928                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1929                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1930         } else {
1931                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1932                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1933         }
1934 }
1935
1936 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1937 {
1938         struct vcpu_svm *svm = to_svm(vcpu);
1939
1940 #ifdef CONFIG_X86_64
1941         if (vcpu->arch.efer & EFER_LME) {
1942                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1943                         vcpu->arch.efer |= EFER_LMA;
1944                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1945                 }
1946
1947                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1948                         vcpu->arch.efer &= ~EFER_LMA;
1949                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1950                 }
1951         }
1952 #endif
1953         vcpu->arch.cr0 = cr0;
1954
1955         if (!npt_enabled)
1956                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1957
1958         if (!vcpu->fpu_active)
1959                 cr0 |= X86_CR0_TS;
1960         /*
1961          * re-enable caching here because the QEMU bios
1962          * does not do it - this results in some delay at
1963          * reboot
1964          */
1965         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1966                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1967         svm->vmcb->save.cr0 = cr0;
1968         mark_dirty(svm->vmcb, VMCB_CR);
1969         update_cr0_intercept(svm);
1970 }
1971
1972 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1973 {
1974         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1975         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1976
1977         if (cr4 & X86_CR4_VMXE)
1978                 return 1;
1979
1980         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1981                 svm_flush_tlb(vcpu);
1982
1983         vcpu->arch.cr4 = cr4;
1984         if (!npt_enabled)
1985                 cr4 |= X86_CR4_PAE;
1986         cr4 |= host_cr4_mce;
1987         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1988         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1989         return 0;
1990 }
1991
1992 static void svm_set_segment(struct kvm_vcpu *vcpu,
1993                             struct kvm_segment *var, int seg)
1994 {
1995         struct vcpu_svm *svm = to_svm(vcpu);
1996         struct vmcb_seg *s = svm_seg(vcpu, seg);
1997
1998         s->base = var->base;
1999         s->limit = var->limit;
2000         s->selector = var->selector;
2001         if (var->unusable)
2002                 s->attrib = 0;
2003         else {
2004                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2005                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2006                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2007                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
2008                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2009                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2010                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2011                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2012         }
2013
2014         /*
2015          * This is always accurate, except if SYSRET returned to a segment
2016          * with SS.DPL != 3.  Intel does not have this quirk, and always
2017          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2018          * would entail passing the CPL to userspace and back.
2019          */
2020         if (seg == VCPU_SREG_SS)
2021                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2022
2023         mark_dirty(svm->vmcb, VMCB_SEG);
2024 }
2025
2026 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2027 {
2028         struct vcpu_svm *svm = to_svm(vcpu);
2029
2030         clr_exception_intercept(svm, BP_VECTOR);
2031
2032         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2033                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2034                         set_exception_intercept(svm, BP_VECTOR);
2035         } else
2036                 vcpu->guest_debug = 0;
2037 }
2038
2039 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2040 {
2041         if (sd->next_asid > sd->max_asid) {
2042                 ++sd->asid_generation;
2043                 sd->next_asid = 1;
2044                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2045         }
2046
2047         svm->asid_generation = sd->asid_generation;
2048         svm->vmcb->control.asid = sd->next_asid++;
2049
2050         mark_dirty(svm->vmcb, VMCB_ASID);
2051 }
2052
2053 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2054 {
2055         return to_svm(vcpu)->vmcb->save.dr6;
2056 }
2057
2058 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2059 {
2060         struct vcpu_svm *svm = to_svm(vcpu);
2061
2062         svm->vmcb->save.dr6 = value;
2063         mark_dirty(svm->vmcb, VMCB_DR);
2064 }
2065
2066 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2067 {
2068         struct vcpu_svm *svm = to_svm(vcpu);
2069
2070         get_debugreg(vcpu->arch.db[0], 0);
2071         get_debugreg(vcpu->arch.db[1], 1);
2072         get_debugreg(vcpu->arch.db[2], 2);
2073         get_debugreg(vcpu->arch.db[3], 3);
2074         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2075         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2076
2077         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2078         set_dr_intercepts(svm);
2079 }
2080
2081 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2082 {
2083         struct vcpu_svm *svm = to_svm(vcpu);
2084
2085         svm->vmcb->save.dr7 = value;
2086         mark_dirty(svm->vmcb, VMCB_DR);
2087 }
2088
2089 static int pf_interception(struct vcpu_svm *svm)
2090 {
2091         u64 fault_address = svm->vmcb->control.exit_info_2;
2092         u32 error_code;
2093         int r = 1;
2094
2095         switch (svm->apf_reason) {
2096         default:
2097                 error_code = svm->vmcb->control.exit_info_1;
2098
2099                 trace_kvm_page_fault(fault_address, error_code);
2100                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2101                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2102                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2103                         svm->vmcb->control.insn_bytes,
2104                         svm->vmcb->control.insn_len);
2105                 break;
2106         case KVM_PV_REASON_PAGE_NOT_PRESENT:
2107                 svm->apf_reason = 0;
2108                 local_irq_disable();
2109                 kvm_async_pf_task_wait(fault_address);
2110                 local_irq_enable();
2111                 break;
2112         case KVM_PV_REASON_PAGE_READY:
2113                 svm->apf_reason = 0;
2114                 local_irq_disable();
2115                 kvm_async_pf_task_wake(fault_address);
2116                 local_irq_enable();
2117                 break;
2118         }
2119         return r;
2120 }
2121
2122 static int db_interception(struct vcpu_svm *svm)
2123 {
2124         struct kvm_run *kvm_run = svm->vcpu.run;
2125
2126         if (!(svm->vcpu.guest_debug &
2127               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2128                 !svm->nmi_singlestep) {
2129                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2130                 return 1;
2131         }
2132
2133         if (svm->nmi_singlestep) {
2134                 svm->nmi_singlestep = false;
2135                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2136                         svm->vmcb->save.rflags &=
2137                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2138         }
2139
2140         if (svm->vcpu.guest_debug &
2141             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2142                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2143                 kvm_run->debug.arch.pc =
2144                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2145                 kvm_run->debug.arch.exception = DB_VECTOR;
2146                 return 0;
2147         }
2148
2149         return 1;
2150 }
2151
2152 static int bp_interception(struct vcpu_svm *svm)
2153 {
2154         struct kvm_run *kvm_run = svm->vcpu.run;
2155
2156         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2157         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2158         kvm_run->debug.arch.exception = BP_VECTOR;
2159         return 0;
2160 }
2161
2162 static int ud_interception(struct vcpu_svm *svm)
2163 {
2164         int er;
2165
2166         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2167         if (er != EMULATE_DONE)
2168                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2169         return 1;
2170 }
2171
2172 static int ac_interception(struct vcpu_svm *svm)
2173 {
2174         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2175         return 1;
2176 }
2177
2178 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
2179 {
2180         struct vcpu_svm *svm = to_svm(vcpu);
2181
2182         clr_exception_intercept(svm, NM_VECTOR);
2183
2184         svm->vcpu.fpu_active = 1;
2185         update_cr0_intercept(svm);
2186 }
2187
2188 static int nm_interception(struct vcpu_svm *svm)
2189 {
2190         svm_fpu_activate(&svm->vcpu);
2191         return 1;
2192 }
2193
2194 static bool is_erratum_383(void)
2195 {
2196         int err, i;
2197         u64 value;
2198
2199         if (!erratum_383_found)
2200                 return false;
2201
2202         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2203         if (err)
2204                 return false;
2205
2206         /* Bit 62 may or may not be set for this mce */
2207         value &= ~(1ULL << 62);
2208
2209         if (value != 0xb600000000010015ULL)
2210                 return false;
2211
2212         /* Clear MCi_STATUS registers */
2213         for (i = 0; i < 6; ++i)
2214                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2215
2216         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2217         if (!err) {
2218                 u32 low, high;
2219
2220                 value &= ~(1ULL << 2);
2221                 low    = lower_32_bits(value);
2222                 high   = upper_32_bits(value);
2223
2224                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2225         }
2226
2227         /* Flush tlb to evict multi-match entries */
2228         __flush_tlb_all();
2229
2230         return true;
2231 }
2232
2233 static void svm_handle_mce(struct vcpu_svm *svm)
2234 {
2235         if (is_erratum_383()) {
2236                 /*
2237                  * Erratum 383 triggered. Guest state is corrupt so kill the
2238                  * guest.
2239                  */
2240                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2241
2242                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2243
2244                 return;
2245         }
2246
2247         /*
2248          * On an #MC intercept the MCE handler is not called automatically in
2249          * the host. So do it by hand here.
2250          */
2251         asm volatile (
2252                 "int $0x12\n");
2253         /* not sure if we ever come back to this point */
2254
2255         return;
2256 }
2257
2258 static int mc_interception(struct vcpu_svm *svm)
2259 {
2260         return 1;
2261 }
2262
2263 static int shutdown_interception(struct vcpu_svm *svm)
2264 {
2265         struct kvm_run *kvm_run = svm->vcpu.run;
2266
2267         /*
2268          * VMCB is undefined after a SHUTDOWN intercept
2269          * so reinitialize it.
2270          */
2271         clear_page(svm->vmcb);
2272         init_vmcb(svm);
2273
2274         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2275         return 0;
2276 }
2277
2278 static int io_interception(struct vcpu_svm *svm)
2279 {
2280         struct kvm_vcpu *vcpu = &svm->vcpu;
2281         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2282         int size, in, string;
2283         unsigned port;
2284
2285         ++svm->vcpu.stat.io_exits;
2286         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2287         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2288         if (string || in)
2289                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2290
2291         port = io_info >> 16;
2292         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2293         svm->next_rip = svm->vmcb->control.exit_info_2;
2294         skip_emulated_instruction(&svm->vcpu);
2295
2296         return kvm_fast_pio_out(vcpu, size, port);
2297 }
2298
2299 static int nmi_interception(struct vcpu_svm *svm)
2300 {
2301         return 1;
2302 }
2303
2304 static int intr_interception(struct vcpu_svm *svm)
2305 {
2306         ++svm->vcpu.stat.irq_exits;
2307         return 1;
2308 }
2309
2310 static int nop_on_interception(struct vcpu_svm *svm)
2311 {
2312         return 1;
2313 }
2314
2315 static int halt_interception(struct vcpu_svm *svm)
2316 {
2317         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2318         return kvm_emulate_halt(&svm->vcpu);
2319 }
2320
2321 static int vmmcall_interception(struct vcpu_svm *svm)
2322 {
2323         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2324         return kvm_emulate_hypercall(&svm->vcpu);
2325 }
2326
2327 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2328 {
2329         struct vcpu_svm *svm = to_svm(vcpu);
2330
2331         return svm->nested.nested_cr3;
2332 }
2333
2334 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2335 {
2336         struct vcpu_svm *svm = to_svm(vcpu);
2337         u64 cr3 = svm->nested.nested_cr3;
2338         u64 pdpte;
2339         int ret;
2340
2341         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2342                                        offset_in_page(cr3) + index * 8, 8);
2343         if (ret)
2344                 return 0;
2345         return pdpte;
2346 }
2347
2348 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2349                                    unsigned long root)
2350 {
2351         struct vcpu_svm *svm = to_svm(vcpu);
2352
2353         svm->vmcb->control.nested_cr3 = root;
2354         mark_dirty(svm->vmcb, VMCB_NPT);
2355         svm_flush_tlb(vcpu);
2356 }
2357
2358 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2359                                        struct x86_exception *fault)
2360 {
2361         struct vcpu_svm *svm = to_svm(vcpu);
2362
2363         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2364                 /*
2365                  * TODO: track the cause of the nested page fault, and
2366                  * correctly fill in the high bits of exit_info_1.
2367                  */
2368                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2369                 svm->vmcb->control.exit_code_hi = 0;
2370                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2371                 svm->vmcb->control.exit_info_2 = fault->address;
2372         }
2373
2374         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2375         svm->vmcb->control.exit_info_1 |= fault->error_code;
2376
2377         /*
2378          * The present bit is always zero for page structure faults on real
2379          * hardware.
2380          */
2381         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2382                 svm->vmcb->control.exit_info_1 &= ~1;
2383
2384         nested_svm_vmexit(svm);
2385 }
2386
2387 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2388 {
2389         WARN_ON(mmu_is_nested(vcpu));
2390         kvm_init_shadow_mmu(vcpu);
2391         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2392         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2393         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2394         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2395         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2396         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2397         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2398 }
2399
2400 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2401 {
2402         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2403 }
2404
2405 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2406 {
2407         if (!(svm->vcpu.arch.efer & EFER_SVME)
2408             || !is_paging(&svm->vcpu)) {
2409                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2410                 return 1;
2411         }
2412
2413         if (svm->vmcb->save.cpl) {
2414                 kvm_inject_gp(&svm->vcpu, 0);
2415                 return 1;
2416         }
2417
2418        return 0;
2419 }
2420
2421 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2422                                       bool has_error_code, u32 error_code)
2423 {
2424         int vmexit;
2425
2426         if (!is_guest_mode(&svm->vcpu))
2427                 return 0;
2428
2429         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2430         svm->vmcb->control.exit_code_hi = 0;
2431         svm->vmcb->control.exit_info_1 = error_code;
2432         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2433
2434         vmexit = nested_svm_intercept(svm);
2435         if (vmexit == NESTED_EXIT_DONE)
2436                 svm->nested.exit_required = true;
2437
2438         return vmexit;
2439 }
2440
2441 /* This function returns true if it is save to enable the irq window */
2442 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2443 {
2444         if (!is_guest_mode(&svm->vcpu))
2445                 return true;
2446
2447         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2448                 return true;
2449
2450         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2451                 return false;
2452
2453         /*
2454          * if vmexit was already requested (by intercepted exception
2455          * for instance) do not overwrite it with "external interrupt"
2456          * vmexit.
2457          */
2458         if (svm->nested.exit_required)
2459                 return false;
2460
2461         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2462         svm->vmcb->control.exit_info_1 = 0;
2463         svm->vmcb->control.exit_info_2 = 0;
2464
2465         if (svm->nested.intercept & 1ULL) {
2466                 /*
2467                  * The #vmexit can't be emulated here directly because this
2468                  * code path runs with irqs and preemption disabled. A
2469                  * #vmexit emulation might sleep. Only signal request for
2470                  * the #vmexit here.
2471                  */
2472                 svm->nested.exit_required = true;
2473                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2474                 return false;
2475         }
2476
2477         return true;
2478 }
2479
2480 /* This function returns true if it is save to enable the nmi window */
2481 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2482 {
2483         if (!is_guest_mode(&svm->vcpu))
2484                 return true;
2485
2486         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2487                 return true;
2488
2489         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2490         svm->nested.exit_required = true;
2491
2492         return false;
2493 }
2494
2495 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2496 {
2497         struct page *page;
2498
2499         might_sleep();
2500
2501         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2502         if (is_error_page(page))
2503                 goto error;
2504
2505         *_page = page;
2506
2507         return kmap(page);
2508
2509 error:
2510         kvm_inject_gp(&svm->vcpu, 0);
2511
2512         return NULL;
2513 }
2514
2515 static void nested_svm_unmap(struct page *page)
2516 {
2517         kunmap(page);
2518         kvm_release_page_dirty(page);
2519 }
2520
2521 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2522 {
2523         unsigned port, size, iopm_len;
2524         u16 val, mask;
2525         u8 start_bit;
2526         u64 gpa;
2527
2528         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2529                 return NESTED_EXIT_HOST;
2530
2531         port = svm->vmcb->control.exit_info_1 >> 16;
2532         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2533                 SVM_IOIO_SIZE_SHIFT;
2534         gpa  = svm->nested.vmcb_iopm + (port / 8);
2535         start_bit = port % 8;
2536         iopm_len = (start_bit + size > 8) ? 2 : 1;
2537         mask = (0xf >> (4 - size)) << start_bit;
2538         val = 0;
2539
2540         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2541                 return NESTED_EXIT_DONE;
2542
2543         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2544 }
2545
2546 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2547 {
2548         u32 offset, msr, value;
2549         int write, mask;
2550
2551         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2552                 return NESTED_EXIT_HOST;
2553
2554         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2555         offset = svm_msrpm_offset(msr);
2556         write  = svm->vmcb->control.exit_info_1 & 1;
2557         mask   = 1 << ((2 * (msr & 0xf)) + write);
2558
2559         if (offset == MSR_INVALID)
2560                 return NESTED_EXIT_DONE;
2561
2562         /* Offset is in 32 bit units but need in 8 bit units */
2563         offset *= 4;
2564
2565         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2566                 return NESTED_EXIT_DONE;
2567
2568         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2569 }
2570
2571 static int nested_svm_exit_special(struct vcpu_svm *svm)
2572 {
2573         u32 exit_code = svm->vmcb->control.exit_code;
2574
2575         switch (exit_code) {
2576         case SVM_EXIT_INTR:
2577         case SVM_EXIT_NMI:
2578         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2579                 return NESTED_EXIT_HOST;
2580         case SVM_EXIT_NPF:
2581                 /* For now we are always handling NPFs when using them */
2582                 if (npt_enabled)
2583                         return NESTED_EXIT_HOST;
2584                 break;
2585         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2586                 /* When we're shadowing, trap PFs, but not async PF */
2587                 if (!npt_enabled && svm->apf_reason == 0)
2588                         return NESTED_EXIT_HOST;
2589                 break;
2590         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2591                 nm_interception(svm);
2592                 break;
2593         default:
2594                 break;
2595         }
2596
2597         return NESTED_EXIT_CONTINUE;
2598 }
2599
2600 /*
2601  * If this function returns true, this #vmexit was already handled
2602  */
2603 static int nested_svm_intercept(struct vcpu_svm *svm)
2604 {
2605         u32 exit_code = svm->vmcb->control.exit_code;
2606         int vmexit = NESTED_EXIT_HOST;
2607
2608         switch (exit_code) {
2609         case SVM_EXIT_MSR:
2610                 vmexit = nested_svm_exit_handled_msr(svm);
2611                 break;
2612         case SVM_EXIT_IOIO:
2613                 vmexit = nested_svm_intercept_ioio(svm);
2614                 break;
2615         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2616                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2617                 if (svm->nested.intercept_cr & bit)
2618                         vmexit = NESTED_EXIT_DONE;
2619                 break;
2620         }
2621         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2622                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2623                 if (svm->nested.intercept_dr & bit)
2624                         vmexit = NESTED_EXIT_DONE;
2625                 break;
2626         }
2627         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2628                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2629                 if (svm->nested.intercept_exceptions & excp_bits)
2630                         vmexit = NESTED_EXIT_DONE;
2631                 /* async page fault always cause vmexit */
2632                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2633                          svm->apf_reason != 0)
2634                         vmexit = NESTED_EXIT_DONE;
2635                 break;
2636         }
2637         case SVM_EXIT_ERR: {
2638                 vmexit = NESTED_EXIT_DONE;
2639                 break;
2640         }
2641         default: {
2642                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2643                 if (svm->nested.intercept & exit_bits)
2644                         vmexit = NESTED_EXIT_DONE;
2645         }
2646         }
2647
2648         return vmexit;
2649 }
2650
2651 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2652 {
2653         int vmexit;
2654
2655         vmexit = nested_svm_intercept(svm);
2656
2657         if (vmexit == NESTED_EXIT_DONE)
2658                 nested_svm_vmexit(svm);
2659
2660         return vmexit;
2661 }
2662
2663 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2664 {
2665         struct vmcb_control_area *dst  = &dst_vmcb->control;
2666         struct vmcb_control_area *from = &from_vmcb->control;
2667
2668         dst->intercept_cr         = from->intercept_cr;
2669         dst->intercept_dr         = from->intercept_dr;
2670         dst->intercept_exceptions = from->intercept_exceptions;
2671         dst->intercept            = from->intercept;
2672         dst->iopm_base_pa         = from->iopm_base_pa;
2673         dst->msrpm_base_pa        = from->msrpm_base_pa;
2674         dst->tsc_offset           = from->tsc_offset;
2675         dst->asid                 = from->asid;
2676         dst->tlb_ctl              = from->tlb_ctl;
2677         dst->int_ctl              = from->int_ctl;
2678         dst->int_vector           = from->int_vector;
2679         dst->int_state            = from->int_state;
2680         dst->exit_code            = from->exit_code;
2681         dst->exit_code_hi         = from->exit_code_hi;
2682         dst->exit_info_1          = from->exit_info_1;
2683         dst->exit_info_2          = from->exit_info_2;
2684         dst->exit_int_info        = from->exit_int_info;
2685         dst->exit_int_info_err    = from->exit_int_info_err;
2686         dst->nested_ctl           = from->nested_ctl;
2687         dst->event_inj            = from->event_inj;
2688         dst->event_inj_err        = from->event_inj_err;
2689         dst->nested_cr3           = from->nested_cr3;
2690         dst->lbr_ctl              = from->lbr_ctl;
2691 }
2692
2693 static int nested_svm_vmexit(struct vcpu_svm *svm)
2694 {
2695         struct vmcb *nested_vmcb;
2696         struct vmcb *hsave = svm->nested.hsave;
2697         struct vmcb *vmcb = svm->vmcb;
2698         struct page *page;
2699
2700         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2701                                        vmcb->control.exit_info_1,
2702                                        vmcb->control.exit_info_2,
2703                                        vmcb->control.exit_int_info,
2704                                        vmcb->control.exit_int_info_err,
2705                                        KVM_ISA_SVM);
2706
2707         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2708         if (!nested_vmcb)
2709                 return 1;
2710
2711         /* Exit Guest-Mode */
2712         leave_guest_mode(&svm->vcpu);
2713         svm->nested.vmcb = 0;
2714
2715         /* Give the current vmcb to the guest */
2716         disable_gif(svm);
2717
2718         nested_vmcb->save.es     = vmcb->save.es;
2719         nested_vmcb->save.cs     = vmcb->save.cs;
2720         nested_vmcb->save.ss     = vmcb->save.ss;
2721         nested_vmcb->save.ds     = vmcb->save.ds;
2722         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2723         nested_vmcb->save.idtr   = vmcb->save.idtr;
2724         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2725         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2726         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2727         nested_vmcb->save.cr2    = vmcb->save.cr2;
2728         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2729         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2730         nested_vmcb->save.rip    = vmcb->save.rip;
2731         nested_vmcb->save.rsp    = vmcb->save.rsp;
2732         nested_vmcb->save.rax    = vmcb->save.rax;
2733         nested_vmcb->save.dr7    = vmcb->save.dr7;
2734         nested_vmcb->save.dr6    = vmcb->save.dr6;
2735         nested_vmcb->save.cpl    = vmcb->save.cpl;
2736
2737         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2738         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2739         nested_vmcb->control.int_state         = vmcb->control.int_state;
2740         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2741         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2742         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2743         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2744         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2745         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2746
2747         if (svm->nrips_enabled)
2748                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
2749
2750         /*
2751          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2752          * to make sure that we do not lose injected events. So check event_inj
2753          * here and copy it to exit_int_info if it is valid.
2754          * Exit_int_info and event_inj can't be both valid because the case
2755          * below only happens on a VMRUN instruction intercept which has
2756          * no valid exit_int_info set.
2757          */
2758         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2759                 struct vmcb_control_area *nc = &nested_vmcb->control;
2760
2761                 nc->exit_int_info     = vmcb->control.event_inj;
2762                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2763         }
2764
2765         nested_vmcb->control.tlb_ctl           = 0;
2766         nested_vmcb->control.event_inj         = 0;
2767         nested_vmcb->control.event_inj_err     = 0;
2768
2769         /* We always set V_INTR_MASKING and remember the old value in hflags */
2770         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2771                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2772
2773         /* Restore the original control entries */
2774         copy_vmcb_control_area(vmcb, hsave);
2775
2776         kvm_clear_exception_queue(&svm->vcpu);
2777         kvm_clear_interrupt_queue(&svm->vcpu);
2778
2779         svm->nested.nested_cr3 = 0;
2780
2781         /* Restore selected save entries */
2782         svm->vmcb->save.es = hsave->save.es;
2783         svm->vmcb->save.cs = hsave->save.cs;
2784         svm->vmcb->save.ss = hsave->save.ss;
2785         svm->vmcb->save.ds = hsave->save.ds;
2786         svm->vmcb->save.gdtr = hsave->save.gdtr;
2787         svm->vmcb->save.idtr = hsave->save.idtr;
2788         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2789         svm_set_efer(&svm->vcpu, hsave->save.efer);
2790         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2791         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2792         if (npt_enabled) {
2793                 svm->vmcb->save.cr3 = hsave->save.cr3;
2794                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2795         } else {
2796                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2797         }
2798         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2799         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2800         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2801         svm->vmcb->save.dr7 = 0;
2802         svm->vmcb->save.cpl = 0;
2803         svm->vmcb->control.exit_int_info = 0;
2804
2805         mark_all_dirty(svm->vmcb);
2806
2807         nested_svm_unmap(page);
2808
2809         nested_svm_uninit_mmu_context(&svm->vcpu);
2810         kvm_mmu_reset_context(&svm->vcpu);
2811         kvm_mmu_load(&svm->vcpu);
2812
2813         return 0;
2814 }
2815
2816 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2817 {
2818         /*
2819          * This function merges the msr permission bitmaps of kvm and the
2820          * nested vmcb. It is optimized in that it only merges the parts where
2821          * the kvm msr permission bitmap may contain zero bits
2822          */
2823         int i;
2824
2825         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2826                 return true;
2827
2828         for (i = 0; i < MSRPM_OFFSETS; i++) {
2829                 u32 value, p;
2830                 u64 offset;
2831
2832                 if (msrpm_offsets[i] == 0xffffffff)
2833                         break;
2834
2835                 p      = msrpm_offsets[i];
2836                 offset = svm->nested.vmcb_msrpm + (p * 4);
2837
2838                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2839                         return false;
2840
2841                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2842         }
2843
2844         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2845
2846         return true;
2847 }
2848
2849 static bool nested_vmcb_checks(struct vmcb *vmcb)
2850 {
2851         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2852                 return false;
2853
2854         if (vmcb->control.asid == 0)
2855                 return false;
2856
2857         if (vmcb->control.nested_ctl && !npt_enabled)
2858                 return false;
2859
2860         return true;
2861 }
2862
2863 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2864 {
2865         struct vmcb *nested_vmcb;
2866         struct vmcb *hsave = svm->nested.hsave;
2867         struct vmcb *vmcb = svm->vmcb;
2868         struct page *page;
2869         u64 vmcb_gpa;
2870
2871         vmcb_gpa = svm->vmcb->save.rax;
2872
2873         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2874         if (!nested_vmcb)
2875                 return false;
2876
2877         if (!nested_vmcb_checks(nested_vmcb)) {
2878                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2879                 nested_vmcb->control.exit_code_hi = 0;
2880                 nested_vmcb->control.exit_info_1  = 0;
2881                 nested_vmcb->control.exit_info_2  = 0;
2882
2883                 nested_svm_unmap(page);
2884
2885                 return false;
2886         }
2887
2888         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2889                                nested_vmcb->save.rip,
2890                                nested_vmcb->control.int_ctl,
2891                                nested_vmcb->control.event_inj,
2892                                nested_vmcb->control.nested_ctl);
2893
2894         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2895                                     nested_vmcb->control.intercept_cr >> 16,
2896                                     nested_vmcb->control.intercept_exceptions,
2897                                     nested_vmcb->control.intercept);
2898
2899         /* Clear internal status */
2900         kvm_clear_exception_queue(&svm->vcpu);
2901         kvm_clear_interrupt_queue(&svm->vcpu);
2902
2903         /*
2904          * Save the old vmcb, so we don't need to pick what we save, but can
2905          * restore everything when a VMEXIT occurs
2906          */
2907         hsave->save.es     = vmcb->save.es;
2908         hsave->save.cs     = vmcb->save.cs;
2909         hsave->save.ss     = vmcb->save.ss;
2910         hsave->save.ds     = vmcb->save.ds;
2911         hsave->save.gdtr   = vmcb->save.gdtr;
2912         hsave->save.idtr   = vmcb->save.idtr;
2913         hsave->save.efer   = svm->vcpu.arch.efer;
2914         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2915         hsave->save.cr4    = svm->vcpu.arch.cr4;
2916         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2917         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2918         hsave->save.rsp    = vmcb->save.rsp;
2919         hsave->save.rax    = vmcb->save.rax;
2920         if (npt_enabled)
2921                 hsave->save.cr3    = vmcb->save.cr3;
2922         else
2923                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2924
2925         copy_vmcb_control_area(hsave, vmcb);
2926
2927         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2928                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2929         else
2930                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2931
2932         if (nested_vmcb->control.nested_ctl) {
2933                 kvm_mmu_unload(&svm->vcpu);
2934                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2935                 nested_svm_init_mmu_context(&svm->vcpu);
2936         }
2937
2938         /* Load the nested guest state */
2939         svm->vmcb->save.es = nested_vmcb->save.es;
2940         svm->vmcb->save.cs = nested_vmcb->save.cs;
2941         svm->vmcb->save.ss = nested_vmcb->save.ss;
2942         svm->vmcb->save.ds = nested_vmcb->save.ds;
2943         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2944         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2945         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2946         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2947         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2948         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2949         if (npt_enabled) {
2950                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2951                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2952         } else
2953                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2954
2955         /* Guest paging mode is active - reset mmu */
2956         kvm_mmu_reset_context(&svm->vcpu);
2957
2958         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2959         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2960         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2961         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2962
2963         /* In case we don't even reach vcpu_run, the fields are not updated */
2964         svm->vmcb->save.rax = nested_vmcb->save.rax;
2965         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2966         svm->vmcb->save.rip = nested_vmcb->save.rip;
2967         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2968         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2969         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2970
2971         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2972         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2973
2974         /* cache intercepts */
2975         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2976         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2977         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2978         svm->nested.intercept            = nested_vmcb->control.intercept;
2979
2980         svm_flush_tlb(&svm->vcpu);
2981         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2982         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2983                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2984         else
2985                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2986
2987         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2988                 /* We only want the cr8 intercept bits of the guest */
2989                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2990                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2991         }
2992
2993         /* We don't want to see VMMCALLs from a nested guest */
2994         clr_intercept(svm, INTERCEPT_VMMCALL);
2995
2996         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2997         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2998         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2999         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3000         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3001         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3002
3003         nested_svm_unmap(page);
3004
3005         /* Enter Guest-Mode */
3006         enter_guest_mode(&svm->vcpu);
3007
3008         /*
3009          * Merge guest and host intercepts - must be called  with vcpu in
3010          * guest-mode to take affect here
3011          */
3012         recalc_intercepts(svm);
3013
3014         svm->nested.vmcb = vmcb_gpa;
3015
3016         enable_gif(svm);
3017
3018         mark_all_dirty(svm->vmcb);
3019
3020         return true;
3021 }
3022
3023 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3024 {
3025         to_vmcb->save.fs = from_vmcb->save.fs;
3026         to_vmcb->save.gs = from_vmcb->save.gs;
3027         to_vmcb->save.tr = from_vmcb->save.tr;
3028         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3029         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3030         to_vmcb->save.star = from_vmcb->save.star;
3031         to_vmcb->save.lstar = from_vmcb->save.lstar;
3032         to_vmcb->save.cstar = from_vmcb->save.cstar;
3033         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3034         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3035         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3036         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3037 }
3038
3039 static int vmload_interception(struct vcpu_svm *svm)
3040 {
3041         struct vmcb *nested_vmcb;
3042         struct page *page;
3043
3044         if (nested_svm_check_permissions(svm))
3045                 return 1;
3046
3047         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3048         if (!nested_vmcb)
3049                 return 1;
3050
3051         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3052         skip_emulated_instruction(&svm->vcpu);
3053
3054         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3055         nested_svm_unmap(page);
3056
3057         return 1;
3058 }
3059
3060 static int vmsave_interception(struct vcpu_svm *svm)
3061 {
3062         struct vmcb *nested_vmcb;
3063         struct page *page;
3064
3065         if (nested_svm_check_permissions(svm))
3066                 return 1;
3067
3068         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3069         if (!nested_vmcb)
3070                 return 1;
3071
3072         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3073         skip_emulated_instruction(&svm->vcpu);
3074
3075         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3076         nested_svm_unmap(page);
3077
3078         return 1;
3079 }
3080
3081 static int vmrun_interception(struct vcpu_svm *svm)
3082 {
3083         if (nested_svm_check_permissions(svm))
3084                 return 1;
3085
3086         /* Save rip after vmrun instruction */
3087         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3088
3089         if (!nested_svm_vmrun(svm))
3090                 return 1;
3091
3092         if (!nested_svm_vmrun_msrpm(svm))
3093                 goto failed;
3094
3095         return 1;
3096
3097 failed:
3098
3099         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3100         svm->vmcb->control.exit_code_hi = 0;
3101         svm->vmcb->control.exit_info_1  = 0;
3102         svm->vmcb->control.exit_info_2  = 0;
3103
3104         nested_svm_vmexit(svm);
3105
3106         return 1;
3107 }
3108
3109 static int stgi_interception(struct vcpu_svm *svm)
3110 {
3111         if (nested_svm_check_permissions(svm))
3112                 return 1;
3113
3114         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3115         skip_emulated_instruction(&svm->vcpu);
3116         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3117
3118         enable_gif(svm);
3119
3120         return 1;
3121 }
3122
3123 static int clgi_interception(struct vcpu_svm *svm)
3124 {
3125         if (nested_svm_check_permissions(svm))
3126                 return 1;
3127
3128         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3129         skip_emulated_instruction(&svm->vcpu);
3130
3131         disable_gif(svm);
3132
3133         /* After a CLGI no interrupts should come */
3134         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3135                 svm_clear_vintr(svm);
3136                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3137                 mark_dirty(svm->vmcb, VMCB_INTR);
3138         }
3139
3140         return 1;
3141 }
3142
3143 static int invlpga_interception(struct vcpu_svm *svm)
3144 {
3145         struct kvm_vcpu *vcpu = &svm->vcpu;
3146
3147         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3148                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3149
3150         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3151         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3152
3153         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3154         skip_emulated_instruction(&svm->vcpu);
3155         return 1;
3156 }
3157
3158 static int skinit_interception(struct vcpu_svm *svm)
3159 {
3160         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3161
3162         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3163         return 1;
3164 }
3165
3166 static int wbinvd_interception(struct vcpu_svm *svm)
3167 {
3168         kvm_emulate_wbinvd(&svm->vcpu);
3169         return 1;
3170 }
3171
3172 static int xsetbv_interception(struct vcpu_svm *svm)
3173 {
3174         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3175         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3176
3177         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3178                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3179                 skip_emulated_instruction(&svm->vcpu);
3180         }
3181
3182         return 1;
3183 }
3184
3185 static int task_switch_interception(struct vcpu_svm *svm)
3186 {
3187         u16 tss_selector;
3188         int reason;
3189         int int_type = svm->vmcb->control.exit_int_info &
3190                 SVM_EXITINTINFO_TYPE_MASK;
3191         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3192         uint32_t type =
3193                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3194         uint32_t idt_v =
3195                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3196         bool has_error_code = false;
3197         u32 error_code = 0;
3198
3199         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3200
3201         if (svm->vmcb->control.exit_info_2 &
3202             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3203                 reason = TASK_SWITCH_IRET;
3204         else if (svm->vmcb->control.exit_info_2 &
3205                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3206                 reason = TASK_SWITCH_JMP;
3207         else if (idt_v)
3208                 reason = TASK_SWITCH_GATE;
3209         else
3210                 reason = TASK_SWITCH_CALL;
3211
3212         if (reason == TASK_SWITCH_GATE) {
3213                 switch (type) {
3214                 case SVM_EXITINTINFO_TYPE_NMI:
3215                         svm->vcpu.arch.nmi_injected = false;
3216                         break;
3217                 case SVM_EXITINTINFO_TYPE_EXEPT:
3218                         if (svm->vmcb->control.exit_info_2 &
3219                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3220                                 has_error_code = true;
3221                                 error_code =
3222                                         (u32)svm->vmcb->control.exit_info_2;
3223                         }
3224                         kvm_clear_exception_queue(&svm->vcpu);
3225                         break;
3226                 case SVM_EXITINTINFO_TYPE_INTR:
3227                         kvm_clear_interrupt_queue(&svm->vcpu);
3228                         break;
3229                 default:
3230                         break;
3231                 }
3232         }
3233
3234         if (reason != TASK_SWITCH_GATE ||
3235             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3236             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3237              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3238                 skip_emulated_instruction(&svm->vcpu);
3239
3240         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3241                 int_vec = -1;
3242
3243         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3244                                 has_error_code, error_code) == EMULATE_FAIL) {
3245                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3246                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3247                 svm->vcpu.run->internal.ndata = 0;
3248                 return 0;
3249         }
3250         return 1;
3251 }
3252
3253 static int cpuid_interception(struct vcpu_svm *svm)
3254 {
3255         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3256         kvm_emulate_cpuid(&svm->vcpu);
3257         return 1;
3258 }
3259
3260 static int iret_interception(struct vcpu_svm *svm)
3261 {
3262         ++svm->vcpu.stat.nmi_window_exits;
3263         clr_intercept(svm, INTERCEPT_IRET);
3264         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3265         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3266         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3267         return 1;
3268 }
3269
3270 static int invlpg_interception(struct vcpu_svm *svm)
3271 {
3272         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3273                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3274
3275         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3276         skip_emulated_instruction(&svm->vcpu);
3277         return 1;
3278 }
3279
3280 static int emulate_on_interception(struct vcpu_svm *svm)
3281 {
3282         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3283 }
3284
3285 static int rdpmc_interception(struct vcpu_svm *svm)
3286 {
3287         int err;
3288
3289         if (!static_cpu_has(X86_FEATURE_NRIPS))
3290                 return emulate_on_interception(svm);
3291
3292         err = kvm_rdpmc(&svm->vcpu);
3293         kvm_complete_insn_gp(&svm->vcpu, err);
3294
3295         return 1;
3296 }
3297
3298 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3299                                             unsigned long val)
3300 {
3301         unsigned long cr0 = svm->vcpu.arch.cr0;
3302         bool ret = false;
3303         u64 intercept;
3304
3305         intercept = svm->nested.intercept;
3306
3307         if (!is_guest_mode(&svm->vcpu) ||
3308             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3309                 return false;
3310
3311         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3312         val &= ~SVM_CR0_SELECTIVE_MASK;
3313
3314         if (cr0 ^ val) {
3315                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3316                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3317         }
3318
3319         return ret;
3320 }
3321
3322 #define CR_VALID (1ULL << 63)
3323
3324 static int cr_interception(struct vcpu_svm *svm)
3325 {
3326         int reg, cr;
3327         unsigned long val;
3328         int err;
3329
3330         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3331                 return emulate_on_interception(svm);
3332
3333         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3334                 return emulate_on_interception(svm);
3335
3336         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3337         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3338                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3339         else
3340                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3341
3342         err = 0;
3343         if (cr >= 16) { /* mov to cr */
3344                 cr -= 16;
3345                 val = kvm_register_read(&svm->vcpu, reg);
3346                 switch (cr) {
3347                 case 0:
3348                         if (!check_selective_cr0_intercepted(svm, val))
3349                                 err = kvm_set_cr0(&svm->vcpu, val);
3350                         else
3351                                 return 1;
3352
3353                         break;
3354                 case 3:
3355                         err = kvm_set_cr3(&svm->vcpu, val);
3356                         break;
3357                 case 4:
3358                         err = kvm_set_cr4(&svm->vcpu, val);
3359                         break;
3360                 case 8:
3361                         err = kvm_set_cr8(&svm->vcpu, val);
3362                         break;
3363                 default:
3364                         WARN(1, "unhandled write to CR%d", cr);
3365                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3366                         return 1;
3367                 }
3368         } else { /* mov from cr */
3369                 switch (cr) {
3370                 case 0:
3371                         val = kvm_read_cr0(&svm->vcpu);
3372                         break;
3373                 case 2:
3374                         val = svm->vcpu.arch.cr2;
3375                         break;
3376                 case 3:
3377                         val = kvm_read_cr3(&svm->vcpu);
3378                         break;
3379                 case 4:
3380                         val = kvm_read_cr4(&svm->vcpu);
3381                         break;
3382                 case 8:
3383                         val = kvm_get_cr8(&svm->vcpu);
3384                         break;
3385                 default:
3386                         WARN(1, "unhandled read from CR%d", cr);
3387                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3388                         return 1;
3389                 }
3390                 kvm_register_write(&svm->vcpu, reg, val);
3391         }
3392         kvm_complete_insn_gp(&svm->vcpu, err);
3393
3394         return 1;
3395 }
3396
3397 static int dr_interception(struct vcpu_svm *svm)
3398 {
3399         int reg, dr;
3400         unsigned long val;
3401
3402         if (svm->vcpu.guest_debug == 0) {
3403                 /*
3404                  * No more DR vmexits; force a reload of the debug registers
3405                  * and reenter on this instruction.  The next vmexit will
3406                  * retrieve the full state of the debug registers.
3407                  */
3408                 clr_dr_intercepts(svm);
3409                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3410                 return 1;
3411         }
3412
3413         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3414                 return emulate_on_interception(svm);
3415
3416         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3417         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3418
3419         if (dr >= 16) { /* mov to DRn */
3420                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3421                         return 1;
3422                 val = kvm_register_read(&svm->vcpu, reg);
3423                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3424         } else {
3425                 if (!kvm_require_dr(&svm->vcpu, dr))
3426                         return 1;
3427                 kvm_get_dr(&svm->vcpu, dr, &val);
3428                 kvm_register_write(&svm->vcpu, reg, val);
3429         }
3430
3431         skip_emulated_instruction(&svm->vcpu);
3432
3433         return 1;
3434 }
3435
3436 static int cr8_write_interception(struct vcpu_svm *svm)
3437 {
3438         struct kvm_run *kvm_run = svm->vcpu.run;
3439         int r;
3440
3441         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3442         /* instruction emulation calls kvm_set_cr8() */
3443         r = cr_interception(svm);
3444         if (lapic_in_kernel(&svm->vcpu))
3445                 return r;
3446         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3447                 return r;
3448         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3449         return 0;
3450 }
3451
3452 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3453 {
3454         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3455         return vmcb->control.tsc_offset + host_tsc;
3456 }
3457
3458 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3459 {
3460         struct vcpu_svm *svm = to_svm(vcpu);
3461
3462         switch (msr_info->index) {
3463         case MSR_IA32_TSC: {
3464                 msr_info->data = svm->vmcb->control.tsc_offset +
3465                         kvm_scale_tsc(vcpu, rdtsc());
3466
3467                 break;
3468         }
3469         case MSR_STAR:
3470                 msr_info->data = svm->vmcb->save.star;
3471                 break;
3472 #ifdef CONFIG_X86_64
3473         case MSR_LSTAR:
3474                 msr_info->data = svm->vmcb->save.lstar;
3475                 break;
3476         case MSR_CSTAR:
3477                 msr_info->data = svm->vmcb->save.cstar;
3478                 break;
3479         case MSR_KERNEL_GS_BASE:
3480                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3481                 break;
3482         case MSR_SYSCALL_MASK:
3483                 msr_info->data = svm->vmcb->save.sfmask;
3484                 break;
3485 #endif
3486         case MSR_IA32_SYSENTER_CS:
3487                 msr_info->data = svm->vmcb->save.sysenter_cs;
3488                 break;
3489         case MSR_IA32_SYSENTER_EIP:
3490                 msr_info->data = svm->sysenter_eip;
3491                 break;
3492         case MSR_IA32_SYSENTER_ESP:
3493                 msr_info->data = svm->sysenter_esp;
3494                 break;
3495         case MSR_TSC_AUX:
3496                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3497                         return 1;
3498                 msr_info->data = svm->tsc_aux;
3499                 break;
3500         /*
3501          * Nobody will change the following 5 values in the VMCB so we can
3502          * safely return them on rdmsr. They will always be 0 until LBRV is
3503          * implemented.
3504          */
3505         case MSR_IA32_DEBUGCTLMSR:
3506                 msr_info->data = svm->vmcb->save.dbgctl;
3507                 break;
3508         case MSR_IA32_LASTBRANCHFROMIP:
3509                 msr_info->data = svm->vmcb->save.br_from;
3510                 break;
3511         case MSR_IA32_LASTBRANCHTOIP:
3512                 msr_info->data = svm->vmcb->save.br_to;
3513                 break;
3514         case MSR_IA32_LASTINTFROMIP:
3515                 msr_info->data = svm->vmcb->save.last_excp_from;
3516                 break;
3517         case MSR_IA32_LASTINTTOIP:
3518                 msr_info->data = svm->vmcb->save.last_excp_to;
3519                 break;
3520         case MSR_VM_HSAVE_PA:
3521                 msr_info->data = svm->nested.hsave_msr;
3522                 break;
3523         case MSR_VM_CR:
3524                 msr_info->data = svm->nested.vm_cr_msr;
3525                 break;
3526         case MSR_IA32_UCODE_REV:
3527                 msr_info->data = 0x01000065;
3528                 break;
3529         case MSR_F15H_IC_CFG: {
3530
3531                 int family, model;
3532
3533                 family = guest_cpuid_family(vcpu);
3534                 model  = guest_cpuid_model(vcpu);
3535
3536                 if (family < 0 || model < 0)
3537                         return kvm_get_msr_common(vcpu, msr_info);
3538
3539                 msr_info->data = 0;
3540
3541                 if (family == 0x15 &&
3542                     (model >= 0x2 && model < 0x20))
3543                         msr_info->data = 0x1E;
3544                 }
3545                 break;
3546         default:
3547                 return kvm_get_msr_common(vcpu, msr_info);
3548         }
3549         return 0;
3550 }
3551
3552 static int rdmsr_interception(struct vcpu_svm *svm)
3553 {
3554         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3555         struct msr_data msr_info;
3556
3557         msr_info.index = ecx;
3558         msr_info.host_initiated = false;
3559         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3560                 trace_kvm_msr_read_ex(ecx);
3561                 kvm_inject_gp(&svm->vcpu, 0);
3562         } else {
3563                 trace_kvm_msr_read(ecx, msr_info.data);
3564
3565                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3566                                    msr_info.data & 0xffffffff);
3567                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3568                                    msr_info.data >> 32);
3569                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3570                 skip_emulated_instruction(&svm->vcpu);
3571         }
3572         return 1;
3573 }
3574
3575 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3576 {
3577         struct vcpu_svm *svm = to_svm(vcpu);
3578         int svm_dis, chg_mask;
3579
3580         if (data & ~SVM_VM_CR_VALID_MASK)
3581                 return 1;
3582
3583         chg_mask = SVM_VM_CR_VALID_MASK;
3584
3585         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3586                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3587
3588         svm->nested.vm_cr_msr &= ~chg_mask;
3589         svm->nested.vm_cr_msr |= (data & chg_mask);
3590
3591         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3592
3593         /* check for svm_disable while efer.svme is set */
3594         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3595                 return 1;
3596
3597         return 0;
3598 }
3599
3600 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3601 {
3602         struct vcpu_svm *svm = to_svm(vcpu);
3603
3604         u32 ecx = msr->index;
3605         u64 data = msr->data;
3606         switch (ecx) {
3607         case MSR_IA32_TSC:
3608                 kvm_write_tsc(vcpu, msr);
3609                 break;
3610         case MSR_STAR:
3611                 svm->vmcb->save.star = data;
3612                 break;
3613 #ifdef CONFIG_X86_64
3614         case MSR_LSTAR:
3615                 svm->vmcb->save.lstar = data;
3616                 break;
3617         case MSR_CSTAR:
3618                 svm->vmcb->save.cstar = data;
3619                 break;
3620         case MSR_KERNEL_GS_BASE:
3621                 svm->vmcb->save.kernel_gs_base = data;
3622                 break;
3623         case MSR_SYSCALL_MASK:
3624                 svm->vmcb->save.sfmask = data;
3625                 break;
3626 #endif
3627         case MSR_IA32_SYSENTER_CS:
3628                 svm->vmcb->save.sysenter_cs = data;
3629                 break;
3630         case MSR_IA32_SYSENTER_EIP:
3631                 svm->sysenter_eip = data;
3632                 svm->vmcb->save.sysenter_eip = data;
3633                 break;
3634         case MSR_IA32_SYSENTER_ESP:
3635                 svm->sysenter_esp = data;
3636                 svm->vmcb->save.sysenter_esp = data;
3637                 break;
3638         case MSR_TSC_AUX:
3639                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3640                         return 1;
3641
3642                 /*
3643                  * This is rare, so we update the MSR here instead of using
3644                  * direct_access_msrs.  Doing that would require a rdmsr in
3645                  * svm_vcpu_put.
3646                  */
3647                 svm->tsc_aux = data;
3648                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3649                 break;
3650         case MSR_IA32_DEBUGCTLMSR:
3651                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3652                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3653                                     __func__, data);
3654                         break;
3655                 }
3656                 if (data & DEBUGCTL_RESERVED_BITS)
3657                         return 1;
3658
3659                 svm->vmcb->save.dbgctl = data;
3660                 mark_dirty(svm->vmcb, VMCB_LBR);
3661                 if (data & (1ULL<<0))
3662                         svm_enable_lbrv(svm);
3663                 else
3664                         svm_disable_lbrv(svm);
3665                 break;
3666         case MSR_VM_HSAVE_PA:
3667                 svm->nested.hsave_msr = data;
3668                 break;
3669         case MSR_VM_CR:
3670                 return svm_set_vm_cr(vcpu, data);
3671         case MSR_VM_IGNNE:
3672                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3673                 break;
3674         case MSR_IA32_APICBASE:
3675                 if (kvm_vcpu_apicv_active(vcpu))
3676                         avic_update_vapic_bar(to_svm(vcpu), data);
3677                 /* Follow through */
3678         default:
3679                 return kvm_set_msr_common(vcpu, msr);
3680         }
3681         return 0;
3682 }
3683
3684 static int wrmsr_interception(struct vcpu_svm *svm)
3685 {
3686         struct msr_data msr;
3687         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3688         u64 data = kvm_read_edx_eax(&svm->vcpu);
3689
3690         msr.data = data;
3691         msr.index = ecx;
3692         msr.host_initiated = false;
3693
3694         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3695         if (kvm_set_msr(&svm->vcpu, &msr)) {
3696                 trace_kvm_msr_write_ex(ecx, data);
3697                 kvm_inject_gp(&svm->vcpu, 0);
3698         } else {
3699                 trace_kvm_msr_write(ecx, data);
3700                 skip_emulated_instruction(&svm->vcpu);
3701         }
3702         return 1;
3703 }
3704
3705 static int msr_interception(struct vcpu_svm *svm)
3706 {
3707         if (svm->vmcb->control.exit_info_1)
3708                 return wrmsr_interception(svm);
3709         else
3710                 return rdmsr_interception(svm);
3711 }
3712
3713 static int interrupt_window_interception(struct vcpu_svm *svm)
3714 {
3715         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3716         svm_clear_vintr(svm);
3717         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3718         mark_dirty(svm->vmcb, VMCB_INTR);
3719         ++svm->vcpu.stat.irq_window_exits;
3720         return 1;
3721 }
3722
3723 static int pause_interception(struct vcpu_svm *svm)
3724 {
3725         kvm_vcpu_on_spin(&(svm->vcpu));
3726         return 1;
3727 }
3728
3729 static int nop_interception(struct vcpu_svm *svm)
3730 {
3731         skip_emulated_instruction(&(svm->vcpu));
3732         return 1;
3733 }
3734
3735 static int monitor_interception(struct vcpu_svm *svm)
3736 {
3737         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3738         return nop_interception(svm);
3739 }
3740
3741 static int mwait_interception(struct vcpu_svm *svm)
3742 {
3743         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3744         return nop_interception(svm);
3745 }
3746
3747 enum avic_ipi_failure_cause {
3748         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3749         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3750         AVIC_IPI_FAILURE_INVALID_TARGET,
3751         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3752 };
3753
3754 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3755 {
3756         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3757         u32 icrl = svm->vmcb->control.exit_info_1;
3758         u32 id = svm->vmcb->control.exit_info_2 >> 32;
3759         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3760         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3761
3762         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3763
3764         switch (id) {
3765         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3766                 /*
3767                  * AVIC hardware handles the generation of
3768                  * IPIs when the specified Message Type is Fixed
3769                  * (also known as fixed delivery mode) and
3770                  * the Trigger Mode is edge-triggered. The hardware
3771                  * also supports self and broadcast delivery modes
3772                  * specified via the Destination Shorthand(DSH)
3773                  * field of the ICRL. Logical and physical APIC ID
3774                  * formats are supported. All other IPI types cause
3775                  * a #VMEXIT, which needs to emulated.
3776                  */
3777                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3778                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3779                 break;
3780         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3781                 int i;
3782                 struct kvm_vcpu *vcpu;
3783                 struct kvm *kvm = svm->vcpu.kvm;
3784                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3785
3786                 /*
3787                  * At this point, we expect that the AVIC HW has already
3788                  * set the appropriate IRR bits on the valid target
3789                  * vcpus. So, we just need to kick the appropriate vcpu.
3790                  */
3791                 kvm_for_each_vcpu(i, vcpu, kvm) {
3792                         bool m = kvm_apic_match_dest(vcpu, apic,
3793                                                      icrl & KVM_APIC_SHORT_MASK,
3794                                                      GET_APIC_DEST_FIELD(icrh),
3795                                                      icrl & KVM_APIC_DEST_MASK);
3796
3797                         if (m && !avic_vcpu_is_running(vcpu))
3798                                 kvm_vcpu_wake_up(vcpu);
3799                 }
3800                 break;
3801         }
3802         case AVIC_IPI_FAILURE_INVALID_TARGET:
3803                 break;
3804         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3805                 WARN_ONCE(1, "Invalid backing page\n");
3806                 break;
3807         default:
3808                 pr_err("Unknown IPI interception\n");
3809         }
3810
3811         return 1;
3812 }
3813
3814 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3815 {
3816         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3817         int index;
3818         u32 *logical_apic_id_table;
3819         int dlid = GET_APIC_LOGICAL_ID(ldr);
3820
3821         if (!dlid)
3822                 return NULL;
3823
3824         if (flat) { /* flat */
3825                 index = ffs(dlid) - 1;
3826                 if (index > 7)
3827                         return NULL;
3828         } else { /* cluster */
3829                 int cluster = (dlid & 0xf0) >> 4;
3830                 int apic = ffs(dlid & 0x0f) - 1;
3831
3832                 if ((apic < 0) || (apic > 7) ||
3833                     (cluster >= 0xf))
3834                         return NULL;
3835                 index = (cluster << 2) + apic;
3836         }
3837
3838         logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3839
3840         return &logical_apic_id_table[index];
3841 }
3842
3843 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3844                           bool valid)
3845 {
3846         bool flat;
3847         u32 *entry, new_entry;
3848
3849         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3850         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3851         if (!entry)
3852                 return -EINVAL;
3853
3854         new_entry = READ_ONCE(*entry);
3855         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3856         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3857         if (valid)
3858                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3859         else
3860                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3861         WRITE_ONCE(*entry, new_entry);
3862
3863         return 0;
3864 }
3865
3866 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3867 {
3868         int ret;
3869         struct vcpu_svm *svm = to_svm(vcpu);
3870         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3871
3872         if (!ldr)
3873                 return 1;
3874
3875         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3876         if (ret && svm->ldr_reg) {
3877                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3878                 svm->ldr_reg = 0;
3879         } else {
3880                 svm->ldr_reg = ldr;
3881         }
3882         return ret;
3883 }
3884
3885 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3886 {
3887         u64 *old, *new;
3888         struct vcpu_svm *svm = to_svm(vcpu);
3889         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3890         u32 id = (apic_id_reg >> 24) & 0xff;
3891
3892         if (vcpu->vcpu_id == id)
3893                 return 0;
3894
3895         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3896         new = avic_get_physical_id_entry(vcpu, id);
3897         if (!new || !old)
3898                 return 1;
3899
3900         /* We need to move physical_id_entry to new offset */
3901         *new = *old;
3902         *old = 0ULL;
3903         to_svm(vcpu)->avic_physical_id_cache = new;
3904
3905         /*
3906          * Also update the guest physical APIC ID in the logical
3907          * APIC ID table entry if already setup the LDR.
3908          */
3909         if (svm->ldr_reg)
3910                 avic_handle_ldr_update(vcpu);
3911
3912         return 0;
3913 }
3914
3915 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3916 {
3917         struct vcpu_svm *svm = to_svm(vcpu);
3918         struct kvm_arch *vm_data = &vcpu->kvm->arch;
3919         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3920         u32 mod = (dfr >> 28) & 0xf;
3921
3922         /*
3923          * We assume that all local APICs are using the same type.
3924          * If this changes, we need to flush the AVIC logical
3925          * APID id table.
3926          */
3927         if (vm_data->ldr_mode == mod)
3928                 return 0;
3929
3930         clear_page(page_address(vm_data->avic_logical_id_table_page));
3931         vm_data->ldr_mode = mod;
3932
3933         if (svm->ldr_reg)
3934                 avic_handle_ldr_update(vcpu);
3935         return 0;
3936 }
3937
3938 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3939 {
3940         struct kvm_lapic *apic = svm->vcpu.arch.apic;
3941         u32 offset = svm->vmcb->control.exit_info_1 &
3942                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3943
3944         switch (offset) {
3945         case APIC_ID:
3946                 if (avic_handle_apic_id_update(&svm->vcpu))
3947                         return 0;
3948                 break;
3949         case APIC_LDR:
3950                 if (avic_handle_ldr_update(&svm->vcpu))
3951                         return 0;
3952                 break;
3953         case APIC_DFR:
3954                 avic_handle_dfr_update(&svm->vcpu);
3955                 break;
3956         default:
3957                 break;
3958         }
3959
3960         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3961
3962         return 1;
3963 }
3964
3965 static bool is_avic_unaccelerated_access_trap(u32 offset)
3966 {
3967         bool ret = false;
3968
3969         switch (offset) {
3970         case APIC_ID:
3971         case APIC_EOI:
3972         case APIC_RRR:
3973         case APIC_LDR:
3974         case APIC_DFR:
3975         case APIC_SPIV:
3976         case APIC_ESR:
3977         case APIC_ICR:
3978         case APIC_LVTT:
3979         case APIC_LVTTHMR:
3980         case APIC_LVTPC:
3981         case APIC_LVT0:
3982         case APIC_LVT1:
3983         case APIC_LVTERR:
3984         case APIC_TMICT:
3985         case APIC_TDCR:
3986                 ret = true;
3987                 break;
3988         default:
3989                 break;
3990         }
3991         return ret;
3992 }
3993
3994 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3995 {
3996         int ret = 0;
3997         u32 offset = svm->vmcb->control.exit_info_1 &
3998                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3999         u32 vector = svm->vmcb->control.exit_info_2 &
4000                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4001         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4002                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4003         bool trap = is_avic_unaccelerated_access_trap(offset);
4004
4005         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4006                                             trap, write, vector);
4007         if (trap) {
4008                 /* Handling Trap */
4009                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4010                 ret = avic_unaccel_trap_write(svm);
4011         } else {
4012                 /* Handling Fault */
4013                 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4014         }
4015
4016         return ret;
4017 }
4018
4019 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4020         [SVM_EXIT_READ_CR0]                     = cr_interception,
4021         [SVM_EXIT_READ_CR3]                     = cr_interception,
4022         [SVM_EXIT_READ_CR4]                     = cr_interception,
4023         [SVM_EXIT_READ_CR8]                     = cr_interception,
4024         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4025         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4026         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4027         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4028         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4029         [SVM_EXIT_READ_DR0]                     = dr_interception,
4030         [SVM_EXIT_READ_DR1]                     = dr_interception,
4031         [SVM_EXIT_READ_DR2]                     = dr_interception,
4032         [SVM_EXIT_READ_DR3]                     = dr_interception,
4033         [SVM_EXIT_READ_DR4]                     = dr_interception,
4034         [SVM_EXIT_READ_DR5]                     = dr_interception,
4035         [SVM_EXIT_READ_DR6]                     = dr_interception,
4036         [SVM_EXIT_READ_DR7]                     = dr_interception,
4037         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4038         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4039         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4040         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4041         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4042         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4043         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4044         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4045         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4046         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4047         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4048         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4049         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
4050         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4051         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4052         [SVM_EXIT_INTR]                         = intr_interception,
4053         [SVM_EXIT_NMI]                          = nmi_interception,
4054         [SVM_EXIT_SMI]                          = nop_on_interception,
4055         [SVM_EXIT_INIT]                         = nop_on_interception,
4056         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4057         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4058         [SVM_EXIT_CPUID]                        = cpuid_interception,
4059         [SVM_EXIT_IRET]                         = iret_interception,
4060         [SVM_EXIT_INVD]                         = emulate_on_interception,
4061         [SVM_EXIT_PAUSE]                        = pause_interception,
4062         [SVM_EXIT_HLT]                          = halt_interception,
4063         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4064         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4065         [SVM_EXIT_IOIO]                         = io_interception,
4066         [SVM_EXIT_MSR]                          = msr_interception,
4067         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4068         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4069         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4070         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4071         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4072         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4073         [SVM_EXIT_STGI]                         = stgi_interception,
4074         [SVM_EXIT_CLGI]                         = clgi_interception,
4075         [SVM_EXIT_SKINIT]                       = skinit_interception,
4076         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4077         [SVM_EXIT_MONITOR]                      = monitor_interception,
4078         [SVM_EXIT_MWAIT]                        = mwait_interception,
4079         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4080         [SVM_EXIT_NPF]                          = pf_interception,
4081         [SVM_EXIT_RSM]                          = emulate_on_interception,
4082         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4083         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4084 };
4085
4086 static void dump_vmcb(struct kvm_vcpu *vcpu)
4087 {
4088         struct vcpu_svm *svm = to_svm(vcpu);
4089         struct vmcb_control_area *control = &svm->vmcb->control;
4090         struct vmcb_save_area *save = &svm->vmcb->save;
4091
4092         pr_err("VMCB Control Area:\n");
4093         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4094         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4095         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4096         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4097         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4098         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4099         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4100         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4101         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4102         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4103         pr_err("%-20s%d\n", "asid:", control->asid);
4104         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4105         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4106         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4107         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4108         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4109         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4110         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4111         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4112         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4113         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4114         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4115         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4116         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4117         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4118         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4119         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4120         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4121         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4122         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4123         pr_err("VMCB State Save Area:\n");
4124         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4125                "es:",
4126                save->es.selector, save->es.attrib,
4127                save->es.limit, save->es.base);
4128         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4129                "cs:",
4130                save->cs.selector, save->cs.attrib,
4131                save->cs.limit, save->cs.base);
4132         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4133                "ss:",
4134                save->ss.selector, save->ss.attrib,
4135                save->ss.limit, save->ss.base);
4136         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4137                "ds:",
4138                save->ds.selector, save->ds.attrib,
4139                save->ds.limit, save->ds.base);
4140         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4141                "fs:",
4142                save->fs.selector, save->fs.attrib,
4143                save->fs.limit, save->fs.base);
4144         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4145                "gs:",
4146                save->gs.selector, save->gs.attrib,
4147                save->gs.limit, save->gs.base);
4148         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4149                "gdtr:",
4150                save->gdtr.selector, save->gdtr.attrib,
4151                save->gdtr.limit, save->gdtr.base);
4152         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4153                "ldtr:",
4154                save->ldtr.selector, save->ldtr.attrib,
4155                save->ldtr.limit, save->ldtr.base);
4156         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4157                "idtr:",
4158                save->idtr.selector, save->idtr.attrib,
4159                save->idtr.limit, save->idtr.base);
4160         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4161                "tr:",
4162                save->tr.selector, save->tr.attrib,
4163                save->tr.limit, save->tr.base);
4164         pr_err("cpl:            %d                efer:         %016llx\n",
4165                 save->cpl, save->efer);
4166         pr_err("%-15s %016llx %-13s %016llx\n",
4167                "cr0:", save->cr0, "cr2:", save->cr2);
4168         pr_err("%-15s %016llx %-13s %016llx\n",
4169                "cr3:", save->cr3, "cr4:", save->cr4);
4170         pr_err("%-15s %016llx %-13s %016llx\n",
4171                "dr6:", save->dr6, "dr7:", save->dr7);
4172         pr_err("%-15s %016llx %-13s %016llx\n",
4173                "rip:", save->rip, "rflags:", save->rflags);
4174         pr_err("%-15s %016llx %-13s %016llx\n",
4175                "rsp:", save->rsp, "rax:", save->rax);
4176         pr_err("%-15s %016llx %-13s %016llx\n",
4177                "star:", save->star, "lstar:", save->lstar);
4178         pr_err("%-15s %016llx %-13s %016llx\n",
4179                "cstar:", save->cstar, "sfmask:", save->sfmask);
4180         pr_err("%-15s %016llx %-13s %016llx\n",
4181                "kernel_gs_base:", save->kernel_gs_base,
4182                "sysenter_cs:", save->sysenter_cs);
4183         pr_err("%-15s %016llx %-13s %016llx\n",
4184                "sysenter_esp:", save->sysenter_esp,
4185                "sysenter_eip:", save->sysenter_eip);
4186         pr_err("%-15s %016llx %-13s %016llx\n",
4187                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4188         pr_err("%-15s %016llx %-13s %016llx\n",
4189                "br_from:", save->br_from, "br_to:", save->br_to);
4190         pr_err("%-15s %016llx %-13s %016llx\n",
4191                "excp_from:", save->last_excp_from,
4192                "excp_to:", save->last_excp_to);
4193 }
4194
4195 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4196 {
4197         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4198
4199         *info1 = control->exit_info_1;
4200         *info2 = control->exit_info_2;
4201 }
4202
4203 static int handle_exit(struct kvm_vcpu *vcpu)
4204 {
4205         struct vcpu_svm *svm = to_svm(vcpu);
4206         struct kvm_run *kvm_run = vcpu->run;
4207         u32 exit_code = svm->vmcb->control.exit_code;
4208
4209         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4210
4211         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4212                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4213         if (npt_enabled)
4214                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4215
4216         if (unlikely(svm->nested.exit_required)) {
4217                 nested_svm_vmexit(svm);
4218                 svm->nested.exit_required = false;
4219
4220                 return 1;
4221         }
4222
4223         if (is_guest_mode(vcpu)) {
4224                 int vmexit;
4225
4226                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4227                                         svm->vmcb->control.exit_info_1,
4228                                         svm->vmcb->control.exit_info_2,
4229                                         svm->vmcb->control.exit_int_info,
4230                                         svm->vmcb->control.exit_int_info_err,
4231                                         KVM_ISA_SVM);
4232
4233                 vmexit = nested_svm_exit_special(svm);
4234
4235                 if (vmexit == NESTED_EXIT_CONTINUE)
4236                         vmexit = nested_svm_exit_handled(svm);
4237
4238                 if (vmexit == NESTED_EXIT_DONE)
4239                         return 1;
4240         }
4241
4242         svm_complete_interrupts(svm);
4243
4244         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4245                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4246                 kvm_run->fail_entry.hardware_entry_failure_reason
4247                         = svm->vmcb->control.exit_code;
4248                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4249                 dump_vmcb(vcpu);
4250                 return 0;
4251         }
4252
4253         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4254             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4255             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4256             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4257                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4258                        "exit_code 0x%x\n",
4259                        __func__, svm->vmcb->control.exit_int_info,
4260                        exit_code);
4261
4262         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4263             || !svm_exit_handlers[exit_code]) {
4264                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4265                 kvm_queue_exception(vcpu, UD_VECTOR);
4266                 return 1;
4267         }
4268
4269         return svm_exit_handlers[exit_code](svm);
4270 }
4271
4272 static void reload_tss(struct kvm_vcpu *vcpu)
4273 {
4274         int cpu = raw_smp_processor_id();
4275
4276         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4277         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4278         load_TR_desc();
4279 }
4280
4281 static void pre_svm_run(struct vcpu_svm *svm)
4282 {
4283         int cpu = raw_smp_processor_id();
4284
4285         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4286
4287         /* FIXME: handle wraparound of asid_generation */
4288         if (svm->asid_generation != sd->asid_generation)
4289                 new_asid(svm, sd);
4290 }
4291
4292 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4293 {
4294         struct vcpu_svm *svm = to_svm(vcpu);
4295
4296         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4297         vcpu->arch.hflags |= HF_NMI_MASK;
4298         set_intercept(svm, INTERCEPT_IRET);
4299         ++vcpu->stat.nmi_injections;
4300 }
4301
4302 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4303 {
4304         struct vmcb_control_area *control;
4305
4306         /* The following fields are ignored when AVIC is enabled */
4307         control = &svm->vmcb->control;
4308         control->int_vector = irq;
4309         control->int_ctl &= ~V_INTR_PRIO_MASK;
4310         control->int_ctl |= V_IRQ_MASK |
4311                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4312         mark_dirty(svm->vmcb, VMCB_INTR);
4313 }
4314
4315 static void svm_set_irq(struct kvm_vcpu *vcpu)
4316 {
4317         struct vcpu_svm *svm = to_svm(vcpu);
4318
4319         BUG_ON(!(gif_set(svm)));
4320
4321         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4322         ++vcpu->stat.irq_injections;
4323
4324         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4325                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4326 }
4327
4328 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4329 {
4330         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4331 }
4332
4333 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4334 {
4335         struct vcpu_svm *svm = to_svm(vcpu);
4336
4337         if (svm_nested_virtualize_tpr(vcpu) ||
4338             kvm_vcpu_apicv_active(vcpu))
4339                 return;
4340
4341         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4342
4343         if (irr == -1)
4344                 return;
4345
4346         if (tpr >= irr)
4347                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4348 }
4349
4350 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4351 {
4352         return;
4353 }
4354
4355 static bool svm_get_enable_apicv(void)
4356 {
4357         return avic;
4358 }
4359
4360 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4361 {
4362 }
4363
4364 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4365 {
4366 }
4367
4368 /* Note: Currently only used by Hyper-V. */
4369 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4370 {
4371         struct vcpu_svm *svm = to_svm(vcpu);
4372         struct vmcb *vmcb = svm->vmcb;
4373
4374         if (!avic)
4375                 return;
4376
4377         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4378         mark_dirty(vmcb, VMCB_INTR);
4379 }
4380
4381 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4382 {
4383         return;
4384 }
4385
4386 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4387 {
4388         return;
4389 }
4390
4391 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4392 {
4393         kvm_lapic_set_irr(vec, vcpu->arch.apic);
4394         smp_mb__after_atomic();
4395
4396         if (avic_vcpu_is_running(vcpu))
4397                 wrmsrl(SVM_AVIC_DOORBELL,
4398                        kvm_cpu_get_apicid(vcpu->cpu));
4399         else
4400                 kvm_vcpu_wake_up(vcpu);
4401 }
4402
4403 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4404 {
4405         unsigned long flags;
4406         struct amd_svm_iommu_ir *cur;
4407
4408         spin_lock_irqsave(&svm->ir_list_lock, flags);
4409         list_for_each_entry(cur, &svm->ir_list, node) {
4410                 if (cur->data != pi->ir_data)
4411                         continue;
4412                 list_del(&cur->node);
4413                 kfree(cur);
4414                 break;
4415         }
4416         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4417 }
4418
4419 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4420 {
4421         int ret = 0;
4422         unsigned long flags;
4423         struct amd_svm_iommu_ir *ir;
4424
4425         /**
4426          * In some cases, the existing irte is updaed and re-set,
4427          * so we need to check here if it's already been * added
4428          * to the ir_list.
4429          */
4430         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4431                 struct kvm *kvm = svm->vcpu.kvm;
4432                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4433                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4434                 struct vcpu_svm *prev_svm;
4435
4436                 if (!prev_vcpu) {
4437                         ret = -EINVAL;
4438                         goto out;
4439                 }
4440
4441                 prev_svm = to_svm(prev_vcpu);
4442                 svm_ir_list_del(prev_svm, pi);
4443         }
4444
4445         /**
4446          * Allocating new amd_iommu_pi_data, which will get
4447          * add to the per-vcpu ir_list.
4448          */
4449         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4450         if (!ir) {
4451                 ret = -ENOMEM;
4452                 goto out;
4453         }
4454         ir->data = pi->ir_data;
4455
4456         spin_lock_irqsave(&svm->ir_list_lock, flags);
4457         list_add(&ir->node, &svm->ir_list);
4458         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4459 out:
4460         return ret;
4461 }
4462
4463 /**
4464  * Note:
4465  * The HW cannot support posting multicast/broadcast
4466  * interrupts to a vCPU. So, we still use legacy interrupt
4467  * remapping for these kind of interrupts.
4468  *
4469  * For lowest-priority interrupts, we only support
4470  * those with single CPU as the destination, e.g. user
4471  * configures the interrupts via /proc/irq or uses
4472  * irqbalance to make the interrupts single-CPU.
4473  */
4474 static int
4475 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4476                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4477 {
4478         struct kvm_lapic_irq irq;
4479         struct kvm_vcpu *vcpu = NULL;
4480
4481         kvm_set_msi_irq(kvm, e, &irq);
4482
4483         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4484                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4485                          __func__, irq.vector);
4486                 return -1;
4487         }
4488
4489         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4490                  irq.vector);
4491         *svm = to_svm(vcpu);
4492         vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4493         vcpu_info->vector = irq.vector;
4494
4495         return 0;
4496 }
4497
4498 /*
4499  * svm_update_pi_irte - set IRTE for Posted-Interrupts
4500  *
4501  * @kvm: kvm
4502  * @host_irq: host irq of the interrupt
4503  * @guest_irq: gsi of the interrupt
4504  * @set: set or unset PI
4505  * returns 0 on success, < 0 on failure
4506  */
4507 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4508                               uint32_t guest_irq, bool set)
4509 {
4510         struct kvm_kernel_irq_routing_entry *e;
4511         struct kvm_irq_routing_table *irq_rt;
4512         int idx, ret = -EINVAL;
4513
4514         if (!kvm_arch_has_assigned_device(kvm) ||
4515             !irq_remapping_cap(IRQ_POSTING_CAP))
4516                 return 0;
4517
4518         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4519                  __func__, host_irq, guest_irq, set);
4520
4521         idx = srcu_read_lock(&kvm->irq_srcu);
4522         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4523         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4524
4525         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4526                 struct vcpu_data vcpu_info;
4527                 struct vcpu_svm *svm = NULL;
4528
4529                 if (e->type != KVM_IRQ_ROUTING_MSI)
4530                         continue;
4531
4532                 /**
4533                  * Here, we setup with legacy mode in the following cases:
4534                  * 1. When cannot target interrupt to a specific vcpu.
4535                  * 2. Unsetting posted interrupt.
4536                  * 3. APIC virtialization is disabled for the vcpu.
4537                  */
4538                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4539                     kvm_vcpu_apicv_active(&svm->vcpu)) {
4540                         struct amd_iommu_pi_data pi;
4541
4542                         /* Try to enable guest_mode in IRTE */
4543                         pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4544                         pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4545                                                      svm->vcpu.vcpu_id);
4546                         pi.is_guest_mode = true;
4547                         pi.vcpu_data = &vcpu_info;
4548                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4549
4550                         /**
4551                          * Here, we successfully setting up vcpu affinity in
4552                          * IOMMU guest mode. Now, we need to store the posted
4553                          * interrupt information in a per-vcpu ir_list so that
4554                          * we can reference to them directly when we update vcpu
4555                          * scheduling information in IOMMU irte.
4556                          */
4557                         if (!ret && pi.is_guest_mode)
4558                                 svm_ir_list_add(svm, &pi);
4559                 } else {
4560                         /* Use legacy mode in IRTE */
4561                         struct amd_iommu_pi_data pi;
4562
4563                         /**
4564                          * Here, pi is used to:
4565                          * - Tell IOMMU to use legacy mode for this interrupt.
4566                          * - Retrieve ga_tag of prior interrupt remapping data.
4567                          */
4568                         pi.is_guest_mode = false;
4569                         ret = irq_set_vcpu_affinity(host_irq, &pi);
4570
4571                         /**
4572                          * Check if the posted interrupt was previously
4573                          * setup with the guest_mode by checking if the ga_tag
4574                          * was cached. If so, we need to clean up the per-vcpu
4575                          * ir_list.
4576                          */
4577                         if (!ret && pi.prev_ga_tag) {
4578                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4579                                 struct kvm_vcpu *vcpu;
4580
4581                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
4582                                 if (vcpu)
4583                                         svm_ir_list_del(to_svm(vcpu), &pi);
4584                         }
4585                 }
4586
4587                 if (!ret && svm) {
4588                         trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4589                                                  host_irq, e->gsi,
4590                                                  vcpu_info.vector,
4591                                                  vcpu_info.pi_desc_addr, set);
4592                 }
4593
4594                 if (ret < 0) {
4595                         pr_err("%s: failed to update PI IRTE\n", __func__);
4596                         goto out;
4597                 }
4598         }
4599
4600         ret = 0;
4601 out:
4602         srcu_read_unlock(&kvm->irq_srcu, idx);
4603         return ret;
4604 }
4605
4606 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4607 {
4608         struct vcpu_svm *svm = to_svm(vcpu);
4609         struct vmcb *vmcb = svm->vmcb;
4610         int ret;
4611         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4612               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4613         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4614
4615         return ret;
4616 }
4617
4618 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4619 {
4620         struct vcpu_svm *svm = to_svm(vcpu);
4621
4622         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4623 }
4624
4625 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4626 {
4627         struct vcpu_svm *svm = to_svm(vcpu);
4628
4629         if (masked) {
4630                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4631                 set_intercept(svm, INTERCEPT_IRET);
4632         } else {
4633                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4634                 clr_intercept(svm, INTERCEPT_IRET);
4635         }
4636 }
4637
4638 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4639 {
4640         struct vcpu_svm *svm = to_svm(vcpu);
4641         struct vmcb *vmcb = svm->vmcb;
4642         int ret;
4643
4644         if (!gif_set(svm) ||
4645              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4646                 return 0;
4647
4648         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4649
4650         if (is_guest_mode(vcpu))
4651                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4652
4653         return ret;
4654 }
4655
4656 static void enable_irq_window(struct kvm_vcpu *vcpu)
4657 {
4658         struct vcpu_svm *svm = to_svm(vcpu);
4659
4660         if (kvm_vcpu_apicv_active(vcpu))
4661                 return;
4662
4663         /*
4664          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4665          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
4666          * get that intercept, this function will be called again though and
4667          * we'll get the vintr intercept.
4668          */
4669         if (gif_set(svm) && nested_svm_intr(svm)) {
4670                 svm_set_vintr(svm);
4671                 svm_inject_irq(svm, 0x0);
4672         }
4673 }
4674
4675 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4676 {
4677         struct vcpu_svm *svm = to_svm(vcpu);
4678
4679         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4680             == HF_NMI_MASK)
4681                 return; /* IRET will cause a vm exit */
4682
4683         /*
4684          * Something prevents NMI from been injected. Single step over possible
4685          * problem (IRET or exception injection or interrupt shadow)
4686          */
4687         svm->nmi_singlestep = true;
4688         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4689 }
4690
4691 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4692 {
4693         return 0;
4694 }
4695
4696 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4697 {
4698         struct vcpu_svm *svm = to_svm(vcpu);
4699
4700         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4701                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4702         else
4703                 svm->asid_generation--;
4704 }
4705
4706 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4707 {
4708 }
4709
4710 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4711 {
4712         struct vcpu_svm *svm = to_svm(vcpu);
4713
4714         if (svm_nested_virtualize_tpr(vcpu))
4715                 return;
4716
4717         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4718                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4719                 kvm_set_cr8(vcpu, cr8);
4720         }
4721 }
4722
4723 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4724 {
4725         struct vcpu_svm *svm = to_svm(vcpu);
4726         u64 cr8;
4727
4728         if (svm_nested_virtualize_tpr(vcpu) ||
4729             kvm_vcpu_apicv_active(vcpu))
4730                 return;
4731
4732         cr8 = kvm_get_cr8(vcpu);
4733         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4734         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4735 }
4736
4737 static void svm_complete_interrupts(struct vcpu_svm *svm)
4738 {
4739         u8 vector;
4740         int type;
4741         u32 exitintinfo = svm->vmcb->control.exit_int_info;
4742         unsigned int3_injected = svm->int3_injected;
4743
4744         svm->int3_injected = 0;
4745
4746         /*
4747          * If we've made progress since setting HF_IRET_MASK, we've
4748          * executed an IRET and can allow NMI injection.
4749          */
4750         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4751             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4752                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4753                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4754         }
4755
4756         svm->vcpu.arch.nmi_injected = false;
4757         kvm_clear_exception_queue(&svm->vcpu);
4758         kvm_clear_interrupt_queue(&svm->vcpu);
4759
4760         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4761                 return;
4762
4763         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4764
4765         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4766         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4767
4768         switch (type) {
4769         case SVM_EXITINTINFO_TYPE_NMI:
4770                 svm->vcpu.arch.nmi_injected = true;
4771                 break;
4772         case SVM_EXITINTINFO_TYPE_EXEPT:
4773                 /*
4774                  * In case of software exceptions, do not reinject the vector,
4775                  * but re-execute the instruction instead. Rewind RIP first
4776                  * if we emulated INT3 before.
4777                  */
4778                 if (kvm_exception_is_soft(vector)) {
4779                         if (vector == BP_VECTOR && int3_injected &&
4780                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4781                                 kvm_rip_write(&svm->vcpu,
4782                                               kvm_rip_read(&svm->vcpu) -
4783                                               int3_injected);
4784                         break;
4785                 }
4786                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4787                         u32 err = svm->vmcb->control.exit_int_info_err;
4788                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
4789
4790                 } else
4791                         kvm_requeue_exception(&svm->vcpu, vector);
4792                 break;
4793         case SVM_EXITINTINFO_TYPE_INTR:
4794                 kvm_queue_interrupt(&svm->vcpu, vector, false);
4795                 break;
4796         default:
4797                 break;
4798         }
4799 }
4800
4801 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4802 {
4803         struct vcpu_svm *svm = to_svm(vcpu);
4804         struct vmcb_control_area *control = &svm->vmcb->control;
4805
4806         control->exit_int_info = control->event_inj;
4807         control->exit_int_info_err = control->event_inj_err;
4808         control->event_inj = 0;
4809         svm_complete_interrupts(svm);
4810 }
4811
4812 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4813 {
4814         struct vcpu_svm *svm = to_svm(vcpu);
4815
4816         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4817         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4818         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4819
4820         /*
4821          * A vmexit emulation is required before the vcpu can be executed
4822          * again.
4823          */
4824         if (unlikely(svm->nested.exit_required))
4825                 return;
4826
4827         pre_svm_run(svm);
4828
4829         sync_lapic_to_cr8(vcpu);
4830
4831         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4832
4833         clgi();
4834
4835         local_irq_enable();
4836
4837         asm volatile (
4838                 "push %%" _ASM_BP "; \n\t"
4839                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4840                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4841                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4842                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4843                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4844                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4845 #ifdef CONFIG_X86_64
4846                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4847                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4848                 "mov %c[r10](%[svm]), %%r10 \n\t"
4849                 "mov %c[r11](%[svm]), %%r11 \n\t"
4850                 "mov %c[r12](%[svm]), %%r12 \n\t"
4851                 "mov %c[r13](%[svm]), %%r13 \n\t"
4852                 "mov %c[r14](%[svm]), %%r14 \n\t"
4853                 "mov %c[r15](%[svm]), %%r15 \n\t"
4854 #endif
4855
4856                 /* Enter guest mode */
4857                 "push %%" _ASM_AX " \n\t"
4858                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4859                 __ex(SVM_VMLOAD) "\n\t"
4860                 __ex(SVM_VMRUN) "\n\t"
4861                 __ex(SVM_VMSAVE) "\n\t"
4862                 "pop %%" _ASM_AX " \n\t"
4863
4864                 /* Save guest registers, load host registers */
4865                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4866                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4867                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4868                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4869                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4870                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4871 #ifdef CONFIG_X86_64
4872                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4873                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4874                 "mov %%r10, %c[r10](%[svm]) \n\t"
4875                 "mov %%r11, %c[r11](%[svm]) \n\t"
4876                 "mov %%r12, %c[r12](%[svm]) \n\t"
4877                 "mov %%r13, %c[r13](%[svm]) \n\t"
4878                 "mov %%r14, %c[r14](%[svm]) \n\t"
4879                 "mov %%r15, %c[r15](%[svm]) \n\t"
4880 #endif
4881                 "pop %%" _ASM_BP
4882                 :
4883                 : [svm]"a"(svm),
4884                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4885                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4886                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4887                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4888                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4889                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4890                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4891 #ifdef CONFIG_X86_64
4892                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4893                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4894                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4895                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4896                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4897                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4898                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4899                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4900 #endif
4901                 : "cc", "memory"
4902 #ifdef CONFIG_X86_64
4903                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4904                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4905 #else
4906                 , "ebx", "ecx", "edx", "esi", "edi"
4907 #endif
4908                 );
4909
4910 #ifdef CONFIG_X86_64
4911         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4912 #else
4913         loadsegment(fs, svm->host.fs);
4914 #ifndef CONFIG_X86_32_LAZY_GS
4915         loadsegment(gs, svm->host.gs);
4916 #endif
4917 #endif
4918
4919         reload_tss(vcpu);
4920
4921         local_irq_disable();
4922
4923         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4924         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4925         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4926         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4927
4928         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4929                 kvm_before_handle_nmi(&svm->vcpu);
4930
4931         stgi();
4932
4933         /* Any pending NMI will happen here */
4934
4935         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4936                 kvm_after_handle_nmi(&svm->vcpu);
4937
4938         sync_cr8_to_lapic(vcpu);
4939
4940         svm->next_rip = 0;
4941
4942         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4943
4944         /* if exit due to PF check for async PF */
4945         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4946                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4947
4948         if (npt_enabled) {
4949                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4950                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4951         }
4952
4953         /*
4954          * We need to handle MC intercepts here before the vcpu has a chance to
4955          * change the physical cpu
4956          */
4957         if (unlikely(svm->vmcb->control.exit_code ==
4958                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4959                 svm_handle_mce(svm);
4960
4961         mark_all_clean(svm->vmcb);
4962 }
4963
4964 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4965 {
4966         struct vcpu_svm *svm = to_svm(vcpu);
4967
4968         svm->vmcb->save.cr3 = root;
4969         mark_dirty(svm->vmcb, VMCB_CR);
4970         svm_flush_tlb(vcpu);
4971 }
4972
4973 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4974 {
4975         struct vcpu_svm *svm = to_svm(vcpu);
4976
4977         svm->vmcb->control.nested_cr3 = root;
4978         mark_dirty(svm->vmcb, VMCB_NPT);
4979
4980         /* Also sync guest cr3 here in case we live migrate */
4981         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4982         mark_dirty(svm->vmcb, VMCB_CR);
4983
4984         svm_flush_tlb(vcpu);
4985 }
4986
4987 static int is_disabled(void)
4988 {
4989         u64 vm_cr;
4990
4991         rdmsrl(MSR_VM_CR, vm_cr);
4992         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4993                 return 1;
4994
4995         return 0;
4996 }
4997
4998 static void
4999 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5000 {
5001         /*
5002          * Patch in the VMMCALL instruction:
5003          */
5004         hypercall[0] = 0x0f;
5005         hypercall[1] = 0x01;
5006         hypercall[2] = 0xd9;
5007 }
5008
5009 static void svm_check_processor_compat(void *rtn)
5010 {
5011         *(int *)rtn = 0;
5012 }
5013
5014 static bool svm_cpu_has_accelerated_tpr(void)
5015 {
5016         return false;
5017 }
5018
5019 static bool svm_has_high_real_mode_segbase(void)
5020 {
5021         return true;
5022 }
5023
5024 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5025 {
5026         return 0;
5027 }
5028
5029 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5030 {
5031         struct vcpu_svm *svm = to_svm(vcpu);
5032         struct kvm_cpuid_entry2 *entry;
5033
5034         /* Update nrips enabled cache */
5035         svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5036
5037         if (!kvm_vcpu_apicv_active(vcpu))
5038                 return;
5039
5040         entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5041         if (entry)
5042                 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5043 }
5044
5045 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5046 {
5047         switch (func) {
5048         case 0x1:
5049                 if (avic)
5050                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5051                 break;
5052         case 0x80000001:
5053                 if (nested)
5054                         entry->ecx |= (1 << 2); /* Set SVM bit */
5055                 break;
5056         case 0x8000000A:
5057                 entry->eax = 1; /* SVM revision 1 */
5058                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5059                                    ASID emulation to nested SVM */
5060                 entry->ecx = 0; /* Reserved */
5061                 entry->edx = 0; /* Per default do not support any
5062                                    additional features */
5063
5064                 /* Support next_rip if host supports it */
5065                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5066                         entry->edx |= SVM_FEATURE_NRIP;
5067
5068                 /* Support NPT for the guest if enabled */
5069                 if (npt_enabled)
5070                         entry->edx |= SVM_FEATURE_NPT;
5071
5072                 break;
5073         }
5074 }
5075
5076 static int svm_get_lpage_level(void)
5077 {
5078         return PT_PDPE_LEVEL;
5079 }
5080
5081 static bool svm_rdtscp_supported(void)
5082 {
5083         return boot_cpu_has(X86_FEATURE_RDTSCP);
5084 }
5085
5086 static bool svm_invpcid_supported(void)
5087 {
5088         return false;
5089 }
5090
5091 static bool svm_mpx_supported(void)
5092 {
5093         return false;
5094 }
5095
5096 static bool svm_xsaves_supported(void)
5097 {
5098         return false;
5099 }
5100
5101 static bool svm_has_wbinvd_exit(void)
5102 {
5103         return true;
5104 }
5105
5106 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
5107 {
5108         struct vcpu_svm *svm = to_svm(vcpu);
5109
5110         set_exception_intercept(svm, NM_VECTOR);
5111         update_cr0_intercept(svm);
5112 }
5113
5114 #define PRE_EX(exit)  { .exit_code = (exit), \
5115                         .stage = X86_ICPT_PRE_EXCEPT, }
5116 #define POST_EX(exit) { .exit_code = (exit), \
5117                         .stage = X86_ICPT_POST_EXCEPT, }
5118 #define POST_MEM(exit) { .exit_code = (exit), \
5119                         .stage = X86_ICPT_POST_MEMACCESS, }
5120
5121 static const struct __x86_intercept {
5122         u32 exit_code;
5123         enum x86_intercept_stage stage;
5124 } x86_intercept_map[] = {
5125         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5126         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5127         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5128         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5129         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5130         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5131         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5132         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5133         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5134         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5135         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5136         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5137         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5138         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5139         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5140         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5141         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5142         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5143         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5144         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5145         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5146         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5147         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5148         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5149         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5150         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5151         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5152         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5153         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5154         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5155         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5156         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5157         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5158         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5159         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5160         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5161         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5162         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5163         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5164         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5165         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5166         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5167         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5168         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5169         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5170         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5171 };
5172
5173 #undef PRE_EX
5174 #undef POST_EX
5175 #undef POST_MEM
5176
5177 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5178                                struct x86_instruction_info *info,
5179                                enum x86_intercept_stage stage)
5180 {
5181         struct vcpu_svm *svm = to_svm(vcpu);
5182         int vmexit, ret = X86EMUL_CONTINUE;
5183         struct __x86_intercept icpt_info;
5184         struct vmcb *vmcb = svm->vmcb;
5185
5186         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5187                 goto out;
5188
5189         icpt_info = x86_intercept_map[info->intercept];
5190
5191         if (stage != icpt_info.stage)
5192                 goto out;
5193
5194         switch (icpt_info.exit_code) {
5195         case SVM_EXIT_READ_CR0:
5196                 if (info->intercept == x86_intercept_cr_read)
5197                         icpt_info.exit_code += info->modrm_reg;
5198                 break;
5199         case SVM_EXIT_WRITE_CR0: {
5200                 unsigned long cr0, val;
5201                 u64 intercept;
5202
5203                 if (info->intercept == x86_intercept_cr_write)
5204                         icpt_info.exit_code += info->modrm_reg;
5205
5206                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5207                     info->intercept == x86_intercept_clts)
5208                         break;
5209
5210                 intercept = svm->nested.intercept;
5211
5212                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5213                         break;
5214
5215                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5216                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
5217
5218                 if (info->intercept == x86_intercept_lmsw) {
5219                         cr0 &= 0xfUL;
5220                         val &= 0xfUL;
5221                         /* lmsw can't clear PE - catch this here */
5222                         if (cr0 & X86_CR0_PE)
5223                                 val |= X86_CR0_PE;
5224                 }
5225
5226                 if (cr0 ^ val)
5227                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5228
5229                 break;
5230         }
5231         case SVM_EXIT_READ_DR0:
5232         case SVM_EXIT_WRITE_DR0:
5233                 icpt_info.exit_code += info->modrm_reg;
5234                 break;
5235         case SVM_EXIT_MSR:
5236                 if (info->intercept == x86_intercept_wrmsr)
5237                         vmcb->control.exit_info_1 = 1;
5238                 else
5239                         vmcb->control.exit_info_1 = 0;
5240                 break;
5241         case SVM_EXIT_PAUSE:
5242                 /*
5243                  * We get this for NOP only, but pause
5244                  * is rep not, check this here
5245                  */
5246                 if (info->rep_prefix != REPE_PREFIX)
5247                         goto out;
5248         case SVM_EXIT_IOIO: {
5249                 u64 exit_info;
5250                 u32 bytes;
5251
5252                 if (info->intercept == x86_intercept_in ||
5253                     info->intercept == x86_intercept_ins) {
5254                         exit_info = ((info->src_val & 0xffff) << 16) |
5255                                 SVM_IOIO_TYPE_MASK;
5256                         bytes = info->dst_bytes;
5257                 } else {
5258                         exit_info = (info->dst_val & 0xffff) << 16;
5259                         bytes = info->src_bytes;
5260                 }
5261
5262                 if (info->intercept == x86_intercept_outs ||
5263                     info->intercept == x86_intercept_ins)
5264                         exit_info |= SVM_IOIO_STR_MASK;
5265
5266                 if (info->rep_prefix)
5267                         exit_info |= SVM_IOIO_REP_MASK;
5268
5269                 bytes = min(bytes, 4u);
5270
5271                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5272
5273                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5274
5275                 vmcb->control.exit_info_1 = exit_info;
5276                 vmcb->control.exit_info_2 = info->next_rip;
5277
5278                 break;
5279         }
5280         default:
5281                 break;
5282         }
5283
5284         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5285         if (static_cpu_has(X86_FEATURE_NRIPS))
5286                 vmcb->control.next_rip  = info->next_rip;
5287         vmcb->control.exit_code = icpt_info.exit_code;
5288         vmexit = nested_svm_exit_handled(svm);
5289
5290         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5291                                            : X86EMUL_CONTINUE;
5292
5293 out:
5294         return ret;
5295 }
5296
5297 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5298 {
5299         local_irq_enable();
5300         /*
5301          * We must have an instruction with interrupts enabled, so
5302          * the timer interrupt isn't delayed by the interrupt shadow.
5303          */
5304         asm("nop");
5305         local_irq_disable();
5306 }
5307
5308 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5309 {
5310 }
5311
5312 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5313 {
5314         if (avic_handle_apic_id_update(vcpu) != 0)
5315                 return;
5316         if (avic_handle_dfr_update(vcpu) != 0)
5317                 return;
5318         avic_handle_ldr_update(vcpu);
5319 }
5320
5321 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5322         .cpu_has_kvm_support = has_svm,
5323         .disabled_by_bios = is_disabled,
5324         .hardware_setup = svm_hardware_setup,
5325         .hardware_unsetup = svm_hardware_unsetup,
5326         .check_processor_compatibility = svm_check_processor_compat,
5327         .hardware_enable = svm_hardware_enable,
5328         .hardware_disable = svm_hardware_disable,
5329         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5330         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5331
5332         .vcpu_create = svm_create_vcpu,
5333         .vcpu_free = svm_free_vcpu,
5334         .vcpu_reset = svm_vcpu_reset,
5335
5336         .vm_init = avic_vm_init,
5337         .vm_destroy = avic_vm_destroy,
5338
5339         .prepare_guest_switch = svm_prepare_guest_switch,
5340         .vcpu_load = svm_vcpu_load,
5341         .vcpu_put = svm_vcpu_put,
5342         .vcpu_blocking = svm_vcpu_blocking,
5343         .vcpu_unblocking = svm_vcpu_unblocking,
5344
5345         .update_bp_intercept = update_bp_intercept,
5346         .get_msr = svm_get_msr,
5347         .set_msr = svm_set_msr,
5348         .get_segment_base = svm_get_segment_base,
5349         .get_segment = svm_get_segment,
5350         .set_segment = svm_set_segment,
5351         .get_cpl = svm_get_cpl,
5352         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5353         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5354         .decache_cr3 = svm_decache_cr3,
5355         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5356         .set_cr0 = svm_set_cr0,
5357         .set_cr3 = svm_set_cr3,
5358         .set_cr4 = svm_set_cr4,
5359         .set_efer = svm_set_efer,
5360         .get_idt = svm_get_idt,
5361         .set_idt = svm_set_idt,
5362         .get_gdt = svm_get_gdt,
5363         .set_gdt = svm_set_gdt,
5364         .get_dr6 = svm_get_dr6,
5365         .set_dr6 = svm_set_dr6,
5366         .set_dr7 = svm_set_dr7,
5367         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5368         .cache_reg = svm_cache_reg,
5369         .get_rflags = svm_get_rflags,
5370         .set_rflags = svm_set_rflags,
5371
5372         .get_pkru = svm_get_pkru,
5373
5374         .fpu_activate = svm_fpu_activate,
5375         .fpu_deactivate = svm_fpu_deactivate,
5376
5377         .tlb_flush = svm_flush_tlb,
5378
5379         .run = svm_vcpu_run,
5380         .handle_exit = handle_exit,
5381         .skip_emulated_instruction = skip_emulated_instruction,
5382         .set_interrupt_shadow = svm_set_interrupt_shadow,
5383         .get_interrupt_shadow = svm_get_interrupt_shadow,
5384         .patch_hypercall = svm_patch_hypercall,
5385         .set_irq = svm_set_irq,
5386         .set_nmi = svm_inject_nmi,
5387         .queue_exception = svm_queue_exception,
5388         .cancel_injection = svm_cancel_injection,
5389         .interrupt_allowed = svm_interrupt_allowed,
5390         .nmi_allowed = svm_nmi_allowed,
5391         .get_nmi_mask = svm_get_nmi_mask,
5392         .set_nmi_mask = svm_set_nmi_mask,
5393         .enable_nmi_window = enable_nmi_window,
5394         .enable_irq_window = enable_irq_window,
5395         .update_cr8_intercept = update_cr8_intercept,
5396         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5397         .get_enable_apicv = svm_get_enable_apicv,
5398         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5399         .load_eoi_exitmap = svm_load_eoi_exitmap,
5400         .sync_pir_to_irr = svm_sync_pir_to_irr,
5401         .hwapic_irr_update = svm_hwapic_irr_update,
5402         .hwapic_isr_update = svm_hwapic_isr_update,
5403         .apicv_post_state_restore = avic_post_state_restore,
5404
5405         .set_tss_addr = svm_set_tss_addr,
5406         .get_tdp_level = get_npt_level,
5407         .get_mt_mask = svm_get_mt_mask,
5408
5409         .get_exit_info = svm_get_exit_info,
5410
5411         .get_lpage_level = svm_get_lpage_level,
5412
5413         .cpuid_update = svm_cpuid_update,
5414
5415         .rdtscp_supported = svm_rdtscp_supported,
5416         .invpcid_supported = svm_invpcid_supported,
5417         .mpx_supported = svm_mpx_supported,
5418         .xsaves_supported = svm_xsaves_supported,
5419
5420         .set_supported_cpuid = svm_set_supported_cpuid,
5421
5422         .has_wbinvd_exit = svm_has_wbinvd_exit,
5423
5424         .write_tsc_offset = svm_write_tsc_offset,
5425         .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest,
5426         .read_l1_tsc = svm_read_l1_tsc,
5427
5428         .set_tdp_cr3 = set_tdp_cr3,
5429
5430         .check_intercept = svm_check_intercept,
5431         .handle_external_intr = svm_handle_external_intr,
5432
5433         .sched_in = svm_sched_in,
5434
5435         .pmu_ops = &amd_pmu_ops,
5436         .deliver_posted_interrupt = svm_deliver_avic_intr,
5437         .update_pi_irte = svm_update_pi_irte,
5438 };
5439
5440 static int __init svm_init(void)
5441 {
5442         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5443                         __alignof__(struct vcpu_svm), THIS_MODULE);
5444 }
5445
5446 static void __exit svm_exit(void)
5447 {
5448         kvm_exit();
5449 }
5450
5451 module_init(svm_init)
5452 module_exit(svm_exit)