arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376 };
 377
 378 #define POSTED_INTR_ON  0
 379 /* Posted-Interrupt Descriptor */
 380 struct pi_desc {
 381         u32 pir[8];     /* Posted interrupt requested */
 382         u32 control;    /* bit 0 of control is outstanding notification bit */
 383         u32 rsvd[7];
 384 } __aligned(64);
 385
 386 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 387 {
 388         return test_and_set_bit(POSTED_INTR_ON,
 389                         (unsigned long *)&pi_desc->control);
 390 }
 391
 392 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 393 {
 394         return test_and_clear_bit(POSTED_INTR_ON,
 395                         (unsigned long *)&pi_desc->control);
 396 }
 397
 398 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 399 {
 400         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 401 }
 402
 403 struct vcpu_vmx {
 404         struct kvm_vcpu       vcpu;
 405         unsigned long         host_rsp;
 406         u8                    fail;
 407         u8                    cpl;
 408         bool                  nmi_known_unmasked;
 409         u32                   exit_intr_info;
 410         u32                   idt_vectoring_info;
 411         ulong                 rflags;
 412         struct shared_msr_entry *guest_msrs;
 413         int                   nmsrs;
 414         int                   save_nmsrs;
 415         unsigned long         host_idt_base;
 416 #ifdef CONFIG_X86_64
 417         u64                   msr_host_kernel_gs_base;
 418         u64                   msr_guest_kernel_gs_base;
 419 #endif
 420         /*
 421          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 422          * non-nested (L1) guest, it always points to vmcs01. For a nested
 423          * guest (L2), it points to a different VMCS.
 424          */
 425         struct loaded_vmcs    vmcs01;
 426         struct loaded_vmcs   *loaded_vmcs;
 427         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 428         struct msr_autoload {
 429                 unsigned nr;
 430                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 431                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 432         } msr_autoload;
 433         struct {
 434                 int           loaded;
 435                 u16           fs_sel, gs_sel, ldt_sel;
 436 #ifdef CONFIG_X86_64
 437                 u16           ds_sel, es_sel;
 438 #endif
 439                 int           gs_ldt_reload_needed;
 440                 int           fs_reload_needed;
 441         } host_state;
 442         struct {
 443                 int vm86_active;
 444                 ulong save_rflags;
 445                 struct kvm_segment segs[8];
 446         } rmode;
 447         struct {
 448                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 449                 struct kvm_save_segment {
 450                         u16 selector;
 451                         unsigned long base;
 452                         u32 limit;
 453                         u32 ar;
 454                 } seg[8];
 455         } segment_cache;
 456         int vpid;
 457         bool emulation_required;
 458
 459         /* Support for vnmi-less CPUs */
 460         int soft_vnmi_blocked;
 461         ktime_t entry_time;
 462         s64 vnmi_blocked_time;
 463         u32 exit_reason;
 464
 465         bool rdtscp_enabled;
 466
 467         /* Posted interrupt descriptor */
 468         struct pi_desc pi_desc;
 469
 470         /* Support for a guest hypervisor (nested VMX) */
 471         struct nested_vmx nested;
 472 };
 473
 474 enum segment_cache_field {
 475         SEG_FIELD_SEL = 0,
 476         SEG_FIELD_BASE = 1,
 477         SEG_FIELD_LIMIT = 2,
 478         SEG_FIELD_AR = 3,
 479
 480         SEG_FIELD_NR = 4
 481 };
 482
 483 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 484 {
 485         return container_of(vcpu, struct vcpu_vmx, vcpu);
 486 }
 487
 488 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 489 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 490 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 491                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 492
 493
 494 static const unsigned long shadow_read_only_fields[] = {
 495         /*
 496          * We do NOT shadow fields that are modified when L0
 497          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 498          * VMXON...) executed by L1.
 499          * For example, VM_INSTRUCTION_ERROR is read
 500          * by L1 if a vmx instruction fails (part of the error path).
 501          * Note the code assumes this logic. If for some reason
 502          * we start shadowing these fields then we need to
 503          * force a shadow sync when L0 emulates vmx instructions
 504          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 505          * by nested_vmx_failValid)
 506          */
 507         VM_EXIT_REASON,
 508         VM_EXIT_INTR_INFO,
 509         VM_EXIT_INSTRUCTION_LEN,
 510         IDT_VECTORING_INFO_FIELD,
 511         IDT_VECTORING_ERROR_CODE,
 512         VM_EXIT_INTR_ERROR_CODE,
 513         EXIT_QUALIFICATION,
 514         GUEST_LINEAR_ADDRESS,
 515         GUEST_PHYSICAL_ADDRESS
 516 };
 517 static const int max_shadow_read_only_fields =
 518         ARRAY_SIZE(shadow_read_only_fields);
 519
 520 static const unsigned long shadow_read_write_fields[] = {
 521         GUEST_RIP,
 522         GUEST_RSP,
 523         GUEST_CR0,
 524         GUEST_CR3,
 525         GUEST_CR4,
 526         GUEST_INTERRUPTIBILITY_INFO,
 527         GUEST_RFLAGS,
 528         GUEST_CS_SELECTOR,
 529         GUEST_CS_AR_BYTES,
 530         GUEST_CS_LIMIT,
 531         GUEST_CS_BASE,
 532         GUEST_ES_BASE,
 533         CR0_GUEST_HOST_MASK,
 534         CR0_READ_SHADOW,
 535         CR4_READ_SHADOW,
 536         TSC_OFFSET,
 537         EXCEPTION_BITMAP,
 538         CPU_BASED_VM_EXEC_CONTROL,
 539         VM_ENTRY_EXCEPTION_ERROR_CODE,
 540         VM_ENTRY_INTR_INFO_FIELD,
 541         VM_ENTRY_INSTRUCTION_LEN,
 542         VM_ENTRY_EXCEPTION_ERROR_CODE,
 543         HOST_FS_BASE,
 544         HOST_GS_BASE,
 545         HOST_FS_SELECTOR,
 546         HOST_GS_SELECTOR
 547 };
 548 static const int max_shadow_read_write_fields =
 549         ARRAY_SIZE(shadow_read_write_fields);
 550
 551 static const unsigned short vmcs_field_to_offset_table[] = {
 552         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 553         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 554         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 555         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 556         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 557         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 558         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 559         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 560         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 561         FIELD(HOST_ES_SELECTOR, host_es_selector),
 562         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 563         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 564         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 565         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 566         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 567         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 568         FIELD64(IO_BITMAP_A, io_bitmap_a),
 569         FIELD64(IO_BITMAP_B, io_bitmap_b),
 570         FIELD64(MSR_BITMAP, msr_bitmap),
 571         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 572         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 573         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 574         FIELD64(TSC_OFFSET, tsc_offset),
 575         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 576         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 577         FIELD64(EPT_POINTER, ept_pointer),
 578         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 579         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 580         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 581         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 582         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 583         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 584         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 585         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 586         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 587         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 588         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 589         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 590         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 591         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 592         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 593         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 594         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 596         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 597         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 598         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 599         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 600         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 601         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 602         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 603         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 604         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 605         FIELD(TPR_THRESHOLD, tpr_threshold),
 606         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 607         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 608         FIELD(VM_EXIT_REASON, vm_exit_reason),
 609         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 610         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 611         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 612         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 613         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 614         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 615         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 616         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 617         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 618         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 619         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 620         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 621         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 622         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 623         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 624         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 625         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 626         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 627         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 628         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 629         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 630         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 631         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 632         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 633         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 634         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 635         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 636         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 637         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 638         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 639         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 640         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 641         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 642         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 643         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 644         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 645         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 646         FIELD(EXIT_QUALIFICATION, exit_qualification),
 647         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 648         FIELD(GUEST_CR0, guest_cr0),
 649         FIELD(GUEST_CR3, guest_cr3),
 650         FIELD(GUEST_CR4, guest_cr4),
 651         FIELD(GUEST_ES_BASE, guest_es_base),
 652         FIELD(GUEST_CS_BASE, guest_cs_base),
 653         FIELD(GUEST_SS_BASE, guest_ss_base),
 654         FIELD(GUEST_DS_BASE, guest_ds_base),
 655         FIELD(GUEST_FS_BASE, guest_fs_base),
 656         FIELD(GUEST_GS_BASE, guest_gs_base),
 657         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 658         FIELD(GUEST_TR_BASE, guest_tr_base),
 659         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 660         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 661         FIELD(GUEST_DR7, guest_dr7),
 662         FIELD(GUEST_RSP, guest_rsp),
 663         FIELD(GUEST_RIP, guest_rip),
 664         FIELD(GUEST_RFLAGS, guest_rflags),
 665         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 666         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 667         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 668         FIELD(HOST_CR0, host_cr0),
 669         FIELD(HOST_CR3, host_cr3),
 670         FIELD(HOST_CR4, host_cr4),
 671         FIELD(HOST_FS_BASE, host_fs_base),
 672         FIELD(HOST_GS_BASE, host_gs_base),
 673         FIELD(HOST_TR_BASE, host_tr_base),
 674         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 675         FIELD(HOST_IDTR_BASE, host_idtr_base),
 676         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 677         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 678         FIELD(HOST_RSP, host_rsp),
 679         FIELD(HOST_RIP, host_rip),
 680 };
 681 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 682
 683 static inline short vmcs_field_to_offset(unsigned long field)
 684 {
 685         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 686                 return -1;
 687         return vmcs_field_to_offset_table[field];
 688 }
 689
 690 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 691 {
 692         return to_vmx(vcpu)->nested.current_vmcs12;
 693 }
 694
 695 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 696 {
 697         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 698         if (is_error_page(page))
 699                 return NULL;
 700
 701         return page;
 702 }
 703
 704 static void nested_release_page(struct page *page)
 705 {
 706         kvm_release_page_dirty(page);
 707 }
 708
 709 static void nested_release_page_clean(struct page *page)
 710 {
 711         kvm_release_page_clean(page);
 712 }
 713
 714 static u64 construct_eptp(unsigned long root_hpa);
 715 static void kvm_cpu_vmxon(u64 addr);
 716 static void kvm_cpu_vmxoff(void);
 717 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 718 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 719 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 720                             struct kvm_segment *var, int seg);
 721 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 722                             struct kvm_segment *var, int seg);
 723 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 724 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 725 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 726 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 727 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 728
 729 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 730 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 731 /*
 732  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 733  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 734  */
 735 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 736 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 737
 738 static unsigned long *vmx_io_bitmap_a;
 739 static unsigned long *vmx_io_bitmap_b;
 740 static unsigned long *vmx_msr_bitmap_legacy;
 741 static unsigned long *vmx_msr_bitmap_longmode;
 742 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 743 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 744 static unsigned long *vmx_vmread_bitmap;
 745 static unsigned long *vmx_vmwrite_bitmap;
 746
 747 static bool cpu_has_load_ia32_efer;
 748 static bool cpu_has_load_perf_global_ctrl;
 749
 750 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 751 static DEFINE_SPINLOCK(vmx_vpid_lock);
 752
 753 static struct vmcs_config {
 754         int size;
 755         int order;
 756         u32 revision_id;
 757         u32 pin_based_exec_ctrl;
 758         u32 cpu_based_exec_ctrl;
 759         u32 cpu_based_2nd_exec_ctrl;
 760         u32 vmexit_ctrl;
 761         u32 vmentry_ctrl;
 762 } vmcs_config;
 763
 764 static struct vmx_capability {
 765         u32 ept;
 766         u32 vpid;
 767 } vmx_capability;
 768
 769 #define VMX_SEGMENT_FIELD(seg)                                  \
 770         [VCPU_SREG_##seg] = {                                   \
 771                 .selector = GUEST_##seg##_SELECTOR,             \
 772                 .base = GUEST_##seg##_BASE,                     \
 773                 .limit = GUEST_##seg##_LIMIT,                   \
 774                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 775         }
 776
 777 static const struct kvm_vmx_segment_field {
 778         unsigned selector;
 779         unsigned base;
 780         unsigned limit;
 781         unsigned ar_bytes;
 782 } kvm_vmx_segment_fields[] = {
 783         VMX_SEGMENT_FIELD(CS),
 784         VMX_SEGMENT_FIELD(DS),
 785         VMX_SEGMENT_FIELD(ES),
 786         VMX_SEGMENT_FIELD(FS),
 787         VMX_SEGMENT_FIELD(GS),
 788         VMX_SEGMENT_FIELD(SS),
 789         VMX_SEGMENT_FIELD(TR),
 790         VMX_SEGMENT_FIELD(LDTR),
 791 };
 792
 793 static u64 host_efer;
 794
 795 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 796
 797 /*
 798  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 799  * away by decrementing the array size.
 800  */
 801 static const u32 vmx_msr_index[] = {
 802 #ifdef CONFIG_X86_64
 803         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 804 #endif
 805         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 806 };
 807 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 808
 809 static inline bool is_page_fault(u32 intr_info)
 810 {
 811         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 812                              INTR_INFO_VALID_MASK)) ==
 813                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 814 }
 815
 816 static inline bool is_no_device(u32 intr_info)
 817 {
 818         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 819                              INTR_INFO_VALID_MASK)) ==
 820                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 821 }
 822
 823 static inline bool is_invalid_opcode(u32 intr_info)
 824 {
 825         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 826                              INTR_INFO_VALID_MASK)) ==
 827                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 828 }
 829
 830 static inline bool is_external_interrupt(u32 intr_info)
 831 {
 832         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 833                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 834 }
 835
 836 static inline bool is_machine_check(u32 intr_info)
 837 {
 838         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 839                              INTR_INFO_VALID_MASK)) ==
 840                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 841 }
 842
 843 static inline bool cpu_has_vmx_msr_bitmap(void)
 844 {
 845         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 846 }
 847
 848 static inline bool cpu_has_vmx_tpr_shadow(void)
 849 {
 850         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 851 }
 852
 853 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 854 {
 855         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 856 }
 857
 858 static inline bool cpu_has_secondary_exec_ctrls(void)
 859 {
 860         return vmcs_config.cpu_based_exec_ctrl &
 861                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 862 }
 863
 864 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 865 {
 866         return vmcs_config.cpu_based_2nd_exec_ctrl &
 867                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 868 }
 869
 870 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 871 {
 872         return vmcs_config.cpu_based_2nd_exec_ctrl &
 873                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 874 }
 875
 876 static inline bool cpu_has_vmx_apic_register_virt(void)
 877 {
 878         return vmcs_config.cpu_based_2nd_exec_ctrl &
 879                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 880 }
 881
 882 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 883 {
 884         return vmcs_config.cpu_based_2nd_exec_ctrl &
 885                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 886 }
 887
 888 static inline bool cpu_has_vmx_posted_intr(void)
 889 {
 890         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 891 }
 892
 893 static inline bool cpu_has_vmx_apicv(void)
 894 {
 895         return cpu_has_vmx_apic_register_virt() &&
 896                 cpu_has_vmx_virtual_intr_delivery() &&
 897                 cpu_has_vmx_posted_intr();
 898 }
 899
 900 static inline bool cpu_has_vmx_flexpriority(void)
 901 {
 902         return cpu_has_vmx_tpr_shadow() &&
 903                 cpu_has_vmx_virtualize_apic_accesses();
 904 }
 905
 906 static inline bool cpu_has_vmx_ept_execute_only(void)
 907 {
 908         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 909 }
 910
 911 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 912 {
 913         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 914 }
 915
 916 static inline bool cpu_has_vmx_eptp_writeback(void)
 917 {
 918         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 919 }
 920
 921 static inline bool cpu_has_vmx_ept_2m_page(void)
 922 {
 923         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 924 }
 925
 926 static inline bool cpu_has_vmx_ept_1g_page(void)
 927 {
 928         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 929 }
 930
 931 static inline bool cpu_has_vmx_ept_4levels(void)
 932 {
 933         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 934 }
 935
 936 static inline bool cpu_has_vmx_ept_ad_bits(void)
 937 {
 938         return vmx_capability.ept & VMX_EPT_AD_BIT;
 939 }
 940
 941 static inline bool cpu_has_vmx_invept_context(void)
 942 {
 943         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 944 }
 945
 946 static inline bool cpu_has_vmx_invept_global(void)
 947 {
 948         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 949 }
 950
 951 static inline bool cpu_has_vmx_invvpid_single(void)
 952 {
 953         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 954 }
 955
 956 static inline bool cpu_has_vmx_invvpid_global(void)
 957 {
 958         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 959 }
 960
 961 static inline bool cpu_has_vmx_ept(void)
 962 {
 963         return vmcs_config.cpu_based_2nd_exec_ctrl &
 964                 SECONDARY_EXEC_ENABLE_EPT;
 965 }
 966
 967 static inline bool cpu_has_vmx_unrestricted_guest(void)
 968 {
 969         return vmcs_config.cpu_based_2nd_exec_ctrl &
 970                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 971 }
 972
 973 static inline bool cpu_has_vmx_ple(void)
 974 {
 975         return vmcs_config.cpu_based_2nd_exec_ctrl &
 976                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 977 }
 978
 979 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 980 {
 981         return flexpriority_enabled && irqchip_in_kernel(kvm);
 982 }
 983
 984 static inline bool cpu_has_vmx_vpid(void)
 985 {
 986         return vmcs_config.cpu_based_2nd_exec_ctrl &
 987                 SECONDARY_EXEC_ENABLE_VPID;
 988 }
 989
 990 static inline bool cpu_has_vmx_rdtscp(void)
 991 {
 992         return vmcs_config.cpu_based_2nd_exec_ctrl &
 993                 SECONDARY_EXEC_RDTSCP;
 994 }
 995
 996 static inline bool cpu_has_vmx_invpcid(void)
 997 {
 998         return vmcs_config.cpu_based_2nd_exec_ctrl &
 999                 SECONDARY_EXEC_ENABLE_INVPCID;
1000 }
1001
1002 static inline bool cpu_has_virtual_nmis(void)
1003 {
1004         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005 }
1006
1007 static inline bool cpu_has_vmx_wbinvd_exit(void)
1008 {
1009         return vmcs_config.cpu_based_2nd_exec_ctrl &
1010                 SECONDARY_EXEC_WBINVD_EXITING;
1011 }
1012
1013 static inline bool cpu_has_vmx_shadow_vmcs(void)
1014 {
1015         u64 vmx_msr;
1016         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017         /* check if the cpu supports writing r/o exit information fields */
1018         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019                 return false;
1020
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_SHADOW_VMCS;
1023 }
1024
1025 static inline bool report_flexpriority(void)
1026 {
1027         return flexpriority_enabled;
1028 }
1029
1030 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031 {
1032         return vmcs12->cpu_based_vm_exec_control & bit;
1033 }
1034
1035 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036 {
1037         return (vmcs12->cpu_based_vm_exec_control &
1038                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039                 (vmcs12->secondary_vm_exec_control & bit);
1040 }
1041
1042 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043         struct kvm_vcpu *vcpu)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline bool is_exception(u32 intr_info)
1049 {
1050         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052 }
1053
1054 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1055 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056                         struct vmcs12 *vmcs12,
1057                         u32 reason, unsigned long qualification);
1058
1059 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1060 {
1061         int i;
1062
1063         for (i = 0; i < vmx->nmsrs; ++i)
1064                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1065                         return i;
1066         return -1;
1067 }
1068
1069 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070 {
1071     struct {
1072         u64 vpid : 16;
1073         u64 rsvd : 48;
1074         u64 gva;
1075     } operand = { vpid, 0, gva };
1076
1077     asm volatile (__ex(ASM_VMX_INVVPID)
1078                   /* CF==1 or ZF==1 --> rc = -1 */
1079                   "; ja 1f ; ud2 ; 1:"
1080                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1081 }
1082
1083 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084 {
1085         struct {
1086                 u64 eptp, gpa;
1087         } operand = {eptp, gpa};
1088
1089         asm volatile (__ex(ASM_VMX_INVEPT)
1090                         /* CF==1 or ZF==1 --> rc = -1 */
1091                         "; ja 1f ; ud2 ; 1:\n"
1092                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1093 }
1094
1095 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1096 {
1097         int i;
1098
1099         i = __find_msr_index(vmx, msr);
1100         if (i >= 0)
1101                 return &vmx->guest_msrs[i];
1102         return NULL;
1103 }
1104
1105 static void vmcs_clear(struct vmcs *vmcs)
1106 {
1107         u64 phys_addr = __pa(vmcs);
1108         u8 error;
1109
1110         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1111                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1112                       : "cc", "memory");
1113         if (error)
1114                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115                        vmcs, phys_addr);
1116 }
1117
1118 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119 {
1120         vmcs_clear(loaded_vmcs->vmcs);
1121         loaded_vmcs->cpu = -1;
1122         loaded_vmcs->launched = 0;
1123 }
1124
1125 static void vmcs_load(struct vmcs *vmcs)
1126 {
1127         u64 phys_addr = __pa(vmcs);
1128         u8 error;
1129
1130         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1131                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1132                         : "cc", "memory");
1133         if (error)
1134                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1135                        vmcs, phys_addr);
1136 }
1137
1138 #ifdef CONFIG_KEXEC
1139 /*
1140  * This bitmap is used to indicate whether the vmclear
1141  * operation is enabled on all cpus. All disabled by
1142  * default.
1143  */
1144 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146 static inline void crash_enable_local_vmclear(int cpu)
1147 {
1148         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149 }
1150
1151 static inline void crash_disable_local_vmclear(int cpu)
1152 {
1153         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline int crash_local_vmclear_enabled(int cpu)
1157 {
1158         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static void crash_vmclear_local_loaded_vmcss(void)
1162 {
1163         int cpu = raw_smp_processor_id();
1164         struct loaded_vmcs *v;
1165
1166         if (!crash_local_vmclear_enabled(cpu))
1167                 return;
1168
1169         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170                             loaded_vmcss_on_cpu_link)
1171                 vmcs_clear(v->vmcs);
1172 }
1173 #else
1174 static inline void crash_enable_local_vmclear(int cpu) { }
1175 static inline void crash_disable_local_vmclear(int cpu) { }
1176 #endif /* CONFIG_KEXEC */
1177
1178 static void __loaded_vmcs_clear(void *arg)
1179 {
1180         struct loaded_vmcs *loaded_vmcs = arg;
1181         int cpu = raw_smp_processor_id();
1182
1183         if (loaded_vmcs->cpu != cpu)
1184                 return; /* vcpu migration can race with cpu offline */
1185         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1186                 per_cpu(current_vmcs, cpu) = NULL;
1187         crash_disable_local_vmclear(cpu);
1188         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1189
1190         /*
1191          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1192          * is before setting loaded_vmcs->vcpu to -1 which is done in
1193          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1194          * then adds the vmcs into percpu list before it is deleted.
1195          */
1196         smp_wmb();
1197
1198         loaded_vmcs_init(loaded_vmcs);
1199         crash_enable_local_vmclear(cpu);
1200 }
1201
1202 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1203 {
1204         int cpu = loaded_vmcs->cpu;
1205
1206         if (cpu != -1)
1207                 smp_call_function_single(cpu,
1208                          __loaded_vmcs_clear, loaded_vmcs, 1);
1209 }
1210
1211 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1212 {
1213         if (vmx->vpid == 0)
1214                 return;
1215
1216         if (cpu_has_vmx_invvpid_single())
1217                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1218 }
1219
1220 static inline void vpid_sync_vcpu_global(void)
1221 {
1222         if (cpu_has_vmx_invvpid_global())
1223                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224 }
1225
1226 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227 {
1228         if (cpu_has_vmx_invvpid_single())
1229                 vpid_sync_vcpu_single(vmx);
1230         else
1231                 vpid_sync_vcpu_global();
1232 }
1233
1234 static inline void ept_sync_global(void)
1235 {
1236         if (cpu_has_vmx_invept_global())
1237                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238 }
1239
1240 static inline void ept_sync_context(u64 eptp)
1241 {
1242         if (enable_ept) {
1243                 if (cpu_has_vmx_invept_context())
1244                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245                 else
1246                         ept_sync_global();
1247         }
1248 }
1249
1250 static __always_inline unsigned long vmcs_readl(unsigned long field)
1251 {
1252         unsigned long value;
1253
1254         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255                       : "=a"(value) : "d"(field) : "cc");
1256         return value;
1257 }
1258
1259 static __always_inline u16 vmcs_read16(unsigned long field)
1260 {
1261         return vmcs_readl(field);
1262 }
1263
1264 static __always_inline u32 vmcs_read32(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u64 vmcs_read64(unsigned long field)
1270 {
1271 #ifdef CONFIG_X86_64
1272         return vmcs_readl(field);
1273 #else
1274         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275 #endif
1276 }
1277
1278 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279 {
1280         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282         dump_stack();
1283 }
1284
1285 static void vmcs_writel(unsigned long field, unsigned long value)
1286 {
1287         u8 error;
1288
1289         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1290                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1291         if (unlikely(error))
1292                 vmwrite_error(field, value);
1293 }
1294
1295 static void vmcs_write16(unsigned long field, u16 value)
1296 {
1297         vmcs_writel(field, value);
1298 }
1299
1300 static void vmcs_write32(unsigned long field, u32 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write64(unsigned long field, u64 value)
1306 {
1307         vmcs_writel(field, value);
1308 #ifndef CONFIG_X86_64
1309         asm volatile ("");
1310         vmcs_writel(field+1, value >> 32);
1311 #endif
1312 }
1313
1314 static void vmcs_clear_bits(unsigned long field, u32 mask)
1315 {
1316         vmcs_writel(field, vmcs_readl(field) & ~mask);
1317 }
1318
1319 static void vmcs_set_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) | mask);
1322 }
1323
1324 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325 {
1326         vmx->segment_cache.bitmask = 0;
1327 }
1328
1329 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330                                        unsigned field)
1331 {
1332         bool ret;
1333         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337                 vmx->segment_cache.bitmask = 0;
1338         }
1339         ret = vmx->segment_cache.bitmask & mask;
1340         vmx->segment_cache.bitmask |= mask;
1341         return ret;
1342 }
1343
1344 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345 {
1346         u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350         return *p;
1351 }
1352
1353 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354 {
1355         ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359         return *p;
1360 }
1361
1362 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363 {
1364         u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368         return *p;
1369 }
1370
1371 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372 {
1373         u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377         return *p;
1378 }
1379
1380 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381 {
1382         u32 eb;
1383
1384         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386         if ((vcpu->guest_debug &
1387              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389                 eb |= 1u << BP_VECTOR;
1390         if (to_vmx(vcpu)->rmode.vm86_active)
1391                 eb = ~0;
1392         if (enable_ept)
1393                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1394         if (vcpu->fpu_active)
1395                 eb &= ~(1u << NM_VECTOR);
1396
1397         /* When we are running a nested L2 guest and L1 specified for it a
1398          * certain exception bitmap, we must trap the same exceptions and pass
1399          * them to L1. When running L2, we will only handle the exceptions
1400          * specified above if L1 did not want them.
1401          */
1402         if (is_guest_mode(vcpu))
1403                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
1405         vmcs_write32(EXCEPTION_BITMAP, eb);
1406 }
1407
1408 static void clear_atomic_switch_msr_special(unsigned long entry,
1409                 unsigned long exit)
1410 {
1411         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413 }
1414
1415 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416 {
1417         unsigned i;
1418         struct msr_autoload *m = &vmx->msr_autoload;
1419
1420         switch (msr) {
1421         case MSR_EFER:
1422                 if (cpu_has_load_ia32_efer) {
1423                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424                                         VM_EXIT_LOAD_IA32_EFER);
1425                         return;
1426                 }
1427                 break;
1428         case MSR_CORE_PERF_GLOBAL_CTRL:
1429                 if (cpu_has_load_perf_global_ctrl) {
1430                         clear_atomic_switch_msr_special(
1431                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433                         return;
1434                 }
1435                 break;
1436         }
1437
1438         for (i = 0; i < m->nr; ++i)
1439                 if (m->guest[i].index == msr)
1440                         break;
1441
1442         if (i == m->nr)
1443                 return;
1444         --m->nr;
1445         m->guest[i] = m->guest[m->nr];
1446         m->host[i] = m->host[m->nr];
1447         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449 }
1450
1451 static void add_atomic_switch_msr_special(unsigned long entry,
1452                 unsigned long exit, unsigned long guest_val_vmcs,
1453                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454 {
1455         vmcs_write64(guest_val_vmcs, guest_val);
1456         vmcs_write64(host_val_vmcs, host_val);
1457         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459 }
1460
1461 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462                                   u64 guest_val, u64 host_val)
1463 {
1464         unsigned i;
1465         struct msr_autoload *m = &vmx->msr_autoload;
1466
1467         switch (msr) {
1468         case MSR_EFER:
1469                 if (cpu_has_load_ia32_efer) {
1470                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471                                         VM_EXIT_LOAD_IA32_EFER,
1472                                         GUEST_IA32_EFER,
1473                                         HOST_IA32_EFER,
1474                                         guest_val, host_val);
1475                         return;
1476                 }
1477                 break;
1478         case MSR_CORE_PERF_GLOBAL_CTRL:
1479                 if (cpu_has_load_perf_global_ctrl) {
1480                         add_atomic_switch_msr_special(
1481                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1484                                         HOST_IA32_PERF_GLOBAL_CTRL,
1485                                         guest_val, host_val);
1486                         return;
1487                 }
1488                 break;
1489         }
1490
1491         for (i = 0; i < m->nr; ++i)
1492                 if (m->guest[i].index == msr)
1493                         break;
1494
1495         if (i == NR_AUTOLOAD_MSRS) {
1496                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497                                 "Can't add msr %x\n", msr);
1498                 return;
1499         } else if (i == m->nr) {
1500                 ++m->nr;
1501                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503         }
1504
1505         m->guest[i].index = msr;
1506         m->guest[i].value = guest_val;
1507         m->host[i].index = msr;
1508         m->host[i].value = host_val;
1509 }
1510
1511 static void reload_tss(void)
1512 {
1513         /*
1514          * VT restores TR but not its size.  Useless.
1515          */
1516         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1517         struct desc_struct *descs;
1518
1519         descs = (void *)gdt->address;
1520         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1521         load_TR_desc();
1522 }
1523
1524 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1525 {
1526         u64 guest_efer;
1527         u64 ignore_bits;
1528
1529         guest_efer = vmx->vcpu.arch.efer;
1530
1531         /*
1532          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1533          * outside long mode
1534          */
1535         ignore_bits = EFER_NX | EFER_SCE;
1536 #ifdef CONFIG_X86_64
1537         ignore_bits |= EFER_LMA | EFER_LME;
1538         /* SCE is meaningful only in long mode on Intel */
1539         if (guest_efer & EFER_LMA)
1540                 ignore_bits &= ~(u64)EFER_SCE;
1541 #endif
1542         guest_efer &= ~ignore_bits;
1543         guest_efer |= host_efer & ignore_bits;
1544         vmx->guest_msrs[efer_offset].data = guest_efer;
1545         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1546
1547         clear_atomic_switch_msr(vmx, MSR_EFER);
1548         /* On ept, can't emulate nx, and must switch nx atomically */
1549         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550                 guest_efer = vmx->vcpu.arch.efer;
1551                 if (!(guest_efer & EFER_LMA))
1552                         guest_efer &= ~EFER_LME;
1553                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554                 return false;
1555         }
1556
1557         return true;
1558 }
1559
1560 static unsigned long segment_base(u16 selector)
1561 {
1562         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1563         struct desc_struct *d;
1564         unsigned long table_base;
1565         unsigned long v;
1566
1567         if (!(selector & ~3))
1568                 return 0;
1569
1570         table_base = gdt->address;
1571
1572         if (selector & 4) {           /* from ldt */
1573                 u16 ldt_selector = kvm_read_ldt();
1574
1575                 if (!(ldt_selector & ~3))
1576                         return 0;
1577
1578                 table_base = segment_base(ldt_selector);
1579         }
1580         d = (struct desc_struct *)(table_base + (selector & ~7));
1581         v = get_desc_base(d);
1582 #ifdef CONFIG_X86_64
1583        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585 #endif
1586         return v;
1587 }
1588
1589 static inline unsigned long kvm_read_tr_base(void)
1590 {
1591         u16 tr;
1592         asm("str %0" : "=g"(tr));
1593         return segment_base(tr);
1594 }
1595
1596 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1597 {
1598         struct vcpu_vmx *vmx = to_vmx(vcpu);
1599         int i;
1600
1601         if (vmx->host_state.loaded)
1602                 return;
1603
1604         vmx->host_state.loaded = 1;
1605         /*
1606          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1607          * allow segment selectors with cpl > 0 or ti == 1.
1608          */
1609         vmx->host_state.ldt_sel = kvm_read_ldt();
1610         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1611         savesegment(fs, vmx->host_state.fs_sel);
1612         if (!(vmx->host_state.fs_sel & 7)) {
1613                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1614                 vmx->host_state.fs_reload_needed = 0;
1615         } else {
1616                 vmcs_write16(HOST_FS_SELECTOR, 0);
1617                 vmx->host_state.fs_reload_needed = 1;
1618         }
1619         savesegment(gs, vmx->host_state.gs_sel);
1620         if (!(vmx->host_state.gs_sel & 7))
1621                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1622         else {
1623                 vmcs_write16(HOST_GS_SELECTOR, 0);
1624                 vmx->host_state.gs_ldt_reload_needed = 1;
1625         }
1626
1627 #ifdef CONFIG_X86_64
1628         savesegment(ds, vmx->host_state.ds_sel);
1629         savesegment(es, vmx->host_state.es_sel);
1630 #endif
1631
1632 #ifdef CONFIG_X86_64
1633         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635 #else
1636         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1638 #endif
1639
1640 #ifdef CONFIG_X86_64
1641         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642         if (is_long_mode(&vmx->vcpu))
1643                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1644 #endif
1645         for (i = 0; i < vmx->save_nmsrs; ++i)
1646                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1647                                    vmx->guest_msrs[i].data,
1648                                    vmx->guest_msrs[i].mask);
1649 }
1650
1651 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1652 {
1653         if (!vmx->host_state.loaded)
1654                 return;
1655
1656         ++vmx->vcpu.stat.host_state_reload;
1657         vmx->host_state.loaded = 0;
1658 #ifdef CONFIG_X86_64
1659         if (is_long_mode(&vmx->vcpu))
1660                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661 #endif
1662         if (vmx->host_state.gs_ldt_reload_needed) {
1663                 kvm_load_ldt(vmx->host_state.ldt_sel);
1664 #ifdef CONFIG_X86_64
1665                 load_gs_index(vmx->host_state.gs_sel);
1666 #else
1667                 loadsegment(gs, vmx->host_state.gs_sel);
1668 #endif
1669         }
1670         if (vmx->host_state.fs_reload_needed)
1671                 loadsegment(fs, vmx->host_state.fs_sel);
1672 #ifdef CONFIG_X86_64
1673         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674                 loadsegment(ds, vmx->host_state.ds_sel);
1675                 loadsegment(es, vmx->host_state.es_sel);
1676         }
1677 #endif
1678         reload_tss();
1679 #ifdef CONFIG_X86_64
1680         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1681 #endif
1682         /*
1683          * If the FPU is not active (through the host task or
1684          * the guest vcpu), then restore the cr0.TS bit.
1685          */
1686         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687                 stts();
1688         load_gdt(&__get_cpu_var(host_gdt));
1689 }
1690
1691 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692 {
1693         preempt_disable();
1694         __vmx_load_host_state(vmx);
1695         preempt_enable();
1696 }
1697
1698 /*
1699  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1700  * vcpu mutex is already taken.
1701  */
1702 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1703 {
1704         struct vcpu_vmx *vmx = to_vmx(vcpu);
1705         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1706
1707         if (!vmm_exclusive)
1708                 kvm_cpu_vmxon(phys_addr);
1709         else if (vmx->loaded_vmcs->cpu != cpu)
1710                 loaded_vmcs_clear(vmx->loaded_vmcs);
1711
1712         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714                 vmcs_load(vmx->loaded_vmcs->vmcs);
1715         }
1716
1717         if (vmx->loaded_vmcs->cpu != cpu) {
1718                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1719                 unsigned long sysenter_esp;
1720
1721                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1722                 local_irq_disable();
1723                 crash_disable_local_vmclear(cpu);
1724
1725                 /*
1726                  * Read loaded_vmcs->cpu should be before fetching
1727                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1728                  * See the comments in __loaded_vmcs_clear().
1729                  */
1730                 smp_rmb();
1731
1732                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1734                 crash_enable_local_vmclear(cpu);
1735                 local_irq_enable();
1736
1737                 /*
1738                  * Linux uses per-cpu TSS and GDT, so set these when switching
1739                  * processors.
1740                  */
1741                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1742                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1743
1744                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1746                 vmx->loaded_vmcs->cpu = cpu;
1747         }
1748 }
1749
1750 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751 {
1752         __vmx_load_host_state(to_vmx(vcpu));
1753         if (!vmm_exclusive) {
1754                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755                 vcpu->cpu = -1;
1756                 kvm_cpu_vmxoff();
1757         }
1758 }
1759
1760 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761 {
1762         ulong cr0;
1763
1764         if (vcpu->fpu_active)
1765                 return;
1766         vcpu->fpu_active = 1;
1767         cr0 = vmcs_readl(GUEST_CR0);
1768         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770         vmcs_writel(GUEST_CR0, cr0);
1771         update_exception_bitmap(vcpu);
1772         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1773         if (is_guest_mode(vcpu))
1774                 vcpu->arch.cr0_guest_owned_bits &=
1775                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1776         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1777 }
1778
1779 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
1781 /*
1782  * Return the cr0 value that a nested guest would read. This is a combination
1783  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1784  * its hypervisor (cr0_read_shadow).
1785  */
1786 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787 {
1788         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790 }
1791 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795 }
1796
1797 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798 {
1799         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1800          * set this *before* calling this function.
1801          */
1802         vmx_decache_cr0_guest_bits(vcpu);
1803         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1804         update_exception_bitmap(vcpu);
1805         vcpu->arch.cr0_guest_owned_bits = 0;
1806         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1807         if (is_guest_mode(vcpu)) {
1808                 /*
1809                  * L1's specified read shadow might not contain the TS bit,
1810                  * so now that we turned on shadowing of this bit, we need to
1811                  * set this bit of the shadow. Like in nested_vmx_run we need
1812                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1813                  * up-to-date here because we just decached cr0.TS (and we'll
1814                  * only update vmcs12->guest_cr0 on nested exit).
1815                  */
1816                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818                         (vcpu->arch.cr0 & X86_CR0_TS);
1819                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820         } else
1821                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1822 }
1823
1824 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825 {
1826         unsigned long rflags, save_rflags;
1827
1828         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830                 rflags = vmcs_readl(GUEST_RFLAGS);
1831                 if (to_vmx(vcpu)->rmode.vm86_active) {
1832                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835                 }
1836                 to_vmx(vcpu)->rflags = rflags;
1837         }
1838         return to_vmx(vcpu)->rflags;
1839 }
1840
1841 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842 {
1843         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844         to_vmx(vcpu)->rflags = rflags;
1845         if (to_vmx(vcpu)->rmode.vm86_active) {
1846                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1847                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1848         }
1849         vmcs_writel(GUEST_RFLAGS, rflags);
1850 }
1851
1852 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853 {
1854         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855         int ret = 0;
1856
1857         if (interruptibility & GUEST_INTR_STATE_STI)
1858                 ret |= KVM_X86_SHADOW_INT_STI;
1859         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1860                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1861
1862         return ret & mask;
1863 }
1864
1865 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866 {
1867         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868         u32 interruptibility = interruptibility_old;
1869
1870         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
1872         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1873                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1874         else if (mask & KVM_X86_SHADOW_INT_STI)
1875                 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877         if ((interruptibility != interruptibility_old))
1878                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879 }
1880
1881 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882 {
1883         unsigned long rip;
1884
1885         rip = kvm_rip_read(vcpu);
1886         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1887         kvm_rip_write(vcpu, rip);
1888
1889         /* skipping an emulated instruction also counts */
1890         vmx_set_interrupt_shadow(vcpu, 0);
1891 }
1892
1893 /*
1894  * KVM wants to inject page-faults which it got to the guest. This function
1895  * checks whether in a nested guest, we need to inject them to L1 or L2.
1896  * This function assumes it is called with the exit reason in vmcs02 being
1897  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1898  * is running).
1899  */
1900 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901 {
1902         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1905         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1906                 return 0;
1907
1908         nested_vmx_vmexit(vcpu);
1909         return 1;
1910 }
1911
1912 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1913                                 bool has_error_code, u32 error_code,
1914                                 bool reinject)
1915 {
1916         struct vcpu_vmx *vmx = to_vmx(vcpu);
1917         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1918
1919         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1920             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1921                 return;
1922
1923         if (has_error_code) {
1924                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1925                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926         }
1927
1928         if (vmx->rmode.vm86_active) {
1929                 int inc_eip = 0;
1930                 if (kvm_exception_is_soft(nr))
1931                         inc_eip = vcpu->arch.event_exit_inst_len;
1932                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1933                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1934                 return;
1935         }
1936
1937         if (kvm_exception_is_soft(nr)) {
1938                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939                              vmx->vcpu.arch.event_exit_inst_len);
1940                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941         } else
1942                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1945 }
1946
1947 static bool vmx_rdtscp_supported(void)
1948 {
1949         return cpu_has_vmx_rdtscp();
1950 }
1951
1952 static bool vmx_invpcid_supported(void)
1953 {
1954         return cpu_has_vmx_invpcid() && enable_ept;
1955 }
1956
1957 /*
1958  * Swap MSR entry in host/guest MSR entry array.
1959  */
1960 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1961 {
1962         struct shared_msr_entry tmp;
1963
1964         tmp = vmx->guest_msrs[to];
1965         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966         vmx->guest_msrs[from] = tmp;
1967 }
1968
1969 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970 {
1971         unsigned long *msr_bitmap;
1972
1973         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974                 if (is_long_mode(vcpu))
1975                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976                 else
1977                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978         } else {
1979                 if (is_long_mode(vcpu))
1980                         msr_bitmap = vmx_msr_bitmap_longmode;
1981                 else
1982                         msr_bitmap = vmx_msr_bitmap_legacy;
1983         }
1984
1985         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986 }
1987
1988 /*
1989  * Set up the vmcs to automatically save and restore system
1990  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1991  * mode, as fiddling with msrs is very expensive.
1992  */
1993 static void setup_msrs(struct vcpu_vmx *vmx)
1994 {
1995         int save_nmsrs, index;
1996
1997         save_nmsrs = 0;
1998 #ifdef CONFIG_X86_64
1999         if (is_long_mode(&vmx->vcpu)) {
2000                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2001                 if (index >= 0)
2002                         move_msr_up(vmx, index, save_nmsrs++);
2003                 index = __find_msr_index(vmx, MSR_LSTAR);
2004                 if (index >= 0)
2005                         move_msr_up(vmx, index, save_nmsrs++);
2006                 index = __find_msr_index(vmx, MSR_CSTAR);
2007                 if (index >= 0)
2008                         move_msr_up(vmx, index, save_nmsrs++);
2009                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010                 if (index >= 0 && vmx->rdtscp_enabled)
2011                         move_msr_up(vmx, index, save_nmsrs++);
2012                 /*
2013                  * MSR_STAR is only needed on long mode guests, and only
2014                  * if efer.sce is enabled.
2015                  */
2016                 index = __find_msr_index(vmx, MSR_STAR);
2017                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2018                         move_msr_up(vmx, index, save_nmsrs++);
2019         }
2020 #endif
2021         index = __find_msr_index(vmx, MSR_EFER);
2022         if (index >= 0 && update_transition_efer(vmx, index))
2023                 move_msr_up(vmx, index, save_nmsrs++);
2024
2025         vmx->save_nmsrs = save_nmsrs;
2026
2027         if (cpu_has_vmx_msr_bitmap())
2028                 vmx_set_msr_bitmap(&vmx->vcpu);
2029 }
2030
2031 /*
2032  * reads and returns guest's timestamp counter "register"
2033  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2034  */
2035 static u64 guest_read_tsc(void)
2036 {
2037         u64 host_tsc, tsc_offset;
2038
2039         rdtscll(host_tsc);
2040         tsc_offset = vmcs_read64(TSC_OFFSET);
2041         return host_tsc + tsc_offset;
2042 }
2043
2044 /*
2045  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2046  * counter, even if a nested guest (L2) is currently running.
2047  */
2048 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2049 {
2050         u64 tsc_offset;
2051
2052         tsc_offset = is_guest_mode(vcpu) ?
2053                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054                 vmcs_read64(TSC_OFFSET);
2055         return host_tsc + tsc_offset;
2056 }
2057
2058 /*
2059  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2060  * software catchup for faster rates on slower CPUs.
2061  */
2062 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2063 {
2064         if (!scale)
2065                 return;
2066
2067         if (user_tsc_khz > tsc_khz) {
2068                 vcpu->arch.tsc_catchup = 1;
2069                 vcpu->arch.tsc_always_catchup = 1;
2070         } else
2071                 WARN(1, "user requested TSC rate below hardware speed\n");
2072 }
2073
2074 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075 {
2076         return vmcs_read64(TSC_OFFSET);
2077 }
2078
2079 /*
2080  * writes 'offset' into guest's timestamp counter offset register
2081  */
2082 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2083 {
2084         if (is_guest_mode(vcpu)) {
2085                 /*
2086                  * We're here if L1 chose not to trap WRMSR to TSC. According
2087                  * to the spec, this should set L1's TSC; The offset that L1
2088                  * set for L2 remains unchanged, and still needs to be added
2089                  * to the newly set TSC to get L2's TSC.
2090                  */
2091                 struct vmcs12 *vmcs12;
2092                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093                 /* recalculate vmcs02.TSC_OFFSET: */
2094                 vmcs12 = get_vmcs12(vcpu);
2095                 vmcs_write64(TSC_OFFSET, offset +
2096                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097                          vmcs12->tsc_offset : 0));
2098         } else {
2099                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2100                                            vmcs_read64(TSC_OFFSET), offset);
2101                 vmcs_write64(TSC_OFFSET, offset);
2102         }
2103 }
2104
2105 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2106 {
2107         u64 offset = vmcs_read64(TSC_OFFSET);
2108
2109         vmcs_write64(TSC_OFFSET, offset + adjustment);
2110         if (is_guest_mode(vcpu)) {
2111                 /* Even when running L2, the adjustment needs to apply to L1 */
2112                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2113         } else
2114                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2115                                            offset + adjustment);
2116 }
2117
2118 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2119 {
2120         return target_tsc - native_read_tsc();
2121 }
2122
2123 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2124 {
2125         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2126         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2127 }
2128
2129 /*
2130  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2131  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2132  * all guests if the "nested" module option is off, and can also be disabled
2133  * for a single guest by disabling its VMX cpuid bit.
2134  */
2135 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2136 {
2137         return nested && guest_cpuid_has_vmx(vcpu);
2138 }
2139
2140 /*
2141  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2142  * returned for the various VMX controls MSRs when nested VMX is enabled.
2143  * The same values should also be used to verify that vmcs12 control fields are
2144  * valid during nested entry from L1 to L2.
2145  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2146  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2147  * bit in the high half is on if the corresponding bit in the control field
2148  * may be on. See also vmx_control_verify().
2149  * TODO: allow these variables to be modified (downgraded) by module options
2150  * or other means.
2151  */
2152 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2153 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2154 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2155 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2156 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2157 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2158 static __init void nested_vmx_setup_ctls_msrs(void)
2159 {
2160         /*
2161          * Note that as a general rule, the high half of the MSRs (bits in
2162          * the control fields which may be 1) should be initialized by the
2163          * intersection of the underlying hardware's MSR (i.e., features which
2164          * can be supported) and the list of features we want to expose -
2165          * because they are known to be properly supported in our code.
2166          * Also, usually, the low half of the MSRs (bits which must be 1) can
2167          * be set to 0, meaning that L1 may turn off any of these bits. The
2168          * reason is that if one of these bits is necessary, it will appear
2169          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2170          * fields of vmcs01 and vmcs02, will turn these bits off - and
2171          * nested_vmx_exit_handled() will not pass related exits to L1.
2172          * These rules have exceptions below.
2173          */
2174
2175         /* pin-based controls */
2176         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2177               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2178         /*
2179          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2180          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2181          */
2182         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2183         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2184                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2185                 PIN_BASED_VMX_PREEMPTION_TIMER;
2186         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2187
2188         /*
2189          * Exit controls
2190          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2191          * 17 must be 1.
2192          */
2193         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2194         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2195 #ifdef CONFIG_X86_64
2196         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2197 #else
2198         nested_vmx_exit_ctls_high = 0;
2199 #endif
2200         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2201
2202         /* entry controls */
2203         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2204                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2205         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2206         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2207         nested_vmx_entry_ctls_high &=
2208                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2209         nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2210
2211         /* cpu-based controls */
2212         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2213                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2214         nested_vmx_procbased_ctls_low = 0;
2215         nested_vmx_procbased_ctls_high &=
2216                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2217                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2218                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2219                 CPU_BASED_CR3_STORE_EXITING |
2220 #ifdef CONFIG_X86_64
2221                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2222 #endif
2223                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2224                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2225                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2226                 CPU_BASED_PAUSE_EXITING |
2227                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2228         /*
2229          * We can allow some features even when not supported by the
2230          * hardware. For example, L1 can specify an MSR bitmap - and we
2231          * can use it to avoid exits to L1 - even when L0 runs L2
2232          * without MSR bitmaps.
2233          */
2234         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2235
2236         /* secondary cpu-based controls */
2237         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2238                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2239         nested_vmx_secondary_ctls_low = 0;
2240         nested_vmx_secondary_ctls_high &=
2241                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2242                 SECONDARY_EXEC_WBINVD_EXITING;
2243
2244         /* miscellaneous data */
2245         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2246         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2247                 VMX_MISC_SAVE_EFER_LMA;
2248         nested_vmx_misc_high = 0;
2249 }
2250
2251 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2252 {
2253         /*
2254          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2255          */
2256         return ((control & high) | low) == control;
2257 }
2258
2259 static inline u64 vmx_control_msr(u32 low, u32 high)
2260 {
2261         return low | ((u64)high << 32);
2262 }
2263
2264 /*
2265  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2266  * also let it use VMX-specific MSRs.
2267  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2268  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2269  * like all other MSRs).
2270  */
2271 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2272 {
2273         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2274                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2275                 /*
2276                  * According to the spec, processors which do not support VMX
2277                  * should throw a #GP(0) when VMX capability MSRs are read.
2278                  */
2279                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2280                 return 1;
2281         }
2282
2283         switch (msr_index) {
2284         case MSR_IA32_FEATURE_CONTROL:
2285                 *pdata = 0;
2286                 break;
2287         case MSR_IA32_VMX_BASIC:
2288                 /*
2289                  * This MSR reports some information about VMX support. We
2290                  * should return information about the VMX we emulate for the
2291                  * guest, and the VMCS structure we give it - not about the
2292                  * VMX support of the underlying hardware.
2293                  */
2294                 *pdata = VMCS12_REVISION |
2295                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2296                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2297                 break;
2298         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2299         case MSR_IA32_VMX_PINBASED_CTLS:
2300                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2301                                         nested_vmx_pinbased_ctls_high);
2302                 break;
2303         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2304         case MSR_IA32_VMX_PROCBASED_CTLS:
2305                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2306                                         nested_vmx_procbased_ctls_high);
2307                 break;
2308         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2309         case MSR_IA32_VMX_EXIT_CTLS:
2310                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2311                                         nested_vmx_exit_ctls_high);
2312                 break;
2313         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2314         case MSR_IA32_VMX_ENTRY_CTLS:
2315                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2316                                         nested_vmx_entry_ctls_high);
2317                 break;
2318         case MSR_IA32_VMX_MISC:
2319                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2320                                          nested_vmx_misc_high);
2321                 break;
2322         /*
2323          * These MSRs specify bits which the guest must keep fixed (on or off)
2324          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2325          * We picked the standard core2 setting.
2326          */
2327 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2328 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2329         case MSR_IA32_VMX_CR0_FIXED0:
2330                 *pdata = VMXON_CR0_ALWAYSON;
2331                 break;
2332         case MSR_IA32_VMX_CR0_FIXED1:
2333                 *pdata = -1ULL;
2334                 break;
2335         case MSR_IA32_VMX_CR4_FIXED0:
2336                 *pdata = VMXON_CR4_ALWAYSON;
2337                 break;
2338         case MSR_IA32_VMX_CR4_FIXED1:
2339                 *pdata = -1ULL;
2340                 break;
2341         case MSR_IA32_VMX_VMCS_ENUM:
2342                 *pdata = 0x1f;
2343                 break;
2344         case MSR_IA32_VMX_PROCBASED_CTLS2:
2345                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2346                                         nested_vmx_secondary_ctls_high);
2347                 break;
2348         case MSR_IA32_VMX_EPT_VPID_CAP:
2349                 /* Currently, no nested ept or nested vpid */
2350                 *pdata = 0;
2351                 break;
2352         default:
2353                 return 0;
2354         }
2355
2356         return 1;
2357 }
2358
2359 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2360 {
2361         if (!nested_vmx_allowed(vcpu))
2362                 return 0;
2363
2364         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2365                 /* TODO: the right thing. */
2366                 return 1;
2367         /*
2368          * No need to treat VMX capability MSRs specially: If we don't handle
2369          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2370          */
2371         return 0;
2372 }
2373
2374 /*
2375  * Reads an msr value (of 'msr_index') into 'pdata'.
2376  * Returns 0 on success, non-0 otherwise.
2377  * Assumes vcpu_load() was already called.
2378  */
2379 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2380 {
2381         u64 data;
2382         struct shared_msr_entry *msr;
2383
2384         if (!pdata) {
2385                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2386                 return -EINVAL;
2387         }
2388
2389         switch (msr_index) {
2390 #ifdef CONFIG_X86_64
2391         case MSR_FS_BASE:
2392                 data = vmcs_readl(GUEST_FS_BASE);
2393                 break;
2394         case MSR_GS_BASE:
2395                 data = vmcs_readl(GUEST_GS_BASE);
2396                 break;
2397         case MSR_KERNEL_GS_BASE:
2398                 vmx_load_host_state(to_vmx(vcpu));
2399                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2400                 break;
2401 #endif
2402         case MSR_EFER:
2403                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2404         case MSR_IA32_TSC:
2405                 data = guest_read_tsc();
2406                 break;
2407         case MSR_IA32_SYSENTER_CS:
2408                 data = vmcs_read32(GUEST_SYSENTER_CS);
2409                 break;
2410         case MSR_IA32_SYSENTER_EIP:
2411                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2412                 break;
2413         case MSR_IA32_SYSENTER_ESP:
2414                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2415                 break;
2416         case MSR_TSC_AUX:
2417                 if (!to_vmx(vcpu)->rdtscp_enabled)
2418                         return 1;
2419                 /* Otherwise falls through */
2420         default:
2421                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2422                         return 0;
2423                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2424                 if (msr) {
2425                         data = msr->data;
2426                         break;
2427                 }
2428                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2429         }
2430
2431         *pdata = data;
2432         return 0;
2433 }
2434
2435 /*
2436  * Writes msr value into into the appropriate "register".
2437  * Returns 0 on success, non-0 otherwise.
2438  * Assumes vcpu_load() was already called.
2439  */
2440 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2441 {
2442         struct vcpu_vmx *vmx = to_vmx(vcpu);
2443         struct shared_msr_entry *msr;
2444         int ret = 0;
2445         u32 msr_index = msr_info->index;
2446         u64 data = msr_info->data;
2447
2448         switch (msr_index) {
2449         case MSR_EFER:
2450                 ret = kvm_set_msr_common(vcpu, msr_info);
2451                 break;
2452 #ifdef CONFIG_X86_64
2453         case MSR_FS_BASE:
2454                 vmx_segment_cache_clear(vmx);
2455                 vmcs_writel(GUEST_FS_BASE, data);
2456                 break;
2457         case MSR_GS_BASE:
2458                 vmx_segment_cache_clear(vmx);
2459                 vmcs_writel(GUEST_GS_BASE, data);
2460                 break;
2461         case MSR_KERNEL_GS_BASE:
2462                 vmx_load_host_state(vmx);
2463                 vmx->msr_guest_kernel_gs_base = data;
2464                 break;
2465 #endif
2466         case MSR_IA32_SYSENTER_CS:
2467                 vmcs_write32(GUEST_SYSENTER_CS, data);
2468                 break;
2469         case MSR_IA32_SYSENTER_EIP:
2470                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2471                 break;
2472         case MSR_IA32_SYSENTER_ESP:
2473                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2474                 break;
2475         case MSR_IA32_TSC:
2476                 kvm_write_tsc(vcpu, msr_info);
2477                 break;
2478         case MSR_IA32_CR_PAT:
2479                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2480                         vmcs_write64(GUEST_IA32_PAT, data);
2481                         vcpu->arch.pat = data;
2482                         break;
2483                 }
2484                 ret = kvm_set_msr_common(vcpu, msr_info);
2485                 break;
2486         case MSR_IA32_TSC_ADJUST:
2487                 ret = kvm_set_msr_common(vcpu, msr_info);
2488                 break;
2489         case MSR_TSC_AUX:
2490                 if (!vmx->rdtscp_enabled)
2491                         return 1;
2492                 /* Check reserved bit, higher 32 bits should be zero */
2493                 if ((data >> 32) != 0)
2494                         return 1;
2495                 /* Otherwise falls through */
2496         default:
2497                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2498                         break;
2499                 msr = find_msr_entry(vmx, msr_index);
2500                 if (msr) {
2501                         msr->data = data;
2502                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2503                                 preempt_disable();
2504                                 kvm_set_shared_msr(msr->index, msr->data,
2505                                                    msr->mask);
2506                                 preempt_enable();
2507                         }
2508                         break;
2509                 }
2510                 ret = kvm_set_msr_common(vcpu, msr_info);
2511         }
2512
2513         return ret;
2514 }
2515
2516 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2517 {
2518         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2519         switch (reg) {
2520         case VCPU_REGS_RSP:
2521                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2522                 break;
2523         case VCPU_REGS_RIP:
2524                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2525                 break;
2526         case VCPU_EXREG_PDPTR:
2527                 if (enable_ept)
2528                         ept_save_pdptrs(vcpu);
2529                 break;
2530         default:
2531                 break;
2532         }
2533 }
2534
2535 static __init int cpu_has_kvm_support(void)
2536 {
2537         return cpu_has_vmx();
2538 }
2539
2540 static __init int vmx_disabled_by_bios(void)
2541 {
2542         u64 msr;
2543
2544         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2545         if (msr & FEATURE_CONTROL_LOCKED) {
2546                 /* launched w/ TXT and VMX disabled */
2547                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2548                         && tboot_enabled())
2549                         return 1;
2550                 /* launched w/o TXT and VMX only enabled w/ TXT */
2551                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2552                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2553                         && !tboot_enabled()) {
2554                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2555                                 "activate TXT before enabling KVM\n");
2556                         return 1;
2557                 }
2558                 /* launched w/o TXT and VMX disabled */
2559                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2560                         && !tboot_enabled())
2561                         return 1;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static void kvm_cpu_vmxon(u64 addr)
2568 {
2569         asm volatile (ASM_VMX_VMXON_RAX
2570                         : : "a"(&addr), "m"(addr)
2571                         : "memory", "cc");
2572 }
2573
2574 static int hardware_enable(void *garbage)
2575 {
2576         int cpu = raw_smp_processor_id();
2577         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2578         u64 old, test_bits;
2579
2580         if (read_cr4() & X86_CR4_VMXE)
2581                 return -EBUSY;
2582
2583         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2584
2585         /*
2586          * Now we can enable the vmclear operation in kdump
2587          * since the loaded_vmcss_on_cpu list on this cpu
2588          * has been initialized.
2589          *
2590          * Though the cpu is not in VMX operation now, there
2591          * is no problem to enable the vmclear operation
2592          * for the loaded_vmcss_on_cpu list is empty!
2593          */
2594         crash_enable_local_vmclear(cpu);
2595
2596         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2597
2598         test_bits = FEATURE_CONTROL_LOCKED;
2599         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2600         if (tboot_enabled())
2601                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2602
2603         if ((old & test_bits) != test_bits) {
2604                 /* enable and lock */
2605                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2606         }
2607         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2608
2609         if (vmm_exclusive) {
2610                 kvm_cpu_vmxon(phys_addr);
2611                 ept_sync_global();
2612         }
2613
2614         native_store_gdt(&__get_cpu_var(host_gdt));
2615
2616         return 0;
2617 }
2618
2619 static void vmclear_local_loaded_vmcss(void)
2620 {
2621         int cpu = raw_smp_processor_id();
2622         struct loaded_vmcs *v, *n;
2623
2624         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2625                                  loaded_vmcss_on_cpu_link)
2626                 __loaded_vmcs_clear(v);
2627 }
2628
2629
2630 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2631  * tricks.
2632  */
2633 static void kvm_cpu_vmxoff(void)
2634 {
2635         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2636 }
2637
2638 static void hardware_disable(void *garbage)
2639 {
2640         if (vmm_exclusive) {
2641                 vmclear_local_loaded_vmcss();
2642                 kvm_cpu_vmxoff();
2643         }
2644         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2645 }
2646
2647 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2648                                       u32 msr, u32 *result)
2649 {
2650         u32 vmx_msr_low, vmx_msr_high;
2651         u32 ctl = ctl_min | ctl_opt;
2652
2653         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2654
2655         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2656         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2657
2658         /* Ensure minimum (required) set of control bits are supported. */
2659         if (ctl_min & ~ctl)
2660                 return -EIO;
2661
2662         *result = ctl;
2663         return 0;
2664 }
2665
2666 static __init bool allow_1_setting(u32 msr, u32 ctl)
2667 {
2668         u32 vmx_msr_low, vmx_msr_high;
2669
2670         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2671         return vmx_msr_high & ctl;
2672 }
2673
2674 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2675 {
2676         u32 vmx_msr_low, vmx_msr_high;
2677         u32 min, opt, min2, opt2;
2678         u32 _pin_based_exec_control = 0;
2679         u32 _cpu_based_exec_control = 0;
2680         u32 _cpu_based_2nd_exec_control = 0;
2681         u32 _vmexit_control = 0;
2682         u32 _vmentry_control = 0;
2683
2684         min = CPU_BASED_HLT_EXITING |
2685 #ifdef CONFIG_X86_64
2686               CPU_BASED_CR8_LOAD_EXITING |
2687               CPU_BASED_CR8_STORE_EXITING |
2688 #endif
2689               CPU_BASED_CR3_LOAD_EXITING |
2690               CPU_BASED_CR3_STORE_EXITING |
2691               CPU_BASED_USE_IO_BITMAPS |
2692               CPU_BASED_MOV_DR_EXITING |
2693               CPU_BASED_USE_TSC_OFFSETING |
2694               CPU_BASED_MWAIT_EXITING |
2695               CPU_BASED_MONITOR_EXITING |
2696               CPU_BASED_INVLPG_EXITING |
2697               CPU_BASED_RDPMC_EXITING;
2698
2699         opt = CPU_BASED_TPR_SHADOW |
2700               CPU_BASED_USE_MSR_BITMAPS |
2701               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2702         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2703                                 &_cpu_based_exec_control) < 0)
2704                 return -EIO;
2705 #ifdef CONFIG_X86_64
2706         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2707                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2708                                            ~CPU_BASED_CR8_STORE_EXITING;
2709 #endif
2710         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2711                 min2 = 0;
2712                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2713                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2714                         SECONDARY_EXEC_WBINVD_EXITING |
2715                         SECONDARY_EXEC_ENABLE_VPID |
2716                         SECONDARY_EXEC_ENABLE_EPT |
2717                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2718                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2719                         SECONDARY_EXEC_RDTSCP |
2720                         SECONDARY_EXEC_ENABLE_INVPCID |
2721                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2722                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2723                         SECONDARY_EXEC_SHADOW_VMCS;
2724                 if (adjust_vmx_controls(min2, opt2,
2725                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2726                                         &_cpu_based_2nd_exec_control) < 0)
2727                         return -EIO;
2728         }
2729 #ifndef CONFIG_X86_64
2730         if (!(_cpu_based_2nd_exec_control &
2731                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2732                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2733 #endif
2734
2735         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2736                 _cpu_based_2nd_exec_control &= ~(
2737                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2738                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2739                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2740
2741         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2742                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2743                    enabled */
2744                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2745                                              CPU_BASED_CR3_STORE_EXITING |
2746                                              CPU_BASED_INVLPG_EXITING);
2747                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2748                       vmx_capability.ept, vmx_capability.vpid);
2749         }
2750
2751         min = 0;
2752 #ifdef CONFIG_X86_64
2753         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2754 #endif
2755         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2756                 VM_EXIT_ACK_INTR_ON_EXIT;
2757         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2758                                 &_vmexit_control) < 0)
2759                 return -EIO;
2760
2761         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2762         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2763         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2764                                 &_pin_based_exec_control) < 0)
2765                 return -EIO;
2766
2767         if (!(_cpu_based_2nd_exec_control &
2768                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2769                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2770                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2771
2772         min = 0;
2773         opt = VM_ENTRY_LOAD_IA32_PAT;
2774         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2775                                 &_vmentry_control) < 0)
2776                 return -EIO;
2777
2778         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2779
2780         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2781         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2782                 return -EIO;
2783
2784 #ifdef CONFIG_X86_64
2785         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2786         if (vmx_msr_high & (1u<<16))
2787                 return -EIO;
2788 #endif
2789
2790         /* Require Write-Back (WB) memory type for VMCS accesses. */
2791         if (((vmx_msr_high >> 18) & 15) != 6)
2792                 return -EIO;
2793
2794         vmcs_conf->size = vmx_msr_high & 0x1fff;
2795         vmcs_conf->order = get_order(vmcs_config.size);
2796         vmcs_conf->revision_id = vmx_msr_low;
2797
2798         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2799         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2800         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2801         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2802         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2803
2804         cpu_has_load_ia32_efer =
2805                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2806                                 VM_ENTRY_LOAD_IA32_EFER)
2807                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2808                                    VM_EXIT_LOAD_IA32_EFER);
2809
2810         cpu_has_load_perf_global_ctrl =
2811                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2812                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2813                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2814                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2815
2816         /*
2817          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2818          * but due to arrata below it can't be used. Workaround is to use
2819          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2820          *
2821          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2822          *
2823          * AAK155             (model 26)
2824          * AAP115             (model 30)
2825          * AAT100             (model 37)
2826          * BC86,AAY89,BD102   (model 44)
2827          * BA97               (model 46)
2828          *
2829          */
2830         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2831                 switch (boot_cpu_data.x86_model) {
2832                 case 26:
2833                 case 30:
2834                 case 37:
2835                 case 44:
2836                 case 46:
2837                         cpu_has_load_perf_global_ctrl = false;
2838                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2839                                         "does not work properly. Using workaround\n");
2840                         break;
2841                 default:
2842                         break;
2843                 }
2844         }
2845
2846         return 0;
2847 }
2848
2849 static struct vmcs *alloc_vmcs_cpu(int cpu)
2850 {
2851         int node = cpu_to_node(cpu);
2852         struct page *pages;
2853         struct vmcs *vmcs;
2854
2855         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2856         if (!pages)
2857                 return NULL;
2858         vmcs = page_address(pages);
2859         memset(vmcs, 0, vmcs_config.size);
2860         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2861         return vmcs;
2862 }
2863
2864 static struct vmcs *alloc_vmcs(void)
2865 {
2866         return alloc_vmcs_cpu(raw_smp_processor_id());
2867 }
2868
2869 static void free_vmcs(struct vmcs *vmcs)
2870 {
2871         free_pages((unsigned long)vmcs, vmcs_config.order);
2872 }
2873
2874 /*
2875  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2876  */
2877 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2878 {
2879         if (!loaded_vmcs->vmcs)
2880                 return;
2881         loaded_vmcs_clear(loaded_vmcs);
2882         free_vmcs(loaded_vmcs->vmcs);
2883         loaded_vmcs->vmcs = NULL;
2884 }
2885
2886 static void free_kvm_area(void)
2887 {
2888         int cpu;
2889
2890         for_each_possible_cpu(cpu) {
2891                 free_vmcs(per_cpu(vmxarea, cpu));
2892                 per_cpu(vmxarea, cpu) = NULL;
2893         }
2894 }
2895
2896 static __init int alloc_kvm_area(void)
2897 {
2898         int cpu;
2899
2900         for_each_possible_cpu(cpu) {
2901                 struct vmcs *vmcs;
2902
2903                 vmcs = alloc_vmcs_cpu(cpu);
2904                 if (!vmcs) {
2905                         free_kvm_area();
2906                         return -ENOMEM;
2907                 }
2908
2909                 per_cpu(vmxarea, cpu) = vmcs;
2910         }
2911         return 0;
2912 }
2913
2914 static __init int hardware_setup(void)
2915 {
2916         if (setup_vmcs_config(&vmcs_config) < 0)
2917                 return -EIO;
2918
2919         if (boot_cpu_has(X86_FEATURE_NX))
2920                 kvm_enable_efer_bits(EFER_NX);
2921
2922         if (!cpu_has_vmx_vpid())
2923                 enable_vpid = 0;
2924         if (!cpu_has_vmx_shadow_vmcs())
2925                 enable_shadow_vmcs = 0;
2926
2927         if (!cpu_has_vmx_ept() ||
2928             !cpu_has_vmx_ept_4levels()) {
2929                 enable_ept = 0;
2930                 enable_unrestricted_guest = 0;
2931                 enable_ept_ad_bits = 0;
2932         }
2933
2934         if (!cpu_has_vmx_ept_ad_bits())
2935                 enable_ept_ad_bits = 0;
2936
2937         if (!cpu_has_vmx_unrestricted_guest())
2938                 enable_unrestricted_guest = 0;
2939
2940         if (!cpu_has_vmx_flexpriority())
2941                 flexpriority_enabled = 0;
2942
2943         if (!cpu_has_vmx_tpr_shadow())
2944                 kvm_x86_ops->update_cr8_intercept = NULL;
2945
2946         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2947                 kvm_disable_largepages();
2948
2949         if (!cpu_has_vmx_ple())
2950                 ple_gap = 0;
2951
2952         if (!cpu_has_vmx_apicv())
2953                 enable_apicv = 0;
2954
2955         if (enable_apicv)
2956                 kvm_x86_ops->update_cr8_intercept = NULL;
2957         else {
2958                 kvm_x86_ops->hwapic_irr_update = NULL;
2959                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2960                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2961         }
2962
2963         if (nested)
2964                 nested_vmx_setup_ctls_msrs();
2965
2966         return alloc_kvm_area();
2967 }
2968
2969 static __exit void hardware_unsetup(void)
2970 {
2971         free_kvm_area();
2972 }
2973
2974 static bool emulation_required(struct kvm_vcpu *vcpu)
2975 {
2976         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2977 }
2978
2979 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2980                 struct kvm_segment *save)
2981 {
2982         if (!emulate_invalid_guest_state) {
2983                 /*
2984                  * CS and SS RPL should be equal during guest entry according
2985                  * to VMX spec, but in reality it is not always so. Since vcpu
2986                  * is in the middle of the transition from real mode to
2987                  * protected mode it is safe to assume that RPL 0 is a good
2988                  * default value.
2989                  */
2990                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2991                         save->selector &= ~SELECTOR_RPL_MASK;
2992                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2993                 save->s = 1;
2994         }
2995         vmx_set_segment(vcpu, save, seg);
2996 }
2997
2998 static void enter_pmode(struct kvm_vcpu *vcpu)
2999 {
3000         unsigned long flags;
3001         struct vcpu_vmx *vmx = to_vmx(vcpu);
3002
3003         /*
3004          * Update real mode segment cache. It may be not up-to-date if sement
3005          * register was written while vcpu was in a guest mode.
3006          */
3007         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3008         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3009         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3010         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3011         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3012         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3013
3014         vmx->rmode.vm86_active = 0;
3015
3016         vmx_segment_cache_clear(vmx);
3017
3018         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3019
3020         flags = vmcs_readl(GUEST_RFLAGS);
3021         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3022         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3023         vmcs_writel(GUEST_RFLAGS, flags);
3024
3025         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3026                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3027
3028         update_exception_bitmap(vcpu);
3029
3030         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3031         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3032         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3033         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3034         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3035         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3036
3037         /* CPL is always 0 when CPU enters protected mode */
3038         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3039         vmx->cpl = 0;
3040 }
3041
3042 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3043 {
3044         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3045         struct kvm_segment var = *save;
3046
3047         var.dpl = 0x3;
3048         if (seg == VCPU_SREG_CS)
3049                 var.type = 0x3;
3050
3051         if (!emulate_invalid_guest_state) {
3052                 var.selector = var.base >> 4;
3053                 var.base = var.base & 0xffff0;
3054                 var.limit = 0xffff;
3055                 var.g = 0;
3056                 var.db = 0;
3057                 var.present = 1;
3058                 var.s = 1;
3059                 var.l = 0;
3060                 var.unusable = 0;
3061                 var.type = 0x3;
3062                 var.avl = 0;
3063                 if (save->base & 0xf)
3064                         printk_once(KERN_WARNING "kvm: segment base is not "
3065                                         "paragraph aligned when entering "
3066                                         "protected mode (seg=%d)", seg);
3067         }
3068
3069         vmcs_write16(sf->selector, var.selector);
3070         vmcs_write32(sf->base, var.base);
3071         vmcs_write32(sf->limit, var.limit);
3072         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3073 }
3074
3075 static void enter_rmode(struct kvm_vcpu *vcpu)
3076 {
3077         unsigned long flags;
3078         struct vcpu_vmx *vmx = to_vmx(vcpu);
3079
3080         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3081         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3082         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3083         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3084         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3085         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3086         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3087
3088         vmx->rmode.vm86_active = 1;
3089
3090         /*
3091          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3092          * vcpu. Warn the user that an update is overdue.
3093          */
3094         if (!vcpu->kvm->arch.tss_addr)
3095                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3096                              "called before entering vcpu\n");
3097
3098         vmx_segment_cache_clear(vmx);
3099
3100         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3101         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3102         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3103
3104         flags = vmcs_readl(GUEST_RFLAGS);
3105         vmx->rmode.save_rflags = flags;
3106
3107         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3108
3109         vmcs_writel(GUEST_RFLAGS, flags);
3110         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3111         update_exception_bitmap(vcpu);
3112
3113         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3114         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3115         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3116         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3117         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3118         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3119
3120         kvm_mmu_reset_context(vcpu);
3121 }
3122
3123 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3124 {
3125         struct vcpu_vmx *vmx = to_vmx(vcpu);
3126         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3127
3128         if (!msr)
3129                 return;
3130
3131         /*
3132          * Force kernel_gs_base reloading before EFER changes, as control
3133          * of this msr depends on is_long_mode().
3134          */
3135         vmx_load_host_state(to_vmx(vcpu));
3136         vcpu->arch.efer = efer;
3137         if (efer & EFER_LMA) {
3138                 vmcs_write32(VM_ENTRY_CONTROLS,
3139                              vmcs_read32(VM_ENTRY_CONTROLS) |
3140                              VM_ENTRY_IA32E_MODE);
3141                 msr->data = efer;
3142         } else {
3143                 vmcs_write32(VM_ENTRY_CONTROLS,
3144                              vmcs_read32(VM_ENTRY_CONTROLS) &
3145                              ~VM_ENTRY_IA32E_MODE);
3146
3147                 msr->data = efer & ~EFER_LME;
3148         }
3149         setup_msrs(vmx);
3150 }
3151
3152 #ifdef CONFIG_X86_64
3153
3154 static void enter_lmode(struct kvm_vcpu *vcpu)
3155 {
3156         u32 guest_tr_ar;
3157
3158         vmx_segment_cache_clear(to_vmx(vcpu));
3159
3160         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3161         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3162                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3163                                      __func__);
3164                 vmcs_write32(GUEST_TR_AR_BYTES,
3165                              (guest_tr_ar & ~AR_TYPE_MASK)
3166                              | AR_TYPE_BUSY_64_TSS);
3167         }
3168         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3169 }
3170
3171 static void exit_lmode(struct kvm_vcpu *vcpu)
3172 {
3173         vmcs_write32(VM_ENTRY_CONTROLS,
3174                      vmcs_read32(VM_ENTRY_CONTROLS)
3175                      & ~VM_ENTRY_IA32E_MODE);
3176         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3177 }
3178
3179 #endif
3180
3181 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3182 {
3183         vpid_sync_context(to_vmx(vcpu));
3184         if (enable_ept) {
3185                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3186                         return;
3187                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3188         }
3189 }
3190
3191 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3192 {
3193         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3194
3195         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3196         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3197 }
3198
3199 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3200 {
3201         if (enable_ept && is_paging(vcpu))
3202                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3203         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3204 }
3205
3206 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3207 {
3208         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3209
3210         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3211         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3212 }
3213
3214 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3215 {
3216         if (!test_bit(VCPU_EXREG_PDPTR,
3217                       (unsigned long *)&vcpu->arch.regs_dirty))
3218                 return;
3219
3220         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3221                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3222                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3223                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3224                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3225         }
3226 }
3227
3228 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3229 {
3230         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3231                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3232                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3233                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3234                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3235         }
3236
3237         __set_bit(VCPU_EXREG_PDPTR,
3238                   (unsigned long *)&vcpu->arch.regs_avail);
3239         __set_bit(VCPU_EXREG_PDPTR,
3240                   (unsigned long *)&vcpu->arch.regs_dirty);
3241 }
3242
3243 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3244
3245 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3246                                         unsigned long cr0,
3247                                         struct kvm_vcpu *vcpu)
3248 {
3249         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3250                 vmx_decache_cr3(vcpu);
3251         if (!(cr0 & X86_CR0_PG)) {
3252                 /* From paging/starting to nonpaging */
3253                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3254                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3255                              (CPU_BASED_CR3_LOAD_EXITING |
3256                               CPU_BASED_CR3_STORE_EXITING));
3257                 vcpu->arch.cr0 = cr0;
3258                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3259         } else if (!is_paging(vcpu)) {
3260                 /* From nonpaging to paging */
3261                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3262                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3263                              ~(CPU_BASED_CR3_LOAD_EXITING |
3264                                CPU_BASED_CR3_STORE_EXITING));
3265                 vcpu->arch.cr0 = cr0;
3266                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3267         }
3268
3269         if (!(cr0 & X86_CR0_WP))
3270                 *hw_cr0 &= ~X86_CR0_WP;
3271 }
3272
3273 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3274 {
3275         struct vcpu_vmx *vmx = to_vmx(vcpu);
3276         unsigned long hw_cr0;
3277
3278         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3279         if (enable_unrestricted_guest)
3280                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3281         else {
3282                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3283
3284                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3285                         enter_pmode(vcpu);
3286
3287                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3288                         enter_rmode(vcpu);
3289         }
3290
3291 #ifdef CONFIG_X86_64
3292         if (vcpu->arch.efer & EFER_LME) {
3293                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3294                         enter_lmode(vcpu);
3295                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3296                         exit_lmode(vcpu);
3297         }
3298 #endif
3299
3300         if (enable_ept)
3301                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3302
3303         if (!vcpu->fpu_active)
3304                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3305
3306         vmcs_writel(CR0_READ_SHADOW, cr0);
3307         vmcs_writel(GUEST_CR0, hw_cr0);
3308         vcpu->arch.cr0 = cr0;
3309
3310         /* depends on vcpu->arch.cr0 to be set to a new value */
3311         vmx->emulation_required = emulation_required(vcpu);
3312 }
3313
3314 static u64 construct_eptp(unsigned long root_hpa)
3315 {
3316         u64 eptp;
3317
3318         /* TODO write the value reading from MSR */
3319         eptp = VMX_EPT_DEFAULT_MT |
3320                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3321         if (enable_ept_ad_bits)
3322                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3323         eptp |= (root_hpa & PAGE_MASK);
3324
3325         return eptp;
3326 }
3327
3328 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3329 {
3330         unsigned long guest_cr3;
3331         u64 eptp;
3332
3333         guest_cr3 = cr3;
3334         if (enable_ept) {
3335                 eptp = construct_eptp(cr3);
3336                 vmcs_write64(EPT_POINTER, eptp);
3337                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3338                         vcpu->kvm->arch.ept_identity_map_addr;
3339                 ept_load_pdptrs(vcpu);
3340         }
3341
3342         vmx_flush_tlb(vcpu);
3343         vmcs_writel(GUEST_CR3, guest_cr3);
3344 }
3345
3346 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3347 {
3348         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3349                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3350
3351         if (cr4 & X86_CR4_VMXE) {
3352                 /*
3353                  * To use VMXON (and later other VMX instructions), a guest
3354                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3355                  * So basically the check on whether to allow nested VMX
3356                  * is here.
3357                  */
3358                 if (!nested_vmx_allowed(vcpu))
3359                         return 1;
3360         }
3361         if (to_vmx(vcpu)->nested.vmxon &&
3362             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3363                 return 1;
3364
3365         vcpu->arch.cr4 = cr4;
3366         if (enable_ept) {
3367                 if (!is_paging(vcpu)) {
3368                         hw_cr4 &= ~X86_CR4_PAE;
3369                         hw_cr4 |= X86_CR4_PSE;
3370                         /*
3371                          * SMEP is disabled if CPU is in non-paging mode in
3372                          * hardware. However KVM always uses paging mode to
3373                          * emulate guest non-paging mode with TDP.
3374                          * To emulate this behavior, SMEP needs to be manually
3375                          * disabled when guest switches to non-paging mode.
3376                          */
3377                         hw_cr4 &= ~X86_CR4_SMEP;
3378                 } else if (!(cr4 & X86_CR4_PAE)) {
3379                         hw_cr4 &= ~X86_CR4_PAE;
3380                 }
3381         }
3382
3383         vmcs_writel(CR4_READ_SHADOW, cr4);
3384         vmcs_writel(GUEST_CR4, hw_cr4);
3385         return 0;
3386 }
3387
3388 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3389                             struct kvm_segment *var, int seg)
3390 {
3391         struct vcpu_vmx *vmx = to_vmx(vcpu);
3392         u32 ar;
3393
3394         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3395                 *var = vmx->rmode.segs[seg];
3396                 if (seg == VCPU_SREG_TR
3397                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3398                         return;
3399                 var->base = vmx_read_guest_seg_base(vmx, seg);
3400                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401                 return;
3402         }
3403         var->base = vmx_read_guest_seg_base(vmx, seg);
3404         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3405         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3406         ar = vmx_read_guest_seg_ar(vmx, seg);
3407         var->type = ar & 15;
3408         var->s = (ar >> 4) & 1;
3409         var->dpl = (ar >> 5) & 3;
3410         var->present = (ar >> 7) & 1;
3411         var->avl = (ar >> 12) & 1;
3412         var->l = (ar >> 13) & 1;
3413         var->db = (ar >> 14) & 1;
3414         var->g = (ar >> 15) & 1;
3415         var->unusable = (ar >> 16) & 1;
3416 }
3417
3418 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3419 {
3420         struct kvm_segment s;
3421
3422         if (to_vmx(vcpu)->rmode.vm86_active) {
3423                 vmx_get_segment(vcpu, &s, seg);
3424                 return s.base;
3425         }
3426         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3427 }
3428
3429 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3430 {
3431         struct vcpu_vmx *vmx = to_vmx(vcpu);
3432
3433         if (!is_protmode(vcpu))
3434                 return 0;
3435
3436         if (!is_long_mode(vcpu)
3437             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3438                 return 3;
3439
3440         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3441                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3442                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3443         }
3444
3445         return vmx->cpl;
3446 }
3447
3448
3449 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3450 {
3451         u32 ar;
3452
3453         if (var->unusable || !var->present)
3454                 ar = 1 << 16;
3455         else {
3456                 ar = var->type & 15;
3457                 ar |= (var->s & 1) << 4;
3458                 ar |= (var->dpl & 3) << 5;
3459                 ar |= (var->present & 1) << 7;
3460                 ar |= (var->avl & 1) << 12;
3461                 ar |= (var->l & 1) << 13;
3462                 ar |= (var->db & 1) << 14;
3463                 ar |= (var->g & 1) << 15;
3464         }
3465
3466         return ar;
3467 }
3468
3469 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3470                             struct kvm_segment *var, int seg)
3471 {
3472         struct vcpu_vmx *vmx = to_vmx(vcpu);
3473         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3474
3475         vmx_segment_cache_clear(vmx);
3476         if (seg == VCPU_SREG_CS)
3477                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3478
3479         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3480                 vmx->rmode.segs[seg] = *var;
3481                 if (seg == VCPU_SREG_TR)
3482                         vmcs_write16(sf->selector, var->selector);
3483                 else if (var->s)
3484                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3485                 goto out;
3486         }
3487
3488         vmcs_writel(sf->base, var->base);
3489         vmcs_write32(sf->limit, var->limit);
3490         vmcs_write16(sf->selector, var->selector);
3491
3492         /*
3493          *   Fix the "Accessed" bit in AR field of segment registers for older
3494          * qemu binaries.
3495          *   IA32 arch specifies that at the time of processor reset the
3496          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3497          * is setting it to 0 in the userland code. This causes invalid guest
3498          * state vmexit when "unrestricted guest" mode is turned on.
3499          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3500          * tree. Newer qemu binaries with that qemu fix would not need this
3501          * kvm hack.
3502          */
3503         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3504                 var->type |= 0x1; /* Accessed */
3505
3506         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3507
3508 out:
3509         vmx->emulation_required |= emulation_required(vcpu);
3510 }
3511
3512 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3513 {
3514         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3515
3516         *db = (ar >> 14) & 1;
3517         *l = (ar >> 13) & 1;
3518 }
3519
3520 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3521 {
3522         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3523         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3524 }
3525
3526 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3527 {
3528         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3529         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3530 }
3531
3532 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3533 {
3534         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3535         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3536 }
3537
3538 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3539 {
3540         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3541         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3542 }
3543
3544 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3545 {
3546         struct kvm_segment var;
3547         u32 ar;
3548
3549         vmx_get_segment(vcpu, &var, seg);
3550         var.dpl = 0x3;
3551         if (seg == VCPU_SREG_CS)
3552                 var.type = 0x3;
3553         ar = vmx_segment_access_rights(&var);
3554
3555         if (var.base != (var.selector << 4))
3556                 return false;
3557         if (var.limit != 0xffff)
3558                 return false;
3559         if (ar != 0xf3)
3560                 return false;
3561
3562         return true;
3563 }
3564
3565 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3566 {
3567         struct kvm_segment cs;
3568         unsigned int cs_rpl;
3569
3570         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3571         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3572
3573         if (cs.unusable)
3574                 return false;
3575         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3576                 return false;
3577         if (!cs.s)
3578                 return false;
3579         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3580                 if (cs.dpl > cs_rpl)
3581                         return false;
3582         } else {
3583                 if (cs.dpl != cs_rpl)
3584                         return false;
3585         }
3586         if (!cs.present)
3587                 return false;
3588
3589         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3590         return true;
3591 }
3592
3593 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3594 {
3595         struct kvm_segment ss;
3596         unsigned int ss_rpl;
3597
3598         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3599         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3600
3601         if (ss.unusable)
3602                 return true;
3603         if (ss.type != 3 && ss.type != 7)
3604                 return false;
3605         if (!ss.s)
3606                 return false;
3607         if (ss.dpl != ss_rpl) /* DPL != RPL */
3608                 return false;
3609         if (!ss.present)
3610                 return false;
3611
3612         return true;
3613 }
3614
3615 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3616 {
3617         struct kvm_segment var;
3618         unsigned int rpl;
3619
3620         vmx_get_segment(vcpu, &var, seg);
3621         rpl = var.selector & SELECTOR_RPL_MASK;
3622
3623         if (var.unusable)
3624                 return true;
3625         if (!var.s)
3626                 return false;
3627         if (!var.present)
3628                 return false;
3629         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3630                 if (var.dpl < rpl) /* DPL < RPL */
3631                         return false;
3632         }
3633
3634         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3635          * rights flags
3636          */
3637         return true;
3638 }
3639
3640 static bool tr_valid(struct kvm_vcpu *vcpu)
3641 {
3642         struct kvm_segment tr;
3643
3644         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3645
3646         if (tr.unusable)
3647                 return false;
3648         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3649                 return false;
3650         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3651                 return false;
3652         if (!tr.present)
3653                 return false;
3654
3655         return true;
3656 }
3657
3658 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3659 {
3660         struct kvm_segment ldtr;
3661
3662         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3663
3664         if (ldtr.unusable)
3665                 return true;
3666         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3667                 return false;
3668         if (ldtr.type != 2)
3669                 return false;
3670         if (!ldtr.present)
3671                 return false;
3672
3673         return true;
3674 }
3675
3676 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3677 {
3678         struct kvm_segment cs, ss;
3679
3680         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3681         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3682
3683         return ((cs.selector & SELECTOR_RPL_MASK) ==
3684                  (ss.selector & SELECTOR_RPL_MASK));
3685 }
3686
3687 /*
3688  * Check if guest state is valid. Returns true if valid, false if
3689  * not.
3690  * We assume that registers are always usable
3691  */
3692 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3693 {
3694         if (enable_unrestricted_guest)
3695                 return true;
3696
3697         /* real mode guest state checks */
3698         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3699                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3700                         return false;
3701                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3702                         return false;
3703                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3704                         return false;
3705                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3706                         return false;
3707                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3708                         return false;
3709                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3710                         return false;
3711         } else {
3712         /* protected mode guest state checks */
3713                 if (!cs_ss_rpl_check(vcpu))
3714                         return false;
3715                 if (!code_segment_valid(vcpu))
3716                         return false;
3717                 if (!stack_segment_valid(vcpu))
3718                         return false;
3719                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3720                         return false;
3721                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3722                         return false;
3723                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3724                         return false;
3725                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3726                         return false;
3727                 if (!tr_valid(vcpu))
3728                         return false;
3729                 if (!ldtr_valid(vcpu))
3730                         return false;
3731         }
3732         /* TODO:
3733          * - Add checks on RIP
3734          * - Add checks on RFLAGS
3735          */
3736
3737         return true;
3738 }
3739
3740 static int init_rmode_tss(struct kvm *kvm)
3741 {
3742         gfn_t fn;
3743         u16 data = 0;
3744         int r, idx, ret = 0;
3745
3746         idx = srcu_read_lock(&kvm->srcu);
3747         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3748         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3749         if (r < 0)
3750                 goto out;
3751         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3752         r = kvm_write_guest_page(kvm, fn++, &data,
3753                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3754         if (r < 0)
3755                 goto out;
3756         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3757         if (r < 0)
3758                 goto out;
3759         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3760         if (r < 0)
3761                 goto out;
3762         data = ~0;
3763         r = kvm_write_guest_page(kvm, fn, &data,
3764                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3765                                  sizeof(u8));
3766         if (r < 0)
3767                 goto out;
3768
3769         ret = 1;
3770 out:
3771         srcu_read_unlock(&kvm->srcu, idx);
3772         return ret;
3773 }
3774
3775 static int init_rmode_identity_map(struct kvm *kvm)
3776 {
3777         int i, idx, r, ret;
3778         pfn_t identity_map_pfn;
3779         u32 tmp;
3780
3781         if (!enable_ept)
3782                 return 1;
3783         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3784                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3785                         "haven't been allocated!\n");
3786                 return 0;
3787         }
3788         if (likely(kvm->arch.ept_identity_pagetable_done))
3789                 return 1;
3790         ret = 0;
3791         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3792         idx = srcu_read_lock(&kvm->srcu);
3793         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3794         if (r < 0)
3795                 goto out;
3796         /* Set up identity-mapping pagetable for EPT in real mode */
3797         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3798                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3799                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3800                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3801                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3802                 if (r < 0)
3803                         goto out;
3804         }
3805         kvm->arch.ept_identity_pagetable_done = true;
3806         ret = 1;
3807 out:
3808         srcu_read_unlock(&kvm->srcu, idx);
3809         return ret;
3810 }
3811
3812 static void seg_setup(int seg)
3813 {
3814         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3815         unsigned int ar;
3816
3817         vmcs_write16(sf->selector, 0);
3818         vmcs_writel(sf->base, 0);
3819         vmcs_write32(sf->limit, 0xffff);
3820         ar = 0x93;
3821         if (seg == VCPU_SREG_CS)
3822                 ar |= 0x08; /* code segment */
3823
3824         vmcs_write32(sf->ar_bytes, ar);
3825 }
3826
3827 static int alloc_apic_access_page(struct kvm *kvm)
3828 {
3829         struct page *page;
3830         struct kvm_userspace_memory_region kvm_userspace_mem;
3831         int r = 0;
3832
3833         mutex_lock(&kvm->slots_lock);
3834         if (kvm->arch.apic_access_page)
3835                 goto out;
3836         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3837         kvm_userspace_mem.flags = 0;
3838         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3839         kvm_userspace_mem.memory_size = PAGE_SIZE;
3840         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3841         if (r)
3842                 goto out;
3843
3844         page = gfn_to_page(kvm, 0xfee00);
3845         if (is_error_page(page)) {
3846                 r = -EFAULT;
3847                 goto out;
3848         }
3849
3850         kvm->arch.apic_access_page = page;
3851 out:
3852         mutex_unlock(&kvm->slots_lock);
3853         return r;
3854 }
3855
3856 static int alloc_identity_pagetable(struct kvm *kvm)
3857 {
3858         struct page *page;
3859         struct kvm_userspace_memory_region kvm_userspace_mem;
3860         int r = 0;
3861
3862         mutex_lock(&kvm->slots_lock);
3863         if (kvm->arch.ept_identity_pagetable)
3864                 goto out;
3865         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3866         kvm_userspace_mem.flags = 0;
3867         kvm_userspace_mem.guest_phys_addr =
3868                 kvm->arch.ept_identity_map_addr;
3869         kvm_userspace_mem.memory_size = PAGE_SIZE;
3870         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3871         if (r)
3872                 goto out;
3873
3874         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3875         if (is_error_page(page)) {
3876                 r = -EFAULT;
3877                 goto out;
3878         }
3879
3880         kvm->arch.ept_identity_pagetable = page;
3881 out:
3882         mutex_unlock(&kvm->slots_lock);
3883         return r;
3884 }
3885
3886 static void allocate_vpid(struct vcpu_vmx *vmx)
3887 {
3888         int vpid;
3889
3890         vmx->vpid = 0;
3891         if (!enable_vpid)
3892                 return;
3893         spin_lock(&vmx_vpid_lock);
3894         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3895         if (vpid < VMX_NR_VPIDS) {
3896                 vmx->vpid = vpid;
3897                 __set_bit(vpid, vmx_vpid_bitmap);
3898         }
3899         spin_unlock(&vmx_vpid_lock);
3900 }
3901
3902 static void free_vpid(struct vcpu_vmx *vmx)
3903 {
3904         if (!enable_vpid)
3905                 return;
3906         spin_lock(&vmx_vpid_lock);
3907         if (vmx->vpid != 0)
3908                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3909         spin_unlock(&vmx_vpid_lock);
3910 }
3911
3912 #define MSR_TYPE_R      1
3913 #define MSR_TYPE_W      2
3914 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3915                                                 u32 msr, int type)
3916 {
3917         int f = sizeof(unsigned long);
3918
3919         if (!cpu_has_vmx_msr_bitmap())
3920                 return;
3921
3922         /*
3923          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3924          * have the write-low and read-high bitmap offsets the wrong way round.
3925          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3926          */
3927         if (msr <= 0x1fff) {
3928                 if (type & MSR_TYPE_R)
3929                         /* read-low */
3930                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3931
3932                 if (type & MSR_TYPE_W)
3933                         /* write-low */
3934                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3935
3936         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3937                 msr &= 0x1fff;
3938                 if (type & MSR_TYPE_R)
3939                         /* read-high */
3940                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3941
3942                 if (type & MSR_TYPE_W)
3943                         /* write-high */
3944                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3945
3946         }
3947 }
3948
3949 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3950                                                 u32 msr, int type)
3951 {
3952         int f = sizeof(unsigned long);
3953
3954         if (!cpu_has_vmx_msr_bitmap())
3955                 return;
3956
3957         /*
3958          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3959          * have the write-low and read-high bitmap offsets the wrong way round.
3960          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3961          */
3962         if (msr <= 0x1fff) {
3963                 if (type & MSR_TYPE_R)
3964                         /* read-low */
3965                         __set_bit(msr, msr_bitmap + 0x000 / f);
3966
3967                 if (type & MSR_TYPE_W)
3968                         /* write-low */
3969                         __set_bit(msr, msr_bitmap + 0x800 / f);
3970
3971         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3972                 msr &= 0x1fff;
3973                 if (type & MSR_TYPE_R)
3974                         /* read-high */
3975                         __set_bit(msr, msr_bitmap + 0x400 / f);
3976
3977                 if (type & MSR_TYPE_W)
3978                         /* write-high */
3979                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3980
3981         }
3982 }
3983
3984 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3985 {
3986         if (!longmode_only)
3987                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3988                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3989         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3990                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3991 }
3992
3993 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3994 {
3995         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3996                         msr, MSR_TYPE_R);
3997         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3998                         msr, MSR_TYPE_R);
3999 }
4000
4001 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4002 {
4003         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4004                         msr, MSR_TYPE_R);
4005         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4006                         msr, MSR_TYPE_R);
4007 }
4008
4009 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4010 {
4011         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4012                         msr, MSR_TYPE_W);
4013         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4014                         msr, MSR_TYPE_W);
4015 }
4016
4017 static int vmx_vm_has_apicv(struct kvm *kvm)
4018 {
4019         return enable_apicv && irqchip_in_kernel(kvm);
4020 }
4021
4022 /*
4023  * Send interrupt to vcpu via posted interrupt way.
4024  * 1. If target vcpu is running(non-root mode), send posted interrupt
4025  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4026  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4027  * interrupt from PIR in next vmentry.
4028  */
4029 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4030 {
4031         struct vcpu_vmx *vmx = to_vmx(vcpu);
4032         int r;
4033
4034         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4035                 return;
4036
4037         r = pi_test_and_set_on(&vmx->pi_desc);
4038         kvm_make_request(KVM_REQ_EVENT, vcpu);
4039 #ifdef CONFIG_SMP
4040         if (!r && (vcpu->mode == IN_GUEST_MODE))
4041                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4042                                 POSTED_INTR_VECTOR);
4043         else
4044 #endif
4045                 kvm_vcpu_kick(vcpu);
4046 }
4047
4048 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4049 {
4050         struct vcpu_vmx *vmx = to_vmx(vcpu);
4051
4052         if (!pi_test_and_clear_on(&vmx->pi_desc))
4053                 return;
4054
4055         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4056 }
4057
4058 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4059 {
4060         return;
4061 }
4062
4063 /*
4064  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4065  * will not change in the lifetime of the guest.
4066  * Note that host-state that does change is set elsewhere. E.g., host-state
4067  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4068  */
4069 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4070 {
4071         u32 low32, high32;
4072         unsigned long tmpl;
4073         struct desc_ptr dt;
4074
4075         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4076         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4077         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4078
4079         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4080 #ifdef CONFIG_X86_64
4081         /*
4082          * Load null selectors, so we can avoid reloading them in
4083          * __vmx_load_host_state(), in case userspace uses the null selectors
4084          * too (the expected case).
4085          */
4086         vmcs_write16(HOST_DS_SELECTOR, 0);
4087         vmcs_write16(HOST_ES_SELECTOR, 0);
4088 #else
4089         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4090         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4091 #endif
4092         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4093         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4094
4095         native_store_idt(&dt);
4096         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4097         vmx->host_idt_base = dt.address;
4098
4099         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4100
4101         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4102         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4103         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4104         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4105
4106         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4107                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4108                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4109         }
4110 }
4111
4112 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4113 {
4114         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4115         if (enable_ept)
4116                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4117         if (is_guest_mode(&vmx->vcpu))
4118                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4119                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4120         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4121 }
4122
4123 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4124 {
4125         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4126
4127         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4128                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4129         return pin_based_exec_ctrl;
4130 }
4131
4132 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4133 {
4134         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4135         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4136                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4137 #ifdef CONFIG_X86_64
4138                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4139                                 CPU_BASED_CR8_LOAD_EXITING;
4140 #endif
4141         }
4142         if (!enable_ept)
4143                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4144                                 CPU_BASED_CR3_LOAD_EXITING  |
4145                                 CPU_BASED_INVLPG_EXITING;
4146         return exec_control;
4147 }
4148
4149 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4150 {
4151         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4152         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4153                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4154         if (vmx->vpid == 0)
4155                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4156         if (!enable_ept) {
4157                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4158                 enable_unrestricted_guest = 0;
4159                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4160                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4161         }
4162         if (!enable_unrestricted_guest)
4163                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4164         if (!ple_gap)
4165                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4166         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4167                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4168                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4169         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4170         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4171            (handle_vmptrld).
4172            We can NOT enable shadow_vmcs here because we don't have yet
4173            a current VMCS12
4174         */
4175         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4176         return exec_control;
4177 }
4178
4179 static void ept_set_mmio_spte_mask(void)
4180 {
4181         /*
4182          * EPT Misconfigurations can be generated if the value of bits 2:0
4183          * of an EPT paging-structure entry is 110b (write/execute).
4184          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4185          * spte.
4186          */
4187         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4188 }
4189
4190 /*
4191  * Sets up the vmcs for emulated real mode.
4192  */
4193 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4194 {
4195 #ifdef CONFIG_X86_64
4196         unsigned long a;
4197 #endif
4198         int i;
4199
4200         /* I/O */
4201         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4202         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4203
4204         if (enable_shadow_vmcs) {
4205                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4206                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4207         }
4208         if (cpu_has_vmx_msr_bitmap())
4209                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4210
4211         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4212
4213         /* Control */
4214         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4215
4216         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4217
4218         if (cpu_has_secondary_exec_ctrls()) {
4219                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4220                                 vmx_secondary_exec_control(vmx));
4221         }
4222
4223         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4224                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4225                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4226                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4227                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4228
4229                 vmcs_write16(GUEST_INTR_STATUS, 0);
4230
4231                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4232                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4233         }
4234
4235         if (ple_gap) {
4236                 vmcs_write32(PLE_GAP, ple_gap);
4237                 vmcs_write32(PLE_WINDOW, ple_window);
4238         }
4239
4240         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4241         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4242         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4243
4244         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4245         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4246         vmx_set_constant_host_state(vmx);
4247 #ifdef CONFIG_X86_64
4248         rdmsrl(MSR_FS_BASE, a);
4249         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4250         rdmsrl(MSR_GS_BASE, a);
4251         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4252 #else
4253         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4254         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4255 #endif
4256
4257         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4258         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4259         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4260         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4261         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4262
4263         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4264                 u32 msr_low, msr_high;
4265                 u64 host_pat;
4266                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4267                 host_pat = msr_low | ((u64) msr_high << 32);
4268                 /* Write the default value follow host pat */
4269                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4270                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4271                 vmx->vcpu.arch.pat = host_pat;
4272         }
4273
4274         for (i = 0; i < NR_VMX_MSR; ++i) {
4275                 u32 index = vmx_msr_index[i];
4276                 u32 data_low, data_high;
4277                 int j = vmx->nmsrs;
4278
4279                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4280                         continue;
4281                 if (wrmsr_safe(index, data_low, data_high) < 0)
4282                         continue;
4283                 vmx->guest_msrs[j].index = i;
4284                 vmx->guest_msrs[j].data = 0;
4285                 vmx->guest_msrs[j].mask = -1ull;
4286                 ++vmx->nmsrs;
4287         }
4288
4289         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4290
4291         /* 22.2.1, 20.8.1 */
4292         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4293
4294         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4295         set_cr4_guest_host_mask(vmx);
4296
4297         return 0;
4298 }
4299
4300 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4301 {
4302         struct vcpu_vmx *vmx = to_vmx(vcpu);
4303         u64 msr;
4304
4305         vmx->rmode.vm86_active = 0;
4306
4307         vmx->soft_vnmi_blocked = 0;
4308
4309         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4310         kvm_set_cr8(&vmx->vcpu, 0);
4311         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4312         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4313                 msr |= MSR_IA32_APICBASE_BSP;
4314         kvm_set_apic_base(&vmx->vcpu, msr);
4315
4316         vmx_segment_cache_clear(vmx);
4317
4318         seg_setup(VCPU_SREG_CS);
4319         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4320         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4321
4322         seg_setup(VCPU_SREG_DS);
4323         seg_setup(VCPU_SREG_ES);
4324         seg_setup(VCPU_SREG_FS);
4325         seg_setup(VCPU_SREG_GS);
4326         seg_setup(VCPU_SREG_SS);
4327
4328         vmcs_write16(GUEST_TR_SELECTOR, 0);
4329         vmcs_writel(GUEST_TR_BASE, 0);
4330         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4331         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4332
4333         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4334         vmcs_writel(GUEST_LDTR_BASE, 0);
4335         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4336         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4337
4338         vmcs_write32(GUEST_SYSENTER_CS, 0);
4339         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4340         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4341
4342         vmcs_writel(GUEST_RFLAGS, 0x02);
4343         kvm_rip_write(vcpu, 0xfff0);
4344
4345         vmcs_writel(GUEST_GDTR_BASE, 0);
4346         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4347
4348         vmcs_writel(GUEST_IDTR_BASE, 0);
4349         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4350
4351         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4352         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4353         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4354
4355         /* Special registers */
4356         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4357
4358         setup_msrs(vmx);
4359
4360         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4361
4362         if (cpu_has_vmx_tpr_shadow()) {
4363                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4364                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4365                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4366                                      __pa(vmx->vcpu.arch.apic->regs));
4367                 vmcs_write32(TPR_THRESHOLD, 0);
4368         }
4369
4370         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4371                 vmcs_write64(APIC_ACCESS_ADDR,
4372                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4373
4374         if (vmx_vm_has_apicv(vcpu->kvm))
4375                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4376
4377         if (vmx->vpid != 0)
4378                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4379
4380         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4381         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4382         vmx_set_cr4(&vmx->vcpu, 0);
4383         vmx_set_efer(&vmx->vcpu, 0);
4384         vmx_fpu_activate(&vmx->vcpu);
4385         update_exception_bitmap(&vmx->vcpu);
4386
4387         vpid_sync_context(vmx);
4388 }
4389
4390 /*
4391  * In nested virtualization, check if L1 asked to exit on external interrupts.
4392  * For most existing hypervisors, this will always return true.
4393  */
4394 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4395 {
4396         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4397                 PIN_BASED_EXT_INTR_MASK;
4398 }
4399
4400 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4401 {
4402         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4403                 PIN_BASED_NMI_EXITING;
4404 }
4405
4406 static int enable_irq_window(struct kvm_vcpu *vcpu)
4407 {
4408         u32 cpu_based_vm_exec_control;
4409
4410         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4411                 /*
4412                  * We get here if vmx_interrupt_allowed() said we can't
4413                  * inject to L1 now because L2 must run. The caller will have
4414                  * to make L2 exit right after entry, so we can inject to L1
4415                  * more promptly.
4416                  */
4417                 return -EBUSY;
4418
4419         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4420         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4421         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4422         return 0;
4423 }
4424
4425 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4426 {
4427         u32 cpu_based_vm_exec_control;
4428
4429         if (!cpu_has_virtual_nmis())
4430                 return enable_irq_window(vcpu);
4431
4432         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4433                 return enable_irq_window(vcpu);
4434
4435         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4436         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4437         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4438         return 0;
4439 }
4440
4441 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4442 {
4443         struct vcpu_vmx *vmx = to_vmx(vcpu);
4444         uint32_t intr;
4445         int irq = vcpu->arch.interrupt.nr;
4446
4447         trace_kvm_inj_virq(irq);
4448
4449         ++vcpu->stat.irq_injections;
4450         if (vmx->rmode.vm86_active) {
4451                 int inc_eip = 0;
4452                 if (vcpu->arch.interrupt.soft)
4453                         inc_eip = vcpu->arch.event_exit_inst_len;
4454                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4455                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4456                 return;
4457         }
4458         intr = irq | INTR_INFO_VALID_MASK;
4459         if (vcpu->arch.interrupt.soft) {
4460                 intr |= INTR_TYPE_SOFT_INTR;
4461                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4462                              vmx->vcpu.arch.event_exit_inst_len);
4463         } else
4464                 intr |= INTR_TYPE_EXT_INTR;
4465         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4466 }
4467
4468 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4469 {
4470         struct vcpu_vmx *vmx = to_vmx(vcpu);
4471
4472         if (is_guest_mode(vcpu))
4473                 return;
4474
4475         if (!cpu_has_virtual_nmis()) {
4476                 /*
4477                  * Tracking the NMI-blocked state in software is built upon
4478                  * finding the next open IRQ window. This, in turn, depends on
4479                  * well-behaving guests: They have to keep IRQs disabled at
4480                  * least as long as the NMI handler runs. Otherwise we may
4481                  * cause NMI nesting, maybe breaking the guest. But as this is
4482                  * highly unlikely, we can live with the residual risk.
4483                  */
4484                 vmx->soft_vnmi_blocked = 1;
4485                 vmx->vnmi_blocked_time = 0;
4486         }
4487
4488         ++vcpu->stat.nmi_injections;
4489         vmx->nmi_known_unmasked = false;
4490         if (vmx->rmode.vm86_active) {
4491                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4492                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4493                 return;
4494         }
4495         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4496                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4497 }
4498
4499 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4500 {
4501         if (!cpu_has_virtual_nmis())
4502                 return to_vmx(vcpu)->soft_vnmi_blocked;
4503         if (to_vmx(vcpu)->nmi_known_unmasked)
4504                 return false;
4505         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4506 }
4507
4508 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4509 {
4510         struct vcpu_vmx *vmx = to_vmx(vcpu);
4511
4512         if (!cpu_has_virtual_nmis()) {
4513                 if (vmx->soft_vnmi_blocked != masked) {
4514                         vmx->soft_vnmi_blocked = masked;
4515                         vmx->vnmi_blocked_time = 0;
4516                 }
4517         } else {
4518                 vmx->nmi_known_unmasked = !masked;
4519                 if (masked)
4520                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4521                                       GUEST_INTR_STATE_NMI);
4522                 else
4523                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4524                                         GUEST_INTR_STATE_NMI);
4525         }
4526 }
4527
4528 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4529 {
4530         if (is_guest_mode(vcpu)) {
4531                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4532
4533                 if (to_vmx(vcpu)->nested.nested_run_pending)
4534                         return 0;
4535                 if (nested_exit_on_nmi(vcpu)) {
4536                         nested_vmx_vmexit(vcpu);
4537                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4538                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4539                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4540                         /*
4541                          * The NMI-triggered VM exit counts as injection:
4542                          * clear this one and block further NMIs.
4543                          */
4544                         vcpu->arch.nmi_pending = 0;
4545                         vmx_set_nmi_mask(vcpu, true);
4546                         return 0;
4547                 }
4548         }
4549
4550         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4551                 return 0;
4552
4553         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4554                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4555                    | GUEST_INTR_STATE_NMI));
4556 }
4557
4558 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4559 {
4560         if (is_guest_mode(vcpu)) {
4561                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4562
4563                 if (to_vmx(vcpu)->nested.nested_run_pending)
4564                         return 0;
4565                 if (nested_exit_on_intr(vcpu)) {
4566                         nested_vmx_vmexit(vcpu);
4567                         vmcs12->vm_exit_reason =
4568                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4569                         vmcs12->vm_exit_intr_info = 0;
4570                         /*
4571                          * fall through to normal code, but now in L1, not L2
4572                          */
4573                 }
4574         }
4575
4576         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4577                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4578                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4579 }
4580
4581 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4582 {
4583         int ret;
4584         struct kvm_userspace_memory_region tss_mem = {
4585                 .slot = TSS_PRIVATE_MEMSLOT,
4586                 .guest_phys_addr = addr,
4587                 .memory_size = PAGE_SIZE * 3,
4588                 .flags = 0,
4589         };
4590
4591         ret = kvm_set_memory_region(kvm, &tss_mem);
4592         if (ret)
4593                 return ret;
4594         kvm->arch.tss_addr = addr;
4595         if (!init_rmode_tss(kvm))
4596                 return  -ENOMEM;
4597
4598         return 0;
4599 }
4600
4601 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4602 {
4603         switch (vec) {
4604         case BP_VECTOR:
4605                 /*
4606                  * Update instruction length as we may reinject the exception
4607                  * from user space while in guest debugging mode.
4608                  */
4609                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4610                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4611                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4612                         return false;
4613                 /* fall through */
4614         case DB_VECTOR:
4615                 if (vcpu->guest_debug &
4616                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4617                         return false;
4618                 /* fall through */
4619         case DE_VECTOR:
4620         case OF_VECTOR:
4621         case BR_VECTOR:
4622         case UD_VECTOR:
4623         case DF_VECTOR:
4624         case SS_VECTOR:
4625         case GP_VECTOR:
4626         case MF_VECTOR:
4627                 return true;
4628         break;
4629         }
4630         return false;
4631 }
4632
4633 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4634                                   int vec, u32 err_code)
4635 {
4636         /*
4637          * Instruction with address size override prefix opcode 0x67
4638          * Cause the #SS fault with 0 error code in VM86 mode.
4639          */
4640         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4641                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4642                         if (vcpu->arch.halt_request) {
4643                                 vcpu->arch.halt_request = 0;
4644                                 return kvm_emulate_halt(vcpu);
4645                         }
4646                         return 1;
4647                 }
4648                 return 0;
4649         }
4650
4651         /*
4652          * Forward all other exceptions that are valid in real mode.
4653          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4654          *        the required debugging infrastructure rework.
4655          */
4656         kvm_queue_exception(vcpu, vec);
4657         return 1;
4658 }
4659
4660 /*
4661  * Trigger machine check on the host. We assume all the MSRs are already set up
4662  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4663  * We pass a fake environment to the machine check handler because we want
4664  * the guest to be always treated like user space, no matter what context
4665  * it used internally.
4666  */
4667 static void kvm_machine_check(void)
4668 {
4669 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4670         struct pt_regs regs = {
4671                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4672                 .flags = X86_EFLAGS_IF,
4673         };
4674
4675         do_machine_check(&regs, 0);
4676 #endif
4677 }
4678
4679 static int handle_machine_check(struct kvm_vcpu *vcpu)
4680 {
4681         /* already handled by vcpu_run */
4682         return 1;
4683 }
4684
4685 static int handle_exception(struct kvm_vcpu *vcpu)
4686 {
4687         struct vcpu_vmx *vmx = to_vmx(vcpu);
4688         struct kvm_run *kvm_run = vcpu->run;
4689         u32 intr_info, ex_no, error_code;
4690         unsigned long cr2, rip, dr6;
4691         u32 vect_info;
4692         enum emulation_result er;
4693
4694         vect_info = vmx->idt_vectoring_info;
4695         intr_info = vmx->exit_intr_info;
4696
4697         if (is_machine_check(intr_info))
4698                 return handle_machine_check(vcpu);
4699
4700         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4701                 return 1;  /* already handled by vmx_vcpu_run() */
4702
4703         if (is_no_device(intr_info)) {
4704                 vmx_fpu_activate(vcpu);
4705                 return 1;
4706         }
4707
4708         if (is_invalid_opcode(intr_info)) {
4709                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4710                 if (er != EMULATE_DONE)
4711                         kvm_queue_exception(vcpu, UD_VECTOR);
4712                 return 1;
4713         }
4714
4715         error_code = 0;
4716         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4717                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4718
4719         /*
4720          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4721          * MMIO, it is better to report an internal error.
4722          * See the comments in vmx_handle_exit.
4723          */
4724         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4725             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4726                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4727                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4728                 vcpu->run->internal.ndata = 2;
4729                 vcpu->run->internal.data[0] = vect_info;
4730                 vcpu->run->internal.data[1] = intr_info;
4731                 return 0;
4732         }
4733
4734         if (is_page_fault(intr_info)) {
4735                 /* EPT won't cause page fault directly */
4736                 BUG_ON(enable_ept);
4737                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4738                 trace_kvm_page_fault(cr2, error_code);
4739
4740                 if (kvm_event_needs_reinjection(vcpu))
4741                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4742                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4743         }
4744
4745         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4746
4747         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4748                 return handle_rmode_exception(vcpu, ex_no, error_code);
4749
4750         switch (ex_no) {
4751         case DB_VECTOR:
4752                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4753                 if (!(vcpu->guest_debug &
4754                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4755                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4756                         kvm_queue_exception(vcpu, DB_VECTOR);
4757                         return 1;
4758                 }
4759                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4760                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4761                 /* fall through */
4762         case BP_VECTOR:
4763                 /*
4764                  * Update instruction length as we may reinject #BP from
4765                  * user space while in guest debugging mode. Reading it for
4766                  * #DB as well causes no harm, it is not used in that case.
4767                  */
4768                 vmx->vcpu.arch.event_exit_inst_len =
4769                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4770                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4771                 rip = kvm_rip_read(vcpu);
4772                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4773                 kvm_run->debug.arch.exception = ex_no;
4774                 break;
4775         default:
4776                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4777                 kvm_run->ex.exception = ex_no;
4778                 kvm_run->ex.error_code = error_code;
4779                 break;
4780         }
4781         return 0;
4782 }
4783
4784 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4785 {
4786         ++vcpu->stat.irq_exits;
4787         return 1;
4788 }
4789
4790 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4791 {
4792         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4793         return 0;
4794 }
4795
4796 static int handle_io(struct kvm_vcpu *vcpu)
4797 {
4798         unsigned long exit_qualification;
4799         int size, in, string;
4800         unsigned port;
4801
4802         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4803         string = (exit_qualification & 16) != 0;
4804         in = (exit_qualification & 8) != 0;
4805
4806         ++vcpu->stat.io_exits;
4807
4808         if (string || in)
4809                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4810
4811         port = exit_qualification >> 16;
4812         size = (exit_qualification & 7) + 1;
4813         skip_emulated_instruction(vcpu);
4814
4815         return kvm_fast_pio_out(vcpu, size, port);
4816 }
4817
4818 static void
4819 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4820 {
4821         /*
4822          * Patch in the VMCALL instruction:
4823          */
4824         hypercall[0] = 0x0f;
4825         hypercall[1] = 0x01;
4826         hypercall[2] = 0xc1;
4827 }
4828
4829 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4830 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4831 {
4832         if (is_guest_mode(vcpu)) {
4833                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4834                 unsigned long orig_val = val;
4835
4836                 /*
4837                  * We get here when L2 changed cr0 in a way that did not change
4838                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4839                  * but did change L0 shadowed bits. So we first calculate the
4840                  * effective cr0 value that L1 would like to write into the
4841                  * hardware. It consists of the L2-owned bits from the new
4842                  * value combined with the L1-owned bits from L1's guest_cr0.
4843                  */
4844                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4845                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4846
4847                 /* TODO: will have to take unrestricted guest mode into
4848                  * account */
4849                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4850                         return 1;
4851
4852                 if (kvm_set_cr0(vcpu, val))
4853                         return 1;
4854                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4855                 return 0;
4856         } else {
4857                 if (to_vmx(vcpu)->nested.vmxon &&
4858                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4859                         return 1;
4860                 return kvm_set_cr0(vcpu, val);
4861         }
4862 }
4863
4864 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4865 {
4866         if (is_guest_mode(vcpu)) {
4867                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4868                 unsigned long orig_val = val;
4869
4870                 /* analogously to handle_set_cr0 */
4871                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4872                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4873                 if (kvm_set_cr4(vcpu, val))
4874                         return 1;
4875                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4876                 return 0;
4877         } else
4878                 return kvm_set_cr4(vcpu, val);
4879 }
4880
4881 /* called to set cr0 as approriate for clts instruction exit. */
4882 static void handle_clts(struct kvm_vcpu *vcpu)
4883 {
4884         if (is_guest_mode(vcpu)) {
4885                 /*
4886                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4887                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4888                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4889                  */
4890                 vmcs_writel(CR0_READ_SHADOW,
4891                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4892                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4893         } else
4894                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4895 }
4896
4897 static int handle_cr(struct kvm_vcpu *vcpu)
4898 {
4899         unsigned long exit_qualification, val;
4900         int cr;
4901         int reg;
4902         int err;
4903
4904         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4905         cr = exit_qualification & 15;
4906         reg = (exit_qualification >> 8) & 15;
4907         switch ((exit_qualification >> 4) & 3) {
4908         case 0: /* mov to cr */
4909                 val = kvm_register_read(vcpu, reg);
4910                 trace_kvm_cr_write(cr, val);
4911                 switch (cr) {
4912                 case 0:
4913                         err = handle_set_cr0(vcpu, val);
4914                         kvm_complete_insn_gp(vcpu, err);
4915                         return 1;
4916                 case 3:
4917                         err = kvm_set_cr3(vcpu, val);
4918                         kvm_complete_insn_gp(vcpu, err);
4919                         return 1;
4920                 case 4:
4921                         err = handle_set_cr4(vcpu, val);
4922                         kvm_complete_insn_gp(vcpu, err);
4923                         return 1;
4924                 case 8: {
4925                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4926                                 u8 cr8 = kvm_register_read(vcpu, reg);
4927                                 err = kvm_set_cr8(vcpu, cr8);
4928                                 kvm_complete_insn_gp(vcpu, err);
4929                                 if (irqchip_in_kernel(vcpu->kvm))
4930                                         return 1;
4931                                 if (cr8_prev <= cr8)
4932                                         return 1;
4933                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4934                                 return 0;
4935                         }
4936                 }
4937                 break;
4938         case 2: /* clts */
4939                 handle_clts(vcpu);
4940                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4941                 skip_emulated_instruction(vcpu);
4942                 vmx_fpu_activate(vcpu);
4943                 return 1;
4944         case 1: /*mov from cr*/
4945                 switch (cr) {
4946                 case 3:
4947                         val = kvm_read_cr3(vcpu);
4948                         kvm_register_write(vcpu, reg, val);
4949                         trace_kvm_cr_read(cr, val);
4950                         skip_emulated_instruction(vcpu);
4951                         return 1;
4952                 case 8:
4953                         val = kvm_get_cr8(vcpu);
4954                         kvm_register_write(vcpu, reg, val);
4955                         trace_kvm_cr_read(cr, val);
4956                         skip_emulated_instruction(vcpu);
4957                         return 1;
4958                 }
4959                 break;
4960         case 3: /* lmsw */
4961                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4962                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4963                 kvm_lmsw(vcpu, val);
4964
4965                 skip_emulated_instruction(vcpu);
4966                 return 1;
4967         default:
4968                 break;
4969         }
4970         vcpu->run->exit_reason = 0;
4971         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4972                (int)(exit_qualification >> 4) & 3, cr);
4973         return 0;
4974 }
4975
4976 static int handle_dr(struct kvm_vcpu *vcpu)
4977 {
4978         unsigned long exit_qualification;
4979         int dr, reg;
4980
4981         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4982         if (!kvm_require_cpl(vcpu, 0))
4983                 return 1;
4984         dr = vmcs_readl(GUEST_DR7);
4985         if (dr & DR7_GD) {
4986                 /*
4987                  * As the vm-exit takes precedence over the debug trap, we
4988                  * need to emulate the latter, either for the host or the
4989                  * guest debugging itself.
4990                  */
4991                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4992                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4993                         vcpu->run->debug.arch.dr7 = dr;
4994                         vcpu->run->debug.arch.pc =
4995                                 vmcs_readl(GUEST_CS_BASE) +
4996                                 vmcs_readl(GUEST_RIP);
4997                         vcpu->run->debug.arch.exception = DB_VECTOR;
4998                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4999                         return 0;
5000                 } else {
5001                         vcpu->arch.dr7 &= ~DR7_GD;
5002                         vcpu->arch.dr6 |= DR6_BD;
5003                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5004                         kvm_queue_exception(vcpu, DB_VECTOR);
5005                         return 1;
5006                 }
5007         }
5008
5009         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5010         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5011         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5012         if (exit_qualification & TYPE_MOV_FROM_DR) {
5013                 unsigned long val;
5014                 if (!kvm_get_dr(vcpu, dr, &val))
5015                         kvm_register_write(vcpu, reg, val);
5016         } else
5017                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5018         skip_emulated_instruction(vcpu);
5019         return 1;
5020 }
5021
5022 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5023 {
5024         vmcs_writel(GUEST_DR7, val);
5025 }
5026
5027 static int handle_cpuid(struct kvm_vcpu *vcpu)
5028 {
5029         kvm_emulate_cpuid(vcpu);
5030         return 1;
5031 }
5032
5033 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5034 {
5035         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5036         u64 data;
5037
5038         if (vmx_get_msr(vcpu, ecx, &data)) {
5039                 trace_kvm_msr_read_ex(ecx);
5040                 kvm_inject_gp(vcpu, 0);
5041                 return 1;
5042         }
5043
5044         trace_kvm_msr_read(ecx, data);
5045
5046         /* FIXME: handling of bits 32:63 of rax, rdx */
5047         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5048         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5049         skip_emulated_instruction(vcpu);
5050         return 1;
5051 }
5052
5053 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5054 {
5055         struct msr_data msr;
5056         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5057         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5058                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5059
5060         msr.data = data;
5061         msr.index = ecx;
5062         msr.host_initiated = false;
5063         if (vmx_set_msr(vcpu, &msr) != 0) {
5064                 trace_kvm_msr_write_ex(ecx, data);
5065                 kvm_inject_gp(vcpu, 0);
5066                 return 1;
5067         }
5068
5069         trace_kvm_msr_write(ecx, data);
5070         skip_emulated_instruction(vcpu);
5071         return 1;
5072 }
5073
5074 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5075 {
5076         kvm_make_request(KVM_REQ_EVENT, vcpu);
5077         return 1;
5078 }
5079
5080 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5081 {
5082         u32 cpu_based_vm_exec_control;
5083
5084         /* clear pending irq */
5085         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5086         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5087         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5088
5089         kvm_make_request(KVM_REQ_EVENT, vcpu);
5090
5091         ++vcpu->stat.irq_window_exits;
5092
5093         /*
5094          * If the user space waits to inject interrupts, exit as soon as
5095          * possible
5096          */
5097         if (!irqchip_in_kernel(vcpu->kvm) &&
5098             vcpu->run->request_interrupt_window &&
5099             !kvm_cpu_has_interrupt(vcpu)) {
5100                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5101                 return 0;
5102         }
5103         return 1;
5104 }
5105
5106 static int handle_halt(struct kvm_vcpu *vcpu)
5107 {
5108         skip_emulated_instruction(vcpu);
5109         return kvm_emulate_halt(vcpu);
5110 }
5111
5112 static int handle_vmcall(struct kvm_vcpu *vcpu)
5113 {
5114         skip_emulated_instruction(vcpu);
5115         kvm_emulate_hypercall(vcpu);
5116         return 1;
5117 }
5118
5119 static int handle_invd(struct kvm_vcpu *vcpu)
5120 {
5121         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5122 }
5123
5124 static int handle_invlpg(struct kvm_vcpu *vcpu)
5125 {
5126         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5127
5128         kvm_mmu_invlpg(vcpu, exit_qualification);
5129         skip_emulated_instruction(vcpu);
5130         return 1;
5131 }
5132
5133 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5134 {
5135         int err;
5136
5137         err = kvm_rdpmc(vcpu);
5138         kvm_complete_insn_gp(vcpu, err);
5139
5140         return 1;
5141 }
5142
5143 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5144 {
5145         skip_emulated_instruction(vcpu);
5146         kvm_emulate_wbinvd(vcpu);
5147         return 1;
5148 }
5149
5150 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5151 {
5152         u64 new_bv = kvm_read_edx_eax(vcpu);
5153         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5154
5155         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5156                 skip_emulated_instruction(vcpu);
5157         return 1;
5158 }
5159
5160 static int handle_apic_access(struct kvm_vcpu *vcpu)
5161 {
5162         if (likely(fasteoi)) {
5163                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5164                 int access_type, offset;
5165
5166                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5167                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5168                 /*
5169                  * Sane guest uses MOV to write EOI, with written value
5170                  * not cared. So make a short-circuit here by avoiding
5171                  * heavy instruction emulation.
5172                  */
5173                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5174                     (offset == APIC_EOI)) {
5175                         kvm_lapic_set_eoi(vcpu);
5176                         skip_emulated_instruction(vcpu);
5177                         return 1;
5178                 }
5179         }
5180         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5181 }
5182
5183 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5184 {
5185         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5186         int vector = exit_qualification & 0xff;
5187
5188         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5189         kvm_apic_set_eoi_accelerated(vcpu, vector);
5190         return 1;
5191 }
5192
5193 static int handle_apic_write(struct kvm_vcpu *vcpu)
5194 {
5195         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5196         u32 offset = exit_qualification & 0xfff;
5197
5198         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5199         kvm_apic_write_nodecode(vcpu, offset);
5200         return 1;
5201 }
5202
5203 static int handle_task_switch(struct kvm_vcpu *vcpu)
5204 {
5205         struct vcpu_vmx *vmx = to_vmx(vcpu);
5206         unsigned long exit_qualification;
5207         bool has_error_code = false;
5208         u32 error_code = 0;
5209         u16 tss_selector;
5210         int reason, type, idt_v, idt_index;
5211
5212         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5213         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5214         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5215
5216         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5217
5218         reason = (u32)exit_qualification >> 30;
5219         if (reason == TASK_SWITCH_GATE && idt_v) {
5220                 switch (type) {
5221                 case INTR_TYPE_NMI_INTR:
5222                         vcpu->arch.nmi_injected = false;
5223                         vmx_set_nmi_mask(vcpu, true);
5224                         break;
5225                 case INTR_TYPE_EXT_INTR:
5226                 case INTR_TYPE_SOFT_INTR:
5227                         kvm_clear_interrupt_queue(vcpu);
5228                         break;
5229                 case INTR_TYPE_HARD_EXCEPTION:
5230                         if (vmx->idt_vectoring_info &
5231                             VECTORING_INFO_DELIVER_CODE_MASK) {
5232                                 has_error_code = true;
5233                                 error_code =
5234                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5235                         }
5236                         /* fall through */
5237                 case INTR_TYPE_SOFT_EXCEPTION:
5238                         kvm_clear_exception_queue(vcpu);
5239                         break;
5240                 default:
5241                         break;
5242                 }
5243         }
5244         tss_selector = exit_qualification;
5245
5246         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5247                        type != INTR_TYPE_EXT_INTR &&
5248                        type != INTR_TYPE_NMI_INTR))
5249                 skip_emulated_instruction(vcpu);
5250
5251         if (kvm_task_switch(vcpu, tss_selector,
5252                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5253                             has_error_code, error_code) == EMULATE_FAIL) {
5254                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5255                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5256                 vcpu->run->internal.ndata = 0;
5257                 return 0;
5258         }
5259
5260         /* clear all local breakpoint enable flags */
5261         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5262
5263         /*
5264          * TODO: What about debug traps on tss switch?
5265          *       Are we supposed to inject them and update dr6?
5266          */
5267
5268         return 1;
5269 }
5270
5271 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5272 {
5273         unsigned long exit_qualification;
5274         gpa_t gpa;
5275         u32 error_code;
5276         int gla_validity;
5277
5278         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5279
5280         gla_validity = (exit_qualification >> 7) & 0x3;
5281         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5282                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5283                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5284                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5285                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5286                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5287                         (long unsigned int)exit_qualification);
5288                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5289                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5290                 return 0;
5291         }
5292
5293         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5294         trace_kvm_page_fault(gpa, exit_qualification);
5295
5296         /* It is a write fault? */
5297         error_code = exit_qualification & (1U << 1);
5298         /* ept page table is present? */
5299         error_code |= (exit_qualification >> 3) & 0x1;
5300
5301         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5302 }
5303
5304 static u64 ept_rsvd_mask(u64 spte, int level)
5305 {
5306         int i;
5307         u64 mask = 0;
5308
5309         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5310                 mask |= (1ULL << i);
5311
5312         if (level > 2)
5313                 /* bits 7:3 reserved */
5314                 mask |= 0xf8;
5315         else if (level == 2) {
5316                 if (spte & (1ULL << 7))
5317                         /* 2MB ref, bits 20:12 reserved */
5318                         mask |= 0x1ff000;
5319                 else
5320                         /* bits 6:3 reserved */
5321                         mask |= 0x78;
5322         }
5323
5324         return mask;
5325 }
5326
5327 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5328                                        int level)
5329 {
5330         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5331
5332         /* 010b (write-only) */
5333         WARN_ON((spte & 0x7) == 0x2);
5334
5335         /* 110b (write/execute) */
5336         WARN_ON((spte & 0x7) == 0x6);
5337
5338         /* 100b (execute-only) and value not supported by logical processor */
5339         if (!cpu_has_vmx_ept_execute_only())
5340                 WARN_ON((spte & 0x7) == 0x4);
5341
5342         /* not 000b */
5343         if ((spte & 0x7)) {
5344                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5345
5346                 if (rsvd_bits != 0) {
5347                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5348                                          __func__, rsvd_bits);
5349                         WARN_ON(1);
5350                 }
5351
5352                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5353                         u64 ept_mem_type = (spte & 0x38) >> 3;
5354
5355                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5356                             ept_mem_type == 7) {
5357                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5358                                                 __func__, ept_mem_type);
5359                                 WARN_ON(1);
5360                         }
5361                 }
5362         }
5363 }
5364
5365 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5366 {
5367         u64 sptes[4];
5368         int nr_sptes, i, ret;
5369         gpa_t gpa;
5370
5371         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5372
5373         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5374         if (likely(ret == RET_MMIO_PF_EMULATE))
5375                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5376                                               EMULATE_DONE;
5377
5378         if (unlikely(ret == RET_MMIO_PF_INVALID))
5379                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5380
5381         if (unlikely(ret == RET_MMIO_PF_RETRY))
5382                 return 1;
5383
5384         /* It is the real ept misconfig */
5385         printk(KERN_ERR "EPT: Misconfiguration.\n");
5386         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5387
5388         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5389
5390         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5391                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5392
5393         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5394         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5395
5396         return 0;
5397 }
5398
5399 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5400 {
5401         u32 cpu_based_vm_exec_control;
5402
5403         /* clear pending NMI */
5404         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5405         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5406         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5407         ++vcpu->stat.nmi_window_exits;
5408         kvm_make_request(KVM_REQ_EVENT, vcpu);
5409
5410         return 1;
5411 }
5412
5413 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5414 {
5415         struct vcpu_vmx *vmx = to_vmx(vcpu);
5416         enum emulation_result err = EMULATE_DONE;
5417         int ret = 1;
5418         u32 cpu_exec_ctrl;
5419         bool intr_window_requested;
5420         unsigned count = 130;
5421
5422         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5423         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5424
5425         while (!guest_state_valid(vcpu) && count-- != 0) {
5426                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5427                         return handle_interrupt_window(&vmx->vcpu);
5428
5429                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5430                         return 1;
5431
5432                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5433
5434                 if (err == EMULATE_DO_MMIO) {
5435                         ret = 0;
5436                         goto out;
5437                 }
5438
5439                 if (err != EMULATE_DONE) {
5440                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5441                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5442                         vcpu->run->internal.ndata = 0;
5443                         return 0;
5444                 }
5445
5446                 if (vcpu->arch.halt_request) {
5447                         vcpu->arch.halt_request = 0;
5448                         ret = kvm_emulate_halt(vcpu);
5449                         goto out;
5450                 }
5451
5452                 if (signal_pending(current))
5453                         goto out;
5454                 if (need_resched())
5455                         schedule();
5456         }
5457
5458         vmx->emulation_required = emulation_required(vcpu);
5459 out:
5460         return ret;
5461 }
5462
5463 /*
5464  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5465  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5466  */
5467 static int handle_pause(struct kvm_vcpu *vcpu)
5468 {
5469         skip_emulated_instruction(vcpu);
5470         kvm_vcpu_on_spin(vcpu);
5471
5472         return 1;
5473 }
5474
5475 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5476 {
5477         kvm_queue_exception(vcpu, UD_VECTOR);
5478         return 1;
5479 }
5480
5481 /*
5482  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5483  * We could reuse a single VMCS for all the L2 guests, but we also want the
5484  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5485  * allows keeping them loaded on the processor, and in the future will allow
5486  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5487  * every entry if they never change.
5488  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5489  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5490  *
5491  * The following functions allocate and free a vmcs02 in this pool.
5492  */
5493
5494 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5495 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5496 {
5497         struct vmcs02_list *item;
5498         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5499                 if (item->vmptr == vmx->nested.current_vmptr) {
5500                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5501                         return &item->vmcs02;
5502                 }
5503
5504         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5505                 /* Recycle the least recently used VMCS. */
5506                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5507                         struct vmcs02_list, list);
5508                 item->vmptr = vmx->nested.current_vmptr;
5509                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5510                 return &item->vmcs02;
5511         }
5512
5513         /* Create a new VMCS */
5514         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5515         if (!item)
5516                 return NULL;
5517         item->vmcs02.vmcs = alloc_vmcs();
5518         if (!item->vmcs02.vmcs) {
5519                 kfree(item);
5520                 return NULL;
5521         }
5522         loaded_vmcs_init(&item->vmcs02);
5523         item->vmptr = vmx->nested.current_vmptr;
5524         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5525         vmx->nested.vmcs02_num++;
5526         return &item->vmcs02;
5527 }
5528
5529 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5530 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5531 {
5532         struct vmcs02_list *item;
5533         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5534                 if (item->vmptr == vmptr) {
5535                         free_loaded_vmcs(&item->vmcs02);
5536                         list_del(&item->list);
5537                         kfree(item);
5538                         vmx->nested.vmcs02_num--;
5539                         return;
5540                 }
5541 }
5542
5543 /*
5544  * Free all VMCSs saved for this vcpu, except the one pointed by
5545  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5546  * currently used, if running L2), and vmcs01 when running L2.
5547  */
5548 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5549 {
5550         struct vmcs02_list *item, *n;
5551         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5552                 if (vmx->loaded_vmcs != &item->vmcs02)
5553                         free_loaded_vmcs(&item->vmcs02);
5554                 list_del(&item->list);
5555                 kfree(item);
5556         }
5557         vmx->nested.vmcs02_num = 0;
5558
5559         if (vmx->loaded_vmcs != &vmx->vmcs01)
5560                 free_loaded_vmcs(&vmx->vmcs01);
5561 }
5562
5563 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5564                                  u32 vm_instruction_error);
5565
5566 /*
5567  * Emulate the VMXON instruction.
5568  * Currently, we just remember that VMX is active, and do not save or even
5569  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5570  * do not currently need to store anything in that guest-allocated memory
5571  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5572  * argument is different from the VMXON pointer (which the spec says they do).
5573  */
5574 static int handle_vmon(struct kvm_vcpu *vcpu)
5575 {
5576         struct kvm_segment cs;
5577         struct vcpu_vmx *vmx = to_vmx(vcpu);
5578         struct vmcs *shadow_vmcs;
5579
5580         /* The Intel VMX Instruction Reference lists a bunch of bits that
5581          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5582          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5583          * Otherwise, we should fail with #UD. We test these now:
5584          */
5585         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5586             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5587             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5588                 kvm_queue_exception(vcpu, UD_VECTOR);
5589                 return 1;
5590         }
5591
5592         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5593         if (is_long_mode(vcpu) && !cs.l) {
5594                 kvm_queue_exception(vcpu, UD_VECTOR);
5595                 return 1;
5596         }
5597
5598         if (vmx_get_cpl(vcpu)) {
5599                 kvm_inject_gp(vcpu, 0);
5600                 return 1;
5601         }
5602         if (vmx->nested.vmxon) {
5603                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5604                 skip_emulated_instruction(vcpu);
5605                 return 1;
5606         }
5607         if (enable_shadow_vmcs) {
5608                 shadow_vmcs = alloc_vmcs();
5609                 if (!shadow_vmcs)
5610                         return -ENOMEM;
5611                 /* mark vmcs as shadow */
5612                 shadow_vmcs->revision_id |= (1u << 31);
5613                 /* init shadow vmcs */
5614                 vmcs_clear(shadow_vmcs);
5615                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5616         }
5617
5618         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5619         vmx->nested.vmcs02_num = 0;
5620
5621         vmx->nested.vmxon = true;
5622
5623         skip_emulated_instruction(vcpu);
5624         return 1;
5625 }
5626
5627 /*
5628  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5629  * for running VMX instructions (except VMXON, whose prerequisites are
5630  * slightly different). It also specifies what exception to inject otherwise.
5631  */
5632 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5633 {
5634         struct kvm_segment cs;
5635         struct vcpu_vmx *vmx = to_vmx(vcpu);
5636
5637         if (!vmx->nested.vmxon) {
5638                 kvm_queue_exception(vcpu, UD_VECTOR);
5639                 return 0;
5640         }
5641
5642         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5643         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5644             (is_long_mode(vcpu) && !cs.l)) {
5645                 kvm_queue_exception(vcpu, UD_VECTOR);
5646                 return 0;
5647         }
5648
5649         if (vmx_get_cpl(vcpu)) {
5650                 kvm_inject_gp(vcpu, 0);
5651                 return 0;
5652         }
5653
5654         return 1;
5655 }
5656
5657 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5658 {
5659         u32 exec_control;
5660         if (enable_shadow_vmcs) {
5661                 if (vmx->nested.current_vmcs12 != NULL) {
5662                         /* copy to memory all shadowed fields in case
5663                            they were modified */
5664                         copy_shadow_to_vmcs12(vmx);
5665                         vmx->nested.sync_shadow_vmcs = false;
5666                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5667                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5668                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5669                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5670                 }
5671         }
5672         kunmap(vmx->nested.current_vmcs12_page);
5673         nested_release_page(vmx->nested.current_vmcs12_page);
5674 }
5675
5676 /*
5677  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5678  * just stops using VMX.
5679  */
5680 static void free_nested(struct vcpu_vmx *vmx)
5681 {
5682         if (!vmx->nested.vmxon)
5683                 return;
5684         vmx->nested.vmxon = false;
5685         if (vmx->nested.current_vmptr != -1ull) {
5686                 nested_release_vmcs12(vmx);
5687                 vmx->nested.current_vmptr = -1ull;
5688                 vmx->nested.current_vmcs12 = NULL;
5689         }
5690         if (enable_shadow_vmcs)
5691                 free_vmcs(vmx->nested.current_shadow_vmcs);
5692         /* Unpin physical memory we referred to in current vmcs02 */
5693         if (vmx->nested.apic_access_page) {
5694                 nested_release_page(vmx->nested.apic_access_page);
5695                 vmx->nested.apic_access_page = 0;
5696         }
5697
5698         nested_free_all_saved_vmcss(vmx);
5699 }
5700
5701 /* Emulate the VMXOFF instruction */
5702 static int handle_vmoff(struct kvm_vcpu *vcpu)
5703 {
5704         if (!nested_vmx_check_permission(vcpu))
5705                 return 1;
5706         free_nested(to_vmx(vcpu));
5707         skip_emulated_instruction(vcpu);
5708         return 1;
5709 }
5710
5711 /*
5712  * Decode the memory-address operand of a vmx instruction, as recorded on an
5713  * exit caused by such an instruction (run by a guest hypervisor).
5714  * On success, returns 0. When the operand is invalid, returns 1 and throws
5715  * #UD or #GP.
5716  */
5717 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5718                                  unsigned long exit_qualification,
5719                                  u32 vmx_instruction_info, gva_t *ret)
5720 {
5721         /*
5722          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5723          * Execution", on an exit, vmx_instruction_info holds most of the
5724          * addressing components of the operand. Only the displacement part
5725          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5726          * For how an actual address is calculated from all these components,
5727          * refer to Vol. 1, "Operand Addressing".
5728          */
5729         int  scaling = vmx_instruction_info & 3;
5730         int  addr_size = (vmx_instruction_info >> 7) & 7;
5731         bool is_reg = vmx_instruction_info & (1u << 10);
5732         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5733         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5734         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5735         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5736         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5737
5738         if (is_reg) {
5739                 kvm_queue_exception(vcpu, UD_VECTOR);
5740                 return 1;
5741         }
5742
5743         /* Addr = segment_base + offset */
5744         /* offset = base + [index * scale] + displacement */
5745         *ret = vmx_get_segment_base(vcpu, seg_reg);
5746         if (base_is_valid)
5747                 *ret += kvm_register_read(vcpu, base_reg);
5748         if (index_is_valid)
5749                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5750         *ret += exit_qualification; /* holds the displacement */
5751
5752         if (addr_size == 1) /* 32 bit */
5753                 *ret &= 0xffffffff;
5754
5755         /*
5756          * TODO: throw #GP (and return 1) in various cases that the VM*
5757          * instructions require it - e.g., offset beyond segment limit,
5758          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5759          * address, and so on. Currently these are not checked.
5760          */
5761         return 0;
5762 }
5763
5764 /*
5765  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5766  * set the success or error code of an emulated VMX instruction, as specified
5767  * by Vol 2B, VMX Instruction Reference, "Conventions".
5768  */
5769 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5770 {
5771         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5772                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5773                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5774 }
5775
5776 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5777 {
5778         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5779                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5780                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5781                         | X86_EFLAGS_CF);
5782 }
5783
5784 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5785                                         u32 vm_instruction_error)
5786 {
5787         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5788                 /*
5789                  * failValid writes the error number to the current VMCS, which
5790                  * can't be done there isn't a current VMCS.
5791                  */
5792                 nested_vmx_failInvalid(vcpu);
5793                 return;
5794         }
5795         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5796                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5797                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5798                         | X86_EFLAGS_ZF);
5799         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5800         /*
5801          * We don't need to force a shadow sync because
5802          * VM_INSTRUCTION_ERROR is not shadowed
5803          */
5804 }
5805
5806 /* Emulate the VMCLEAR instruction */
5807 static int handle_vmclear(struct kvm_vcpu *vcpu)
5808 {
5809         struct vcpu_vmx *vmx = to_vmx(vcpu);
5810         gva_t gva;
5811         gpa_t vmptr;
5812         struct vmcs12 *vmcs12;
5813         struct page *page;
5814         struct x86_exception e;
5815
5816         if (!nested_vmx_check_permission(vcpu))
5817                 return 1;
5818
5819         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5820                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5821                 return 1;
5822
5823         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5824                                 sizeof(vmptr), &e)) {
5825                 kvm_inject_page_fault(vcpu, &e);
5826                 return 1;
5827         }
5828
5829         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5830                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5831                 skip_emulated_instruction(vcpu);
5832                 return 1;
5833         }
5834
5835         if (vmptr == vmx->nested.current_vmptr) {
5836                 nested_release_vmcs12(vmx);
5837                 vmx->nested.current_vmptr = -1ull;
5838                 vmx->nested.current_vmcs12 = NULL;
5839         }
5840
5841         page = nested_get_page(vcpu, vmptr);
5842         if (page == NULL) {
5843                 /*
5844                  * For accurate processor emulation, VMCLEAR beyond available
5845                  * physical memory should do nothing at all. However, it is
5846                  * possible that a nested vmx bug, not a guest hypervisor bug,
5847                  * resulted in this case, so let's shut down before doing any
5848                  * more damage:
5849                  */
5850                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5851                 return 1;
5852         }
5853         vmcs12 = kmap(page);
5854         vmcs12->launch_state = 0;
5855         kunmap(page);
5856         nested_release_page(page);
5857
5858         nested_free_vmcs02(vmx, vmptr);
5859
5860         skip_emulated_instruction(vcpu);
5861         nested_vmx_succeed(vcpu);
5862         return 1;
5863 }
5864
5865 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5866
5867 /* Emulate the VMLAUNCH instruction */
5868 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5869 {
5870         return nested_vmx_run(vcpu, true);
5871 }
5872
5873 /* Emulate the VMRESUME instruction */
5874 static int handle_vmresume(struct kvm_vcpu *vcpu)
5875 {
5876
5877         return nested_vmx_run(vcpu, false);
5878 }
5879
5880 enum vmcs_field_type {
5881         VMCS_FIELD_TYPE_U16 = 0,
5882         VMCS_FIELD_TYPE_U64 = 1,
5883         VMCS_FIELD_TYPE_U32 = 2,
5884         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5885 };
5886
5887 static inline int vmcs_field_type(unsigned long field)
5888 {
5889         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5890                 return VMCS_FIELD_TYPE_U32;
5891         return (field >> 13) & 0x3 ;
5892 }
5893
5894 static inline int vmcs_field_readonly(unsigned long field)
5895 {
5896         return (((field >> 10) & 0x3) == 1);
5897 }
5898
5899 /*
5900  * Read a vmcs12 field. Since these can have varying lengths and we return
5901  * one type, we chose the biggest type (u64) and zero-extend the return value
5902  * to that size. Note that the caller, handle_vmread, might need to use only
5903  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5904  * 64-bit fields are to be returned).
5905  */
5906 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5907                                         unsigned long field, u64 *ret)
5908 {
5909         short offset = vmcs_field_to_offset(field);
5910         char *p;
5911
5912         if (offset < 0)
5913                 return 0;
5914
5915         p = ((char *)(get_vmcs12(vcpu))) + offset;
5916
5917         switch (vmcs_field_type(field)) {
5918         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5919                 *ret = *((natural_width *)p);
5920                 return 1;
5921         case VMCS_FIELD_TYPE_U16:
5922                 *ret = *((u16 *)p);
5923                 return 1;
5924         case VMCS_FIELD_TYPE_U32:
5925                 *ret = *((u32 *)p);
5926                 return 1;
5927         case VMCS_FIELD_TYPE_U64:
5928                 *ret = *((u64 *)p);
5929                 return 1;
5930         default:
5931                 return 0; /* can never happen. */
5932         }
5933 }
5934
5935
5936 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5937                                     unsigned long field, u64 field_value){
5938         short offset = vmcs_field_to_offset(field);
5939         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5940         if (offset < 0)
5941                 return false;
5942
5943         switch (vmcs_field_type(field)) {
5944         case VMCS_FIELD_TYPE_U16:
5945                 *(u16 *)p = field_value;
5946                 return true;
5947         case VMCS_FIELD_TYPE_U32:
5948                 *(u32 *)p = field_value;
5949                 return true;
5950         case VMCS_FIELD_TYPE_U64:
5951                 *(u64 *)p = field_value;
5952                 return true;
5953         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5954                 *(natural_width *)p = field_value;
5955                 return true;
5956         default:
5957                 return false; /* can never happen. */
5958         }
5959
5960 }
5961
5962 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5963 {
5964         int i;
5965         unsigned long field;
5966         u64 field_value;
5967         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5968         unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5969         int num_fields = max_shadow_read_write_fields;
5970
5971         vmcs_load(shadow_vmcs);
5972
5973         for (i = 0; i < num_fields; i++) {
5974                 field = fields[i];
5975                 switch (vmcs_field_type(field)) {
5976                 case VMCS_FIELD_TYPE_U16:
5977                         field_value = vmcs_read16(field);
5978                         break;
5979                 case VMCS_FIELD_TYPE_U32:
5980                         field_value = vmcs_read32(field);
5981                         break;
5982                 case VMCS_FIELD_TYPE_U64:
5983                         field_value = vmcs_read64(field);
5984                         break;
5985                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5986                         field_value = vmcs_readl(field);
5987                         break;
5988                 }
5989                 vmcs12_write_any(&vmx->vcpu, field, field_value);
5990         }
5991
5992         vmcs_clear(shadow_vmcs);
5993         vmcs_load(vmx->loaded_vmcs->vmcs);
5994 }
5995
5996 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
5997 {
5998         unsigned long *fields[] = {
5999                 (unsigned long *)shadow_read_write_fields,
6000                 (unsigned long *)shadow_read_only_fields
6001         };
6002         int num_lists =  ARRAY_SIZE(fields);
6003         int max_fields[] = {
6004                 max_shadow_read_write_fields,
6005                 max_shadow_read_only_fields
6006         };
6007         int i, q;
6008         unsigned long field;
6009         u64 field_value = 0;
6010         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6011
6012         vmcs_load(shadow_vmcs);
6013
6014         for (q = 0; q < num_lists; q++) {
6015                 for (i = 0; i < max_fields[q]; i++) {
6016                         field = fields[q][i];
6017                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6018
6019                         switch (vmcs_field_type(field)) {
6020                         case VMCS_FIELD_TYPE_U16:
6021                                 vmcs_write16(field, (u16)field_value);
6022                                 break;
6023                         case VMCS_FIELD_TYPE_U32:
6024                                 vmcs_write32(field, (u32)field_value);
6025                                 break;
6026                         case VMCS_FIELD_TYPE_U64:
6027                                 vmcs_write64(field, (u64)field_value);
6028                                 break;
6029                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6030                                 vmcs_writel(field, (long)field_value);
6031                                 break;
6032                         }
6033                 }
6034         }
6035
6036         vmcs_clear(shadow_vmcs);
6037         vmcs_load(vmx->loaded_vmcs->vmcs);
6038 }
6039
6040 /*
6041  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6042  * used before) all generate the same failure when it is missing.
6043  */
6044 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6045 {
6046         struct vcpu_vmx *vmx = to_vmx(vcpu);
6047         if (vmx->nested.current_vmptr == -1ull) {
6048                 nested_vmx_failInvalid(vcpu);
6049                 skip_emulated_instruction(vcpu);
6050                 return 0;
6051         }
6052         return 1;
6053 }
6054
6055 static int handle_vmread(struct kvm_vcpu *vcpu)
6056 {
6057         unsigned long field;
6058         u64 field_value;
6059         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6060         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6061         gva_t gva = 0;
6062
6063         if (!nested_vmx_check_permission(vcpu) ||
6064             !nested_vmx_check_vmcs12(vcpu))
6065                 return 1;
6066
6067         /* Decode instruction info and find the field to read */
6068         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6069         /* Read the field, zero-extended to a u64 field_value */
6070         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6071                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6072                 skip_emulated_instruction(vcpu);
6073                 return 1;
6074         }
6075         /*
6076          * Now copy part of this value to register or memory, as requested.
6077          * Note that the number of bits actually copied is 32 or 64 depending
6078          * on the guest's mode (32 or 64 bit), not on the given field's length.
6079          */
6080         if (vmx_instruction_info & (1u << 10)) {
6081                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6082                         field_value);
6083         } else {
6084                 if (get_vmx_mem_address(vcpu, exit_qualification,
6085                                 vmx_instruction_info, &gva))
6086                         return 1;
6087                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6088                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6089                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6090         }
6091
6092         nested_vmx_succeed(vcpu);
6093         skip_emulated_instruction(vcpu);
6094         return 1;
6095 }
6096
6097
6098 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6099 {
6100         unsigned long field;
6101         gva_t gva;
6102         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6103         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6104         /* The value to write might be 32 or 64 bits, depending on L1's long
6105          * mode, and eventually we need to write that into a field of several
6106          * possible lengths. The code below first zero-extends the value to 64
6107          * bit (field_value), and then copies only the approriate number of
6108          * bits into the vmcs12 field.
6109          */
6110         u64 field_value = 0;
6111         struct x86_exception e;
6112
6113         if (!nested_vmx_check_permission(vcpu) ||
6114             !nested_vmx_check_vmcs12(vcpu))
6115                 return 1;
6116
6117         if (vmx_instruction_info & (1u << 10))
6118                 field_value = kvm_register_read(vcpu,
6119                         (((vmx_instruction_info) >> 3) & 0xf));
6120         else {
6121                 if (get_vmx_mem_address(vcpu, exit_qualification,
6122                                 vmx_instruction_info, &gva))
6123                         return 1;
6124                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6125                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6126                         kvm_inject_page_fault(vcpu, &e);
6127                         return 1;
6128                 }
6129         }
6130
6131
6132         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6133         if (vmcs_field_readonly(field)) {
6134                 nested_vmx_failValid(vcpu,
6135                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6136                 skip_emulated_instruction(vcpu);
6137                 return 1;
6138         }
6139
6140         if (!vmcs12_write_any(vcpu, field, field_value)) {
6141                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6142                 skip_emulated_instruction(vcpu);
6143                 return 1;
6144         }
6145
6146         nested_vmx_succeed(vcpu);
6147         skip_emulated_instruction(vcpu);
6148         return 1;
6149 }
6150
6151 /* Emulate the VMPTRLD instruction */
6152 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6153 {
6154         struct vcpu_vmx *vmx = to_vmx(vcpu);
6155         gva_t gva;
6156         gpa_t vmptr;
6157         struct x86_exception e;
6158         u32 exec_control;
6159
6160         if (!nested_vmx_check_permission(vcpu))
6161                 return 1;
6162
6163         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6164                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6165                 return 1;
6166
6167         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6168                                 sizeof(vmptr), &e)) {
6169                 kvm_inject_page_fault(vcpu, &e);
6170                 return 1;
6171         }
6172
6173         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6174                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6175                 skip_emulated_instruction(vcpu);
6176                 return 1;
6177         }
6178
6179         if (vmx->nested.current_vmptr != vmptr) {
6180                 struct vmcs12 *new_vmcs12;
6181                 struct page *page;
6182                 page = nested_get_page(vcpu, vmptr);
6183                 if (page == NULL) {
6184                         nested_vmx_failInvalid(vcpu);
6185                         skip_emulated_instruction(vcpu);
6186                         return 1;
6187                 }
6188                 new_vmcs12 = kmap(page);
6189                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6190                         kunmap(page);
6191                         nested_release_page_clean(page);
6192                         nested_vmx_failValid(vcpu,
6193                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6194                         skip_emulated_instruction(vcpu);
6195                         return 1;
6196                 }
6197                 if (vmx->nested.current_vmptr != -1ull)
6198                         nested_release_vmcs12(vmx);
6199
6200                 vmx->nested.current_vmptr = vmptr;
6201                 vmx->nested.current_vmcs12 = new_vmcs12;
6202                 vmx->nested.current_vmcs12_page = page;
6203                 if (enable_shadow_vmcs) {
6204                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6205                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6206                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6207                         vmcs_write64(VMCS_LINK_POINTER,
6208                                      __pa(vmx->nested.current_shadow_vmcs));
6209                         vmx->nested.sync_shadow_vmcs = true;
6210                 }
6211         }
6212
6213         nested_vmx_succeed(vcpu);
6214         skip_emulated_instruction(vcpu);
6215         return 1;
6216 }
6217
6218 /* Emulate the VMPTRST instruction */
6219 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6220 {
6221         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6222         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6223         gva_t vmcs_gva;
6224         struct x86_exception e;
6225
6226         if (!nested_vmx_check_permission(vcpu))
6227                 return 1;
6228
6229         if (get_vmx_mem_address(vcpu, exit_qualification,
6230                         vmx_instruction_info, &vmcs_gva))
6231                 return 1;
6232         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6233         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6234                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6235                                  sizeof(u64), &e)) {
6236                 kvm_inject_page_fault(vcpu, &e);
6237                 return 1;
6238         }
6239         nested_vmx_succeed(vcpu);
6240         skip_emulated_instruction(vcpu);
6241         return 1;
6242 }
6243
6244 /*
6245  * The exit handlers return 1 if the exit was handled fully and guest execution
6246  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6247  * to be done to userspace and return 0.
6248  */
6249 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6250         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6251         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6252         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6253         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6254         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6255         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6256         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6257         [EXIT_REASON_CPUID]                   = handle_cpuid,
6258         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6259         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6260         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6261         [EXIT_REASON_HLT]                     = handle_halt,
6262         [EXIT_REASON_INVD]                    = handle_invd,
6263         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6264         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6265         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6266         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6267         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6268         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6269         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6270         [EXIT_REASON_VMREAD]                  = handle_vmread,
6271         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6272         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6273         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6274         [EXIT_REASON_VMON]                    = handle_vmon,
6275         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6276         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6277         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6278         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6279         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6280         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6281         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6282         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6283         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6284         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6285         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6286         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6287         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6288 };
6289
6290 static const int kvm_vmx_max_exit_handlers =
6291         ARRAY_SIZE(kvm_vmx_exit_handlers);
6292
6293 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6294                                        struct vmcs12 *vmcs12)
6295 {
6296         unsigned long exit_qualification;
6297         gpa_t bitmap, last_bitmap;
6298         unsigned int port;
6299         int size;
6300         u8 b;
6301
6302         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6303                 return 1;
6304
6305         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6306                 return 0;
6307
6308         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6309
6310         port = exit_qualification >> 16;
6311         size = (exit_qualification & 7) + 1;
6312
6313         last_bitmap = (gpa_t)-1;
6314         b = -1;
6315
6316         while (size > 0) {
6317                 if (port < 0x8000)
6318                         bitmap = vmcs12->io_bitmap_a;
6319                 else if (port < 0x10000)
6320                         bitmap = vmcs12->io_bitmap_b;
6321                 else
6322                         return 1;
6323                 bitmap += (port & 0x7fff) / 8;
6324
6325                 if (last_bitmap != bitmap)
6326                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6327                                 return 1;
6328                 if (b & (1 << (port & 7)))
6329                         return 1;
6330
6331                 port++;
6332                 size--;
6333                 last_bitmap = bitmap;
6334         }
6335
6336         return 0;
6337 }
6338
6339 /*
6340  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6341  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6342  * disinterest in the current event (read or write a specific MSR) by using an
6343  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6344  */
6345 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6346         struct vmcs12 *vmcs12, u32 exit_reason)
6347 {
6348         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6349         gpa_t bitmap;
6350
6351         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6352                 return 1;
6353
6354         /*
6355          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6356          * for the four combinations of read/write and low/high MSR numbers.
6357          * First we need to figure out which of the four to use:
6358          */
6359         bitmap = vmcs12->msr_bitmap;
6360         if (exit_reason == EXIT_REASON_MSR_WRITE)
6361                 bitmap += 2048;
6362         if (msr_index >= 0xc0000000) {
6363                 msr_index -= 0xc0000000;
6364                 bitmap += 1024;
6365         }
6366
6367         /* Then read the msr_index'th bit from this bitmap: */
6368         if (msr_index < 1024*8) {
6369                 unsigned char b;
6370                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6371                         return 1;
6372                 return 1 & (b >> (msr_index & 7));
6373         } else
6374                 return 1; /* let L1 handle the wrong parameter */
6375 }
6376
6377 /*
6378  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6379  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6380  * intercept (via guest_host_mask etc.) the current event.
6381  */
6382 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6383         struct vmcs12 *vmcs12)
6384 {
6385         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6386         int cr = exit_qualification & 15;
6387         int reg = (exit_qualification >> 8) & 15;
6388         unsigned long val = kvm_register_read(vcpu, reg);
6389
6390         switch ((exit_qualification >> 4) & 3) {
6391         case 0: /* mov to cr */
6392                 switch (cr) {
6393                 case 0:
6394                         if (vmcs12->cr0_guest_host_mask &
6395                             (val ^ vmcs12->cr0_read_shadow))
6396                                 return 1;
6397                         break;
6398                 case 3:
6399                         if ((vmcs12->cr3_target_count >= 1 &&
6400                                         vmcs12->cr3_target_value0 == val) ||
6401                                 (vmcs12->cr3_target_count >= 2 &&
6402                                         vmcs12->cr3_target_value1 == val) ||
6403                                 (vmcs12->cr3_target_count >= 3 &&
6404                                         vmcs12->cr3_target_value2 == val) ||
6405                                 (vmcs12->cr3_target_count >= 4 &&
6406                                         vmcs12->cr3_target_value3 == val))
6407                                 return 0;
6408                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6409                                 return 1;
6410                         break;
6411                 case 4:
6412                         if (vmcs12->cr4_guest_host_mask &
6413                             (vmcs12->cr4_read_shadow ^ val))
6414                                 return 1;
6415                         break;
6416                 case 8:
6417                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6418                                 return 1;
6419                         break;
6420                 }
6421                 break;
6422         case 2: /* clts */
6423                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6424                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6425                         return 1;
6426                 break;
6427         case 1: /* mov from cr */
6428                 switch (cr) {
6429                 case 3:
6430                         if (vmcs12->cpu_based_vm_exec_control &
6431                             CPU_BASED_CR3_STORE_EXITING)
6432                                 return 1;
6433                         break;
6434                 case 8:
6435                         if (vmcs12->cpu_based_vm_exec_control &
6436                             CPU_BASED_CR8_STORE_EXITING)
6437                                 return 1;
6438                         break;
6439                 }
6440                 break;
6441         case 3: /* lmsw */
6442                 /*
6443                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6444                  * cr0. Other attempted changes are ignored, with no exit.
6445                  */
6446                 if (vmcs12->cr0_guest_host_mask & 0xe &
6447                     (val ^ vmcs12->cr0_read_shadow))
6448                         return 1;
6449                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6450                     !(vmcs12->cr0_read_shadow & 0x1) &&
6451                     (val & 0x1))
6452                         return 1;
6453                 break;
6454         }
6455         return 0;
6456 }
6457
6458 /*
6459  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6460  * should handle it ourselves in L0 (and then continue L2). Only call this
6461  * when in is_guest_mode (L2).
6462  */
6463 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6464 {
6465         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6466         struct vcpu_vmx *vmx = to_vmx(vcpu);
6467         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6468         u32 exit_reason = vmx->exit_reason;
6469
6470         if (vmx->nested.nested_run_pending)
6471                 return 0;
6472
6473         if (unlikely(vmx->fail)) {
6474                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6475                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6476                 return 1;
6477         }
6478
6479         switch (exit_reason) {
6480         case EXIT_REASON_EXCEPTION_NMI:
6481                 if (!is_exception(intr_info))
6482                         return 0;
6483                 else if (is_page_fault(intr_info))
6484                         return enable_ept;
6485                 return vmcs12->exception_bitmap &
6486                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6487         case EXIT_REASON_EXTERNAL_INTERRUPT:
6488                 return 0;
6489         case EXIT_REASON_TRIPLE_FAULT:
6490                 return 1;
6491         case EXIT_REASON_PENDING_INTERRUPT:
6492                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6493         case EXIT_REASON_NMI_WINDOW:
6494                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6495         case EXIT_REASON_TASK_SWITCH:
6496                 return 1;
6497         case EXIT_REASON_CPUID:
6498                 return 1;
6499         case EXIT_REASON_HLT:
6500                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6501         case EXIT_REASON_INVD:
6502                 return 1;
6503         case EXIT_REASON_INVLPG:
6504                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6505         case EXIT_REASON_RDPMC:
6506                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6507         case EXIT_REASON_RDTSC:
6508                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6509         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6510         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6511         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6512         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6513         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6514                 /*
6515                  * VMX instructions trap unconditionally. This allows L1 to
6516                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6517                  */
6518                 return 1;
6519         case EXIT_REASON_CR_ACCESS:
6520                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6521         case EXIT_REASON_DR_ACCESS:
6522                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6523         case EXIT_REASON_IO_INSTRUCTION:
6524                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6525         case EXIT_REASON_MSR_READ:
6526         case EXIT_REASON_MSR_WRITE:
6527                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6528         case EXIT_REASON_INVALID_STATE:
6529                 return 1;
6530         case EXIT_REASON_MWAIT_INSTRUCTION:
6531                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6532         case EXIT_REASON_MONITOR_INSTRUCTION:
6533                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6534         case EXIT_REASON_PAUSE_INSTRUCTION:
6535                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6536                         nested_cpu_has2(vmcs12,
6537                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6538         case EXIT_REASON_MCE_DURING_VMENTRY:
6539                 return 0;
6540         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6541                 return 1;
6542         case EXIT_REASON_APIC_ACCESS:
6543                 return nested_cpu_has2(vmcs12,
6544                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6545         case EXIT_REASON_EPT_VIOLATION:
6546         case EXIT_REASON_EPT_MISCONFIG:
6547                 return 0;
6548         case EXIT_REASON_PREEMPTION_TIMER:
6549                 return vmcs12->pin_based_vm_exec_control &
6550                         PIN_BASED_VMX_PREEMPTION_TIMER;
6551         case EXIT_REASON_WBINVD:
6552                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6553         case EXIT_REASON_XSETBV:
6554                 return 1;
6555         default:
6556                 return 1;
6557         }
6558 }
6559
6560 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6561 {
6562         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6563         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6564 }
6565
6566 /*
6567  * The guest has exited.  See if we can fix it or if we need userspace
6568  * assistance.
6569  */
6570 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6571 {
6572         struct vcpu_vmx *vmx = to_vmx(vcpu);
6573         u32 exit_reason = vmx->exit_reason;
6574         u32 vectoring_info = vmx->idt_vectoring_info;
6575
6576         /* If guest state is invalid, start emulating */
6577         if (vmx->emulation_required)
6578                 return handle_invalid_guest_state(vcpu);
6579
6580         /*
6581          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6582          * we did not inject a still-pending event to L1 now because of
6583          * nested_run_pending, we need to re-enable this bit.
6584          */
6585         if (vmx->nested.nested_run_pending)
6586                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6587
6588         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6589             exit_reason == EXIT_REASON_VMRESUME))
6590                 vmx->nested.nested_run_pending = 1;
6591         else
6592                 vmx->nested.nested_run_pending = 0;
6593
6594         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6595                 nested_vmx_vmexit(vcpu);
6596                 return 1;
6597         }
6598
6599         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6600                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6601                 vcpu->run->fail_entry.hardware_entry_failure_reason
6602                         = exit_reason;
6603                 return 0;
6604         }
6605
6606         if (unlikely(vmx->fail)) {
6607                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6608                 vcpu->run->fail_entry.hardware_entry_failure_reason
6609                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6610                 return 0;
6611         }
6612
6613         /*
6614          * Note:
6615          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6616          * delivery event since it indicates guest is accessing MMIO.
6617          * The vm-exit can be triggered again after return to guest that
6618          * will cause infinite loop.
6619          */
6620         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6621                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6622                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6623                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6624                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6625                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6626                 vcpu->run->internal.ndata = 2;
6627                 vcpu->run->internal.data[0] = vectoring_info;
6628                 vcpu->run->internal.data[1] = exit_reason;
6629                 return 0;
6630         }
6631
6632         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6633             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6634                                         get_vmcs12(vcpu), vcpu)))) {
6635                 if (vmx_interrupt_allowed(vcpu)) {
6636                         vmx->soft_vnmi_blocked = 0;
6637                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6638                            vcpu->arch.nmi_pending) {
6639                         /*
6640                          * This CPU don't support us in finding the end of an
6641                          * NMI-blocked window if the guest runs with IRQs
6642                          * disabled. So we pull the trigger after 1 s of
6643                          * futile waiting, but inform the user about this.
6644                          */
6645                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6646                                "state on VCPU %d after 1 s timeout\n",
6647                                __func__, vcpu->vcpu_id);
6648                         vmx->soft_vnmi_blocked = 0;
6649                 }
6650         }
6651
6652         if (exit_reason < kvm_vmx_max_exit_handlers
6653             && kvm_vmx_exit_handlers[exit_reason])
6654                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6655         else {
6656                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6657                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6658         }
6659         return 0;
6660 }
6661
6662 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6663 {
6664         if (irr == -1 || tpr < irr) {
6665                 vmcs_write32(TPR_THRESHOLD, 0);
6666                 return;
6667         }
6668
6669         vmcs_write32(TPR_THRESHOLD, irr);
6670 }
6671
6672 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6673 {
6674         u32 sec_exec_control;
6675
6676         /*
6677          * There is not point to enable virtualize x2apic without enable
6678          * apicv
6679          */
6680         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6681                                 !vmx_vm_has_apicv(vcpu->kvm))
6682                 return;
6683
6684         if (!vm_need_tpr_shadow(vcpu->kvm))
6685                 return;
6686
6687         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6688
6689         if (set) {
6690                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6691                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6692         } else {
6693                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6694                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6695         }
6696         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6697
6698         vmx_set_msr_bitmap(vcpu);
6699 }
6700
6701 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6702 {
6703         u16 status;
6704         u8 old;
6705
6706         if (!vmx_vm_has_apicv(kvm))
6707                 return;
6708
6709         if (isr == -1)
6710                 isr = 0;
6711
6712         status = vmcs_read16(GUEST_INTR_STATUS);
6713         old = status >> 8;
6714         if (isr != old) {
6715                 status &= 0xff;
6716                 status |= isr << 8;
6717                 vmcs_write16(GUEST_INTR_STATUS, status);
6718         }
6719 }
6720
6721 static void vmx_set_rvi(int vector)
6722 {
6723         u16 status;
6724         u8 old;
6725
6726         status = vmcs_read16(GUEST_INTR_STATUS);
6727         old = (u8)status & 0xff;
6728         if ((u8)vector != old) {
6729                 status &= ~0xff;
6730                 status |= (u8)vector;
6731                 vmcs_write16(GUEST_INTR_STATUS, status);
6732         }
6733 }
6734
6735 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6736 {
6737         if (max_irr == -1)
6738                 return;
6739
6740         vmx_set_rvi(max_irr);
6741 }
6742
6743 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6744 {
6745         if (!vmx_vm_has_apicv(vcpu->kvm))
6746                 return;
6747
6748         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6749         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6750         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6751         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6752 }
6753
6754 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6755 {
6756         u32 exit_intr_info;
6757
6758         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6759               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6760                 return;
6761
6762         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6763         exit_intr_info = vmx->exit_intr_info;
6764
6765         /* Handle machine checks before interrupts are enabled */
6766         if (is_machine_check(exit_intr_info))
6767                 kvm_machine_check();
6768
6769         /* We need to handle NMIs before interrupts are enabled */
6770         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6771             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6772                 kvm_before_handle_nmi(&vmx->vcpu);
6773                 asm("int $2");
6774                 kvm_after_handle_nmi(&vmx->vcpu);
6775         }
6776 }
6777
6778 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6779 {
6780         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6781
6782         /*
6783          * If external interrupt exists, IF bit is set in rflags/eflags on the
6784          * interrupt stack frame, and interrupt will be enabled on a return
6785          * from interrupt handler.
6786          */
6787         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6788                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6789                 unsigned int vector;
6790                 unsigned long entry;
6791                 gate_desc *desc;
6792                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6793 #ifdef CONFIG_X86_64
6794                 unsigned long tmp;
6795 #endif
6796
6797                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6798                 desc = (gate_desc *)vmx->host_idt_base + vector;
6799                 entry = gate_offset(*desc);
6800                 asm volatile(
6801 #ifdef CONFIG_X86_64
6802                         "mov %%" _ASM_SP ", %[sp]\n\t"
6803                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6804                         "push $%c[ss]\n\t"
6805                         "push %[sp]\n\t"
6806 #endif
6807                         "pushf\n\t"
6808                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6809                         __ASM_SIZE(push) " $%c[cs]\n\t"
6810                         "call *%[entry]\n\t"
6811                         :
6812 #ifdef CONFIG_X86_64
6813                         [sp]"=&r"(tmp)
6814 #endif
6815                         :
6816                         [entry]"r"(entry),
6817                         [ss]"i"(__KERNEL_DS),
6818                         [cs]"i"(__KERNEL_CS)
6819                         );
6820         } else
6821                 local_irq_enable();
6822 }
6823
6824 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6825 {
6826         u32 exit_intr_info;
6827         bool unblock_nmi;
6828         u8 vector;
6829         bool idtv_info_valid;
6830
6831         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6832
6833         if (cpu_has_virtual_nmis()) {
6834                 if (vmx->nmi_known_unmasked)
6835                         return;
6836                 /*
6837                  * Can't use vmx->exit_intr_info since we're not sure what
6838                  * the exit reason is.
6839                  */
6840                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6841                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6842                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6843                 /*
6844                  * SDM 3: 27.7.1.2 (September 2008)
6845                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6846                  * a guest IRET fault.
6847                  * SDM 3: 23.2.2 (September 2008)
6848                  * Bit 12 is undefined in any of the following cases:
6849                  *  If the VM exit sets the valid bit in the IDT-vectoring
6850                  *   information field.
6851                  *  If the VM exit is due to a double fault.
6852                  */
6853                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6854                     vector != DF_VECTOR && !idtv_info_valid)
6855                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6856                                       GUEST_INTR_STATE_NMI);
6857                 else
6858                         vmx->nmi_known_unmasked =
6859                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6860                                   & GUEST_INTR_STATE_NMI);
6861         } else if (unlikely(vmx->soft_vnmi_blocked))
6862                 vmx->vnmi_blocked_time +=
6863                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6864 }
6865
6866 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6867                                       u32 idt_vectoring_info,
6868                                       int instr_len_field,
6869                                       int error_code_field)
6870 {
6871         u8 vector;
6872         int type;
6873         bool idtv_info_valid;
6874
6875         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6876
6877         vcpu->arch.nmi_injected = false;
6878         kvm_clear_exception_queue(vcpu);
6879         kvm_clear_interrupt_queue(vcpu);
6880
6881         if (!idtv_info_valid)
6882                 return;
6883
6884         kvm_make_request(KVM_REQ_EVENT, vcpu);
6885
6886         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6887         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6888
6889         switch (type) {
6890         case INTR_TYPE_NMI_INTR:
6891                 vcpu->arch.nmi_injected = true;
6892                 /*
6893                  * SDM 3: 27.7.1.2 (September 2008)
6894                  * Clear bit "block by NMI" before VM entry if a NMI
6895                  * delivery faulted.
6896                  */
6897                 vmx_set_nmi_mask(vcpu, false);
6898                 break;
6899         case INTR_TYPE_SOFT_EXCEPTION:
6900                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6901                 /* fall through */
6902         case INTR_TYPE_HARD_EXCEPTION:
6903                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6904                         u32 err = vmcs_read32(error_code_field);
6905                         kvm_queue_exception_e(vcpu, vector, err);
6906                 } else
6907                         kvm_queue_exception(vcpu, vector);
6908                 break;
6909         case INTR_TYPE_SOFT_INTR:
6910                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6911                 /* fall through */
6912         case INTR_TYPE_EXT_INTR:
6913                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6914                 break;
6915         default:
6916                 break;
6917         }
6918 }
6919
6920 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6921 {
6922         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6923                                   VM_EXIT_INSTRUCTION_LEN,
6924                                   IDT_VECTORING_ERROR_CODE);
6925 }
6926
6927 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6928 {
6929         __vmx_complete_interrupts(vcpu,
6930                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6931                                   VM_ENTRY_INSTRUCTION_LEN,
6932                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6933
6934         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6935 }
6936
6937 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6938 {
6939         int i, nr_msrs;
6940         struct perf_guest_switch_msr *msrs;
6941
6942         msrs = perf_guest_get_msrs(&nr_msrs);
6943
6944         if (!msrs)
6945                 return;
6946
6947         for (i = 0; i < nr_msrs; i++)
6948                 if (msrs[i].host == msrs[i].guest)
6949                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6950                 else
6951                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6952                                         msrs[i].host);
6953 }
6954
6955 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6956 {
6957         struct vcpu_vmx *vmx = to_vmx(vcpu);
6958         unsigned long debugctlmsr;
6959
6960         /* Record the guest's net vcpu time for enforced NMI injections. */
6961         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6962                 vmx->entry_time = ktime_get();
6963
6964         /* Don't enter VMX if guest state is invalid, let the exit handler
6965            start emulation until we arrive back to a valid state */
6966         if (vmx->emulation_required)
6967                 return;
6968
6969         if (vmx->nested.sync_shadow_vmcs) {
6970                 copy_vmcs12_to_shadow(vmx);
6971                 vmx->nested.sync_shadow_vmcs = false;
6972         }
6973
6974         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6975                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6976         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6977                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6978
6979         /* When single-stepping over STI and MOV SS, we must clear the
6980          * corresponding interruptibility bits in the guest state. Otherwise
6981          * vmentry fails as it then expects bit 14 (BS) in pending debug
6982          * exceptions being set, but that's not correct for the guest debugging
6983          * case. */
6984         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6985                 vmx_set_interrupt_shadow(vcpu, 0);
6986
6987         atomic_switch_perf_msrs(vmx);
6988         debugctlmsr = get_debugctlmsr();
6989
6990         vmx->__launched = vmx->loaded_vmcs->launched;
6991         asm(
6992                 /* Store host registers */
6993                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6994                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6995                 "push %%" _ASM_CX " \n\t"
6996                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6997                 "je 1f \n\t"
6998                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6999                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7000                 "1: \n\t"
7001                 /* Reload cr2 if changed */
7002                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7003                 "mov %%cr2, %%" _ASM_DX " \n\t"
7004                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7005                 "je 2f \n\t"
7006                 "mov %%" _ASM_AX", %%cr2 \n\t"
7007                 "2: \n\t"
7008                 /* Check if vmlaunch of vmresume is needed */
7009                 "cmpl $0, %c[launched](%0) \n\t"
7010                 /* Load guest registers.  Don't clobber flags. */
7011                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7012                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7013                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7014                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7015                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7016                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7017 #ifdef CONFIG_X86_64
7018                 "mov %c[r8](%0),  %%r8  \n\t"
7019                 "mov %c[r9](%0),  %%r9  \n\t"
7020                 "mov %c[r10](%0), %%r10 \n\t"
7021                 "mov %c[r11](%0), %%r11 \n\t"
7022                 "mov %c[r12](%0), %%r12 \n\t"
7023                 "mov %c[r13](%0), %%r13 \n\t"
7024                 "mov %c[r14](%0), %%r14 \n\t"
7025                 "mov %c[r15](%0), %%r15 \n\t"
7026 #endif
7027                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7028
7029                 /* Enter guest mode */
7030                 "jne 1f \n\t"
7031                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7032                 "jmp 2f \n\t"
7033                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7034                 "2: "
7035                 /* Save guest registers, load host registers, keep flags */
7036                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7037                 "pop %0 \n\t"
7038                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7039                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7040                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7041                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7042                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7043                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7044                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7045 #ifdef CONFIG_X86_64
7046                 "mov %%r8,  %c[r8](%0) \n\t"
7047                 "mov %%r9,  %c[r9](%0) \n\t"
7048                 "mov %%r10, %c[r10](%0) \n\t"
7049                 "mov %%r11, %c[r11](%0) \n\t"
7050                 "mov %%r12, %c[r12](%0) \n\t"
7051                 "mov %%r13, %c[r13](%0) \n\t"
7052                 "mov %%r14, %c[r14](%0) \n\t"
7053                 "mov %%r15, %c[r15](%0) \n\t"
7054 #endif
7055                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7056                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7057
7058                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7059                 "setbe %c[fail](%0) \n\t"
7060                 ".pushsection .rodata \n\t"
7061                 ".global vmx_return \n\t"
7062                 "vmx_return: " _ASM_PTR " 2b \n\t"
7063                 ".popsection"
7064               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7065                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7066                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7067                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7068                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7069                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7070                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7071                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7072                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7073                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7074                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7075 #ifdef CONFIG_X86_64
7076                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7077                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7078                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7079                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7080                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7081                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7082                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7083                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7084 #endif
7085                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7086                 [wordsize]"i"(sizeof(ulong))
7087               : "cc", "memory"
7088 #ifdef CONFIG_X86_64
7089                 , "rax", "rbx", "rdi", "rsi"
7090                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7091 #else
7092                 , "eax", "ebx", "edi", "esi"
7093 #endif
7094               );
7095
7096         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7097         if (debugctlmsr)
7098                 update_debugctlmsr(debugctlmsr);
7099
7100 #ifndef CONFIG_X86_64
7101         /*
7102          * The sysexit path does not restore ds/es, so we must set them to
7103          * a reasonable value ourselves.
7104          *
7105          * We can't defer this to vmx_load_host_state() since that function
7106          * may be executed in interrupt context, which saves and restore segments
7107          * around it, nullifying its effect.
7108          */
7109         loadsegment(ds, __USER_DS);
7110         loadsegment(es, __USER_DS);
7111 #endif
7112
7113         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7114                                   | (1 << VCPU_EXREG_RFLAGS)
7115                                   | (1 << VCPU_EXREG_CPL)
7116                                   | (1 << VCPU_EXREG_PDPTR)
7117                                   | (1 << VCPU_EXREG_SEGMENTS)
7118                                   | (1 << VCPU_EXREG_CR3));
7119         vcpu->arch.regs_dirty = 0;
7120
7121         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7122
7123         vmx->loaded_vmcs->launched = 1;
7124
7125         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7126         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7127
7128         vmx_complete_atomic_exit(vmx);
7129         vmx_recover_nmi_blocking(vmx);
7130         vmx_complete_interrupts(vmx);
7131 }
7132
7133 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7134 {
7135         struct vcpu_vmx *vmx = to_vmx(vcpu);
7136
7137         free_vpid(vmx);
7138         free_nested(vmx);
7139         free_loaded_vmcs(vmx->loaded_vmcs);
7140         kfree(vmx->guest_msrs);
7141         kvm_vcpu_uninit(vcpu);
7142         kmem_cache_free(kvm_vcpu_cache, vmx);
7143 }
7144
7145 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7146 {
7147         int err;
7148         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7149         int cpu;
7150
7151         if (!vmx)
7152                 return ERR_PTR(-ENOMEM);
7153
7154         allocate_vpid(vmx);
7155
7156         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7157         if (err)
7158                 goto free_vcpu;
7159
7160         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7161         err = -ENOMEM;
7162         if (!vmx->guest_msrs) {
7163                 goto uninit_vcpu;
7164         }
7165
7166         vmx->loaded_vmcs = &vmx->vmcs01;
7167         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7168         if (!vmx->loaded_vmcs->vmcs)
7169                 goto free_msrs;
7170         if (!vmm_exclusive)
7171                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7172         loaded_vmcs_init(vmx->loaded_vmcs);
7173         if (!vmm_exclusive)
7174                 kvm_cpu_vmxoff();
7175
7176         cpu = get_cpu();
7177         vmx_vcpu_load(&vmx->vcpu, cpu);
7178         vmx->vcpu.cpu = cpu;
7179         err = vmx_vcpu_setup(vmx);
7180         vmx_vcpu_put(&vmx->vcpu);
7181         put_cpu();
7182         if (err)
7183                 goto free_vmcs;
7184         if (vm_need_virtualize_apic_accesses(kvm)) {
7185                 err = alloc_apic_access_page(kvm);
7186                 if (err)
7187                         goto free_vmcs;
7188         }
7189
7190         if (enable_ept) {
7191                 if (!kvm->arch.ept_identity_map_addr)
7192                         kvm->arch.ept_identity_map_addr =
7193                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7194                 err = -ENOMEM;
7195                 if (alloc_identity_pagetable(kvm) != 0)
7196                         goto free_vmcs;
7197                 if (!init_rmode_identity_map(kvm))
7198                         goto free_vmcs;
7199         }
7200
7201         vmx->nested.current_vmptr = -1ull;
7202         vmx->nested.current_vmcs12 = NULL;
7203
7204         return &vmx->vcpu;
7205
7206 free_vmcs:
7207         free_loaded_vmcs(vmx->loaded_vmcs);
7208 free_msrs:
7209         kfree(vmx->guest_msrs);
7210 uninit_vcpu:
7211         kvm_vcpu_uninit(&vmx->vcpu);
7212 free_vcpu:
7213         free_vpid(vmx);
7214         kmem_cache_free(kvm_vcpu_cache, vmx);
7215         return ERR_PTR(err);
7216 }
7217
7218 static void __init vmx_check_processor_compat(void *rtn)
7219 {
7220         struct vmcs_config vmcs_conf;
7221
7222         *(int *)rtn = 0;
7223         if (setup_vmcs_config(&vmcs_conf) < 0)
7224                 *(int *)rtn = -EIO;
7225         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7226                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7227                                 smp_processor_id());
7228                 *(int *)rtn = -EIO;
7229         }
7230 }
7231
7232 static int get_ept_level(void)
7233 {
7234         return VMX_EPT_DEFAULT_GAW + 1;
7235 }
7236
7237 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7238 {
7239         u64 ret;
7240
7241         /* For VT-d and EPT combination
7242          * 1. MMIO: always map as UC
7243          * 2. EPT with VT-d:
7244          *   a. VT-d without snooping control feature: can't guarantee the
7245          *      result, try to trust guest.
7246          *   b. VT-d with snooping control feature: snooping control feature of
7247          *      VT-d engine can guarantee the cache correctness. Just set it
7248          *      to WB to keep consistent with host. So the same as item 3.
7249          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7250          *    consistent with host MTRR
7251          */
7252         if (is_mmio)
7253                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7254         else if (vcpu->kvm->arch.iommu_domain &&
7255                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7256                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7257                       VMX_EPT_MT_EPTE_SHIFT;
7258         else
7259                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7260                         | VMX_EPT_IPAT_BIT;
7261
7262         return ret;
7263 }
7264
7265 static int vmx_get_lpage_level(void)
7266 {
7267         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7268                 return PT_DIRECTORY_LEVEL;
7269         else
7270                 /* For shadow and EPT supported 1GB page */
7271                 return PT_PDPE_LEVEL;
7272 }
7273
7274 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7275 {
7276         struct kvm_cpuid_entry2 *best;
7277         struct vcpu_vmx *vmx = to_vmx(vcpu);
7278         u32 exec_control;
7279
7280         vmx->rdtscp_enabled = false;
7281         if (vmx_rdtscp_supported()) {
7282                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7283                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7284                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7285                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7286                                 vmx->rdtscp_enabled = true;
7287                         else {
7288                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7289                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7290                                                 exec_control);
7291                         }
7292                 }
7293         }
7294
7295         /* Exposing INVPCID only when PCID is exposed */
7296         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7297         if (vmx_invpcid_supported() &&
7298             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7299             guest_cpuid_has_pcid(vcpu)) {
7300                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7301                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7302                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7303                              exec_control);
7304         } else {
7305                 if (cpu_has_secondary_exec_ctrls()) {
7306                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7307                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7308                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7309                                      exec_control);
7310                 }
7311                 if (best)
7312                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7313         }
7314 }
7315
7316 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7317 {
7318         if (func == 1 && nested)
7319                 entry->ecx |= bit(X86_FEATURE_VMX);
7320 }
7321
7322 /*
7323  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7324  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7325  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7326  * guest in a way that will both be appropriate to L1's requests, and our
7327  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7328  * function also has additional necessary side-effects, like setting various
7329  * vcpu->arch fields.
7330  */
7331 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7332 {
7333         struct vcpu_vmx *vmx = to_vmx(vcpu);
7334         u32 exec_control;
7335
7336         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7337         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7338         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7339         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7340         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7341         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7342         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7343         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7344         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7345         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7346         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7347         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7348         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7349         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7350         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7351         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7352         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7353         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7354         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7355         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7356         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7357         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7358         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7359         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7360         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7361         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7362         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7363         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7364         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7365         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7366         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7367         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7368         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7369         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7370         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7371         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7372
7373         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7374         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7375                 vmcs12->vm_entry_intr_info_field);
7376         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7377                 vmcs12->vm_entry_exception_error_code);
7378         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7379                 vmcs12->vm_entry_instruction_len);
7380         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7381                 vmcs12->guest_interruptibility_info);
7382         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7383         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7384         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7385         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7386                 vmcs12->guest_pending_dbg_exceptions);
7387         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7388         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7389
7390         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7391
7392         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7393                 (vmcs_config.pin_based_exec_ctrl |
7394                  vmcs12->pin_based_vm_exec_control));
7395
7396         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7397                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7398                              vmcs12->vmx_preemption_timer_value);
7399
7400         /*
7401          * Whether page-faults are trapped is determined by a combination of
7402          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7403          * If enable_ept, L0 doesn't care about page faults and we should
7404          * set all of these to L1's desires. However, if !enable_ept, L0 does
7405          * care about (at least some) page faults, and because it is not easy
7406          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7407          * to exit on each and every L2 page fault. This is done by setting
7408          * MASK=MATCH=0 and (see below) EB.PF=1.
7409          * Note that below we don't need special code to set EB.PF beyond the
7410          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7411          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7412          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7413          *
7414          * A problem with this approach (when !enable_ept) is that L1 may be
7415          * injected with more page faults than it asked for. This could have
7416          * caused problems, but in practice existing hypervisors don't care.
7417          * To fix this, we will need to emulate the PFEC checking (on the L1
7418          * page tables), using walk_addr(), when injecting PFs to L1.
7419          */
7420         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7421                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7422         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7423                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7424
7425         if (cpu_has_secondary_exec_ctrls()) {
7426                 u32 exec_control = vmx_secondary_exec_control(vmx);
7427                 if (!vmx->rdtscp_enabled)
7428                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7429                 /* Take the following fields only from vmcs12 */
7430                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7431                 if (nested_cpu_has(vmcs12,
7432                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7433                         exec_control |= vmcs12->secondary_vm_exec_control;
7434
7435                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7436                         /*
7437                          * Translate L1 physical address to host physical
7438                          * address for vmcs02. Keep the page pinned, so this
7439                          * physical address remains valid. We keep a reference
7440                          * to it so we can release it later.
7441                          */
7442                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7443                                 nested_release_page(vmx->nested.apic_access_page);
7444                         vmx->nested.apic_access_page =
7445                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7446                         /*
7447                          * If translation failed, no matter: This feature asks
7448                          * to exit when accessing the given address, and if it
7449                          * can never be accessed, this feature won't do
7450                          * anything anyway.
7451                          */
7452                         if (!vmx->nested.apic_access_page)
7453                                 exec_control &=
7454                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7455                         else
7456                                 vmcs_write64(APIC_ACCESS_ADDR,
7457                                   page_to_phys(vmx->nested.apic_access_page));
7458                 }
7459
7460                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7461         }
7462
7463
7464         /*
7465          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7466          * Some constant fields are set here by vmx_set_constant_host_state().
7467          * Other fields are different per CPU, and will be set later when
7468          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7469          */
7470         vmx_set_constant_host_state(vmx);
7471
7472         /*
7473          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7474          * entry, but only if the current (host) sp changed from the value
7475          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7476          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7477          * here we just force the write to happen on entry.
7478          */
7479         vmx->host_rsp = 0;
7480
7481         exec_control = vmx_exec_control(vmx); /* L0's desires */
7482         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7483         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7484         exec_control &= ~CPU_BASED_TPR_SHADOW;
7485         exec_control |= vmcs12->cpu_based_vm_exec_control;
7486         /*
7487          * Merging of IO and MSR bitmaps not currently supported.
7488          * Rather, exit every time.
7489          */
7490         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7491         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7492         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7493
7494         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7495
7496         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7497          * bitwise-or of what L1 wants to trap for L2, and what we want to
7498          * trap. Note that CR0.TS also needs updating - we do this later.
7499          */
7500         update_exception_bitmap(vcpu);
7501         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7502         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7503
7504         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7505         vmcs_write32(VM_EXIT_CONTROLS,
7506                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7507         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7508                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7509
7510         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7511                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7512         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7513                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7514
7515
7516         set_cr4_guest_host_mask(vmx);
7517
7518         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7519                 vmcs_write64(TSC_OFFSET,
7520                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7521         else
7522                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7523
7524         if (enable_vpid) {
7525                 /*
7526                  * Trivially support vpid by letting L2s share their parent
7527                  * L1's vpid. TODO: move to a more elaborate solution, giving
7528                  * each L2 its own vpid and exposing the vpid feature to L1.
7529                  */
7530                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7531                 vmx_flush_tlb(vcpu);
7532         }
7533
7534         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7535                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7536         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7537                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7538         else
7539                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7540         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7541         vmx_set_efer(vcpu, vcpu->arch.efer);
7542
7543         /*
7544          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7545          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7546          * The CR0_READ_SHADOW is what L2 should have expected to read given
7547          * the specifications by L1; It's not enough to take
7548          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7549          * have more bits than L1 expected.
7550          */
7551         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7552         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7553
7554         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7555         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7556
7557         /* shadow page tables on either EPT or shadow page tables */
7558         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7559         kvm_mmu_reset_context(vcpu);
7560
7561         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7562         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7563 }
7564
7565 /*
7566  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7567  * for running an L2 nested guest.
7568  */
7569 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7570 {
7571         struct vmcs12 *vmcs12;
7572         struct vcpu_vmx *vmx = to_vmx(vcpu);
7573         int cpu;
7574         struct loaded_vmcs *vmcs02;
7575         bool ia32e;
7576
7577         if (!nested_vmx_check_permission(vcpu) ||
7578             !nested_vmx_check_vmcs12(vcpu))
7579                 return 1;
7580
7581         skip_emulated_instruction(vcpu);
7582         vmcs12 = get_vmcs12(vcpu);
7583
7584         if (enable_shadow_vmcs)
7585                 copy_shadow_to_vmcs12(vmx);
7586
7587         /*
7588          * The nested entry process starts with enforcing various prerequisites
7589          * on vmcs12 as required by the Intel SDM, and act appropriately when
7590          * they fail: As the SDM explains, some conditions should cause the
7591          * instruction to fail, while others will cause the instruction to seem
7592          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7593          * To speed up the normal (success) code path, we should avoid checking
7594          * for misconfigurations which will anyway be caught by the processor
7595          * when using the merged vmcs02.
7596          */
7597         if (vmcs12->launch_state == launch) {
7598                 nested_vmx_failValid(vcpu,
7599                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7600                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7601                 return 1;
7602         }
7603
7604         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7605                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7606                 return 1;
7607         }
7608
7609         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7610                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7611                 /*TODO: Also verify bits beyond physical address width are 0*/
7612                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7613                 return 1;
7614         }
7615
7616         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7617                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7618                 /*TODO: Also verify bits beyond physical address width are 0*/
7619                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7620                 return 1;
7621         }
7622
7623         if (vmcs12->vm_entry_msr_load_count > 0 ||
7624             vmcs12->vm_exit_msr_load_count > 0 ||
7625             vmcs12->vm_exit_msr_store_count > 0) {
7626                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7627                                     __func__);
7628                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7629                 return 1;
7630         }
7631
7632         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7633               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7634             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7635               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7636             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7637               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7638             !vmx_control_verify(vmcs12->vm_exit_controls,
7639               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7640             !vmx_control_verify(vmcs12->vm_entry_controls,
7641               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7642         {
7643                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7644                 return 1;
7645         }
7646
7647         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7648             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7649                 nested_vmx_failValid(vcpu,
7650                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7651                 return 1;
7652         }
7653
7654         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7655             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7656                 nested_vmx_entry_failure(vcpu, vmcs12,
7657                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7658                 return 1;
7659         }
7660         if (vmcs12->vmcs_link_pointer != -1ull) {
7661                 nested_vmx_entry_failure(vcpu, vmcs12,
7662                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7663                 return 1;
7664         }
7665
7666         /*
7667          * If the load IA32_EFER VM-entry control is 1, the following checks
7668          * are performed on the field for the IA32_EFER MSR:
7669          * - Bits reserved in the IA32_EFER MSR must be 0.
7670          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7671          *   the IA-32e mode guest VM-exit control. It must also be identical
7672          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7673          *   CR0.PG) is 1.
7674          */
7675         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7676                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7677                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7678                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7679                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7680                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7681                         nested_vmx_entry_failure(vcpu, vmcs12,
7682                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7683                         return 1;
7684                 }
7685         }
7686
7687         /*
7688          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7689          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7690          * the values of the LMA and LME bits in the field must each be that of
7691          * the host address-space size VM-exit control.
7692          */
7693         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7694                 ia32e = (vmcs12->vm_exit_controls &
7695                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7696                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7697                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7698                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7699                         nested_vmx_entry_failure(vcpu, vmcs12,
7700                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7701                         return 1;
7702                 }
7703         }
7704
7705         /*
7706          * We're finally done with prerequisite checking, and can start with
7707          * the nested entry.
7708          */
7709
7710         vmcs02 = nested_get_current_vmcs02(vmx);
7711         if (!vmcs02)
7712                 return -ENOMEM;
7713
7714         enter_guest_mode(vcpu);
7715
7716         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7717
7718         cpu = get_cpu();
7719         vmx->loaded_vmcs = vmcs02;
7720         vmx_vcpu_put(vcpu);
7721         vmx_vcpu_load(vcpu, cpu);
7722         vcpu->cpu = cpu;
7723         put_cpu();
7724
7725         vmx_segment_cache_clear(vmx);
7726
7727         vmcs12->launch_state = 1;
7728
7729         prepare_vmcs02(vcpu, vmcs12);
7730
7731         /*
7732          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7733          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7734          * returned as far as L1 is concerned. It will only return (and set
7735          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7736          */
7737         return 1;
7738 }
7739
7740 /*
7741  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7742  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7743  * This function returns the new value we should put in vmcs12.guest_cr0.
7744  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7745  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7746  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7747  *     didn't trap the bit, because if L1 did, so would L0).
7748  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7749  *     been modified by L2, and L1 knows it. So just leave the old value of
7750  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7751  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7752  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7753  *     changed these bits, and therefore they need to be updated, but L0
7754  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7755  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7756  */
7757 static inline unsigned long
7758 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7759 {
7760         return
7761         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7762         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7763         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7764                         vcpu->arch.cr0_guest_owned_bits));
7765 }
7766
7767 static inline unsigned long
7768 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7769 {
7770         return
7771         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7772         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7773         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7774                         vcpu->arch.cr4_guest_owned_bits));
7775 }
7776
7777 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7778                                        struct vmcs12 *vmcs12)
7779 {
7780         u32 idt_vectoring;
7781         unsigned int nr;
7782
7783         if (vcpu->arch.exception.pending) {
7784                 nr = vcpu->arch.exception.nr;
7785                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7786
7787                 if (kvm_exception_is_soft(nr)) {
7788                         vmcs12->vm_exit_instruction_len =
7789                                 vcpu->arch.event_exit_inst_len;
7790                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7791                 } else
7792                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7793
7794                 if (vcpu->arch.exception.has_error_code) {
7795                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7796                         vmcs12->idt_vectoring_error_code =
7797                                 vcpu->arch.exception.error_code;
7798                 }
7799
7800                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7801         } else if (vcpu->arch.nmi_pending) {
7802                 vmcs12->idt_vectoring_info_field =
7803                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7804         } else if (vcpu->arch.interrupt.pending) {
7805                 nr = vcpu->arch.interrupt.nr;
7806                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7807
7808                 if (vcpu->arch.interrupt.soft) {
7809                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7810                         vmcs12->vm_entry_instruction_len =
7811                                 vcpu->arch.event_exit_inst_len;
7812                 } else
7813                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7814
7815                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7816         }
7817 }
7818
7819 /*
7820  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7821  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7822  * and this function updates it to reflect the changes to the guest state while
7823  * L2 was running (and perhaps made some exits which were handled directly by L0
7824  * without going back to L1), and to reflect the exit reason.
7825  * Note that we do not have to copy here all VMCS fields, just those that
7826  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7827  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7828  * which already writes to vmcs12 directly.
7829  */
7830 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7831 {
7832         /* update guest state fields: */
7833         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7834         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7835
7836         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7837         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7838         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7839         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7840
7841         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7842         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7843         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7844         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7845         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7846         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7847         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7848         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7849         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7850         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7851         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7852         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7853         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7854         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7855         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7856         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7857         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7858         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7859         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7860         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7861         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7862         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7863         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7864         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7865         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7866         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7867         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7868         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7869         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7870         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7871         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7872         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7873         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7874         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7875         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7876         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7877
7878         vmcs12->guest_interruptibility_info =
7879                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7880         vmcs12->guest_pending_dbg_exceptions =
7881                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7882
7883         vmcs12->vm_entry_controls =
7884                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7885                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7886
7887         /* TODO: These cannot have changed unless we have MSR bitmaps and
7888          * the relevant bit asks not to trap the change */
7889         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7890         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7891                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7892         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7893         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7894         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7895
7896         /* update exit information fields: */
7897
7898         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7899         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7900
7901         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7902         if ((vmcs12->vm_exit_intr_info &
7903              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7904             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7905                 vmcs12->vm_exit_intr_error_code =
7906                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7907         vmcs12->idt_vectoring_info_field = 0;
7908         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7909         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7910
7911         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7912                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7913                  * instead of reading the real value. */
7914                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7915
7916                 /*
7917                  * Transfer the event that L0 or L1 may wanted to inject into
7918                  * L2 to IDT_VECTORING_INFO_FIELD.
7919                  */
7920                 vmcs12_save_pending_event(vcpu, vmcs12);
7921         }
7922
7923         /*
7924          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7925          * preserved above and would only end up incorrectly in L1.
7926          */
7927         vcpu->arch.nmi_injected = false;
7928         kvm_clear_exception_queue(vcpu);
7929         kvm_clear_interrupt_queue(vcpu);
7930 }
7931
7932 /*
7933  * A part of what we need to when the nested L2 guest exits and we want to
7934  * run its L1 parent, is to reset L1's guest state to the host state specified
7935  * in vmcs12.
7936  * This function is to be called not only on normal nested exit, but also on
7937  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7938  * Failures During or After Loading Guest State").
7939  * This function should be called when the active VMCS is L1's (vmcs01).
7940  */
7941 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7942                                    struct vmcs12 *vmcs12)
7943 {
7944         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7945                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7946         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7947                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7948         else
7949                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7950         vmx_set_efer(vcpu, vcpu->arch.efer);
7951
7952         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7953         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7954         vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
7955         /*
7956          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7957          * actually changed, because it depends on the current state of
7958          * fpu_active (which may have changed).
7959          * Note that vmx_set_cr0 refers to efer set above.
7960          */
7961         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7962         /*
7963          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7964          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7965          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7966          */
7967         update_exception_bitmap(vcpu);
7968         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7969         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7970
7971         /*
7972          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7973          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7974          */
7975         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7976         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7977
7978         /* shadow page tables on either EPT or shadow page tables */
7979         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7980         kvm_mmu_reset_context(vcpu);
7981
7982         if (enable_vpid) {
7983                 /*
7984                  * Trivially support vpid by letting L2s share their parent
7985                  * L1's vpid. TODO: move to a more elaborate solution, giving
7986                  * each L2 its own vpid and exposing the vpid feature to L1.
7987                  */
7988                 vmx_flush_tlb(vcpu);
7989         }
7990
7991
7992         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7993         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7994         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7995         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7996         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7997         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7998         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7999         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
8000         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
8001         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
8002         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
8003         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
8004         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
8005         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
8006         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
8007
8008         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8009                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8010         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8011                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8012                         vmcs12->host_ia32_perf_global_ctrl);
8013
8014         kvm_set_dr(vcpu, 7, 0x400);
8015         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8016 }
8017
8018 /*
8019  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8020  * and modify vmcs12 to make it see what it would expect to see there if
8021  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8022  */
8023 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8024 {
8025         struct vcpu_vmx *vmx = to_vmx(vcpu);
8026         int cpu;
8027         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8028
8029         /* trying to cancel vmlaunch/vmresume is a bug */
8030         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8031
8032         leave_guest_mode(vcpu);
8033         prepare_vmcs12(vcpu, vmcs12);
8034
8035         cpu = get_cpu();
8036         vmx->loaded_vmcs = &vmx->vmcs01;
8037         vmx_vcpu_put(vcpu);
8038         vmx_vcpu_load(vcpu, cpu);
8039         vcpu->cpu = cpu;
8040         put_cpu();
8041
8042         vmx_segment_cache_clear(vmx);
8043
8044         /* if no vmcs02 cache requested, remove the one we used */
8045         if (VMCS02_POOL_SIZE == 0)
8046                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8047
8048         load_vmcs12_host_state(vcpu, vmcs12);
8049
8050         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8051         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8052
8053         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8054         vmx->host_rsp = 0;
8055
8056         /* Unpin physical memory we referred to in vmcs02 */
8057         if (vmx->nested.apic_access_page) {
8058                 nested_release_page(vmx->nested.apic_access_page);
8059                 vmx->nested.apic_access_page = 0;
8060         }
8061
8062         /*
8063          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8064          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8065          * success or failure flag accordingly.
8066          */
8067         if (unlikely(vmx->fail)) {
8068                 vmx->fail = 0;
8069                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8070         } else
8071                 nested_vmx_succeed(vcpu);
8072         if (enable_shadow_vmcs)
8073                 vmx->nested.sync_shadow_vmcs = true;
8074 }
8075
8076 /*
8077  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8078  * 23.7 "VM-entry failures during or after loading guest state" (this also
8079  * lists the acceptable exit-reason and exit-qualification parameters).
8080  * It should only be called before L2 actually succeeded to run, and when
8081  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8082  */
8083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8084                         struct vmcs12 *vmcs12,
8085                         u32 reason, unsigned long qualification)
8086 {
8087         load_vmcs12_host_state(vcpu, vmcs12);
8088         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8089         vmcs12->exit_qualification = qualification;
8090         nested_vmx_succeed(vcpu);
8091         if (enable_shadow_vmcs)
8092                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8093 }
8094
8095 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8096                                struct x86_instruction_info *info,
8097                                enum x86_intercept_stage stage)
8098 {
8099         return X86EMUL_CONTINUE;
8100 }
8101
8102 static struct kvm_x86_ops vmx_x86_ops = {
8103         .cpu_has_kvm_support = cpu_has_kvm_support,
8104         .disabled_by_bios = vmx_disabled_by_bios,
8105         .hardware_setup = hardware_setup,
8106         .hardware_unsetup = hardware_unsetup,
8107         .check_processor_compatibility = vmx_check_processor_compat,
8108         .hardware_enable = hardware_enable,
8109         .hardware_disable = hardware_disable,
8110         .cpu_has_accelerated_tpr = report_flexpriority,
8111
8112         .vcpu_create = vmx_create_vcpu,
8113         .vcpu_free = vmx_free_vcpu,
8114         .vcpu_reset = vmx_vcpu_reset,
8115
8116         .prepare_guest_switch = vmx_save_host_state,
8117         .vcpu_load = vmx_vcpu_load,
8118         .vcpu_put = vmx_vcpu_put,
8119
8120         .update_db_bp_intercept = update_exception_bitmap,
8121         .get_msr = vmx_get_msr,
8122         .set_msr = vmx_set_msr,
8123         .get_segment_base = vmx_get_segment_base,
8124         .get_segment = vmx_get_segment,
8125         .set_segment = vmx_set_segment,
8126         .get_cpl = vmx_get_cpl,
8127         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8128         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8129         .decache_cr3 = vmx_decache_cr3,
8130         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8131         .set_cr0 = vmx_set_cr0,
8132         .set_cr3 = vmx_set_cr3,
8133         .set_cr4 = vmx_set_cr4,
8134         .set_efer = vmx_set_efer,
8135         .get_idt = vmx_get_idt,
8136         .set_idt = vmx_set_idt,
8137         .get_gdt = vmx_get_gdt,
8138         .set_gdt = vmx_set_gdt,
8139         .set_dr7 = vmx_set_dr7,
8140         .cache_reg = vmx_cache_reg,
8141         .get_rflags = vmx_get_rflags,
8142         .set_rflags = vmx_set_rflags,
8143         .fpu_activate = vmx_fpu_activate,
8144         .fpu_deactivate = vmx_fpu_deactivate,
8145
8146         .tlb_flush = vmx_flush_tlb,
8147
8148         .run = vmx_vcpu_run,
8149         .handle_exit = vmx_handle_exit,
8150         .skip_emulated_instruction = skip_emulated_instruction,
8151         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8152         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8153         .patch_hypercall = vmx_patch_hypercall,
8154         .set_irq = vmx_inject_irq,
8155         .set_nmi = vmx_inject_nmi,
8156         .queue_exception = vmx_queue_exception,
8157         .cancel_injection = vmx_cancel_injection,
8158         .interrupt_allowed = vmx_interrupt_allowed,
8159         .nmi_allowed = vmx_nmi_allowed,
8160         .get_nmi_mask = vmx_get_nmi_mask,
8161         .set_nmi_mask = vmx_set_nmi_mask,
8162         .enable_nmi_window = enable_nmi_window,
8163         .enable_irq_window = enable_irq_window,
8164         .update_cr8_intercept = update_cr8_intercept,
8165         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8166         .vm_has_apicv = vmx_vm_has_apicv,
8167         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8168         .hwapic_irr_update = vmx_hwapic_irr_update,
8169         .hwapic_isr_update = vmx_hwapic_isr_update,
8170         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8171         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8172
8173         .set_tss_addr = vmx_set_tss_addr,
8174         .get_tdp_level = get_ept_level,
8175         .get_mt_mask = vmx_get_mt_mask,
8176
8177         .get_exit_info = vmx_get_exit_info,
8178
8179         .get_lpage_level = vmx_get_lpage_level,
8180
8181         .cpuid_update = vmx_cpuid_update,
8182
8183         .rdtscp_supported = vmx_rdtscp_supported,
8184         .invpcid_supported = vmx_invpcid_supported,
8185
8186         .set_supported_cpuid = vmx_set_supported_cpuid,
8187
8188         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8189
8190         .set_tsc_khz = vmx_set_tsc_khz,
8191         .read_tsc_offset = vmx_read_tsc_offset,
8192         .write_tsc_offset = vmx_write_tsc_offset,
8193         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8194         .compute_tsc_offset = vmx_compute_tsc_offset,
8195         .read_l1_tsc = vmx_read_l1_tsc,
8196
8197         .set_tdp_cr3 = vmx_set_cr3,
8198
8199         .check_intercept = vmx_check_intercept,
8200         .handle_external_intr = vmx_handle_external_intr,
8201 };
8202
8203 static int __init vmx_init(void)
8204 {
8205         int r, i, msr;
8206
8207         rdmsrl_safe(MSR_EFER, &host_efer);
8208
8209         for (i = 0; i < NR_VMX_MSR; ++i)
8210                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8211
8212         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8213         if (!vmx_io_bitmap_a)
8214                 return -ENOMEM;
8215
8216         r = -ENOMEM;
8217
8218         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8219         if (!vmx_io_bitmap_b)
8220                 goto out;
8221
8222         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8223         if (!vmx_msr_bitmap_legacy)
8224                 goto out1;
8225
8226         vmx_msr_bitmap_legacy_x2apic =
8227                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8228         if (!vmx_msr_bitmap_legacy_x2apic)
8229                 goto out2;
8230
8231         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8232         if (!vmx_msr_bitmap_longmode)
8233                 goto out3;
8234
8235         vmx_msr_bitmap_longmode_x2apic =
8236                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8237         if (!vmx_msr_bitmap_longmode_x2apic)
8238                 goto out4;
8239         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8240         if (!vmx_vmread_bitmap)
8241                 goto out5;
8242
8243         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8244         if (!vmx_vmwrite_bitmap)
8245                 goto out6;
8246
8247         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8248         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8249         /* shadowed read/write fields */
8250         for (i = 0; i < max_shadow_read_write_fields; i++) {
8251                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8252                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8253         }
8254         /* shadowed read only fields */
8255         for (i = 0; i < max_shadow_read_only_fields; i++)
8256                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8257
8258         /*
8259          * Allow direct access to the PC debug port (it is often used for I/O
8260          * delays, but the vmexits simply slow things down).
8261          */
8262         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8263         clear_bit(0x80, vmx_io_bitmap_a);
8264
8265         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8266
8267         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8268         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8269
8270         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8271
8272         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8273                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8274         if (r)
8275                 goto out7;
8276
8277 #ifdef CONFIG_KEXEC
8278         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8279                            crash_vmclear_local_loaded_vmcss);
8280 #endif
8281
8282         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8283         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8284         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8285         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8286         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8287         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8288         memcpy(vmx_msr_bitmap_legacy_x2apic,
8289                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8290         memcpy(vmx_msr_bitmap_longmode_x2apic,
8291                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8292
8293         if (enable_apicv) {
8294                 for (msr = 0x800; msr <= 0x8ff; msr++)
8295                         vmx_disable_intercept_msr_read_x2apic(msr);
8296
8297                 /* According SDM, in x2apic mode, the whole id reg is used.
8298                  * But in KVM, it only use the highest eight bits. Need to
8299                  * intercept it */
8300                 vmx_enable_intercept_msr_read_x2apic(0x802);
8301                 /* TMCCT */
8302                 vmx_enable_intercept_msr_read_x2apic(0x839);
8303                 /* TPR */
8304                 vmx_disable_intercept_msr_write_x2apic(0x808);
8305                 /* EOI */
8306                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8307                 /* SELF-IPI */
8308                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8309         }
8310
8311         if (enable_ept) {
8312                 kvm_mmu_set_mask_ptes(0ull,
8313                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8314                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8315                         0ull, VMX_EPT_EXECUTABLE_MASK);
8316                 ept_set_mmio_spte_mask();
8317                 kvm_enable_tdp();
8318         } else
8319                 kvm_disable_tdp();
8320
8321         return 0;
8322
8323 out7:
8324         free_page((unsigned long)vmx_vmwrite_bitmap);
8325 out6:
8326         free_page((unsigned long)vmx_vmread_bitmap);
8327 out5:
8328         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8329 out4:
8330         free_page((unsigned long)vmx_msr_bitmap_longmode);
8331 out3:
8332         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8333 out2:
8334         free_page((unsigned long)vmx_msr_bitmap_legacy);
8335 out1:
8336         free_page((unsigned long)vmx_io_bitmap_b);
8337 out:
8338         free_page((unsigned long)vmx_io_bitmap_a);
8339         return r;
8340 }
8341
8342 static void __exit vmx_exit(void)
8343 {
8344         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8345         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8346         free_page((unsigned long)vmx_msr_bitmap_legacy);
8347         free_page((unsigned long)vmx_msr_bitmap_longmode);
8348         free_page((unsigned long)vmx_io_bitmap_b);
8349         free_page((unsigned long)vmx_io_bitmap_a);
8350         free_page((unsigned long)vmx_vmwrite_bitmap);
8351         free_page((unsigned long)vmx_vmread_bitmap);
8352
8353 #ifdef CONFIG_KEXEC
8354         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8355         synchronize_rcu();
8356 #endif
8357
8358         kvm_exit();
8359 }
8360
8361 module_init(vmx_init)
8362 module_exit(vmx_exit)