arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_mpx_supported(void);
 867 static bool vmx_xsaves_supported(void);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 876 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 877 static int alloc_identity_pagetable(struct kvm *kvm);
 878
 879 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 880 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 881 /*
 882  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 883  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 884  */
 885 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 886 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 887
 888 /*
 889  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 890  * can find which vCPU should be waken up.
 891  */
 892 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 893 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 894
 895 static unsigned long *vmx_io_bitmap_a;
 896 static unsigned long *vmx_io_bitmap_b;
 897 static unsigned long *vmx_msr_bitmap_legacy;
 898 static unsigned long *vmx_msr_bitmap_longmode;
 899 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 900 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 901 static unsigned long *vmx_msr_bitmap_nested;
 902 static unsigned long *vmx_vmread_bitmap;
 903 static unsigned long *vmx_vmwrite_bitmap;
 904
 905 static bool cpu_has_load_ia32_efer;
 906 static bool cpu_has_load_perf_global_ctrl;
 907
 908 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 909 static DEFINE_SPINLOCK(vmx_vpid_lock);
 910
 911 static struct vmcs_config {
 912         int size;
 913         int order;
 914         u32 revision_id;
 915         u32 pin_based_exec_ctrl;
 916         u32 cpu_based_exec_ctrl;
 917         u32 cpu_based_2nd_exec_ctrl;
 918         u32 vmexit_ctrl;
 919         u32 vmentry_ctrl;
 920 } vmcs_config;
 921
 922 static struct vmx_capability {
 923         u32 ept;
 924         u32 vpid;
 925 } vmx_capability;
 926
 927 #define VMX_SEGMENT_FIELD(seg)                                  \
 928         [VCPU_SREG_##seg] = {                                   \
 929                 .selector = GUEST_##seg##_SELECTOR,             \
 930                 .base = GUEST_##seg##_BASE,                     \
 931                 .limit = GUEST_##seg##_LIMIT,                   \
 932                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 933         }
 934
 935 static const struct kvm_vmx_segment_field {
 936         unsigned selector;
 937         unsigned base;
 938         unsigned limit;
 939         unsigned ar_bytes;
 940 } kvm_vmx_segment_fields[] = {
 941         VMX_SEGMENT_FIELD(CS),
 942         VMX_SEGMENT_FIELD(DS),
 943         VMX_SEGMENT_FIELD(ES),
 944         VMX_SEGMENT_FIELD(FS),
 945         VMX_SEGMENT_FIELD(GS),
 946         VMX_SEGMENT_FIELD(SS),
 947         VMX_SEGMENT_FIELD(TR),
 948         VMX_SEGMENT_FIELD(LDTR),
 949 };
 950
 951 static u64 host_efer;
 952
 953 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 954
 955 /*
 956  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 957  * away by decrementing the array size.
 958  */
 959 static const u32 vmx_msr_index[] = {
 960 #ifdef CONFIG_X86_64
 961         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 962 #endif
 963         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 964 };
 965
 966 static inline bool is_page_fault(u32 intr_info)
 967 {
 968         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 969                              INTR_INFO_VALID_MASK)) ==
 970                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 971 }
 972
 973 static inline bool is_no_device(u32 intr_info)
 974 {
 975         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 976                              INTR_INFO_VALID_MASK)) ==
 977                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 978 }
 979
 980 static inline bool is_invalid_opcode(u32 intr_info)
 981 {
 982         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 983                              INTR_INFO_VALID_MASK)) ==
 984                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 985 }
 986
 987 static inline bool is_external_interrupt(u32 intr_info)
 988 {
 989         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 990                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 991 }
 992
 993 static inline bool is_machine_check(u32 intr_info)
 994 {
 995         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 996                              INTR_INFO_VALID_MASK)) ==
 997                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 998 }
 999
1000 static inline bool cpu_has_vmx_msr_bitmap(void)
1001 {
1002         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1003 }
1004
1005 static inline bool cpu_has_vmx_tpr_shadow(void)
1006 {
1007         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1008 }
1009
1010 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1011 {
1012         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1013 }
1014
1015 static inline bool cpu_has_secondary_exec_ctrls(void)
1016 {
1017         return vmcs_config.cpu_based_exec_ctrl &
1018                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1019 }
1020
1021 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1022 {
1023         return vmcs_config.cpu_based_2nd_exec_ctrl &
1024                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1025 }
1026
1027 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1028 {
1029         return vmcs_config.cpu_based_2nd_exec_ctrl &
1030                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1031 }
1032
1033 static inline bool cpu_has_vmx_apic_register_virt(void)
1034 {
1035         return vmcs_config.cpu_based_2nd_exec_ctrl &
1036                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1037 }
1038
1039 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1040 {
1041         return vmcs_config.cpu_based_2nd_exec_ctrl &
1042                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1043 }
1044
1045 static inline bool cpu_has_vmx_posted_intr(void)
1046 {
1047         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1048                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1049 }
1050
1051 static inline bool cpu_has_vmx_apicv(void)
1052 {
1053         return cpu_has_vmx_apic_register_virt() &&
1054                 cpu_has_vmx_virtual_intr_delivery() &&
1055                 cpu_has_vmx_posted_intr();
1056 }
1057
1058 static inline bool cpu_has_vmx_flexpriority(void)
1059 {
1060         return cpu_has_vmx_tpr_shadow() &&
1061                 cpu_has_vmx_virtualize_apic_accesses();
1062 }
1063
1064 static inline bool cpu_has_vmx_ept_execute_only(void)
1065 {
1066         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1067 }
1068
1069 static inline bool cpu_has_vmx_ept_2m_page(void)
1070 {
1071         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1072 }
1073
1074 static inline bool cpu_has_vmx_ept_1g_page(void)
1075 {
1076         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1077 }
1078
1079 static inline bool cpu_has_vmx_ept_4levels(void)
1080 {
1081         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1082 }
1083
1084 static inline bool cpu_has_vmx_ept_ad_bits(void)
1085 {
1086         return vmx_capability.ept & VMX_EPT_AD_BIT;
1087 }
1088
1089 static inline bool cpu_has_vmx_invept_context(void)
1090 {
1091         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1092 }
1093
1094 static inline bool cpu_has_vmx_invept_global(void)
1095 {
1096         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1097 }
1098
1099 static inline bool cpu_has_vmx_invvpid_single(void)
1100 {
1101         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1102 }
1103
1104 static inline bool cpu_has_vmx_invvpid_global(void)
1105 {
1106         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1107 }
1108
1109 static inline bool cpu_has_vmx_ept(void)
1110 {
1111         return vmcs_config.cpu_based_2nd_exec_ctrl &
1112                 SECONDARY_EXEC_ENABLE_EPT;
1113 }
1114
1115 static inline bool cpu_has_vmx_unrestricted_guest(void)
1116 {
1117         return vmcs_config.cpu_based_2nd_exec_ctrl &
1118                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1119 }
1120
1121 static inline bool cpu_has_vmx_ple(void)
1122 {
1123         return vmcs_config.cpu_based_2nd_exec_ctrl &
1124                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1125 }
1126
1127 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1128 {
1129         return flexpriority_enabled && lapic_in_kernel(vcpu);
1130 }
1131
1132 static inline bool cpu_has_vmx_vpid(void)
1133 {
1134         return vmcs_config.cpu_based_2nd_exec_ctrl &
1135                 SECONDARY_EXEC_ENABLE_VPID;
1136 }
1137
1138 static inline bool cpu_has_vmx_rdtscp(void)
1139 {
1140         return vmcs_config.cpu_based_2nd_exec_ctrl &
1141                 SECONDARY_EXEC_RDTSCP;
1142 }
1143
1144 static inline bool cpu_has_vmx_invpcid(void)
1145 {
1146         return vmcs_config.cpu_based_2nd_exec_ctrl &
1147                 SECONDARY_EXEC_ENABLE_INVPCID;
1148 }
1149
1150 static inline bool cpu_has_virtual_nmis(void)
1151 {
1152         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1153 }
1154
1155 static inline bool cpu_has_vmx_wbinvd_exit(void)
1156 {
1157         return vmcs_config.cpu_based_2nd_exec_ctrl &
1158                 SECONDARY_EXEC_WBINVD_EXITING;
1159 }
1160
1161 static inline bool cpu_has_vmx_shadow_vmcs(void)
1162 {
1163         u64 vmx_msr;
1164         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1165         /* check if the cpu supports writing r/o exit information fields */
1166         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1167                 return false;
1168
1169         return vmcs_config.cpu_based_2nd_exec_ctrl &
1170                 SECONDARY_EXEC_SHADOW_VMCS;
1171 }
1172
1173 static inline bool cpu_has_vmx_pml(void)
1174 {
1175         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1176 }
1177
1178 static inline bool cpu_has_vmx_tsc_scaling(void)
1179 {
1180         return vmcs_config.cpu_based_2nd_exec_ctrl &
1181                 SECONDARY_EXEC_TSC_SCALING;
1182 }
1183
1184 static inline bool report_flexpriority(void)
1185 {
1186         return flexpriority_enabled;
1187 }
1188
1189 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1190 {
1191         return vmcs12->cpu_based_vm_exec_control & bit;
1192 }
1193
1194 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1195 {
1196         return (vmcs12->cpu_based_vm_exec_control &
1197                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1198                 (vmcs12->secondary_vm_exec_control & bit);
1199 }
1200
1201 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1202 {
1203         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1204 }
1205
1206 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1207 {
1208         return vmcs12->pin_based_vm_exec_control &
1209                 PIN_BASED_VMX_PREEMPTION_TIMER;
1210 }
1211
1212 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1213 {
1214         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1215 }
1216
1217 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1218 {
1219         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1220                 vmx_xsaves_supported();
1221 }
1222
1223 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1224 {
1225         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1226 }
1227
1228 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1229 {
1230         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1231 }
1232
1233 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1234 {
1235         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1236 }
1237
1238 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1239 {
1240         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1241 }
1242
1243 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1244 {
1245         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1246 }
1247
1248 static inline bool is_exception(u32 intr_info)
1249 {
1250         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1251                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1252 }
1253
1254 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1255                               u32 exit_intr_info,
1256                               unsigned long exit_qualification);
1257 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1258                         struct vmcs12 *vmcs12,
1259                         u32 reason, unsigned long qualification);
1260
1261 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1262 {
1263         int i;
1264
1265         for (i = 0; i < vmx->nmsrs; ++i)
1266                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1267                         return i;
1268         return -1;
1269 }
1270
1271 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1272 {
1273     struct {
1274         u64 vpid : 16;
1275         u64 rsvd : 48;
1276         u64 gva;
1277     } operand = { vpid, 0, gva };
1278
1279     asm volatile (__ex(ASM_VMX_INVVPID)
1280                   /* CF==1 or ZF==1 --> rc = -1 */
1281                   "; ja 1f ; ud2 ; 1:"
1282                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1283 }
1284
1285 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1286 {
1287         struct {
1288                 u64 eptp, gpa;
1289         } operand = {eptp, gpa};
1290
1291         asm volatile (__ex(ASM_VMX_INVEPT)
1292                         /* CF==1 or ZF==1 --> rc = -1 */
1293                         "; ja 1f ; ud2 ; 1:\n"
1294                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1295 }
1296
1297 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1298 {
1299         int i;
1300
1301         i = __find_msr_index(vmx, msr);
1302         if (i >= 0)
1303                 return &vmx->guest_msrs[i];
1304         return NULL;
1305 }
1306
1307 static void vmcs_clear(struct vmcs *vmcs)
1308 {
1309         u64 phys_addr = __pa(vmcs);
1310         u8 error;
1311
1312         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1313                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1314                       : "cc", "memory");
1315         if (error)
1316                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1317                        vmcs, phys_addr);
1318 }
1319
1320 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1321 {
1322         vmcs_clear(loaded_vmcs->vmcs);
1323         loaded_vmcs->cpu = -1;
1324         loaded_vmcs->launched = 0;
1325 }
1326
1327 static void vmcs_load(struct vmcs *vmcs)
1328 {
1329         u64 phys_addr = __pa(vmcs);
1330         u8 error;
1331
1332         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1333                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1334                         : "cc", "memory");
1335         if (error)
1336                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1337                        vmcs, phys_addr);
1338 }
1339
1340 #ifdef CONFIG_KEXEC_CORE
1341 /*
1342  * This bitmap is used to indicate whether the vmclear
1343  * operation is enabled on all cpus. All disabled by
1344  * default.
1345  */
1346 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1347
1348 static inline void crash_enable_local_vmclear(int cpu)
1349 {
1350         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1351 }
1352
1353 static inline void crash_disable_local_vmclear(int cpu)
1354 {
1355         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1356 }
1357
1358 static inline int crash_local_vmclear_enabled(int cpu)
1359 {
1360         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1361 }
1362
1363 static void crash_vmclear_local_loaded_vmcss(void)
1364 {
1365         int cpu = raw_smp_processor_id();
1366         struct loaded_vmcs *v;
1367
1368         if (!crash_local_vmclear_enabled(cpu))
1369                 return;
1370
1371         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1372                             loaded_vmcss_on_cpu_link)
1373                 vmcs_clear(v->vmcs);
1374 }
1375 #else
1376 static inline void crash_enable_local_vmclear(int cpu) { }
1377 static inline void crash_disable_local_vmclear(int cpu) { }
1378 #endif /* CONFIG_KEXEC_CORE */
1379
1380 static void __loaded_vmcs_clear(void *arg)
1381 {
1382         struct loaded_vmcs *loaded_vmcs = arg;
1383         int cpu = raw_smp_processor_id();
1384
1385         if (loaded_vmcs->cpu != cpu)
1386                 return; /* vcpu migration can race with cpu offline */
1387         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1388                 per_cpu(current_vmcs, cpu) = NULL;
1389         crash_disable_local_vmclear(cpu);
1390         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1391
1392         /*
1393          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1394          * is before setting loaded_vmcs->vcpu to -1 which is done in
1395          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1396          * then adds the vmcs into percpu list before it is deleted.
1397          */
1398         smp_wmb();
1399
1400         loaded_vmcs_init(loaded_vmcs);
1401         crash_enable_local_vmclear(cpu);
1402 }
1403
1404 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1405 {
1406         int cpu = loaded_vmcs->cpu;
1407
1408         if (cpu != -1)
1409                 smp_call_function_single(cpu,
1410                          __loaded_vmcs_clear, loaded_vmcs, 1);
1411 }
1412
1413 static inline void vpid_sync_vcpu_single(int vpid)
1414 {
1415         if (vpid == 0)
1416                 return;
1417
1418         if (cpu_has_vmx_invvpid_single())
1419                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1420 }
1421
1422 static inline void vpid_sync_vcpu_global(void)
1423 {
1424         if (cpu_has_vmx_invvpid_global())
1425                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1426 }
1427
1428 static inline void vpid_sync_context(int vpid)
1429 {
1430         if (cpu_has_vmx_invvpid_single())
1431                 vpid_sync_vcpu_single(vpid);
1432         else
1433                 vpid_sync_vcpu_global();
1434 }
1435
1436 static inline void ept_sync_global(void)
1437 {
1438         if (cpu_has_vmx_invept_global())
1439                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1440 }
1441
1442 static inline void ept_sync_context(u64 eptp)
1443 {
1444         if (enable_ept) {
1445                 if (cpu_has_vmx_invept_context())
1446                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1447                 else
1448                         ept_sync_global();
1449         }
1450 }
1451
1452 static __always_inline void vmcs_check16(unsigned long field)
1453 {
1454         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1455                          "16-bit accessor invalid for 64-bit field");
1456         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1457                          "16-bit accessor invalid for 64-bit high field");
1458         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1459                          "16-bit accessor invalid for 32-bit high field");
1460         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1461                          "16-bit accessor invalid for natural width field");
1462 }
1463
1464 static __always_inline void vmcs_check32(unsigned long field)
1465 {
1466         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1467                          "32-bit accessor invalid for 16-bit field");
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1469                          "32-bit accessor invalid for natural width field");
1470 }
1471
1472 static __always_inline void vmcs_check64(unsigned long field)
1473 {
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1475                          "64-bit accessor invalid for 16-bit field");
1476         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1477                          "64-bit accessor invalid for 64-bit high field");
1478         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1479                          "64-bit accessor invalid for 32-bit field");
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1481                          "64-bit accessor invalid for natural width field");
1482 }
1483
1484 static __always_inline void vmcs_checkl(unsigned long field)
1485 {
1486         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1487                          "Natural width accessor invalid for 16-bit field");
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1489                          "Natural width accessor invalid for 64-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "Natural width accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "Natural width accessor invalid for 32-bit field");
1494 }
1495
1496 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1497 {
1498         unsigned long value;
1499
1500         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1501                       : "=a"(value) : "d"(field) : "cc");
1502         return value;
1503 }
1504
1505 static __always_inline u16 vmcs_read16(unsigned long field)
1506 {
1507         vmcs_check16(field);
1508         return __vmcs_readl(field);
1509 }
1510
1511 static __always_inline u32 vmcs_read32(unsigned long field)
1512 {
1513         vmcs_check32(field);
1514         return __vmcs_readl(field);
1515 }
1516
1517 static __always_inline u64 vmcs_read64(unsigned long field)
1518 {
1519         vmcs_check64(field);
1520 #ifdef CONFIG_X86_64
1521         return __vmcs_readl(field);
1522 #else
1523         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1524 #endif
1525 }
1526
1527 static __always_inline unsigned long vmcs_readl(unsigned long field)
1528 {
1529         vmcs_checkl(field);
1530         return __vmcs_readl(field);
1531 }
1532
1533 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1534 {
1535         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1536                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1537         dump_stack();
1538 }
1539
1540 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1541 {
1542         u8 error;
1543
1544         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1545                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1546         if (unlikely(error))
1547                 vmwrite_error(field, value);
1548 }
1549
1550 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1551 {
1552         vmcs_check16(field);
1553         __vmcs_writel(field, value);
1554 }
1555
1556 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1557 {
1558         vmcs_check32(field);
1559         __vmcs_writel(field, value);
1560 }
1561
1562 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1563 {
1564         vmcs_check64(field);
1565         __vmcs_writel(field, value);
1566 #ifndef CONFIG_X86_64
1567         asm volatile ("");
1568         __vmcs_writel(field+1, value >> 32);
1569 #endif
1570 }
1571
1572 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1573 {
1574         vmcs_checkl(field);
1575         __vmcs_writel(field, value);
1576 }
1577
1578 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1579 {
1580         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1581                          "vmcs_clear_bits does not support 64-bit fields");
1582         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1583 }
1584
1585 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1586 {
1587         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1588                          "vmcs_set_bits does not support 64-bit fields");
1589         __vmcs_writel(field, __vmcs_readl(field) | mask);
1590 }
1591
1592 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1593 {
1594         vmcs_write32(VM_ENTRY_CONTROLS, val);
1595         vmx->vm_entry_controls_shadow = val;
1596 }
1597
1598 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1599 {
1600         if (vmx->vm_entry_controls_shadow != val)
1601                 vm_entry_controls_init(vmx, val);
1602 }
1603
1604 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1605 {
1606         return vmx->vm_entry_controls_shadow;
1607 }
1608
1609
1610 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1611 {
1612         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1613 }
1614
1615 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1616 {
1617         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1618 }
1619
1620 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1621 {
1622         vmcs_write32(VM_EXIT_CONTROLS, val);
1623         vmx->vm_exit_controls_shadow = val;
1624 }
1625
1626 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1627 {
1628         if (vmx->vm_exit_controls_shadow != val)
1629                 vm_exit_controls_init(vmx, val);
1630 }
1631
1632 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1633 {
1634         return vmx->vm_exit_controls_shadow;
1635 }
1636
1637
1638 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1639 {
1640         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1641 }
1642
1643 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1644 {
1645         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1646 }
1647
1648 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1649 {
1650         vmx->segment_cache.bitmask = 0;
1651 }
1652
1653 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1654                                        unsigned field)
1655 {
1656         bool ret;
1657         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1658
1659         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1660                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1661                 vmx->segment_cache.bitmask = 0;
1662         }
1663         ret = vmx->segment_cache.bitmask & mask;
1664         vmx->segment_cache.bitmask |= mask;
1665         return ret;
1666 }
1667
1668 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1669 {
1670         u16 *p = &vmx->segment_cache.seg[seg].selector;
1671
1672         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1673                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1674         return *p;
1675 }
1676
1677 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1678 {
1679         ulong *p = &vmx->segment_cache.seg[seg].base;
1680
1681         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1682                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1683         return *p;
1684 }
1685
1686 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1687 {
1688         u32 *p = &vmx->segment_cache.seg[seg].limit;
1689
1690         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1691                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1692         return *p;
1693 }
1694
1695 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1696 {
1697         u32 *p = &vmx->segment_cache.seg[seg].ar;
1698
1699         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1700                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1701         return *p;
1702 }
1703
1704 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1705 {
1706         u32 eb;
1707
1708         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1709              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1710         if ((vcpu->guest_debug &
1711              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1712             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1713                 eb |= 1u << BP_VECTOR;
1714         if (to_vmx(vcpu)->rmode.vm86_active)
1715                 eb = ~0;
1716         if (enable_ept)
1717                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1718         if (vcpu->fpu_active)
1719                 eb &= ~(1u << NM_VECTOR);
1720
1721         /* When we are running a nested L2 guest and L1 specified for it a
1722          * certain exception bitmap, we must trap the same exceptions and pass
1723          * them to L1. When running L2, we will only handle the exceptions
1724          * specified above if L1 did not want them.
1725          */
1726         if (is_guest_mode(vcpu))
1727                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1728
1729         vmcs_write32(EXCEPTION_BITMAP, eb);
1730 }
1731
1732 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1733                 unsigned long entry, unsigned long exit)
1734 {
1735         vm_entry_controls_clearbit(vmx, entry);
1736         vm_exit_controls_clearbit(vmx, exit);
1737 }
1738
1739 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1740 {
1741         unsigned i;
1742         struct msr_autoload *m = &vmx->msr_autoload;
1743
1744         switch (msr) {
1745         case MSR_EFER:
1746                 if (cpu_has_load_ia32_efer) {
1747                         clear_atomic_switch_msr_special(vmx,
1748                                         VM_ENTRY_LOAD_IA32_EFER,
1749                                         VM_EXIT_LOAD_IA32_EFER);
1750                         return;
1751                 }
1752                 break;
1753         case MSR_CORE_PERF_GLOBAL_CTRL:
1754                 if (cpu_has_load_perf_global_ctrl) {
1755                         clear_atomic_switch_msr_special(vmx,
1756                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1757                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1758                         return;
1759                 }
1760                 break;
1761         }
1762
1763         for (i = 0; i < m->nr; ++i)
1764                 if (m->guest[i].index == msr)
1765                         break;
1766
1767         if (i == m->nr)
1768                 return;
1769         --m->nr;
1770         m->guest[i] = m->guest[m->nr];
1771         m->host[i] = m->host[m->nr];
1772         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1773         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1774 }
1775
1776 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1777                 unsigned long entry, unsigned long exit,
1778                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1779                 u64 guest_val, u64 host_val)
1780 {
1781         vmcs_write64(guest_val_vmcs, guest_val);
1782         vmcs_write64(host_val_vmcs, host_val);
1783         vm_entry_controls_setbit(vmx, entry);
1784         vm_exit_controls_setbit(vmx, exit);
1785 }
1786
1787 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1788                                   u64 guest_val, u64 host_val)
1789 {
1790         unsigned i;
1791         struct msr_autoload *m = &vmx->msr_autoload;
1792
1793         switch (msr) {
1794         case MSR_EFER:
1795                 if (cpu_has_load_ia32_efer) {
1796                         add_atomic_switch_msr_special(vmx,
1797                                         VM_ENTRY_LOAD_IA32_EFER,
1798                                         VM_EXIT_LOAD_IA32_EFER,
1799                                         GUEST_IA32_EFER,
1800                                         HOST_IA32_EFER,
1801                                         guest_val, host_val);
1802                         return;
1803                 }
1804                 break;
1805         case MSR_CORE_PERF_GLOBAL_CTRL:
1806                 if (cpu_has_load_perf_global_ctrl) {
1807                         add_atomic_switch_msr_special(vmx,
1808                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1809                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1810                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1811                                         HOST_IA32_PERF_GLOBAL_CTRL,
1812                                         guest_val, host_val);
1813                         return;
1814                 }
1815                 break;
1816         }
1817
1818         for (i = 0; i < m->nr; ++i)
1819                 if (m->guest[i].index == msr)
1820                         break;
1821
1822         if (i == NR_AUTOLOAD_MSRS) {
1823                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1824                                 "Can't add msr %x\n", msr);
1825                 return;
1826         } else if (i == m->nr) {
1827                 ++m->nr;
1828                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1829                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1830         }
1831
1832         m->guest[i].index = msr;
1833         m->guest[i].value = guest_val;
1834         m->host[i].index = msr;
1835         m->host[i].value = host_val;
1836 }
1837
1838 static void reload_tss(void)
1839 {
1840         /*
1841          * VT restores TR but not its size.  Useless.
1842          */
1843         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1844         struct desc_struct *descs;
1845
1846         descs = (void *)gdt->address;
1847         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1848         load_TR_desc();
1849 }
1850
1851 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1852 {
1853         u64 guest_efer;
1854         u64 ignore_bits;
1855
1856         guest_efer = vmx->vcpu.arch.efer;
1857
1858         /*
1859          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1860          * outside long mode
1861          */
1862         ignore_bits = EFER_NX | EFER_SCE;
1863 #ifdef CONFIG_X86_64
1864         ignore_bits |= EFER_LMA | EFER_LME;
1865         /* SCE is meaningful only in long mode on Intel */
1866         if (guest_efer & EFER_LMA)
1867                 ignore_bits &= ~(u64)EFER_SCE;
1868 #endif
1869         guest_efer &= ~ignore_bits;
1870         guest_efer |= host_efer & ignore_bits;
1871         vmx->guest_msrs[efer_offset].data = guest_efer;
1872         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1873
1874         clear_atomic_switch_msr(vmx, MSR_EFER);
1875
1876         /*
1877          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1878          * On CPUs that support "load IA32_EFER", always switch EFER
1879          * atomically, since it's faster than switching it manually.
1880          */
1881         if (cpu_has_load_ia32_efer ||
1882             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1883                 guest_efer = vmx->vcpu.arch.efer;
1884                 if (!(guest_efer & EFER_LMA))
1885                         guest_efer &= ~EFER_LME;
1886                 if (guest_efer != host_efer)
1887                         add_atomic_switch_msr(vmx, MSR_EFER,
1888                                               guest_efer, host_efer);
1889                 return false;
1890         }
1891
1892         return true;
1893 }
1894
1895 static unsigned long segment_base(u16 selector)
1896 {
1897         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1898         struct desc_struct *d;
1899         unsigned long table_base;
1900         unsigned long v;
1901
1902         if (!(selector & ~3))
1903                 return 0;
1904
1905         table_base = gdt->address;
1906
1907         if (selector & 4) {           /* from ldt */
1908                 u16 ldt_selector = kvm_read_ldt();
1909
1910                 if (!(ldt_selector & ~3))
1911                         return 0;
1912
1913                 table_base = segment_base(ldt_selector);
1914         }
1915         d = (struct desc_struct *)(table_base + (selector & ~7));
1916         v = get_desc_base(d);
1917 #ifdef CONFIG_X86_64
1918        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1919                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1920 #endif
1921         return v;
1922 }
1923
1924 static inline unsigned long kvm_read_tr_base(void)
1925 {
1926         u16 tr;
1927         asm("str %0" : "=g"(tr));
1928         return segment_base(tr);
1929 }
1930
1931 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1932 {
1933         struct vcpu_vmx *vmx = to_vmx(vcpu);
1934         int i;
1935
1936         if (vmx->host_state.loaded)
1937                 return;
1938
1939         vmx->host_state.loaded = 1;
1940         /*
1941          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1942          * allow segment selectors with cpl > 0 or ti == 1.
1943          */
1944         vmx->host_state.ldt_sel = kvm_read_ldt();
1945         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1946         savesegment(fs, vmx->host_state.fs_sel);
1947         if (!(vmx->host_state.fs_sel & 7)) {
1948                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1949                 vmx->host_state.fs_reload_needed = 0;
1950         } else {
1951                 vmcs_write16(HOST_FS_SELECTOR, 0);
1952                 vmx->host_state.fs_reload_needed = 1;
1953         }
1954         savesegment(gs, vmx->host_state.gs_sel);
1955         if (!(vmx->host_state.gs_sel & 7))
1956                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1957         else {
1958                 vmcs_write16(HOST_GS_SELECTOR, 0);
1959                 vmx->host_state.gs_ldt_reload_needed = 1;
1960         }
1961
1962 #ifdef CONFIG_X86_64
1963         savesegment(ds, vmx->host_state.ds_sel);
1964         savesegment(es, vmx->host_state.es_sel);
1965 #endif
1966
1967 #ifdef CONFIG_X86_64
1968         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1969         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1970 #else
1971         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1972         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1973 #endif
1974
1975 #ifdef CONFIG_X86_64
1976         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1977         if (is_long_mode(&vmx->vcpu))
1978                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1979 #endif
1980         if (boot_cpu_has(X86_FEATURE_MPX))
1981                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1982         for (i = 0; i < vmx->save_nmsrs; ++i)
1983                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1984                                    vmx->guest_msrs[i].data,
1985                                    vmx->guest_msrs[i].mask);
1986 }
1987
1988 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1989 {
1990         if (!vmx->host_state.loaded)
1991                 return;
1992
1993         ++vmx->vcpu.stat.host_state_reload;
1994         vmx->host_state.loaded = 0;
1995 #ifdef CONFIG_X86_64
1996         if (is_long_mode(&vmx->vcpu))
1997                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1998 #endif
1999         if (vmx->host_state.gs_ldt_reload_needed) {
2000                 kvm_load_ldt(vmx->host_state.ldt_sel);
2001 #ifdef CONFIG_X86_64
2002                 load_gs_index(vmx->host_state.gs_sel);
2003 #else
2004                 loadsegment(gs, vmx->host_state.gs_sel);
2005 #endif
2006         }
2007         if (vmx->host_state.fs_reload_needed)
2008                 loadsegment(fs, vmx->host_state.fs_sel);
2009 #ifdef CONFIG_X86_64
2010         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2011                 loadsegment(ds, vmx->host_state.ds_sel);
2012                 loadsegment(es, vmx->host_state.es_sel);
2013         }
2014 #endif
2015         reload_tss();
2016 #ifdef CONFIG_X86_64
2017         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2018 #endif
2019         if (vmx->host_state.msr_host_bndcfgs)
2020                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2021         /*
2022          * If the FPU is not active (through the host task or
2023          * the guest vcpu), then restore the cr0.TS bit.
2024          */
2025         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2026                 stts();
2027         load_gdt(this_cpu_ptr(&host_gdt));
2028 }
2029
2030 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2031 {
2032         preempt_disable();
2033         __vmx_load_host_state(vmx);
2034         preempt_enable();
2035 }
2036
2037 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2038 {
2039         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2040         struct pi_desc old, new;
2041         unsigned int dest;
2042
2043         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2044                 !irq_remapping_cap(IRQ_POSTING_CAP))
2045                 return;
2046
2047         do {
2048                 old.control = new.control = pi_desc->control;
2049
2050                 /*
2051                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2052                  * are two possible cases:
2053                  * 1. After running 'pre_block', context switch
2054                  *    happened. For this case, 'sn' was set in
2055                  *    vmx_vcpu_put(), so we need to clear it here.
2056                  * 2. After running 'pre_block', we were blocked,
2057                  *    and woken up by some other guy. For this case,
2058                  *    we don't need to do anything, 'pi_post_block'
2059                  *    will do everything for us. However, we cannot
2060                  *    check whether it is case #1 or case #2 here
2061                  *    (maybe, not needed), so we also clear sn here,
2062                  *    I think it is not a big deal.
2063                  */
2064                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2065                         if (vcpu->cpu != cpu) {
2066                                 dest = cpu_physical_id(cpu);
2067
2068                                 if (x2apic_enabled())
2069                                         new.ndst = dest;
2070                                 else
2071                                         new.ndst = (dest << 8) & 0xFF00;
2072                         }
2073
2074                         /* set 'NV' to 'notification vector' */
2075                         new.nv = POSTED_INTR_VECTOR;
2076                 }
2077
2078                 /* Allow posting non-urgent interrupts */
2079                 new.sn = 0;
2080         } while (cmpxchg(&pi_desc->control, old.control,
2081                         new.control) != old.control);
2082 }
2083 /*
2084  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2085  * vcpu mutex is already taken.
2086  */
2087 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2088 {
2089         struct vcpu_vmx *vmx = to_vmx(vcpu);
2090         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2091
2092         if (!vmm_exclusive)
2093                 kvm_cpu_vmxon(phys_addr);
2094         else if (vmx->loaded_vmcs->cpu != cpu)
2095                 loaded_vmcs_clear(vmx->loaded_vmcs);
2096
2097         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2098                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2099                 vmcs_load(vmx->loaded_vmcs->vmcs);
2100         }
2101
2102         if (vmx->loaded_vmcs->cpu != cpu) {
2103                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2104                 unsigned long sysenter_esp;
2105
2106                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2107                 local_irq_disable();
2108                 crash_disable_local_vmclear(cpu);
2109
2110                 /*
2111                  * Read loaded_vmcs->cpu should be before fetching
2112                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2113                  * See the comments in __loaded_vmcs_clear().
2114                  */
2115                 smp_rmb();
2116
2117                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2118                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2119                 crash_enable_local_vmclear(cpu);
2120                 local_irq_enable();
2121
2122                 /*
2123                  * Linux uses per-cpu TSS and GDT, so set these when switching
2124                  * processors.
2125                  */
2126                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2127                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2128
2129                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2130                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2131
2132                 vmx->loaded_vmcs->cpu = cpu;
2133         }
2134
2135         /* Setup TSC multiplier */
2136         if (kvm_has_tsc_control &&
2137             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2138                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2139                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2140         }
2141
2142         vmx_vcpu_pi_load(vcpu, cpu);
2143 }
2144
2145 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2146 {
2147         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2148
2149         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2150                 !irq_remapping_cap(IRQ_POSTING_CAP))
2151                 return;
2152
2153         /* Set SN when the vCPU is preempted */
2154         if (vcpu->preempted)
2155                 pi_set_sn(pi_desc);
2156 }
2157
2158 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2159 {
2160         vmx_vcpu_pi_put(vcpu);
2161
2162         __vmx_load_host_state(to_vmx(vcpu));
2163         if (!vmm_exclusive) {
2164                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2165                 vcpu->cpu = -1;
2166                 kvm_cpu_vmxoff();
2167         }
2168 }
2169
2170 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2171 {
2172         ulong cr0;
2173
2174         if (vcpu->fpu_active)
2175                 return;
2176         vcpu->fpu_active = 1;
2177         cr0 = vmcs_readl(GUEST_CR0);
2178         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2179         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2180         vmcs_writel(GUEST_CR0, cr0);
2181         update_exception_bitmap(vcpu);
2182         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2183         if (is_guest_mode(vcpu))
2184                 vcpu->arch.cr0_guest_owned_bits &=
2185                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2186         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2187 }
2188
2189 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2190
2191 /*
2192  * Return the cr0 value that a nested guest would read. This is a combination
2193  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2194  * its hypervisor (cr0_read_shadow).
2195  */
2196 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2197 {
2198         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2199                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2200 }
2201 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2202 {
2203         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2204                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2205 }
2206
2207 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2208 {
2209         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2210          * set this *before* calling this function.
2211          */
2212         vmx_decache_cr0_guest_bits(vcpu);
2213         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2214         update_exception_bitmap(vcpu);
2215         vcpu->arch.cr0_guest_owned_bits = 0;
2216         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2217         if (is_guest_mode(vcpu)) {
2218                 /*
2219                  * L1's specified read shadow might not contain the TS bit,
2220                  * so now that we turned on shadowing of this bit, we need to
2221                  * set this bit of the shadow. Like in nested_vmx_run we need
2222                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2223                  * up-to-date here because we just decached cr0.TS (and we'll
2224                  * only update vmcs12->guest_cr0 on nested exit).
2225                  */
2226                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2227                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2228                         (vcpu->arch.cr0 & X86_CR0_TS);
2229                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2230         } else
2231                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2232 }
2233
2234 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2235 {
2236         unsigned long rflags, save_rflags;
2237
2238         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2239                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2240                 rflags = vmcs_readl(GUEST_RFLAGS);
2241                 if (to_vmx(vcpu)->rmode.vm86_active) {
2242                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2243                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2244                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2245                 }
2246                 to_vmx(vcpu)->rflags = rflags;
2247         }
2248         return to_vmx(vcpu)->rflags;
2249 }
2250
2251 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2252 {
2253         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2254         to_vmx(vcpu)->rflags = rflags;
2255         if (to_vmx(vcpu)->rmode.vm86_active) {
2256                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2257                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2258         }
2259         vmcs_writel(GUEST_RFLAGS, rflags);
2260 }
2261
2262 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2263 {
2264         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2265         int ret = 0;
2266
2267         if (interruptibility & GUEST_INTR_STATE_STI)
2268                 ret |= KVM_X86_SHADOW_INT_STI;
2269         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2270                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2271
2272         return ret;
2273 }
2274
2275 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2276 {
2277         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2278         u32 interruptibility = interruptibility_old;
2279
2280         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2281
2282         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2283                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2284         else if (mask & KVM_X86_SHADOW_INT_STI)
2285                 interruptibility |= GUEST_INTR_STATE_STI;
2286
2287         if ((interruptibility != interruptibility_old))
2288                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2289 }
2290
2291 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2292 {
2293         unsigned long rip;
2294
2295         rip = kvm_rip_read(vcpu);
2296         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2297         kvm_rip_write(vcpu, rip);
2298
2299         /* skipping an emulated instruction also counts */
2300         vmx_set_interrupt_shadow(vcpu, 0);
2301 }
2302
2303 /*
2304  * KVM wants to inject page-faults which it got to the guest. This function
2305  * checks whether in a nested guest, we need to inject them to L1 or L2.
2306  */
2307 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2308 {
2309         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2310
2311         if (!(vmcs12->exception_bitmap & (1u << nr)))
2312                 return 0;
2313
2314         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2315                           vmcs_read32(VM_EXIT_INTR_INFO),
2316                           vmcs_readl(EXIT_QUALIFICATION));
2317         return 1;
2318 }
2319
2320 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2321                                 bool has_error_code, u32 error_code,
2322                                 bool reinject)
2323 {
2324         struct vcpu_vmx *vmx = to_vmx(vcpu);
2325         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2326
2327         if (!reinject && is_guest_mode(vcpu) &&
2328             nested_vmx_check_exception(vcpu, nr))
2329                 return;
2330
2331         if (has_error_code) {
2332                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2333                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2334         }
2335
2336         if (vmx->rmode.vm86_active) {
2337                 int inc_eip = 0;
2338                 if (kvm_exception_is_soft(nr))
2339                         inc_eip = vcpu->arch.event_exit_inst_len;
2340                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2341                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2342                 return;
2343         }
2344
2345         if (kvm_exception_is_soft(nr)) {
2346                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2347                              vmx->vcpu.arch.event_exit_inst_len);
2348                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2349         } else
2350                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2351
2352         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2353 }
2354
2355 static bool vmx_rdtscp_supported(void)
2356 {
2357         return cpu_has_vmx_rdtscp();
2358 }
2359
2360 static bool vmx_invpcid_supported(void)
2361 {
2362         return cpu_has_vmx_invpcid() && enable_ept;
2363 }
2364
2365 /*
2366  * Swap MSR entry in host/guest MSR entry array.
2367  */
2368 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2369 {
2370         struct shared_msr_entry tmp;
2371
2372         tmp = vmx->guest_msrs[to];
2373         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2374         vmx->guest_msrs[from] = tmp;
2375 }
2376
2377 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2378 {
2379         unsigned long *msr_bitmap;
2380
2381         if (is_guest_mode(vcpu))
2382                 msr_bitmap = vmx_msr_bitmap_nested;
2383         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2384                 if (is_long_mode(vcpu))
2385                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2386                 else
2387                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2388         } else {
2389                 if (is_long_mode(vcpu))
2390                         msr_bitmap = vmx_msr_bitmap_longmode;
2391                 else
2392                         msr_bitmap = vmx_msr_bitmap_legacy;
2393         }
2394
2395         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2396 }
2397
2398 /*
2399  * Set up the vmcs to automatically save and restore system
2400  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2401  * mode, as fiddling with msrs is very expensive.
2402  */
2403 static void setup_msrs(struct vcpu_vmx *vmx)
2404 {
2405         int save_nmsrs, index;
2406
2407         save_nmsrs = 0;
2408 #ifdef CONFIG_X86_64
2409         if (is_long_mode(&vmx->vcpu)) {
2410                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2411                 if (index >= 0)
2412                         move_msr_up(vmx, index, save_nmsrs++);
2413                 index = __find_msr_index(vmx, MSR_LSTAR);
2414                 if (index >= 0)
2415                         move_msr_up(vmx, index, save_nmsrs++);
2416                 index = __find_msr_index(vmx, MSR_CSTAR);
2417                 if (index >= 0)
2418                         move_msr_up(vmx, index, save_nmsrs++);
2419                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2420                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2421                         move_msr_up(vmx, index, save_nmsrs++);
2422                 /*
2423                  * MSR_STAR is only needed on long mode guests, and only
2424                  * if efer.sce is enabled.
2425                  */
2426                 index = __find_msr_index(vmx, MSR_STAR);
2427                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2428                         move_msr_up(vmx, index, save_nmsrs++);
2429         }
2430 #endif
2431         index = __find_msr_index(vmx, MSR_EFER);
2432         if (index >= 0 && update_transition_efer(vmx, index))
2433                 move_msr_up(vmx, index, save_nmsrs++);
2434
2435         vmx->save_nmsrs = save_nmsrs;
2436
2437         if (cpu_has_vmx_msr_bitmap())
2438                 vmx_set_msr_bitmap(&vmx->vcpu);
2439 }
2440
2441 /*
2442  * reads and returns guest's timestamp counter "register"
2443  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2444  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2445  */
2446 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2447 {
2448         u64 host_tsc, tsc_offset;
2449
2450         host_tsc = rdtsc();
2451         tsc_offset = vmcs_read64(TSC_OFFSET);
2452         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2453 }
2454
2455 /*
2456  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2457  * counter, even if a nested guest (L2) is currently running.
2458  */
2459 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2460 {
2461         u64 tsc_offset;
2462
2463         tsc_offset = is_guest_mode(vcpu) ?
2464                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2465                 vmcs_read64(TSC_OFFSET);
2466         return host_tsc + tsc_offset;
2467 }
2468
2469 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2470 {
2471         return vmcs_read64(TSC_OFFSET);
2472 }
2473
2474 /*
2475  * writes 'offset' into guest's timestamp counter offset register
2476  */
2477 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2478 {
2479         if (is_guest_mode(vcpu)) {
2480                 /*
2481                  * We're here if L1 chose not to trap WRMSR to TSC. According
2482                  * to the spec, this should set L1's TSC; The offset that L1
2483                  * set for L2 remains unchanged, and still needs to be added
2484                  * to the newly set TSC to get L2's TSC.
2485                  */
2486                 struct vmcs12 *vmcs12;
2487                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2488                 /* recalculate vmcs02.TSC_OFFSET: */
2489                 vmcs12 = get_vmcs12(vcpu);
2490                 vmcs_write64(TSC_OFFSET, offset +
2491                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2492                          vmcs12->tsc_offset : 0));
2493         } else {
2494                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2495                                            vmcs_read64(TSC_OFFSET), offset);
2496                 vmcs_write64(TSC_OFFSET, offset);
2497         }
2498 }
2499
2500 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2501 {
2502         u64 offset = vmcs_read64(TSC_OFFSET);
2503
2504         vmcs_write64(TSC_OFFSET, offset + adjustment);
2505         if (is_guest_mode(vcpu)) {
2506                 /* Even when running L2, the adjustment needs to apply to L1 */
2507                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2508         } else
2509                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2510                                            offset + adjustment);
2511 }
2512
2513 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2514 {
2515         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2516         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2517 }
2518
2519 /*
2520  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2521  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2522  * all guests if the "nested" module option is off, and can also be disabled
2523  * for a single guest by disabling its VMX cpuid bit.
2524  */
2525 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2526 {
2527         return nested && guest_cpuid_has_vmx(vcpu);
2528 }
2529
2530 /*
2531  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2532  * returned for the various VMX controls MSRs when nested VMX is enabled.
2533  * The same values should also be used to verify that vmcs12 control fields are
2534  * valid during nested entry from L1 to L2.
2535  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2536  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2537  * bit in the high half is on if the corresponding bit in the control field
2538  * may be on. See also vmx_control_verify().
2539  */
2540 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2541 {
2542         /*
2543          * Note that as a general rule, the high half of the MSRs (bits in
2544          * the control fields which may be 1) should be initialized by the
2545          * intersection of the underlying hardware's MSR (i.e., features which
2546          * can be supported) and the list of features we want to expose -
2547          * because they are known to be properly supported in our code.
2548          * Also, usually, the low half of the MSRs (bits which must be 1) can
2549          * be set to 0, meaning that L1 may turn off any of these bits. The
2550          * reason is that if one of these bits is necessary, it will appear
2551          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2552          * fields of vmcs01 and vmcs02, will turn these bits off - and
2553          * nested_vmx_exit_handled() will not pass related exits to L1.
2554          * These rules have exceptions below.
2555          */
2556
2557         /* pin-based controls */
2558         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2559                 vmx->nested.nested_vmx_pinbased_ctls_low,
2560                 vmx->nested.nested_vmx_pinbased_ctls_high);
2561         vmx->nested.nested_vmx_pinbased_ctls_low |=
2562                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2563         vmx->nested.nested_vmx_pinbased_ctls_high &=
2564                 PIN_BASED_EXT_INTR_MASK |
2565                 PIN_BASED_NMI_EXITING |
2566                 PIN_BASED_VIRTUAL_NMIS;
2567         vmx->nested.nested_vmx_pinbased_ctls_high |=
2568                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2569                 PIN_BASED_VMX_PREEMPTION_TIMER;
2570         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2571                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2572                         PIN_BASED_POSTED_INTR;
2573
2574         /* exit controls */
2575         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2576                 vmx->nested.nested_vmx_exit_ctls_low,
2577                 vmx->nested.nested_vmx_exit_ctls_high);
2578         vmx->nested.nested_vmx_exit_ctls_low =
2579                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2580
2581         vmx->nested.nested_vmx_exit_ctls_high &=
2582 #ifdef CONFIG_X86_64
2583                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2584 #endif
2585                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2586         vmx->nested.nested_vmx_exit_ctls_high |=
2587                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2588                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2589                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2590
2591         if (vmx_mpx_supported())
2592                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2593
2594         /* We support free control of debug control saving. */
2595         vmx->nested.nested_vmx_true_exit_ctls_low =
2596                 vmx->nested.nested_vmx_exit_ctls_low &
2597                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2598
2599         /* entry controls */
2600         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2601                 vmx->nested.nested_vmx_entry_ctls_low,
2602                 vmx->nested.nested_vmx_entry_ctls_high);
2603         vmx->nested.nested_vmx_entry_ctls_low =
2604                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2605         vmx->nested.nested_vmx_entry_ctls_high &=
2606 #ifdef CONFIG_X86_64
2607                 VM_ENTRY_IA32E_MODE |
2608 #endif
2609                 VM_ENTRY_LOAD_IA32_PAT;
2610         vmx->nested.nested_vmx_entry_ctls_high |=
2611                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2612         if (vmx_mpx_supported())
2613                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2614
2615         /* We support free control of debug control loading. */
2616         vmx->nested.nested_vmx_true_entry_ctls_low =
2617                 vmx->nested.nested_vmx_entry_ctls_low &
2618                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2619
2620         /* cpu-based controls */
2621         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2622                 vmx->nested.nested_vmx_procbased_ctls_low,
2623                 vmx->nested.nested_vmx_procbased_ctls_high);
2624         vmx->nested.nested_vmx_procbased_ctls_low =
2625                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2626         vmx->nested.nested_vmx_procbased_ctls_high &=
2627                 CPU_BASED_VIRTUAL_INTR_PENDING |
2628                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2629                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2630                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2631                 CPU_BASED_CR3_STORE_EXITING |
2632 #ifdef CONFIG_X86_64
2633                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2634 #endif
2635                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2636                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2637                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2638                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2639                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2640         /*
2641          * We can allow some features even when not supported by the
2642          * hardware. For example, L1 can specify an MSR bitmap - and we
2643          * can use it to avoid exits to L1 - even when L0 runs L2
2644          * without MSR bitmaps.
2645          */
2646         vmx->nested.nested_vmx_procbased_ctls_high |=
2647                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2648                 CPU_BASED_USE_MSR_BITMAPS;
2649
2650         /* We support free control of CR3 access interception. */
2651         vmx->nested.nested_vmx_true_procbased_ctls_low =
2652                 vmx->nested.nested_vmx_procbased_ctls_low &
2653                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2654
2655         /* secondary cpu-based controls */
2656         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2657                 vmx->nested.nested_vmx_secondary_ctls_low,
2658                 vmx->nested.nested_vmx_secondary_ctls_high);
2659         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2660         vmx->nested.nested_vmx_secondary_ctls_high &=
2661                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2662                 SECONDARY_EXEC_RDTSCP |
2663                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2664                 SECONDARY_EXEC_ENABLE_VPID |
2665                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2666                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2667                 SECONDARY_EXEC_WBINVD_EXITING |
2668                 SECONDARY_EXEC_XSAVES |
2669                 SECONDARY_EXEC_PCOMMIT;
2670
2671         if (enable_ept) {
2672                 /* nested EPT: emulate EPT also to L1 */
2673                 vmx->nested.nested_vmx_secondary_ctls_high |=
2674                         SECONDARY_EXEC_ENABLE_EPT;
2675                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2676                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2677                          VMX_EPT_INVEPT_BIT;
2678                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2679                 /*
2680                  * For nested guests, we don't do anything specific
2681                  * for single context invalidation. Hence, only advertise
2682                  * support for global context invalidation.
2683                  */
2684                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2685         } else
2686                 vmx->nested.nested_vmx_ept_caps = 0;
2687
2688         if (enable_vpid)
2689                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2690                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2691         else
2692                 vmx->nested.nested_vmx_vpid_caps = 0;
2693
2694         if (enable_unrestricted_guest)
2695                 vmx->nested.nested_vmx_secondary_ctls_high |=
2696                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2697
2698         /* miscellaneous data */
2699         rdmsr(MSR_IA32_VMX_MISC,
2700                 vmx->nested.nested_vmx_misc_low,
2701                 vmx->nested.nested_vmx_misc_high);
2702         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2703         vmx->nested.nested_vmx_misc_low |=
2704                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2705                 VMX_MISC_ACTIVITY_HLT;
2706         vmx->nested.nested_vmx_misc_high = 0;
2707 }
2708
2709 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2710 {
2711         /*
2712          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2713          */
2714         return ((control & high) | low) == control;
2715 }
2716
2717 static inline u64 vmx_control_msr(u32 low, u32 high)
2718 {
2719         return low | ((u64)high << 32);
2720 }
2721
2722 /* Returns 0 on success, non-0 otherwise. */
2723 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2724 {
2725         struct vcpu_vmx *vmx = to_vmx(vcpu);
2726
2727         switch (msr_index) {
2728         case MSR_IA32_VMX_BASIC:
2729                 /*
2730                  * This MSR reports some information about VMX support. We
2731                  * should return information about the VMX we emulate for the
2732                  * guest, and the VMCS structure we give it - not about the
2733                  * VMX support of the underlying hardware.
2734                  */
2735                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2736                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2737                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2738                 break;
2739         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2740         case MSR_IA32_VMX_PINBASED_CTLS:
2741                 *pdata = vmx_control_msr(
2742                         vmx->nested.nested_vmx_pinbased_ctls_low,
2743                         vmx->nested.nested_vmx_pinbased_ctls_high);
2744                 break;
2745         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2746                 *pdata = vmx_control_msr(
2747                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2748                         vmx->nested.nested_vmx_procbased_ctls_high);
2749                 break;
2750         case MSR_IA32_VMX_PROCBASED_CTLS:
2751                 *pdata = vmx_control_msr(
2752                         vmx->nested.nested_vmx_procbased_ctls_low,
2753                         vmx->nested.nested_vmx_procbased_ctls_high);
2754                 break;
2755         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2756                 *pdata = vmx_control_msr(
2757                         vmx->nested.nested_vmx_true_exit_ctls_low,
2758                         vmx->nested.nested_vmx_exit_ctls_high);
2759                 break;
2760         case MSR_IA32_VMX_EXIT_CTLS:
2761                 *pdata = vmx_control_msr(
2762                         vmx->nested.nested_vmx_exit_ctls_low,
2763                         vmx->nested.nested_vmx_exit_ctls_high);
2764                 break;
2765         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2766                 *pdata = vmx_control_msr(
2767                         vmx->nested.nested_vmx_true_entry_ctls_low,
2768                         vmx->nested.nested_vmx_entry_ctls_high);
2769                 break;
2770         case MSR_IA32_VMX_ENTRY_CTLS:
2771                 *pdata = vmx_control_msr(
2772                         vmx->nested.nested_vmx_entry_ctls_low,
2773                         vmx->nested.nested_vmx_entry_ctls_high);
2774                 break;
2775         case MSR_IA32_VMX_MISC:
2776                 *pdata = vmx_control_msr(
2777                         vmx->nested.nested_vmx_misc_low,
2778                         vmx->nested.nested_vmx_misc_high);
2779                 break;
2780         /*
2781          * These MSRs specify bits which the guest must keep fixed (on or off)
2782          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2783          * We picked the standard core2 setting.
2784          */
2785 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2786 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2787         case MSR_IA32_VMX_CR0_FIXED0:
2788                 *pdata = VMXON_CR0_ALWAYSON;
2789                 break;
2790         case MSR_IA32_VMX_CR0_FIXED1:
2791                 *pdata = -1ULL;
2792                 break;
2793         case MSR_IA32_VMX_CR4_FIXED0:
2794                 *pdata = VMXON_CR4_ALWAYSON;
2795                 break;
2796         case MSR_IA32_VMX_CR4_FIXED1:
2797                 *pdata = -1ULL;
2798                 break;
2799         case MSR_IA32_VMX_VMCS_ENUM:
2800                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2801                 break;
2802         case MSR_IA32_VMX_PROCBASED_CTLS2:
2803                 *pdata = vmx_control_msr(
2804                         vmx->nested.nested_vmx_secondary_ctls_low,
2805                         vmx->nested.nested_vmx_secondary_ctls_high);
2806                 break;
2807         case MSR_IA32_VMX_EPT_VPID_CAP:
2808                 /* Currently, no nested vpid support */
2809                 *pdata = vmx->nested.nested_vmx_ept_caps |
2810                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2811                 break;
2812         default:
2813                 return 1;
2814         }
2815
2816         return 0;
2817 }
2818
2819 /*
2820  * Reads an msr value (of 'msr_index') into 'pdata'.
2821  * Returns 0 on success, non-0 otherwise.
2822  * Assumes vcpu_load() was already called.
2823  */
2824 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2825 {
2826         struct shared_msr_entry *msr;
2827
2828         switch (msr_info->index) {
2829 #ifdef CONFIG_X86_64
2830         case MSR_FS_BASE:
2831                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2832                 break;
2833         case MSR_GS_BASE:
2834                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2835                 break;
2836         case MSR_KERNEL_GS_BASE:
2837                 vmx_load_host_state(to_vmx(vcpu));
2838                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2839                 break;
2840 #endif
2841         case MSR_EFER:
2842                 return kvm_get_msr_common(vcpu, msr_info);
2843         case MSR_IA32_TSC:
2844                 msr_info->data = guest_read_tsc(vcpu);
2845                 break;
2846         case MSR_IA32_SYSENTER_CS:
2847                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2848                 break;
2849         case MSR_IA32_SYSENTER_EIP:
2850                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2851                 break;
2852         case MSR_IA32_SYSENTER_ESP:
2853                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2854                 break;
2855         case MSR_IA32_BNDCFGS:
2856                 if (!vmx_mpx_supported())
2857                         return 1;
2858                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2859                 break;
2860         case MSR_IA32_FEATURE_CONTROL:
2861                 if (!nested_vmx_allowed(vcpu))
2862                         return 1;
2863                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2864                 break;
2865         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2866                 if (!nested_vmx_allowed(vcpu))
2867                         return 1;
2868                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2869         case MSR_IA32_XSS:
2870                 if (!vmx_xsaves_supported())
2871                         return 1;
2872                 msr_info->data = vcpu->arch.ia32_xss;
2873                 break;
2874         case MSR_TSC_AUX:
2875                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2876                         return 1;
2877                 /* Otherwise falls through */
2878         default:
2879                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2880                 if (msr) {
2881                         msr_info->data = msr->data;
2882                         break;
2883                 }
2884                 return kvm_get_msr_common(vcpu, msr_info);
2885         }
2886
2887         return 0;
2888 }
2889
2890 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2891
2892 /*
2893  * Writes msr value into into the appropriate "register".
2894  * Returns 0 on success, non-0 otherwise.
2895  * Assumes vcpu_load() was already called.
2896  */
2897 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2898 {
2899         struct vcpu_vmx *vmx = to_vmx(vcpu);
2900         struct shared_msr_entry *msr;
2901         int ret = 0;
2902         u32 msr_index = msr_info->index;
2903         u64 data = msr_info->data;
2904
2905         switch (msr_index) {
2906         case MSR_EFER:
2907                 ret = kvm_set_msr_common(vcpu, msr_info);
2908                 break;
2909 #ifdef CONFIG_X86_64
2910         case MSR_FS_BASE:
2911                 vmx_segment_cache_clear(vmx);
2912                 vmcs_writel(GUEST_FS_BASE, data);
2913                 break;
2914         case MSR_GS_BASE:
2915                 vmx_segment_cache_clear(vmx);
2916                 vmcs_writel(GUEST_GS_BASE, data);
2917                 break;
2918         case MSR_KERNEL_GS_BASE:
2919                 vmx_load_host_state(vmx);
2920                 vmx->msr_guest_kernel_gs_base = data;
2921                 break;
2922 #endif
2923         case MSR_IA32_SYSENTER_CS:
2924                 vmcs_write32(GUEST_SYSENTER_CS, data);
2925                 break;
2926         case MSR_IA32_SYSENTER_EIP:
2927                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2928                 break;
2929         case MSR_IA32_SYSENTER_ESP:
2930                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2931                 break;
2932         case MSR_IA32_BNDCFGS:
2933                 if (!vmx_mpx_supported())
2934                         return 1;
2935                 vmcs_write64(GUEST_BNDCFGS, data);
2936                 break;
2937         case MSR_IA32_TSC:
2938                 kvm_write_tsc(vcpu, msr_info);
2939                 break;
2940         case MSR_IA32_CR_PAT:
2941                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2942                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2943                                 return 1;
2944                         vmcs_write64(GUEST_IA32_PAT, data);
2945                         vcpu->arch.pat = data;
2946                         break;
2947                 }
2948                 ret = kvm_set_msr_common(vcpu, msr_info);
2949                 break;
2950         case MSR_IA32_TSC_ADJUST:
2951                 ret = kvm_set_msr_common(vcpu, msr_info);
2952                 break;
2953         case MSR_IA32_FEATURE_CONTROL:
2954                 if (!nested_vmx_allowed(vcpu) ||
2955                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2956                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2957                         return 1;
2958                 vmx->nested.msr_ia32_feature_control = data;
2959                 if (msr_info->host_initiated && data == 0)
2960                         vmx_leave_nested(vcpu);
2961                 break;
2962         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2963                 return 1; /* they are read-only */
2964         case MSR_IA32_XSS:
2965                 if (!vmx_xsaves_supported())
2966                         return 1;
2967                 /*
2968                  * The only supported bit as of Skylake is bit 8, but
2969                  * it is not supported on KVM.
2970                  */
2971                 if (data != 0)
2972                         return 1;
2973                 vcpu->arch.ia32_xss = data;
2974                 if (vcpu->arch.ia32_xss != host_xss)
2975                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2976                                 vcpu->arch.ia32_xss, host_xss);
2977                 else
2978                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2979                 break;
2980         case MSR_TSC_AUX:
2981                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2982                         return 1;
2983                 /* Check reserved bit, higher 32 bits should be zero */
2984                 if ((data >> 32) != 0)
2985                         return 1;
2986                 /* Otherwise falls through */
2987         default:
2988                 msr = find_msr_entry(vmx, msr_index);
2989                 if (msr) {
2990                         u64 old_msr_data = msr->data;
2991                         msr->data = data;
2992                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2993                                 preempt_disable();
2994                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2995                                                          msr->mask);
2996                                 preempt_enable();
2997                                 if (ret)
2998                                         msr->data = old_msr_data;
2999                         }
3000                         break;
3001                 }
3002                 ret = kvm_set_msr_common(vcpu, msr_info);
3003         }
3004
3005         return ret;
3006 }
3007
3008 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3009 {
3010         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3011         switch (reg) {
3012         case VCPU_REGS_RSP:
3013                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3014                 break;
3015         case VCPU_REGS_RIP:
3016                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3017                 break;
3018         case VCPU_EXREG_PDPTR:
3019                 if (enable_ept)
3020                         ept_save_pdptrs(vcpu);
3021                 break;
3022         default:
3023                 break;
3024         }
3025 }
3026
3027 static __init int cpu_has_kvm_support(void)
3028 {
3029         return cpu_has_vmx();
3030 }
3031
3032 static __init int vmx_disabled_by_bios(void)
3033 {
3034         u64 msr;
3035
3036         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3037         if (msr & FEATURE_CONTROL_LOCKED) {
3038                 /* launched w/ TXT and VMX disabled */
3039                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3040                         && tboot_enabled())
3041                         return 1;
3042                 /* launched w/o TXT and VMX only enabled w/ TXT */
3043                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3044                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3045                         && !tboot_enabled()) {
3046                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3047                                 "activate TXT before enabling KVM\n");
3048                         return 1;
3049                 }
3050                 /* launched w/o TXT and VMX disabled */
3051                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3052                         && !tboot_enabled())
3053                         return 1;
3054         }
3055
3056         return 0;
3057 }
3058
3059 static void kvm_cpu_vmxon(u64 addr)
3060 {
3061         asm volatile (ASM_VMX_VMXON_RAX
3062                         : : "a"(&addr), "m"(addr)
3063                         : "memory", "cc");
3064 }
3065
3066 static int hardware_enable(void)
3067 {
3068         int cpu = raw_smp_processor_id();
3069         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3070         u64 old, test_bits;
3071
3072         if (cr4_read_shadow() & X86_CR4_VMXE)
3073                 return -EBUSY;
3074
3075         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3076         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3077         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3078
3079         /*
3080          * Now we can enable the vmclear operation in kdump
3081          * since the loaded_vmcss_on_cpu list on this cpu
3082          * has been initialized.
3083          *
3084          * Though the cpu is not in VMX operation now, there
3085          * is no problem to enable the vmclear operation
3086          * for the loaded_vmcss_on_cpu list is empty!
3087          */
3088         crash_enable_local_vmclear(cpu);
3089
3090         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3091
3092         test_bits = FEATURE_CONTROL_LOCKED;
3093         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3094         if (tboot_enabled())
3095                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3096
3097         if ((old & test_bits) != test_bits) {
3098                 /* enable and lock */
3099                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3100         }
3101         cr4_set_bits(X86_CR4_VMXE);
3102
3103         if (vmm_exclusive) {
3104                 kvm_cpu_vmxon(phys_addr);
3105                 ept_sync_global();
3106         }
3107
3108         native_store_gdt(this_cpu_ptr(&host_gdt));
3109
3110         return 0;
3111 }
3112
3113 static void vmclear_local_loaded_vmcss(void)
3114 {
3115         int cpu = raw_smp_processor_id();
3116         struct loaded_vmcs *v, *n;
3117
3118         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3119                                  loaded_vmcss_on_cpu_link)
3120                 __loaded_vmcs_clear(v);
3121 }
3122
3123
3124 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3125  * tricks.
3126  */
3127 static void kvm_cpu_vmxoff(void)
3128 {
3129         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3130 }
3131
3132 static void hardware_disable(void)
3133 {
3134         if (vmm_exclusive) {
3135                 vmclear_local_loaded_vmcss();
3136                 kvm_cpu_vmxoff();
3137         }
3138         cr4_clear_bits(X86_CR4_VMXE);
3139 }
3140
3141 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3142                                       u32 msr, u32 *result)
3143 {
3144         u32 vmx_msr_low, vmx_msr_high;
3145         u32 ctl = ctl_min | ctl_opt;
3146
3147         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3148
3149         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3150         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3151
3152         /* Ensure minimum (required) set of control bits are supported. */
3153         if (ctl_min & ~ctl)
3154                 return -EIO;
3155
3156         *result = ctl;
3157         return 0;
3158 }
3159
3160 static __init bool allow_1_setting(u32 msr, u32 ctl)
3161 {
3162         u32 vmx_msr_low, vmx_msr_high;
3163
3164         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3165         return vmx_msr_high & ctl;
3166 }
3167
3168 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3169 {
3170         u32 vmx_msr_low, vmx_msr_high;
3171         u32 min, opt, min2, opt2;
3172         u32 _pin_based_exec_control = 0;
3173         u32 _cpu_based_exec_control = 0;
3174         u32 _cpu_based_2nd_exec_control = 0;
3175         u32 _vmexit_control = 0;
3176         u32 _vmentry_control = 0;
3177
3178         min = CPU_BASED_HLT_EXITING |
3179 #ifdef CONFIG_X86_64
3180               CPU_BASED_CR8_LOAD_EXITING |
3181               CPU_BASED_CR8_STORE_EXITING |
3182 #endif
3183               CPU_BASED_CR3_LOAD_EXITING |
3184               CPU_BASED_CR3_STORE_EXITING |
3185               CPU_BASED_USE_IO_BITMAPS |
3186               CPU_BASED_MOV_DR_EXITING |
3187               CPU_BASED_USE_TSC_OFFSETING |
3188               CPU_BASED_MWAIT_EXITING |
3189               CPU_BASED_MONITOR_EXITING |
3190               CPU_BASED_INVLPG_EXITING |
3191               CPU_BASED_RDPMC_EXITING;
3192
3193         opt = CPU_BASED_TPR_SHADOW |
3194               CPU_BASED_USE_MSR_BITMAPS |
3195               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3196         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3197                                 &_cpu_based_exec_control) < 0)
3198                 return -EIO;
3199 #ifdef CONFIG_X86_64
3200         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3201                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3202                                            ~CPU_BASED_CR8_STORE_EXITING;
3203 #endif
3204         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3205                 min2 = 0;
3206                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3207                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3208                         SECONDARY_EXEC_WBINVD_EXITING |
3209                         SECONDARY_EXEC_ENABLE_VPID |
3210                         SECONDARY_EXEC_ENABLE_EPT |
3211                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3212                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3213                         SECONDARY_EXEC_RDTSCP |
3214                         SECONDARY_EXEC_ENABLE_INVPCID |
3215                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3216                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3217                         SECONDARY_EXEC_SHADOW_VMCS |
3218                         SECONDARY_EXEC_XSAVES |
3219                         SECONDARY_EXEC_ENABLE_PML |
3220                         SECONDARY_EXEC_PCOMMIT |
3221                         SECONDARY_EXEC_TSC_SCALING;
3222                 if (adjust_vmx_controls(min2, opt2,
3223                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3224                                         &_cpu_based_2nd_exec_control) < 0)
3225                         return -EIO;
3226         }
3227 #ifndef CONFIG_X86_64
3228         if (!(_cpu_based_2nd_exec_control &
3229                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3230                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3231 #endif
3232
3233         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3234                 _cpu_based_2nd_exec_control &= ~(
3235                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3236                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3237                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3238
3239         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3240                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3241                    enabled */
3242                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3243                                              CPU_BASED_CR3_STORE_EXITING |
3244                                              CPU_BASED_INVLPG_EXITING);
3245                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3246                       vmx_capability.ept, vmx_capability.vpid);
3247         }
3248
3249         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3250 #ifdef CONFIG_X86_64
3251         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3252 #endif
3253         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3254                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3255         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3256                                 &_vmexit_control) < 0)
3257                 return -EIO;
3258
3259         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3260         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3261         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3262                                 &_pin_based_exec_control) < 0)
3263                 return -EIO;
3264
3265         if (!(_cpu_based_2nd_exec_control &
3266                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3267                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3268                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3269
3270         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3271         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3272         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3273                                 &_vmentry_control) < 0)
3274                 return -EIO;
3275
3276         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3277
3278         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3279         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3280                 return -EIO;
3281
3282 #ifdef CONFIG_X86_64
3283         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3284         if (vmx_msr_high & (1u<<16))
3285                 return -EIO;
3286 #endif
3287
3288         /* Require Write-Back (WB) memory type for VMCS accesses. */
3289         if (((vmx_msr_high >> 18) & 15) != 6)
3290                 return -EIO;
3291
3292         vmcs_conf->size = vmx_msr_high & 0x1fff;
3293         vmcs_conf->order = get_order(vmcs_config.size);
3294         vmcs_conf->revision_id = vmx_msr_low;
3295
3296         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3297         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3298         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3299         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3300         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3301
3302         cpu_has_load_ia32_efer =
3303                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3304                                 VM_ENTRY_LOAD_IA32_EFER)
3305                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3306                                    VM_EXIT_LOAD_IA32_EFER);
3307
3308         cpu_has_load_perf_global_ctrl =
3309                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3310                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3311                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3312                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3313
3314         /*
3315          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3316          * but due to arrata below it can't be used. Workaround is to use
3317          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3318          *
3319          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3320          *
3321          * AAK155             (model 26)
3322          * AAP115             (model 30)
3323          * AAT100             (model 37)
3324          * BC86,AAY89,BD102   (model 44)
3325          * BA97               (model 46)
3326          *
3327          */
3328         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3329                 switch (boot_cpu_data.x86_model) {
3330                 case 26:
3331                 case 30:
3332                 case 37:
3333                 case 44:
3334                 case 46:
3335                         cpu_has_load_perf_global_ctrl = false;
3336                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3337                                         "does not work properly. Using workaround\n");
3338                         break;
3339                 default:
3340                         break;
3341                 }
3342         }
3343
3344         if (cpu_has_xsaves)
3345                 rdmsrl(MSR_IA32_XSS, host_xss);
3346
3347         return 0;
3348 }
3349
3350 static struct vmcs *alloc_vmcs_cpu(int cpu)
3351 {
3352         int node = cpu_to_node(cpu);
3353         struct page *pages;
3354         struct vmcs *vmcs;
3355
3356         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3357         if (!pages)
3358                 return NULL;
3359         vmcs = page_address(pages);
3360         memset(vmcs, 0, vmcs_config.size);
3361         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3362         return vmcs;
3363 }
3364
3365 static struct vmcs *alloc_vmcs(void)
3366 {
3367         return alloc_vmcs_cpu(raw_smp_processor_id());
3368 }
3369
3370 static void free_vmcs(struct vmcs *vmcs)
3371 {
3372         free_pages((unsigned long)vmcs, vmcs_config.order);
3373 }
3374
3375 /*
3376  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3377  */
3378 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3379 {
3380         if (!loaded_vmcs->vmcs)
3381                 return;
3382         loaded_vmcs_clear(loaded_vmcs);
3383         free_vmcs(loaded_vmcs->vmcs);
3384         loaded_vmcs->vmcs = NULL;
3385 }
3386
3387 static void free_kvm_area(void)
3388 {
3389         int cpu;
3390
3391         for_each_possible_cpu(cpu) {
3392                 free_vmcs(per_cpu(vmxarea, cpu));
3393                 per_cpu(vmxarea, cpu) = NULL;
3394         }
3395 }
3396
3397 static void init_vmcs_shadow_fields(void)
3398 {
3399         int i, j;
3400
3401         /* No checks for read only fields yet */
3402
3403         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3404                 switch (shadow_read_write_fields[i]) {
3405                 case GUEST_BNDCFGS:
3406                         if (!vmx_mpx_supported())
3407                                 continue;
3408                         break;
3409                 default:
3410                         break;
3411                 }
3412
3413                 if (j < i)
3414                         shadow_read_write_fields[j] =
3415                                 shadow_read_write_fields[i];
3416                 j++;
3417         }
3418         max_shadow_read_write_fields = j;
3419
3420         /* shadowed fields guest access without vmexit */
3421         for (i = 0; i < max_shadow_read_write_fields; i++) {
3422                 clear_bit(shadow_read_write_fields[i],
3423                           vmx_vmwrite_bitmap);
3424                 clear_bit(shadow_read_write_fields[i],
3425                           vmx_vmread_bitmap);
3426         }
3427         for (i = 0; i < max_shadow_read_only_fields; i++)
3428                 clear_bit(shadow_read_only_fields[i],
3429                           vmx_vmread_bitmap);
3430 }
3431
3432 static __init int alloc_kvm_area(void)
3433 {
3434         int cpu;
3435
3436         for_each_possible_cpu(cpu) {
3437                 struct vmcs *vmcs;
3438
3439                 vmcs = alloc_vmcs_cpu(cpu);
3440                 if (!vmcs) {
3441                         free_kvm_area();
3442                         return -ENOMEM;
3443                 }
3444
3445                 per_cpu(vmxarea, cpu) = vmcs;
3446         }
3447         return 0;
3448 }
3449
3450 static bool emulation_required(struct kvm_vcpu *vcpu)
3451 {
3452         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3453 }
3454
3455 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3456                 struct kvm_segment *save)
3457 {
3458         if (!emulate_invalid_guest_state) {
3459                 /*
3460                  * CS and SS RPL should be equal during guest entry according
3461                  * to VMX spec, but in reality it is not always so. Since vcpu
3462                  * is in the middle of the transition from real mode to
3463                  * protected mode it is safe to assume that RPL 0 is a good
3464                  * default value.
3465                  */
3466                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3467                         save->selector &= ~SEGMENT_RPL_MASK;
3468                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3469                 save->s = 1;
3470         }
3471         vmx_set_segment(vcpu, save, seg);
3472 }
3473
3474 static void enter_pmode(struct kvm_vcpu *vcpu)
3475 {
3476         unsigned long flags;
3477         struct vcpu_vmx *vmx = to_vmx(vcpu);
3478
3479         /*
3480          * Update real mode segment cache. It may be not up-to-date if sement
3481          * register was written while vcpu was in a guest mode.
3482          */
3483         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3484         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3485         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3486         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3487         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3488         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3489
3490         vmx->rmode.vm86_active = 0;
3491
3492         vmx_segment_cache_clear(vmx);
3493
3494         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3495
3496         flags = vmcs_readl(GUEST_RFLAGS);
3497         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3498         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3499         vmcs_writel(GUEST_RFLAGS, flags);
3500
3501         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3502                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3503
3504         update_exception_bitmap(vcpu);
3505
3506         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3507         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3508         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3509         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3510         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3511         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3512 }
3513
3514 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3515 {
3516         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3517         struct kvm_segment var = *save;
3518
3519         var.dpl = 0x3;
3520         if (seg == VCPU_SREG_CS)
3521                 var.type = 0x3;
3522
3523         if (!emulate_invalid_guest_state) {
3524                 var.selector = var.base >> 4;
3525                 var.base = var.base & 0xffff0;
3526                 var.limit = 0xffff;
3527                 var.g = 0;
3528                 var.db = 0;
3529                 var.present = 1;
3530                 var.s = 1;
3531                 var.l = 0;
3532                 var.unusable = 0;
3533                 var.type = 0x3;
3534                 var.avl = 0;
3535                 if (save->base & 0xf)
3536                         printk_once(KERN_WARNING "kvm: segment base is not "
3537                                         "paragraph aligned when entering "
3538                                         "protected mode (seg=%d)", seg);
3539         }
3540
3541         vmcs_write16(sf->selector, var.selector);
3542         vmcs_write32(sf->base, var.base);
3543         vmcs_write32(sf->limit, var.limit);
3544         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3545 }
3546
3547 static void enter_rmode(struct kvm_vcpu *vcpu)
3548 {
3549         unsigned long flags;
3550         struct vcpu_vmx *vmx = to_vmx(vcpu);
3551
3552         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3553         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3554         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3555         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3556         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3557         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3558         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3559
3560         vmx->rmode.vm86_active = 1;
3561
3562         /*
3563          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3564          * vcpu. Warn the user that an update is overdue.
3565          */
3566         if (!vcpu->kvm->arch.tss_addr)
3567                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3568                              "called before entering vcpu\n");
3569
3570         vmx_segment_cache_clear(vmx);
3571
3572         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3573         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3574         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3575
3576         flags = vmcs_readl(GUEST_RFLAGS);
3577         vmx->rmode.save_rflags = flags;
3578
3579         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3580
3581         vmcs_writel(GUEST_RFLAGS, flags);
3582         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3583         update_exception_bitmap(vcpu);
3584
3585         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3586         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3587         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3588         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3589         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3590         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3591
3592         kvm_mmu_reset_context(vcpu);
3593 }
3594
3595 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3596 {
3597         struct vcpu_vmx *vmx = to_vmx(vcpu);
3598         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3599
3600         if (!msr)
3601                 return;
3602
3603         /*
3604          * Force kernel_gs_base reloading before EFER changes, as control
3605          * of this msr depends on is_long_mode().
3606          */
3607         vmx_load_host_state(to_vmx(vcpu));
3608         vcpu->arch.efer = efer;
3609         if (efer & EFER_LMA) {
3610                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3611                 msr->data = efer;
3612         } else {
3613                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3614
3615                 msr->data = efer & ~EFER_LME;
3616         }
3617         setup_msrs(vmx);
3618 }
3619
3620 #ifdef CONFIG_X86_64
3621
3622 static void enter_lmode(struct kvm_vcpu *vcpu)
3623 {
3624         u32 guest_tr_ar;
3625
3626         vmx_segment_cache_clear(to_vmx(vcpu));
3627
3628         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3629         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3630                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3631                                      __func__);
3632                 vmcs_write32(GUEST_TR_AR_BYTES,
3633                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3634                              | VMX_AR_TYPE_BUSY_64_TSS);
3635         }
3636         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3637 }
3638
3639 static void exit_lmode(struct kvm_vcpu *vcpu)
3640 {
3641         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3642         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3643 }
3644
3645 #endif
3646
3647 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3648 {
3649         vpid_sync_context(vpid);
3650         if (enable_ept) {
3651                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3652                         return;
3653                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3654         }
3655 }
3656
3657 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3658 {
3659         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3660 }
3661
3662 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3663 {
3664         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3665
3666         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3667         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3668 }
3669
3670 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3671 {
3672         if (enable_ept && is_paging(vcpu))
3673                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3674         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3675 }
3676
3677 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3678 {
3679         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3680
3681         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3682         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3683 }
3684
3685 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3686 {
3687         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3688
3689         if (!test_bit(VCPU_EXREG_PDPTR,
3690                       (unsigned long *)&vcpu->arch.regs_dirty))
3691                 return;
3692
3693         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3694                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3695                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3696                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3697                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3698         }
3699 }
3700
3701 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3702 {
3703         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3704
3705         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3706                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3707                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3708                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3709                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3710         }
3711
3712         __set_bit(VCPU_EXREG_PDPTR,
3713                   (unsigned long *)&vcpu->arch.regs_avail);
3714         __set_bit(VCPU_EXREG_PDPTR,
3715                   (unsigned long *)&vcpu->arch.regs_dirty);
3716 }
3717
3718 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3719
3720 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3721                                         unsigned long cr0,
3722                                         struct kvm_vcpu *vcpu)
3723 {
3724         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3725                 vmx_decache_cr3(vcpu);
3726         if (!(cr0 & X86_CR0_PG)) {
3727                 /* From paging/starting to nonpaging */
3728                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3729                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3730                              (CPU_BASED_CR3_LOAD_EXITING |
3731                               CPU_BASED_CR3_STORE_EXITING));
3732                 vcpu->arch.cr0 = cr0;
3733                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3734         } else if (!is_paging(vcpu)) {
3735                 /* From nonpaging to paging */
3736                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3737                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3738                              ~(CPU_BASED_CR3_LOAD_EXITING |
3739                                CPU_BASED_CR3_STORE_EXITING));
3740                 vcpu->arch.cr0 = cr0;
3741                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3742         }
3743
3744         if (!(cr0 & X86_CR0_WP))
3745                 *hw_cr0 &= ~X86_CR0_WP;
3746 }
3747
3748 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3749 {
3750         struct vcpu_vmx *vmx = to_vmx(vcpu);
3751         unsigned long hw_cr0;
3752
3753         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3754         if (enable_unrestricted_guest)
3755                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3756         else {
3757                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3758
3759                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3760                         enter_pmode(vcpu);
3761
3762                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3763                         enter_rmode(vcpu);
3764         }
3765
3766 #ifdef CONFIG_X86_64
3767         if (vcpu->arch.efer & EFER_LME) {
3768                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3769                         enter_lmode(vcpu);
3770                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3771                         exit_lmode(vcpu);
3772         }
3773 #endif
3774
3775         if (enable_ept)
3776                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3777
3778         if (!vcpu->fpu_active)
3779                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3780
3781         vmcs_writel(CR0_READ_SHADOW, cr0);
3782         vmcs_writel(GUEST_CR0, hw_cr0);
3783         vcpu->arch.cr0 = cr0;
3784
3785         /* depends on vcpu->arch.cr0 to be set to a new value */
3786         vmx->emulation_required = emulation_required(vcpu);
3787 }
3788
3789 static u64 construct_eptp(unsigned long root_hpa)
3790 {
3791         u64 eptp;
3792
3793         /* TODO write the value reading from MSR */
3794         eptp = VMX_EPT_DEFAULT_MT |
3795                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3796         if (enable_ept_ad_bits)
3797                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3798         eptp |= (root_hpa & PAGE_MASK);
3799
3800         return eptp;
3801 }
3802
3803 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3804 {
3805         unsigned long guest_cr3;
3806         u64 eptp;
3807
3808         guest_cr3 = cr3;
3809         if (enable_ept) {
3810                 eptp = construct_eptp(cr3);
3811                 vmcs_write64(EPT_POINTER, eptp);
3812                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3813                         guest_cr3 = kvm_read_cr3(vcpu);
3814                 else
3815                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3816                 ept_load_pdptrs(vcpu);
3817         }
3818
3819         vmx_flush_tlb(vcpu);
3820         vmcs_writel(GUEST_CR3, guest_cr3);
3821 }
3822
3823 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3824 {
3825         /*
3826          * Pass through host's Machine Check Enable value to hw_cr4, which
3827          * is in force while we are in guest mode.  Do not let guests control
3828          * this bit, even if host CR4.MCE == 0.
3829          */
3830         unsigned long hw_cr4 =
3831                 (cr4_read_shadow() & X86_CR4_MCE) |
3832                 (cr4 & ~X86_CR4_MCE) |
3833                 (to_vmx(vcpu)->rmode.vm86_active ?
3834                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3835
3836         if (cr4 & X86_CR4_VMXE) {
3837                 /*
3838                  * To use VMXON (and later other VMX instructions), a guest
3839                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3840                  * So basically the check on whether to allow nested VMX
3841                  * is here.
3842                  */
3843                 if (!nested_vmx_allowed(vcpu))
3844                         return 1;
3845         }
3846         if (to_vmx(vcpu)->nested.vmxon &&
3847             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3848                 return 1;
3849
3850         vcpu->arch.cr4 = cr4;
3851         if (enable_ept) {
3852                 if (!is_paging(vcpu)) {
3853                         hw_cr4 &= ~X86_CR4_PAE;
3854                         hw_cr4 |= X86_CR4_PSE;
3855                 } else if (!(cr4 & X86_CR4_PAE)) {
3856                         hw_cr4 &= ~X86_CR4_PAE;
3857                 }
3858         }
3859
3860         if (!enable_unrestricted_guest && !is_paging(vcpu))
3861                 /*
3862                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3863                  * hardware.  However KVM always uses paging mode without
3864                  * unrestricted guest.
3865                  * To emulate this behavior, SMEP/SMAP needs to be manually
3866                  * disabled when guest switches to non-paging mode.
3867                  */
3868                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3869
3870         vmcs_writel(CR4_READ_SHADOW, cr4);
3871         vmcs_writel(GUEST_CR4, hw_cr4);
3872         return 0;
3873 }
3874
3875 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3876                             struct kvm_segment *var, int seg)
3877 {
3878         struct vcpu_vmx *vmx = to_vmx(vcpu);
3879         u32 ar;
3880
3881         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3882                 *var = vmx->rmode.segs[seg];
3883                 if (seg == VCPU_SREG_TR
3884                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3885                         return;
3886                 var->base = vmx_read_guest_seg_base(vmx, seg);
3887                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3888                 return;
3889         }
3890         var->base = vmx_read_guest_seg_base(vmx, seg);
3891         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3892         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3893         ar = vmx_read_guest_seg_ar(vmx, seg);
3894         var->unusable = (ar >> 16) & 1;
3895         var->type = ar & 15;
3896         var->s = (ar >> 4) & 1;
3897         var->dpl = (ar >> 5) & 3;
3898         /*
3899          * Some userspaces do not preserve unusable property. Since usable
3900          * segment has to be present according to VMX spec we can use present
3901          * property to amend userspace bug by making unusable segment always
3902          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3903          * segment as unusable.
3904          */
3905         var->present = !var->unusable;
3906         var->avl = (ar >> 12) & 1;
3907         var->l = (ar >> 13) & 1;
3908         var->db = (ar >> 14) & 1;
3909         var->g = (ar >> 15) & 1;
3910 }
3911
3912 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3913 {
3914         struct kvm_segment s;
3915
3916         if (to_vmx(vcpu)->rmode.vm86_active) {
3917                 vmx_get_segment(vcpu, &s, seg);
3918                 return s.base;
3919         }
3920         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3921 }
3922
3923 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3924 {
3925         struct vcpu_vmx *vmx = to_vmx(vcpu);
3926
3927         if (unlikely(vmx->rmode.vm86_active))
3928                 return 0;
3929         else {
3930                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3931                 return VMX_AR_DPL(ar);
3932         }
3933 }
3934
3935 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3936 {
3937         u32 ar;
3938
3939         if (var->unusable || !var->present)
3940                 ar = 1 << 16;
3941         else {
3942                 ar = var->type & 15;
3943                 ar |= (var->s & 1) << 4;
3944                 ar |= (var->dpl & 3) << 5;
3945                 ar |= (var->present & 1) << 7;
3946                 ar |= (var->avl & 1) << 12;
3947                 ar |= (var->l & 1) << 13;
3948                 ar |= (var->db & 1) << 14;
3949                 ar |= (var->g & 1) << 15;
3950         }
3951
3952         return ar;
3953 }
3954
3955 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3956                             struct kvm_segment *var, int seg)
3957 {
3958         struct vcpu_vmx *vmx = to_vmx(vcpu);
3959         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3960
3961         vmx_segment_cache_clear(vmx);
3962
3963         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3964                 vmx->rmode.segs[seg] = *var;
3965                 if (seg == VCPU_SREG_TR)
3966                         vmcs_write16(sf->selector, var->selector);
3967                 else if (var->s)
3968                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3969                 goto out;
3970         }
3971
3972         vmcs_writel(sf->base, var->base);
3973         vmcs_write32(sf->limit, var->limit);
3974         vmcs_write16(sf->selector, var->selector);
3975
3976         /*
3977          *   Fix the "Accessed" bit in AR field of segment registers for older
3978          * qemu binaries.
3979          *   IA32 arch specifies that at the time of processor reset the
3980          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3981          * is setting it to 0 in the userland code. This causes invalid guest
3982          * state vmexit when "unrestricted guest" mode is turned on.
3983          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3984          * tree. Newer qemu binaries with that qemu fix would not need this
3985          * kvm hack.
3986          */
3987         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3988                 var->type |= 0x1; /* Accessed */
3989
3990         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3991
3992 out:
3993         vmx->emulation_required = emulation_required(vcpu);
3994 }
3995
3996 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3997 {
3998         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3999
4000         *db = (ar >> 14) & 1;
4001         *l = (ar >> 13) & 1;
4002 }
4003
4004 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4005 {
4006         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4007         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4008 }
4009
4010 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4011 {
4012         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4013         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4014 }
4015
4016 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4017 {
4018         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4019         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4020 }
4021
4022 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4023 {
4024         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4025         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4026 }
4027
4028 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4029 {
4030         struct kvm_segment var;
4031         u32 ar;
4032
4033         vmx_get_segment(vcpu, &var, seg);
4034         var.dpl = 0x3;
4035         if (seg == VCPU_SREG_CS)
4036                 var.type = 0x3;
4037         ar = vmx_segment_access_rights(&var);
4038
4039         if (var.base != (var.selector << 4))
4040                 return false;
4041         if (var.limit != 0xffff)
4042                 return false;
4043         if (ar != 0xf3)
4044                 return false;
4045
4046         return true;
4047 }
4048
4049 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4050 {
4051         struct kvm_segment cs;
4052         unsigned int cs_rpl;
4053
4054         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4055         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4056
4057         if (cs.unusable)
4058                 return false;
4059         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4060                 return false;
4061         if (!cs.s)
4062                 return false;
4063         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4064                 if (cs.dpl > cs_rpl)
4065                         return false;
4066         } else {
4067                 if (cs.dpl != cs_rpl)
4068                         return false;
4069         }
4070         if (!cs.present)
4071                 return false;
4072
4073         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4074         return true;
4075 }
4076
4077 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4078 {
4079         struct kvm_segment ss;
4080         unsigned int ss_rpl;
4081
4082         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4083         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4084
4085         if (ss.unusable)
4086                 return true;
4087         if (ss.type != 3 && ss.type != 7)
4088                 return false;
4089         if (!ss.s)
4090                 return false;
4091         if (ss.dpl != ss_rpl) /* DPL != RPL */
4092                 return false;
4093         if (!ss.present)
4094                 return false;
4095
4096         return true;
4097 }
4098
4099 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4100 {
4101         struct kvm_segment var;
4102         unsigned int rpl;
4103
4104         vmx_get_segment(vcpu, &var, seg);
4105         rpl = var.selector & SEGMENT_RPL_MASK;
4106
4107         if (var.unusable)
4108                 return true;
4109         if (!var.s)
4110                 return false;
4111         if (!var.present)
4112                 return false;
4113         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4114                 if (var.dpl < rpl) /* DPL < RPL */
4115                         return false;
4116         }
4117
4118         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4119          * rights flags
4120          */
4121         return true;
4122 }
4123
4124 static bool tr_valid(struct kvm_vcpu *vcpu)
4125 {
4126         struct kvm_segment tr;
4127
4128         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4129
4130         if (tr.unusable)
4131                 return false;
4132         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4133                 return false;
4134         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4135                 return false;
4136         if (!tr.present)
4137                 return false;
4138
4139         return true;
4140 }
4141
4142 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4143 {
4144         struct kvm_segment ldtr;
4145
4146         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4147
4148         if (ldtr.unusable)
4149                 return true;
4150         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4151                 return false;
4152         if (ldtr.type != 2)
4153                 return false;
4154         if (!ldtr.present)
4155                 return false;
4156
4157         return true;
4158 }
4159
4160 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4161 {
4162         struct kvm_segment cs, ss;
4163
4164         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4165         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4166
4167         return ((cs.selector & SEGMENT_RPL_MASK) ==
4168                  (ss.selector & SEGMENT_RPL_MASK));
4169 }
4170
4171 /*
4172  * Check if guest state is valid. Returns true if valid, false if
4173  * not.
4174  * We assume that registers are always usable
4175  */
4176 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4177 {
4178         if (enable_unrestricted_guest)
4179                 return true;
4180
4181         /* real mode guest state checks */
4182         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4183                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4184                         return false;
4185                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4186                         return false;
4187                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4188                         return false;
4189                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4190                         return false;
4191                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4192                         return false;
4193                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4194                         return false;
4195         } else {
4196         /* protected mode guest state checks */
4197                 if (!cs_ss_rpl_check(vcpu))
4198                         return false;
4199                 if (!code_segment_valid(vcpu))
4200                         return false;
4201                 if (!stack_segment_valid(vcpu))
4202                         return false;
4203                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4204                         return false;
4205                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4206                         return false;
4207                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4208                         return false;
4209                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4210                         return false;
4211                 if (!tr_valid(vcpu))
4212                         return false;
4213                 if (!ldtr_valid(vcpu))
4214                         return false;
4215         }
4216         /* TODO:
4217          * - Add checks on RIP
4218          * - Add checks on RFLAGS
4219          */
4220
4221         return true;
4222 }
4223
4224 static int init_rmode_tss(struct kvm *kvm)
4225 {
4226         gfn_t fn;
4227         u16 data = 0;
4228         int idx, r;
4229
4230         idx = srcu_read_lock(&kvm->srcu);
4231         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4232         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4233         if (r < 0)
4234                 goto out;
4235         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4236         r = kvm_write_guest_page(kvm, fn++, &data,
4237                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4238         if (r < 0)
4239                 goto out;
4240         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4241         if (r < 0)
4242                 goto out;
4243         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4244         if (r < 0)
4245                 goto out;
4246         data = ~0;
4247         r = kvm_write_guest_page(kvm, fn, &data,
4248                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4249                                  sizeof(u8));
4250 out:
4251         srcu_read_unlock(&kvm->srcu, idx);
4252         return r;
4253 }
4254
4255 static int init_rmode_identity_map(struct kvm *kvm)
4256 {
4257         int i, idx, r = 0;
4258         kvm_pfn_t identity_map_pfn;
4259         u32 tmp;
4260
4261         if (!enable_ept)
4262                 return 0;
4263
4264         /* Protect kvm->arch.ept_identity_pagetable_done. */
4265         mutex_lock(&kvm->slots_lock);
4266
4267         if (likely(kvm->arch.ept_identity_pagetable_done))
4268                 goto out2;
4269
4270         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4271
4272         r = alloc_identity_pagetable(kvm);
4273         if (r < 0)
4274                 goto out2;
4275
4276         idx = srcu_read_lock(&kvm->srcu);
4277         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4278         if (r < 0)
4279                 goto out;
4280         /* Set up identity-mapping pagetable for EPT in real mode */
4281         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4282                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4283                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4284                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4285                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4286                 if (r < 0)
4287                         goto out;
4288         }
4289         kvm->arch.ept_identity_pagetable_done = true;
4290
4291 out:
4292         srcu_read_unlock(&kvm->srcu, idx);
4293
4294 out2:
4295         mutex_unlock(&kvm->slots_lock);
4296         return r;
4297 }
4298
4299 static void seg_setup(int seg)
4300 {
4301         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4302         unsigned int ar;
4303
4304         vmcs_write16(sf->selector, 0);
4305         vmcs_writel(sf->base, 0);
4306         vmcs_write32(sf->limit, 0xffff);
4307         ar = 0x93;
4308         if (seg == VCPU_SREG_CS)
4309                 ar |= 0x08; /* code segment */
4310
4311         vmcs_write32(sf->ar_bytes, ar);
4312 }
4313
4314 static int alloc_apic_access_page(struct kvm *kvm)
4315 {
4316         struct page *page;
4317         int r = 0;
4318
4319         mutex_lock(&kvm->slots_lock);
4320         if (kvm->arch.apic_access_page_done)
4321                 goto out;
4322         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4323                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4324         if (r)
4325                 goto out;
4326
4327         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4328         if (is_error_page(page)) {
4329                 r = -EFAULT;
4330                 goto out;
4331         }
4332
4333         /*
4334          * Do not pin the page in memory, so that memory hot-unplug
4335          * is able to migrate it.
4336          */
4337         put_page(page);
4338         kvm->arch.apic_access_page_done = true;
4339 out:
4340         mutex_unlock(&kvm->slots_lock);
4341         return r;
4342 }
4343
4344 static int alloc_identity_pagetable(struct kvm *kvm)
4345 {
4346         /* Called with kvm->slots_lock held. */
4347
4348         int r = 0;
4349
4350         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4351
4352         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4353                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4354
4355         return r;
4356 }
4357
4358 static int allocate_vpid(void)
4359 {
4360         int vpid;
4361
4362         if (!enable_vpid)
4363                 return 0;
4364         spin_lock(&vmx_vpid_lock);
4365         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4366         if (vpid < VMX_NR_VPIDS)
4367                 __set_bit(vpid, vmx_vpid_bitmap);
4368         else
4369                 vpid = 0;
4370         spin_unlock(&vmx_vpid_lock);
4371         return vpid;
4372 }
4373
4374 static void free_vpid(int vpid)
4375 {
4376         if (!enable_vpid || vpid == 0)
4377                 return;
4378         spin_lock(&vmx_vpid_lock);
4379         __clear_bit(vpid, vmx_vpid_bitmap);
4380         spin_unlock(&vmx_vpid_lock);
4381 }
4382
4383 #define MSR_TYPE_R      1
4384 #define MSR_TYPE_W      2
4385 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4386                                                 u32 msr, int type)
4387 {
4388         int f = sizeof(unsigned long);
4389
4390         if (!cpu_has_vmx_msr_bitmap())
4391                 return;
4392
4393         /*
4394          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4395          * have the write-low and read-high bitmap offsets the wrong way round.
4396          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4397          */
4398         if (msr <= 0x1fff) {
4399                 if (type & MSR_TYPE_R)
4400                         /* read-low */
4401                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4402
4403                 if (type & MSR_TYPE_W)
4404                         /* write-low */
4405                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4406
4407         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4408                 msr &= 0x1fff;
4409                 if (type & MSR_TYPE_R)
4410                         /* read-high */
4411                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4412
4413                 if (type & MSR_TYPE_W)
4414                         /* write-high */
4415                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4416
4417         }
4418 }
4419
4420 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4421                                                 u32 msr, int type)
4422 {
4423         int f = sizeof(unsigned long);
4424
4425         if (!cpu_has_vmx_msr_bitmap())
4426                 return;
4427
4428         /*
4429          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4430          * have the write-low and read-high bitmap offsets the wrong way round.
4431          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4432          */
4433         if (msr <= 0x1fff) {
4434                 if (type & MSR_TYPE_R)
4435                         /* read-low */
4436                         __set_bit(msr, msr_bitmap + 0x000 / f);
4437
4438                 if (type & MSR_TYPE_W)
4439                         /* write-low */
4440                         __set_bit(msr, msr_bitmap + 0x800 / f);
4441
4442         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4443                 msr &= 0x1fff;
4444                 if (type & MSR_TYPE_R)
4445                         /* read-high */
4446                         __set_bit(msr, msr_bitmap + 0x400 / f);
4447
4448                 if (type & MSR_TYPE_W)
4449                         /* write-high */
4450                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4451
4452         }
4453 }
4454
4455 /*
4456  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4457  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4458  */
4459 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4460                                                unsigned long *msr_bitmap_nested,
4461                                                u32 msr, int type)
4462 {
4463         int f = sizeof(unsigned long);
4464
4465         if (!cpu_has_vmx_msr_bitmap()) {
4466                 WARN_ON(1);
4467                 return;
4468         }
4469
4470         /*
4471          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4472          * have the write-low and read-high bitmap offsets the wrong way round.
4473          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4474          */
4475         if (msr <= 0x1fff) {
4476                 if (type & MSR_TYPE_R &&
4477                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4478                         /* read-low */
4479                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4480
4481                 if (type & MSR_TYPE_W &&
4482                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4483                         /* write-low */
4484                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4485
4486         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4487                 msr &= 0x1fff;
4488                 if (type & MSR_TYPE_R &&
4489                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4490                         /* read-high */
4491                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4492
4493                 if (type & MSR_TYPE_W &&
4494                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4495                         /* write-high */
4496                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4497
4498         }
4499 }
4500
4501 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4502 {
4503         if (!longmode_only)
4504                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4505                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4506         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4507                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4508 }
4509
4510 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4511 {
4512         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4513                         msr, MSR_TYPE_R);
4514         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4515                         msr, MSR_TYPE_R);
4516 }
4517
4518 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4519 {
4520         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4521                         msr, MSR_TYPE_R);
4522         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4523                         msr, MSR_TYPE_R);
4524 }
4525
4526 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4527 {
4528         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4529                         msr, MSR_TYPE_W);
4530         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4531                         msr, MSR_TYPE_W);
4532 }
4533
4534 static bool vmx_get_enable_apicv(void)
4535 {
4536         return enable_apicv;
4537 }
4538
4539 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4540 {
4541         struct vcpu_vmx *vmx = to_vmx(vcpu);
4542         int max_irr;
4543         void *vapic_page;
4544         u16 status;
4545
4546         if (vmx->nested.pi_desc &&
4547             vmx->nested.pi_pending) {
4548                 vmx->nested.pi_pending = false;
4549                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4550                         return 0;
4551
4552                 max_irr = find_last_bit(
4553                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4554
4555                 if (max_irr == 256)
4556                         return 0;
4557
4558                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4559                 if (!vapic_page) {
4560                         WARN_ON(1);
4561                         return -ENOMEM;
4562                 }
4563                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4564                 kunmap(vmx->nested.virtual_apic_page);
4565
4566                 status = vmcs_read16(GUEST_INTR_STATUS);
4567                 if ((u8)max_irr > ((u8)status & 0xff)) {
4568                         status &= ~0xff;
4569                         status |= (u8)max_irr;
4570                         vmcs_write16(GUEST_INTR_STATUS, status);
4571                 }
4572         }
4573         return 0;
4574 }
4575
4576 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4577 {
4578 #ifdef CONFIG_SMP
4579         if (vcpu->mode == IN_GUEST_MODE) {
4580                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4581
4582                 /*
4583                  * Currently, we don't support urgent interrupt,
4584                  * all interrupts are recognized as non-urgent
4585                  * interrupt, so we cannot post interrupts when
4586                  * 'SN' is set.
4587                  *
4588                  * If the vcpu is in guest mode, it means it is
4589                  * running instead of being scheduled out and
4590                  * waiting in the run queue, and that's the only
4591                  * case when 'SN' is set currently, warning if
4592                  * 'SN' is set.
4593                  */
4594                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4595
4596                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4597                                 POSTED_INTR_VECTOR);
4598                 return true;
4599         }
4600 #endif
4601         return false;
4602 }
4603
4604 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4605                                                 int vector)
4606 {
4607         struct vcpu_vmx *vmx = to_vmx(vcpu);
4608
4609         if (is_guest_mode(vcpu) &&
4610             vector == vmx->nested.posted_intr_nv) {
4611                 /* the PIR and ON have been set by L1. */
4612                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4613                 /*
4614                  * If a posted intr is not recognized by hardware,
4615                  * we will accomplish it in the next vmentry.
4616                  */
4617                 vmx->nested.pi_pending = true;
4618                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4619                 return 0;
4620         }
4621         return -1;
4622 }
4623 /*
4624  * Send interrupt to vcpu via posted interrupt way.
4625  * 1. If target vcpu is running(non-root mode), send posted interrupt
4626  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4627  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4628  * interrupt from PIR in next vmentry.
4629  */
4630 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4631 {
4632         struct vcpu_vmx *vmx = to_vmx(vcpu);
4633         int r;
4634
4635         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4636         if (!r)
4637                 return;
4638
4639         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4640                 return;
4641
4642         r = pi_test_and_set_on(&vmx->pi_desc);
4643         kvm_make_request(KVM_REQ_EVENT, vcpu);
4644         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4645                 kvm_vcpu_kick(vcpu);
4646 }
4647
4648 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4649 {
4650         struct vcpu_vmx *vmx = to_vmx(vcpu);
4651
4652         if (!pi_test_and_clear_on(&vmx->pi_desc))
4653                 return;
4654
4655         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4656 }
4657
4658 /*
4659  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4660  * will not change in the lifetime of the guest.
4661  * Note that host-state that does change is set elsewhere. E.g., host-state
4662  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4663  */
4664 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4665 {
4666         u32 low32, high32;
4667         unsigned long tmpl;
4668         struct desc_ptr dt;
4669         unsigned long cr4;
4670
4671         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4672         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4673
4674         /* Save the most likely value for this task's CR4 in the VMCS. */
4675         cr4 = cr4_read_shadow();
4676         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4677         vmx->host_state.vmcs_host_cr4 = cr4;
4678
4679         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4680 #ifdef CONFIG_X86_64
4681         /*
4682          * Load null selectors, so we can avoid reloading them in
4683          * __vmx_load_host_state(), in case userspace uses the null selectors
4684          * too (the expected case).
4685          */
4686         vmcs_write16(HOST_DS_SELECTOR, 0);
4687         vmcs_write16(HOST_ES_SELECTOR, 0);
4688 #else
4689         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4690         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4691 #endif
4692         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4693         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4694
4695         native_store_idt(&dt);
4696         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4697         vmx->host_idt_base = dt.address;
4698
4699         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4700
4701         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4702         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4703         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4704         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4705
4706         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4707                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4708                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4709         }
4710 }
4711
4712 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4713 {
4714         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4715         if (enable_ept)
4716                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4717         if (is_guest_mode(&vmx->vcpu))
4718                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4719                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4720         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4721 }
4722
4723 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4724 {
4725         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4726
4727         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4728                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4729         return pin_based_exec_ctrl;
4730 }
4731
4732 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4733 {
4734         struct vcpu_vmx *vmx = to_vmx(vcpu);
4735
4736         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4737 }
4738
4739 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4740 {
4741         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4742
4743         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4744                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4745
4746         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4747                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4748 #ifdef CONFIG_X86_64
4749                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4750                                 CPU_BASED_CR8_LOAD_EXITING;
4751 #endif
4752         }
4753         if (!enable_ept)
4754                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4755                                 CPU_BASED_CR3_LOAD_EXITING  |
4756                                 CPU_BASED_INVLPG_EXITING;
4757         return exec_control;
4758 }
4759
4760 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4761 {
4762         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4763         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4764                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4765         if (vmx->vpid == 0)
4766                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4767         if (!enable_ept) {
4768                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4769                 enable_unrestricted_guest = 0;
4770                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4771                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4772         }
4773         if (!enable_unrestricted_guest)
4774                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4775         if (!ple_gap)
4776                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4777         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4778                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4779                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4780         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4781         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4782            (handle_vmptrld).
4783            We can NOT enable shadow_vmcs here because we don't have yet
4784            a current VMCS12
4785         */
4786         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4787
4788         if (!enable_pml)
4789                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4790
4791         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4792         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4793
4794         return exec_control;
4795 }
4796
4797 static void ept_set_mmio_spte_mask(void)
4798 {
4799         /*
4800          * EPT Misconfigurations can be generated if the value of bits 2:0
4801          * of an EPT paging-structure entry is 110b (write/execute).
4802          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4803          * spte.
4804          */
4805         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4806 }
4807
4808 #define VMX_XSS_EXIT_BITMAP 0
4809 /*
4810  * Sets up the vmcs for emulated real mode.
4811  */
4812 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4813 {
4814 #ifdef CONFIG_X86_64
4815         unsigned long a;
4816 #endif
4817         int i;
4818
4819         /* I/O */
4820         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4821         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4822
4823         if (enable_shadow_vmcs) {
4824                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4825                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4826         }
4827         if (cpu_has_vmx_msr_bitmap())
4828                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4829
4830         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4831
4832         /* Control */
4833         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4834
4835         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4836
4837         if (cpu_has_secondary_exec_ctrls())
4838                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4839                                 vmx_secondary_exec_control(vmx));
4840
4841         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4842                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4843                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4844                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4845                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4846
4847                 vmcs_write16(GUEST_INTR_STATUS, 0);
4848
4849                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4850                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4851         }
4852
4853         if (ple_gap) {
4854                 vmcs_write32(PLE_GAP, ple_gap);
4855                 vmx->ple_window = ple_window;
4856                 vmx->ple_window_dirty = true;
4857         }
4858
4859         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4860         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4861         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4862
4863         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4864         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4865         vmx_set_constant_host_state(vmx);
4866 #ifdef CONFIG_X86_64
4867         rdmsrl(MSR_FS_BASE, a);
4868         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4869         rdmsrl(MSR_GS_BASE, a);
4870         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4871 #else
4872         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4873         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4874 #endif
4875
4876         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4877         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4878         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4879         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4880         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4881
4882         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4883                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4884
4885         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4886                 u32 index = vmx_msr_index[i];
4887                 u32 data_low, data_high;
4888                 int j = vmx->nmsrs;
4889
4890                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4891                         continue;
4892                 if (wrmsr_safe(index, data_low, data_high) < 0)
4893                         continue;
4894                 vmx->guest_msrs[j].index = i;
4895                 vmx->guest_msrs[j].data = 0;
4896                 vmx->guest_msrs[j].mask = -1ull;
4897                 ++vmx->nmsrs;
4898         }
4899
4900
4901         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4902
4903         /* 22.2.1, 20.8.1 */
4904         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4905
4906         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4907         set_cr4_guest_host_mask(vmx);
4908
4909         if (vmx_xsaves_supported())
4910                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4911
4912         return 0;
4913 }
4914
4915 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4916 {
4917         struct vcpu_vmx *vmx = to_vmx(vcpu);
4918         struct msr_data apic_base_msr;
4919         u64 cr0;
4920
4921         vmx->rmode.vm86_active = 0;
4922
4923         vmx->soft_vnmi_blocked = 0;
4924
4925         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4926         kvm_set_cr8(vcpu, 0);
4927
4928         if (!init_event) {
4929                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4930                                      MSR_IA32_APICBASE_ENABLE;
4931                 if (kvm_vcpu_is_reset_bsp(vcpu))
4932                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4933                 apic_base_msr.host_initiated = true;
4934                 kvm_set_apic_base(vcpu, &apic_base_msr);
4935         }
4936
4937         vmx_segment_cache_clear(vmx);
4938
4939         seg_setup(VCPU_SREG_CS);
4940         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4941         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4942
4943         seg_setup(VCPU_SREG_DS);
4944         seg_setup(VCPU_SREG_ES);
4945         seg_setup(VCPU_SREG_FS);
4946         seg_setup(VCPU_SREG_GS);
4947         seg_setup(VCPU_SREG_SS);
4948
4949         vmcs_write16(GUEST_TR_SELECTOR, 0);
4950         vmcs_writel(GUEST_TR_BASE, 0);
4951         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4952         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4953
4954         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4955         vmcs_writel(GUEST_LDTR_BASE, 0);
4956         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4957         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4958
4959         if (!init_event) {
4960                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4961                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4962                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4963                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4964         }
4965
4966         vmcs_writel(GUEST_RFLAGS, 0x02);
4967         kvm_rip_write(vcpu, 0xfff0);
4968
4969         vmcs_writel(GUEST_GDTR_BASE, 0);
4970         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4971
4972         vmcs_writel(GUEST_IDTR_BASE, 0);
4973         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4974
4975         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4976         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4977         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4978
4979         setup_msrs(vmx);
4980
4981         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4982
4983         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4984                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4985                 if (cpu_need_tpr_shadow(vcpu))
4986                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4987                                      __pa(vcpu->arch.apic->regs));
4988                 vmcs_write32(TPR_THRESHOLD, 0);
4989         }
4990
4991         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4992
4993         if (kvm_vcpu_apicv_active(vcpu))
4994                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4995
4996         if (vmx->vpid != 0)
4997                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4998
4999         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5000         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5001         vmx->vcpu.arch.cr0 = cr0;
5002         vmx_set_cr4(vcpu, 0);
5003         vmx_set_efer(vcpu, 0);
5004         vmx_fpu_activate(vcpu);
5005         update_exception_bitmap(vcpu);
5006
5007         vpid_sync_context(vmx->vpid);
5008 }
5009
5010 /*
5011  * In nested virtualization, check if L1 asked to exit on external interrupts.
5012  * For most existing hypervisors, this will always return true.
5013  */
5014 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5015 {
5016         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5017                 PIN_BASED_EXT_INTR_MASK;
5018 }
5019
5020 /*
5021  * In nested virtualization, check if L1 has set
5022  * VM_EXIT_ACK_INTR_ON_EXIT
5023  */
5024 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5025 {
5026         return get_vmcs12(vcpu)->vm_exit_controls &
5027                 VM_EXIT_ACK_INTR_ON_EXIT;
5028 }
5029
5030 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5031 {
5032         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5033                 PIN_BASED_NMI_EXITING;
5034 }
5035
5036 static void enable_irq_window(struct kvm_vcpu *vcpu)
5037 {
5038         u32 cpu_based_vm_exec_control;
5039
5040         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5041         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5042         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5043 }
5044
5045 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5046 {
5047         u32 cpu_based_vm_exec_control;
5048
5049         if (!cpu_has_virtual_nmis() ||
5050             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5051                 enable_irq_window(vcpu);
5052                 return;
5053         }
5054
5055         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5056         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5057         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5058 }
5059
5060 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5061 {
5062         struct vcpu_vmx *vmx = to_vmx(vcpu);
5063         uint32_t intr;
5064         int irq = vcpu->arch.interrupt.nr;
5065
5066         trace_kvm_inj_virq(irq);
5067
5068         ++vcpu->stat.irq_injections;
5069         if (vmx->rmode.vm86_active) {
5070                 int inc_eip = 0;
5071                 if (vcpu->arch.interrupt.soft)
5072                         inc_eip = vcpu->arch.event_exit_inst_len;
5073                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5074                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5075                 return;
5076         }
5077         intr = irq | INTR_INFO_VALID_MASK;
5078         if (vcpu->arch.interrupt.soft) {
5079                 intr |= INTR_TYPE_SOFT_INTR;
5080                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5081                              vmx->vcpu.arch.event_exit_inst_len);
5082         } else
5083                 intr |= INTR_TYPE_EXT_INTR;
5084         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5085 }
5086
5087 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5088 {
5089         struct vcpu_vmx *vmx = to_vmx(vcpu);
5090
5091         if (is_guest_mode(vcpu))
5092                 return;
5093
5094         if (!cpu_has_virtual_nmis()) {
5095                 /*
5096                  * Tracking the NMI-blocked state in software is built upon
5097                  * finding the next open IRQ window. This, in turn, depends on
5098                  * well-behaving guests: They have to keep IRQs disabled at
5099                  * least as long as the NMI handler runs. Otherwise we may
5100                  * cause NMI nesting, maybe breaking the guest. But as this is
5101                  * highly unlikely, we can live with the residual risk.
5102                  */
5103                 vmx->soft_vnmi_blocked = 1;
5104                 vmx->vnmi_blocked_time = 0;
5105         }
5106
5107         ++vcpu->stat.nmi_injections;
5108         vmx->nmi_known_unmasked = false;
5109         if (vmx->rmode.vm86_active) {
5110                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5111                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5112                 return;
5113         }
5114         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5115                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5116 }
5117
5118 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5119 {
5120         if (!cpu_has_virtual_nmis())
5121                 return to_vmx(vcpu)->soft_vnmi_blocked;
5122         if (to_vmx(vcpu)->nmi_known_unmasked)
5123                 return false;
5124         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5125 }
5126
5127 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5128 {
5129         struct vcpu_vmx *vmx = to_vmx(vcpu);
5130
5131         if (!cpu_has_virtual_nmis()) {
5132                 if (vmx->soft_vnmi_blocked != masked) {
5133                         vmx->soft_vnmi_blocked = masked;
5134                         vmx->vnmi_blocked_time = 0;
5135                 }
5136         } else {
5137                 vmx->nmi_known_unmasked = !masked;
5138                 if (masked)
5139                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5140                                       GUEST_INTR_STATE_NMI);
5141                 else
5142                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5143                                         GUEST_INTR_STATE_NMI);
5144         }
5145 }
5146
5147 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5148 {
5149         if (to_vmx(vcpu)->nested.nested_run_pending)
5150                 return 0;
5151
5152         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5153                 return 0;
5154
5155         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5156                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5157                    | GUEST_INTR_STATE_NMI));
5158 }
5159
5160 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5161 {
5162         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5163                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5164                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5165                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5166 }
5167
5168 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5169 {
5170         int ret;
5171
5172         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5173                                     PAGE_SIZE * 3);
5174         if (ret)
5175                 return ret;
5176         kvm->arch.tss_addr = addr;
5177         return init_rmode_tss(kvm);
5178 }
5179
5180 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5181 {
5182         switch (vec) {
5183         case BP_VECTOR:
5184                 /*
5185                  * Update instruction length as we may reinject the exception
5186                  * from user space while in guest debugging mode.
5187                  */
5188                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5189                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5190                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5191                         return false;
5192                 /* fall through */
5193         case DB_VECTOR:
5194                 if (vcpu->guest_debug &
5195                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5196                         return false;
5197                 /* fall through */
5198         case DE_VECTOR:
5199         case OF_VECTOR:
5200         case BR_VECTOR:
5201         case UD_VECTOR:
5202         case DF_VECTOR:
5203         case SS_VECTOR:
5204         case GP_VECTOR:
5205         case MF_VECTOR:
5206                 return true;
5207         break;
5208         }
5209         return false;
5210 }
5211
5212 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5213                                   int vec, u32 err_code)
5214 {
5215         /*
5216          * Instruction with address size override prefix opcode 0x67
5217          * Cause the #SS fault with 0 error code in VM86 mode.
5218          */
5219         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5220                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5221                         if (vcpu->arch.halt_request) {
5222                                 vcpu->arch.halt_request = 0;
5223                                 return kvm_vcpu_halt(vcpu);
5224                         }
5225                         return 1;
5226                 }
5227                 return 0;
5228         }
5229
5230         /*
5231          * Forward all other exceptions that are valid in real mode.
5232          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5233          *        the required debugging infrastructure rework.
5234          */
5235         kvm_queue_exception(vcpu, vec);
5236         return 1;
5237 }
5238
5239 /*
5240  * Trigger machine check on the host. We assume all the MSRs are already set up
5241  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5242  * We pass a fake environment to the machine check handler because we want
5243  * the guest to be always treated like user space, no matter what context
5244  * it used internally.
5245  */
5246 static void kvm_machine_check(void)
5247 {
5248 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5249         struct pt_regs regs = {
5250                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5251                 .flags = X86_EFLAGS_IF,
5252         };
5253
5254         do_machine_check(&regs, 0);
5255 #endif
5256 }
5257
5258 static int handle_machine_check(struct kvm_vcpu *vcpu)
5259 {
5260         /* already handled by vcpu_run */
5261         return 1;
5262 }
5263
5264 static int handle_exception(struct kvm_vcpu *vcpu)
5265 {
5266         struct vcpu_vmx *vmx = to_vmx(vcpu);
5267         struct kvm_run *kvm_run = vcpu->run;
5268         u32 intr_info, ex_no, error_code;
5269         unsigned long cr2, rip, dr6;
5270         u32 vect_info;
5271         enum emulation_result er;
5272
5273         vect_info = vmx->idt_vectoring_info;
5274         intr_info = vmx->exit_intr_info;
5275
5276         if (is_machine_check(intr_info))
5277                 return handle_machine_check(vcpu);
5278
5279         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5280                 return 1;  /* already handled by vmx_vcpu_run() */
5281
5282         if (is_no_device(intr_info)) {
5283                 vmx_fpu_activate(vcpu);
5284                 return 1;
5285         }
5286
5287         if (is_invalid_opcode(intr_info)) {
5288                 if (is_guest_mode(vcpu)) {
5289                         kvm_queue_exception(vcpu, UD_VECTOR);
5290                         return 1;
5291                 }
5292                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5293                 if (er != EMULATE_DONE)
5294                         kvm_queue_exception(vcpu, UD_VECTOR);
5295                 return 1;
5296         }
5297
5298         error_code = 0;
5299         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5300                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5301
5302         /*
5303          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5304          * MMIO, it is better to report an internal error.
5305          * See the comments in vmx_handle_exit.
5306          */
5307         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5308             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5309                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5310                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5311                 vcpu->run->internal.ndata = 3;
5312                 vcpu->run->internal.data[0] = vect_info;
5313                 vcpu->run->internal.data[1] = intr_info;
5314                 vcpu->run->internal.data[2] = error_code;
5315                 return 0;
5316         }
5317
5318         if (is_page_fault(intr_info)) {
5319                 /* EPT won't cause page fault directly */
5320                 BUG_ON(enable_ept);
5321                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5322                 trace_kvm_page_fault(cr2, error_code);
5323
5324                 if (kvm_event_needs_reinjection(vcpu))
5325                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5326                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5327         }
5328
5329         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5330
5331         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5332                 return handle_rmode_exception(vcpu, ex_no, error_code);
5333
5334         switch (ex_no) {
5335         case AC_VECTOR:
5336                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5337                 return 1;
5338         case DB_VECTOR:
5339                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5340                 if (!(vcpu->guest_debug &
5341                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5342                         vcpu->arch.dr6 &= ~15;
5343                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5344                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5345                                 skip_emulated_instruction(vcpu);
5346
5347                         kvm_queue_exception(vcpu, DB_VECTOR);
5348                         return 1;
5349                 }
5350                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5351                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5352                 /* fall through */
5353         case BP_VECTOR:
5354                 /*
5355                  * Update instruction length as we may reinject #BP from
5356                  * user space while in guest debugging mode. Reading it for
5357                  * #DB as well causes no harm, it is not used in that case.
5358                  */
5359                 vmx->vcpu.arch.event_exit_inst_len =
5360                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5361                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5362                 rip = kvm_rip_read(vcpu);
5363                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5364                 kvm_run->debug.arch.exception = ex_no;
5365                 break;
5366         default:
5367                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5368                 kvm_run->ex.exception = ex_no;
5369                 kvm_run->ex.error_code = error_code;
5370                 break;
5371         }
5372         return 0;
5373 }
5374
5375 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5376 {
5377         ++vcpu->stat.irq_exits;
5378         return 1;
5379 }
5380
5381 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5382 {
5383         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5384         return 0;
5385 }
5386
5387 static int handle_io(struct kvm_vcpu *vcpu)
5388 {
5389         unsigned long exit_qualification;
5390         int size, in, string;
5391         unsigned port;
5392
5393         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5394         string = (exit_qualification & 16) != 0;
5395         in = (exit_qualification & 8) != 0;
5396
5397         ++vcpu->stat.io_exits;
5398
5399         if (string || in)
5400                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5401
5402         port = exit_qualification >> 16;
5403         size = (exit_qualification & 7) + 1;
5404         skip_emulated_instruction(vcpu);
5405
5406         return kvm_fast_pio_out(vcpu, size, port);
5407 }
5408
5409 static void
5410 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5411 {
5412         /*
5413          * Patch in the VMCALL instruction:
5414          */
5415         hypercall[0] = 0x0f;
5416         hypercall[1] = 0x01;
5417         hypercall[2] = 0xc1;
5418 }
5419
5420 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5421 {
5422         unsigned long always_on = VMXON_CR0_ALWAYSON;
5423         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5424
5425         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5426                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5427             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5428                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5429         return (val & always_on) == always_on;
5430 }
5431
5432 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5433 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5434 {
5435         if (is_guest_mode(vcpu)) {
5436                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5437                 unsigned long orig_val = val;
5438
5439                 /*
5440                  * We get here when L2 changed cr0 in a way that did not change
5441                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5442                  * but did change L0 shadowed bits. So we first calculate the
5443                  * effective cr0 value that L1 would like to write into the
5444                  * hardware. It consists of the L2-owned bits from the new
5445                  * value combined with the L1-owned bits from L1's guest_cr0.
5446                  */
5447                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5448                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5449
5450                 if (!nested_cr0_valid(vcpu, val))
5451                         return 1;
5452
5453                 if (kvm_set_cr0(vcpu, val))
5454                         return 1;
5455                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5456                 return 0;
5457         } else {
5458                 if (to_vmx(vcpu)->nested.vmxon &&
5459                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5460                         return 1;
5461                 return kvm_set_cr0(vcpu, val);
5462         }
5463 }
5464
5465 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5466 {
5467         if (is_guest_mode(vcpu)) {
5468                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5469                 unsigned long orig_val = val;
5470
5471                 /* analogously to handle_set_cr0 */
5472                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5473                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5474                 if (kvm_set_cr4(vcpu, val))
5475                         return 1;
5476                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5477                 return 0;
5478         } else
5479                 return kvm_set_cr4(vcpu, val);
5480 }
5481
5482 /* called to set cr0 as approriate for clts instruction exit. */
5483 static void handle_clts(struct kvm_vcpu *vcpu)
5484 {
5485         if (is_guest_mode(vcpu)) {
5486                 /*
5487                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5488                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5489                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5490                  */
5491                 vmcs_writel(CR0_READ_SHADOW,
5492                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5493                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5494         } else
5495                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5496 }
5497
5498 static int handle_cr(struct kvm_vcpu *vcpu)
5499 {
5500         unsigned long exit_qualification, val;
5501         int cr;
5502         int reg;
5503         int err;
5504
5505         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5506         cr = exit_qualification & 15;
5507         reg = (exit_qualification >> 8) & 15;
5508         switch ((exit_qualification >> 4) & 3) {
5509         case 0: /* mov to cr */
5510                 val = kvm_register_readl(vcpu, reg);
5511                 trace_kvm_cr_write(cr, val);
5512                 switch (cr) {
5513                 case 0:
5514                         err = handle_set_cr0(vcpu, val);
5515                         kvm_complete_insn_gp(vcpu, err);
5516                         return 1;
5517                 case 3:
5518                         err = kvm_set_cr3(vcpu, val);
5519                         kvm_complete_insn_gp(vcpu, err);
5520                         return 1;
5521                 case 4:
5522                         err = handle_set_cr4(vcpu, val);
5523                         kvm_complete_insn_gp(vcpu, err);
5524                         return 1;
5525                 case 8: {
5526                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5527                                 u8 cr8 = (u8)val;
5528                                 err = kvm_set_cr8(vcpu, cr8);
5529                                 kvm_complete_insn_gp(vcpu, err);
5530                                 if (lapic_in_kernel(vcpu))
5531                                         return 1;
5532                                 if (cr8_prev <= cr8)
5533                                         return 1;
5534                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5535                                 return 0;
5536                         }
5537                 }
5538                 break;
5539         case 2: /* clts */
5540                 handle_clts(vcpu);
5541                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5542                 skip_emulated_instruction(vcpu);
5543                 vmx_fpu_activate(vcpu);
5544                 return 1;
5545         case 1: /*mov from cr*/
5546                 switch (cr) {
5547                 case 3:
5548                         val = kvm_read_cr3(vcpu);
5549                         kvm_register_write(vcpu, reg, val);
5550                         trace_kvm_cr_read(cr, val);
5551                         skip_emulated_instruction(vcpu);
5552                         return 1;
5553                 case 8:
5554                         val = kvm_get_cr8(vcpu);
5555                         kvm_register_write(vcpu, reg, val);
5556                         trace_kvm_cr_read(cr, val);
5557                         skip_emulated_instruction(vcpu);
5558                         return 1;
5559                 }
5560                 break;
5561         case 3: /* lmsw */
5562                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5563                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5564                 kvm_lmsw(vcpu, val);
5565
5566                 skip_emulated_instruction(vcpu);
5567                 return 1;
5568         default:
5569                 break;
5570         }
5571         vcpu->run->exit_reason = 0;
5572         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5573                (int)(exit_qualification >> 4) & 3, cr);
5574         return 0;
5575 }
5576
5577 static int handle_dr(struct kvm_vcpu *vcpu)
5578 {
5579         unsigned long exit_qualification;
5580         int dr, dr7, reg;
5581
5582         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5583         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5584
5585         /* First, if DR does not exist, trigger UD */
5586         if (!kvm_require_dr(vcpu, dr))
5587                 return 1;
5588
5589         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5590         if (!kvm_require_cpl(vcpu, 0))
5591                 return 1;
5592         dr7 = vmcs_readl(GUEST_DR7);
5593         if (dr7 & DR7_GD) {
5594                 /*
5595                  * As the vm-exit takes precedence over the debug trap, we
5596                  * need to emulate the latter, either for the host or the
5597                  * guest debugging itself.
5598                  */
5599                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5600                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5601                         vcpu->run->debug.arch.dr7 = dr7;
5602                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5603                         vcpu->run->debug.arch.exception = DB_VECTOR;
5604                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5605                         return 0;
5606                 } else {
5607                         vcpu->arch.dr6 &= ~15;
5608                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5609                         kvm_queue_exception(vcpu, DB_VECTOR);
5610                         return 1;
5611                 }
5612         }
5613
5614         if (vcpu->guest_debug == 0) {
5615                 u32 cpu_based_vm_exec_control;
5616
5617                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5618                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5619                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5620
5621                 /*
5622                  * No more DR vmexits; force a reload of the debug registers
5623                  * and reenter on this instruction.  The next vmexit will
5624                  * retrieve the full state of the debug registers.
5625                  */
5626                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5627                 return 1;
5628         }
5629
5630         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5631         if (exit_qualification & TYPE_MOV_FROM_DR) {
5632                 unsigned long val;
5633
5634                 if (kvm_get_dr(vcpu, dr, &val))
5635                         return 1;
5636                 kvm_register_write(vcpu, reg, val);
5637         } else
5638                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5639                         return 1;
5640
5641         skip_emulated_instruction(vcpu);
5642         return 1;
5643 }
5644
5645 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5646 {
5647         return vcpu->arch.dr6;
5648 }
5649
5650 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5651 {
5652 }
5653
5654 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5655 {
5656         u32 cpu_based_vm_exec_control;
5657
5658         get_debugreg(vcpu->arch.db[0], 0);
5659         get_debugreg(vcpu->arch.db[1], 1);
5660         get_debugreg(vcpu->arch.db[2], 2);
5661         get_debugreg(vcpu->arch.db[3], 3);
5662         get_debugreg(vcpu->arch.dr6, 6);
5663         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5664
5665         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5666
5667         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5668         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5669         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5670 }
5671
5672 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5673 {
5674         vmcs_writel(GUEST_DR7, val);
5675 }
5676
5677 static int handle_cpuid(struct kvm_vcpu *vcpu)
5678 {
5679         kvm_emulate_cpuid(vcpu);
5680         return 1;
5681 }
5682
5683 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5684 {
5685         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5686         struct msr_data msr_info;
5687
5688         msr_info.index = ecx;
5689         msr_info.host_initiated = false;
5690         if (vmx_get_msr(vcpu, &msr_info)) {
5691                 trace_kvm_msr_read_ex(ecx);
5692                 kvm_inject_gp(vcpu, 0);
5693                 return 1;
5694         }
5695
5696         trace_kvm_msr_read(ecx, msr_info.data);
5697
5698         /* FIXME: handling of bits 32:63 of rax, rdx */
5699         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5700         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5701         skip_emulated_instruction(vcpu);
5702         return 1;
5703 }
5704
5705 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5706 {
5707         struct msr_data msr;
5708         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5709         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5710                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5711
5712         msr.data = data;
5713         msr.index = ecx;
5714         msr.host_initiated = false;
5715         if (kvm_set_msr(vcpu, &msr) != 0) {
5716                 trace_kvm_msr_write_ex(ecx, data);
5717                 kvm_inject_gp(vcpu, 0);
5718                 return 1;
5719         }
5720
5721         trace_kvm_msr_write(ecx, data);
5722         skip_emulated_instruction(vcpu);
5723         return 1;
5724 }
5725
5726 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5727 {
5728         kvm_make_request(KVM_REQ_EVENT, vcpu);
5729         return 1;
5730 }
5731
5732 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5733 {
5734         u32 cpu_based_vm_exec_control;
5735
5736         /* clear pending irq */
5737         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5738         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5739         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5740
5741         kvm_make_request(KVM_REQ_EVENT, vcpu);
5742
5743         ++vcpu->stat.irq_window_exits;
5744         return 1;
5745 }
5746
5747 static int handle_halt(struct kvm_vcpu *vcpu)
5748 {
5749         return kvm_emulate_halt(vcpu);
5750 }
5751
5752 static int handle_vmcall(struct kvm_vcpu *vcpu)
5753 {
5754         kvm_emulate_hypercall(vcpu);
5755         return 1;
5756 }
5757
5758 static int handle_invd(struct kvm_vcpu *vcpu)
5759 {
5760         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5761 }
5762
5763 static int handle_invlpg(struct kvm_vcpu *vcpu)
5764 {
5765         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5766
5767         kvm_mmu_invlpg(vcpu, exit_qualification);
5768         skip_emulated_instruction(vcpu);
5769         return 1;
5770 }
5771
5772 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5773 {
5774         int err;
5775
5776         err = kvm_rdpmc(vcpu);
5777         kvm_complete_insn_gp(vcpu, err);
5778
5779         return 1;
5780 }
5781
5782 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5783 {
5784         kvm_emulate_wbinvd(vcpu);
5785         return 1;
5786 }
5787
5788 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5789 {
5790         u64 new_bv = kvm_read_edx_eax(vcpu);
5791         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5792
5793         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5794                 skip_emulated_instruction(vcpu);
5795         return 1;
5796 }
5797
5798 static int handle_xsaves(struct kvm_vcpu *vcpu)
5799 {
5800         skip_emulated_instruction(vcpu);
5801         WARN(1, "this should never happen\n");
5802         return 1;
5803 }
5804
5805 static int handle_xrstors(struct kvm_vcpu *vcpu)
5806 {
5807         skip_emulated_instruction(vcpu);
5808         WARN(1, "this should never happen\n");
5809         return 1;
5810 }
5811
5812 static int handle_apic_access(struct kvm_vcpu *vcpu)
5813 {
5814         if (likely(fasteoi)) {
5815                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5816                 int access_type, offset;
5817
5818                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5819                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5820                 /*
5821                  * Sane guest uses MOV to write EOI, with written value
5822                  * not cared. So make a short-circuit here by avoiding
5823                  * heavy instruction emulation.
5824                  */
5825                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5826                     (offset == APIC_EOI)) {
5827                         kvm_lapic_set_eoi(vcpu);
5828                         skip_emulated_instruction(vcpu);
5829                         return 1;
5830                 }
5831         }
5832         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5833 }
5834
5835 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5836 {
5837         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5838         int vector = exit_qualification & 0xff;
5839
5840         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5841         kvm_apic_set_eoi_accelerated(vcpu, vector);
5842         return 1;
5843 }
5844
5845 static int handle_apic_write(struct kvm_vcpu *vcpu)
5846 {
5847         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5848         u32 offset = exit_qualification & 0xfff;
5849
5850         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5851         kvm_apic_write_nodecode(vcpu, offset);
5852         return 1;
5853 }
5854
5855 static int handle_task_switch(struct kvm_vcpu *vcpu)
5856 {
5857         struct vcpu_vmx *vmx = to_vmx(vcpu);
5858         unsigned long exit_qualification;
5859         bool has_error_code = false;
5860         u32 error_code = 0;
5861         u16 tss_selector;
5862         int reason, type, idt_v, idt_index;
5863
5864         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5865         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5866         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5867
5868         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5869
5870         reason = (u32)exit_qualification >> 30;
5871         if (reason == TASK_SWITCH_GATE && idt_v) {
5872                 switch (type) {
5873                 case INTR_TYPE_NMI_INTR:
5874                         vcpu->arch.nmi_injected = false;
5875                         vmx_set_nmi_mask(vcpu, true);
5876                         break;
5877                 case INTR_TYPE_EXT_INTR:
5878                 case INTR_TYPE_SOFT_INTR:
5879                         kvm_clear_interrupt_queue(vcpu);
5880                         break;
5881                 case INTR_TYPE_HARD_EXCEPTION:
5882                         if (vmx->idt_vectoring_info &
5883                             VECTORING_INFO_DELIVER_CODE_MASK) {
5884                                 has_error_code = true;
5885                                 error_code =
5886                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5887                         }
5888                         /* fall through */
5889                 case INTR_TYPE_SOFT_EXCEPTION:
5890                         kvm_clear_exception_queue(vcpu);
5891                         break;
5892                 default:
5893                         break;
5894                 }
5895         }
5896         tss_selector = exit_qualification;
5897
5898         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5899                        type != INTR_TYPE_EXT_INTR &&
5900                        type != INTR_TYPE_NMI_INTR))
5901                 skip_emulated_instruction(vcpu);
5902
5903         if (kvm_task_switch(vcpu, tss_selector,
5904                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5905                             has_error_code, error_code) == EMULATE_FAIL) {
5906                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5907                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5908                 vcpu->run->internal.ndata = 0;
5909                 return 0;
5910         }
5911
5912         /*
5913          * TODO: What about debug traps on tss switch?
5914          *       Are we supposed to inject them and update dr6?
5915          */
5916
5917         return 1;
5918 }
5919
5920 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5921 {
5922         unsigned long exit_qualification;
5923         gpa_t gpa;
5924         u32 error_code;
5925         int gla_validity;
5926
5927         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5928
5929         gla_validity = (exit_qualification >> 7) & 0x3;
5930         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5931                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5932                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5933                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5934                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5935                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5936                         (long unsigned int)exit_qualification);
5937                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5938                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5939                 return 0;
5940         }
5941
5942         /*
5943          * EPT violation happened while executing iret from NMI,
5944          * "blocked by NMI" bit has to be set before next VM entry.
5945          * There are errata that may cause this bit to not be set:
5946          * AAK134, BY25.
5947          */
5948         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5949                         cpu_has_virtual_nmis() &&
5950                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5951                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5952
5953         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5954         trace_kvm_page_fault(gpa, exit_qualification);
5955
5956         /* It is a write fault? */
5957         error_code = exit_qualification & PFERR_WRITE_MASK;
5958         /* It is a fetch fault? */
5959         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5960         /* ept page table is present? */
5961         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5962
5963         vcpu->arch.exit_qualification = exit_qualification;
5964
5965         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5966 }
5967
5968 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5969 {
5970         int ret;
5971         gpa_t gpa;
5972
5973         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5974         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5975                 skip_emulated_instruction(vcpu);
5976                 trace_kvm_fast_mmio(gpa);
5977                 return 1;
5978         }
5979
5980         ret = handle_mmio_page_fault(vcpu, gpa, true);
5981         if (likely(ret == RET_MMIO_PF_EMULATE))
5982                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5983                                               EMULATE_DONE;
5984
5985         if (unlikely(ret == RET_MMIO_PF_INVALID))
5986                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5987
5988         if (unlikely(ret == RET_MMIO_PF_RETRY))
5989                 return 1;
5990
5991         /* It is the real ept misconfig */
5992         WARN_ON(1);
5993
5994         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5995         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5996
5997         return 0;
5998 }
5999
6000 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6001 {
6002         u32 cpu_based_vm_exec_control;
6003
6004         /* clear pending NMI */
6005         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6006         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6007         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6008         ++vcpu->stat.nmi_window_exits;
6009         kvm_make_request(KVM_REQ_EVENT, vcpu);
6010
6011         return 1;
6012 }
6013
6014 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6015 {
6016         struct vcpu_vmx *vmx = to_vmx(vcpu);
6017         enum emulation_result err = EMULATE_DONE;
6018         int ret = 1;
6019         u32 cpu_exec_ctrl;
6020         bool intr_window_requested;
6021         unsigned count = 130;
6022
6023         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6024         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6025
6026         while (vmx->emulation_required && count-- != 0) {
6027                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6028                         return handle_interrupt_window(&vmx->vcpu);
6029
6030                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6031                         return 1;
6032
6033                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6034
6035                 if (err == EMULATE_USER_EXIT) {
6036                         ++vcpu->stat.mmio_exits;
6037                         ret = 0;
6038                         goto out;
6039                 }
6040
6041                 if (err != EMULATE_DONE) {
6042                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6043                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6044                         vcpu->run->internal.ndata = 0;
6045                         return 0;
6046                 }
6047
6048                 if (vcpu->arch.halt_request) {
6049                         vcpu->arch.halt_request = 0;
6050                         ret = kvm_vcpu_halt(vcpu);
6051                         goto out;
6052                 }
6053
6054                 if (signal_pending(current))
6055                         goto out;
6056                 if (need_resched())
6057                         schedule();
6058         }
6059
6060 out:
6061         return ret;
6062 }
6063
6064 static int __grow_ple_window(int val)
6065 {
6066         if (ple_window_grow < 1)
6067                 return ple_window;
6068
6069         val = min(val, ple_window_actual_max);
6070
6071         if (ple_window_grow < ple_window)
6072                 val *= ple_window_grow;
6073         else
6074                 val += ple_window_grow;
6075
6076         return val;
6077 }
6078
6079 static int __shrink_ple_window(int val, int modifier, int minimum)
6080 {
6081         if (modifier < 1)
6082                 return ple_window;
6083
6084         if (modifier < ple_window)
6085                 val /= modifier;
6086         else
6087                 val -= modifier;
6088
6089         return max(val, minimum);
6090 }
6091
6092 static void grow_ple_window(struct kvm_vcpu *vcpu)
6093 {
6094         struct vcpu_vmx *vmx = to_vmx(vcpu);
6095         int old = vmx->ple_window;
6096
6097         vmx->ple_window = __grow_ple_window(old);
6098
6099         if (vmx->ple_window != old)
6100                 vmx->ple_window_dirty = true;
6101
6102         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6103 }
6104
6105 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6106 {
6107         struct vcpu_vmx *vmx = to_vmx(vcpu);
6108         int old = vmx->ple_window;
6109
6110         vmx->ple_window = __shrink_ple_window(old,
6111                                               ple_window_shrink, ple_window);
6112
6113         if (vmx->ple_window != old)
6114                 vmx->ple_window_dirty = true;
6115
6116         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6117 }
6118
6119 /*
6120  * ple_window_actual_max is computed to be one grow_ple_window() below
6121  * ple_window_max. (See __grow_ple_window for the reason.)
6122  * This prevents overflows, because ple_window_max is int.
6123  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6124  * this process.
6125  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6126  */
6127 static void update_ple_window_actual_max(void)
6128 {
6129         ple_window_actual_max =
6130                         __shrink_ple_window(max(ple_window_max, ple_window),
6131                                             ple_window_grow, INT_MIN);
6132 }
6133
6134 /*
6135  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6136  */
6137 static void wakeup_handler(void)
6138 {
6139         struct kvm_vcpu *vcpu;
6140         int cpu = smp_processor_id();
6141
6142         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6143         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6144                         blocked_vcpu_list) {
6145                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6146
6147                 if (pi_test_on(pi_desc) == 1)
6148                         kvm_vcpu_kick(vcpu);
6149         }
6150         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6151 }
6152
6153 static __init int hardware_setup(void)
6154 {
6155         int r = -ENOMEM, i, msr;
6156
6157         rdmsrl_safe(MSR_EFER, &host_efer);
6158
6159         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6160                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6161
6162         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6163         if (!vmx_io_bitmap_a)
6164                 return r;
6165
6166         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6167         if (!vmx_io_bitmap_b)
6168                 goto out;
6169
6170         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6171         if (!vmx_msr_bitmap_legacy)
6172                 goto out1;
6173
6174         vmx_msr_bitmap_legacy_x2apic =
6175                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6176         if (!vmx_msr_bitmap_legacy_x2apic)
6177                 goto out2;
6178
6179         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6180         if (!vmx_msr_bitmap_longmode)
6181                 goto out3;
6182
6183         vmx_msr_bitmap_longmode_x2apic =
6184                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6185         if (!vmx_msr_bitmap_longmode_x2apic)
6186                 goto out4;
6187
6188         if (nested) {
6189                 vmx_msr_bitmap_nested =
6190                         (unsigned long *)__get_free_page(GFP_KERNEL);
6191                 if (!vmx_msr_bitmap_nested)
6192                         goto out5;
6193         }
6194
6195         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6196         if (!vmx_vmread_bitmap)
6197                 goto out6;
6198
6199         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6200         if (!vmx_vmwrite_bitmap)
6201                 goto out7;
6202
6203         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6204         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6205
6206         /*
6207          * Allow direct access to the PC debug port (it is often used for I/O
6208          * delays, but the vmexits simply slow things down).
6209          */
6210         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6211         clear_bit(0x80, vmx_io_bitmap_a);
6212
6213         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6214
6215         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6216         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6217         if (nested)
6218                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6219
6220         if (setup_vmcs_config(&vmcs_config) < 0) {
6221                 r = -EIO;
6222                 goto out8;
6223         }
6224
6225         if (boot_cpu_has(X86_FEATURE_NX))
6226                 kvm_enable_efer_bits(EFER_NX);
6227
6228         if (!cpu_has_vmx_vpid())
6229                 enable_vpid = 0;
6230         if (!cpu_has_vmx_shadow_vmcs())
6231                 enable_shadow_vmcs = 0;
6232         if (enable_shadow_vmcs)
6233                 init_vmcs_shadow_fields();
6234
6235         if (!cpu_has_vmx_ept() ||
6236             !cpu_has_vmx_ept_4levels()) {
6237                 enable_ept = 0;
6238                 enable_unrestricted_guest = 0;
6239                 enable_ept_ad_bits = 0;
6240         }
6241
6242         if (!cpu_has_vmx_ept_ad_bits())
6243                 enable_ept_ad_bits = 0;
6244
6245         if (!cpu_has_vmx_unrestricted_guest())
6246                 enable_unrestricted_guest = 0;
6247
6248         if (!cpu_has_vmx_flexpriority())
6249                 flexpriority_enabled = 0;
6250
6251         /*
6252          * set_apic_access_page_addr() is used to reload apic access
6253          * page upon invalidation.  No need to do anything if not
6254          * using the APIC_ACCESS_ADDR VMCS field.
6255          */
6256         if (!flexpriority_enabled)
6257                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6258
6259         if (!cpu_has_vmx_tpr_shadow())
6260                 kvm_x86_ops->update_cr8_intercept = NULL;
6261
6262         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6263                 kvm_disable_largepages();
6264
6265         if (!cpu_has_vmx_ple())
6266                 ple_gap = 0;
6267
6268         if (!cpu_has_vmx_apicv())
6269                 enable_apicv = 0;
6270
6271         if (cpu_has_vmx_tsc_scaling()) {
6272                 kvm_has_tsc_control = true;
6273                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6274                 kvm_tsc_scaling_ratio_frac_bits = 48;
6275         }
6276
6277         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6278         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6279         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6280         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6281         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6282         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6283         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6284
6285         memcpy(vmx_msr_bitmap_legacy_x2apic,
6286                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6287         memcpy(vmx_msr_bitmap_longmode_x2apic,
6288                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6289
6290         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6291
6292         if (enable_apicv) {
6293                 for (msr = 0x800; msr <= 0x8ff; msr++)
6294                         vmx_disable_intercept_msr_read_x2apic(msr);
6295
6296                 /* According SDM, in x2apic mode, the whole id reg is used.
6297                  * But in KVM, it only use the highest eight bits. Need to
6298                  * intercept it */
6299                 vmx_enable_intercept_msr_read_x2apic(0x802);
6300                 /* TMCCT */
6301                 vmx_enable_intercept_msr_read_x2apic(0x839);
6302                 /* TPR */
6303                 vmx_disable_intercept_msr_write_x2apic(0x808);
6304                 /* EOI */
6305                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6306                 /* SELF-IPI */
6307                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6308         }
6309
6310         if (enable_ept) {
6311                 kvm_mmu_set_mask_ptes(0ull,
6312                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6313                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6314                         0ull, VMX_EPT_EXECUTABLE_MASK);
6315                 ept_set_mmio_spte_mask();
6316                 kvm_enable_tdp();
6317         } else
6318                 kvm_disable_tdp();
6319
6320         update_ple_window_actual_max();
6321
6322         /*
6323          * Only enable PML when hardware supports PML feature, and both EPT
6324          * and EPT A/D bit features are enabled -- PML depends on them to work.
6325          */
6326         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6327                 enable_pml = 0;
6328
6329         if (!enable_pml) {
6330                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6331                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6332                 kvm_x86_ops->flush_log_dirty = NULL;
6333                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6334         }
6335
6336         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6337
6338         return alloc_kvm_area();
6339
6340 out8:
6341         free_page((unsigned long)vmx_vmwrite_bitmap);
6342 out7:
6343         free_page((unsigned long)vmx_vmread_bitmap);
6344 out6:
6345         if (nested)
6346                 free_page((unsigned long)vmx_msr_bitmap_nested);
6347 out5:
6348         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6349 out4:
6350         free_page((unsigned long)vmx_msr_bitmap_longmode);
6351 out3:
6352         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6353 out2:
6354         free_page((unsigned long)vmx_msr_bitmap_legacy);
6355 out1:
6356         free_page((unsigned long)vmx_io_bitmap_b);
6357 out:
6358         free_page((unsigned long)vmx_io_bitmap_a);
6359
6360     return r;
6361 }
6362
6363 static __exit void hardware_unsetup(void)
6364 {
6365         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6366         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6367         free_page((unsigned long)vmx_msr_bitmap_legacy);
6368         free_page((unsigned long)vmx_msr_bitmap_longmode);
6369         free_page((unsigned long)vmx_io_bitmap_b);
6370         free_page((unsigned long)vmx_io_bitmap_a);
6371         free_page((unsigned long)vmx_vmwrite_bitmap);
6372         free_page((unsigned long)vmx_vmread_bitmap);
6373         if (nested)
6374                 free_page((unsigned long)vmx_msr_bitmap_nested);
6375
6376         free_kvm_area();
6377 }
6378
6379 /*
6380  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6381  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6382  */
6383 static int handle_pause(struct kvm_vcpu *vcpu)
6384 {
6385         if (ple_gap)
6386                 grow_ple_window(vcpu);
6387
6388         skip_emulated_instruction(vcpu);
6389         kvm_vcpu_on_spin(vcpu);
6390
6391         return 1;
6392 }
6393
6394 static int handle_nop(struct kvm_vcpu *vcpu)
6395 {
6396         skip_emulated_instruction(vcpu);
6397         return 1;
6398 }
6399
6400 static int handle_mwait(struct kvm_vcpu *vcpu)
6401 {
6402         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6403         return handle_nop(vcpu);
6404 }
6405
6406 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6407 {
6408         return 1;
6409 }
6410
6411 static int handle_monitor(struct kvm_vcpu *vcpu)
6412 {
6413         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6414         return handle_nop(vcpu);
6415 }
6416
6417 /*
6418  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6419  * We could reuse a single VMCS for all the L2 guests, but we also want the
6420  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6421  * allows keeping them loaded on the processor, and in the future will allow
6422  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6423  * every entry if they never change.
6424  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6425  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6426  *
6427  * The following functions allocate and free a vmcs02 in this pool.
6428  */
6429
6430 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6431 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6432 {
6433         struct vmcs02_list *item;
6434         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6435                 if (item->vmptr == vmx->nested.current_vmptr) {
6436                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6437                         return &item->vmcs02;
6438                 }
6439
6440         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6441                 /* Recycle the least recently used VMCS. */
6442                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6443                         struct vmcs02_list, list);
6444                 item->vmptr = vmx->nested.current_vmptr;
6445                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6446                 return &item->vmcs02;
6447         }
6448
6449         /* Create a new VMCS */
6450         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6451         if (!item)
6452                 return NULL;
6453         item->vmcs02.vmcs = alloc_vmcs();
6454         if (!item->vmcs02.vmcs) {
6455                 kfree(item);
6456                 return NULL;
6457         }
6458         loaded_vmcs_init(&item->vmcs02);
6459         item->vmptr = vmx->nested.current_vmptr;
6460         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6461         vmx->nested.vmcs02_num++;
6462         return &item->vmcs02;
6463 }
6464
6465 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6466 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6467 {
6468         struct vmcs02_list *item;
6469         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6470                 if (item->vmptr == vmptr) {
6471                         free_loaded_vmcs(&item->vmcs02);
6472                         list_del(&item->list);
6473                         kfree(item);
6474                         vmx->nested.vmcs02_num--;
6475                         return;
6476                 }
6477 }
6478
6479 /*
6480  * Free all VMCSs saved for this vcpu, except the one pointed by
6481  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6482  * must be &vmx->vmcs01.
6483  */
6484 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6485 {
6486         struct vmcs02_list *item, *n;
6487
6488         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6489         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6490                 /*
6491                  * Something will leak if the above WARN triggers.  Better than
6492                  * a use-after-free.
6493                  */
6494                 if (vmx->loaded_vmcs == &item->vmcs02)
6495                         continue;
6496
6497                 free_loaded_vmcs(&item->vmcs02);
6498                 list_del(&item->list);
6499                 kfree(item);
6500                 vmx->nested.vmcs02_num--;
6501         }
6502 }
6503
6504 /*
6505  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6506  * set the success or error code of an emulated VMX instruction, as specified
6507  * by Vol 2B, VMX Instruction Reference, "Conventions".
6508  */
6509 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6510 {
6511         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6512                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6513                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6514 }
6515
6516 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6517 {
6518         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6519                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6520                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6521                         | X86_EFLAGS_CF);
6522 }
6523
6524 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6525                                         u32 vm_instruction_error)
6526 {
6527         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6528                 /*
6529                  * failValid writes the error number to the current VMCS, which
6530                  * can't be done there isn't a current VMCS.
6531                  */
6532                 nested_vmx_failInvalid(vcpu);
6533                 return;
6534         }
6535         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6536                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6537                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6538                         | X86_EFLAGS_ZF);
6539         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6540         /*
6541          * We don't need to force a shadow sync because
6542          * VM_INSTRUCTION_ERROR is not shadowed
6543          */
6544 }
6545
6546 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6547 {
6548         /* TODO: not to reset guest simply here. */
6549         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6550         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6551 }
6552
6553 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6554 {
6555         struct vcpu_vmx *vmx =
6556                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6557
6558         vmx->nested.preemption_timer_expired = true;
6559         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6560         kvm_vcpu_kick(&vmx->vcpu);
6561
6562         return HRTIMER_NORESTART;
6563 }
6564
6565 /*
6566  * Decode the memory-address operand of a vmx instruction, as recorded on an
6567  * exit caused by such an instruction (run by a guest hypervisor).
6568  * On success, returns 0. When the operand is invalid, returns 1 and throws
6569  * #UD or #GP.
6570  */
6571 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6572                                  unsigned long exit_qualification,
6573                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6574 {
6575         gva_t off;
6576         bool exn;
6577         struct kvm_segment s;
6578
6579         /*
6580          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6581          * Execution", on an exit, vmx_instruction_info holds most of the
6582          * addressing components of the operand. Only the displacement part
6583          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6584          * For how an actual address is calculated from all these components,
6585          * refer to Vol. 1, "Operand Addressing".
6586          */
6587         int  scaling = vmx_instruction_info & 3;
6588         int  addr_size = (vmx_instruction_info >> 7) & 7;
6589         bool is_reg = vmx_instruction_info & (1u << 10);
6590         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6591         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6592         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6593         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6594         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6595
6596         if (is_reg) {
6597                 kvm_queue_exception(vcpu, UD_VECTOR);
6598                 return 1;
6599         }
6600
6601         /* Addr = segment_base + offset */
6602         /* offset = base + [index * scale] + displacement */
6603         off = exit_qualification; /* holds the displacement */
6604         if (base_is_valid)
6605                 off += kvm_register_read(vcpu, base_reg);
6606         if (index_is_valid)
6607                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6608         vmx_get_segment(vcpu, &s, seg_reg);
6609         *ret = s.base + off;
6610
6611         if (addr_size == 1) /* 32 bit */
6612                 *ret &= 0xffffffff;
6613
6614         /* Checks for #GP/#SS exceptions. */
6615         exn = false;
6616         if (is_protmode(vcpu)) {
6617                 /* Protected mode: apply checks for segment validity in the
6618                  * following order:
6619                  * - segment type check (#GP(0) may be thrown)
6620                  * - usability check (#GP(0)/#SS(0))
6621                  * - limit check (#GP(0)/#SS(0))
6622                  */
6623                 if (wr)
6624                         /* #GP(0) if the destination operand is located in a
6625                          * read-only data segment or any code segment.
6626                          */
6627                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6628                 else
6629                         /* #GP(0) if the source operand is located in an
6630                          * execute-only code segment
6631                          */
6632                         exn = ((s.type & 0xa) == 8);
6633         }
6634         if (exn) {
6635                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6636                 return 1;
6637         }
6638         if (is_long_mode(vcpu)) {
6639                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6640                  * non-canonical form. This is an only check for long mode.
6641                  */
6642                 exn = is_noncanonical_address(*ret);
6643         } else if (is_protmode(vcpu)) {
6644                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6645                  */
6646                 exn = (s.unusable != 0);
6647                 /* Protected mode: #GP(0)/#SS(0) if the memory
6648                  * operand is outside the segment limit.
6649                  */
6650                 exn = exn || (off + sizeof(u64) > s.limit);
6651         }
6652         if (exn) {
6653                 kvm_queue_exception_e(vcpu,
6654                                       seg_reg == VCPU_SREG_SS ?
6655                                                 SS_VECTOR : GP_VECTOR,
6656                                       0);
6657                 return 1;
6658         }
6659
6660         return 0;
6661 }
6662
6663 /*
6664  * This function performs the various checks including
6665  * - if it's 4KB aligned
6666  * - No bits beyond the physical address width are set
6667  * - Returns 0 on success or else 1
6668  * (Intel SDM Section 30.3)
6669  */
6670 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6671                                   gpa_t *vmpointer)
6672 {
6673         gva_t gva;
6674         gpa_t vmptr;
6675         struct x86_exception e;
6676         struct page *page;
6677         struct vcpu_vmx *vmx = to_vmx(vcpu);
6678         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6679
6680         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6681                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6682                 return 1;
6683
6684         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6685                                 sizeof(vmptr), &e)) {
6686                 kvm_inject_page_fault(vcpu, &e);
6687                 return 1;
6688         }
6689
6690         switch (exit_reason) {
6691         case EXIT_REASON_VMON:
6692                 /*
6693                  * SDM 3: 24.11.5
6694                  * The first 4 bytes of VMXON region contain the supported
6695                  * VMCS revision identifier
6696                  *
6697                  * Note - IA32_VMX_BASIC[48] will never be 1
6698                  * for the nested case;
6699                  * which replaces physical address width with 32
6700                  *
6701                  */
6702                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6703                         nested_vmx_failInvalid(vcpu);
6704                         skip_emulated_instruction(vcpu);
6705                         return 1;
6706                 }
6707
6708                 page = nested_get_page(vcpu, vmptr);
6709                 if (page == NULL ||
6710                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6711                         nested_vmx_failInvalid(vcpu);
6712                         kunmap(page);
6713                         skip_emulated_instruction(vcpu);
6714                         return 1;
6715                 }
6716                 kunmap(page);
6717                 vmx->nested.vmxon_ptr = vmptr;
6718                 break;
6719         case EXIT_REASON_VMCLEAR:
6720                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6721                         nested_vmx_failValid(vcpu,
6722                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6723                         skip_emulated_instruction(vcpu);
6724                         return 1;
6725                 }
6726
6727                 if (vmptr == vmx->nested.vmxon_ptr) {
6728                         nested_vmx_failValid(vcpu,
6729                                              VMXERR_VMCLEAR_VMXON_POINTER);
6730                         skip_emulated_instruction(vcpu);
6731                         return 1;
6732                 }
6733                 break;
6734         case EXIT_REASON_VMPTRLD:
6735                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6736                         nested_vmx_failValid(vcpu,
6737                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6738                         skip_emulated_instruction(vcpu);
6739                         return 1;
6740                 }
6741
6742                 if (vmptr == vmx->nested.vmxon_ptr) {
6743                         nested_vmx_failValid(vcpu,
6744                                              VMXERR_VMCLEAR_VMXON_POINTER);
6745                         skip_emulated_instruction(vcpu);
6746                         return 1;
6747                 }
6748                 break;
6749         default:
6750                 return 1; /* shouldn't happen */
6751         }
6752
6753         if (vmpointer)
6754                 *vmpointer = vmptr;
6755         return 0;
6756 }
6757
6758 /*
6759  * Emulate the VMXON instruction.
6760  * Currently, we just remember that VMX is active, and do not save or even
6761  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6762  * do not currently need to store anything in that guest-allocated memory
6763  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6764  * argument is different from the VMXON pointer (which the spec says they do).
6765  */
6766 static int handle_vmon(struct kvm_vcpu *vcpu)
6767 {
6768         struct kvm_segment cs;
6769         struct vcpu_vmx *vmx = to_vmx(vcpu);
6770         struct vmcs *shadow_vmcs;
6771         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6772                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6773
6774         /* The Intel VMX Instruction Reference lists a bunch of bits that
6775          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6776          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6777          * Otherwise, we should fail with #UD. We test these now:
6778          */
6779         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6780             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6781             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6782                 kvm_queue_exception(vcpu, UD_VECTOR);
6783                 return 1;
6784         }
6785
6786         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6787         if (is_long_mode(vcpu) && !cs.l) {
6788                 kvm_queue_exception(vcpu, UD_VECTOR);
6789                 return 1;
6790         }
6791
6792         if (vmx_get_cpl(vcpu)) {
6793                 kvm_inject_gp(vcpu, 0);
6794                 return 1;
6795         }
6796
6797         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6798                 return 1;
6799
6800         if (vmx->nested.vmxon) {
6801                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6802                 skip_emulated_instruction(vcpu);
6803                 return 1;
6804         }
6805
6806         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6807                         != VMXON_NEEDED_FEATURES) {
6808                 kvm_inject_gp(vcpu, 0);
6809                 return 1;
6810         }
6811
6812         if (enable_shadow_vmcs) {
6813                 shadow_vmcs = alloc_vmcs();
6814                 if (!shadow_vmcs)
6815                         return -ENOMEM;
6816                 /* mark vmcs as shadow */
6817                 shadow_vmcs->revision_id |= (1u << 31);
6818                 /* init shadow vmcs */
6819                 vmcs_clear(shadow_vmcs);
6820                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6821         }
6822
6823         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6824         vmx->nested.vmcs02_num = 0;
6825
6826         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6827                      HRTIMER_MODE_REL);
6828         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6829
6830         vmx->nested.vmxon = true;
6831
6832         skip_emulated_instruction(vcpu);
6833         nested_vmx_succeed(vcpu);
6834         return 1;
6835 }
6836
6837 /*
6838  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6839  * for running VMX instructions (except VMXON, whose prerequisites are
6840  * slightly different). It also specifies what exception to inject otherwise.
6841  */
6842 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6843 {
6844         struct kvm_segment cs;
6845         struct vcpu_vmx *vmx = to_vmx(vcpu);
6846
6847         if (!vmx->nested.vmxon) {
6848                 kvm_queue_exception(vcpu, UD_VECTOR);
6849                 return 0;
6850         }
6851
6852         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6853         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6854             (is_long_mode(vcpu) && !cs.l)) {
6855                 kvm_queue_exception(vcpu, UD_VECTOR);
6856                 return 0;
6857         }
6858
6859         if (vmx_get_cpl(vcpu)) {
6860                 kvm_inject_gp(vcpu, 0);
6861                 return 0;
6862         }
6863
6864         return 1;
6865 }
6866
6867 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6868 {
6869         if (vmx->nested.current_vmptr == -1ull)
6870                 return;
6871
6872         /* current_vmptr and current_vmcs12 are always set/reset together */
6873         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6874                 return;
6875
6876         if (enable_shadow_vmcs) {
6877                 /* copy to memory all shadowed fields in case
6878                    they were modified */
6879                 copy_shadow_to_vmcs12(vmx);
6880                 vmx->nested.sync_shadow_vmcs = false;
6881                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6882                                 SECONDARY_EXEC_SHADOW_VMCS);
6883                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6884         }
6885         vmx->nested.posted_intr_nv = -1;
6886         kunmap(vmx->nested.current_vmcs12_page);
6887         nested_release_page(vmx->nested.current_vmcs12_page);
6888         vmx->nested.current_vmptr = -1ull;
6889         vmx->nested.current_vmcs12 = NULL;
6890 }
6891
6892 /*
6893  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6894  * just stops using VMX.
6895  */
6896 static void free_nested(struct vcpu_vmx *vmx)
6897 {
6898         if (!vmx->nested.vmxon)
6899                 return;
6900
6901         vmx->nested.vmxon = false;
6902         free_vpid(vmx->nested.vpid02);
6903         nested_release_vmcs12(vmx);
6904         if (enable_shadow_vmcs)
6905                 free_vmcs(vmx->nested.current_shadow_vmcs);
6906         /* Unpin physical memory we referred to in current vmcs02 */
6907         if (vmx->nested.apic_access_page) {
6908                 nested_release_page(vmx->nested.apic_access_page);
6909                 vmx->nested.apic_access_page = NULL;
6910         }
6911         if (vmx->nested.virtual_apic_page) {
6912                 nested_release_page(vmx->nested.virtual_apic_page);
6913                 vmx->nested.virtual_apic_page = NULL;
6914         }
6915         if (vmx->nested.pi_desc_page) {
6916                 kunmap(vmx->nested.pi_desc_page);
6917                 nested_release_page(vmx->nested.pi_desc_page);
6918                 vmx->nested.pi_desc_page = NULL;
6919                 vmx->nested.pi_desc = NULL;
6920         }
6921
6922         nested_free_all_saved_vmcss(vmx);
6923 }
6924
6925 /* Emulate the VMXOFF instruction */
6926 static int handle_vmoff(struct kvm_vcpu *vcpu)
6927 {
6928         if (!nested_vmx_check_permission(vcpu))
6929                 return 1;
6930         free_nested(to_vmx(vcpu));
6931         skip_emulated_instruction(vcpu);
6932         nested_vmx_succeed(vcpu);
6933         return 1;
6934 }
6935
6936 /* Emulate the VMCLEAR instruction */
6937 static int handle_vmclear(struct kvm_vcpu *vcpu)
6938 {
6939         struct vcpu_vmx *vmx = to_vmx(vcpu);
6940         gpa_t vmptr;
6941         struct vmcs12 *vmcs12;
6942         struct page *page;
6943
6944         if (!nested_vmx_check_permission(vcpu))
6945                 return 1;
6946
6947         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6948                 return 1;
6949
6950         if (vmptr == vmx->nested.current_vmptr)
6951                 nested_release_vmcs12(vmx);
6952
6953         page = nested_get_page(vcpu, vmptr);
6954         if (page == NULL) {
6955                 /*
6956                  * For accurate processor emulation, VMCLEAR beyond available
6957                  * physical memory should do nothing at all. However, it is
6958                  * possible that a nested vmx bug, not a guest hypervisor bug,
6959                  * resulted in this case, so let's shut down before doing any
6960                  * more damage:
6961                  */
6962                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6963                 return 1;
6964         }
6965         vmcs12 = kmap(page);
6966         vmcs12->launch_state = 0;
6967         kunmap(page);
6968         nested_release_page(page);
6969
6970         nested_free_vmcs02(vmx, vmptr);
6971
6972         skip_emulated_instruction(vcpu);
6973         nested_vmx_succeed(vcpu);
6974         return 1;
6975 }
6976
6977 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6978
6979 /* Emulate the VMLAUNCH instruction */
6980 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6981 {
6982         return nested_vmx_run(vcpu, true);
6983 }
6984
6985 /* Emulate the VMRESUME instruction */
6986 static int handle_vmresume(struct kvm_vcpu *vcpu)
6987 {
6988
6989         return nested_vmx_run(vcpu, false);
6990 }
6991
6992 enum vmcs_field_type {
6993         VMCS_FIELD_TYPE_U16 = 0,
6994         VMCS_FIELD_TYPE_U64 = 1,
6995         VMCS_FIELD_TYPE_U32 = 2,
6996         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6997 };
6998
6999 static inline int vmcs_field_type(unsigned long field)
7000 {
7001         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7002                 return VMCS_FIELD_TYPE_U32;
7003         return (field >> 13) & 0x3 ;
7004 }
7005
7006 static inline int vmcs_field_readonly(unsigned long field)
7007 {
7008         return (((field >> 10) & 0x3) == 1);
7009 }
7010
7011 /*
7012  * Read a vmcs12 field. Since these can have varying lengths and we return
7013  * one type, we chose the biggest type (u64) and zero-extend the return value
7014  * to that size. Note that the caller, handle_vmread, might need to use only
7015  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7016  * 64-bit fields are to be returned).
7017  */
7018 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7019                                   unsigned long field, u64 *ret)
7020 {
7021         short offset = vmcs_field_to_offset(field);
7022         char *p;
7023
7024         if (offset < 0)
7025                 return offset;
7026
7027         p = ((char *)(get_vmcs12(vcpu))) + offset;
7028
7029         switch (vmcs_field_type(field)) {
7030         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7031                 *ret = *((natural_width *)p);
7032                 return 0;
7033         case VMCS_FIELD_TYPE_U16:
7034                 *ret = *((u16 *)p);
7035                 return 0;
7036         case VMCS_FIELD_TYPE_U32:
7037                 *ret = *((u32 *)p);
7038                 return 0;
7039         case VMCS_FIELD_TYPE_U64:
7040                 *ret = *((u64 *)p);
7041                 return 0;
7042         default:
7043                 WARN_ON(1);
7044                 return -ENOENT;
7045         }
7046 }
7047
7048
7049 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7050                                    unsigned long field, u64 field_value){
7051         short offset = vmcs_field_to_offset(field);
7052         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7053         if (offset < 0)
7054                 return offset;
7055
7056         switch (vmcs_field_type(field)) {
7057         case VMCS_FIELD_TYPE_U16:
7058                 *(u16 *)p = field_value;
7059                 return 0;
7060         case VMCS_FIELD_TYPE_U32:
7061                 *(u32 *)p = field_value;
7062                 return 0;
7063         case VMCS_FIELD_TYPE_U64:
7064                 *(u64 *)p = field_value;
7065                 return 0;
7066         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7067                 *(natural_width *)p = field_value;
7068                 return 0;
7069         default:
7070                 WARN_ON(1);
7071                 return -ENOENT;
7072         }
7073
7074 }
7075
7076 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7077 {
7078         int i;
7079         unsigned long field;
7080         u64 field_value;
7081         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7082         const unsigned long *fields = shadow_read_write_fields;
7083         const int num_fields = max_shadow_read_write_fields;
7084
7085         preempt_disable();
7086
7087         vmcs_load(shadow_vmcs);
7088
7089         for (i = 0; i < num_fields; i++) {
7090                 field = fields[i];
7091                 switch (vmcs_field_type(field)) {
7092                 case VMCS_FIELD_TYPE_U16:
7093                         field_value = vmcs_read16(field);
7094                         break;
7095                 case VMCS_FIELD_TYPE_U32:
7096                         field_value = vmcs_read32(field);
7097                         break;
7098                 case VMCS_FIELD_TYPE_U64:
7099                         field_value = vmcs_read64(field);
7100                         break;
7101                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7102                         field_value = vmcs_readl(field);
7103                         break;
7104                 default:
7105                         WARN_ON(1);
7106                         continue;
7107                 }
7108                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7109         }
7110
7111         vmcs_clear(shadow_vmcs);
7112         vmcs_load(vmx->loaded_vmcs->vmcs);
7113
7114         preempt_enable();
7115 }
7116
7117 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7118 {
7119         const unsigned long *fields[] = {
7120                 shadow_read_write_fields,
7121                 shadow_read_only_fields
7122         };
7123         const int max_fields[] = {
7124                 max_shadow_read_write_fields,
7125                 max_shadow_read_only_fields
7126         };
7127         int i, q;
7128         unsigned long field;
7129         u64 field_value = 0;
7130         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7131
7132         vmcs_load(shadow_vmcs);
7133
7134         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7135                 for (i = 0; i < max_fields[q]; i++) {
7136                         field = fields[q][i];
7137                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7138
7139                         switch (vmcs_field_type(field)) {
7140                         case VMCS_FIELD_TYPE_U16:
7141                                 vmcs_write16(field, (u16)field_value);
7142                                 break;
7143                         case VMCS_FIELD_TYPE_U32:
7144                                 vmcs_write32(field, (u32)field_value);
7145                                 break;
7146                         case VMCS_FIELD_TYPE_U64:
7147                                 vmcs_write64(field, (u64)field_value);
7148                                 break;
7149                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7150                                 vmcs_writel(field, (long)field_value);
7151                                 break;
7152                         default:
7153                                 WARN_ON(1);
7154                                 break;
7155                         }
7156                 }
7157         }
7158
7159         vmcs_clear(shadow_vmcs);
7160         vmcs_load(vmx->loaded_vmcs->vmcs);
7161 }
7162
7163 /*
7164  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7165  * used before) all generate the same failure when it is missing.
7166  */
7167 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7168 {
7169         struct vcpu_vmx *vmx = to_vmx(vcpu);
7170         if (vmx->nested.current_vmptr == -1ull) {
7171                 nested_vmx_failInvalid(vcpu);
7172                 skip_emulated_instruction(vcpu);
7173                 return 0;
7174         }
7175         return 1;
7176 }
7177
7178 static int handle_vmread(struct kvm_vcpu *vcpu)
7179 {
7180         unsigned long field;
7181         u64 field_value;
7182         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7183         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7184         gva_t gva = 0;
7185
7186         if (!nested_vmx_check_permission(vcpu) ||
7187             !nested_vmx_check_vmcs12(vcpu))
7188                 return 1;
7189
7190         /* Decode instruction info and find the field to read */
7191         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7192         /* Read the field, zero-extended to a u64 field_value */
7193         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7194                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7195                 skip_emulated_instruction(vcpu);
7196                 return 1;
7197         }
7198         /*
7199          * Now copy part of this value to register or memory, as requested.
7200          * Note that the number of bits actually copied is 32 or 64 depending
7201          * on the guest's mode (32 or 64 bit), not on the given field's length.
7202          */
7203         if (vmx_instruction_info & (1u << 10)) {
7204                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7205                         field_value);
7206         } else {
7207                 if (get_vmx_mem_address(vcpu, exit_qualification,
7208                                 vmx_instruction_info, true, &gva))
7209                         return 1;
7210                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7211                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7212                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7213         }
7214
7215         nested_vmx_succeed(vcpu);
7216         skip_emulated_instruction(vcpu);
7217         return 1;
7218 }
7219
7220
7221 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7222 {
7223         unsigned long field;
7224         gva_t gva;
7225         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7226         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7227         /* The value to write might be 32 or 64 bits, depending on L1's long
7228          * mode, and eventually we need to write that into a field of several
7229          * possible lengths. The code below first zero-extends the value to 64
7230          * bit (field_value), and then copies only the approriate number of
7231          * bits into the vmcs12 field.
7232          */
7233         u64 field_value = 0;
7234         struct x86_exception e;
7235
7236         if (!nested_vmx_check_permission(vcpu) ||
7237             !nested_vmx_check_vmcs12(vcpu))
7238                 return 1;
7239
7240         if (vmx_instruction_info & (1u << 10))
7241                 field_value = kvm_register_readl(vcpu,
7242                         (((vmx_instruction_info) >> 3) & 0xf));
7243         else {
7244                 if (get_vmx_mem_address(vcpu, exit_qualification,
7245                                 vmx_instruction_info, false, &gva))
7246                         return 1;
7247                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7248                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7249                         kvm_inject_page_fault(vcpu, &e);
7250                         return 1;
7251                 }
7252         }
7253
7254
7255         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7256         if (vmcs_field_readonly(field)) {
7257                 nested_vmx_failValid(vcpu,
7258                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7259                 skip_emulated_instruction(vcpu);
7260                 return 1;
7261         }
7262
7263         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7264                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7265                 skip_emulated_instruction(vcpu);
7266                 return 1;
7267         }
7268
7269         nested_vmx_succeed(vcpu);
7270         skip_emulated_instruction(vcpu);
7271         return 1;
7272 }
7273
7274 /* Emulate the VMPTRLD instruction */
7275 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7276 {
7277         struct vcpu_vmx *vmx = to_vmx(vcpu);
7278         gpa_t vmptr;
7279
7280         if (!nested_vmx_check_permission(vcpu))
7281                 return 1;
7282
7283         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7284                 return 1;
7285
7286         if (vmx->nested.current_vmptr != vmptr) {
7287                 struct vmcs12 *new_vmcs12;
7288                 struct page *page;
7289                 page = nested_get_page(vcpu, vmptr);
7290                 if (page == NULL) {
7291                         nested_vmx_failInvalid(vcpu);
7292                         skip_emulated_instruction(vcpu);
7293                         return 1;
7294                 }
7295                 new_vmcs12 = kmap(page);
7296                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7297                         kunmap(page);
7298                         nested_release_page_clean(page);
7299                         nested_vmx_failValid(vcpu,
7300                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7301                         skip_emulated_instruction(vcpu);
7302                         return 1;
7303                 }
7304
7305                 nested_release_vmcs12(vmx);
7306                 vmx->nested.current_vmptr = vmptr;
7307                 vmx->nested.current_vmcs12 = new_vmcs12;
7308                 vmx->nested.current_vmcs12_page = page;
7309                 if (enable_shadow_vmcs) {
7310                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7311                                       SECONDARY_EXEC_SHADOW_VMCS);
7312                         vmcs_write64(VMCS_LINK_POINTER,
7313                                      __pa(vmx->nested.current_shadow_vmcs));
7314                         vmx->nested.sync_shadow_vmcs = true;
7315                 }
7316         }
7317
7318         nested_vmx_succeed(vcpu);
7319         skip_emulated_instruction(vcpu);
7320         return 1;
7321 }
7322
7323 /* Emulate the VMPTRST instruction */
7324 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7325 {
7326         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7327         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7328         gva_t vmcs_gva;
7329         struct x86_exception e;
7330
7331         if (!nested_vmx_check_permission(vcpu))
7332                 return 1;
7333
7334         if (get_vmx_mem_address(vcpu, exit_qualification,
7335                         vmx_instruction_info, true, &vmcs_gva))
7336                 return 1;
7337         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7338         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7339                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7340                                  sizeof(u64), &e)) {
7341                 kvm_inject_page_fault(vcpu, &e);
7342                 return 1;
7343         }
7344         nested_vmx_succeed(vcpu);
7345         skip_emulated_instruction(vcpu);
7346         return 1;
7347 }
7348
7349 /* Emulate the INVEPT instruction */
7350 static int handle_invept(struct kvm_vcpu *vcpu)
7351 {
7352         struct vcpu_vmx *vmx = to_vmx(vcpu);
7353         u32 vmx_instruction_info, types;
7354         unsigned long type;
7355         gva_t gva;
7356         struct x86_exception e;
7357         struct {
7358                 u64 eptp, gpa;
7359         } operand;
7360
7361         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7362               SECONDARY_EXEC_ENABLE_EPT) ||
7363             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7364                 kvm_queue_exception(vcpu, UD_VECTOR);
7365                 return 1;
7366         }
7367
7368         if (!nested_vmx_check_permission(vcpu))
7369                 return 1;
7370
7371         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7372                 kvm_queue_exception(vcpu, UD_VECTOR);
7373                 return 1;
7374         }
7375
7376         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7377         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7378
7379         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7380
7381         if (!(types & (1UL << type))) {
7382                 nested_vmx_failValid(vcpu,
7383                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7384                 return 1;
7385         }
7386
7387         /* According to the Intel VMX instruction reference, the memory
7388          * operand is read even if it isn't needed (e.g., for type==global)
7389          */
7390         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7391                         vmx_instruction_info, false, &gva))
7392                 return 1;
7393         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7394                                 sizeof(operand), &e)) {
7395                 kvm_inject_page_fault(vcpu, &e);
7396                 return 1;
7397         }
7398
7399         switch (type) {
7400         case VMX_EPT_EXTENT_GLOBAL:
7401                 kvm_mmu_sync_roots(vcpu);
7402                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7403                 nested_vmx_succeed(vcpu);
7404                 break;
7405         default:
7406                 /* Trap single context invalidation invept calls */
7407                 BUG_ON(1);
7408                 break;
7409         }
7410
7411         skip_emulated_instruction(vcpu);
7412         return 1;
7413 }
7414
7415 static int handle_invvpid(struct kvm_vcpu *vcpu)
7416 {
7417         struct vcpu_vmx *vmx = to_vmx(vcpu);
7418         u32 vmx_instruction_info;
7419         unsigned long type, types;
7420         gva_t gva;
7421         struct x86_exception e;
7422         int vpid;
7423
7424         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7425               SECONDARY_EXEC_ENABLE_VPID) ||
7426                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7427                 kvm_queue_exception(vcpu, UD_VECTOR);
7428                 return 1;
7429         }
7430
7431         if (!nested_vmx_check_permission(vcpu))
7432                 return 1;
7433
7434         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7435         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7436
7437         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7438
7439         if (!(types & (1UL << type))) {
7440                 nested_vmx_failValid(vcpu,
7441                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7442                 return 1;
7443         }
7444
7445         /* according to the intel vmx instruction reference, the memory
7446          * operand is read even if it isn't needed (e.g., for type==global)
7447          */
7448         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7449                         vmx_instruction_info, false, &gva))
7450                 return 1;
7451         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7452                                 sizeof(u32), &e)) {
7453                 kvm_inject_page_fault(vcpu, &e);
7454                 return 1;
7455         }
7456
7457         switch (type) {
7458         case VMX_VPID_EXTENT_ALL_CONTEXT:
7459                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7460                 nested_vmx_succeed(vcpu);
7461                 break;
7462         default:
7463                 /* Trap single context invalidation invvpid calls */
7464                 BUG_ON(1);
7465                 break;
7466         }
7467
7468         skip_emulated_instruction(vcpu);
7469         return 1;
7470 }
7471
7472 static int handle_pml_full(struct kvm_vcpu *vcpu)
7473 {
7474         unsigned long exit_qualification;
7475
7476         trace_kvm_pml_full(vcpu->vcpu_id);
7477
7478         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7479
7480         /*
7481          * PML buffer FULL happened while executing iret from NMI,
7482          * "blocked by NMI" bit has to be set before next VM entry.
7483          */
7484         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7485                         cpu_has_virtual_nmis() &&
7486                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7487                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7488                                 GUEST_INTR_STATE_NMI);
7489
7490         /*
7491          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7492          * here.., and there's no userspace involvement needed for PML.
7493          */
7494         return 1;
7495 }
7496
7497 static int handle_pcommit(struct kvm_vcpu *vcpu)
7498 {
7499         /* we never catch pcommit instruct for L1 guest. */
7500         WARN_ON(1);
7501         return 1;
7502 }
7503
7504 /*
7505  * The exit handlers return 1 if the exit was handled fully and guest execution
7506  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7507  * to be done to userspace and return 0.
7508  */
7509 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7510         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7511         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7512         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7513         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7514         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7515         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7516         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7517         [EXIT_REASON_CPUID]                   = handle_cpuid,
7518         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7519         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7520         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7521         [EXIT_REASON_HLT]                     = handle_halt,
7522         [EXIT_REASON_INVD]                    = handle_invd,
7523         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7524         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7525         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7526         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7527         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7528         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7529         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7530         [EXIT_REASON_VMREAD]                  = handle_vmread,
7531         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7532         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7533         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7534         [EXIT_REASON_VMON]                    = handle_vmon,
7535         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7536         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7537         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7538         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7539         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7540         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7541         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7542         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7543         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7544         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7545         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7546         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7547         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7548         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7549         [EXIT_REASON_INVEPT]                  = handle_invept,
7550         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7551         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7552         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7553         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7554         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7555 };
7556
7557 static const int kvm_vmx_max_exit_handlers =
7558         ARRAY_SIZE(kvm_vmx_exit_handlers);
7559
7560 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7561                                        struct vmcs12 *vmcs12)
7562 {
7563         unsigned long exit_qualification;
7564         gpa_t bitmap, last_bitmap;
7565         unsigned int port;
7566         int size;
7567         u8 b;
7568
7569         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7570                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7571
7572         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7573
7574         port = exit_qualification >> 16;
7575         size = (exit_qualification & 7) + 1;
7576
7577         last_bitmap = (gpa_t)-1;
7578         b = -1;
7579
7580         while (size > 0) {
7581                 if (port < 0x8000)
7582                         bitmap = vmcs12->io_bitmap_a;
7583                 else if (port < 0x10000)
7584                         bitmap = vmcs12->io_bitmap_b;
7585                 else
7586                         return true;
7587                 bitmap += (port & 0x7fff) / 8;
7588
7589                 if (last_bitmap != bitmap)
7590                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7591                                 return true;
7592                 if (b & (1 << (port & 7)))
7593                         return true;
7594
7595                 port++;
7596                 size--;
7597                 last_bitmap = bitmap;
7598         }
7599
7600         return false;
7601 }
7602
7603 /*
7604  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7605  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7606  * disinterest in the current event (read or write a specific MSR) by using an
7607  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7608  */
7609 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7610         struct vmcs12 *vmcs12, u32 exit_reason)
7611 {
7612         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7613         gpa_t bitmap;
7614
7615         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7616                 return true;
7617
7618         /*
7619          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7620          * for the four combinations of read/write and low/high MSR numbers.
7621          * First we need to figure out which of the four to use:
7622          */
7623         bitmap = vmcs12->msr_bitmap;
7624         if (exit_reason == EXIT_REASON_MSR_WRITE)
7625                 bitmap += 2048;
7626         if (msr_index >= 0xc0000000) {
7627                 msr_index -= 0xc0000000;
7628                 bitmap += 1024;
7629         }
7630
7631         /* Then read the msr_index'th bit from this bitmap: */
7632         if (msr_index < 1024*8) {
7633                 unsigned char b;
7634                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7635                         return true;
7636                 return 1 & (b >> (msr_index & 7));
7637         } else
7638                 return true; /* let L1 handle the wrong parameter */
7639 }
7640
7641 /*
7642  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7643  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7644  * intercept (via guest_host_mask etc.) the current event.
7645  */
7646 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7647         struct vmcs12 *vmcs12)
7648 {
7649         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7650         int cr = exit_qualification & 15;
7651         int reg = (exit_qualification >> 8) & 15;
7652         unsigned long val = kvm_register_readl(vcpu, reg);
7653
7654         switch ((exit_qualification >> 4) & 3) {
7655         case 0: /* mov to cr */
7656                 switch (cr) {
7657                 case 0:
7658                         if (vmcs12->cr0_guest_host_mask &
7659                             (val ^ vmcs12->cr0_read_shadow))
7660                                 return true;
7661                         break;
7662                 case 3:
7663                         if ((vmcs12->cr3_target_count >= 1 &&
7664                                         vmcs12->cr3_target_value0 == val) ||
7665                                 (vmcs12->cr3_target_count >= 2 &&
7666                                         vmcs12->cr3_target_value1 == val) ||
7667                                 (vmcs12->cr3_target_count >= 3 &&
7668                                         vmcs12->cr3_target_value2 == val) ||
7669                                 (vmcs12->cr3_target_count >= 4 &&
7670                                         vmcs12->cr3_target_value3 == val))
7671                                 return false;
7672                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7673                                 return true;
7674                         break;
7675                 case 4:
7676                         if (vmcs12->cr4_guest_host_mask &
7677                             (vmcs12->cr4_read_shadow ^ val))
7678                                 return true;
7679                         break;
7680                 case 8:
7681                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7682                                 return true;
7683                         break;
7684                 }
7685                 break;
7686         case 2: /* clts */
7687                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7688                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7689                         return true;
7690                 break;
7691         case 1: /* mov from cr */
7692                 switch (cr) {
7693                 case 3:
7694                         if (vmcs12->cpu_based_vm_exec_control &
7695                             CPU_BASED_CR3_STORE_EXITING)
7696                                 return true;
7697                         break;
7698                 case 8:
7699                         if (vmcs12->cpu_based_vm_exec_control &
7700                             CPU_BASED_CR8_STORE_EXITING)
7701                                 return true;
7702                         break;
7703                 }
7704                 break;
7705         case 3: /* lmsw */
7706                 /*
7707                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7708                  * cr0. Other attempted changes are ignored, with no exit.
7709                  */
7710                 if (vmcs12->cr0_guest_host_mask & 0xe &
7711                     (val ^ vmcs12->cr0_read_shadow))
7712                         return true;
7713                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7714                     !(vmcs12->cr0_read_shadow & 0x1) &&
7715                     (val & 0x1))
7716                         return true;
7717                 break;
7718         }
7719         return false;
7720 }
7721
7722 /*
7723  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7724  * should handle it ourselves in L0 (and then continue L2). Only call this
7725  * when in is_guest_mode (L2).
7726  */
7727 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7728 {
7729         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7730         struct vcpu_vmx *vmx = to_vmx(vcpu);
7731         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7732         u32 exit_reason = vmx->exit_reason;
7733
7734         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7735                                 vmcs_readl(EXIT_QUALIFICATION),
7736                                 vmx->idt_vectoring_info,
7737                                 intr_info,
7738                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7739                                 KVM_ISA_VMX);
7740
7741         if (vmx->nested.nested_run_pending)
7742                 return false;
7743
7744         if (unlikely(vmx->fail)) {
7745                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7746                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7747                 return true;
7748         }
7749
7750         switch (exit_reason) {
7751         case EXIT_REASON_EXCEPTION_NMI:
7752                 if (!is_exception(intr_info))
7753                         return false;
7754                 else if (is_page_fault(intr_info))
7755                         return enable_ept;
7756                 else if (is_no_device(intr_info) &&
7757                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7758                         return false;
7759                 return vmcs12->exception_bitmap &
7760                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7761         case EXIT_REASON_EXTERNAL_INTERRUPT:
7762                 return false;
7763         case EXIT_REASON_TRIPLE_FAULT:
7764                 return true;
7765         case EXIT_REASON_PENDING_INTERRUPT:
7766                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7767         case EXIT_REASON_NMI_WINDOW:
7768                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7769         case EXIT_REASON_TASK_SWITCH:
7770                 return true;
7771         case EXIT_REASON_CPUID:
7772                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7773                         return false;
7774                 return true;
7775         case EXIT_REASON_HLT:
7776                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7777         case EXIT_REASON_INVD:
7778                 return true;
7779         case EXIT_REASON_INVLPG:
7780                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7781         case EXIT_REASON_RDPMC:
7782                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7783         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7784                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7785         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7786         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7787         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7788         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7789         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7790         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7791                 /*
7792                  * VMX instructions trap unconditionally. This allows L1 to
7793                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7794                  */
7795                 return true;
7796         case EXIT_REASON_CR_ACCESS:
7797                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7798         case EXIT_REASON_DR_ACCESS:
7799                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7800         case EXIT_REASON_IO_INSTRUCTION:
7801                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7802         case EXIT_REASON_MSR_READ:
7803         case EXIT_REASON_MSR_WRITE:
7804                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7805         case EXIT_REASON_INVALID_STATE:
7806                 return true;
7807         case EXIT_REASON_MWAIT_INSTRUCTION:
7808                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7809         case EXIT_REASON_MONITOR_TRAP_FLAG:
7810                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7811         case EXIT_REASON_MONITOR_INSTRUCTION:
7812                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7813         case EXIT_REASON_PAUSE_INSTRUCTION:
7814                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7815                         nested_cpu_has2(vmcs12,
7816                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7817         case EXIT_REASON_MCE_DURING_VMENTRY:
7818                 return false;
7819         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7820                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7821         case EXIT_REASON_APIC_ACCESS:
7822                 return nested_cpu_has2(vmcs12,
7823                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7824         case EXIT_REASON_APIC_WRITE:
7825         case EXIT_REASON_EOI_INDUCED:
7826                 /* apic_write and eoi_induced should exit unconditionally. */
7827                 return true;
7828         case EXIT_REASON_EPT_VIOLATION:
7829                 /*
7830                  * L0 always deals with the EPT violation. If nested EPT is
7831                  * used, and the nested mmu code discovers that the address is
7832                  * missing in the guest EPT table (EPT12), the EPT violation
7833                  * will be injected with nested_ept_inject_page_fault()
7834                  */
7835                 return false;
7836         case EXIT_REASON_EPT_MISCONFIG:
7837                 /*
7838                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7839                  * table (shadow on EPT) or a merged EPT table that L0 built
7840                  * (EPT on EPT). So any problems with the structure of the
7841                  * table is L0's fault.
7842                  */
7843                 return false;
7844         case EXIT_REASON_WBINVD:
7845                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7846         case EXIT_REASON_XSETBV:
7847                 return true;
7848         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7849                 /*
7850                  * This should never happen, since it is not possible to
7851                  * set XSS to a non-zero value---neither in L1 nor in L2.
7852                  * If if it were, XSS would have to be checked against
7853                  * the XSS exit bitmap in vmcs12.
7854                  */
7855                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7856         case EXIT_REASON_PCOMMIT:
7857                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7858         default:
7859                 return true;
7860         }
7861 }
7862
7863 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7864 {
7865         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7866         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7867 }
7868
7869 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7870 {
7871         struct page *pml_pg;
7872
7873         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7874         if (!pml_pg)
7875                 return -ENOMEM;
7876
7877         vmx->pml_pg = pml_pg;
7878
7879         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7880         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7881
7882         return 0;
7883 }
7884
7885 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7886 {
7887         if (vmx->pml_pg) {
7888                 __free_page(vmx->pml_pg);
7889                 vmx->pml_pg = NULL;
7890         }
7891 }
7892
7893 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7894 {
7895         struct vcpu_vmx *vmx = to_vmx(vcpu);
7896         u64 *pml_buf;
7897         u16 pml_idx;
7898
7899         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7900
7901         /* Do nothing if PML buffer is empty */
7902         if (pml_idx == (PML_ENTITY_NUM - 1))
7903                 return;
7904
7905         /* PML index always points to next available PML buffer entity */
7906         if (pml_idx >= PML_ENTITY_NUM)
7907                 pml_idx = 0;
7908         else
7909                 pml_idx++;
7910
7911         pml_buf = page_address(vmx->pml_pg);
7912         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7913                 u64 gpa;
7914
7915                 gpa = pml_buf[pml_idx];
7916                 WARN_ON(gpa & (PAGE_SIZE - 1));
7917                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7918         }
7919
7920         /* reset PML index */
7921         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7922 }
7923
7924 /*
7925  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7926  * Called before reporting dirty_bitmap to userspace.
7927  */
7928 static void kvm_flush_pml_buffers(struct kvm *kvm)
7929 {
7930         int i;
7931         struct kvm_vcpu *vcpu;
7932         /*
7933          * We only need to kick vcpu out of guest mode here, as PML buffer
7934          * is flushed at beginning of all VMEXITs, and it's obvious that only
7935          * vcpus running in guest are possible to have unflushed GPAs in PML
7936          * buffer.
7937          */
7938         kvm_for_each_vcpu(i, vcpu, kvm)
7939                 kvm_vcpu_kick(vcpu);
7940 }
7941
7942 static void vmx_dump_sel(char *name, uint32_t sel)
7943 {
7944         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7945                name, vmcs_read32(sel),
7946                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7947                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7948                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7949 }
7950
7951 static void vmx_dump_dtsel(char *name, uint32_t limit)
7952 {
7953         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7954                name, vmcs_read32(limit),
7955                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7956 }
7957
7958 static void dump_vmcs(void)
7959 {
7960         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7961         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7962         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7963         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7964         u32 secondary_exec_control = 0;
7965         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7966         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7967         int i, n;
7968
7969         if (cpu_has_secondary_exec_ctrls())
7970                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7971
7972         pr_err("*** Guest State ***\n");
7973         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7974                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7975                vmcs_readl(CR0_GUEST_HOST_MASK));
7976         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7977                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7978         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7979         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7980             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7981         {
7982                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
7983                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
7984                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
7985                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
7986         }
7987         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7988                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7989         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7990                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7991         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7992                vmcs_readl(GUEST_SYSENTER_ESP),
7993                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7994         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7995         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7996         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7997         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7998         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7999         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8000         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8001         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8002         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8003         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8004         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8005             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8006                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8007                        efer, vmcs_read64(GUEST_IA32_PAT));
8008         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8009                vmcs_read64(GUEST_IA32_DEBUGCTL),
8010                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8011         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8012                 pr_err("PerfGlobCtl = 0x%016llx\n",
8013                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8014         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8015                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8016         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8017                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8018                vmcs_read32(GUEST_ACTIVITY_STATE));
8019         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8020                 pr_err("InterruptStatus = %04x\n",
8021                        vmcs_read16(GUEST_INTR_STATUS));
8022
8023         pr_err("*** Host State ***\n");
8024         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8025                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8026         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8027                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8028                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8029                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8030                vmcs_read16(HOST_TR_SELECTOR));
8031         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8032                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8033                vmcs_readl(HOST_TR_BASE));
8034         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8035                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8036         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8037                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8038                vmcs_readl(HOST_CR4));
8039         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8040                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8041                vmcs_read32(HOST_IA32_SYSENTER_CS),
8042                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8043         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8044                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8045                        vmcs_read64(HOST_IA32_EFER),
8046                        vmcs_read64(HOST_IA32_PAT));
8047         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8048                 pr_err("PerfGlobCtl = 0x%016llx\n",
8049                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8050
8051         pr_err("*** Control State ***\n");
8052         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8053                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8054         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8055         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8056                vmcs_read32(EXCEPTION_BITMAP),
8057                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8058                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8059         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8060                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8061                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8062                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8063         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8064                vmcs_read32(VM_EXIT_INTR_INFO),
8065                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8066                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8067         pr_err("        reason=%08x qualification=%016lx\n",
8068                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8069         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8070                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8071                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8072         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8073         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8074                 pr_err("TSC Multiplier = 0x%016llx\n",
8075                        vmcs_read64(TSC_MULTIPLIER));
8076         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8077                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8078         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8079                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8080         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8081                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8082         n = vmcs_read32(CR3_TARGET_COUNT);
8083         for (i = 0; i + 1 < n; i += 4)
8084                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8085                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8086                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8087         if (i < n)
8088                 pr_err("CR3 target%u=%016lx\n",
8089                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8090         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8091                 pr_err("PLE Gap=%08x Window=%08x\n",
8092                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8093         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8094                 pr_err("Virtual processor ID = 0x%04x\n",
8095                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8096 }
8097
8098 /*
8099  * The guest has exited.  See if we can fix it or if we need userspace
8100  * assistance.
8101  */
8102 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8103 {
8104         struct vcpu_vmx *vmx = to_vmx(vcpu);
8105         u32 exit_reason = vmx->exit_reason;
8106         u32 vectoring_info = vmx->idt_vectoring_info;
8107
8108         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8109
8110         /*
8111          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8112          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8113          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8114          * mode as if vcpus is in root mode, the PML buffer must has been
8115          * flushed already.
8116          */
8117         if (enable_pml)
8118                 vmx_flush_pml_buffer(vcpu);
8119
8120         /* If guest state is invalid, start emulating */
8121         if (vmx->emulation_required)
8122                 return handle_invalid_guest_state(vcpu);
8123
8124         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8125                 nested_vmx_vmexit(vcpu, exit_reason,
8126                                   vmcs_read32(VM_EXIT_INTR_INFO),
8127                                   vmcs_readl(EXIT_QUALIFICATION));
8128                 return 1;
8129         }
8130
8131         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8132                 dump_vmcs();
8133                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8134                 vcpu->run->fail_entry.hardware_entry_failure_reason
8135                         = exit_reason;
8136                 return 0;
8137         }
8138
8139         if (unlikely(vmx->fail)) {
8140                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8141                 vcpu->run->fail_entry.hardware_entry_failure_reason
8142                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8143                 return 0;
8144         }
8145
8146         /*
8147          * Note:
8148          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8149          * delivery event since it indicates guest is accessing MMIO.
8150          * The vm-exit can be triggered again after return to guest that
8151          * will cause infinite loop.
8152          */
8153         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8154                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8155                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8156                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8157                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8158                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8159                 vcpu->run->internal.ndata = 2;
8160                 vcpu->run->internal.data[0] = vectoring_info;
8161                 vcpu->run->internal.data[1] = exit_reason;
8162                 return 0;
8163         }
8164
8165         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8166             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8167                                         get_vmcs12(vcpu))))) {
8168                 if (vmx_interrupt_allowed(vcpu)) {
8169                         vmx->soft_vnmi_blocked = 0;
8170                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8171                            vcpu->arch.nmi_pending) {
8172                         /*
8173                          * This CPU don't support us in finding the end of an
8174                          * NMI-blocked window if the guest runs with IRQs
8175                          * disabled. So we pull the trigger after 1 s of
8176                          * futile waiting, but inform the user about this.
8177                          */
8178                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8179                                "state on VCPU %d after 1 s timeout\n",
8180                                __func__, vcpu->vcpu_id);
8181                         vmx->soft_vnmi_blocked = 0;
8182                 }
8183         }
8184
8185         if (exit_reason < kvm_vmx_max_exit_handlers
8186             && kvm_vmx_exit_handlers[exit_reason])
8187                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8188         else {
8189                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8190                 kvm_queue_exception(vcpu, UD_VECTOR);
8191                 return 1;
8192         }
8193 }
8194
8195 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8196 {
8197         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8198
8199         if (is_guest_mode(vcpu) &&
8200                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8201                 return;
8202
8203         if (irr == -1 || tpr < irr) {
8204                 vmcs_write32(TPR_THRESHOLD, 0);
8205                 return;
8206         }
8207
8208         vmcs_write32(TPR_THRESHOLD, irr);
8209 }
8210
8211 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8212 {
8213         u32 sec_exec_control;
8214
8215         /*
8216          * There is not point to enable virtualize x2apic without enable
8217          * apicv
8218          */
8219         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8220                                 !kvm_vcpu_apicv_active(vcpu))
8221                 return;
8222
8223         if (!cpu_need_tpr_shadow(vcpu))
8224                 return;
8225
8226         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8227
8228         if (set) {
8229                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8230                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8231         } else {
8232                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8233                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8234         }
8235         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8236
8237         vmx_set_msr_bitmap(vcpu);
8238 }
8239
8240 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8241 {
8242         struct vcpu_vmx *vmx = to_vmx(vcpu);
8243
8244         /*
8245          * Currently we do not handle the nested case where L2 has an
8246          * APIC access page of its own; that page is still pinned.
8247          * Hence, we skip the case where the VCPU is in guest mode _and_
8248          * L1 prepared an APIC access page for L2.
8249          *
8250          * For the case where L1 and L2 share the same APIC access page
8251          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8252          * in the vmcs12), this function will only update either the vmcs01
8253          * or the vmcs02.  If the former, the vmcs02 will be updated by
8254          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8255          * the next L2->L1 exit.
8256          */
8257         if (!is_guest_mode(vcpu) ||
8258             !nested_cpu_has2(vmx->nested.current_vmcs12,
8259                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8260                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8261 }
8262
8263 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8264 {
8265         u16 status;
8266         u8 old;
8267
8268         if (isr == -1)
8269                 isr = 0;
8270
8271         status = vmcs_read16(GUEST_INTR_STATUS);
8272         old = status >> 8;
8273         if (isr != old) {
8274                 status &= 0xff;
8275                 status |= isr << 8;
8276                 vmcs_write16(GUEST_INTR_STATUS, status);
8277         }
8278 }
8279
8280 static void vmx_set_rvi(int vector)
8281 {
8282         u16 status;
8283         u8 old;
8284
8285         if (vector == -1)
8286                 vector = 0;
8287
8288         status = vmcs_read16(GUEST_INTR_STATUS);
8289         old = (u8)status & 0xff;
8290         if ((u8)vector != old) {
8291                 status &= ~0xff;
8292                 status |= (u8)vector;
8293                 vmcs_write16(GUEST_INTR_STATUS, status);
8294         }
8295 }
8296
8297 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8298 {
8299         if (!is_guest_mode(vcpu)) {
8300                 vmx_set_rvi(max_irr);
8301                 return;
8302         }
8303
8304         if (max_irr == -1)
8305                 return;
8306
8307         /*
8308          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8309          * handles it.
8310          */
8311         if (nested_exit_on_intr(vcpu))
8312                 return;
8313
8314         /*
8315          * Else, fall back to pre-APICv interrupt injection since L2
8316          * is run without virtual interrupt delivery.
8317          */
8318         if (!kvm_event_needs_reinjection(vcpu) &&
8319             vmx_interrupt_allowed(vcpu)) {
8320                 kvm_queue_interrupt(vcpu, max_irr, false);
8321                 vmx_inject_irq(vcpu);
8322         }
8323 }
8324
8325 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8326 {
8327         if (!kvm_vcpu_apicv_active(vcpu))
8328                 return;
8329
8330         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8331         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8332         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8333         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8334 }
8335
8336 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8337 {
8338         u32 exit_intr_info;
8339
8340         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8341               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8342                 return;
8343
8344         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8345         exit_intr_info = vmx->exit_intr_info;
8346
8347         /* Handle machine checks before interrupts are enabled */
8348         if (is_machine_check(exit_intr_info))
8349                 kvm_machine_check();
8350
8351         /* We need to handle NMIs before interrupts are enabled */
8352         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8353             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8354                 kvm_before_handle_nmi(&vmx->vcpu);
8355                 asm("int $2");
8356                 kvm_after_handle_nmi(&vmx->vcpu);
8357         }
8358 }
8359
8360 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8361 {
8362         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8363
8364         /*
8365          * If external interrupt exists, IF bit is set in rflags/eflags on the
8366          * interrupt stack frame, and interrupt will be enabled on a return
8367          * from interrupt handler.
8368          */
8369         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8370                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8371                 unsigned int vector;
8372                 unsigned long entry;
8373                 gate_desc *desc;
8374                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8375 #ifdef CONFIG_X86_64
8376                 unsigned long tmp;
8377 #endif
8378
8379                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8380                 desc = (gate_desc *)vmx->host_idt_base + vector;
8381                 entry = gate_offset(*desc);
8382                 asm volatile(
8383 #ifdef CONFIG_X86_64
8384                         "mov %%" _ASM_SP ", %[sp]\n\t"
8385                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8386                         "push $%c[ss]\n\t"
8387                         "push %[sp]\n\t"
8388 #endif
8389                         "pushf\n\t"
8390                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8391                         __ASM_SIZE(push) " $%c[cs]\n\t"
8392                         "call *%[entry]\n\t"
8393                         :
8394 #ifdef CONFIG_X86_64
8395                         [sp]"=&r"(tmp)
8396 #endif
8397                         :
8398                         [entry]"r"(entry),
8399                         [ss]"i"(__KERNEL_DS),
8400                         [cs]"i"(__KERNEL_CS)
8401                         );
8402         } else
8403                 local_irq_enable();
8404 }
8405
8406 static bool vmx_has_high_real_mode_segbase(void)
8407 {
8408         return enable_unrestricted_guest || emulate_invalid_guest_state;
8409 }
8410
8411 static bool vmx_mpx_supported(void)
8412 {
8413         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8414                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8415 }
8416
8417 static bool vmx_xsaves_supported(void)
8418 {
8419         return vmcs_config.cpu_based_2nd_exec_ctrl &
8420                 SECONDARY_EXEC_XSAVES;
8421 }
8422
8423 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8424 {
8425         u32 exit_intr_info;
8426         bool unblock_nmi;
8427         u8 vector;
8428         bool idtv_info_valid;
8429
8430         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8431
8432         if (cpu_has_virtual_nmis()) {
8433                 if (vmx->nmi_known_unmasked)
8434                         return;
8435                 /*
8436                  * Can't use vmx->exit_intr_info since we're not sure what
8437                  * the exit reason is.
8438                  */
8439                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8440                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8441                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8442                 /*
8443                  * SDM 3: 27.7.1.2 (September 2008)
8444                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8445                  * a guest IRET fault.
8446                  * SDM 3: 23.2.2 (September 2008)
8447                  * Bit 12 is undefined in any of the following cases:
8448                  *  If the VM exit sets the valid bit in the IDT-vectoring
8449                  *   information field.
8450                  *  If the VM exit is due to a double fault.
8451                  */
8452                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8453                     vector != DF_VECTOR && !idtv_info_valid)
8454                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8455                                       GUEST_INTR_STATE_NMI);
8456                 else
8457                         vmx->nmi_known_unmasked =
8458                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8459                                   & GUEST_INTR_STATE_NMI);
8460         } else if (unlikely(vmx->soft_vnmi_blocked))
8461                 vmx->vnmi_blocked_time +=
8462                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8463 }
8464
8465 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8466                                       u32 idt_vectoring_info,
8467                                       int instr_len_field,
8468                                       int error_code_field)
8469 {
8470         u8 vector;
8471         int type;
8472         bool idtv_info_valid;
8473
8474         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8475
8476         vcpu->arch.nmi_injected = false;
8477         kvm_clear_exception_queue(vcpu);
8478         kvm_clear_interrupt_queue(vcpu);
8479
8480         if (!idtv_info_valid)
8481                 return;
8482
8483         kvm_make_request(KVM_REQ_EVENT, vcpu);
8484
8485         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8486         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8487
8488         switch (type) {
8489         case INTR_TYPE_NMI_INTR:
8490                 vcpu->arch.nmi_injected = true;
8491                 /*
8492                  * SDM 3: 27.7.1.2 (September 2008)
8493                  * Clear bit "block by NMI" before VM entry if a NMI
8494                  * delivery faulted.
8495                  */
8496                 vmx_set_nmi_mask(vcpu, false);
8497                 break;
8498         case INTR_TYPE_SOFT_EXCEPTION:
8499                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8500                 /* fall through */
8501         case INTR_TYPE_HARD_EXCEPTION:
8502                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8503                         u32 err = vmcs_read32(error_code_field);
8504                         kvm_requeue_exception_e(vcpu, vector, err);
8505                 } else
8506                         kvm_requeue_exception(vcpu, vector);
8507                 break;
8508         case INTR_TYPE_SOFT_INTR:
8509                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8510                 /* fall through */
8511         case INTR_TYPE_EXT_INTR:
8512                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8513                 break;
8514         default:
8515                 break;
8516         }
8517 }
8518
8519 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8520 {
8521         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8522                                   VM_EXIT_INSTRUCTION_LEN,
8523                                   IDT_VECTORING_ERROR_CODE);
8524 }
8525
8526 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8527 {
8528         __vmx_complete_interrupts(vcpu,
8529                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8530                                   VM_ENTRY_INSTRUCTION_LEN,
8531                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8532
8533         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8534 }
8535
8536 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8537 {
8538         int i, nr_msrs;
8539         struct perf_guest_switch_msr *msrs;
8540
8541         msrs = perf_guest_get_msrs(&nr_msrs);
8542
8543         if (!msrs)
8544                 return;
8545
8546         for (i = 0; i < nr_msrs; i++)
8547                 if (msrs[i].host == msrs[i].guest)
8548                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8549                 else
8550                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8551                                         msrs[i].host);
8552 }
8553
8554 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8555 {
8556         struct vcpu_vmx *vmx = to_vmx(vcpu);
8557         unsigned long debugctlmsr, cr4;
8558
8559         /* Record the guest's net vcpu time for enforced NMI injections. */
8560         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8561                 vmx->entry_time = ktime_get();
8562
8563         /* Don't enter VMX if guest state is invalid, let the exit handler
8564            start emulation until we arrive back to a valid state */
8565         if (vmx->emulation_required)
8566                 return;
8567
8568         if (vmx->ple_window_dirty) {
8569                 vmx->ple_window_dirty = false;
8570                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8571         }
8572
8573         if (vmx->nested.sync_shadow_vmcs) {
8574                 copy_vmcs12_to_shadow(vmx);
8575                 vmx->nested.sync_shadow_vmcs = false;
8576         }
8577
8578         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8579                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8580         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8581                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8582
8583         cr4 = cr4_read_shadow();
8584         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8585                 vmcs_writel(HOST_CR4, cr4);
8586                 vmx->host_state.vmcs_host_cr4 = cr4;
8587         }
8588
8589         /* When single-stepping over STI and MOV SS, we must clear the
8590          * corresponding interruptibility bits in the guest state. Otherwise
8591          * vmentry fails as it then expects bit 14 (BS) in pending debug
8592          * exceptions being set, but that's not correct for the guest debugging
8593          * case. */
8594         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8595                 vmx_set_interrupt_shadow(vcpu, 0);
8596
8597         atomic_switch_perf_msrs(vmx);
8598         debugctlmsr = get_debugctlmsr();
8599
8600         vmx->__launched = vmx->loaded_vmcs->launched;
8601         asm(
8602                 /* Store host registers */
8603                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8604                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8605                 "push %%" _ASM_CX " \n\t"
8606                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8607                 "je 1f \n\t"
8608                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8609                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8610                 "1: \n\t"
8611                 /* Reload cr2 if changed */
8612                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8613                 "mov %%cr2, %%" _ASM_DX " \n\t"
8614                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8615                 "je 2f \n\t"
8616                 "mov %%" _ASM_AX", %%cr2 \n\t"
8617                 "2: \n\t"
8618                 /* Check if vmlaunch of vmresume is needed */
8619                 "cmpl $0, %c[launched](%0) \n\t"
8620                 /* Load guest registers.  Don't clobber flags. */
8621                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8622                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8623                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8624                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8625                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8626                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8627 #ifdef CONFIG_X86_64
8628                 "mov %c[r8](%0),  %%r8  \n\t"
8629                 "mov %c[r9](%0),  %%r9  \n\t"
8630                 "mov %c[r10](%0), %%r10 \n\t"
8631                 "mov %c[r11](%0), %%r11 \n\t"
8632                 "mov %c[r12](%0), %%r12 \n\t"
8633                 "mov %c[r13](%0), %%r13 \n\t"
8634                 "mov %c[r14](%0), %%r14 \n\t"
8635                 "mov %c[r15](%0), %%r15 \n\t"
8636 #endif
8637                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8638
8639                 /* Enter guest mode */
8640                 "jne 1f \n\t"
8641                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8642                 "jmp 2f \n\t"
8643                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8644                 "2: "
8645                 /* Save guest registers, load host registers, keep flags */
8646                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8647                 "pop %0 \n\t"
8648                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8649                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8650                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8651                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8652                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8653                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8654                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8655 #ifdef CONFIG_X86_64
8656                 "mov %%r8,  %c[r8](%0) \n\t"
8657                 "mov %%r9,  %c[r9](%0) \n\t"
8658                 "mov %%r10, %c[r10](%0) \n\t"
8659                 "mov %%r11, %c[r11](%0) \n\t"
8660                 "mov %%r12, %c[r12](%0) \n\t"
8661                 "mov %%r13, %c[r13](%0) \n\t"
8662                 "mov %%r14, %c[r14](%0) \n\t"
8663                 "mov %%r15, %c[r15](%0) \n\t"
8664 #endif
8665                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8666                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8667
8668                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8669                 "setbe %c[fail](%0) \n\t"
8670                 ".pushsection .rodata \n\t"
8671                 ".global vmx_return \n\t"
8672                 "vmx_return: " _ASM_PTR " 2b \n\t"
8673                 ".popsection"
8674               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8675                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8676                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8677                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8678                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8679                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8680                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8681                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8682                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8683                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8684                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8685 #ifdef CONFIG_X86_64
8686                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8687                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8688                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8689                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8690                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8691                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8692                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8693                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8694 #endif
8695                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8696                 [wordsize]"i"(sizeof(ulong))
8697               : "cc", "memory"
8698 #ifdef CONFIG_X86_64
8699                 , "rax", "rbx", "rdi", "rsi"
8700                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8701 #else
8702                 , "eax", "ebx", "edi", "esi"
8703 #endif
8704               );
8705
8706         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8707         if (debugctlmsr)
8708                 update_debugctlmsr(debugctlmsr);
8709
8710 #ifndef CONFIG_X86_64
8711         /*
8712          * The sysexit path does not restore ds/es, so we must set them to
8713          * a reasonable value ourselves.
8714          *
8715          * We can't defer this to vmx_load_host_state() since that function
8716          * may be executed in interrupt context, which saves and restore segments
8717          * around it, nullifying its effect.
8718          */
8719         loadsegment(ds, __USER_DS);
8720         loadsegment(es, __USER_DS);
8721 #endif
8722
8723         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8724                                   | (1 << VCPU_EXREG_RFLAGS)
8725                                   | (1 << VCPU_EXREG_PDPTR)
8726                                   | (1 << VCPU_EXREG_SEGMENTS)
8727                                   | (1 << VCPU_EXREG_CR3));
8728         vcpu->arch.regs_dirty = 0;
8729
8730         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8731
8732         vmx->loaded_vmcs->launched = 1;
8733
8734         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8735
8736         /*
8737          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8738          * we did not inject a still-pending event to L1 now because of
8739          * nested_run_pending, we need to re-enable this bit.
8740          */
8741         if (vmx->nested.nested_run_pending)
8742                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8743
8744         vmx->nested.nested_run_pending = 0;
8745
8746         vmx_complete_atomic_exit(vmx);
8747         vmx_recover_nmi_blocking(vmx);
8748         vmx_complete_interrupts(vmx);
8749 }
8750
8751 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8752 {
8753         struct vcpu_vmx *vmx = to_vmx(vcpu);
8754         int cpu;
8755
8756         if (vmx->loaded_vmcs == &vmx->vmcs01)
8757                 return;
8758
8759         cpu = get_cpu();
8760         vmx->loaded_vmcs = &vmx->vmcs01;
8761         vmx_vcpu_put(vcpu);
8762         vmx_vcpu_load(vcpu, cpu);
8763         vcpu->cpu = cpu;
8764         put_cpu();
8765 }
8766
8767 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8768 {
8769         struct vcpu_vmx *vmx = to_vmx(vcpu);
8770
8771         if (enable_pml)
8772                 vmx_destroy_pml_buffer(vmx);
8773         free_vpid(vmx->vpid);
8774         leave_guest_mode(vcpu);
8775         vmx_load_vmcs01(vcpu);
8776         free_nested(vmx);
8777         free_loaded_vmcs(vmx->loaded_vmcs);
8778         kfree(vmx->guest_msrs);
8779         kvm_vcpu_uninit(vcpu);
8780         kmem_cache_free(kvm_vcpu_cache, vmx);
8781 }
8782
8783 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8784 {
8785         int err;
8786         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8787         int cpu;
8788
8789         if (!vmx)
8790                 return ERR_PTR(-ENOMEM);
8791
8792         vmx->vpid = allocate_vpid();
8793
8794         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8795         if (err)
8796                 goto free_vcpu;
8797
8798         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8799         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8800                      > PAGE_SIZE);
8801
8802         err = -ENOMEM;
8803         if (!vmx->guest_msrs) {
8804                 goto uninit_vcpu;
8805         }
8806
8807         vmx->loaded_vmcs = &vmx->vmcs01;
8808         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8809         if (!vmx->loaded_vmcs->vmcs)
8810                 goto free_msrs;
8811         if (!vmm_exclusive)
8812                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8813         loaded_vmcs_init(vmx->loaded_vmcs);
8814         if (!vmm_exclusive)
8815                 kvm_cpu_vmxoff();
8816
8817         cpu = get_cpu();
8818         vmx_vcpu_load(&vmx->vcpu, cpu);
8819         vmx->vcpu.cpu = cpu;
8820         err = vmx_vcpu_setup(vmx);
8821         vmx_vcpu_put(&vmx->vcpu);
8822         put_cpu();
8823         if (err)
8824                 goto free_vmcs;
8825         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8826                 err = alloc_apic_access_page(kvm);
8827                 if (err)
8828                         goto free_vmcs;
8829         }
8830
8831         if (enable_ept) {
8832                 if (!kvm->arch.ept_identity_map_addr)
8833                         kvm->arch.ept_identity_map_addr =
8834                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8835                 err = init_rmode_identity_map(kvm);
8836                 if (err)
8837                         goto free_vmcs;
8838         }
8839
8840         if (nested) {
8841                 nested_vmx_setup_ctls_msrs(vmx);
8842                 vmx->nested.vpid02 = allocate_vpid();
8843         }
8844
8845         vmx->nested.posted_intr_nv = -1;
8846         vmx->nested.current_vmptr = -1ull;
8847         vmx->nested.current_vmcs12 = NULL;
8848
8849         /*
8850          * If PML is turned on, failure on enabling PML just results in failure
8851          * of creating the vcpu, therefore we can simplify PML logic (by
8852          * avoiding dealing with cases, such as enabling PML partially on vcpus
8853          * for the guest, etc.
8854          */
8855         if (enable_pml) {
8856                 err = vmx_create_pml_buffer(vmx);
8857                 if (err)
8858                         goto free_vmcs;
8859         }
8860
8861         return &vmx->vcpu;
8862
8863 free_vmcs:
8864         free_vpid(vmx->nested.vpid02);
8865         free_loaded_vmcs(vmx->loaded_vmcs);
8866 free_msrs:
8867         kfree(vmx->guest_msrs);
8868 uninit_vcpu:
8869         kvm_vcpu_uninit(&vmx->vcpu);
8870 free_vcpu:
8871         free_vpid(vmx->vpid);
8872         kmem_cache_free(kvm_vcpu_cache, vmx);
8873         return ERR_PTR(err);
8874 }
8875
8876 static void __init vmx_check_processor_compat(void *rtn)
8877 {
8878         struct vmcs_config vmcs_conf;
8879
8880         *(int *)rtn = 0;
8881         if (setup_vmcs_config(&vmcs_conf) < 0)
8882                 *(int *)rtn = -EIO;
8883         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8884                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8885                                 smp_processor_id());
8886                 *(int *)rtn = -EIO;
8887         }
8888 }
8889
8890 static int get_ept_level(void)
8891 {
8892         return VMX_EPT_DEFAULT_GAW + 1;
8893 }
8894
8895 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8896 {
8897         u8 cache;
8898         u64 ipat = 0;
8899
8900         /* For VT-d and EPT combination
8901          * 1. MMIO: always map as UC
8902          * 2. EPT with VT-d:
8903          *   a. VT-d without snooping control feature: can't guarantee the
8904          *      result, try to trust guest.
8905          *   b. VT-d with snooping control feature: snooping control feature of
8906          *      VT-d engine can guarantee the cache correctness. Just set it
8907          *      to WB to keep consistent with host. So the same as item 3.
8908          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8909          *    consistent with host MTRR
8910          */
8911         if (is_mmio) {
8912                 cache = MTRR_TYPE_UNCACHABLE;
8913                 goto exit;
8914         }
8915
8916         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8917                 ipat = VMX_EPT_IPAT_BIT;
8918                 cache = MTRR_TYPE_WRBACK;
8919                 goto exit;
8920         }
8921
8922         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8923                 ipat = VMX_EPT_IPAT_BIT;
8924                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8925                         cache = MTRR_TYPE_WRBACK;
8926                 else
8927                         cache = MTRR_TYPE_UNCACHABLE;
8928                 goto exit;
8929         }
8930
8931         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8932
8933 exit:
8934         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8935 }
8936
8937 static int vmx_get_lpage_level(void)
8938 {
8939         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8940                 return PT_DIRECTORY_LEVEL;
8941         else
8942                 /* For shadow and EPT supported 1GB page */
8943                 return PT_PDPE_LEVEL;
8944 }
8945
8946 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8947 {
8948         /*
8949          * These bits in the secondary execution controls field
8950          * are dynamic, the others are mostly based on the hypervisor
8951          * architecture and the guest's CPUID.  Do not touch the
8952          * dynamic bits.
8953          */
8954         u32 mask =
8955                 SECONDARY_EXEC_SHADOW_VMCS |
8956                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8957                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8958
8959         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8960
8961         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8962                      (new_ctl & ~mask) | (cur_ctl & mask));
8963 }
8964
8965 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8966 {
8967         struct kvm_cpuid_entry2 *best;
8968         struct vcpu_vmx *vmx = to_vmx(vcpu);
8969         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8970
8971         if (vmx_rdtscp_supported()) {
8972                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8973                 if (!rdtscp_enabled)
8974                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8975
8976                 if (nested) {
8977                         if (rdtscp_enabled)
8978                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8979                                         SECONDARY_EXEC_RDTSCP;
8980                         else
8981                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8982                                         ~SECONDARY_EXEC_RDTSCP;
8983                 }
8984         }
8985
8986         /* Exposing INVPCID only when PCID is exposed */
8987         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8988         if (vmx_invpcid_supported() &&
8989             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8990             !guest_cpuid_has_pcid(vcpu))) {
8991                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8992
8993                 if (best)
8994                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8995         }
8996
8997         if (cpu_has_secondary_exec_ctrls())
8998                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8999
9000         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9001                 if (guest_cpuid_has_pcommit(vcpu))
9002                         vmx->nested.nested_vmx_secondary_ctls_high |=
9003                                 SECONDARY_EXEC_PCOMMIT;
9004                 else
9005                         vmx->nested.nested_vmx_secondary_ctls_high &=
9006                                 ~SECONDARY_EXEC_PCOMMIT;
9007         }
9008 }
9009
9010 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9011 {
9012         if (func == 1 && nested)
9013                 entry->ecx |= bit(X86_FEATURE_VMX);
9014 }
9015
9016 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9017                 struct x86_exception *fault)
9018 {
9019         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9020         u32 exit_reason;
9021
9022         if (fault->error_code & PFERR_RSVD_MASK)
9023                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9024         else
9025                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9026         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9027         vmcs12->guest_physical_address = fault->address;
9028 }
9029
9030 /* Callbacks for nested_ept_init_mmu_context: */
9031
9032 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9033 {
9034         /* return the page table to be shadowed - in our case, EPT12 */
9035         return get_vmcs12(vcpu)->ept_pointer;
9036 }
9037
9038 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9039 {
9040         WARN_ON(mmu_is_nested(vcpu));
9041         kvm_init_shadow_ept_mmu(vcpu,
9042                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9043                         VMX_EPT_EXECUTE_ONLY_BIT);
9044         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9045         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9046         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9047
9048         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9049 }
9050
9051 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9052 {
9053         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9054 }
9055
9056 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9057                                             u16 error_code)
9058 {
9059         bool inequality, bit;
9060
9061         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9062         inequality =
9063                 (error_code & vmcs12->page_fault_error_code_mask) !=
9064                  vmcs12->page_fault_error_code_match;
9065         return inequality ^ bit;
9066 }
9067
9068 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9069                 struct x86_exception *fault)
9070 {
9071         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9072
9073         WARN_ON(!is_guest_mode(vcpu));
9074
9075         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9076                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9077                                   vmcs_read32(VM_EXIT_INTR_INFO),
9078                                   vmcs_readl(EXIT_QUALIFICATION));
9079         else
9080                 kvm_inject_page_fault(vcpu, fault);
9081 }
9082
9083 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9084                                         struct vmcs12 *vmcs12)
9085 {
9086         struct vcpu_vmx *vmx = to_vmx(vcpu);
9087         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9088
9089         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9091                     vmcs12->apic_access_addr >> maxphyaddr)
9092                         return false;
9093
9094                 /*
9095                  * Translate L1 physical address to host physical
9096                  * address for vmcs02. Keep the page pinned, so this
9097                  * physical address remains valid. We keep a reference
9098                  * to it so we can release it later.
9099                  */
9100                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9101                         nested_release_page(vmx->nested.apic_access_page);
9102                 vmx->nested.apic_access_page =
9103                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9104         }
9105
9106         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9107                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9108                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9109                         return false;
9110
9111                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9112                         nested_release_page(vmx->nested.virtual_apic_page);
9113                 vmx->nested.virtual_apic_page =
9114                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9115
9116                 /*
9117                  * Failing the vm entry is _not_ what the processor does
9118                  * but it's basically the only possibility we have.
9119                  * We could still enter the guest if CR8 load exits are
9120                  * enabled, CR8 store exits are enabled, and virtualize APIC
9121                  * access is disabled; in this case the processor would never
9122                  * use the TPR shadow and we could simply clear the bit from
9123                  * the execution control.  But such a configuration is useless,
9124                  * so let's keep the code simple.
9125                  */
9126                 if (!vmx->nested.virtual_apic_page)
9127                         return false;
9128         }
9129
9130         if (nested_cpu_has_posted_intr(vmcs12)) {
9131                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9132                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9133                         return false;
9134
9135                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9136                         kunmap(vmx->nested.pi_desc_page);
9137                         nested_release_page(vmx->nested.pi_desc_page);
9138                 }
9139                 vmx->nested.pi_desc_page =
9140                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9141                 if (!vmx->nested.pi_desc_page)
9142                         return false;
9143
9144                 vmx->nested.pi_desc =
9145                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9146                 if (!vmx->nested.pi_desc) {
9147                         nested_release_page_clean(vmx->nested.pi_desc_page);
9148                         return false;
9149                 }
9150                 vmx->nested.pi_desc =
9151                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9152                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9153                         (PAGE_SIZE - 1)));
9154         }
9155
9156         return true;
9157 }
9158
9159 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9160 {
9161         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9162         struct vcpu_vmx *vmx = to_vmx(vcpu);
9163
9164         if (vcpu->arch.virtual_tsc_khz == 0)
9165                 return;
9166
9167         /* Make sure short timeouts reliably trigger an immediate vmexit.
9168          * hrtimer_start does not guarantee this. */
9169         if (preemption_timeout <= 1) {
9170                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9171                 return;
9172         }
9173
9174         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9175         preemption_timeout *= 1000000;
9176         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9177         hrtimer_start(&vmx->nested.preemption_timer,
9178                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9179 }
9180
9181 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9182                                                 struct vmcs12 *vmcs12)
9183 {
9184         int maxphyaddr;
9185         u64 addr;
9186
9187         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9188                 return 0;
9189
9190         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9191                 WARN_ON(1);
9192                 return -EINVAL;
9193         }
9194         maxphyaddr = cpuid_maxphyaddr(vcpu);
9195
9196         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9197            ((addr + PAGE_SIZE) >> maxphyaddr))
9198                 return -EINVAL;
9199
9200         return 0;
9201 }
9202
9203 /*
9204  * Merge L0's and L1's MSR bitmap, return false to indicate that
9205  * we do not use the hardware.
9206  */
9207 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9208                                                struct vmcs12 *vmcs12)
9209 {
9210         int msr;
9211         struct page *page;
9212         unsigned long *msr_bitmap;
9213
9214         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9215                 return false;
9216
9217         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9218         if (!page) {
9219                 WARN_ON(1);
9220                 return false;
9221         }
9222         msr_bitmap = (unsigned long *)kmap(page);
9223         if (!msr_bitmap) {
9224                 nested_release_page_clean(page);
9225                 WARN_ON(1);
9226                 return false;
9227         }
9228
9229         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9230                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9231                         for (msr = 0x800; msr <= 0x8ff; msr++)
9232                                 nested_vmx_disable_intercept_for_msr(
9233                                         msr_bitmap,
9234                                         vmx_msr_bitmap_nested,
9235                                         msr, MSR_TYPE_R);
9236                 /* TPR is allowed */
9237                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9238                                 vmx_msr_bitmap_nested,
9239                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9240                                 MSR_TYPE_R | MSR_TYPE_W);
9241                 if (nested_cpu_has_vid(vmcs12)) {
9242                         /* EOI and self-IPI are allowed */
9243                         nested_vmx_disable_intercept_for_msr(
9244                                 msr_bitmap,
9245                                 vmx_msr_bitmap_nested,
9246                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9247                                 MSR_TYPE_W);
9248                         nested_vmx_disable_intercept_for_msr(
9249                                 msr_bitmap,
9250                                 vmx_msr_bitmap_nested,
9251                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9252                                 MSR_TYPE_W);
9253                 }
9254         } else {
9255                 /*
9256                  * Enable reading intercept of all the x2apic
9257                  * MSRs. We should not rely on vmcs12 to do any
9258                  * optimizations here, it may have been modified
9259                  * by L1.
9260                  */
9261                 for (msr = 0x800; msr <= 0x8ff; msr++)
9262                         __vmx_enable_intercept_for_msr(
9263                                 vmx_msr_bitmap_nested,
9264                                 msr,
9265                                 MSR_TYPE_R);
9266
9267                 __vmx_enable_intercept_for_msr(
9268                                 vmx_msr_bitmap_nested,
9269                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9270                                 MSR_TYPE_W);
9271                 __vmx_enable_intercept_for_msr(
9272                                 vmx_msr_bitmap_nested,
9273                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9274                                 MSR_TYPE_W);
9275                 __vmx_enable_intercept_for_msr(
9276                                 vmx_msr_bitmap_nested,
9277                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9278                                 MSR_TYPE_W);
9279         }
9280         kunmap(page);
9281         nested_release_page_clean(page);
9282
9283         return true;
9284 }
9285
9286 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9287                                            struct vmcs12 *vmcs12)
9288 {
9289         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9290             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9291             !nested_cpu_has_vid(vmcs12) &&
9292             !nested_cpu_has_posted_intr(vmcs12))
9293                 return 0;
9294
9295         /*
9296          * If virtualize x2apic mode is enabled,
9297          * virtualize apic access must be disabled.
9298          */
9299         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9300             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9301                 return -EINVAL;
9302
9303         /*
9304          * If virtual interrupt delivery is enabled,
9305          * we must exit on external interrupts.
9306          */
9307         if (nested_cpu_has_vid(vmcs12) &&
9308            !nested_exit_on_intr(vcpu))
9309                 return -EINVAL;
9310
9311         /*
9312          * bits 15:8 should be zero in posted_intr_nv,
9313          * the descriptor address has been already checked
9314          * in nested_get_vmcs12_pages.
9315          */
9316         if (nested_cpu_has_posted_intr(vmcs12) &&
9317            (!nested_cpu_has_vid(vmcs12) ||
9318             !nested_exit_intr_ack_set(vcpu) ||
9319             vmcs12->posted_intr_nv & 0xff00))
9320                 return -EINVAL;
9321
9322         /* tpr shadow is needed by all apicv features. */
9323         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9324                 return -EINVAL;
9325
9326         return 0;
9327 }
9328
9329 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9330                                        unsigned long count_field,
9331                                        unsigned long addr_field)
9332 {
9333         int maxphyaddr;
9334         u64 count, addr;
9335
9336         if (vmcs12_read_any(vcpu, count_field, &count) ||
9337             vmcs12_read_any(vcpu, addr_field, &addr)) {
9338                 WARN_ON(1);
9339                 return -EINVAL;
9340         }
9341         if (count == 0)
9342                 return 0;
9343         maxphyaddr = cpuid_maxphyaddr(vcpu);
9344         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9345             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9346                 pr_warn_ratelimited(
9347                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9348                         addr_field, maxphyaddr, count, addr);
9349                 return -EINVAL;
9350         }
9351         return 0;
9352 }
9353
9354 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9355                                                 struct vmcs12 *vmcs12)
9356 {
9357         if (vmcs12->vm_exit_msr_load_count == 0 &&
9358             vmcs12->vm_exit_msr_store_count == 0 &&
9359             vmcs12->vm_entry_msr_load_count == 0)
9360                 return 0; /* Fast path */
9361         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9362                                         VM_EXIT_MSR_LOAD_ADDR) ||
9363             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9364                                         VM_EXIT_MSR_STORE_ADDR) ||
9365             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9366                                         VM_ENTRY_MSR_LOAD_ADDR))
9367                 return -EINVAL;
9368         return 0;
9369 }
9370
9371 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9372                                        struct vmx_msr_entry *e)
9373 {
9374         /* x2APIC MSR accesses are not allowed */
9375         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9376                 return -EINVAL;
9377         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9378             e->index == MSR_IA32_UCODE_REV)
9379                 return -EINVAL;
9380         if (e->reserved != 0)
9381                 return -EINVAL;
9382         return 0;
9383 }
9384
9385 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9386                                      struct vmx_msr_entry *e)
9387 {
9388         if (e->index == MSR_FS_BASE ||
9389             e->index == MSR_GS_BASE ||
9390             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9391             nested_vmx_msr_check_common(vcpu, e))
9392                 return -EINVAL;
9393         return 0;
9394 }
9395
9396 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9397                                       struct vmx_msr_entry *e)
9398 {
9399         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9400             nested_vmx_msr_check_common(vcpu, e))
9401                 return -EINVAL;
9402         return 0;
9403 }
9404
9405 /*
9406  * Load guest's/host's msr at nested entry/exit.
9407  * return 0 for success, entry index for failure.
9408  */
9409 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9410 {
9411         u32 i;
9412         struct vmx_msr_entry e;
9413         struct msr_data msr;
9414
9415         msr.host_initiated = false;
9416         for (i = 0; i < count; i++) {
9417                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9418                                         &e, sizeof(e))) {
9419                         pr_warn_ratelimited(
9420                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9421                                 __func__, i, gpa + i * sizeof(e));
9422                         goto fail;
9423                 }
9424                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9425                         pr_warn_ratelimited(
9426                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9427                                 __func__, i, e.index, e.reserved);
9428                         goto fail;
9429                 }
9430                 msr.index = e.index;
9431                 msr.data = e.value;
9432                 if (kvm_set_msr(vcpu, &msr)) {
9433                         pr_warn_ratelimited(
9434                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9435                                 __func__, i, e.index, e.value);
9436                         goto fail;
9437                 }
9438         }
9439         return 0;
9440 fail:
9441         return i + 1;
9442 }
9443
9444 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9445 {
9446         u32 i;
9447         struct vmx_msr_entry e;
9448
9449         for (i = 0; i < count; i++) {
9450                 struct msr_data msr_info;
9451                 if (kvm_vcpu_read_guest(vcpu,
9452                                         gpa + i * sizeof(e),
9453                                         &e, 2 * sizeof(u32))) {
9454                         pr_warn_ratelimited(
9455                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9456                                 __func__, i, gpa + i * sizeof(e));
9457                         return -EINVAL;
9458                 }
9459                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9460                         pr_warn_ratelimited(
9461                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9462                                 __func__, i, e.index, e.reserved);
9463                         return -EINVAL;
9464                 }
9465                 msr_info.host_initiated = false;
9466                 msr_info.index = e.index;
9467                 if (kvm_get_msr(vcpu, &msr_info)) {
9468                         pr_warn_ratelimited(
9469                                 "%s cannot read MSR (%u, 0x%x)\n",
9470                                 __func__, i, e.index);
9471                         return -EINVAL;
9472                 }
9473                 if (kvm_vcpu_write_guest(vcpu,
9474                                          gpa + i * sizeof(e) +
9475                                              offsetof(struct vmx_msr_entry, value),
9476                                          &msr_info.data, sizeof(msr_info.data))) {
9477                         pr_warn_ratelimited(
9478                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9479                                 __func__, i, e.index, msr_info.data);
9480                         return -EINVAL;
9481                 }
9482         }
9483         return 0;
9484 }
9485
9486 /*
9487  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9488  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9489  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9490  * guest in a way that will both be appropriate to L1's requests, and our
9491  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9492  * function also has additional necessary side-effects, like setting various
9493  * vcpu->arch fields.
9494  */
9495 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9496 {
9497         struct vcpu_vmx *vmx = to_vmx(vcpu);
9498         u32 exec_control;
9499
9500         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9501         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9502         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9503         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9504         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9505         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9506         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9507         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9508         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9509         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9510         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9511         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9512         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9513         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9514         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9515         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9516         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9517         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9518         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9519         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9520         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9521         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9522         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9523         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9524         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9525         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9526         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9527         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9528         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9529         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9530         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9531         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9532         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9533         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9534         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9535         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9536
9537         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9538                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9539                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9540         } else {
9541                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9542                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9543         }
9544         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9545                 vmcs12->vm_entry_intr_info_field);
9546         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9547                 vmcs12->vm_entry_exception_error_code);
9548         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9549                 vmcs12->vm_entry_instruction_len);
9550         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9551                 vmcs12->guest_interruptibility_info);
9552         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9553         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9554         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9555                 vmcs12->guest_pending_dbg_exceptions);
9556         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9557         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9558
9559         if (nested_cpu_has_xsaves(vmcs12))
9560                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9561         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9562
9563         exec_control = vmcs12->pin_based_vm_exec_control;
9564         exec_control |= vmcs_config.pin_based_exec_ctrl;
9565         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9566
9567         if (nested_cpu_has_posted_intr(vmcs12)) {
9568                 /*
9569                  * Note that we use L0's vector here and in
9570                  * vmx_deliver_nested_posted_interrupt.
9571                  */
9572                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9573                 vmx->nested.pi_pending = false;
9574                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9575                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9576                         page_to_phys(vmx->nested.pi_desc_page) +
9577                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9578                         (PAGE_SIZE - 1)));
9579         } else
9580                 exec_control &= ~PIN_BASED_POSTED_INTR;
9581
9582         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9583
9584         vmx->nested.preemption_timer_expired = false;
9585         if (nested_cpu_has_preemption_timer(vmcs12))
9586                 vmx_start_preemption_timer(vcpu);
9587
9588         /*
9589          * Whether page-faults are trapped is determined by a combination of
9590          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9591          * If enable_ept, L0 doesn't care about page faults and we should
9592          * set all of these to L1's desires. However, if !enable_ept, L0 does
9593          * care about (at least some) page faults, and because it is not easy
9594          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9595          * to exit on each and every L2 page fault. This is done by setting
9596          * MASK=MATCH=0 and (see below) EB.PF=1.
9597          * Note that below we don't need special code to set EB.PF beyond the
9598          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9599          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9600          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9601          *
9602          * A problem with this approach (when !enable_ept) is that L1 may be
9603          * injected with more page faults than it asked for. This could have
9604          * caused problems, but in practice existing hypervisors don't care.
9605          * To fix this, we will need to emulate the PFEC checking (on the L1
9606          * page tables), using walk_addr(), when injecting PFs to L1.
9607          */
9608         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9609                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9610         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9611                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9612
9613         if (cpu_has_secondary_exec_ctrls()) {
9614                 exec_control = vmx_secondary_exec_control(vmx);
9615
9616                 /* Take the following fields only from vmcs12 */
9617                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9618                                   SECONDARY_EXEC_RDTSCP |
9619                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9620                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9621                                   SECONDARY_EXEC_PCOMMIT);
9622                 if (nested_cpu_has(vmcs12,
9623                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9624                         exec_control |= vmcs12->secondary_vm_exec_control;
9625
9626                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9627                         /*
9628                          * If translation failed, no matter: This feature asks
9629                          * to exit when accessing the given address, and if it
9630                          * can never be accessed, this feature won't do
9631                          * anything anyway.
9632                          */
9633                         if (!vmx->nested.apic_access_page)
9634                                 exec_control &=
9635                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9636                         else
9637                                 vmcs_write64(APIC_ACCESS_ADDR,
9638                                   page_to_phys(vmx->nested.apic_access_page));
9639                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9640                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9641                         exec_control |=
9642                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9643                         kvm_vcpu_reload_apic_access_page(vcpu);
9644                 }
9645
9646                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9647                         vmcs_write64(EOI_EXIT_BITMAP0,
9648                                 vmcs12->eoi_exit_bitmap0);
9649                         vmcs_write64(EOI_EXIT_BITMAP1,
9650                                 vmcs12->eoi_exit_bitmap1);
9651                         vmcs_write64(EOI_EXIT_BITMAP2,
9652                                 vmcs12->eoi_exit_bitmap2);
9653                         vmcs_write64(EOI_EXIT_BITMAP3,
9654                                 vmcs12->eoi_exit_bitmap3);
9655                         vmcs_write16(GUEST_INTR_STATUS,
9656                                 vmcs12->guest_intr_status);
9657                 }
9658
9659                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9660         }
9661
9662
9663         /*
9664          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9665          * Some constant fields are set here by vmx_set_constant_host_state().
9666          * Other fields are different per CPU, and will be set later when
9667          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9668          */
9669         vmx_set_constant_host_state(vmx);
9670
9671         /*
9672          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9673          * entry, but only if the current (host) sp changed from the value
9674          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9675          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9676          * here we just force the write to happen on entry.
9677          */
9678         vmx->host_rsp = 0;
9679
9680         exec_control = vmx_exec_control(vmx); /* L0's desires */
9681         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9682         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9683         exec_control &= ~CPU_BASED_TPR_SHADOW;
9684         exec_control |= vmcs12->cpu_based_vm_exec_control;
9685
9686         if (exec_control & CPU_BASED_TPR_SHADOW) {
9687                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9688                                 page_to_phys(vmx->nested.virtual_apic_page));
9689                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9690         }
9691
9692         if (cpu_has_vmx_msr_bitmap() &&
9693             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9694                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9695                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9696         } else
9697                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9698
9699         /*
9700          * Merging of IO bitmap not currently supported.
9701          * Rather, exit every time.
9702          */
9703         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9704         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9705
9706         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9707
9708         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9709          * bitwise-or of what L1 wants to trap for L2, and what we want to
9710          * trap. Note that CR0.TS also needs updating - we do this later.
9711          */
9712         update_exception_bitmap(vcpu);
9713         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9714         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9715
9716         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9717          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9718          * bits are further modified by vmx_set_efer() below.
9719          */
9720         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9721
9722         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9723          * emulated by vmx_set_efer(), below.
9724          */
9725         vm_entry_controls_init(vmx,
9726                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9727                         ~VM_ENTRY_IA32E_MODE) |
9728                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9729
9730         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9731                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9732                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9733         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9734                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9735
9736
9737         set_cr4_guest_host_mask(vmx);
9738
9739         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9740                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9741
9742         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9743                 vmcs_write64(TSC_OFFSET,
9744                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9745         else
9746                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9747
9748         if (enable_vpid) {
9749                 /*
9750                  * There is no direct mapping between vpid02 and vpid12, the
9751                  * vpid02 is per-vCPU for L0 and reused while the value of
9752                  * vpid12 is changed w/ one invvpid during nested vmentry.
9753                  * The vpid12 is allocated by L1 for L2, so it will not
9754                  * influence global bitmap(for vpid01 and vpid02 allocation)
9755                  * even if spawn a lot of nested vCPUs.
9756                  */
9757                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9758                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9759                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9760                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9761                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9762                         }
9763                 } else {
9764                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9765                         vmx_flush_tlb(vcpu);
9766                 }
9767
9768         }
9769
9770         if (nested_cpu_has_ept(vmcs12)) {
9771                 kvm_mmu_unload(vcpu);
9772                 nested_ept_init_mmu_context(vcpu);
9773         }
9774
9775         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9776                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9777         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9778                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9779         else
9780                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9781         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9782         vmx_set_efer(vcpu, vcpu->arch.efer);
9783
9784         /*
9785          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9786          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9787          * The CR0_READ_SHADOW is what L2 should have expected to read given
9788          * the specifications by L1; It's not enough to take
9789          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9790          * have more bits than L1 expected.
9791          */
9792         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9793         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9794
9795         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9796         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9797
9798         /* shadow page tables on either EPT or shadow page tables */
9799         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9800         kvm_mmu_reset_context(vcpu);
9801
9802         if (!enable_ept)
9803                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9804
9805         /*
9806          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9807          */
9808         if (enable_ept) {
9809                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9810                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9811                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9812                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9813         }
9814
9815         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9816         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9817 }
9818
9819 /*
9820  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9821  * for running an L2 nested guest.
9822  */
9823 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9824 {
9825         struct vmcs12 *vmcs12;
9826         struct vcpu_vmx *vmx = to_vmx(vcpu);
9827         int cpu;
9828         struct loaded_vmcs *vmcs02;
9829         bool ia32e;
9830         u32 msr_entry_idx;
9831
9832         if (!nested_vmx_check_permission(vcpu) ||
9833             !nested_vmx_check_vmcs12(vcpu))
9834                 return 1;
9835
9836         skip_emulated_instruction(vcpu);
9837         vmcs12 = get_vmcs12(vcpu);
9838
9839         if (enable_shadow_vmcs)
9840                 copy_shadow_to_vmcs12(vmx);
9841
9842         /*
9843          * The nested entry process starts with enforcing various prerequisites
9844          * on vmcs12 as required by the Intel SDM, and act appropriately when
9845          * they fail: As the SDM explains, some conditions should cause the
9846          * instruction to fail, while others will cause the instruction to seem
9847          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9848          * To speed up the normal (success) code path, we should avoid checking
9849          * for misconfigurations which will anyway be caught by the processor
9850          * when using the merged vmcs02.
9851          */
9852         if (vmcs12->launch_state == launch) {
9853                 nested_vmx_failValid(vcpu,
9854                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9855                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9856                 return 1;
9857         }
9858
9859         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9860             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9861                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9862                 return 1;
9863         }
9864
9865         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9866                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9867                 return 1;
9868         }
9869
9870         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9871                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9872                 return 1;
9873         }
9874
9875         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9876                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9877                 return 1;
9878         }
9879
9880         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9881                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9882                 return 1;
9883         }
9884
9885         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9886                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9887                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9888             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9889                                 vmx->nested.nested_vmx_secondary_ctls_low,
9890                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9891             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9892                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9893                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9894             !vmx_control_verify(vmcs12->vm_exit_controls,
9895                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9896                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9897             !vmx_control_verify(vmcs12->vm_entry_controls,
9898                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9899                                 vmx->nested.nested_vmx_entry_ctls_high))
9900         {
9901                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9902                 return 1;
9903         }
9904
9905         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9906             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9907                 nested_vmx_failValid(vcpu,
9908                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9909                 return 1;
9910         }
9911
9912         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9913             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9914                 nested_vmx_entry_failure(vcpu, vmcs12,
9915                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9916                 return 1;
9917         }
9918         if (vmcs12->vmcs_link_pointer != -1ull) {
9919                 nested_vmx_entry_failure(vcpu, vmcs12,
9920                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9921                 return 1;
9922         }
9923
9924         /*
9925          * If the load IA32_EFER VM-entry control is 1, the following checks
9926          * are performed on the field for the IA32_EFER MSR:
9927          * - Bits reserved in the IA32_EFER MSR must be 0.
9928          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9929          *   the IA-32e mode guest VM-exit control. It must also be identical
9930          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9931          *   CR0.PG) is 1.
9932          */
9933         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9934                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9935                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9936                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9937                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9938                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9939                         nested_vmx_entry_failure(vcpu, vmcs12,
9940                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9941                         return 1;
9942                 }
9943         }
9944
9945         /*
9946          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9947          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9948          * the values of the LMA and LME bits in the field must each be that of
9949          * the host address-space size VM-exit control.
9950          */
9951         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9952                 ia32e = (vmcs12->vm_exit_controls &
9953                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9954                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9955                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9956                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9957                         nested_vmx_entry_failure(vcpu, vmcs12,
9958                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9959                         return 1;
9960                 }
9961         }
9962
9963         /*
9964          * We're finally done with prerequisite checking, and can start with
9965          * the nested entry.
9966          */
9967
9968         vmcs02 = nested_get_current_vmcs02(vmx);
9969         if (!vmcs02)
9970                 return -ENOMEM;
9971
9972         enter_guest_mode(vcpu);
9973
9974         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9975
9976         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9977                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9978
9979         cpu = get_cpu();
9980         vmx->loaded_vmcs = vmcs02;
9981         vmx_vcpu_put(vcpu);
9982         vmx_vcpu_load(vcpu, cpu);
9983         vcpu->cpu = cpu;
9984         put_cpu();
9985
9986         vmx_segment_cache_clear(vmx);
9987
9988         prepare_vmcs02(vcpu, vmcs12);
9989
9990         msr_entry_idx = nested_vmx_load_msr(vcpu,
9991                                             vmcs12->vm_entry_msr_load_addr,
9992                                             vmcs12->vm_entry_msr_load_count);
9993         if (msr_entry_idx) {
9994                 leave_guest_mode(vcpu);
9995                 vmx_load_vmcs01(vcpu);
9996                 nested_vmx_entry_failure(vcpu, vmcs12,
9997                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9998                 return 1;
9999         }
10000
10001         vmcs12->launch_state = 1;
10002
10003         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10004                 return kvm_vcpu_halt(vcpu);
10005
10006         vmx->nested.nested_run_pending = 1;
10007
10008         /*
10009          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10010          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10011          * returned as far as L1 is concerned. It will only return (and set
10012          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10013          */
10014         return 1;
10015 }
10016
10017 /*
10018  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10019  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10020  * This function returns the new value we should put in vmcs12.guest_cr0.
10021  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10022  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10023  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10024  *     didn't trap the bit, because if L1 did, so would L0).
10025  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10026  *     been modified by L2, and L1 knows it. So just leave the old value of
10027  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10028  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10029  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10030  *     changed these bits, and therefore they need to be updated, but L0
10031  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10032  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10033  */
10034 static inline unsigned long
10035 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10036 {
10037         return
10038         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10039         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10040         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10041                         vcpu->arch.cr0_guest_owned_bits));
10042 }
10043
10044 static inline unsigned long
10045 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10046 {
10047         return
10048         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10049         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10050         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10051                         vcpu->arch.cr4_guest_owned_bits));
10052 }
10053
10054 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10055                                        struct vmcs12 *vmcs12)
10056 {
10057         u32 idt_vectoring;
10058         unsigned int nr;
10059
10060         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10061                 nr = vcpu->arch.exception.nr;
10062                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10063
10064                 if (kvm_exception_is_soft(nr)) {
10065                         vmcs12->vm_exit_instruction_len =
10066                                 vcpu->arch.event_exit_inst_len;
10067                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10068                 } else
10069                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10070
10071                 if (vcpu->arch.exception.has_error_code) {
10072                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10073                         vmcs12->idt_vectoring_error_code =
10074                                 vcpu->arch.exception.error_code;
10075                 }
10076
10077                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10078         } else if (vcpu->arch.nmi_injected) {
10079                 vmcs12->idt_vectoring_info_field =
10080                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10081         } else if (vcpu->arch.interrupt.pending) {
10082                 nr = vcpu->arch.interrupt.nr;
10083                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10084
10085                 if (vcpu->arch.interrupt.soft) {
10086                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10087                         vmcs12->vm_entry_instruction_len =
10088                                 vcpu->arch.event_exit_inst_len;
10089                 } else
10090                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10091
10092                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10093         }
10094 }
10095
10096 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10097 {
10098         struct vcpu_vmx *vmx = to_vmx(vcpu);
10099
10100         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10101             vmx->nested.preemption_timer_expired) {
10102                 if (vmx->nested.nested_run_pending)
10103                         return -EBUSY;
10104                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10105                 return 0;
10106         }
10107
10108         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10109                 if (vmx->nested.nested_run_pending ||
10110                     vcpu->arch.interrupt.pending)
10111                         return -EBUSY;
10112                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10113                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10114                                   INTR_INFO_VALID_MASK, 0);
10115                 /*
10116                  * The NMI-triggered VM exit counts as injection:
10117                  * clear this one and block further NMIs.
10118                  */
10119                 vcpu->arch.nmi_pending = 0;
10120                 vmx_set_nmi_mask(vcpu, true);
10121                 return 0;
10122         }
10123
10124         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10125             nested_exit_on_intr(vcpu)) {
10126                 if (vmx->nested.nested_run_pending)
10127                         return -EBUSY;
10128                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10129                 return 0;
10130         }
10131
10132         return vmx_complete_nested_posted_interrupt(vcpu);
10133 }
10134
10135 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10136 {
10137         ktime_t remaining =
10138                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10139         u64 value;
10140
10141         if (ktime_to_ns(remaining) <= 0)
10142                 return 0;
10143
10144         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10145         do_div(value, 1000000);
10146         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10147 }
10148
10149 /*
10150  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10151  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10152  * and this function updates it to reflect the changes to the guest state while
10153  * L2 was running (and perhaps made some exits which were handled directly by L0
10154  * without going back to L1), and to reflect the exit reason.
10155  * Note that we do not have to copy here all VMCS fields, just those that
10156  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10157  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10158  * which already writes to vmcs12 directly.
10159  */
10160 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10161                            u32 exit_reason, u32 exit_intr_info,
10162                            unsigned long exit_qualification)
10163 {
10164         /* update guest state fields: */
10165         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10166         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10167
10168         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10169         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10170         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10171
10172         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10173         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10174         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10175         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10176         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10177         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10178         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10179         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10180         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10181         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10182         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10183         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10184         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10185         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10186         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10187         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10188         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10189         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10190         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10191         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10192         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10193         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10194         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10195         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10196         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10197         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10198         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10199         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10200         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10201         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10202         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10203         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10204         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10205         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10206         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10207         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10208
10209         vmcs12->guest_interruptibility_info =
10210                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10211         vmcs12->guest_pending_dbg_exceptions =
10212                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10213         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10214                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10215         else
10216                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10217
10218         if (nested_cpu_has_preemption_timer(vmcs12)) {
10219                 if (vmcs12->vm_exit_controls &
10220                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10221                         vmcs12->vmx_preemption_timer_value =
10222                                 vmx_get_preemption_timer_value(vcpu);
10223                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10224         }
10225
10226         /*
10227          * In some cases (usually, nested EPT), L2 is allowed to change its
10228          * own CR3 without exiting. If it has changed it, we must keep it.
10229          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10230          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10231          *
10232          * Additionally, restore L2's PDPTR to vmcs12.
10233          */
10234         if (enable_ept) {
10235                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10236                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10237                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10238                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10239                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10240         }
10241
10242         if (nested_cpu_has_vid(vmcs12))
10243                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10244
10245         vmcs12->vm_entry_controls =
10246                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10247                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10248
10249         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10250                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10251                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10252         }
10253
10254         /* TODO: These cannot have changed unless we have MSR bitmaps and
10255          * the relevant bit asks not to trap the change */
10256         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10257                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10258         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10259                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10260         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10261         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10262         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10263         if (vmx_mpx_supported())
10264                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10265         if (nested_cpu_has_xsaves(vmcs12))
10266                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10267
10268         /* update exit information fields: */
10269
10270         vmcs12->vm_exit_reason = exit_reason;
10271         vmcs12->exit_qualification = exit_qualification;
10272
10273         vmcs12->vm_exit_intr_info = exit_intr_info;
10274         if ((vmcs12->vm_exit_intr_info &
10275              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10276             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10277                 vmcs12->vm_exit_intr_error_code =
10278                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10279         vmcs12->idt_vectoring_info_field = 0;
10280         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10281         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10282
10283         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10284                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10285                  * instead of reading the real value. */
10286                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10287
10288                 /*
10289                  * Transfer the event that L0 or L1 may wanted to inject into
10290                  * L2 to IDT_VECTORING_INFO_FIELD.
10291                  */
10292                 vmcs12_save_pending_event(vcpu, vmcs12);
10293         }
10294
10295         /*
10296          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10297          * preserved above and would only end up incorrectly in L1.
10298          */
10299         vcpu->arch.nmi_injected = false;
10300         kvm_clear_exception_queue(vcpu);
10301         kvm_clear_interrupt_queue(vcpu);
10302 }
10303
10304 /*
10305  * A part of what we need to when the nested L2 guest exits and we want to
10306  * run its L1 parent, is to reset L1's guest state to the host state specified
10307  * in vmcs12.
10308  * This function is to be called not only on normal nested exit, but also on
10309  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10310  * Failures During or After Loading Guest State").
10311  * This function should be called when the active VMCS is L1's (vmcs01).
10312  */
10313 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10314                                    struct vmcs12 *vmcs12)
10315 {
10316         struct kvm_segment seg;
10317
10318         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10319                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10320         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10321                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10322         else
10323                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10324         vmx_set_efer(vcpu, vcpu->arch.efer);
10325
10326         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10327         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10328         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10329         /*
10330          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10331          * actually changed, because it depends on the current state of
10332          * fpu_active (which may have changed).
10333          * Note that vmx_set_cr0 refers to efer set above.
10334          */
10335         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10336         /*
10337          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10338          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10339          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10340          */
10341         update_exception_bitmap(vcpu);
10342         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10343         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10344
10345         /*
10346          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10347          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10348          */
10349         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10350         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10351
10352         nested_ept_uninit_mmu_context(vcpu);
10353
10354         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10355         kvm_mmu_reset_context(vcpu);
10356
10357         if (!enable_ept)
10358                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10359
10360         if (enable_vpid) {
10361                 /*
10362                  * Trivially support vpid by letting L2s share their parent
10363                  * L1's vpid. TODO: move to a more elaborate solution, giving
10364                  * each L2 its own vpid and exposing the vpid feature to L1.
10365                  */
10366                 vmx_flush_tlb(vcpu);
10367         }
10368
10369
10370         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10371         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10372         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10373         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10374         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10375
10376         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10377         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10378                 vmcs_write64(GUEST_BNDCFGS, 0);
10379
10380         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10381                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10382                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10383         }
10384         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10385                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10386                         vmcs12->host_ia32_perf_global_ctrl);
10387
10388         /* Set L1 segment info according to Intel SDM
10389             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10390         seg = (struct kvm_segment) {
10391                 .base = 0,
10392                 .limit = 0xFFFFFFFF,
10393                 .selector = vmcs12->host_cs_selector,
10394                 .type = 11,
10395                 .present = 1,
10396                 .s = 1,
10397                 .g = 1
10398         };
10399         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10400                 seg.l = 1;
10401         else
10402                 seg.db = 1;
10403         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10404         seg = (struct kvm_segment) {
10405                 .base = 0,
10406                 .limit = 0xFFFFFFFF,
10407                 .type = 3,
10408                 .present = 1,
10409                 .s = 1,
10410                 .db = 1,
10411                 .g = 1
10412         };
10413         seg.selector = vmcs12->host_ds_selector;
10414         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10415         seg.selector = vmcs12->host_es_selector;
10416         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10417         seg.selector = vmcs12->host_ss_selector;
10418         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10419         seg.selector = vmcs12->host_fs_selector;
10420         seg.base = vmcs12->host_fs_base;
10421         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10422         seg.selector = vmcs12->host_gs_selector;
10423         seg.base = vmcs12->host_gs_base;
10424         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10425         seg = (struct kvm_segment) {
10426                 .base = vmcs12->host_tr_base,
10427                 .limit = 0x67,
10428                 .selector = vmcs12->host_tr_selector,
10429                 .type = 11,
10430                 .present = 1
10431         };
10432         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10433
10434         kvm_set_dr(vcpu, 7, 0x400);
10435         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10436
10437         if (cpu_has_vmx_msr_bitmap())
10438                 vmx_set_msr_bitmap(vcpu);
10439
10440         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10441                                 vmcs12->vm_exit_msr_load_count))
10442                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10443 }
10444
10445 /*
10446  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10447  * and modify vmcs12 to make it see what it would expect to see there if
10448  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10449  */
10450 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10451                               u32 exit_intr_info,
10452                               unsigned long exit_qualification)
10453 {
10454         struct vcpu_vmx *vmx = to_vmx(vcpu);
10455         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10456
10457         /* trying to cancel vmlaunch/vmresume is a bug */
10458         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10459
10460         leave_guest_mode(vcpu);
10461         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10462                        exit_qualification);
10463
10464         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10465                                  vmcs12->vm_exit_msr_store_count))
10466                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10467
10468         vmx_load_vmcs01(vcpu);
10469
10470         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10471             && nested_exit_intr_ack_set(vcpu)) {
10472                 int irq = kvm_cpu_get_interrupt(vcpu);
10473                 WARN_ON(irq < 0);
10474                 vmcs12->vm_exit_intr_info = irq |
10475                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10476         }
10477
10478         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10479                                        vmcs12->exit_qualification,
10480                                        vmcs12->idt_vectoring_info_field,
10481                                        vmcs12->vm_exit_intr_info,
10482                                        vmcs12->vm_exit_intr_error_code,
10483                                        KVM_ISA_VMX);
10484
10485         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10486         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10487         vmx_segment_cache_clear(vmx);
10488
10489         /* if no vmcs02 cache requested, remove the one we used */
10490         if (VMCS02_POOL_SIZE == 0)
10491                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10492
10493         load_vmcs12_host_state(vcpu, vmcs12);
10494
10495         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10496         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10497
10498         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10499         vmx->host_rsp = 0;
10500
10501         /* Unpin physical memory we referred to in vmcs02 */
10502         if (vmx->nested.apic_access_page) {
10503                 nested_release_page(vmx->nested.apic_access_page);
10504                 vmx->nested.apic_access_page = NULL;
10505         }
10506         if (vmx->nested.virtual_apic_page) {
10507                 nested_release_page(vmx->nested.virtual_apic_page);
10508                 vmx->nested.virtual_apic_page = NULL;
10509         }
10510         if (vmx->nested.pi_desc_page) {
10511                 kunmap(vmx->nested.pi_desc_page);
10512                 nested_release_page(vmx->nested.pi_desc_page);
10513                 vmx->nested.pi_desc_page = NULL;
10514                 vmx->nested.pi_desc = NULL;
10515         }
10516
10517         /*
10518          * We are now running in L2, mmu_notifier will force to reload the
10519          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10520          */
10521         kvm_vcpu_reload_apic_access_page(vcpu);
10522
10523         /*
10524          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10525          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10526          * success or failure flag accordingly.
10527          */
10528         if (unlikely(vmx->fail)) {
10529                 vmx->fail = 0;
10530                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10531         } else
10532                 nested_vmx_succeed(vcpu);
10533         if (enable_shadow_vmcs)
10534                 vmx->nested.sync_shadow_vmcs = true;
10535
10536         /* in case we halted in L2 */
10537         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10538 }
10539
10540 /*
10541  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10542  */
10543 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10544 {
10545         if (is_guest_mode(vcpu))
10546                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10547         free_nested(to_vmx(vcpu));
10548 }
10549
10550 /*
10551  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10552  * 23.7 "VM-entry failures during or after loading guest state" (this also
10553  * lists the acceptable exit-reason and exit-qualification parameters).
10554  * It should only be called before L2 actually succeeded to run, and when
10555  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10556  */
10557 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10558                         struct vmcs12 *vmcs12,
10559                         u32 reason, unsigned long qualification)
10560 {
10561         load_vmcs12_host_state(vcpu, vmcs12);
10562         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10563         vmcs12->exit_qualification = qualification;
10564         nested_vmx_succeed(vcpu);
10565         if (enable_shadow_vmcs)
10566                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10567 }
10568
10569 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10570                                struct x86_instruction_info *info,
10571                                enum x86_intercept_stage stage)
10572 {
10573         return X86EMUL_CONTINUE;
10574 }
10575
10576 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10577 {
10578         if (ple_gap)
10579                 shrink_ple_window(vcpu);
10580 }
10581
10582 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10583                                      struct kvm_memory_slot *slot)
10584 {
10585         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10586         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10587 }
10588
10589 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10590                                        struct kvm_memory_slot *slot)
10591 {
10592         kvm_mmu_slot_set_dirty(kvm, slot);
10593 }
10594
10595 static void vmx_flush_log_dirty(struct kvm *kvm)
10596 {
10597         kvm_flush_pml_buffers(kvm);
10598 }
10599
10600 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10601                                            struct kvm_memory_slot *memslot,
10602                                            gfn_t offset, unsigned long mask)
10603 {
10604         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10605 }
10606
10607 /*
10608  * This routine does the following things for vCPU which is going
10609  * to be blocked if VT-d PI is enabled.
10610  * - Store the vCPU to the wakeup list, so when interrupts happen
10611  *   we can find the right vCPU to wake up.
10612  * - Change the Posted-interrupt descriptor as below:
10613  *      'NDST' <-- vcpu->pre_pcpu
10614  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10615  * - If 'ON' is set during this process, which means at least one
10616  *   interrupt is posted for this vCPU, we cannot block it, in
10617  *   this case, return 1, otherwise, return 0.
10618  *
10619  */
10620 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10621 {
10622         unsigned long flags;
10623         unsigned int dest;
10624         struct pi_desc old, new;
10625         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10626
10627         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10628                 !irq_remapping_cap(IRQ_POSTING_CAP))
10629                 return 0;
10630
10631         vcpu->pre_pcpu = vcpu->cpu;
10632         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10633                           vcpu->pre_pcpu), flags);
10634         list_add_tail(&vcpu->blocked_vcpu_list,
10635                       &per_cpu(blocked_vcpu_on_cpu,
10636                       vcpu->pre_pcpu));
10637         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10638                                vcpu->pre_pcpu), flags);
10639
10640         do {
10641                 old.control = new.control = pi_desc->control;
10642
10643                 /*
10644                  * We should not block the vCPU if
10645                  * an interrupt is posted for it.
10646                  */
10647                 if (pi_test_on(pi_desc) == 1) {
10648                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10649                                           vcpu->pre_pcpu), flags);
10650                         list_del(&vcpu->blocked_vcpu_list);
10651                         spin_unlock_irqrestore(
10652                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10653                                         vcpu->pre_pcpu), flags);
10654                         vcpu->pre_pcpu = -1;
10655
10656                         return 1;
10657                 }
10658
10659                 WARN((pi_desc->sn == 1),
10660                      "Warning: SN field of posted-interrupts "
10661                      "is set before blocking\n");
10662
10663                 /*
10664                  * Since vCPU can be preempted during this process,
10665                  * vcpu->cpu could be different with pre_pcpu, we
10666                  * need to set pre_pcpu as the destination of wakeup
10667                  * notification event, then we can find the right vCPU
10668                  * to wakeup in wakeup handler if interrupts happen
10669                  * when the vCPU is in blocked state.
10670                  */
10671                 dest = cpu_physical_id(vcpu->pre_pcpu);
10672
10673                 if (x2apic_enabled())
10674                         new.ndst = dest;
10675                 else
10676                         new.ndst = (dest << 8) & 0xFF00;
10677
10678                 /* set 'NV' to 'wakeup vector' */
10679                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10680         } while (cmpxchg(&pi_desc->control, old.control,
10681                         new.control) != old.control);
10682
10683         return 0;
10684 }
10685
10686 static void vmx_post_block(struct kvm_vcpu *vcpu)
10687 {
10688         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10689         struct pi_desc old, new;
10690         unsigned int dest;
10691         unsigned long flags;
10692
10693         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10694                 !irq_remapping_cap(IRQ_POSTING_CAP))
10695                 return;
10696
10697         do {
10698                 old.control = new.control = pi_desc->control;
10699
10700                 dest = cpu_physical_id(vcpu->cpu);
10701
10702                 if (x2apic_enabled())
10703                         new.ndst = dest;
10704                 else
10705                         new.ndst = (dest << 8) & 0xFF00;
10706
10707                 /* Allow posting non-urgent interrupts */
10708                 new.sn = 0;
10709
10710                 /* set 'NV' to 'notification vector' */
10711                 new.nv = POSTED_INTR_VECTOR;
10712         } while (cmpxchg(&pi_desc->control, old.control,
10713                         new.control) != old.control);
10714
10715         if(vcpu->pre_pcpu != -1) {
10716                 spin_lock_irqsave(
10717                         &per_cpu(blocked_vcpu_on_cpu_lock,
10718                         vcpu->pre_pcpu), flags);
10719                 list_del(&vcpu->blocked_vcpu_list);
10720                 spin_unlock_irqrestore(
10721                         &per_cpu(blocked_vcpu_on_cpu_lock,
10722                         vcpu->pre_pcpu), flags);
10723                 vcpu->pre_pcpu = -1;
10724         }
10725 }
10726
10727 /*
10728  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10729  *
10730  * @kvm: kvm
10731  * @host_irq: host irq of the interrupt
10732  * @guest_irq: gsi of the interrupt
10733  * @set: set or unset PI
10734  * returns 0 on success, < 0 on failure
10735  */
10736 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10737                               uint32_t guest_irq, bool set)
10738 {
10739         struct kvm_kernel_irq_routing_entry *e;
10740         struct kvm_irq_routing_table *irq_rt;
10741         struct kvm_lapic_irq irq;
10742         struct kvm_vcpu *vcpu;
10743         struct vcpu_data vcpu_info;
10744         int idx, ret = -EINVAL;
10745
10746         if (!kvm_arch_has_assigned_device(kvm) ||
10747                 !irq_remapping_cap(IRQ_POSTING_CAP))
10748                 return 0;
10749
10750         idx = srcu_read_lock(&kvm->irq_srcu);
10751         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10752         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10753
10754         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10755                 if (e->type != KVM_IRQ_ROUTING_MSI)
10756                         continue;
10757                 /*
10758                  * VT-d PI cannot support posting multicast/broadcast
10759                  * interrupts to a vCPU, we still use interrupt remapping
10760                  * for these kind of interrupts.
10761                  *
10762                  * For lowest-priority interrupts, we only support
10763                  * those with single CPU as the destination, e.g. user
10764                  * configures the interrupts via /proc/irq or uses
10765                  * irqbalance to make the interrupts single-CPU.
10766                  *
10767                  * We will support full lowest-priority interrupt later.
10768                  */
10769
10770                 kvm_set_msi_irq(e, &irq);
10771                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10772                         continue;
10773
10774                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10775                 vcpu_info.vector = irq.vector;
10776
10777                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10778                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10779
10780                 if (set)
10781                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10782                 else {
10783                         /* suppress notification event before unposting */
10784                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10785                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10786                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10787                 }
10788
10789                 if (ret < 0) {
10790                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10791                                         __func__);
10792                         goto out;
10793                 }
10794         }
10795
10796         ret = 0;
10797 out:
10798         srcu_read_unlock(&kvm->irq_srcu, idx);
10799         return ret;
10800 }
10801
10802 static struct kvm_x86_ops vmx_x86_ops = {
10803         .cpu_has_kvm_support = cpu_has_kvm_support,
10804         .disabled_by_bios = vmx_disabled_by_bios,
10805         .hardware_setup = hardware_setup,
10806         .hardware_unsetup = hardware_unsetup,
10807         .check_processor_compatibility = vmx_check_processor_compat,
10808         .hardware_enable = hardware_enable,
10809         .hardware_disable = hardware_disable,
10810         .cpu_has_accelerated_tpr = report_flexpriority,
10811         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10812
10813         .vcpu_create = vmx_create_vcpu,
10814         .vcpu_free = vmx_free_vcpu,
10815         .vcpu_reset = vmx_vcpu_reset,
10816
10817         .prepare_guest_switch = vmx_save_host_state,
10818         .vcpu_load = vmx_vcpu_load,
10819         .vcpu_put = vmx_vcpu_put,
10820
10821         .update_bp_intercept = update_exception_bitmap,
10822         .get_msr = vmx_get_msr,
10823         .set_msr = vmx_set_msr,
10824         .get_segment_base = vmx_get_segment_base,
10825         .get_segment = vmx_get_segment,
10826         .set_segment = vmx_set_segment,
10827         .get_cpl = vmx_get_cpl,
10828         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10829         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10830         .decache_cr3 = vmx_decache_cr3,
10831         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10832         .set_cr0 = vmx_set_cr0,
10833         .set_cr3 = vmx_set_cr3,
10834         .set_cr4 = vmx_set_cr4,
10835         .set_efer = vmx_set_efer,
10836         .get_idt = vmx_get_idt,
10837         .set_idt = vmx_set_idt,
10838         .get_gdt = vmx_get_gdt,
10839         .set_gdt = vmx_set_gdt,
10840         .get_dr6 = vmx_get_dr6,
10841         .set_dr6 = vmx_set_dr6,
10842         .set_dr7 = vmx_set_dr7,
10843         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10844         .cache_reg = vmx_cache_reg,
10845         .get_rflags = vmx_get_rflags,
10846         .set_rflags = vmx_set_rflags,
10847         .fpu_activate = vmx_fpu_activate,
10848         .fpu_deactivate = vmx_fpu_deactivate,
10849
10850         .tlb_flush = vmx_flush_tlb,
10851
10852         .run = vmx_vcpu_run,
10853         .handle_exit = vmx_handle_exit,
10854         .skip_emulated_instruction = skip_emulated_instruction,
10855         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10856         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10857         .patch_hypercall = vmx_patch_hypercall,
10858         .set_irq = vmx_inject_irq,
10859         .set_nmi = vmx_inject_nmi,
10860         .queue_exception = vmx_queue_exception,
10861         .cancel_injection = vmx_cancel_injection,
10862         .interrupt_allowed = vmx_interrupt_allowed,
10863         .nmi_allowed = vmx_nmi_allowed,
10864         .get_nmi_mask = vmx_get_nmi_mask,
10865         .set_nmi_mask = vmx_set_nmi_mask,
10866         .enable_nmi_window = enable_nmi_window,
10867         .enable_irq_window = enable_irq_window,
10868         .update_cr8_intercept = update_cr8_intercept,
10869         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10870         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10871         .get_enable_apicv = vmx_get_enable_apicv,
10872         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10873         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10874         .hwapic_irr_update = vmx_hwapic_irr_update,
10875         .hwapic_isr_update = vmx_hwapic_isr_update,
10876         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10877         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10878
10879         .set_tss_addr = vmx_set_tss_addr,
10880         .get_tdp_level = get_ept_level,
10881         .get_mt_mask = vmx_get_mt_mask,
10882
10883         .get_exit_info = vmx_get_exit_info,
10884
10885         .get_lpage_level = vmx_get_lpage_level,
10886
10887         .cpuid_update = vmx_cpuid_update,
10888
10889         .rdtscp_supported = vmx_rdtscp_supported,
10890         .invpcid_supported = vmx_invpcid_supported,
10891
10892         .set_supported_cpuid = vmx_set_supported_cpuid,
10893
10894         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10895
10896         .read_tsc_offset = vmx_read_tsc_offset,
10897         .write_tsc_offset = vmx_write_tsc_offset,
10898         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10899         .read_l1_tsc = vmx_read_l1_tsc,
10900
10901         .set_tdp_cr3 = vmx_set_cr3,
10902
10903         .check_intercept = vmx_check_intercept,
10904         .handle_external_intr = vmx_handle_external_intr,
10905         .mpx_supported = vmx_mpx_supported,
10906         .xsaves_supported = vmx_xsaves_supported,
10907
10908         .check_nested_events = vmx_check_nested_events,
10909
10910         .sched_in = vmx_sched_in,
10911
10912         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10913         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10914         .flush_log_dirty = vmx_flush_log_dirty,
10915         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10916
10917         .pre_block = vmx_pre_block,
10918         .post_block = vmx_post_block,
10919
10920         .pmu_ops = &intel_pmu_ops,
10921
10922         .update_pi_irte = vmx_update_pi_irte,
10923 };
10924
10925 static int __init vmx_init(void)
10926 {
10927         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10928                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10929         if (r)
10930                 return r;
10931
10932 #ifdef CONFIG_KEXEC_CORE
10933         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10934                            crash_vmclear_local_loaded_vmcss);
10935 #endif
10936
10937         return 0;
10938 }
10939
10940 static void __exit vmx_exit(void)
10941 {
10942 #ifdef CONFIG_KEXEC_CORE
10943         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10944         synchronize_rcu();
10945 #endif
10946
10947         kvm_exit();
10948 }
10949
10950 module_init(vmx_init)
10951 module_exit(vmx_exit)