arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP    128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 131 module_param(ple_gap, int, S_IRUGO);
 132
 133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 134 module_param(ple_window, int, S_IRUGO);
 135
 136 extern const ulong vmx_return;
 137
 138 #define NR_AUTOLOAD_MSRS 8
 139 #define VMCS02_POOL_SIZE 1
 140
 141 struct vmcs {
 142         u32 revision_id;
 143         u32 abort;
 144         char data[0];
 145 };
 146
 147 /*
 148  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 149  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 150  * loaded on this CPU (so we can clear them if the CPU goes down).
 151  */
 152 struct loaded_vmcs {
 153         struct vmcs *vmcs;
 154         int cpu;
 155         int launched;
 156         struct list_head loaded_vmcss_on_cpu_link;
 157 };
 158
 159 struct shared_msr_entry {
 160         unsigned index;
 161         u64 data;
 162         u64 mask;
 163 };
 164
 165 /*
 166  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 167  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 168  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 169  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 170  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 171  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 172  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 173  * underlying hardware which will be used to run L2.
 174  * This structure is packed to ensure that its layout is identical across
 175  * machines (necessary for live migration).
 176  * If there are changes in this struct, VMCS12_REVISION must be changed.
 177  */
 178 typedef u64 natural_width;
 179 struct __packed vmcs12 {
 180         /* According to the Intel spec, a VMCS region must start with the
 181          * following two fields. Then follow implementation-specific data.
 182          */
 183         u32 revision_id;
 184         u32 abort;
 185
 186         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 187         u32 padding[7]; /* room for future expansion */
 188
 189         u64 io_bitmap_a;
 190         u64 io_bitmap_b;
 191         u64 msr_bitmap;
 192         u64 vm_exit_msr_store_addr;
 193         u64 vm_exit_msr_load_addr;
 194         u64 vm_entry_msr_load_addr;
 195         u64 tsc_offset;
 196         u64 virtual_apic_page_addr;
 197         u64 apic_access_addr;
 198         u64 ept_pointer;
 199         u64 guest_physical_address;
 200         u64 vmcs_link_pointer;
 201         u64 guest_ia32_debugctl;
 202         u64 guest_ia32_pat;
 203         u64 guest_ia32_efer;
 204         u64 guest_ia32_perf_global_ctrl;
 205         u64 guest_pdptr0;
 206         u64 guest_pdptr1;
 207         u64 guest_pdptr2;
 208         u64 guest_pdptr3;
 209         u64 guest_bndcfgs;
 210         u64 host_ia32_pat;
 211         u64 host_ia32_efer;
 212         u64 host_ia32_perf_global_ctrl;
 213         u64 padding64[8]; /* room for future expansion */
 214         /*
 215          * To allow migration of L1 (complete with its L2 guests) between
 216          * machines of different natural widths (32 or 64 bit), we cannot have
 217          * unsigned long fields with no explict size. We use u64 (aliased
 218          * natural_width) instead. Luckily, x86 is little-endian.
 219          */
 220         natural_width cr0_guest_host_mask;
 221         natural_width cr4_guest_host_mask;
 222         natural_width cr0_read_shadow;
 223         natural_width cr4_read_shadow;
 224         natural_width cr3_target_value0;
 225         natural_width cr3_target_value1;
 226         natural_width cr3_target_value2;
 227         natural_width cr3_target_value3;
 228         natural_width exit_qualification;
 229         natural_width guest_linear_address;
 230         natural_width guest_cr0;
 231         natural_width guest_cr3;
 232         natural_width guest_cr4;
 233         natural_width guest_es_base;
 234         natural_width guest_cs_base;
 235         natural_width guest_ss_base;
 236         natural_width guest_ds_base;
 237         natural_width guest_fs_base;
 238         natural_width guest_gs_base;
 239         natural_width guest_ldtr_base;
 240         natural_width guest_tr_base;
 241         natural_width guest_gdtr_base;
 242         natural_width guest_idtr_base;
 243         natural_width guest_dr7;
 244         natural_width guest_rsp;
 245         natural_width guest_rip;
 246         natural_width guest_rflags;
 247         natural_width guest_pending_dbg_exceptions;
 248         natural_width guest_sysenter_esp;
 249         natural_width guest_sysenter_eip;
 250         natural_width host_cr0;
 251         natural_width host_cr3;
 252         natural_width host_cr4;
 253         natural_width host_fs_base;
 254         natural_width host_gs_base;
 255         natural_width host_tr_base;
 256         natural_width host_gdtr_base;
 257         natural_width host_idtr_base;
 258         natural_width host_ia32_sysenter_esp;
 259         natural_width host_ia32_sysenter_eip;
 260         natural_width host_rsp;
 261         natural_width host_rip;
 262         natural_width paddingl[8]; /* room for future expansion */
 263         u32 pin_based_vm_exec_control;
 264         u32 cpu_based_vm_exec_control;
 265         u32 exception_bitmap;
 266         u32 page_fault_error_code_mask;
 267         u32 page_fault_error_code_match;
 268         u32 cr3_target_count;
 269         u32 vm_exit_controls;
 270         u32 vm_exit_msr_store_count;
 271         u32 vm_exit_msr_load_count;
 272         u32 vm_entry_controls;
 273         u32 vm_entry_msr_load_count;
 274         u32 vm_entry_intr_info_field;
 275         u32 vm_entry_exception_error_code;
 276         u32 vm_entry_instruction_len;
 277         u32 tpr_threshold;
 278         u32 secondary_vm_exec_control;
 279         u32 vm_instruction_error;
 280         u32 vm_exit_reason;
 281         u32 vm_exit_intr_info;
 282         u32 vm_exit_intr_error_code;
 283         u32 idt_vectoring_info_field;
 284         u32 idt_vectoring_error_code;
 285         u32 vm_exit_instruction_len;
 286         u32 vmx_instruction_info;
 287         u32 guest_es_limit;
 288         u32 guest_cs_limit;
 289         u32 guest_ss_limit;
 290         u32 guest_ds_limit;
 291         u32 guest_fs_limit;
 292         u32 guest_gs_limit;
 293         u32 guest_ldtr_limit;
 294         u32 guest_tr_limit;
 295         u32 guest_gdtr_limit;
 296         u32 guest_idtr_limit;
 297         u32 guest_es_ar_bytes;
 298         u32 guest_cs_ar_bytes;
 299         u32 guest_ss_ar_bytes;
 300         u32 guest_ds_ar_bytes;
 301         u32 guest_fs_ar_bytes;
 302         u32 guest_gs_ar_bytes;
 303         u32 guest_ldtr_ar_bytes;
 304         u32 guest_tr_ar_bytes;
 305         u32 guest_interruptibility_info;
 306         u32 guest_activity_state;
 307         u32 guest_sysenter_cs;
 308         u32 host_ia32_sysenter_cs;
 309         u32 vmx_preemption_timer_value;
 310         u32 padding32[7]; /* room for future expansion */
 311         u16 virtual_processor_id;
 312         u16 guest_es_selector;
 313         u16 guest_cs_selector;
 314         u16 guest_ss_selector;
 315         u16 guest_ds_selector;
 316         u16 guest_fs_selector;
 317         u16 guest_gs_selector;
 318         u16 guest_ldtr_selector;
 319         u16 guest_tr_selector;
 320         u16 host_es_selector;
 321         u16 host_cs_selector;
 322         u16 host_ss_selector;
 323         u16 host_ds_selector;
 324         u16 host_fs_selector;
 325         u16 host_gs_selector;
 326         u16 host_tr_selector;
 327 };
 328
 329 /*
 330  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 331  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 332  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 333  */
 334 #define VMCS12_REVISION 0x11e57ed0
 335
 336 /*
 337  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 338  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 339  * current implementation, 4K are reserved to avoid future complications.
 340  */
 341 #define VMCS12_SIZE 0x1000
 342
 343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 344 struct vmcs02_list {
 345         struct list_head list;
 346         gpa_t vmptr;
 347         struct loaded_vmcs vmcs02;
 348 };
 349
 350 /*
 351  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 352  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 353  */
 354 struct nested_vmx {
 355         /* Has the level1 guest done vmxon? */
 356         bool vmxon;
 357
 358         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 359         gpa_t current_vmptr;
 360         /* The host-usable pointer to the above */
 361         struct page *current_vmcs12_page;
 362         struct vmcs12 *current_vmcs12;
 363         struct vmcs *current_shadow_vmcs;
 364         /*
 365          * Indicates if the shadow vmcs must be updated with the
 366          * data hold by vmcs12
 367          */
 368         bool sync_shadow_vmcs;
 369
 370         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 371         struct list_head vmcs02_pool;
 372         int vmcs02_num;
 373         u64 vmcs01_tsc_offset;
 374         /* L2 must run next, and mustn't decide to exit to L1. */
 375         bool nested_run_pending;
 376         /*
 377          * Guest pages referred to in vmcs02 with host-physical pointers, so
 378          * we must keep them pinned while L2 runs.
 379          */
 380         struct page *apic_access_page;
 381         u64 msr_ia32_feature_control;
 382
 383         struct hrtimer preemption_timer;
 384         bool preemption_timer_expired;
 385 };
 386
 387 #define POSTED_INTR_ON  0
 388 /* Posted-Interrupt Descriptor */
 389 struct pi_desc {
 390         u32 pir[8];     /* Posted interrupt requested */
 391         u32 control;    /* bit 0 of control is outstanding notification bit */
 392         u32 rsvd[7];
 393 } __aligned(64);
 394
 395 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 396 {
 397         return test_and_set_bit(POSTED_INTR_ON,
 398                         (unsigned long *)&pi_desc->control);
 399 }
 400
 401 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 402 {
 403         return test_and_clear_bit(POSTED_INTR_ON,
 404                         (unsigned long *)&pi_desc->control);
 405 }
 406
 407 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 408 {
 409         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 410 }
 411
 412 struct vcpu_vmx {
 413         struct kvm_vcpu       vcpu;
 414         unsigned long         host_rsp;
 415         u8                    fail;
 416         u8                    cpl;
 417         bool                  nmi_known_unmasked;
 418         u32                   exit_intr_info;
 419         u32                   idt_vectoring_info;
 420         ulong                 rflags;
 421         struct shared_msr_entry *guest_msrs;
 422         int                   nmsrs;
 423         int                   save_nmsrs;
 424         unsigned long         host_idt_base;
 425 #ifdef CONFIG_X86_64
 426         u64                   msr_host_kernel_gs_base;
 427         u64                   msr_guest_kernel_gs_base;
 428 #endif
 429         u32 vm_entry_controls_shadow;
 430         u32 vm_exit_controls_shadow;
 431         /*
 432          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 433          * non-nested (L1) guest, it always points to vmcs01. For a nested
 434          * guest (L2), it points to a different VMCS.
 435          */
 436         struct loaded_vmcs    vmcs01;
 437         struct loaded_vmcs   *loaded_vmcs;
 438         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 439         struct msr_autoload {
 440                 unsigned nr;
 441                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 442                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 443         } msr_autoload;
 444         struct {
 445                 int           loaded;
 446                 u16           fs_sel, gs_sel, ldt_sel;
 447 #ifdef CONFIG_X86_64
 448                 u16           ds_sel, es_sel;
 449 #endif
 450                 int           gs_ldt_reload_needed;
 451                 int           fs_reload_needed;
 452                 u64           msr_host_bndcfgs;
 453         } host_state;
 454         struct {
 455                 int vm86_active;
 456                 ulong save_rflags;
 457                 struct kvm_segment segs[8];
 458         } rmode;
 459         struct {
 460                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 461                 struct kvm_save_segment {
 462                         u16 selector;
 463                         unsigned long base;
 464                         u32 limit;
 465                         u32 ar;
 466                 } seg[8];
 467         } segment_cache;
 468         int vpid;
 469         bool emulation_required;
 470
 471         /* Support for vnmi-less CPUs */
 472         int soft_vnmi_blocked;
 473         ktime_t entry_time;
 474         s64 vnmi_blocked_time;
 475         u32 exit_reason;
 476
 477         bool rdtscp_enabled;
 478
 479         /* Posted interrupt descriptor */
 480         struct pi_desc pi_desc;
 481
 482         /* Support for a guest hypervisor (nested VMX) */
 483         struct nested_vmx nested;
 484 };
 485
 486 enum segment_cache_field {
 487         SEG_FIELD_SEL = 0,
 488         SEG_FIELD_BASE = 1,
 489         SEG_FIELD_LIMIT = 2,
 490         SEG_FIELD_AR = 3,
 491
 492         SEG_FIELD_NR = 4
 493 };
 494
 495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 496 {
 497         return container_of(vcpu, struct vcpu_vmx, vcpu);
 498 }
 499
 500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 501 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 502 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 503                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 504
 505
 506 static unsigned long shadow_read_only_fields[] = {
 507         /*
 508          * We do NOT shadow fields that are modified when L0
 509          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 510          * VMXON...) executed by L1.
 511          * For example, VM_INSTRUCTION_ERROR is read
 512          * by L1 if a vmx instruction fails (part of the error path).
 513          * Note the code assumes this logic. If for some reason
 514          * we start shadowing these fields then we need to
 515          * force a shadow sync when L0 emulates vmx instructions
 516          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 517          * by nested_vmx_failValid)
 518          */
 519         VM_EXIT_REASON,
 520         VM_EXIT_INTR_INFO,
 521         VM_EXIT_INSTRUCTION_LEN,
 522         IDT_VECTORING_INFO_FIELD,
 523         IDT_VECTORING_ERROR_CODE,
 524         VM_EXIT_INTR_ERROR_CODE,
 525         EXIT_QUALIFICATION,
 526         GUEST_LINEAR_ADDRESS,
 527         GUEST_PHYSICAL_ADDRESS
 528 };
 529 static int max_shadow_read_only_fields =
 530         ARRAY_SIZE(shadow_read_only_fields);
 531
 532 static unsigned long shadow_read_write_fields[] = {
 533         GUEST_RIP,
 534         GUEST_RSP,
 535         GUEST_CR0,
 536         GUEST_CR3,
 537         GUEST_CR4,
 538         GUEST_INTERRUPTIBILITY_INFO,
 539         GUEST_RFLAGS,
 540         GUEST_CS_SELECTOR,
 541         GUEST_CS_AR_BYTES,
 542         GUEST_CS_LIMIT,
 543         GUEST_CS_BASE,
 544         GUEST_ES_BASE,
 545         GUEST_BNDCFGS,
 546         CR0_GUEST_HOST_MASK,
 547         CR0_READ_SHADOW,
 548         CR4_READ_SHADOW,
 549         TSC_OFFSET,
 550         EXCEPTION_BITMAP,
 551         CPU_BASED_VM_EXEC_CONTROL,
 552         VM_ENTRY_EXCEPTION_ERROR_CODE,
 553         VM_ENTRY_INTR_INFO_FIELD,
 554         VM_ENTRY_INSTRUCTION_LEN,
 555         VM_ENTRY_EXCEPTION_ERROR_CODE,
 556         HOST_FS_BASE,
 557         HOST_GS_BASE,
 558         HOST_FS_SELECTOR,
 559         HOST_GS_SELECTOR
 560 };
 561 static int max_shadow_read_write_fields =
 562         ARRAY_SIZE(shadow_read_write_fields);
 563
 564 static const unsigned short vmcs_field_to_offset_table[] = {
 565         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 566         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 567         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 568         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 569         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 570         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 571         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 572         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 573         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 574         FIELD(HOST_ES_SELECTOR, host_es_selector),
 575         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 576         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 577         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 578         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 579         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 580         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 581         FIELD64(IO_BITMAP_A, io_bitmap_a),
 582         FIELD64(IO_BITMAP_B, io_bitmap_b),
 583         FIELD64(MSR_BITMAP, msr_bitmap),
 584         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 585         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 586         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 587         FIELD64(TSC_OFFSET, tsc_offset),
 588         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 589         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 590         FIELD64(EPT_POINTER, ept_pointer),
 591         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 592         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 593         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 594         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 595         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 596         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 597         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 598         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 599         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 600         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 601         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 602         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 603         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 604         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 605         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 606         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 607         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 608         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 609         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 610         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 611         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 612         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 613         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 614         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 615         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 616         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 617         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 618         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 619         FIELD(TPR_THRESHOLD, tpr_threshold),
 620         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 621         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 622         FIELD(VM_EXIT_REASON, vm_exit_reason),
 623         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 624         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 625         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 626         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 627         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 628         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 629         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 630         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 631         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 632         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 633         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 634         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 635         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 636         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 637         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 638         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 639         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 640         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 641         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 642         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 643         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 644         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 645         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 646         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 647         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 648         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 649         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 650         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 651         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 652         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 653         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 654         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 655         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 656         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 657         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 658         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 659         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 660         FIELD(EXIT_QUALIFICATION, exit_qualification),
 661         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 662         FIELD(GUEST_CR0, guest_cr0),
 663         FIELD(GUEST_CR3, guest_cr3),
 664         FIELD(GUEST_CR4, guest_cr4),
 665         FIELD(GUEST_ES_BASE, guest_es_base),
 666         FIELD(GUEST_CS_BASE, guest_cs_base),
 667         FIELD(GUEST_SS_BASE, guest_ss_base),
 668         FIELD(GUEST_DS_BASE, guest_ds_base),
 669         FIELD(GUEST_FS_BASE, guest_fs_base),
 670         FIELD(GUEST_GS_BASE, guest_gs_base),
 671         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 672         FIELD(GUEST_TR_BASE, guest_tr_base),
 673         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 674         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 675         FIELD(GUEST_DR7, guest_dr7),
 676         FIELD(GUEST_RSP, guest_rsp),
 677         FIELD(GUEST_RIP, guest_rip),
 678         FIELD(GUEST_RFLAGS, guest_rflags),
 679         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 680         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 681         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 682         FIELD(HOST_CR0, host_cr0),
 683         FIELD(HOST_CR3, host_cr3),
 684         FIELD(HOST_CR4, host_cr4),
 685         FIELD(HOST_FS_BASE, host_fs_base),
 686         FIELD(HOST_GS_BASE, host_gs_base),
 687         FIELD(HOST_TR_BASE, host_tr_base),
 688         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 689         FIELD(HOST_IDTR_BASE, host_idtr_base),
 690         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 691         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 692         FIELD(HOST_RSP, host_rsp),
 693         FIELD(HOST_RIP, host_rip),
 694 };
 695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 696
 697 static inline short vmcs_field_to_offset(unsigned long field)
 698 {
 699         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 700                 return -1;
 701         return vmcs_field_to_offset_table[field];
 702 }
 703
 704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 705 {
 706         return to_vmx(vcpu)->nested.current_vmcs12;
 707 }
 708
 709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 710 {
 711         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 712         if (is_error_page(page))
 713                 return NULL;
 714
 715         return page;
 716 }
 717
 718 static void nested_release_page(struct page *page)
 719 {
 720         kvm_release_page_dirty(page);
 721 }
 722
 723 static void nested_release_page_clean(struct page *page)
 724 {
 725         kvm_release_page_clean(page);
 726 }
 727
 728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 729 static u64 construct_eptp(unsigned long root_hpa);
 730 static void kvm_cpu_vmxon(u64 addr);
 731 static void kvm_cpu_vmxoff(void);
 732 static bool vmx_mpx_supported(void);
 733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 735                             struct kvm_segment *var, int seg);
 736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 737                             struct kvm_segment *var, int seg);
 738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 743 static bool vmx_mpx_supported(void);
 744
 745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 747 /*
 748  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 749  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 750  */
 751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 753
 754 static unsigned long *vmx_io_bitmap_a;
 755 static unsigned long *vmx_io_bitmap_b;
 756 static unsigned long *vmx_msr_bitmap_legacy;
 757 static unsigned long *vmx_msr_bitmap_longmode;
 758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 760 static unsigned long *vmx_vmread_bitmap;
 761 static unsigned long *vmx_vmwrite_bitmap;
 762
 763 static bool cpu_has_load_ia32_efer;
 764 static bool cpu_has_load_perf_global_ctrl;
 765
 766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 767 static DEFINE_SPINLOCK(vmx_vpid_lock);
 768
 769 static struct vmcs_config {
 770         int size;
 771         int order;
 772         u32 revision_id;
 773         u32 pin_based_exec_ctrl;
 774         u32 cpu_based_exec_ctrl;
 775         u32 cpu_based_2nd_exec_ctrl;
 776         u32 vmexit_ctrl;
 777         u32 vmentry_ctrl;
 778 } vmcs_config;
 779
 780 static struct vmx_capability {
 781         u32 ept;
 782         u32 vpid;
 783 } vmx_capability;
 784
 785 #define VMX_SEGMENT_FIELD(seg)                                  \
 786         [VCPU_SREG_##seg] = {                                   \
 787                 .selector = GUEST_##seg##_SELECTOR,             \
 788                 .base = GUEST_##seg##_BASE,                     \
 789                 .limit = GUEST_##seg##_LIMIT,                   \
 790                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 791         }
 792
 793 static const struct kvm_vmx_segment_field {
 794         unsigned selector;
 795         unsigned base;
 796         unsigned limit;
 797         unsigned ar_bytes;
 798 } kvm_vmx_segment_fields[] = {
 799         VMX_SEGMENT_FIELD(CS),
 800         VMX_SEGMENT_FIELD(DS),
 801         VMX_SEGMENT_FIELD(ES),
 802         VMX_SEGMENT_FIELD(FS),
 803         VMX_SEGMENT_FIELD(GS),
 804         VMX_SEGMENT_FIELD(SS),
 805         VMX_SEGMENT_FIELD(TR),
 806         VMX_SEGMENT_FIELD(LDTR),
 807 };
 808
 809 static u64 host_efer;
 810
 811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 812
 813 /*
 814  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 815  * away by decrementing the array size.
 816  */
 817 static const u32 vmx_msr_index[] = {
 818 #ifdef CONFIG_X86_64
 819         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 820 #endif
 821         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 822 };
 823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 824
 825 static inline bool is_page_fault(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_no_device(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 835                              INTR_INFO_VALID_MASK)) ==
 836                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_invalid_opcode(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool is_external_interrupt(u32 intr_info)
 847 {
 848         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 849                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 850 }
 851
 852 static inline bool is_machine_check(u32 intr_info)
 853 {
 854         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 855                              INTR_INFO_VALID_MASK)) ==
 856                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 857 }
 858
 859 static inline bool cpu_has_vmx_msr_bitmap(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 862 }
 863
 864 static inline bool cpu_has_vmx_tpr_shadow(void)
 865 {
 866         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 867 }
 868
 869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 870 {
 871         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 872 }
 873
 874 static inline bool cpu_has_secondary_exec_ctrls(void)
 875 {
 876         return vmcs_config.cpu_based_exec_ctrl &
 877                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 878 }
 879
 880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 884 }
 885
 886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 890 }
 891
 892 static inline bool cpu_has_vmx_apic_register_virt(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 896 }
 897
 898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 899 {
 900         return vmcs_config.cpu_based_2nd_exec_ctrl &
 901                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 902 }
 903
 904 static inline bool cpu_has_vmx_posted_intr(void)
 905 {
 906         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 907 }
 908
 909 static inline bool cpu_has_vmx_apicv(void)
 910 {
 911         return cpu_has_vmx_apic_register_virt() &&
 912                 cpu_has_vmx_virtual_intr_delivery() &&
 913                 cpu_has_vmx_posted_intr();
 914 }
 915
 916 static inline bool cpu_has_vmx_flexpriority(void)
 917 {
 918         return cpu_has_vmx_tpr_shadow() &&
 919                 cpu_has_vmx_virtualize_apic_accesses();
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_execute_only(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 928 {
 929         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_eptp_writeback(void)
 933 {
 934         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_2m_page(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_ept_1g_page(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_ept_4levels(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_ad_bits(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_AD_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invept_context(void)
 958 {
 959         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_invept_global(void)
 963 {
 964         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_invvpid_single(void)
 968 {
 969         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_invvpid_global(void)
 973 {
 974         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_ENABLE_EPT;
 981 }
 982
 983 static inline bool cpu_has_vmx_unrestricted_guest(void)
 984 {
 985         return vmcs_config.cpu_based_2nd_exec_ctrl &
 986                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 987 }
 988
 989 static inline bool cpu_has_vmx_ple(void)
 990 {
 991         return vmcs_config.cpu_based_2nd_exec_ctrl &
 992                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 993 }
 994
 995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 996 {
 997         return flexpriority_enabled && irqchip_in_kernel(kvm);
 998 }
 999
1000 static inline bool cpu_has_vmx_vpid(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_VPID;
1004 }
1005
1006 static inline bool cpu_has_vmx_rdtscp(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_RDTSCP;
1010 }
1011
1012 static inline bool cpu_has_vmx_invpcid(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_ENABLE_INVPCID;
1016 }
1017
1018 static inline bool cpu_has_virtual_nmis(void)
1019 {
1020         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021 }
1022
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_WBINVD_EXITING;
1027 }
1028
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1030 {
1031         u64 vmx_msr;
1032         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033         /* check if the cpu supports writing r/o exit information fields */
1034         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035                 return false;
1036
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_SHADOW_VMCS;
1039 }
1040
1041 static inline bool report_flexpriority(void)
1042 {
1043         return flexpriority_enabled;
1044 }
1045
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047 {
1048         return vmcs12->cpu_based_vm_exec_control & bit;
1049 }
1050
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052 {
1053         return (vmcs12->cpu_based_vm_exec_control &
1054                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055                 (vmcs12->secondary_vm_exec_control & bit);
1056 }
1057
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1059 {
1060         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061 }
1062
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064 {
1065         return vmcs12->pin_based_vm_exec_control &
1066                 PIN_BASED_VMX_PREEMPTION_TIMER;
1067 }
1068
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070 {
1071         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072 }
1073
1074 static inline bool is_exception(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081                               u32 exit_intr_info,
1082                               unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084                         struct vmcs12 *vmcs12,
1085                         u32 reason, unsigned long qualification);
1086
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1088 {
1089         int i;
1090
1091         for (i = 0; i < vmx->nmsrs; ++i)
1092                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1093                         return i;
1094         return -1;
1095 }
1096
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098 {
1099     struct {
1100         u64 vpid : 16;
1101         u64 rsvd : 48;
1102         u64 gva;
1103     } operand = { vpid, 0, gva };
1104
1105     asm volatile (__ex(ASM_VMX_INVVPID)
1106                   /* CF==1 or ZF==1 --> rc = -1 */
1107                   "; ja 1f ; ud2 ; 1:"
1108                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1109 }
1110
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112 {
1113         struct {
1114                 u64 eptp, gpa;
1115         } operand = {eptp, gpa};
1116
1117         asm volatile (__ex(ASM_VMX_INVEPT)
1118                         /* CF==1 or ZF==1 --> rc = -1 */
1119                         "; ja 1f ; ud2 ; 1:\n"
1120                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1121 }
1122
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1124 {
1125         int i;
1126
1127         i = __find_msr_index(vmx, msr);
1128         if (i >= 0)
1129                 return &vmx->guest_msrs[i];
1130         return NULL;
1131 }
1132
1133 static void vmcs_clear(struct vmcs *vmcs)
1134 {
1135         u64 phys_addr = __pa(vmcs);
1136         u8 error;
1137
1138         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1140                       : "cc", "memory");
1141         if (error)
1142                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143                        vmcs, phys_addr);
1144 }
1145
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147 {
1148         vmcs_clear(loaded_vmcs->vmcs);
1149         loaded_vmcs->cpu = -1;
1150         loaded_vmcs->launched = 0;
1151 }
1152
1153 static void vmcs_load(struct vmcs *vmcs)
1154 {
1155         u64 phys_addr = __pa(vmcs);
1156         u8 error;
1157
1158         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1160                         : "cc", "memory");
1161         if (error)
1162                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1163                        vmcs, phys_addr);
1164 }
1165
1166 #ifdef CONFIG_KEXEC
1167 /*
1168  * This bitmap is used to indicate whether the vmclear
1169  * operation is enabled on all cpus. All disabled by
1170  * default.
1171  */
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174 static inline void crash_enable_local_vmclear(int cpu)
1175 {
1176         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 }
1178
1179 static inline void crash_disable_local_vmclear(int cpu)
1180 {
1181         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 }
1183
1184 static inline int crash_local_vmclear_enabled(int cpu)
1185 {
1186         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187 }
1188
1189 static void crash_vmclear_local_loaded_vmcss(void)
1190 {
1191         int cpu = raw_smp_processor_id();
1192         struct loaded_vmcs *v;
1193
1194         if (!crash_local_vmclear_enabled(cpu))
1195                 return;
1196
1197         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198                             loaded_vmcss_on_cpu_link)
1199                 vmcs_clear(v->vmcs);
1200 }
1201 #else
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1205
1206 static void __loaded_vmcs_clear(void *arg)
1207 {
1208         struct loaded_vmcs *loaded_vmcs = arg;
1209         int cpu = raw_smp_processor_id();
1210
1211         if (loaded_vmcs->cpu != cpu)
1212                 return; /* vcpu migration can race with cpu offline */
1213         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214                 per_cpu(current_vmcs, cpu) = NULL;
1215         crash_disable_local_vmclear(cpu);
1216         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1217
1218         /*
1219          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220          * is before setting loaded_vmcs->vcpu to -1 which is done in
1221          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222          * then adds the vmcs into percpu list before it is deleted.
1223          */
1224         smp_wmb();
1225
1226         loaded_vmcs_init(loaded_vmcs);
1227         crash_enable_local_vmclear(cpu);
1228 }
1229
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1231 {
1232         int cpu = loaded_vmcs->cpu;
1233
1234         if (cpu != -1)
1235                 smp_call_function_single(cpu,
1236                          __loaded_vmcs_clear, loaded_vmcs, 1);
1237 }
1238
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1240 {
1241         if (vmx->vpid == 0)
1242                 return;
1243
1244         if (cpu_has_vmx_invvpid_single())
1245                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1246 }
1247
1248 static inline void vpid_sync_vcpu_global(void)
1249 {
1250         if (cpu_has_vmx_invvpid_global())
1251                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252 }
1253
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255 {
1256         if (cpu_has_vmx_invvpid_single())
1257                 vpid_sync_vcpu_single(vmx);
1258         else
1259                 vpid_sync_vcpu_global();
1260 }
1261
1262 static inline void ept_sync_global(void)
1263 {
1264         if (cpu_has_vmx_invept_global())
1265                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266 }
1267
1268 static inline void ept_sync_context(u64 eptp)
1269 {
1270         if (enable_ept) {
1271                 if (cpu_has_vmx_invept_context())
1272                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273                 else
1274                         ept_sync_global();
1275         }
1276 }
1277
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1279 {
1280         unsigned long value;
1281
1282         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283                       : "=a"(value) : "d"(field) : "cc");
1284         return value;
1285 }
1286
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1288 {
1289         return vmcs_readl(field);
1290 }
1291
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1293 {
1294         return vmcs_readl(field);
1295 }
1296
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1298 {
1299 #ifdef CONFIG_X86_64
1300         return vmcs_readl(field);
1301 #else
1302         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303 #endif
1304 }
1305
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307 {
1308         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310         dump_stack();
1311 }
1312
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1314 {
1315         u8 error;
1316
1317         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1319         if (unlikely(error))
1320                 vmwrite_error(field, value);
1321 }
1322
1323 static void vmcs_write16(unsigned long field, u16 value)
1324 {
1325         vmcs_writel(field, value);
1326 }
1327
1328 static void vmcs_write32(unsigned long field, u32 value)
1329 {
1330         vmcs_writel(field, value);
1331 }
1332
1333 static void vmcs_write64(unsigned long field, u64 value)
1334 {
1335         vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1337         asm volatile ("");
1338         vmcs_writel(field+1, value >> 32);
1339 #endif
1340 }
1341
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1343 {
1344         vmcs_writel(field, vmcs_readl(field) & ~mask);
1345 }
1346
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1348 {
1349         vmcs_writel(field, vmcs_readl(field) | mask);
1350 }
1351
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353 {
1354         vmcs_write32(VM_ENTRY_CONTROLS, val);
1355         vmx->vm_entry_controls_shadow = val;
1356 }
1357
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359 {
1360         if (vmx->vm_entry_controls_shadow != val)
1361                 vm_entry_controls_init(vmx, val);
1362 }
1363
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365 {
1366         return vmx->vm_entry_controls_shadow;
1367 }
1368
1369
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371 {
1372         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373 }
1374
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378 }
1379
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381 {
1382         vmcs_write32(VM_EXIT_CONTROLS, val);
1383         vmx->vm_exit_controls_shadow = val;
1384 }
1385
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387 {
1388         if (vmx->vm_exit_controls_shadow != val)
1389                 vm_exit_controls_init(vmx, val);
1390 }
1391
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393 {
1394         return vmx->vm_exit_controls_shadow;
1395 }
1396
1397
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401 }
1402
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406 }
1407
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409 {
1410         vmx->segment_cache.bitmask = 0;
1411 }
1412
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414                                        unsigned field)
1415 {
1416         bool ret;
1417         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421                 vmx->segment_cache.bitmask = 0;
1422         }
1423         ret = vmx->segment_cache.bitmask & mask;
1424         vmx->segment_cache.bitmask |= mask;
1425         return ret;
1426 }
1427
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429 {
1430         u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434         return *p;
1435 }
1436
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438 {
1439         ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443         return *p;
1444 }
1445
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447 {
1448         u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452         return *p;
1453 }
1454
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456 {
1457         u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461         return *p;
1462 }
1463
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465 {
1466         u32 eb;
1467
1468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470         if ((vcpu->guest_debug &
1471              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473                 eb |= 1u << BP_VECTOR;
1474         if (to_vmx(vcpu)->rmode.vm86_active)
1475                 eb = ~0;
1476         if (enable_ept)
1477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478         if (vcpu->fpu_active)
1479                 eb &= ~(1u << NM_VECTOR);
1480
1481         /* When we are running a nested L2 guest and L1 specified for it a
1482          * certain exception bitmap, we must trap the same exceptions and pass
1483          * them to L1. When running L2, we will only handle the exceptions
1484          * specified above if L1 did not want them.
1485          */
1486         if (is_guest_mode(vcpu))
1487                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
1489         vmcs_write32(EXCEPTION_BITMAP, eb);
1490 }
1491
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493                 unsigned long entry, unsigned long exit)
1494 {
1495         vm_entry_controls_clearbit(vmx, entry);
1496         vm_exit_controls_clearbit(vmx, exit);
1497 }
1498
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500 {
1501         unsigned i;
1502         struct msr_autoload *m = &vmx->msr_autoload;
1503
1504         switch (msr) {
1505         case MSR_EFER:
1506                 if (cpu_has_load_ia32_efer) {
1507                         clear_atomic_switch_msr_special(vmx,
1508                                         VM_ENTRY_LOAD_IA32_EFER,
1509                                         VM_EXIT_LOAD_IA32_EFER);
1510                         return;
1511                 }
1512                 break;
1513         case MSR_CORE_PERF_GLOBAL_CTRL:
1514                 if (cpu_has_load_perf_global_ctrl) {
1515                         clear_atomic_switch_msr_special(vmx,
1516                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518                         return;
1519                 }
1520                 break;
1521         }
1522
1523         for (i = 0; i < m->nr; ++i)
1524                 if (m->guest[i].index == msr)
1525                         break;
1526
1527         if (i == m->nr)
1528                 return;
1529         --m->nr;
1530         m->guest[i] = m->guest[m->nr];
1531         m->host[i] = m->host[m->nr];
1532         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534 }
1535
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537                 unsigned long entry, unsigned long exit,
1538                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539                 u64 guest_val, u64 host_val)
1540 {
1541         vmcs_write64(guest_val_vmcs, guest_val);
1542         vmcs_write64(host_val_vmcs, host_val);
1543         vm_entry_controls_setbit(vmx, entry);
1544         vm_exit_controls_setbit(vmx, exit);
1545 }
1546
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548                                   u64 guest_val, u64 host_val)
1549 {
1550         unsigned i;
1551         struct msr_autoload *m = &vmx->msr_autoload;
1552
1553         switch (msr) {
1554         case MSR_EFER:
1555                 if (cpu_has_load_ia32_efer) {
1556                         add_atomic_switch_msr_special(vmx,
1557                                         VM_ENTRY_LOAD_IA32_EFER,
1558                                         VM_EXIT_LOAD_IA32_EFER,
1559                                         GUEST_IA32_EFER,
1560                                         HOST_IA32_EFER,
1561                                         guest_val, host_val);
1562                         return;
1563                 }
1564                 break;
1565         case MSR_CORE_PERF_GLOBAL_CTRL:
1566                 if (cpu_has_load_perf_global_ctrl) {
1567                         add_atomic_switch_msr_special(vmx,
1568                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1571                                         HOST_IA32_PERF_GLOBAL_CTRL,
1572                                         guest_val, host_val);
1573                         return;
1574                 }
1575                 break;
1576         }
1577
1578         for (i = 0; i < m->nr; ++i)
1579                 if (m->guest[i].index == msr)
1580                         break;
1581
1582         if (i == NR_AUTOLOAD_MSRS) {
1583                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584                                 "Can't add msr %x\n", msr);
1585                 return;
1586         } else if (i == m->nr) {
1587                 ++m->nr;
1588                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590         }
1591
1592         m->guest[i].index = msr;
1593         m->guest[i].value = guest_val;
1594         m->host[i].index = msr;
1595         m->host[i].value = host_val;
1596 }
1597
1598 static void reload_tss(void)
1599 {
1600         /*
1601          * VT restores TR but not its size.  Useless.
1602          */
1603         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604         struct desc_struct *descs;
1605
1606         descs = (void *)gdt->address;
1607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608         load_TR_desc();
1609 }
1610
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1612 {
1613         u64 guest_efer;
1614         u64 ignore_bits;
1615
1616         guest_efer = vmx->vcpu.arch.efer;
1617
1618         /*
1619          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1620          * outside long mode
1621          */
1622         ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624         ignore_bits |= EFER_LMA | EFER_LME;
1625         /* SCE is meaningful only in long mode on Intel */
1626         if (guest_efer & EFER_LMA)
1627                 ignore_bits &= ~(u64)EFER_SCE;
1628 #endif
1629         guest_efer &= ~ignore_bits;
1630         guest_efer |= host_efer & ignore_bits;
1631         vmx->guest_msrs[efer_offset].data = guest_efer;
1632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1633
1634         clear_atomic_switch_msr(vmx, MSR_EFER);
1635         /* On ept, can't emulate nx, and must switch nx atomically */
1636         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637                 guest_efer = vmx->vcpu.arch.efer;
1638                 if (!(guest_efer & EFER_LMA))
1639                         guest_efer &= ~EFER_LME;
1640                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static unsigned long segment_base(u16 selector)
1648 {
1649         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650         struct desc_struct *d;
1651         unsigned long table_base;
1652         unsigned long v;
1653
1654         if (!(selector & ~3))
1655                 return 0;
1656
1657         table_base = gdt->address;
1658
1659         if (selector & 4) {           /* from ldt */
1660                 u16 ldt_selector = kvm_read_ldt();
1661
1662                 if (!(ldt_selector & ~3))
1663                         return 0;
1664
1665                 table_base = segment_base(ldt_selector);
1666         }
1667         d = (struct desc_struct *)(table_base + (selector & ~7));
1668         v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672 #endif
1673         return v;
1674 }
1675
1676 static inline unsigned long kvm_read_tr_base(void)
1677 {
1678         u16 tr;
1679         asm("str %0" : "=g"(tr));
1680         return segment_base(tr);
1681 }
1682
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         int i;
1687
1688         if (vmx->host_state.loaded)
1689                 return;
1690
1691         vmx->host_state.loaded = 1;
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         vmx->host_state.ldt_sel = kvm_read_ldt();
1697         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698         savesegment(fs, vmx->host_state.fs_sel);
1699         if (!(vmx->host_state.fs_sel & 7)) {
1700                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701                 vmx->host_state.fs_reload_needed = 0;
1702         } else {
1703                 vmcs_write16(HOST_FS_SELECTOR, 0);
1704                 vmx->host_state.fs_reload_needed = 1;
1705         }
1706         savesegment(gs, vmx->host_state.gs_sel);
1707         if (!(vmx->host_state.gs_sel & 7))
1708                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1709         else {
1710                 vmcs_write16(HOST_GS_SELECTOR, 0);
1711                 vmx->host_state.gs_ldt_reload_needed = 1;
1712         }
1713
1714 #ifdef CONFIG_X86_64
1715         savesegment(ds, vmx->host_state.ds_sel);
1716         savesegment(es, vmx->host_state.es_sel);
1717 #endif
1718
1719 #ifdef CONFIG_X86_64
1720         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722 #else
1723         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1725 #endif
1726
1727 #ifdef CONFIG_X86_64
1728         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729         if (is_long_mode(&vmx->vcpu))
1730                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1731 #endif
1732         if (boot_cpu_has(X86_FEATURE_MPX))
1733                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734         for (i = 0; i < vmx->save_nmsrs; ++i)
1735                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736                                    vmx->guest_msrs[i].data,
1737                                    vmx->guest_msrs[i].mask);
1738 }
1739
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1741 {
1742         if (!vmx->host_state.loaded)
1743                 return;
1744
1745         ++vmx->vcpu.stat.host_state_reload;
1746         vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748         if (is_long_mode(&vmx->vcpu))
1749                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750 #endif
1751         if (vmx->host_state.gs_ldt_reload_needed) {
1752                 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754                 load_gs_index(vmx->host_state.gs_sel);
1755 #else
1756                 loadsegment(gs, vmx->host_state.gs_sel);
1757 #endif
1758         }
1759         if (vmx->host_state.fs_reload_needed)
1760                 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763                 loadsegment(ds, vmx->host_state.ds_sel);
1764                 loadsegment(es, vmx->host_state.es_sel);
1765         }
1766 #endif
1767         reload_tss();
1768 #ifdef CONFIG_X86_64
1769         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770 #endif
1771         if (vmx->host_state.msr_host_bndcfgs)
1772                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1773         /*
1774          * If the FPU is not active (through the host task or
1775          * the guest vcpu), then restore the cr0.TS bit.
1776          */
1777         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778                 stts();
1779         load_gdt(&__get_cpu_var(host_gdt));
1780 }
1781
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783 {
1784         preempt_disable();
1785         __vmx_load_host_state(vmx);
1786         preempt_enable();
1787 }
1788
1789 /*
1790  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791  * vcpu mutex is already taken.
1792  */
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1794 {
1795         struct vcpu_vmx *vmx = to_vmx(vcpu);
1796         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1797
1798         if (!vmm_exclusive)
1799                 kvm_cpu_vmxon(phys_addr);
1800         else if (vmx->loaded_vmcs->cpu != cpu)
1801                 loaded_vmcs_clear(vmx->loaded_vmcs);
1802
1803         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805                 vmcs_load(vmx->loaded_vmcs->vmcs);
1806         }
1807
1808         if (vmx->loaded_vmcs->cpu != cpu) {
1809                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810                 unsigned long sysenter_esp;
1811
1812                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813                 local_irq_disable();
1814                 crash_disable_local_vmclear(cpu);
1815
1816                 /*
1817                  * Read loaded_vmcs->cpu should be before fetching
1818                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819                  * See the comments in __loaded_vmcs_clear().
1820                  */
1821                 smp_rmb();
1822
1823                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1825                 crash_enable_local_vmclear(cpu);
1826                 local_irq_enable();
1827
1828                 /*
1829                  * Linux uses per-cpu TSS and GDT, so set these when switching
1830                  * processors.
1831                  */
1832                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1834
1835                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837                 vmx->loaded_vmcs->cpu = cpu;
1838         }
1839 }
1840
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842 {
1843         __vmx_load_host_state(to_vmx(vcpu));
1844         if (!vmm_exclusive) {
1845                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846                 vcpu->cpu = -1;
1847                 kvm_cpu_vmxoff();
1848         }
1849 }
1850
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852 {
1853         ulong cr0;
1854
1855         if (vcpu->fpu_active)
1856                 return;
1857         vcpu->fpu_active = 1;
1858         cr0 = vmcs_readl(GUEST_CR0);
1859         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861         vmcs_writel(GUEST_CR0, cr0);
1862         update_exception_bitmap(vcpu);
1863         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864         if (is_guest_mode(vcpu))
1865                 vcpu->arch.cr0_guest_owned_bits &=
1866                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1868 }
1869
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
1872 /*
1873  * Return the cr0 value that a nested guest would read. This is a combination
1874  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875  * its hypervisor (cr0_read_shadow).
1876  */
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878 {
1879         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881 }
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883 {
1884         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886 }
1887
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889 {
1890         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891          * set this *before* calling this function.
1892          */
1893         vmx_decache_cr0_guest_bits(vcpu);
1894         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895         update_exception_bitmap(vcpu);
1896         vcpu->arch.cr0_guest_owned_bits = 0;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898         if (is_guest_mode(vcpu)) {
1899                 /*
1900                  * L1's specified read shadow might not contain the TS bit,
1901                  * so now that we turned on shadowing of this bit, we need to
1902                  * set this bit of the shadow. Like in nested_vmx_run we need
1903                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904                  * up-to-date here because we just decached cr0.TS (and we'll
1905                  * only update vmcs12->guest_cr0 on nested exit).
1906                  */
1907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909                         (vcpu->arch.cr0 & X86_CR0_TS);
1910                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911         } else
1912                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1913 }
1914
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916 {
1917         unsigned long rflags, save_rflags;
1918
1919         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921                 rflags = vmcs_readl(GUEST_RFLAGS);
1922                 if (to_vmx(vcpu)->rmode.vm86_active) {
1923                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926                 }
1927                 to_vmx(vcpu)->rflags = rflags;
1928         }
1929         return to_vmx(vcpu)->rflags;
1930 }
1931
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933 {
1934         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935         to_vmx(vcpu)->rflags = rflags;
1936         if (to_vmx(vcpu)->rmode.vm86_active) {
1937                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1939         }
1940         vmcs_writel(GUEST_RFLAGS, rflags);
1941 }
1942
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944 {
1945         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946         int ret = 0;
1947
1948         if (interruptibility & GUEST_INTR_STATE_STI)
1949                 ret |= KVM_X86_SHADOW_INT_STI;
1950         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1952
1953         return ret & mask;
1954 }
1955
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957 {
1958         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959         u32 interruptibility = interruptibility_old;
1960
1961         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
1963         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965         else if (mask & KVM_X86_SHADOW_INT_STI)
1966                 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968         if ((interruptibility != interruptibility_old))
1969                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970 }
1971
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973 {
1974         unsigned long rip;
1975
1976         rip = kvm_rip_read(vcpu);
1977         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978         kvm_rip_write(vcpu, rip);
1979
1980         /* skipping an emulated instruction also counts */
1981         vmx_set_interrupt_shadow(vcpu, 0);
1982 }
1983
1984 /*
1985  * KVM wants to inject page-faults which it got to the guest. This function
1986  * checks whether in a nested guest, we need to inject them to L1 or L2.
1987  */
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1989 {
1990         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
1992         if (!(vmcs12->exception_bitmap & (1u << nr)))
1993                 return 0;
1994
1995         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996                           vmcs_read32(VM_EXIT_INTR_INFO),
1997                           vmcs_readl(EXIT_QUALIFICATION));
1998         return 1;
1999 }
2000
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002                                 bool has_error_code, u32 error_code,
2003                                 bool reinject)
2004 {
2005         struct vcpu_vmx *vmx = to_vmx(vcpu);
2006         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2007
2008         if (!reinject && is_guest_mode(vcpu) &&
2009             nested_vmx_check_exception(vcpu, nr))
2010                 return;
2011
2012         if (has_error_code) {
2013                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015         }
2016
2017         if (vmx->rmode.vm86_active) {
2018                 int inc_eip = 0;
2019                 if (kvm_exception_is_soft(nr))
2020                         inc_eip = vcpu->arch.event_exit_inst_len;
2021                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2023                 return;
2024         }
2025
2026         if (kvm_exception_is_soft(nr)) {
2027                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028                              vmx->vcpu.arch.event_exit_inst_len);
2029                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030         } else
2031                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2034 }
2035
2036 static bool vmx_rdtscp_supported(void)
2037 {
2038         return cpu_has_vmx_rdtscp();
2039 }
2040
2041 static bool vmx_invpcid_supported(void)
2042 {
2043         return cpu_has_vmx_invpcid() && enable_ept;
2044 }
2045
2046 /*
2047  * Swap MSR entry in host/guest MSR entry array.
2048  */
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2050 {
2051         struct shared_msr_entry tmp;
2052
2053         tmp = vmx->guest_msrs[to];
2054         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055         vmx->guest_msrs[from] = tmp;
2056 }
2057
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059 {
2060         unsigned long *msr_bitmap;
2061
2062         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063                 if (is_long_mode(vcpu))
2064                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065                 else
2066                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067         } else {
2068                 if (is_long_mode(vcpu))
2069                         msr_bitmap = vmx_msr_bitmap_longmode;
2070                 else
2071                         msr_bitmap = vmx_msr_bitmap_legacy;
2072         }
2073
2074         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075 }
2076
2077 /*
2078  * Set up the vmcs to automatically save and restore system
2079  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2080  * mode, as fiddling with msrs is very expensive.
2081  */
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2083 {
2084         int save_nmsrs, index;
2085
2086         save_nmsrs = 0;
2087 #ifdef CONFIG_X86_64
2088         if (is_long_mode(&vmx->vcpu)) {
2089                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2090                 if (index >= 0)
2091                         move_msr_up(vmx, index, save_nmsrs++);
2092                 index = __find_msr_index(vmx, MSR_LSTAR);
2093                 if (index >= 0)
2094                         move_msr_up(vmx, index, save_nmsrs++);
2095                 index = __find_msr_index(vmx, MSR_CSTAR);
2096                 if (index >= 0)
2097                         move_msr_up(vmx, index, save_nmsrs++);
2098                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099                 if (index >= 0 && vmx->rdtscp_enabled)
2100                         move_msr_up(vmx, index, save_nmsrs++);
2101                 /*
2102                  * MSR_STAR is only needed on long mode guests, and only
2103                  * if efer.sce is enabled.
2104                  */
2105                 index = __find_msr_index(vmx, MSR_STAR);
2106                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107                         move_msr_up(vmx, index, save_nmsrs++);
2108         }
2109 #endif
2110         index = __find_msr_index(vmx, MSR_EFER);
2111         if (index >= 0 && update_transition_efer(vmx, index))
2112                 move_msr_up(vmx, index, save_nmsrs++);
2113
2114         vmx->save_nmsrs = save_nmsrs;
2115
2116         if (cpu_has_vmx_msr_bitmap())
2117                 vmx_set_msr_bitmap(&vmx->vcpu);
2118 }
2119
2120 /*
2121  * reads and returns guest's timestamp counter "register"
2122  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2123  */
2124 static u64 guest_read_tsc(void)
2125 {
2126         u64 host_tsc, tsc_offset;
2127
2128         rdtscll(host_tsc);
2129         tsc_offset = vmcs_read64(TSC_OFFSET);
2130         return host_tsc + tsc_offset;
2131 }
2132
2133 /*
2134  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135  * counter, even if a nested guest (L2) is currently running.
2136  */
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2138 {
2139         u64 tsc_offset;
2140
2141         tsc_offset = is_guest_mode(vcpu) ?
2142                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143                 vmcs_read64(TSC_OFFSET);
2144         return host_tsc + tsc_offset;
2145 }
2146
2147 /*
2148  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2149  * software catchup for faster rates on slower CPUs.
2150  */
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2152 {
2153         if (!scale)
2154                 return;
2155
2156         if (user_tsc_khz > tsc_khz) {
2157                 vcpu->arch.tsc_catchup = 1;
2158                 vcpu->arch.tsc_always_catchup = 1;
2159         } else
2160                 WARN(1, "user requested TSC rate below hardware speed\n");
2161 }
2162
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164 {
2165         return vmcs_read64(TSC_OFFSET);
2166 }
2167
2168 /*
2169  * writes 'offset' into guest's timestamp counter offset register
2170  */
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2172 {
2173         if (is_guest_mode(vcpu)) {
2174                 /*
2175                  * We're here if L1 chose not to trap WRMSR to TSC. According
2176                  * to the spec, this should set L1's TSC; The offset that L1
2177                  * set for L2 remains unchanged, and still needs to be added
2178                  * to the newly set TSC to get L2's TSC.
2179                  */
2180                 struct vmcs12 *vmcs12;
2181                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182                 /* recalculate vmcs02.TSC_OFFSET: */
2183                 vmcs12 = get_vmcs12(vcpu);
2184                 vmcs_write64(TSC_OFFSET, offset +
2185                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186                          vmcs12->tsc_offset : 0));
2187         } else {
2188                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189                                            vmcs_read64(TSC_OFFSET), offset);
2190                 vmcs_write64(TSC_OFFSET, offset);
2191         }
2192 }
2193
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2195 {
2196         u64 offset = vmcs_read64(TSC_OFFSET);
2197
2198         vmcs_write64(TSC_OFFSET, offset + adjustment);
2199         if (is_guest_mode(vcpu)) {
2200                 /* Even when running L2, the adjustment needs to apply to L1 */
2201                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2202         } else
2203                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204                                            offset + adjustment);
2205 }
2206
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208 {
2209         return target_tsc - native_read_tsc();
2210 }
2211
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213 {
2214         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216 }
2217
2218 /*
2219  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221  * all guests if the "nested" module option is off, and can also be disabled
2222  * for a single guest by disabling its VMX cpuid bit.
2223  */
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225 {
2226         return nested && guest_cpuid_has_vmx(vcpu);
2227 }
2228
2229 /*
2230  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231  * returned for the various VMX controls MSRs when nested VMX is enabled.
2232  * The same values should also be used to verify that vmcs12 control fields are
2233  * valid during nested entry from L1 to L2.
2234  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236  * bit in the high half is on if the corresponding bit in the control field
2237  * may be on. See also vmx_control_verify().
2238  * TODO: allow these variables to be modified (downgraded) by module options
2239  * or other means.
2240  */
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2249 {
2250         /*
2251          * Note that as a general rule, the high half of the MSRs (bits in
2252          * the control fields which may be 1) should be initialized by the
2253          * intersection of the underlying hardware's MSR (i.e., features which
2254          * can be supported) and the list of features we want to expose -
2255          * because they are known to be properly supported in our code.
2256          * Also, usually, the low half of the MSRs (bits which must be 1) can
2257          * be set to 0, meaning that L1 may turn off any of these bits. The
2258          * reason is that if one of these bits is necessary, it will appear
2259          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260          * fields of vmcs01 and vmcs02, will turn these bits off - and
2261          * nested_vmx_exit_handled() will not pass related exits to L1.
2262          * These rules have exceptions below.
2263          */
2264
2265         /* pin-based controls */
2266         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2268         /*
2269          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271          */
2272         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 PIN_BASED_VMX_PREEMPTION_TIMER;
2277
2278         /*
2279          * Exit controls
2280          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281          * 17 must be 1.
2282          */
2283         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2287         nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2290 #endif
2291                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2295         if (vmx_mpx_supported())
2296                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2297
2298         /* entry controls */
2299         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2301         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2303         nested_vmx_entry_ctls_high &=
2304 #ifdef CONFIG_X86_64
2305                 VM_ENTRY_IA32E_MODE |
2306 #endif
2307                 VM_ENTRY_LOAD_IA32_PAT;
2308         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309                                        VM_ENTRY_LOAD_IA32_EFER);
2310         if (vmx_mpx_supported())
2311                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2312
2313         /* cpu-based controls */
2314         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316         nested_vmx_procbased_ctls_low = 0;
2317         nested_vmx_procbased_ctls_high &=
2318                 CPU_BASED_VIRTUAL_INTR_PENDING |
2319                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2320                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322                 CPU_BASED_CR3_STORE_EXITING |
2323 #ifdef CONFIG_X86_64
2324                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2325 #endif
2326                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2328                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2329                 CPU_BASED_PAUSE_EXITING |
2330                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2331         /*
2332          * We can allow some features even when not supported by the
2333          * hardware. For example, L1 can specify an MSR bitmap - and we
2334          * can use it to avoid exits to L1 - even when L0 runs L2
2335          * without MSR bitmaps.
2336          */
2337         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2338
2339         /* secondary cpu-based controls */
2340         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342         nested_vmx_secondary_ctls_low = 0;
2343         nested_vmx_secondary_ctls_high &=
2344                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2345                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2346                 SECONDARY_EXEC_WBINVD_EXITING;
2347
2348         if (enable_ept) {
2349                 /* nested EPT: emulate EPT also to L1 */
2350                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2351                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2352                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2353                          VMX_EPT_INVEPT_BIT;
2354                 nested_vmx_ept_caps &= vmx_capability.ept;
2355                 /*
2356                  * Since invept is completely emulated we support both global
2357                  * and context invalidation independent of what host cpu
2358                  * supports
2359                  */
2360                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2361                         VMX_EPT_EXTENT_CONTEXT_BIT;
2362         } else
2363                 nested_vmx_ept_caps = 0;
2364
2365         /* miscellaneous data */
2366         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2367         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369                 VMX_MISC_ACTIVITY_HLT;
2370         nested_vmx_misc_high = 0;
2371 }
2372
2373 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2374 {
2375         /*
2376          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377          */
2378         return ((control & high) | low) == control;
2379 }
2380
2381 static inline u64 vmx_control_msr(u32 low, u32 high)
2382 {
2383         return low | ((u64)high << 32);
2384 }
2385
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2388 {
2389         switch (msr_index) {
2390         case MSR_IA32_VMX_BASIC:
2391                 /*
2392                  * This MSR reports some information about VMX support. We
2393                  * should return information about the VMX we emulate for the
2394                  * guest, and the VMCS structure we give it - not about the
2395                  * VMX support of the underlying hardware.
2396                  */
2397                 *pdata = VMCS12_REVISION |
2398                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400                 break;
2401         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402         case MSR_IA32_VMX_PINBASED_CTLS:
2403                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404                                         nested_vmx_pinbased_ctls_high);
2405                 break;
2406         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407         case MSR_IA32_VMX_PROCBASED_CTLS:
2408                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409                                         nested_vmx_procbased_ctls_high);
2410                 break;
2411         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412         case MSR_IA32_VMX_EXIT_CTLS:
2413                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414                                         nested_vmx_exit_ctls_high);
2415                 break;
2416         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417         case MSR_IA32_VMX_ENTRY_CTLS:
2418                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419                                         nested_vmx_entry_ctls_high);
2420                 break;
2421         case MSR_IA32_VMX_MISC:
2422                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423                                          nested_vmx_misc_high);
2424                 break;
2425         /*
2426          * These MSRs specify bits which the guest must keep fixed (on or off)
2427          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428          * We picked the standard core2 setting.
2429          */
2430 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2432         case MSR_IA32_VMX_CR0_FIXED0:
2433                 *pdata = VMXON_CR0_ALWAYSON;
2434                 break;
2435         case MSR_IA32_VMX_CR0_FIXED1:
2436                 *pdata = -1ULL;
2437                 break;
2438         case MSR_IA32_VMX_CR4_FIXED0:
2439                 *pdata = VMXON_CR4_ALWAYSON;
2440                 break;
2441         case MSR_IA32_VMX_CR4_FIXED1:
2442                 *pdata = -1ULL;
2443                 break;
2444         case MSR_IA32_VMX_VMCS_ENUM:
2445                 *pdata = 0x1f;
2446                 break;
2447         case MSR_IA32_VMX_PROCBASED_CTLS2:
2448                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449                                         nested_vmx_secondary_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_EPT_VPID_CAP:
2452                 /* Currently, no nested vpid support */
2453                 *pdata = nested_vmx_ept_caps;
2454                 break;
2455         default:
2456                 return 1;
2457         }
2458
2459         return 0;
2460 }
2461
2462 /*
2463  * Reads an msr value (of 'msr_index') into 'pdata'.
2464  * Returns 0 on success, non-0 otherwise.
2465  * Assumes vcpu_load() was already called.
2466  */
2467 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468 {
2469         u64 data;
2470         struct shared_msr_entry *msr;
2471
2472         if (!pdata) {
2473                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474                 return -EINVAL;
2475         }
2476
2477         switch (msr_index) {
2478 #ifdef CONFIG_X86_64
2479         case MSR_FS_BASE:
2480                 data = vmcs_readl(GUEST_FS_BASE);
2481                 break;
2482         case MSR_GS_BASE:
2483                 data = vmcs_readl(GUEST_GS_BASE);
2484                 break;
2485         case MSR_KERNEL_GS_BASE:
2486                 vmx_load_host_state(to_vmx(vcpu));
2487                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488                 break;
2489 #endif
2490         case MSR_EFER:
2491                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2492         case MSR_IA32_TSC:
2493                 data = guest_read_tsc();
2494                 break;
2495         case MSR_IA32_SYSENTER_CS:
2496                 data = vmcs_read32(GUEST_SYSENTER_CS);
2497                 break;
2498         case MSR_IA32_SYSENTER_EIP:
2499                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2500                 break;
2501         case MSR_IA32_SYSENTER_ESP:
2502                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2503                 break;
2504         case MSR_IA32_BNDCFGS:
2505                 if (!vmx_mpx_supported())
2506                         return 1;
2507                 data = vmcs_read64(GUEST_BNDCFGS);
2508                 break;
2509         case MSR_IA32_FEATURE_CONTROL:
2510                 if (!nested_vmx_allowed(vcpu))
2511                         return 1;
2512                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513                 break;
2514         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515                 if (!nested_vmx_allowed(vcpu))
2516                         return 1;
2517                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2518         case MSR_TSC_AUX:
2519                 if (!to_vmx(vcpu)->rdtscp_enabled)
2520                         return 1;
2521                 /* Otherwise falls through */
2522         default:
2523                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2524                 if (msr) {
2525                         data = msr->data;
2526                         break;
2527                 }
2528                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2529         }
2530
2531         *pdata = data;
2532         return 0;
2533 }
2534
2535 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
2537 /*
2538  * Writes msr value into into the appropriate "register".
2539  * Returns 0 on success, non-0 otherwise.
2540  * Assumes vcpu_load() was already called.
2541  */
2542 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2543 {
2544         struct vcpu_vmx *vmx = to_vmx(vcpu);
2545         struct shared_msr_entry *msr;
2546         int ret = 0;
2547         u32 msr_index = msr_info->index;
2548         u64 data = msr_info->data;
2549
2550         switch (msr_index) {
2551         case MSR_EFER:
2552                 ret = kvm_set_msr_common(vcpu, msr_info);
2553                 break;
2554 #ifdef CONFIG_X86_64
2555         case MSR_FS_BASE:
2556                 vmx_segment_cache_clear(vmx);
2557                 vmcs_writel(GUEST_FS_BASE, data);
2558                 break;
2559         case MSR_GS_BASE:
2560                 vmx_segment_cache_clear(vmx);
2561                 vmcs_writel(GUEST_GS_BASE, data);
2562                 break;
2563         case MSR_KERNEL_GS_BASE:
2564                 vmx_load_host_state(vmx);
2565                 vmx->msr_guest_kernel_gs_base = data;
2566                 break;
2567 #endif
2568         case MSR_IA32_SYSENTER_CS:
2569                 vmcs_write32(GUEST_SYSENTER_CS, data);
2570                 break;
2571         case MSR_IA32_SYSENTER_EIP:
2572                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2573                 break;
2574         case MSR_IA32_SYSENTER_ESP:
2575                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2576                 break;
2577         case MSR_IA32_BNDCFGS:
2578                 if (!vmx_mpx_supported())
2579                         return 1;
2580                 vmcs_write64(GUEST_BNDCFGS, data);
2581                 break;
2582         case MSR_IA32_TSC:
2583                 kvm_write_tsc(vcpu, msr_info);
2584                 break;
2585         case MSR_IA32_CR_PAT:
2586                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587                         vmcs_write64(GUEST_IA32_PAT, data);
2588                         vcpu->arch.pat = data;
2589                         break;
2590                 }
2591                 ret = kvm_set_msr_common(vcpu, msr_info);
2592                 break;
2593         case MSR_IA32_TSC_ADJUST:
2594                 ret = kvm_set_msr_common(vcpu, msr_info);
2595                 break;
2596         case MSR_IA32_FEATURE_CONTROL:
2597                 if (!nested_vmx_allowed(vcpu) ||
2598                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600                         return 1;
2601                 vmx->nested.msr_ia32_feature_control = data;
2602                 if (msr_info->host_initiated && data == 0)
2603                         vmx_leave_nested(vcpu);
2604                 break;
2605         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606                 return 1; /* they are read-only */
2607         case MSR_TSC_AUX:
2608                 if (!vmx->rdtscp_enabled)
2609                         return 1;
2610                 /* Check reserved bit, higher 32 bits should be zero */
2611                 if ((data >> 32) != 0)
2612                         return 1;
2613                 /* Otherwise falls through */
2614         default:
2615                 msr = find_msr_entry(vmx, msr_index);
2616                 if (msr) {
2617                         msr->data = data;
2618                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619                                 preempt_disable();
2620                                 kvm_set_shared_msr(msr->index, msr->data,
2621                                                    msr->mask);
2622                                 preempt_enable();
2623                         }
2624                         break;
2625                 }
2626                 ret = kvm_set_msr_common(vcpu, msr_info);
2627         }
2628
2629         return ret;
2630 }
2631
2632 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2633 {
2634         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635         switch (reg) {
2636         case VCPU_REGS_RSP:
2637                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638                 break;
2639         case VCPU_REGS_RIP:
2640                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641                 break;
2642         case VCPU_EXREG_PDPTR:
2643                 if (enable_ept)
2644                         ept_save_pdptrs(vcpu);
2645                 break;
2646         default:
2647                 break;
2648         }
2649 }
2650
2651 static __init int cpu_has_kvm_support(void)
2652 {
2653         return cpu_has_vmx();
2654 }
2655
2656 static __init int vmx_disabled_by_bios(void)
2657 {
2658         u64 msr;
2659
2660         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2661         if (msr & FEATURE_CONTROL_LOCKED) {
2662                 /* launched w/ TXT and VMX disabled */
2663                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664                         && tboot_enabled())
2665                         return 1;
2666                 /* launched w/o TXT and VMX only enabled w/ TXT */
2667                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2669                         && !tboot_enabled()) {
2670                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2671                                 "activate TXT before enabling KVM\n");
2672                         return 1;
2673                 }
2674                 /* launched w/o TXT and VMX disabled */
2675                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676                         && !tboot_enabled())
2677                         return 1;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static void kvm_cpu_vmxon(u64 addr)
2684 {
2685         asm volatile (ASM_VMX_VMXON_RAX
2686                         : : "a"(&addr), "m"(addr)
2687                         : "memory", "cc");
2688 }
2689
2690 static int hardware_enable(void *garbage)
2691 {
2692         int cpu = raw_smp_processor_id();
2693         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2694         u64 old, test_bits;
2695
2696         if (read_cr4() & X86_CR4_VMXE)
2697                 return -EBUSY;
2698
2699         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2700
2701         /*
2702          * Now we can enable the vmclear operation in kdump
2703          * since the loaded_vmcss_on_cpu list on this cpu
2704          * has been initialized.
2705          *
2706          * Though the cpu is not in VMX operation now, there
2707          * is no problem to enable the vmclear operation
2708          * for the loaded_vmcss_on_cpu list is empty!
2709          */
2710         crash_enable_local_vmclear(cpu);
2711
2712         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2713
2714         test_bits = FEATURE_CONTROL_LOCKED;
2715         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716         if (tboot_enabled())
2717                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719         if ((old & test_bits) != test_bits) {
2720                 /* enable and lock */
2721                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722         }
2723         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2724
2725         if (vmm_exclusive) {
2726                 kvm_cpu_vmxon(phys_addr);
2727                 ept_sync_global();
2728         }
2729
2730         native_store_gdt(&__get_cpu_var(host_gdt));
2731
2732         return 0;
2733 }
2734
2735 static void vmclear_local_loaded_vmcss(void)
2736 {
2737         int cpu = raw_smp_processor_id();
2738         struct loaded_vmcs *v, *n;
2739
2740         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741                                  loaded_vmcss_on_cpu_link)
2742                 __loaded_vmcs_clear(v);
2743 }
2744
2745
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747  * tricks.
2748  */
2749 static void kvm_cpu_vmxoff(void)
2750 {
2751         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2752 }
2753
2754 static void hardware_disable(void *garbage)
2755 {
2756         if (vmm_exclusive) {
2757                 vmclear_local_loaded_vmcss();
2758                 kvm_cpu_vmxoff();
2759         }
2760         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2761 }
2762
2763 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2764                                       u32 msr, u32 *result)
2765 {
2766         u32 vmx_msr_low, vmx_msr_high;
2767         u32 ctl = ctl_min | ctl_opt;
2768
2769         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2773
2774         /* Ensure minimum (required) set of control bits are supported. */
2775         if (ctl_min & ~ctl)
2776                 return -EIO;
2777
2778         *result = ctl;
2779         return 0;
2780 }
2781
2782 static __init bool allow_1_setting(u32 msr, u32 ctl)
2783 {
2784         u32 vmx_msr_low, vmx_msr_high;
2785
2786         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787         return vmx_msr_high & ctl;
2788 }
2789
2790 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2791 {
2792         u32 vmx_msr_low, vmx_msr_high;
2793         u32 min, opt, min2, opt2;
2794         u32 _pin_based_exec_control = 0;
2795         u32 _cpu_based_exec_control = 0;
2796         u32 _cpu_based_2nd_exec_control = 0;
2797         u32 _vmexit_control = 0;
2798         u32 _vmentry_control = 0;
2799
2800         min = CPU_BASED_HLT_EXITING |
2801 #ifdef CONFIG_X86_64
2802               CPU_BASED_CR8_LOAD_EXITING |
2803               CPU_BASED_CR8_STORE_EXITING |
2804 #endif
2805               CPU_BASED_CR3_LOAD_EXITING |
2806               CPU_BASED_CR3_STORE_EXITING |
2807               CPU_BASED_USE_IO_BITMAPS |
2808               CPU_BASED_MOV_DR_EXITING |
2809               CPU_BASED_USE_TSC_OFFSETING |
2810               CPU_BASED_MWAIT_EXITING |
2811               CPU_BASED_MONITOR_EXITING |
2812               CPU_BASED_INVLPG_EXITING |
2813               CPU_BASED_RDPMC_EXITING;
2814
2815         opt = CPU_BASED_TPR_SHADOW |
2816               CPU_BASED_USE_MSR_BITMAPS |
2817               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819                                 &_cpu_based_exec_control) < 0)
2820                 return -EIO;
2821 #ifdef CONFIG_X86_64
2822         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824                                            ~CPU_BASED_CR8_STORE_EXITING;
2825 #endif
2826         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2827                 min2 = 0;
2828                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2829                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2830                         SECONDARY_EXEC_WBINVD_EXITING |
2831                         SECONDARY_EXEC_ENABLE_VPID |
2832                         SECONDARY_EXEC_ENABLE_EPT |
2833                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2834                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2835                         SECONDARY_EXEC_RDTSCP |
2836                         SECONDARY_EXEC_ENABLE_INVPCID |
2837                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2838                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839                         SECONDARY_EXEC_SHADOW_VMCS;
2840                 if (adjust_vmx_controls(min2, opt2,
2841                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2842                                         &_cpu_based_2nd_exec_control) < 0)
2843                         return -EIO;
2844         }
2845 #ifndef CONFIG_X86_64
2846         if (!(_cpu_based_2nd_exec_control &
2847                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849 #endif
2850
2851         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852                 _cpu_based_2nd_exec_control &= ~(
2853                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2854                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2856
2857         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2858                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859                    enabled */
2860                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861                                              CPU_BASED_CR3_STORE_EXITING |
2862                                              CPU_BASED_INVLPG_EXITING);
2863                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864                       vmx_capability.ept, vmx_capability.vpid);
2865         }
2866
2867         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2868 #ifdef CONFIG_X86_64
2869         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870 #endif
2871         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2872                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2873         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874                                 &_vmexit_control) < 0)
2875                 return -EIO;
2876
2877         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880                                 &_pin_based_exec_control) < 0)
2881                 return -EIO;
2882
2883         if (!(_cpu_based_2nd_exec_control &
2884                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
2888         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2889         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2890         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891                                 &_vmentry_control) < 0)
2892                 return -EIO;
2893
2894         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2895
2896         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2898                 return -EIO;
2899
2900 #ifdef CONFIG_X86_64
2901         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902         if (vmx_msr_high & (1u<<16))
2903                 return -EIO;
2904 #endif
2905
2906         /* Require Write-Back (WB) memory type for VMCS accesses. */
2907         if (((vmx_msr_high >> 18) & 15) != 6)
2908                 return -EIO;
2909
2910         vmcs_conf->size = vmx_msr_high & 0x1fff;
2911         vmcs_conf->order = get_order(vmcs_config.size);
2912         vmcs_conf->revision_id = vmx_msr_low;
2913
2914         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2916         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2917         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2918         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2919
2920         cpu_has_load_ia32_efer =
2921                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922                                 VM_ENTRY_LOAD_IA32_EFER)
2923                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924                                    VM_EXIT_LOAD_IA32_EFER);
2925
2926         cpu_has_load_perf_global_ctrl =
2927                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932         /*
2933          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934          * but due to arrata below it can't be used. Workaround is to use
2935          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936          *
2937          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938          *
2939          * AAK155             (model 26)
2940          * AAP115             (model 30)
2941          * AAT100             (model 37)
2942          * BC86,AAY89,BD102   (model 44)
2943          * BA97               (model 46)
2944          *
2945          */
2946         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947                 switch (boot_cpu_data.x86_model) {
2948                 case 26:
2949                 case 30:
2950                 case 37:
2951                 case 44:
2952                 case 46:
2953                         cpu_has_load_perf_global_ctrl = false;
2954                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955                                         "does not work properly. Using workaround\n");
2956                         break;
2957                 default:
2958                         break;
2959                 }
2960         }
2961
2962         return 0;
2963 }
2964
2965 static struct vmcs *alloc_vmcs_cpu(int cpu)
2966 {
2967         int node = cpu_to_node(cpu);
2968         struct page *pages;
2969         struct vmcs *vmcs;
2970
2971         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2972         if (!pages)
2973                 return NULL;
2974         vmcs = page_address(pages);
2975         memset(vmcs, 0, vmcs_config.size);
2976         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2977         return vmcs;
2978 }
2979
2980 static struct vmcs *alloc_vmcs(void)
2981 {
2982         return alloc_vmcs_cpu(raw_smp_processor_id());
2983 }
2984
2985 static void free_vmcs(struct vmcs *vmcs)
2986 {
2987         free_pages((unsigned long)vmcs, vmcs_config.order);
2988 }
2989
2990 /*
2991  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992  */
2993 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994 {
2995         if (!loaded_vmcs->vmcs)
2996                 return;
2997         loaded_vmcs_clear(loaded_vmcs);
2998         free_vmcs(loaded_vmcs->vmcs);
2999         loaded_vmcs->vmcs = NULL;
3000 }
3001
3002 static void free_kvm_area(void)
3003 {
3004         int cpu;
3005
3006         for_each_possible_cpu(cpu) {
3007                 free_vmcs(per_cpu(vmxarea, cpu));
3008                 per_cpu(vmxarea, cpu) = NULL;
3009         }
3010 }
3011
3012 static void init_vmcs_shadow_fields(void)
3013 {
3014         int i, j;
3015
3016         /* No checks for read only fields yet */
3017
3018         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3019                 switch (shadow_read_write_fields[i]) {
3020                 case GUEST_BNDCFGS:
3021                         if (!vmx_mpx_supported())
3022                                 continue;
3023                         break;
3024                 default:
3025                         break;
3026                 }
3027
3028                 if (j < i)
3029                         shadow_read_write_fields[j] =
3030                                 shadow_read_write_fields[i];
3031                 j++;
3032         }
3033         max_shadow_read_write_fields = j;
3034
3035         /* shadowed fields guest access without vmexit */
3036         for (i = 0; i < max_shadow_read_write_fields; i++) {
3037                 clear_bit(shadow_read_write_fields[i],
3038                           vmx_vmwrite_bitmap);
3039                 clear_bit(shadow_read_write_fields[i],
3040                           vmx_vmread_bitmap);
3041         }
3042         for (i = 0; i < max_shadow_read_only_fields; i++)
3043                 clear_bit(shadow_read_only_fields[i],
3044                           vmx_vmread_bitmap);
3045 }
3046
3047 static __init int alloc_kvm_area(void)
3048 {
3049         int cpu;
3050
3051         for_each_possible_cpu(cpu) {
3052                 struct vmcs *vmcs;
3053
3054                 vmcs = alloc_vmcs_cpu(cpu);
3055                 if (!vmcs) {
3056                         free_kvm_area();
3057                         return -ENOMEM;
3058                 }
3059
3060                 per_cpu(vmxarea, cpu) = vmcs;
3061         }
3062         return 0;
3063 }
3064
3065 static __init int hardware_setup(void)
3066 {
3067         if (setup_vmcs_config(&vmcs_config) < 0)
3068                 return -EIO;
3069
3070         if (boot_cpu_has(X86_FEATURE_NX))
3071                 kvm_enable_efer_bits(EFER_NX);
3072
3073         if (!cpu_has_vmx_vpid())
3074                 enable_vpid = 0;
3075         if (!cpu_has_vmx_shadow_vmcs())
3076                 enable_shadow_vmcs = 0;
3077         if (enable_shadow_vmcs)
3078                 init_vmcs_shadow_fields();
3079
3080         if (!cpu_has_vmx_ept() ||
3081             !cpu_has_vmx_ept_4levels()) {
3082                 enable_ept = 0;
3083                 enable_unrestricted_guest = 0;
3084                 enable_ept_ad_bits = 0;
3085         }
3086
3087         if (!cpu_has_vmx_ept_ad_bits())
3088                 enable_ept_ad_bits = 0;
3089
3090         if (!cpu_has_vmx_unrestricted_guest())
3091                 enable_unrestricted_guest = 0;
3092
3093         if (!cpu_has_vmx_flexpriority())
3094                 flexpriority_enabled = 0;
3095
3096         if (!cpu_has_vmx_tpr_shadow())
3097                 kvm_x86_ops->update_cr8_intercept = NULL;
3098
3099         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3100                 kvm_disable_largepages();
3101
3102         if (!cpu_has_vmx_ple())
3103                 ple_gap = 0;
3104
3105         if (!cpu_has_vmx_apicv())
3106                 enable_apicv = 0;
3107
3108         if (enable_apicv)
3109                 kvm_x86_ops->update_cr8_intercept = NULL;
3110         else {
3111                 kvm_x86_ops->hwapic_irr_update = NULL;
3112                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3113                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3114         }
3115
3116         if (nested)
3117                 nested_vmx_setup_ctls_msrs();
3118
3119         return alloc_kvm_area();
3120 }
3121
3122 static __exit void hardware_unsetup(void)
3123 {
3124         free_kvm_area();
3125 }
3126
3127 static bool emulation_required(struct kvm_vcpu *vcpu)
3128 {
3129         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3130 }
3131
3132 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3133                 struct kvm_segment *save)
3134 {
3135         if (!emulate_invalid_guest_state) {
3136                 /*
3137                  * CS and SS RPL should be equal during guest entry according
3138                  * to VMX spec, but in reality it is not always so. Since vcpu
3139                  * is in the middle of the transition from real mode to
3140                  * protected mode it is safe to assume that RPL 0 is a good
3141                  * default value.
3142                  */
3143                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3144                         save->selector &= ~SELECTOR_RPL_MASK;
3145                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3146                 save->s = 1;
3147         }
3148         vmx_set_segment(vcpu, save, seg);
3149 }
3150
3151 static void enter_pmode(struct kvm_vcpu *vcpu)
3152 {
3153         unsigned long flags;
3154         struct vcpu_vmx *vmx = to_vmx(vcpu);
3155
3156         /*
3157          * Update real mode segment cache. It may be not up-to-date if sement
3158          * register was written while vcpu was in a guest mode.
3159          */
3160         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3161         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3162         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3163         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3164         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3165         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3166
3167         vmx->rmode.vm86_active = 0;
3168
3169         vmx_segment_cache_clear(vmx);
3170
3171         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3172
3173         flags = vmcs_readl(GUEST_RFLAGS);
3174         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3175         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3176         vmcs_writel(GUEST_RFLAGS, flags);
3177
3178         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3179                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3180
3181         update_exception_bitmap(vcpu);
3182
3183         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3184         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3185         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3186         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3187         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3188         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3189
3190         /* CPL is always 0 when CPU enters protected mode */
3191         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3192         vmx->cpl = 0;
3193 }
3194
3195 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3196 {
3197         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3198         struct kvm_segment var = *save;
3199
3200         var.dpl = 0x3;
3201         if (seg == VCPU_SREG_CS)
3202                 var.type = 0x3;
3203
3204         if (!emulate_invalid_guest_state) {
3205                 var.selector = var.base >> 4;
3206                 var.base = var.base & 0xffff0;
3207                 var.limit = 0xffff;
3208                 var.g = 0;
3209                 var.db = 0;
3210                 var.present = 1;
3211                 var.s = 1;
3212                 var.l = 0;
3213                 var.unusable = 0;
3214                 var.type = 0x3;
3215                 var.avl = 0;
3216                 if (save->base & 0xf)
3217                         printk_once(KERN_WARNING "kvm: segment base is not "
3218                                         "paragraph aligned when entering "
3219                                         "protected mode (seg=%d)", seg);
3220         }
3221
3222         vmcs_write16(sf->selector, var.selector);
3223         vmcs_write32(sf->base, var.base);
3224         vmcs_write32(sf->limit, var.limit);
3225         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3226 }
3227
3228 static void enter_rmode(struct kvm_vcpu *vcpu)
3229 {
3230         unsigned long flags;
3231         struct vcpu_vmx *vmx = to_vmx(vcpu);
3232
3233         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3234         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3235         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3236         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3237         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3238         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3239         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3240
3241         vmx->rmode.vm86_active = 1;
3242
3243         /*
3244          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3245          * vcpu. Warn the user that an update is overdue.
3246          */
3247         if (!vcpu->kvm->arch.tss_addr)
3248                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3249                              "called before entering vcpu\n");
3250
3251         vmx_segment_cache_clear(vmx);
3252
3253         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3254         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3255         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3256
3257         flags = vmcs_readl(GUEST_RFLAGS);
3258         vmx->rmode.save_rflags = flags;
3259
3260         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3261
3262         vmcs_writel(GUEST_RFLAGS, flags);
3263         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3264         update_exception_bitmap(vcpu);
3265
3266         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3267         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3268         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3269         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3270         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3271         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3272
3273         kvm_mmu_reset_context(vcpu);
3274 }
3275
3276 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3277 {
3278         struct vcpu_vmx *vmx = to_vmx(vcpu);
3279         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3280
3281         if (!msr)
3282                 return;
3283
3284         /*
3285          * Force kernel_gs_base reloading before EFER changes, as control
3286          * of this msr depends on is_long_mode().
3287          */
3288         vmx_load_host_state(to_vmx(vcpu));
3289         vcpu->arch.efer = efer;
3290         if (efer & EFER_LMA) {
3291                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3292                 msr->data = efer;
3293         } else {
3294                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3295
3296                 msr->data = efer & ~EFER_LME;
3297         }
3298         setup_msrs(vmx);
3299 }
3300
3301 #ifdef CONFIG_X86_64
3302
3303 static void enter_lmode(struct kvm_vcpu *vcpu)
3304 {
3305         u32 guest_tr_ar;
3306
3307         vmx_segment_cache_clear(to_vmx(vcpu));
3308
3309         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3310         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3311                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3312                                      __func__);
3313                 vmcs_write32(GUEST_TR_AR_BYTES,
3314                              (guest_tr_ar & ~AR_TYPE_MASK)
3315                              | AR_TYPE_BUSY_64_TSS);
3316         }
3317         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3318 }
3319
3320 static void exit_lmode(struct kvm_vcpu *vcpu)
3321 {
3322         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3323         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3324 }
3325
3326 #endif
3327
3328 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3329 {
3330         vpid_sync_context(to_vmx(vcpu));
3331         if (enable_ept) {
3332                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3333                         return;
3334                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3335         }
3336 }
3337
3338 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3339 {
3340         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3341
3342         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3343         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3344 }
3345
3346 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3347 {
3348         if (enable_ept && is_paging(vcpu))
3349                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3350         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3351 }
3352
3353 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3354 {
3355         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3356
3357         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3358         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3359 }
3360
3361 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3362 {
3363         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3364
3365         if (!test_bit(VCPU_EXREG_PDPTR,
3366                       (unsigned long *)&vcpu->arch.regs_dirty))
3367                 return;
3368
3369         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3370                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3371                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3372                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3373                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3374         }
3375 }
3376
3377 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3378 {
3379         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3380
3381         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3382                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3383                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3384                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3385                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3386         }
3387
3388         __set_bit(VCPU_EXREG_PDPTR,
3389                   (unsigned long *)&vcpu->arch.regs_avail);
3390         __set_bit(VCPU_EXREG_PDPTR,
3391                   (unsigned long *)&vcpu->arch.regs_dirty);
3392 }
3393
3394 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3395
3396 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3397                                         unsigned long cr0,
3398                                         struct kvm_vcpu *vcpu)
3399 {
3400         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3401                 vmx_decache_cr3(vcpu);
3402         if (!(cr0 & X86_CR0_PG)) {
3403                 /* From paging/starting to nonpaging */
3404                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3405                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3406                              (CPU_BASED_CR3_LOAD_EXITING |
3407                               CPU_BASED_CR3_STORE_EXITING));
3408                 vcpu->arch.cr0 = cr0;
3409                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3410         } else if (!is_paging(vcpu)) {
3411                 /* From nonpaging to paging */
3412                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3413                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3414                              ~(CPU_BASED_CR3_LOAD_EXITING |
3415                                CPU_BASED_CR3_STORE_EXITING));
3416                 vcpu->arch.cr0 = cr0;
3417                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3418         }
3419
3420         if (!(cr0 & X86_CR0_WP))
3421                 *hw_cr0 &= ~X86_CR0_WP;
3422 }
3423
3424 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3425 {
3426         struct vcpu_vmx *vmx = to_vmx(vcpu);
3427         unsigned long hw_cr0;
3428
3429         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3430         if (enable_unrestricted_guest)
3431                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3432         else {
3433                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3434
3435                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3436                         enter_pmode(vcpu);
3437
3438                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3439                         enter_rmode(vcpu);
3440         }
3441
3442 #ifdef CONFIG_X86_64
3443         if (vcpu->arch.efer & EFER_LME) {
3444                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3445                         enter_lmode(vcpu);
3446                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3447                         exit_lmode(vcpu);
3448         }
3449 #endif
3450
3451         if (enable_ept)
3452                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3453
3454         if (!vcpu->fpu_active)
3455                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3456
3457         vmcs_writel(CR0_READ_SHADOW, cr0);
3458         vmcs_writel(GUEST_CR0, hw_cr0);
3459         vcpu->arch.cr0 = cr0;
3460
3461         /* depends on vcpu->arch.cr0 to be set to a new value */
3462         vmx->emulation_required = emulation_required(vcpu);
3463 }
3464
3465 static u64 construct_eptp(unsigned long root_hpa)
3466 {
3467         u64 eptp;
3468
3469         /* TODO write the value reading from MSR */
3470         eptp = VMX_EPT_DEFAULT_MT |
3471                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3472         if (enable_ept_ad_bits)
3473                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3474         eptp |= (root_hpa & PAGE_MASK);
3475
3476         return eptp;
3477 }
3478
3479 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3480 {
3481         unsigned long guest_cr3;
3482         u64 eptp;
3483
3484         guest_cr3 = cr3;
3485         if (enable_ept) {
3486                 eptp = construct_eptp(cr3);
3487                 vmcs_write64(EPT_POINTER, eptp);
3488                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3489                         guest_cr3 = kvm_read_cr3(vcpu);
3490                 else
3491                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3492                 ept_load_pdptrs(vcpu);
3493         }
3494
3495         vmx_flush_tlb(vcpu);
3496         vmcs_writel(GUEST_CR3, guest_cr3);
3497 }
3498
3499 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3500 {
3501         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3502                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3503
3504         if (cr4 & X86_CR4_VMXE) {
3505                 /*
3506                  * To use VMXON (and later other VMX instructions), a guest
3507                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3508                  * So basically the check on whether to allow nested VMX
3509                  * is here.
3510                  */
3511                 if (!nested_vmx_allowed(vcpu))
3512                         return 1;
3513         }
3514         if (to_vmx(vcpu)->nested.vmxon &&
3515             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3516                 return 1;
3517
3518         vcpu->arch.cr4 = cr4;
3519         if (enable_ept) {
3520                 if (!is_paging(vcpu)) {
3521                         hw_cr4 &= ~X86_CR4_PAE;
3522                         hw_cr4 |= X86_CR4_PSE;
3523                         /*
3524                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3525                          * in hardware. However KVM always uses paging mode to
3526                          * emulate guest non-paging mode with TDP.
3527                          * To emulate this behavior, SMEP/SMAP needs to be
3528                          * manually disabled when guest switches to non-paging
3529                          * mode.
3530                          */
3531                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3532                 } else if (!(cr4 & X86_CR4_PAE)) {
3533                         hw_cr4 &= ~X86_CR4_PAE;
3534                 }
3535         }
3536
3537         vmcs_writel(CR4_READ_SHADOW, cr4);
3538         vmcs_writel(GUEST_CR4, hw_cr4);
3539         return 0;
3540 }
3541
3542 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3543                             struct kvm_segment *var, int seg)
3544 {
3545         struct vcpu_vmx *vmx = to_vmx(vcpu);
3546         u32 ar;
3547
3548         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3549                 *var = vmx->rmode.segs[seg];
3550                 if (seg == VCPU_SREG_TR
3551                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3552                         return;
3553                 var->base = vmx_read_guest_seg_base(vmx, seg);
3554                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3555                 return;
3556         }
3557         var->base = vmx_read_guest_seg_base(vmx, seg);
3558         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3559         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3560         ar = vmx_read_guest_seg_ar(vmx, seg);
3561         var->unusable = (ar >> 16) & 1;
3562         var->type = ar & 15;
3563         var->s = (ar >> 4) & 1;
3564         var->dpl = (ar >> 5) & 3;
3565         /*
3566          * Some userspaces do not preserve unusable property. Since usable
3567          * segment has to be present according to VMX spec we can use present
3568          * property to amend userspace bug by making unusable segment always
3569          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3570          * segment as unusable.
3571          */
3572         var->present = !var->unusable;
3573         var->avl = (ar >> 12) & 1;
3574         var->l = (ar >> 13) & 1;
3575         var->db = (ar >> 14) & 1;
3576         var->g = (ar >> 15) & 1;
3577 }
3578
3579 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3580 {
3581         struct kvm_segment s;
3582
3583         if (to_vmx(vcpu)->rmode.vm86_active) {
3584                 vmx_get_segment(vcpu, &s, seg);
3585                 return s.base;
3586         }
3587         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3588 }
3589
3590 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3591 {
3592         struct vcpu_vmx *vmx = to_vmx(vcpu);
3593
3594         if (!is_protmode(vcpu))
3595                 return 0;
3596
3597         if (!is_long_mode(vcpu)
3598             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3599                 return 3;
3600
3601         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3602                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3603                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3604         }
3605
3606         return vmx->cpl;
3607 }
3608
3609
3610 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3611 {
3612         u32 ar;
3613
3614         if (var->unusable || !var->present)
3615                 ar = 1 << 16;
3616         else {
3617                 ar = var->type & 15;
3618                 ar |= (var->s & 1) << 4;
3619                 ar |= (var->dpl & 3) << 5;
3620                 ar |= (var->present & 1) << 7;
3621                 ar |= (var->avl & 1) << 12;
3622                 ar |= (var->l & 1) << 13;
3623                 ar |= (var->db & 1) << 14;
3624                 ar |= (var->g & 1) << 15;
3625         }
3626
3627         return ar;
3628 }
3629
3630 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3631                             struct kvm_segment *var, int seg)
3632 {
3633         struct vcpu_vmx *vmx = to_vmx(vcpu);
3634         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3635
3636         vmx_segment_cache_clear(vmx);
3637         if (seg == VCPU_SREG_CS)
3638                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3639
3640         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3641                 vmx->rmode.segs[seg] = *var;
3642                 if (seg == VCPU_SREG_TR)
3643                         vmcs_write16(sf->selector, var->selector);
3644                 else if (var->s)
3645                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3646                 goto out;
3647         }
3648
3649         vmcs_writel(sf->base, var->base);
3650         vmcs_write32(sf->limit, var->limit);
3651         vmcs_write16(sf->selector, var->selector);
3652
3653         /*
3654          *   Fix the "Accessed" bit in AR field of segment registers for older
3655          * qemu binaries.
3656          *   IA32 arch specifies that at the time of processor reset the
3657          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3658          * is setting it to 0 in the userland code. This causes invalid guest
3659          * state vmexit when "unrestricted guest" mode is turned on.
3660          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3661          * tree. Newer qemu binaries with that qemu fix would not need this
3662          * kvm hack.
3663          */
3664         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3665                 var->type |= 0x1; /* Accessed */
3666
3667         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3668
3669 out:
3670         vmx->emulation_required |= emulation_required(vcpu);
3671 }
3672
3673 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3674 {
3675         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3676
3677         *db = (ar >> 14) & 1;
3678         *l = (ar >> 13) & 1;
3679 }
3680
3681 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3682 {
3683         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3684         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3685 }
3686
3687 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3688 {
3689         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3690         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3691 }
3692
3693 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3694 {
3695         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3696         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3697 }
3698
3699 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3700 {
3701         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3702         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3703 }
3704
3705 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3706 {
3707         struct kvm_segment var;
3708         u32 ar;
3709
3710         vmx_get_segment(vcpu, &var, seg);
3711         var.dpl = 0x3;
3712         if (seg == VCPU_SREG_CS)
3713                 var.type = 0x3;
3714         ar = vmx_segment_access_rights(&var);
3715
3716         if (var.base != (var.selector << 4))
3717                 return false;
3718         if (var.limit != 0xffff)
3719                 return false;
3720         if (ar != 0xf3)
3721                 return false;
3722
3723         return true;
3724 }
3725
3726 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3727 {
3728         struct kvm_segment cs;
3729         unsigned int cs_rpl;
3730
3731         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3732         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3733
3734         if (cs.unusable)
3735                 return false;
3736         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3737                 return false;
3738         if (!cs.s)
3739                 return false;
3740         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3741                 if (cs.dpl > cs_rpl)
3742                         return false;
3743         } else {
3744                 if (cs.dpl != cs_rpl)
3745                         return false;
3746         }
3747         if (!cs.present)
3748                 return false;
3749
3750         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3751         return true;
3752 }
3753
3754 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3755 {
3756         struct kvm_segment ss;
3757         unsigned int ss_rpl;
3758
3759         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3760         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3761
3762         if (ss.unusable)
3763                 return true;
3764         if (ss.type != 3 && ss.type != 7)
3765                 return false;
3766         if (!ss.s)
3767                 return false;
3768         if (ss.dpl != ss_rpl) /* DPL != RPL */
3769                 return false;
3770         if (!ss.present)
3771                 return false;
3772
3773         return true;
3774 }
3775
3776 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3777 {
3778         struct kvm_segment var;
3779         unsigned int rpl;
3780
3781         vmx_get_segment(vcpu, &var, seg);
3782         rpl = var.selector & SELECTOR_RPL_MASK;
3783
3784         if (var.unusable)
3785                 return true;
3786         if (!var.s)
3787                 return false;
3788         if (!var.present)
3789                 return false;
3790         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3791                 if (var.dpl < rpl) /* DPL < RPL */
3792                         return false;
3793         }
3794
3795         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3796          * rights flags
3797          */
3798         return true;
3799 }
3800
3801 static bool tr_valid(struct kvm_vcpu *vcpu)
3802 {
3803         struct kvm_segment tr;
3804
3805         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3806
3807         if (tr.unusable)
3808                 return false;
3809         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3810                 return false;
3811         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3812                 return false;
3813         if (!tr.present)
3814                 return false;
3815
3816         return true;
3817 }
3818
3819 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3820 {
3821         struct kvm_segment ldtr;
3822
3823         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3824
3825         if (ldtr.unusable)
3826                 return true;
3827         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3828                 return false;
3829         if (ldtr.type != 2)
3830                 return false;
3831         if (!ldtr.present)
3832                 return false;
3833
3834         return true;
3835 }
3836
3837 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3838 {
3839         struct kvm_segment cs, ss;
3840
3841         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3842         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3843
3844         return ((cs.selector & SELECTOR_RPL_MASK) ==
3845                  (ss.selector & SELECTOR_RPL_MASK));
3846 }
3847
3848 /*
3849  * Check if guest state is valid. Returns true if valid, false if
3850  * not.
3851  * We assume that registers are always usable
3852  */
3853 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3854 {
3855         if (enable_unrestricted_guest)
3856                 return true;
3857
3858         /* real mode guest state checks */
3859         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3860                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3861                         return false;
3862                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3863                         return false;
3864                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3865                         return false;
3866                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3867                         return false;
3868                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3869                         return false;
3870                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3871                         return false;
3872         } else {
3873         /* protected mode guest state checks */
3874                 if (!cs_ss_rpl_check(vcpu))
3875                         return false;
3876                 if (!code_segment_valid(vcpu))
3877                         return false;
3878                 if (!stack_segment_valid(vcpu))
3879                         return false;
3880                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3881                         return false;
3882                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3883                         return false;
3884                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3885                         return false;
3886                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3887                         return false;
3888                 if (!tr_valid(vcpu))
3889                         return false;
3890                 if (!ldtr_valid(vcpu))
3891                         return false;
3892         }
3893         /* TODO:
3894          * - Add checks on RIP
3895          * - Add checks on RFLAGS
3896          */
3897
3898         return true;
3899 }
3900
3901 static int init_rmode_tss(struct kvm *kvm)
3902 {
3903         gfn_t fn;
3904         u16 data = 0;
3905         int r, idx, ret = 0;
3906
3907         idx = srcu_read_lock(&kvm->srcu);
3908         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3909         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3910         if (r < 0)
3911                 goto out;
3912         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3913         r = kvm_write_guest_page(kvm, fn++, &data,
3914                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3915         if (r < 0)
3916                 goto out;
3917         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3918         if (r < 0)
3919                 goto out;
3920         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3921         if (r < 0)
3922                 goto out;
3923         data = ~0;
3924         r = kvm_write_guest_page(kvm, fn, &data,
3925                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3926                                  sizeof(u8));
3927         if (r < 0)
3928                 goto out;
3929
3930         ret = 1;
3931 out:
3932         srcu_read_unlock(&kvm->srcu, idx);
3933         return ret;
3934 }
3935
3936 static int init_rmode_identity_map(struct kvm *kvm)
3937 {
3938         int i, idx, r, ret;
3939         pfn_t identity_map_pfn;
3940         u32 tmp;
3941
3942         if (!enable_ept)
3943                 return 1;
3944         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3945                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3946                         "haven't been allocated!\n");
3947                 return 0;
3948         }
3949         if (likely(kvm->arch.ept_identity_pagetable_done))
3950                 return 1;
3951         ret = 0;
3952         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3953         idx = srcu_read_lock(&kvm->srcu);
3954         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3955         if (r < 0)
3956                 goto out;
3957         /* Set up identity-mapping pagetable for EPT in real mode */
3958         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3959                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3960                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3961                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3962                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3963                 if (r < 0)
3964                         goto out;
3965         }
3966         kvm->arch.ept_identity_pagetable_done = true;
3967         ret = 1;
3968 out:
3969         srcu_read_unlock(&kvm->srcu, idx);
3970         return ret;
3971 }
3972
3973 static void seg_setup(int seg)
3974 {
3975         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3976         unsigned int ar;
3977
3978         vmcs_write16(sf->selector, 0);
3979         vmcs_writel(sf->base, 0);
3980         vmcs_write32(sf->limit, 0xffff);
3981         ar = 0x93;
3982         if (seg == VCPU_SREG_CS)
3983                 ar |= 0x08; /* code segment */
3984
3985         vmcs_write32(sf->ar_bytes, ar);
3986 }
3987
3988 static int alloc_apic_access_page(struct kvm *kvm)
3989 {
3990         struct page *page;
3991         struct kvm_userspace_memory_region kvm_userspace_mem;
3992         int r = 0;
3993
3994         mutex_lock(&kvm->slots_lock);
3995         if (kvm->arch.apic_access_page)
3996                 goto out;
3997         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3998         kvm_userspace_mem.flags = 0;
3999         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4000         kvm_userspace_mem.memory_size = PAGE_SIZE;
4001         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4002         if (r)
4003                 goto out;
4004
4005         page = gfn_to_page(kvm, 0xfee00);
4006         if (is_error_page(page)) {
4007                 r = -EFAULT;
4008                 goto out;
4009         }
4010
4011         kvm->arch.apic_access_page = page;
4012 out:
4013         mutex_unlock(&kvm->slots_lock);
4014         return r;
4015 }
4016
4017 static int alloc_identity_pagetable(struct kvm *kvm)
4018 {
4019         struct page *page;
4020         struct kvm_userspace_memory_region kvm_userspace_mem;
4021         int r = 0;
4022
4023         mutex_lock(&kvm->slots_lock);
4024         if (kvm->arch.ept_identity_pagetable)
4025                 goto out;
4026         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4027         kvm_userspace_mem.flags = 0;
4028         kvm_userspace_mem.guest_phys_addr =
4029                 kvm->arch.ept_identity_map_addr;
4030         kvm_userspace_mem.memory_size = PAGE_SIZE;
4031         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4032         if (r)
4033                 goto out;
4034
4035         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4036         if (is_error_page(page)) {
4037                 r = -EFAULT;
4038                 goto out;
4039         }
4040
4041         kvm->arch.ept_identity_pagetable = page;
4042 out:
4043         mutex_unlock(&kvm->slots_lock);
4044         return r;
4045 }
4046
4047 static void allocate_vpid(struct vcpu_vmx *vmx)
4048 {
4049         int vpid;
4050
4051         vmx->vpid = 0;
4052         if (!enable_vpid)
4053                 return;
4054         spin_lock(&vmx_vpid_lock);
4055         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4056         if (vpid < VMX_NR_VPIDS) {
4057                 vmx->vpid = vpid;
4058                 __set_bit(vpid, vmx_vpid_bitmap);
4059         }
4060         spin_unlock(&vmx_vpid_lock);
4061 }
4062
4063 static void free_vpid(struct vcpu_vmx *vmx)
4064 {
4065         if (!enable_vpid)
4066                 return;
4067         spin_lock(&vmx_vpid_lock);
4068         if (vmx->vpid != 0)
4069                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4070         spin_unlock(&vmx_vpid_lock);
4071 }
4072
4073 #define MSR_TYPE_R      1
4074 #define MSR_TYPE_W      2
4075 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4076                                                 u32 msr, int type)
4077 {
4078         int f = sizeof(unsigned long);
4079
4080         if (!cpu_has_vmx_msr_bitmap())
4081                 return;
4082
4083         /*
4084          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4085          * have the write-low and read-high bitmap offsets the wrong way round.
4086          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4087          */
4088         if (msr <= 0x1fff) {
4089                 if (type & MSR_TYPE_R)
4090                         /* read-low */
4091                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4092
4093                 if (type & MSR_TYPE_W)
4094                         /* write-low */
4095                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4096
4097         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4098                 msr &= 0x1fff;
4099                 if (type & MSR_TYPE_R)
4100                         /* read-high */
4101                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4102
4103                 if (type & MSR_TYPE_W)
4104                         /* write-high */
4105                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4106
4107         }
4108 }
4109
4110 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4111                                                 u32 msr, int type)
4112 {
4113         int f = sizeof(unsigned long);
4114
4115         if (!cpu_has_vmx_msr_bitmap())
4116                 return;
4117
4118         /*
4119          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4120          * have the write-low and read-high bitmap offsets the wrong way round.
4121          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4122          */
4123         if (msr <= 0x1fff) {
4124                 if (type & MSR_TYPE_R)
4125                         /* read-low */
4126                         __set_bit(msr, msr_bitmap + 0x000 / f);
4127
4128                 if (type & MSR_TYPE_W)
4129                         /* write-low */
4130                         __set_bit(msr, msr_bitmap + 0x800 / f);
4131
4132         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4133                 msr &= 0x1fff;
4134                 if (type & MSR_TYPE_R)
4135                         /* read-high */
4136                         __set_bit(msr, msr_bitmap + 0x400 / f);
4137
4138                 if (type & MSR_TYPE_W)
4139                         /* write-high */
4140                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4141
4142         }
4143 }
4144
4145 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4146 {
4147         if (!longmode_only)
4148                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4149                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4150         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4151                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4152 }
4153
4154 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4155 {
4156         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4157                         msr, MSR_TYPE_R);
4158         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4159                         msr, MSR_TYPE_R);
4160 }
4161
4162 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4163 {
4164         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4165                         msr, MSR_TYPE_R);
4166         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4167                         msr, MSR_TYPE_R);
4168 }
4169
4170 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4171 {
4172         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4173                         msr, MSR_TYPE_W);
4174         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4175                         msr, MSR_TYPE_W);
4176 }
4177
4178 static int vmx_vm_has_apicv(struct kvm *kvm)
4179 {
4180         return enable_apicv && irqchip_in_kernel(kvm);
4181 }
4182
4183 /*
4184  * Send interrupt to vcpu via posted interrupt way.
4185  * 1. If target vcpu is running(non-root mode), send posted interrupt
4186  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4187  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4188  * interrupt from PIR in next vmentry.
4189  */
4190 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4191 {
4192         struct vcpu_vmx *vmx = to_vmx(vcpu);
4193         int r;
4194
4195         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4196                 return;
4197
4198         r = pi_test_and_set_on(&vmx->pi_desc);
4199         kvm_make_request(KVM_REQ_EVENT, vcpu);
4200 #ifdef CONFIG_SMP
4201         if (!r && (vcpu->mode == IN_GUEST_MODE))
4202                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4203                                 POSTED_INTR_VECTOR);
4204         else
4205 #endif
4206                 kvm_vcpu_kick(vcpu);
4207 }
4208
4209 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4210 {
4211         struct vcpu_vmx *vmx = to_vmx(vcpu);
4212
4213         if (!pi_test_and_clear_on(&vmx->pi_desc))
4214                 return;
4215
4216         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4217 }
4218
4219 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4220 {
4221         return;
4222 }
4223
4224 /*
4225  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4226  * will not change in the lifetime of the guest.
4227  * Note that host-state that does change is set elsewhere. E.g., host-state
4228  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4229  */
4230 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4231 {
4232         u32 low32, high32;
4233         unsigned long tmpl;
4234         struct desc_ptr dt;
4235
4236         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4237         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4238         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4239
4240         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4241 #ifdef CONFIG_X86_64
4242         /*
4243          * Load null selectors, so we can avoid reloading them in
4244          * __vmx_load_host_state(), in case userspace uses the null selectors
4245          * too (the expected case).
4246          */
4247         vmcs_write16(HOST_DS_SELECTOR, 0);
4248         vmcs_write16(HOST_ES_SELECTOR, 0);
4249 #else
4250         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4251         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4252 #endif
4253         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4254         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4255
4256         native_store_idt(&dt);
4257         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4258         vmx->host_idt_base = dt.address;
4259
4260         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4261
4262         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4263         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4264         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4265         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4266
4267         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4268                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4269                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4270         }
4271 }
4272
4273 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4274 {
4275         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4276         if (enable_ept)
4277                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4278         if (is_guest_mode(&vmx->vcpu))
4279                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4280                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4281         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4282 }
4283
4284 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4285 {
4286         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4287
4288         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4289                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4290         return pin_based_exec_ctrl;
4291 }
4292
4293 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4294 {
4295         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4296
4297         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4298                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4299
4300         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4301                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4302 #ifdef CONFIG_X86_64
4303                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4304                                 CPU_BASED_CR8_LOAD_EXITING;
4305 #endif
4306         }
4307         if (!enable_ept)
4308                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4309                                 CPU_BASED_CR3_LOAD_EXITING  |
4310                                 CPU_BASED_INVLPG_EXITING;
4311         return exec_control;
4312 }
4313
4314 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4315 {
4316         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4317         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4318                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4319         if (vmx->vpid == 0)
4320                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4321         if (!enable_ept) {
4322                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4323                 enable_unrestricted_guest = 0;
4324                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4325                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4326         }
4327         if (!enable_unrestricted_guest)
4328                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4329         if (!ple_gap)
4330                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4331         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4332                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4333                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4334         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4335         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4336            (handle_vmptrld).
4337            We can NOT enable shadow_vmcs here because we don't have yet
4338            a current VMCS12
4339         */
4340         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4341         return exec_control;
4342 }
4343
4344 static void ept_set_mmio_spte_mask(void)
4345 {
4346         /*
4347          * EPT Misconfigurations can be generated if the value of bits 2:0
4348          * of an EPT paging-structure entry is 110b (write/execute).
4349          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4350          * spte.
4351          */
4352         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4353 }
4354
4355 /*
4356  * Sets up the vmcs for emulated real mode.
4357  */
4358 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4359 {
4360 #ifdef CONFIG_X86_64
4361         unsigned long a;
4362 #endif
4363         int i;
4364
4365         /* I/O */
4366         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4367         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4368
4369         if (enable_shadow_vmcs) {
4370                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4371                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4372         }
4373         if (cpu_has_vmx_msr_bitmap())
4374                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4375
4376         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4377
4378         /* Control */
4379         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4380
4381         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4382
4383         if (cpu_has_secondary_exec_ctrls()) {
4384                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4385                                 vmx_secondary_exec_control(vmx));
4386         }
4387
4388         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4389                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4390                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4391                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4392                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4393
4394                 vmcs_write16(GUEST_INTR_STATUS, 0);
4395
4396                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4397                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4398         }
4399
4400         if (ple_gap) {
4401                 vmcs_write32(PLE_GAP, ple_gap);
4402                 vmcs_write32(PLE_WINDOW, ple_window);
4403         }
4404
4405         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4406         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4407         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4408
4409         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4410         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4411         vmx_set_constant_host_state(vmx);
4412 #ifdef CONFIG_X86_64
4413         rdmsrl(MSR_FS_BASE, a);
4414         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4415         rdmsrl(MSR_GS_BASE, a);
4416         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4417 #else
4418         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4419         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4420 #endif
4421
4422         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4423         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4424         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4425         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4426         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4427
4428         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4429                 u32 msr_low, msr_high;
4430                 u64 host_pat;
4431                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4432                 host_pat = msr_low | ((u64) msr_high << 32);
4433                 /* Write the default value follow host pat */
4434                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4435                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4436                 vmx->vcpu.arch.pat = host_pat;
4437         }
4438
4439         for (i = 0; i < NR_VMX_MSR; ++i) {
4440                 u32 index = vmx_msr_index[i];
4441                 u32 data_low, data_high;
4442                 int j = vmx->nmsrs;
4443
4444                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4445                         continue;
4446                 if (wrmsr_safe(index, data_low, data_high) < 0)
4447                         continue;
4448                 vmx->guest_msrs[j].index = i;
4449                 vmx->guest_msrs[j].data = 0;
4450                 vmx->guest_msrs[j].mask = -1ull;
4451                 ++vmx->nmsrs;
4452         }
4453
4454
4455         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4456
4457         /* 22.2.1, 20.8.1 */
4458         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4459
4460         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4461         set_cr4_guest_host_mask(vmx);
4462
4463         return 0;
4464 }
4465
4466 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4467 {
4468         struct vcpu_vmx *vmx = to_vmx(vcpu);
4469         struct msr_data apic_base_msr;
4470
4471         vmx->rmode.vm86_active = 0;
4472
4473         vmx->soft_vnmi_blocked = 0;
4474
4475         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4476         kvm_set_cr8(&vmx->vcpu, 0);
4477         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4478         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4479                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4480         apic_base_msr.host_initiated = true;
4481         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4482
4483         vmx_segment_cache_clear(vmx);
4484
4485         seg_setup(VCPU_SREG_CS);
4486         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4487         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4488
4489         seg_setup(VCPU_SREG_DS);
4490         seg_setup(VCPU_SREG_ES);
4491         seg_setup(VCPU_SREG_FS);
4492         seg_setup(VCPU_SREG_GS);
4493         seg_setup(VCPU_SREG_SS);
4494
4495         vmcs_write16(GUEST_TR_SELECTOR, 0);
4496         vmcs_writel(GUEST_TR_BASE, 0);
4497         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4498         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4499
4500         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4501         vmcs_writel(GUEST_LDTR_BASE, 0);
4502         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4503         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4504
4505         vmcs_write32(GUEST_SYSENTER_CS, 0);
4506         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4507         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4508
4509         vmcs_writel(GUEST_RFLAGS, 0x02);
4510         kvm_rip_write(vcpu, 0xfff0);
4511
4512         vmcs_writel(GUEST_GDTR_BASE, 0);
4513         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4514
4515         vmcs_writel(GUEST_IDTR_BASE, 0);
4516         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4517
4518         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4519         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4520         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4521
4522         /* Special registers */
4523         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4524
4525         setup_msrs(vmx);
4526
4527         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4528
4529         if (cpu_has_vmx_tpr_shadow()) {
4530                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4531                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4532                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4533                                      __pa(vmx->vcpu.arch.apic->regs));
4534                 vmcs_write32(TPR_THRESHOLD, 0);
4535         }
4536
4537         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4538                 vmcs_write64(APIC_ACCESS_ADDR,
4539                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4540
4541         if (vmx_vm_has_apicv(vcpu->kvm))
4542                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4543
4544         if (vmx->vpid != 0)
4545                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4546
4547         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4548         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4549         vmx_set_cr4(&vmx->vcpu, 0);
4550         vmx_set_efer(&vmx->vcpu, 0);
4551         vmx_fpu_activate(&vmx->vcpu);
4552         update_exception_bitmap(&vmx->vcpu);
4553
4554         vpid_sync_context(vmx);
4555 }
4556
4557 /*
4558  * In nested virtualization, check if L1 asked to exit on external interrupts.
4559  * For most existing hypervisors, this will always return true.
4560  */
4561 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4562 {
4563         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4564                 PIN_BASED_EXT_INTR_MASK;
4565 }
4566
4567 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4568 {
4569         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4570                 PIN_BASED_NMI_EXITING;
4571 }
4572
4573 static void enable_irq_window(struct kvm_vcpu *vcpu)
4574 {
4575         u32 cpu_based_vm_exec_control;
4576
4577         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4578         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4579         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4580 }
4581
4582 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4583 {
4584         u32 cpu_based_vm_exec_control;
4585
4586         if (!cpu_has_virtual_nmis() ||
4587             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4588                 enable_irq_window(vcpu);
4589                 return;
4590         }
4591
4592         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4593         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4594         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4595 }
4596
4597 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4598 {
4599         struct vcpu_vmx *vmx = to_vmx(vcpu);
4600         uint32_t intr;
4601         int irq = vcpu->arch.interrupt.nr;
4602
4603         trace_kvm_inj_virq(irq);
4604
4605         ++vcpu->stat.irq_injections;
4606         if (vmx->rmode.vm86_active) {
4607                 int inc_eip = 0;
4608                 if (vcpu->arch.interrupt.soft)
4609                         inc_eip = vcpu->arch.event_exit_inst_len;
4610                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4611                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4612                 return;
4613         }
4614         intr = irq | INTR_INFO_VALID_MASK;
4615         if (vcpu->arch.interrupt.soft) {
4616                 intr |= INTR_TYPE_SOFT_INTR;
4617                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4618                              vmx->vcpu.arch.event_exit_inst_len);
4619         } else
4620                 intr |= INTR_TYPE_EXT_INTR;
4621         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4622 }
4623
4624 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4625 {
4626         struct vcpu_vmx *vmx = to_vmx(vcpu);
4627
4628         if (is_guest_mode(vcpu))
4629                 return;
4630
4631         if (!cpu_has_virtual_nmis()) {
4632                 /*
4633                  * Tracking the NMI-blocked state in software is built upon
4634                  * finding the next open IRQ window. This, in turn, depends on
4635                  * well-behaving guests: They have to keep IRQs disabled at
4636                  * least as long as the NMI handler runs. Otherwise we may
4637                  * cause NMI nesting, maybe breaking the guest. But as this is
4638                  * highly unlikely, we can live with the residual risk.
4639                  */
4640                 vmx->soft_vnmi_blocked = 1;
4641                 vmx->vnmi_blocked_time = 0;
4642         }
4643
4644         ++vcpu->stat.nmi_injections;
4645         vmx->nmi_known_unmasked = false;
4646         if (vmx->rmode.vm86_active) {
4647                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4648                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4649                 return;
4650         }
4651         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4652                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4653 }
4654
4655 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4656 {
4657         if (!cpu_has_virtual_nmis())
4658                 return to_vmx(vcpu)->soft_vnmi_blocked;
4659         if (to_vmx(vcpu)->nmi_known_unmasked)
4660                 return false;
4661         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4662 }
4663
4664 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4665 {
4666         struct vcpu_vmx *vmx = to_vmx(vcpu);
4667
4668         if (!cpu_has_virtual_nmis()) {
4669                 if (vmx->soft_vnmi_blocked != masked) {
4670                         vmx->soft_vnmi_blocked = masked;
4671                         vmx->vnmi_blocked_time = 0;
4672                 }
4673         } else {
4674                 vmx->nmi_known_unmasked = !masked;
4675                 if (masked)
4676                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4677                                       GUEST_INTR_STATE_NMI);
4678                 else
4679                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4680                                         GUEST_INTR_STATE_NMI);
4681         }
4682 }
4683
4684 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4685 {
4686         if (to_vmx(vcpu)->nested.nested_run_pending)
4687                 return 0;
4688
4689         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4690                 return 0;
4691
4692         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4693                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4694                    | GUEST_INTR_STATE_NMI));
4695 }
4696
4697 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4698 {
4699         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4700                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4701                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4702                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4703 }
4704
4705 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4706 {
4707         int ret;
4708         struct kvm_userspace_memory_region tss_mem = {
4709                 .slot = TSS_PRIVATE_MEMSLOT,
4710                 .guest_phys_addr = addr,
4711                 .memory_size = PAGE_SIZE * 3,
4712                 .flags = 0,
4713         };
4714
4715         ret = kvm_set_memory_region(kvm, &tss_mem);
4716         if (ret)
4717                 return ret;
4718         kvm->arch.tss_addr = addr;
4719         if (!init_rmode_tss(kvm))
4720                 return  -ENOMEM;
4721
4722         return 0;
4723 }
4724
4725 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4726 {
4727         switch (vec) {
4728         case BP_VECTOR:
4729                 /*
4730                  * Update instruction length as we may reinject the exception
4731                  * from user space while in guest debugging mode.
4732                  */
4733                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4734                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4735                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4736                         return false;
4737                 /* fall through */
4738         case DB_VECTOR:
4739                 if (vcpu->guest_debug &
4740                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4741                         return false;
4742                 /* fall through */
4743         case DE_VECTOR:
4744         case OF_VECTOR:
4745         case BR_VECTOR:
4746         case UD_VECTOR:
4747         case DF_VECTOR:
4748         case SS_VECTOR:
4749         case GP_VECTOR:
4750         case MF_VECTOR:
4751                 return true;
4752         break;
4753         }
4754         return false;
4755 }
4756
4757 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4758                                   int vec, u32 err_code)
4759 {
4760         /*
4761          * Instruction with address size override prefix opcode 0x67
4762          * Cause the #SS fault with 0 error code in VM86 mode.
4763          */
4764         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4765                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4766                         if (vcpu->arch.halt_request) {
4767                                 vcpu->arch.halt_request = 0;
4768                                 return kvm_emulate_halt(vcpu);
4769                         }
4770                         return 1;
4771                 }
4772                 return 0;
4773         }
4774
4775         /*
4776          * Forward all other exceptions that are valid in real mode.
4777          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4778          *        the required debugging infrastructure rework.
4779          */
4780         kvm_queue_exception(vcpu, vec);
4781         return 1;
4782 }
4783
4784 /*
4785  * Trigger machine check on the host. We assume all the MSRs are already set up
4786  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4787  * We pass a fake environment to the machine check handler because we want
4788  * the guest to be always treated like user space, no matter what context
4789  * it used internally.
4790  */
4791 static void kvm_machine_check(void)
4792 {
4793 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4794         struct pt_regs regs = {
4795                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4796                 .flags = X86_EFLAGS_IF,
4797         };
4798
4799         do_machine_check(&regs, 0);
4800 #endif
4801 }
4802
4803 static int handle_machine_check(struct kvm_vcpu *vcpu)
4804 {
4805         /* already handled by vcpu_run */
4806         return 1;
4807 }
4808
4809 static int handle_exception(struct kvm_vcpu *vcpu)
4810 {
4811         struct vcpu_vmx *vmx = to_vmx(vcpu);
4812         struct kvm_run *kvm_run = vcpu->run;
4813         u32 intr_info, ex_no, error_code;
4814         unsigned long cr2, rip, dr6;
4815         u32 vect_info;
4816         enum emulation_result er;
4817
4818         vect_info = vmx->idt_vectoring_info;
4819         intr_info = vmx->exit_intr_info;
4820
4821         if (is_machine_check(intr_info))
4822                 return handle_machine_check(vcpu);
4823
4824         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4825                 return 1;  /* already handled by vmx_vcpu_run() */
4826
4827         if (is_no_device(intr_info)) {
4828                 vmx_fpu_activate(vcpu);
4829                 return 1;
4830         }
4831
4832         if (is_invalid_opcode(intr_info)) {
4833                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4834                 if (er != EMULATE_DONE)
4835                         kvm_queue_exception(vcpu, UD_VECTOR);
4836                 return 1;
4837         }
4838
4839         error_code = 0;
4840         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4841                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4842
4843         /*
4844          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4845          * MMIO, it is better to report an internal error.
4846          * See the comments in vmx_handle_exit.
4847          */
4848         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4849             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4850                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4851                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4852                 vcpu->run->internal.ndata = 2;
4853                 vcpu->run->internal.data[0] = vect_info;
4854                 vcpu->run->internal.data[1] = intr_info;
4855                 return 0;
4856         }
4857
4858         if (is_page_fault(intr_info)) {
4859                 /* EPT won't cause page fault directly */
4860                 BUG_ON(enable_ept);
4861                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4862                 trace_kvm_page_fault(cr2, error_code);
4863
4864                 if (kvm_event_needs_reinjection(vcpu))
4865                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4866                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4867         }
4868
4869         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4870
4871         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4872                 return handle_rmode_exception(vcpu, ex_no, error_code);
4873
4874         switch (ex_no) {
4875         case DB_VECTOR:
4876                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4877                 if (!(vcpu->guest_debug &
4878                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4879                         vcpu->arch.dr6 &= ~15;
4880                         vcpu->arch.dr6 |= dr6;
4881                         kvm_queue_exception(vcpu, DB_VECTOR);
4882                         return 1;
4883                 }
4884                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4885                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4886                 /* fall through */
4887         case BP_VECTOR:
4888                 /*
4889                  * Update instruction length as we may reinject #BP from
4890                  * user space while in guest debugging mode. Reading it for
4891                  * #DB as well causes no harm, it is not used in that case.
4892                  */
4893                 vmx->vcpu.arch.event_exit_inst_len =
4894                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4895                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4896                 rip = kvm_rip_read(vcpu);
4897                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4898                 kvm_run->debug.arch.exception = ex_no;
4899                 break;
4900         default:
4901                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4902                 kvm_run->ex.exception = ex_no;
4903                 kvm_run->ex.error_code = error_code;
4904                 break;
4905         }
4906         return 0;
4907 }
4908
4909 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4910 {
4911         ++vcpu->stat.irq_exits;
4912         return 1;
4913 }
4914
4915 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4916 {
4917         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4918         return 0;
4919 }
4920
4921 static int handle_io(struct kvm_vcpu *vcpu)
4922 {
4923         unsigned long exit_qualification;
4924         int size, in, string;
4925         unsigned port;
4926
4927         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4928         string = (exit_qualification & 16) != 0;
4929         in = (exit_qualification & 8) != 0;
4930
4931         ++vcpu->stat.io_exits;
4932
4933         if (string || in)
4934                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4935
4936         port = exit_qualification >> 16;
4937         size = (exit_qualification & 7) + 1;
4938         skip_emulated_instruction(vcpu);
4939
4940         return kvm_fast_pio_out(vcpu, size, port);
4941 }
4942
4943 static void
4944 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4945 {
4946         /*
4947          * Patch in the VMCALL instruction:
4948          */
4949         hypercall[0] = 0x0f;
4950         hypercall[1] = 0x01;
4951         hypercall[2] = 0xc1;
4952 }
4953
4954 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4955 {
4956         unsigned long always_on = VMXON_CR0_ALWAYSON;
4957
4958         if (nested_vmx_secondary_ctls_high &
4959                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4960             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4961                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4962         return (val & always_on) == always_on;
4963 }
4964
4965 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4966 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4967 {
4968         if (is_guest_mode(vcpu)) {
4969                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4970                 unsigned long orig_val = val;
4971
4972                 /*
4973                  * We get here when L2 changed cr0 in a way that did not change
4974                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4975                  * but did change L0 shadowed bits. So we first calculate the
4976                  * effective cr0 value that L1 would like to write into the
4977                  * hardware. It consists of the L2-owned bits from the new
4978                  * value combined with the L1-owned bits from L1's guest_cr0.
4979                  */
4980                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4981                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4982
4983                 if (!nested_cr0_valid(vmcs12, val))
4984                         return 1;
4985
4986                 if (kvm_set_cr0(vcpu, val))
4987                         return 1;
4988                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4989                 return 0;
4990         } else {
4991                 if (to_vmx(vcpu)->nested.vmxon &&
4992                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4993                         return 1;
4994                 return kvm_set_cr0(vcpu, val);
4995         }
4996 }
4997
4998 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4999 {
5000         if (is_guest_mode(vcpu)) {
5001                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5002                 unsigned long orig_val = val;
5003
5004                 /* analogously to handle_set_cr0 */
5005                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5006                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5007                 if (kvm_set_cr4(vcpu, val))
5008                         return 1;
5009                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5010                 return 0;
5011         } else
5012                 return kvm_set_cr4(vcpu, val);
5013 }
5014
5015 /* called to set cr0 as approriate for clts instruction exit. */
5016 static void handle_clts(struct kvm_vcpu *vcpu)
5017 {
5018         if (is_guest_mode(vcpu)) {
5019                 /*
5020                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5021                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5022                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5023                  */
5024                 vmcs_writel(CR0_READ_SHADOW,
5025                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5026                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5027         } else
5028                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5029 }
5030
5031 static int handle_cr(struct kvm_vcpu *vcpu)
5032 {
5033         unsigned long exit_qualification, val;
5034         int cr;
5035         int reg;
5036         int err;
5037
5038         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5039         cr = exit_qualification & 15;
5040         reg = (exit_qualification >> 8) & 15;
5041         switch ((exit_qualification >> 4) & 3) {
5042         case 0: /* mov to cr */
5043                 val = kvm_register_read(vcpu, reg);
5044                 trace_kvm_cr_write(cr, val);
5045                 switch (cr) {
5046                 case 0:
5047                         err = handle_set_cr0(vcpu, val);
5048                         kvm_complete_insn_gp(vcpu, err);
5049                         return 1;
5050                 case 3:
5051                         err = kvm_set_cr3(vcpu, val);
5052                         kvm_complete_insn_gp(vcpu, err);
5053                         return 1;
5054                 case 4:
5055                         err = handle_set_cr4(vcpu, val);
5056                         kvm_complete_insn_gp(vcpu, err);
5057                         return 1;
5058                 case 8: {
5059                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5060                                 u8 cr8 = kvm_register_read(vcpu, reg);
5061                                 err = kvm_set_cr8(vcpu, cr8);
5062                                 kvm_complete_insn_gp(vcpu, err);
5063                                 if (irqchip_in_kernel(vcpu->kvm))
5064                                         return 1;
5065                                 if (cr8_prev <= cr8)
5066                                         return 1;
5067                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5068                                 return 0;
5069                         }
5070                 }
5071                 break;
5072         case 2: /* clts */
5073                 handle_clts(vcpu);
5074                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5075                 skip_emulated_instruction(vcpu);
5076                 vmx_fpu_activate(vcpu);
5077                 return 1;
5078         case 1: /*mov from cr*/
5079                 switch (cr) {
5080                 case 3:
5081                         val = kvm_read_cr3(vcpu);
5082                         kvm_register_write(vcpu, reg, val);
5083                         trace_kvm_cr_read(cr, val);
5084                         skip_emulated_instruction(vcpu);
5085                         return 1;
5086                 case 8:
5087                         val = kvm_get_cr8(vcpu);
5088                         kvm_register_write(vcpu, reg, val);
5089                         trace_kvm_cr_read(cr, val);
5090                         skip_emulated_instruction(vcpu);
5091                         return 1;
5092                 }
5093                 break;
5094         case 3: /* lmsw */
5095                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5096                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5097                 kvm_lmsw(vcpu, val);
5098
5099                 skip_emulated_instruction(vcpu);
5100                 return 1;
5101         default:
5102                 break;
5103         }
5104         vcpu->run->exit_reason = 0;
5105         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5106                (int)(exit_qualification >> 4) & 3, cr);
5107         return 0;
5108 }
5109
5110 static int handle_dr(struct kvm_vcpu *vcpu)
5111 {
5112         unsigned long exit_qualification;
5113         int dr, reg;
5114
5115         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5116         if (!kvm_require_cpl(vcpu, 0))
5117                 return 1;
5118         dr = vmcs_readl(GUEST_DR7);
5119         if (dr & DR7_GD) {
5120                 /*
5121                  * As the vm-exit takes precedence over the debug trap, we
5122                  * need to emulate the latter, either for the host or the
5123                  * guest debugging itself.
5124                  */
5125                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5126                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5127                         vcpu->run->debug.arch.dr7 = dr;
5128                         vcpu->run->debug.arch.pc =
5129                                 vmcs_readl(GUEST_CS_BASE) +
5130                                 vmcs_readl(GUEST_RIP);
5131                         vcpu->run->debug.arch.exception = DB_VECTOR;
5132                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5133                         return 0;
5134                 } else {
5135                         vcpu->arch.dr7 &= ~DR7_GD;
5136                         vcpu->arch.dr6 |= DR6_BD;
5137                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5138                         kvm_queue_exception(vcpu, DB_VECTOR);
5139                         return 1;
5140                 }
5141         }
5142
5143         if (vcpu->guest_debug == 0) {
5144                 u32 cpu_based_vm_exec_control;
5145
5146                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5147                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5148                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5149
5150                 /*
5151                  * No more DR vmexits; force a reload of the debug registers
5152                  * and reenter on this instruction.  The next vmexit will
5153                  * retrieve the full state of the debug registers.
5154                  */
5155                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5156                 return 1;
5157         }
5158
5159         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5160         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5161         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5162         if (exit_qualification & TYPE_MOV_FROM_DR) {
5163                 unsigned long val;
5164
5165                 if (kvm_get_dr(vcpu, dr, &val))
5166                         return 1;
5167                 kvm_register_write(vcpu, reg, val);
5168         } else
5169                 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5170                         return 1;
5171
5172         skip_emulated_instruction(vcpu);
5173         return 1;
5174 }
5175
5176 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5177 {
5178         return vcpu->arch.dr6;
5179 }
5180
5181 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5182 {
5183 }
5184
5185 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5186 {
5187         u32 cpu_based_vm_exec_control;
5188
5189         get_debugreg(vcpu->arch.db[0], 0);
5190         get_debugreg(vcpu->arch.db[1], 1);
5191         get_debugreg(vcpu->arch.db[2], 2);
5192         get_debugreg(vcpu->arch.db[3], 3);
5193         get_debugreg(vcpu->arch.dr6, 6);
5194         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5195
5196         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5197
5198         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5199         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5200         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5201 }
5202
5203 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5204 {
5205         vmcs_writel(GUEST_DR7, val);
5206 }
5207
5208 static int handle_cpuid(struct kvm_vcpu *vcpu)
5209 {
5210         kvm_emulate_cpuid(vcpu);
5211         return 1;
5212 }
5213
5214 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5215 {
5216         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5217         u64 data;
5218
5219         if (vmx_get_msr(vcpu, ecx, &data)) {
5220                 trace_kvm_msr_read_ex(ecx);
5221                 kvm_inject_gp(vcpu, 0);
5222                 return 1;
5223         }
5224
5225         trace_kvm_msr_read(ecx, data);
5226
5227         /* FIXME: handling of bits 32:63 of rax, rdx */
5228         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5229         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5230         skip_emulated_instruction(vcpu);
5231         return 1;
5232 }
5233
5234 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5235 {
5236         struct msr_data msr;
5237         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5238         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5239                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5240
5241         msr.data = data;
5242         msr.index = ecx;
5243         msr.host_initiated = false;
5244         if (vmx_set_msr(vcpu, &msr) != 0) {
5245                 trace_kvm_msr_write_ex(ecx, data);
5246                 kvm_inject_gp(vcpu, 0);
5247                 return 1;
5248         }
5249
5250         trace_kvm_msr_write(ecx, data);
5251         skip_emulated_instruction(vcpu);
5252         return 1;
5253 }
5254
5255 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5256 {
5257         kvm_make_request(KVM_REQ_EVENT, vcpu);
5258         return 1;
5259 }
5260
5261 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5262 {
5263         u32 cpu_based_vm_exec_control;
5264
5265         /* clear pending irq */
5266         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5267         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5268         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5269
5270         kvm_make_request(KVM_REQ_EVENT, vcpu);
5271
5272         ++vcpu->stat.irq_window_exits;
5273
5274         /*
5275          * If the user space waits to inject interrupts, exit as soon as
5276          * possible
5277          */
5278         if (!irqchip_in_kernel(vcpu->kvm) &&
5279             vcpu->run->request_interrupt_window &&
5280             !kvm_cpu_has_interrupt(vcpu)) {
5281                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5282                 return 0;
5283         }
5284         return 1;
5285 }
5286
5287 static int handle_halt(struct kvm_vcpu *vcpu)
5288 {
5289         skip_emulated_instruction(vcpu);
5290         return kvm_emulate_halt(vcpu);
5291 }
5292
5293 static int handle_vmcall(struct kvm_vcpu *vcpu)
5294 {
5295         skip_emulated_instruction(vcpu);
5296         kvm_emulate_hypercall(vcpu);
5297         return 1;
5298 }
5299
5300 static int handle_invd(struct kvm_vcpu *vcpu)
5301 {
5302         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5303 }
5304
5305 static int handle_invlpg(struct kvm_vcpu *vcpu)
5306 {
5307         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5308
5309         kvm_mmu_invlpg(vcpu, exit_qualification);
5310         skip_emulated_instruction(vcpu);
5311         return 1;
5312 }
5313
5314 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5315 {
5316         int err;
5317
5318         err = kvm_rdpmc(vcpu);
5319         kvm_complete_insn_gp(vcpu, err);
5320
5321         return 1;
5322 }
5323
5324 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5325 {
5326         skip_emulated_instruction(vcpu);
5327         kvm_emulate_wbinvd(vcpu);
5328         return 1;
5329 }
5330
5331 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5332 {
5333         u64 new_bv = kvm_read_edx_eax(vcpu);
5334         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5335
5336         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5337                 skip_emulated_instruction(vcpu);
5338         return 1;
5339 }
5340
5341 static int handle_apic_access(struct kvm_vcpu *vcpu)
5342 {
5343         if (likely(fasteoi)) {
5344                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5345                 int access_type, offset;
5346
5347                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5348                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5349                 /*
5350                  * Sane guest uses MOV to write EOI, with written value
5351                  * not cared. So make a short-circuit here by avoiding
5352                  * heavy instruction emulation.
5353                  */
5354                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5355                     (offset == APIC_EOI)) {
5356                         kvm_lapic_set_eoi(vcpu);
5357                         skip_emulated_instruction(vcpu);
5358                         return 1;
5359                 }
5360         }
5361         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5362 }
5363
5364 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5365 {
5366         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5367         int vector = exit_qualification & 0xff;
5368
5369         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5370         kvm_apic_set_eoi_accelerated(vcpu, vector);
5371         return 1;
5372 }
5373
5374 static int handle_apic_write(struct kvm_vcpu *vcpu)
5375 {
5376         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5377         u32 offset = exit_qualification & 0xfff;
5378
5379         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5380         kvm_apic_write_nodecode(vcpu, offset);
5381         return 1;
5382 }
5383
5384 static int handle_task_switch(struct kvm_vcpu *vcpu)
5385 {
5386         struct vcpu_vmx *vmx = to_vmx(vcpu);
5387         unsigned long exit_qualification;
5388         bool has_error_code = false;
5389         u32 error_code = 0;
5390         u16 tss_selector;
5391         int reason, type, idt_v, idt_index;
5392
5393         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5394         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5395         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5396
5397         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5398
5399         reason = (u32)exit_qualification >> 30;
5400         if (reason == TASK_SWITCH_GATE && idt_v) {
5401                 switch (type) {
5402                 case INTR_TYPE_NMI_INTR:
5403                         vcpu->arch.nmi_injected = false;
5404                         vmx_set_nmi_mask(vcpu, true);
5405                         break;
5406                 case INTR_TYPE_EXT_INTR:
5407                 case INTR_TYPE_SOFT_INTR:
5408                         kvm_clear_interrupt_queue(vcpu);
5409                         break;
5410                 case INTR_TYPE_HARD_EXCEPTION:
5411                         if (vmx->idt_vectoring_info &
5412                             VECTORING_INFO_DELIVER_CODE_MASK) {
5413                                 has_error_code = true;
5414                                 error_code =
5415                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5416                         }
5417                         /* fall through */
5418                 case INTR_TYPE_SOFT_EXCEPTION:
5419                         kvm_clear_exception_queue(vcpu);
5420                         break;
5421                 default:
5422                         break;
5423                 }
5424         }
5425         tss_selector = exit_qualification;
5426
5427         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5428                        type != INTR_TYPE_EXT_INTR &&
5429                        type != INTR_TYPE_NMI_INTR))
5430                 skip_emulated_instruction(vcpu);
5431
5432         if (kvm_task_switch(vcpu, tss_selector,
5433                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5434                             has_error_code, error_code) == EMULATE_FAIL) {
5435                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5436                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5437                 vcpu->run->internal.ndata = 0;
5438                 return 0;
5439         }
5440
5441         /* clear all local breakpoint enable flags */
5442         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5443
5444         /*
5445          * TODO: What about debug traps on tss switch?
5446          *       Are we supposed to inject them and update dr6?
5447          */
5448
5449         return 1;
5450 }
5451
5452 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5453 {
5454         unsigned long exit_qualification;
5455         gpa_t gpa;
5456         u32 error_code;
5457         int gla_validity;
5458
5459         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5460
5461         gla_validity = (exit_qualification >> 7) & 0x3;
5462         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5463                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5464                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5465                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5466                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5467                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5468                         (long unsigned int)exit_qualification);
5469                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5470                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5471                 return 0;
5472         }
5473
5474         /*
5475          * EPT violation happened while executing iret from NMI,
5476          * "blocked by NMI" bit has to be set before next VM entry.
5477          * There are errata that may cause this bit to not be set:
5478          * AAK134, BY25.
5479          */
5480         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5481                         cpu_has_virtual_nmis() &&
5482                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5483                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5484
5485         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5486         trace_kvm_page_fault(gpa, exit_qualification);
5487
5488         /* It is a write fault? */
5489         error_code = exit_qualification & (1U << 1);
5490         /* It is a fetch fault? */
5491         error_code |= (exit_qualification & (1U << 2)) << 2;
5492         /* ept page table is present? */
5493         error_code |= (exit_qualification >> 3) & 0x1;
5494
5495         vcpu->arch.exit_qualification = exit_qualification;
5496
5497         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5498 }
5499
5500 static u64 ept_rsvd_mask(u64 spte, int level)
5501 {
5502         int i;
5503         u64 mask = 0;
5504
5505         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5506                 mask |= (1ULL << i);
5507
5508         if (level > 2)
5509                 /* bits 7:3 reserved */
5510                 mask |= 0xf8;
5511         else if (level == 2) {
5512                 if (spte & (1ULL << 7))
5513                         /* 2MB ref, bits 20:12 reserved */
5514                         mask |= 0x1ff000;
5515                 else
5516                         /* bits 6:3 reserved */
5517                         mask |= 0x78;
5518         }
5519
5520         return mask;
5521 }
5522
5523 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5524                                        int level)
5525 {
5526         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5527
5528         /* 010b (write-only) */
5529         WARN_ON((spte & 0x7) == 0x2);
5530
5531         /* 110b (write/execute) */
5532         WARN_ON((spte & 0x7) == 0x6);
5533
5534         /* 100b (execute-only) and value not supported by logical processor */
5535         if (!cpu_has_vmx_ept_execute_only())
5536                 WARN_ON((spte & 0x7) == 0x4);
5537
5538         /* not 000b */
5539         if ((spte & 0x7)) {
5540                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5541
5542                 if (rsvd_bits != 0) {
5543                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5544                                          __func__, rsvd_bits);
5545                         WARN_ON(1);
5546                 }
5547
5548                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5549                         u64 ept_mem_type = (spte & 0x38) >> 3;
5550
5551                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5552                             ept_mem_type == 7) {
5553                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5554                                                 __func__, ept_mem_type);
5555                                 WARN_ON(1);
5556                         }
5557                 }
5558         }
5559 }
5560
5561 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5562 {
5563         u64 sptes[4];
5564         int nr_sptes, i, ret;
5565         gpa_t gpa;
5566
5567         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5568
5569         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5570         if (likely(ret == RET_MMIO_PF_EMULATE))
5571                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5572                                               EMULATE_DONE;
5573
5574         if (unlikely(ret == RET_MMIO_PF_INVALID))
5575                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5576
5577         if (unlikely(ret == RET_MMIO_PF_RETRY))
5578                 return 1;
5579
5580         /* It is the real ept misconfig */
5581         printk(KERN_ERR "EPT: Misconfiguration.\n");
5582         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5583
5584         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5585
5586         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5587                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5588
5589         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5590         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5591
5592         return 0;
5593 }
5594
5595 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5596 {
5597         u32 cpu_based_vm_exec_control;
5598
5599         /* clear pending NMI */
5600         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5601         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5602         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5603         ++vcpu->stat.nmi_window_exits;
5604         kvm_make_request(KVM_REQ_EVENT, vcpu);
5605
5606         return 1;
5607 }
5608
5609 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5610 {
5611         struct vcpu_vmx *vmx = to_vmx(vcpu);
5612         enum emulation_result err = EMULATE_DONE;
5613         int ret = 1;
5614         u32 cpu_exec_ctrl;
5615         bool intr_window_requested;
5616         unsigned count = 130;
5617
5618         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5619         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5620
5621         while (!guest_state_valid(vcpu) && count-- != 0) {
5622                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5623                         return handle_interrupt_window(&vmx->vcpu);
5624
5625                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5626                         return 1;
5627
5628                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5629
5630                 if (err == EMULATE_USER_EXIT) {
5631                         ++vcpu->stat.mmio_exits;
5632                         ret = 0;
5633                         goto out;
5634                 }
5635
5636                 if (err != EMULATE_DONE) {
5637                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5638                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5639                         vcpu->run->internal.ndata = 0;
5640                         return 0;
5641                 }
5642
5643                 if (vcpu->arch.halt_request) {
5644                         vcpu->arch.halt_request = 0;
5645                         ret = kvm_emulate_halt(vcpu);
5646                         goto out;
5647                 }
5648
5649                 if (signal_pending(current))
5650                         goto out;
5651                 if (need_resched())
5652                         schedule();
5653         }
5654
5655         vmx->emulation_required = emulation_required(vcpu);
5656 out:
5657         return ret;
5658 }
5659
5660 /*
5661  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5662  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5663  */
5664 static int handle_pause(struct kvm_vcpu *vcpu)
5665 {
5666         skip_emulated_instruction(vcpu);
5667         kvm_vcpu_on_spin(vcpu);
5668
5669         return 1;
5670 }
5671
5672 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5673 {
5674         kvm_queue_exception(vcpu, UD_VECTOR);
5675         return 1;
5676 }
5677
5678 /*
5679  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5680  * We could reuse a single VMCS for all the L2 guests, but we also want the
5681  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5682  * allows keeping them loaded on the processor, and in the future will allow
5683  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5684  * every entry if they never change.
5685  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5686  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5687  *
5688  * The following functions allocate and free a vmcs02 in this pool.
5689  */
5690
5691 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5692 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5693 {
5694         struct vmcs02_list *item;
5695         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5696                 if (item->vmptr == vmx->nested.current_vmptr) {
5697                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5698                         return &item->vmcs02;
5699                 }
5700
5701         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5702                 /* Recycle the least recently used VMCS. */
5703                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5704                         struct vmcs02_list, list);
5705                 item->vmptr = vmx->nested.current_vmptr;
5706                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5707                 return &item->vmcs02;
5708         }
5709
5710         /* Create a new VMCS */
5711         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5712         if (!item)
5713                 return NULL;
5714         item->vmcs02.vmcs = alloc_vmcs();
5715         if (!item->vmcs02.vmcs) {
5716                 kfree(item);
5717                 return NULL;
5718         }
5719         loaded_vmcs_init(&item->vmcs02);
5720         item->vmptr = vmx->nested.current_vmptr;
5721         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5722         vmx->nested.vmcs02_num++;
5723         return &item->vmcs02;
5724 }
5725
5726 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5727 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5728 {
5729         struct vmcs02_list *item;
5730         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5731                 if (item->vmptr == vmptr) {
5732                         free_loaded_vmcs(&item->vmcs02);
5733                         list_del(&item->list);
5734                         kfree(item);
5735                         vmx->nested.vmcs02_num--;
5736                         return;
5737                 }
5738 }
5739
5740 /*
5741  * Free all VMCSs saved for this vcpu, except the one pointed by
5742  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5743  * currently used, if running L2), and vmcs01 when running L2.
5744  */
5745 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5746 {
5747         struct vmcs02_list *item, *n;
5748         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5749                 if (vmx->loaded_vmcs != &item->vmcs02)
5750                         free_loaded_vmcs(&item->vmcs02);
5751                 list_del(&item->list);
5752                 kfree(item);
5753         }
5754         vmx->nested.vmcs02_num = 0;
5755
5756         if (vmx->loaded_vmcs != &vmx->vmcs01)
5757                 free_loaded_vmcs(&vmx->vmcs01);
5758 }
5759
5760 /*
5761  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5762  * set the success or error code of an emulated VMX instruction, as specified
5763  * by Vol 2B, VMX Instruction Reference, "Conventions".
5764  */
5765 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5766 {
5767         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5768                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5769                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5770 }
5771
5772 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5773 {
5774         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5775                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5776                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5777                         | X86_EFLAGS_CF);
5778 }
5779
5780 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5781                                         u32 vm_instruction_error)
5782 {
5783         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5784                 /*
5785                  * failValid writes the error number to the current VMCS, which
5786                  * can't be done there isn't a current VMCS.
5787                  */
5788                 nested_vmx_failInvalid(vcpu);
5789                 return;
5790         }
5791         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5792                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5793                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5794                         | X86_EFLAGS_ZF);
5795         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5796         /*
5797          * We don't need to force a shadow sync because
5798          * VM_INSTRUCTION_ERROR is not shadowed
5799          */
5800 }
5801
5802 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5803 {
5804         struct vcpu_vmx *vmx =
5805                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5806
5807         vmx->nested.preemption_timer_expired = true;
5808         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5809         kvm_vcpu_kick(&vmx->vcpu);
5810
5811         return HRTIMER_NORESTART;
5812 }
5813
5814 /*
5815  * Emulate the VMXON instruction.
5816  * Currently, we just remember that VMX is active, and do not save or even
5817  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5818  * do not currently need to store anything in that guest-allocated memory
5819  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5820  * argument is different from the VMXON pointer (which the spec says they do).
5821  */
5822 static int handle_vmon(struct kvm_vcpu *vcpu)
5823 {
5824         struct kvm_segment cs;
5825         struct vcpu_vmx *vmx = to_vmx(vcpu);
5826         struct vmcs *shadow_vmcs;
5827         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5828                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5829
5830         /* The Intel VMX Instruction Reference lists a bunch of bits that
5831          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5832          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5833          * Otherwise, we should fail with #UD. We test these now:
5834          */
5835         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5836             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5837             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5838                 kvm_queue_exception(vcpu, UD_VECTOR);
5839                 return 1;
5840         }
5841
5842         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5843         if (is_long_mode(vcpu) && !cs.l) {
5844                 kvm_queue_exception(vcpu, UD_VECTOR);
5845                 return 1;
5846         }
5847
5848         if (vmx_get_cpl(vcpu)) {
5849                 kvm_inject_gp(vcpu, 0);
5850                 return 1;
5851         }
5852         if (vmx->nested.vmxon) {
5853                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5854                 skip_emulated_instruction(vcpu);
5855                 return 1;
5856         }
5857
5858         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5859                         != VMXON_NEEDED_FEATURES) {
5860                 kvm_inject_gp(vcpu, 0);
5861                 return 1;
5862         }
5863
5864         if (enable_shadow_vmcs) {
5865                 shadow_vmcs = alloc_vmcs();
5866                 if (!shadow_vmcs)
5867                         return -ENOMEM;
5868                 /* mark vmcs as shadow */
5869                 shadow_vmcs->revision_id |= (1u << 31);
5870                 /* init shadow vmcs */
5871                 vmcs_clear(shadow_vmcs);
5872                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5873         }
5874
5875         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5876         vmx->nested.vmcs02_num = 0;
5877
5878         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5879                      HRTIMER_MODE_REL);
5880         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5881
5882         vmx->nested.vmxon = true;
5883
5884         skip_emulated_instruction(vcpu);
5885         nested_vmx_succeed(vcpu);
5886         return 1;
5887 }
5888
5889 /*
5890  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5891  * for running VMX instructions (except VMXON, whose prerequisites are
5892  * slightly different). It also specifies what exception to inject otherwise.
5893  */
5894 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5895 {
5896         struct kvm_segment cs;
5897         struct vcpu_vmx *vmx = to_vmx(vcpu);
5898
5899         if (!vmx->nested.vmxon) {
5900                 kvm_queue_exception(vcpu, UD_VECTOR);
5901                 return 0;
5902         }
5903
5904         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5905         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5906             (is_long_mode(vcpu) && !cs.l)) {
5907                 kvm_queue_exception(vcpu, UD_VECTOR);
5908                 return 0;
5909         }
5910
5911         if (vmx_get_cpl(vcpu)) {
5912                 kvm_inject_gp(vcpu, 0);
5913                 return 0;
5914         }
5915
5916         return 1;
5917 }
5918
5919 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5920 {
5921         u32 exec_control;
5922         if (enable_shadow_vmcs) {
5923                 if (vmx->nested.current_vmcs12 != NULL) {
5924                         /* copy to memory all shadowed fields in case
5925                            they were modified */
5926                         copy_shadow_to_vmcs12(vmx);
5927                         vmx->nested.sync_shadow_vmcs = false;
5928                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5929                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5930                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5931                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5932                 }
5933         }
5934         kunmap(vmx->nested.current_vmcs12_page);
5935         nested_release_page(vmx->nested.current_vmcs12_page);
5936 }
5937
5938 /*
5939  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5940  * just stops using VMX.
5941  */
5942 static void free_nested(struct vcpu_vmx *vmx)
5943 {
5944         if (!vmx->nested.vmxon)
5945                 return;
5946         vmx->nested.vmxon = false;
5947         if (vmx->nested.current_vmptr != -1ull) {
5948                 nested_release_vmcs12(vmx);
5949                 vmx->nested.current_vmptr = -1ull;
5950                 vmx->nested.current_vmcs12 = NULL;
5951         }
5952         if (enable_shadow_vmcs)
5953                 free_vmcs(vmx->nested.current_shadow_vmcs);
5954         /* Unpin physical memory we referred to in current vmcs02 */
5955         if (vmx->nested.apic_access_page) {
5956                 nested_release_page(vmx->nested.apic_access_page);
5957                 vmx->nested.apic_access_page = 0;
5958         }
5959
5960         nested_free_all_saved_vmcss(vmx);
5961 }
5962
5963 /* Emulate the VMXOFF instruction */
5964 static int handle_vmoff(struct kvm_vcpu *vcpu)
5965 {
5966         if (!nested_vmx_check_permission(vcpu))
5967                 return 1;
5968         free_nested(to_vmx(vcpu));
5969         skip_emulated_instruction(vcpu);
5970         nested_vmx_succeed(vcpu);
5971         return 1;
5972 }
5973
5974 /*
5975  * Decode the memory-address operand of a vmx instruction, as recorded on an
5976  * exit caused by such an instruction (run by a guest hypervisor).
5977  * On success, returns 0. When the operand is invalid, returns 1 and throws
5978  * #UD or #GP.
5979  */
5980 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5981                                  unsigned long exit_qualification,
5982                                  u32 vmx_instruction_info, gva_t *ret)
5983 {
5984         /*
5985          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5986          * Execution", on an exit, vmx_instruction_info holds most of the
5987          * addressing components of the operand. Only the displacement part
5988          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5989          * For how an actual address is calculated from all these components,
5990          * refer to Vol. 1, "Operand Addressing".
5991          */
5992         int  scaling = vmx_instruction_info & 3;
5993         int  addr_size = (vmx_instruction_info >> 7) & 7;
5994         bool is_reg = vmx_instruction_info & (1u << 10);
5995         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5996         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5997         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5998         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5999         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6000
6001         if (is_reg) {
6002                 kvm_queue_exception(vcpu, UD_VECTOR);
6003                 return 1;
6004         }
6005
6006         /* Addr = segment_base + offset */
6007         /* offset = base + [index * scale] + displacement */
6008         *ret = vmx_get_segment_base(vcpu, seg_reg);
6009         if (base_is_valid)
6010                 *ret += kvm_register_read(vcpu, base_reg);
6011         if (index_is_valid)
6012                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6013         *ret += exit_qualification; /* holds the displacement */
6014
6015         if (addr_size == 1) /* 32 bit */
6016                 *ret &= 0xffffffff;
6017
6018         /*
6019          * TODO: throw #GP (and return 1) in various cases that the VM*
6020          * instructions require it - e.g., offset beyond segment limit,
6021          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6022          * address, and so on. Currently these are not checked.
6023          */
6024         return 0;
6025 }
6026
6027 /* Emulate the VMCLEAR instruction */
6028 static int handle_vmclear(struct kvm_vcpu *vcpu)
6029 {
6030         struct vcpu_vmx *vmx = to_vmx(vcpu);
6031         gva_t gva;
6032         gpa_t vmptr;
6033         struct vmcs12 *vmcs12;
6034         struct page *page;
6035         struct x86_exception e;
6036
6037         if (!nested_vmx_check_permission(vcpu))
6038                 return 1;
6039
6040         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6041                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6042                 return 1;
6043
6044         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6045                                 sizeof(vmptr), &e)) {
6046                 kvm_inject_page_fault(vcpu, &e);
6047                 return 1;
6048         }
6049
6050         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6051                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6052                 skip_emulated_instruction(vcpu);
6053                 return 1;
6054         }
6055
6056         if (vmptr == vmx->nested.current_vmptr) {
6057                 nested_release_vmcs12(vmx);
6058                 vmx->nested.current_vmptr = -1ull;
6059                 vmx->nested.current_vmcs12 = NULL;
6060         }
6061
6062         page = nested_get_page(vcpu, vmptr);
6063         if (page == NULL) {
6064                 /*
6065                  * For accurate processor emulation, VMCLEAR beyond available
6066                  * physical memory should do nothing at all. However, it is
6067                  * possible that a nested vmx bug, not a guest hypervisor bug,
6068                  * resulted in this case, so let's shut down before doing any
6069                  * more damage:
6070                  */
6071                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6072                 return 1;
6073         }
6074         vmcs12 = kmap(page);
6075         vmcs12->launch_state = 0;
6076         kunmap(page);
6077         nested_release_page(page);
6078
6079         nested_free_vmcs02(vmx, vmptr);
6080
6081         skip_emulated_instruction(vcpu);
6082         nested_vmx_succeed(vcpu);
6083         return 1;
6084 }
6085
6086 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6087
6088 /* Emulate the VMLAUNCH instruction */
6089 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6090 {
6091         return nested_vmx_run(vcpu, true);
6092 }
6093
6094 /* Emulate the VMRESUME instruction */
6095 static int handle_vmresume(struct kvm_vcpu *vcpu)
6096 {
6097
6098         return nested_vmx_run(vcpu, false);
6099 }
6100
6101 enum vmcs_field_type {
6102         VMCS_FIELD_TYPE_U16 = 0,
6103         VMCS_FIELD_TYPE_U64 = 1,
6104         VMCS_FIELD_TYPE_U32 = 2,
6105         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6106 };
6107
6108 static inline int vmcs_field_type(unsigned long field)
6109 {
6110         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6111                 return VMCS_FIELD_TYPE_U32;
6112         return (field >> 13) & 0x3 ;
6113 }
6114
6115 static inline int vmcs_field_readonly(unsigned long field)
6116 {
6117         return (((field >> 10) & 0x3) == 1);
6118 }
6119
6120 /*
6121  * Read a vmcs12 field. Since these can have varying lengths and we return
6122  * one type, we chose the biggest type (u64) and zero-extend the return value
6123  * to that size. Note that the caller, handle_vmread, might need to use only
6124  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6125  * 64-bit fields are to be returned).
6126  */
6127 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6128                                         unsigned long field, u64 *ret)
6129 {
6130         short offset = vmcs_field_to_offset(field);
6131         char *p;
6132
6133         if (offset < 0)
6134                 return 0;
6135
6136         p = ((char *)(get_vmcs12(vcpu))) + offset;
6137
6138         switch (vmcs_field_type(field)) {
6139         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6140                 *ret = *((natural_width *)p);
6141                 return 1;
6142         case VMCS_FIELD_TYPE_U16:
6143                 *ret = *((u16 *)p);
6144                 return 1;
6145         case VMCS_FIELD_TYPE_U32:
6146                 *ret = *((u32 *)p);
6147                 return 1;
6148         case VMCS_FIELD_TYPE_U64:
6149                 *ret = *((u64 *)p);
6150                 return 1;
6151         default:
6152                 return 0; /* can never happen. */
6153         }
6154 }
6155
6156
6157 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6158                                     unsigned long field, u64 field_value){
6159         short offset = vmcs_field_to_offset(field);
6160         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6161         if (offset < 0)
6162                 return false;
6163
6164         switch (vmcs_field_type(field)) {
6165         case VMCS_FIELD_TYPE_U16:
6166                 *(u16 *)p = field_value;
6167                 return true;
6168         case VMCS_FIELD_TYPE_U32:
6169                 *(u32 *)p = field_value;
6170                 return true;
6171         case VMCS_FIELD_TYPE_U64:
6172                 *(u64 *)p = field_value;
6173                 return true;
6174         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6175                 *(natural_width *)p = field_value;
6176                 return true;
6177         default:
6178                 return false; /* can never happen. */
6179         }
6180
6181 }
6182
6183 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6184 {
6185         int i;
6186         unsigned long field;
6187         u64 field_value;
6188         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6189         const unsigned long *fields = shadow_read_write_fields;
6190         const int num_fields = max_shadow_read_write_fields;
6191
6192         vmcs_load(shadow_vmcs);
6193
6194         for (i = 0; i < num_fields; i++) {
6195                 field = fields[i];
6196                 switch (vmcs_field_type(field)) {
6197                 case VMCS_FIELD_TYPE_U16:
6198                         field_value = vmcs_read16(field);
6199                         break;
6200                 case VMCS_FIELD_TYPE_U32:
6201                         field_value = vmcs_read32(field);
6202                         break;
6203                 case VMCS_FIELD_TYPE_U64:
6204                         field_value = vmcs_read64(field);
6205                         break;
6206                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6207                         field_value = vmcs_readl(field);
6208                         break;
6209                 }
6210                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6211         }
6212
6213         vmcs_clear(shadow_vmcs);
6214         vmcs_load(vmx->loaded_vmcs->vmcs);
6215 }
6216
6217 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6218 {
6219         const unsigned long *fields[] = {
6220                 shadow_read_write_fields,
6221                 shadow_read_only_fields
6222         };
6223         const int max_fields[] = {
6224                 max_shadow_read_write_fields,
6225                 max_shadow_read_only_fields
6226         };
6227         int i, q;
6228         unsigned long field;
6229         u64 field_value = 0;
6230         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6231
6232         vmcs_load(shadow_vmcs);
6233
6234         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6235                 for (i = 0; i < max_fields[q]; i++) {
6236                         field = fields[q][i];
6237                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6238
6239                         switch (vmcs_field_type(field)) {
6240                         case VMCS_FIELD_TYPE_U16:
6241                                 vmcs_write16(field, (u16)field_value);
6242                                 break;
6243                         case VMCS_FIELD_TYPE_U32:
6244                                 vmcs_write32(field, (u32)field_value);
6245                                 break;
6246                         case VMCS_FIELD_TYPE_U64:
6247                                 vmcs_write64(field, (u64)field_value);
6248                                 break;
6249                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6250                                 vmcs_writel(field, (long)field_value);
6251                                 break;
6252                         }
6253                 }
6254         }
6255
6256         vmcs_clear(shadow_vmcs);
6257         vmcs_load(vmx->loaded_vmcs->vmcs);
6258 }
6259
6260 /*
6261  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6262  * used before) all generate the same failure when it is missing.
6263  */
6264 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6265 {
6266         struct vcpu_vmx *vmx = to_vmx(vcpu);
6267         if (vmx->nested.current_vmptr == -1ull) {
6268                 nested_vmx_failInvalid(vcpu);
6269                 skip_emulated_instruction(vcpu);
6270                 return 0;
6271         }
6272         return 1;
6273 }
6274
6275 static int handle_vmread(struct kvm_vcpu *vcpu)
6276 {
6277         unsigned long field;
6278         u64 field_value;
6279         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6280         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6281         gva_t gva = 0;
6282
6283         if (!nested_vmx_check_permission(vcpu) ||
6284             !nested_vmx_check_vmcs12(vcpu))
6285                 return 1;
6286
6287         /* Decode instruction info and find the field to read */
6288         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6289         /* Read the field, zero-extended to a u64 field_value */
6290         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6291                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6292                 skip_emulated_instruction(vcpu);
6293                 return 1;
6294         }
6295         /*
6296          * Now copy part of this value to register or memory, as requested.
6297          * Note that the number of bits actually copied is 32 or 64 depending
6298          * on the guest's mode (32 or 64 bit), not on the given field's length.
6299          */
6300         if (vmx_instruction_info & (1u << 10)) {
6301                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6302                         field_value);
6303         } else {
6304                 if (get_vmx_mem_address(vcpu, exit_qualification,
6305                                 vmx_instruction_info, &gva))
6306                         return 1;
6307                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6308                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6309                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6310         }
6311
6312         nested_vmx_succeed(vcpu);
6313         skip_emulated_instruction(vcpu);
6314         return 1;
6315 }
6316
6317
6318 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6319 {
6320         unsigned long field;
6321         gva_t gva;
6322         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6323         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6324         /* The value to write might be 32 or 64 bits, depending on L1's long
6325          * mode, and eventually we need to write that into a field of several
6326          * possible lengths. The code below first zero-extends the value to 64
6327          * bit (field_value), and then copies only the approriate number of
6328          * bits into the vmcs12 field.
6329          */
6330         u64 field_value = 0;
6331         struct x86_exception e;
6332
6333         if (!nested_vmx_check_permission(vcpu) ||
6334             !nested_vmx_check_vmcs12(vcpu))
6335                 return 1;
6336
6337         if (vmx_instruction_info & (1u << 10))
6338                 field_value = kvm_register_read(vcpu,
6339                         (((vmx_instruction_info) >> 3) & 0xf));
6340         else {
6341                 if (get_vmx_mem_address(vcpu, exit_qualification,
6342                                 vmx_instruction_info, &gva))
6343                         return 1;
6344                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6345                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6346                         kvm_inject_page_fault(vcpu, &e);
6347                         return 1;
6348                 }
6349         }
6350
6351
6352         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6353         if (vmcs_field_readonly(field)) {
6354                 nested_vmx_failValid(vcpu,
6355                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6356                 skip_emulated_instruction(vcpu);
6357                 return 1;
6358         }
6359
6360         if (!vmcs12_write_any(vcpu, field, field_value)) {
6361                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6362                 skip_emulated_instruction(vcpu);
6363                 return 1;
6364         }
6365
6366         nested_vmx_succeed(vcpu);
6367         skip_emulated_instruction(vcpu);
6368         return 1;
6369 }
6370
6371 /* Emulate the VMPTRLD instruction */
6372 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6373 {
6374         struct vcpu_vmx *vmx = to_vmx(vcpu);
6375         gva_t gva;
6376         gpa_t vmptr;
6377         struct x86_exception e;
6378         u32 exec_control;
6379
6380         if (!nested_vmx_check_permission(vcpu))
6381                 return 1;
6382
6383         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6384                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6385                 return 1;
6386
6387         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6388                                 sizeof(vmptr), &e)) {
6389                 kvm_inject_page_fault(vcpu, &e);
6390                 return 1;
6391         }
6392
6393         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6394                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6395                 skip_emulated_instruction(vcpu);
6396                 return 1;
6397         }
6398
6399         if (vmx->nested.current_vmptr != vmptr) {
6400                 struct vmcs12 *new_vmcs12;
6401                 struct page *page;
6402                 page = nested_get_page(vcpu, vmptr);
6403                 if (page == NULL) {
6404                         nested_vmx_failInvalid(vcpu);
6405                         skip_emulated_instruction(vcpu);
6406                         return 1;
6407                 }
6408                 new_vmcs12 = kmap(page);
6409                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6410                         kunmap(page);
6411                         nested_release_page_clean(page);
6412                         nested_vmx_failValid(vcpu,
6413                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6414                         skip_emulated_instruction(vcpu);
6415                         return 1;
6416                 }
6417                 if (vmx->nested.current_vmptr != -1ull)
6418                         nested_release_vmcs12(vmx);
6419
6420                 vmx->nested.current_vmptr = vmptr;
6421                 vmx->nested.current_vmcs12 = new_vmcs12;
6422                 vmx->nested.current_vmcs12_page = page;
6423                 if (enable_shadow_vmcs) {
6424                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6425                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6426                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6427                         vmcs_write64(VMCS_LINK_POINTER,
6428                                      __pa(vmx->nested.current_shadow_vmcs));
6429                         vmx->nested.sync_shadow_vmcs = true;
6430                 }
6431         }
6432
6433         nested_vmx_succeed(vcpu);
6434         skip_emulated_instruction(vcpu);
6435         return 1;
6436 }
6437
6438 /* Emulate the VMPTRST instruction */
6439 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6440 {
6441         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6442         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6443         gva_t vmcs_gva;
6444         struct x86_exception e;
6445
6446         if (!nested_vmx_check_permission(vcpu))
6447                 return 1;
6448
6449         if (get_vmx_mem_address(vcpu, exit_qualification,
6450                         vmx_instruction_info, &vmcs_gva))
6451                 return 1;
6452         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6453         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6454                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6455                                  sizeof(u64), &e)) {
6456                 kvm_inject_page_fault(vcpu, &e);
6457                 return 1;
6458         }
6459         nested_vmx_succeed(vcpu);
6460         skip_emulated_instruction(vcpu);
6461         return 1;
6462 }
6463
6464 /* Emulate the INVEPT instruction */
6465 static int handle_invept(struct kvm_vcpu *vcpu)
6466 {
6467         u32 vmx_instruction_info, types;
6468         unsigned long type;
6469         gva_t gva;
6470         struct x86_exception e;
6471         struct {
6472                 u64 eptp, gpa;
6473         } operand;
6474         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6475
6476         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6477             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6478                 kvm_queue_exception(vcpu, UD_VECTOR);
6479                 return 1;
6480         }
6481
6482         if (!nested_vmx_check_permission(vcpu))
6483                 return 1;
6484
6485         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6486                 kvm_queue_exception(vcpu, UD_VECTOR);
6487                 return 1;
6488         }
6489
6490         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6491         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6492
6493         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6494
6495         if (!(types & (1UL << type))) {
6496                 nested_vmx_failValid(vcpu,
6497                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6498                 return 1;
6499         }
6500
6501         /* According to the Intel VMX instruction reference, the memory
6502          * operand is read even if it isn't needed (e.g., for type==global)
6503          */
6504         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6505                         vmx_instruction_info, &gva))
6506                 return 1;
6507         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6508                                 sizeof(operand), &e)) {
6509                 kvm_inject_page_fault(vcpu, &e);
6510                 return 1;
6511         }
6512
6513         switch (type) {
6514         case VMX_EPT_EXTENT_CONTEXT:
6515                 if ((operand.eptp & eptp_mask) !=
6516                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6517                         break;
6518         case VMX_EPT_EXTENT_GLOBAL:
6519                 kvm_mmu_sync_roots(vcpu);
6520                 kvm_mmu_flush_tlb(vcpu);
6521                 nested_vmx_succeed(vcpu);
6522                 break;
6523         default:
6524                 BUG_ON(1);
6525                 break;
6526         }
6527
6528         skip_emulated_instruction(vcpu);
6529         return 1;
6530 }
6531
6532 /*
6533  * The exit handlers return 1 if the exit was handled fully and guest execution
6534  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6535  * to be done to userspace and return 0.
6536  */
6537 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6538         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6539         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6540         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6541         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6542         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6543         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6544         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6545         [EXIT_REASON_CPUID]                   = handle_cpuid,
6546         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6547         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6548         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6549         [EXIT_REASON_HLT]                     = handle_halt,
6550         [EXIT_REASON_INVD]                    = handle_invd,
6551         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6552         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6553         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6554         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6555         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6556         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6557         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6558         [EXIT_REASON_VMREAD]                  = handle_vmread,
6559         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6560         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6561         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6562         [EXIT_REASON_VMON]                    = handle_vmon,
6563         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6564         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6565         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6566         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6567         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6568         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6569         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6570         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6571         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6572         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6573         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6574         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6575         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6576         [EXIT_REASON_INVEPT]                  = handle_invept,
6577 };
6578
6579 static const int kvm_vmx_max_exit_handlers =
6580         ARRAY_SIZE(kvm_vmx_exit_handlers);
6581
6582 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6583                                        struct vmcs12 *vmcs12)
6584 {
6585         unsigned long exit_qualification;
6586         gpa_t bitmap, last_bitmap;
6587         unsigned int port;
6588         int size;
6589         u8 b;
6590
6591         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6592                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6593
6594         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6595
6596         port = exit_qualification >> 16;
6597         size = (exit_qualification & 7) + 1;
6598
6599         last_bitmap = (gpa_t)-1;
6600         b = -1;
6601
6602         while (size > 0) {
6603                 if (port < 0x8000)
6604                         bitmap = vmcs12->io_bitmap_a;
6605                 else if (port < 0x10000)
6606                         bitmap = vmcs12->io_bitmap_b;
6607                 else
6608                         return 1;
6609                 bitmap += (port & 0x7fff) / 8;
6610
6611                 if (last_bitmap != bitmap)
6612                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6613                                 return 1;
6614                 if (b & (1 << (port & 7)))
6615                         return 1;
6616
6617                 port++;
6618                 size--;
6619                 last_bitmap = bitmap;
6620         }
6621
6622         return 0;
6623 }
6624
6625 /*
6626  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6627  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6628  * disinterest in the current event (read or write a specific MSR) by using an
6629  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6630  */
6631 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6632         struct vmcs12 *vmcs12, u32 exit_reason)
6633 {
6634         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6635         gpa_t bitmap;
6636
6637         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6638                 return 1;
6639
6640         /*
6641          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6642          * for the four combinations of read/write and low/high MSR numbers.
6643          * First we need to figure out which of the four to use:
6644          */
6645         bitmap = vmcs12->msr_bitmap;
6646         if (exit_reason == EXIT_REASON_MSR_WRITE)
6647                 bitmap += 2048;
6648         if (msr_index >= 0xc0000000) {
6649                 msr_index -= 0xc0000000;
6650                 bitmap += 1024;
6651         }
6652
6653         /* Then read the msr_index'th bit from this bitmap: */
6654         if (msr_index < 1024*8) {
6655                 unsigned char b;
6656                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6657                         return 1;
6658                 return 1 & (b >> (msr_index & 7));
6659         } else
6660                 return 1; /* let L1 handle the wrong parameter */
6661 }
6662
6663 /*
6664  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6665  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6666  * intercept (via guest_host_mask etc.) the current event.
6667  */
6668 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6669         struct vmcs12 *vmcs12)
6670 {
6671         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6672         int cr = exit_qualification & 15;
6673         int reg = (exit_qualification >> 8) & 15;
6674         unsigned long val = kvm_register_read(vcpu, reg);
6675
6676         switch ((exit_qualification >> 4) & 3) {
6677         case 0: /* mov to cr */
6678                 switch (cr) {
6679                 case 0:
6680                         if (vmcs12->cr0_guest_host_mask &
6681                             (val ^ vmcs12->cr0_read_shadow))
6682                                 return 1;
6683                         break;
6684                 case 3:
6685                         if ((vmcs12->cr3_target_count >= 1 &&
6686                                         vmcs12->cr3_target_value0 == val) ||
6687                                 (vmcs12->cr3_target_count >= 2 &&
6688                                         vmcs12->cr3_target_value1 == val) ||
6689                                 (vmcs12->cr3_target_count >= 3 &&
6690                                         vmcs12->cr3_target_value2 == val) ||
6691                                 (vmcs12->cr3_target_count >= 4 &&
6692                                         vmcs12->cr3_target_value3 == val))
6693                                 return 0;
6694                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6695                                 return 1;
6696                         break;
6697                 case 4:
6698                         if (vmcs12->cr4_guest_host_mask &
6699                             (vmcs12->cr4_read_shadow ^ val))
6700                                 return 1;
6701                         break;
6702                 case 8:
6703                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6704                                 return 1;
6705                         break;
6706                 }
6707                 break;
6708         case 2: /* clts */
6709                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6710                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6711                         return 1;
6712                 break;
6713         case 1: /* mov from cr */
6714                 switch (cr) {
6715                 case 3:
6716                         if (vmcs12->cpu_based_vm_exec_control &
6717                             CPU_BASED_CR3_STORE_EXITING)
6718                                 return 1;
6719                         break;
6720                 case 8:
6721                         if (vmcs12->cpu_based_vm_exec_control &
6722                             CPU_BASED_CR8_STORE_EXITING)
6723                                 return 1;
6724                         break;
6725                 }
6726                 break;
6727         case 3: /* lmsw */
6728                 /*
6729                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6730                  * cr0. Other attempted changes are ignored, with no exit.
6731                  */
6732                 if (vmcs12->cr0_guest_host_mask & 0xe &
6733                     (val ^ vmcs12->cr0_read_shadow))
6734                         return 1;
6735                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6736                     !(vmcs12->cr0_read_shadow & 0x1) &&
6737                     (val & 0x1))
6738                         return 1;
6739                 break;
6740         }
6741         return 0;
6742 }
6743
6744 /*
6745  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6746  * should handle it ourselves in L0 (and then continue L2). Only call this
6747  * when in is_guest_mode (L2).
6748  */
6749 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6750 {
6751         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6752         struct vcpu_vmx *vmx = to_vmx(vcpu);
6753         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6754         u32 exit_reason = vmx->exit_reason;
6755
6756         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6757                                 vmcs_readl(EXIT_QUALIFICATION),
6758                                 vmx->idt_vectoring_info,
6759                                 intr_info,
6760                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6761                                 KVM_ISA_VMX);
6762
6763         if (vmx->nested.nested_run_pending)
6764                 return 0;
6765
6766         if (unlikely(vmx->fail)) {
6767                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6768                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6769                 return 1;
6770         }
6771
6772         switch (exit_reason) {
6773         case EXIT_REASON_EXCEPTION_NMI:
6774                 if (!is_exception(intr_info))
6775                         return 0;
6776                 else if (is_page_fault(intr_info))
6777                         return enable_ept;
6778                 else if (is_no_device(intr_info) &&
6779                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6780                         return 0;
6781                 return vmcs12->exception_bitmap &
6782                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6783         case EXIT_REASON_EXTERNAL_INTERRUPT:
6784                 return 0;
6785         case EXIT_REASON_TRIPLE_FAULT:
6786                 return 1;
6787         case EXIT_REASON_PENDING_INTERRUPT:
6788                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6789         case EXIT_REASON_NMI_WINDOW:
6790                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6791         case EXIT_REASON_TASK_SWITCH:
6792                 return 1;
6793         case EXIT_REASON_CPUID:
6794                 return 1;
6795         case EXIT_REASON_HLT:
6796                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6797         case EXIT_REASON_INVD:
6798                 return 1;
6799         case EXIT_REASON_INVLPG:
6800                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6801         case EXIT_REASON_RDPMC:
6802                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6803         case EXIT_REASON_RDTSC:
6804                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6805         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6806         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6807         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6808         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6809         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6810         case EXIT_REASON_INVEPT:
6811                 /*
6812                  * VMX instructions trap unconditionally. This allows L1 to
6813                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6814                  */
6815                 return 1;
6816         case EXIT_REASON_CR_ACCESS:
6817                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6818         case EXIT_REASON_DR_ACCESS:
6819                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6820         case EXIT_REASON_IO_INSTRUCTION:
6821                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6822         case EXIT_REASON_MSR_READ:
6823         case EXIT_REASON_MSR_WRITE:
6824                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6825         case EXIT_REASON_INVALID_STATE:
6826                 return 1;
6827         case EXIT_REASON_MWAIT_INSTRUCTION:
6828                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6829         case EXIT_REASON_MONITOR_INSTRUCTION:
6830                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6831         case EXIT_REASON_PAUSE_INSTRUCTION:
6832                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6833                         nested_cpu_has2(vmcs12,
6834                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6835         case EXIT_REASON_MCE_DURING_VMENTRY:
6836                 return 0;
6837         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6838                 return 1;
6839         case EXIT_REASON_APIC_ACCESS:
6840                 return nested_cpu_has2(vmcs12,
6841                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6842         case EXIT_REASON_EPT_VIOLATION:
6843                 /*
6844                  * L0 always deals with the EPT violation. If nested EPT is
6845                  * used, and the nested mmu code discovers that the address is
6846                  * missing in the guest EPT table (EPT12), the EPT violation
6847                  * will be injected with nested_ept_inject_page_fault()
6848                  */
6849                 return 0;
6850         case EXIT_REASON_EPT_MISCONFIG:
6851                 /*
6852                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6853                  * table (shadow on EPT) or a merged EPT table that L0 built
6854                  * (EPT on EPT). So any problems with the structure of the
6855                  * table is L0's fault.
6856                  */
6857                 return 0;
6858         case EXIT_REASON_WBINVD:
6859                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6860         case EXIT_REASON_XSETBV:
6861                 return 1;
6862         default:
6863                 return 1;
6864         }
6865 }
6866
6867 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6868 {
6869         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6870         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6871 }
6872
6873 /*
6874  * The guest has exited.  See if we can fix it or if we need userspace
6875  * assistance.
6876  */
6877 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6878 {
6879         struct vcpu_vmx *vmx = to_vmx(vcpu);
6880         u32 exit_reason = vmx->exit_reason;
6881         u32 vectoring_info = vmx->idt_vectoring_info;
6882
6883         /* If guest state is invalid, start emulating */
6884         if (vmx->emulation_required)
6885                 return handle_invalid_guest_state(vcpu);
6886
6887         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6888                 nested_vmx_vmexit(vcpu, exit_reason,
6889                                   vmcs_read32(VM_EXIT_INTR_INFO),
6890                                   vmcs_readl(EXIT_QUALIFICATION));
6891                 return 1;
6892         }
6893
6894         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6895                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6896                 vcpu->run->fail_entry.hardware_entry_failure_reason
6897                         = exit_reason;
6898                 return 0;
6899         }
6900
6901         if (unlikely(vmx->fail)) {
6902                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6903                 vcpu->run->fail_entry.hardware_entry_failure_reason
6904                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6905                 return 0;
6906         }
6907
6908         /*
6909          * Note:
6910          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6911          * delivery event since it indicates guest is accessing MMIO.
6912          * The vm-exit can be triggered again after return to guest that
6913          * will cause infinite loop.
6914          */
6915         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6916                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6917                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6918                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6919                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6920                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6921                 vcpu->run->internal.ndata = 2;
6922                 vcpu->run->internal.data[0] = vectoring_info;
6923                 vcpu->run->internal.data[1] = exit_reason;
6924                 return 0;
6925         }
6926
6927         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6928             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6929                                         get_vmcs12(vcpu))))) {
6930                 if (vmx_interrupt_allowed(vcpu)) {
6931                         vmx->soft_vnmi_blocked = 0;
6932                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6933                            vcpu->arch.nmi_pending) {
6934                         /*
6935                          * This CPU don't support us in finding the end of an
6936                          * NMI-blocked window if the guest runs with IRQs
6937                          * disabled. So we pull the trigger after 1 s of
6938                          * futile waiting, but inform the user about this.
6939                          */
6940                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6941                                "state on VCPU %d after 1 s timeout\n",
6942                                __func__, vcpu->vcpu_id);
6943                         vmx->soft_vnmi_blocked = 0;
6944                 }
6945         }
6946
6947         if (exit_reason < kvm_vmx_max_exit_handlers
6948             && kvm_vmx_exit_handlers[exit_reason])
6949                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6950         else {
6951                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6952                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6953         }
6954         return 0;
6955 }
6956
6957 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6958 {
6959         if (irr == -1 || tpr < irr) {
6960                 vmcs_write32(TPR_THRESHOLD, 0);
6961                 return;
6962         }
6963
6964         vmcs_write32(TPR_THRESHOLD, irr);
6965 }
6966
6967 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6968 {
6969         u32 sec_exec_control;
6970
6971         /*
6972          * There is not point to enable virtualize x2apic without enable
6973          * apicv
6974          */
6975         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6976                                 !vmx_vm_has_apicv(vcpu->kvm))
6977                 return;
6978
6979         if (!vm_need_tpr_shadow(vcpu->kvm))
6980                 return;
6981
6982         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6983
6984         if (set) {
6985                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6986                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6987         } else {
6988                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6989                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6990         }
6991         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6992
6993         vmx_set_msr_bitmap(vcpu);
6994 }
6995
6996 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6997 {
6998         u16 status;
6999         u8 old;
7000
7001         if (!vmx_vm_has_apicv(kvm))
7002                 return;
7003
7004         if (isr == -1)
7005                 isr = 0;
7006
7007         status = vmcs_read16(GUEST_INTR_STATUS);
7008         old = status >> 8;
7009         if (isr != old) {
7010                 status &= 0xff;
7011                 status |= isr << 8;
7012                 vmcs_write16(GUEST_INTR_STATUS, status);
7013         }
7014 }
7015
7016 static void vmx_set_rvi(int vector)
7017 {
7018         u16 status;
7019         u8 old;
7020
7021         status = vmcs_read16(GUEST_INTR_STATUS);
7022         old = (u8)status & 0xff;
7023         if ((u8)vector != old) {
7024                 status &= ~0xff;
7025                 status |= (u8)vector;
7026                 vmcs_write16(GUEST_INTR_STATUS, status);
7027         }
7028 }
7029
7030 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7031 {
7032         if (max_irr == -1)
7033                 return;
7034
7035         vmx_set_rvi(max_irr);
7036 }
7037
7038 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7039 {
7040         if (!vmx_vm_has_apicv(vcpu->kvm))
7041                 return;
7042
7043         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7044         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7045         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7046         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7047 }
7048
7049 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7050 {
7051         u32 exit_intr_info;
7052
7053         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7054               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7055                 return;
7056
7057         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7058         exit_intr_info = vmx->exit_intr_info;
7059
7060         /* Handle machine checks before interrupts are enabled */
7061         if (is_machine_check(exit_intr_info))
7062                 kvm_machine_check();
7063
7064         /* We need to handle NMIs before interrupts are enabled */
7065         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7066             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7067                 kvm_before_handle_nmi(&vmx->vcpu);
7068                 asm("int $2");
7069                 kvm_after_handle_nmi(&vmx->vcpu);
7070         }
7071 }
7072
7073 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7074 {
7075         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7076
7077         /*
7078          * If external interrupt exists, IF bit is set in rflags/eflags on the
7079          * interrupt stack frame, and interrupt will be enabled on a return
7080          * from interrupt handler.
7081          */
7082         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7083                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7084                 unsigned int vector;
7085                 unsigned long entry;
7086                 gate_desc *desc;
7087                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7088 #ifdef CONFIG_X86_64
7089                 unsigned long tmp;
7090 #endif
7091
7092                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7093                 desc = (gate_desc *)vmx->host_idt_base + vector;
7094                 entry = gate_offset(*desc);
7095                 asm volatile(
7096 #ifdef CONFIG_X86_64
7097                         "mov %%" _ASM_SP ", %[sp]\n\t"
7098                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7099                         "push $%c[ss]\n\t"
7100                         "push %[sp]\n\t"
7101 #endif
7102                         "pushf\n\t"
7103                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7104                         __ASM_SIZE(push) " $%c[cs]\n\t"
7105                         "call *%[entry]\n\t"
7106                         :
7107 #ifdef CONFIG_X86_64
7108                         [sp]"=&r"(tmp)
7109 #endif
7110                         :
7111                         [entry]"r"(entry),
7112                         [ss]"i"(__KERNEL_DS),
7113                         [cs]"i"(__KERNEL_CS)
7114                         );
7115         } else
7116                 local_irq_enable();
7117 }
7118
7119 static bool vmx_mpx_supported(void)
7120 {
7121         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7122                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7123 }
7124
7125 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7126 {
7127         u32 exit_intr_info;
7128         bool unblock_nmi;
7129         u8 vector;
7130         bool idtv_info_valid;
7131
7132         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7133
7134         if (cpu_has_virtual_nmis()) {
7135                 if (vmx->nmi_known_unmasked)
7136                         return;
7137                 /*
7138                  * Can't use vmx->exit_intr_info since we're not sure what
7139                  * the exit reason is.
7140                  */
7141                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7142                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7143                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7144                 /*
7145                  * SDM 3: 27.7.1.2 (September 2008)
7146                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7147                  * a guest IRET fault.
7148                  * SDM 3: 23.2.2 (September 2008)
7149                  * Bit 12 is undefined in any of the following cases:
7150                  *  If the VM exit sets the valid bit in the IDT-vectoring
7151                  *   information field.
7152                  *  If the VM exit is due to a double fault.
7153                  */
7154                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7155                     vector != DF_VECTOR && !idtv_info_valid)
7156                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7157                                       GUEST_INTR_STATE_NMI);
7158                 else
7159                         vmx->nmi_known_unmasked =
7160                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7161                                   & GUEST_INTR_STATE_NMI);
7162         } else if (unlikely(vmx->soft_vnmi_blocked))
7163                 vmx->vnmi_blocked_time +=
7164                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7165 }
7166
7167 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7168                                       u32 idt_vectoring_info,
7169                                       int instr_len_field,
7170                                       int error_code_field)
7171 {
7172         u8 vector;
7173         int type;
7174         bool idtv_info_valid;
7175
7176         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7177
7178         vcpu->arch.nmi_injected = false;
7179         kvm_clear_exception_queue(vcpu);
7180         kvm_clear_interrupt_queue(vcpu);
7181
7182         if (!idtv_info_valid)
7183                 return;
7184
7185         kvm_make_request(KVM_REQ_EVENT, vcpu);
7186
7187         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7188         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7189
7190         switch (type) {
7191         case INTR_TYPE_NMI_INTR:
7192                 vcpu->arch.nmi_injected = true;
7193                 /*
7194                  * SDM 3: 27.7.1.2 (September 2008)
7195                  * Clear bit "block by NMI" before VM entry if a NMI
7196                  * delivery faulted.
7197                  */
7198                 vmx_set_nmi_mask(vcpu, false);
7199                 break;
7200         case INTR_TYPE_SOFT_EXCEPTION:
7201                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7202                 /* fall through */
7203         case INTR_TYPE_HARD_EXCEPTION:
7204                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7205                         u32 err = vmcs_read32(error_code_field);
7206                         kvm_requeue_exception_e(vcpu, vector, err);
7207                 } else
7208                         kvm_requeue_exception(vcpu, vector);
7209                 break;
7210         case INTR_TYPE_SOFT_INTR:
7211                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7212                 /* fall through */
7213         case INTR_TYPE_EXT_INTR:
7214                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7215                 break;
7216         default:
7217                 break;
7218         }
7219 }
7220
7221 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7222 {
7223         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7224                                   VM_EXIT_INSTRUCTION_LEN,
7225                                   IDT_VECTORING_ERROR_CODE);
7226 }
7227
7228 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7229 {
7230         __vmx_complete_interrupts(vcpu,
7231                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7232                                   VM_ENTRY_INSTRUCTION_LEN,
7233                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7234
7235         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7236 }
7237
7238 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7239 {
7240         int i, nr_msrs;
7241         struct perf_guest_switch_msr *msrs;
7242
7243         msrs = perf_guest_get_msrs(&nr_msrs);
7244
7245         if (!msrs)
7246                 return;
7247
7248         for (i = 0; i < nr_msrs; i++)
7249                 if (msrs[i].host == msrs[i].guest)
7250                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7251                 else
7252                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7253                                         msrs[i].host);
7254 }
7255
7256 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7257 {
7258         struct vcpu_vmx *vmx = to_vmx(vcpu);
7259         unsigned long debugctlmsr;
7260
7261         /* Record the guest's net vcpu time for enforced NMI injections. */
7262         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7263                 vmx->entry_time = ktime_get();
7264
7265         /* Don't enter VMX if guest state is invalid, let the exit handler
7266            start emulation until we arrive back to a valid state */
7267         if (vmx->emulation_required)
7268                 return;
7269
7270         if (vmx->nested.sync_shadow_vmcs) {
7271                 copy_vmcs12_to_shadow(vmx);
7272                 vmx->nested.sync_shadow_vmcs = false;
7273         }
7274
7275         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7276                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7277         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7278                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7279
7280         /* When single-stepping over STI and MOV SS, we must clear the
7281          * corresponding interruptibility bits in the guest state. Otherwise
7282          * vmentry fails as it then expects bit 14 (BS) in pending debug
7283          * exceptions being set, but that's not correct for the guest debugging
7284          * case. */
7285         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7286                 vmx_set_interrupt_shadow(vcpu, 0);
7287
7288         atomic_switch_perf_msrs(vmx);
7289         debugctlmsr = get_debugctlmsr();
7290
7291         vmx->__launched = vmx->loaded_vmcs->launched;
7292         asm(
7293                 /* Store host registers */
7294                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7295                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7296                 "push %%" _ASM_CX " \n\t"
7297                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7298                 "je 1f \n\t"
7299                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7300                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7301                 "1: \n\t"
7302                 /* Reload cr2 if changed */
7303                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7304                 "mov %%cr2, %%" _ASM_DX " \n\t"
7305                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7306                 "je 2f \n\t"
7307                 "mov %%" _ASM_AX", %%cr2 \n\t"
7308                 "2: \n\t"
7309                 /* Check if vmlaunch of vmresume is needed */
7310                 "cmpl $0, %c[launched](%0) \n\t"
7311                 /* Load guest registers.  Don't clobber flags. */
7312                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7313                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7314                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7315                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7316                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7317                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7318 #ifdef CONFIG_X86_64
7319                 "mov %c[r8](%0),  %%r8  \n\t"
7320                 "mov %c[r9](%0),  %%r9  \n\t"
7321                 "mov %c[r10](%0), %%r10 \n\t"
7322                 "mov %c[r11](%0), %%r11 \n\t"
7323                 "mov %c[r12](%0), %%r12 \n\t"
7324                 "mov %c[r13](%0), %%r13 \n\t"
7325                 "mov %c[r14](%0), %%r14 \n\t"
7326                 "mov %c[r15](%0), %%r15 \n\t"
7327 #endif
7328                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7329
7330                 /* Enter guest mode */
7331                 "jne 1f \n\t"
7332                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7333                 "jmp 2f \n\t"
7334                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7335                 "2: "
7336                 /* Save guest registers, load host registers, keep flags */
7337                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7338                 "pop %0 \n\t"
7339                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7340                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7341                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7342                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7343                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7344                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7345                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7346 #ifdef CONFIG_X86_64
7347                 "mov %%r8,  %c[r8](%0) \n\t"
7348                 "mov %%r9,  %c[r9](%0) \n\t"
7349                 "mov %%r10, %c[r10](%0) \n\t"
7350                 "mov %%r11, %c[r11](%0) \n\t"
7351                 "mov %%r12, %c[r12](%0) \n\t"
7352                 "mov %%r13, %c[r13](%0) \n\t"
7353                 "mov %%r14, %c[r14](%0) \n\t"
7354                 "mov %%r15, %c[r15](%0) \n\t"
7355 #endif
7356                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7357                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7358
7359                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7360                 "setbe %c[fail](%0) \n\t"
7361                 ".pushsection .rodata \n\t"
7362                 ".global vmx_return \n\t"
7363                 "vmx_return: " _ASM_PTR " 2b \n\t"
7364                 ".popsection"
7365               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7366                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7367                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7368                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7369                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7370                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7371                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7372                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7373                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7374                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7375                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7376 #ifdef CONFIG_X86_64
7377                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7378                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7379                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7380                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7381                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7382                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7383                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7384                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7385 #endif
7386                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7387                 [wordsize]"i"(sizeof(ulong))
7388               : "cc", "memory"
7389 #ifdef CONFIG_X86_64
7390                 , "rax", "rbx", "rdi", "rsi"
7391                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7392 #else
7393                 , "eax", "ebx", "edi", "esi"
7394 #endif
7395               );
7396
7397         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7398         if (debugctlmsr)
7399                 update_debugctlmsr(debugctlmsr);
7400
7401 #ifndef CONFIG_X86_64
7402         /*
7403          * The sysexit path does not restore ds/es, so we must set them to
7404          * a reasonable value ourselves.
7405          *
7406          * We can't defer this to vmx_load_host_state() since that function
7407          * may be executed in interrupt context, which saves and restore segments
7408          * around it, nullifying its effect.
7409          */
7410         loadsegment(ds, __USER_DS);
7411         loadsegment(es, __USER_DS);
7412 #endif
7413
7414         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7415                                   | (1 << VCPU_EXREG_RFLAGS)
7416                                   | (1 << VCPU_EXREG_CPL)
7417                                   | (1 << VCPU_EXREG_PDPTR)
7418                                   | (1 << VCPU_EXREG_SEGMENTS)
7419                                   | (1 << VCPU_EXREG_CR3));
7420         vcpu->arch.regs_dirty = 0;
7421
7422         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7423
7424         vmx->loaded_vmcs->launched = 1;
7425
7426         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7427         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7428
7429         /*
7430          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7431          * we did not inject a still-pending event to L1 now because of
7432          * nested_run_pending, we need to re-enable this bit.
7433          */
7434         if (vmx->nested.nested_run_pending)
7435                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7436
7437         vmx->nested.nested_run_pending = 0;
7438
7439         vmx_complete_atomic_exit(vmx);
7440         vmx_recover_nmi_blocking(vmx);
7441         vmx_complete_interrupts(vmx);
7442 }
7443
7444 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7445 {
7446         struct vcpu_vmx *vmx = to_vmx(vcpu);
7447
7448         free_vpid(vmx);
7449         free_loaded_vmcs(vmx->loaded_vmcs);
7450         free_nested(vmx);
7451         kfree(vmx->guest_msrs);
7452         kvm_vcpu_uninit(vcpu);
7453         kmem_cache_free(kvm_vcpu_cache, vmx);
7454 }
7455
7456 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7457 {
7458         int err;
7459         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7460         int cpu;
7461
7462         if (!vmx)
7463                 return ERR_PTR(-ENOMEM);
7464
7465         allocate_vpid(vmx);
7466
7467         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7468         if (err)
7469                 goto free_vcpu;
7470
7471         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7472         err = -ENOMEM;
7473         if (!vmx->guest_msrs) {
7474                 goto uninit_vcpu;
7475         }
7476
7477         vmx->loaded_vmcs = &vmx->vmcs01;
7478         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7479         if (!vmx->loaded_vmcs->vmcs)
7480                 goto free_msrs;
7481         if (!vmm_exclusive)
7482                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7483         loaded_vmcs_init(vmx->loaded_vmcs);
7484         if (!vmm_exclusive)
7485                 kvm_cpu_vmxoff();
7486
7487         cpu = get_cpu();
7488         vmx_vcpu_load(&vmx->vcpu, cpu);
7489         vmx->vcpu.cpu = cpu;
7490         err = vmx_vcpu_setup(vmx);
7491         vmx_vcpu_put(&vmx->vcpu);
7492         put_cpu();
7493         if (err)
7494                 goto free_vmcs;
7495         if (vm_need_virtualize_apic_accesses(kvm)) {
7496                 err = alloc_apic_access_page(kvm);
7497                 if (err)
7498                         goto free_vmcs;
7499         }
7500
7501         if (enable_ept) {
7502                 if (!kvm->arch.ept_identity_map_addr)
7503                         kvm->arch.ept_identity_map_addr =
7504                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7505                 err = -ENOMEM;
7506                 if (alloc_identity_pagetable(kvm) != 0)
7507                         goto free_vmcs;
7508                 if (!init_rmode_identity_map(kvm))
7509                         goto free_vmcs;
7510         }
7511
7512         vmx->nested.current_vmptr = -1ull;
7513         vmx->nested.current_vmcs12 = NULL;
7514
7515         return &vmx->vcpu;
7516
7517 free_vmcs:
7518         free_loaded_vmcs(vmx->loaded_vmcs);
7519 free_msrs:
7520         kfree(vmx->guest_msrs);
7521 uninit_vcpu:
7522         kvm_vcpu_uninit(&vmx->vcpu);
7523 free_vcpu:
7524         free_vpid(vmx);
7525         kmem_cache_free(kvm_vcpu_cache, vmx);
7526         return ERR_PTR(err);
7527 }
7528
7529 static void __init vmx_check_processor_compat(void *rtn)
7530 {
7531         struct vmcs_config vmcs_conf;
7532
7533         *(int *)rtn = 0;
7534         if (setup_vmcs_config(&vmcs_conf) < 0)
7535                 *(int *)rtn = -EIO;
7536         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7537                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7538                                 smp_processor_id());
7539                 *(int *)rtn = -EIO;
7540         }
7541 }
7542
7543 static int get_ept_level(void)
7544 {
7545         return VMX_EPT_DEFAULT_GAW + 1;
7546 }
7547
7548 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7549 {
7550         u64 ret;
7551
7552         /* For VT-d and EPT combination
7553          * 1. MMIO: always map as UC
7554          * 2. EPT with VT-d:
7555          *   a. VT-d without snooping control feature: can't guarantee the
7556          *      result, try to trust guest.
7557          *   b. VT-d with snooping control feature: snooping control feature of
7558          *      VT-d engine can guarantee the cache correctness. Just set it
7559          *      to WB to keep consistent with host. So the same as item 3.
7560          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7561          *    consistent with host MTRR
7562          */
7563         if (is_mmio)
7564                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7565         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7566                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7567                       VMX_EPT_MT_EPTE_SHIFT;
7568         else
7569                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7570                         | VMX_EPT_IPAT_BIT;
7571
7572         return ret;
7573 }
7574
7575 static int vmx_get_lpage_level(void)
7576 {
7577         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7578                 return PT_DIRECTORY_LEVEL;
7579         else
7580                 /* For shadow and EPT supported 1GB page */
7581                 return PT_PDPE_LEVEL;
7582 }
7583
7584 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7585 {
7586         struct kvm_cpuid_entry2 *best;
7587         struct vcpu_vmx *vmx = to_vmx(vcpu);
7588         u32 exec_control;
7589
7590         vmx->rdtscp_enabled = false;
7591         if (vmx_rdtscp_supported()) {
7592                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7593                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7594                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7595                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7596                                 vmx->rdtscp_enabled = true;
7597                         else {
7598                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7599                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7600                                                 exec_control);
7601                         }
7602                 }
7603         }
7604
7605         /* Exposing INVPCID only when PCID is exposed */
7606         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7607         if (vmx_invpcid_supported() &&
7608             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7609             guest_cpuid_has_pcid(vcpu)) {
7610                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7611                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7612                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7613                              exec_control);
7614         } else {
7615                 if (cpu_has_secondary_exec_ctrls()) {
7616                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7617                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7618                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7619                                      exec_control);
7620                 }
7621                 if (best)
7622                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7623         }
7624 }
7625
7626 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7627 {
7628         if (func == 1 && nested)
7629                 entry->ecx |= bit(X86_FEATURE_VMX);
7630 }
7631
7632 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7633                 struct x86_exception *fault)
7634 {
7635         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7636         u32 exit_reason;
7637
7638         if (fault->error_code & PFERR_RSVD_MASK)
7639                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7640         else
7641                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7642         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7643         vmcs12->guest_physical_address = fault->address;
7644 }
7645
7646 /* Callbacks for nested_ept_init_mmu_context: */
7647
7648 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7649 {
7650         /* return the page table to be shadowed - in our case, EPT12 */
7651         return get_vmcs12(vcpu)->ept_pointer;
7652 }
7653
7654 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7655 {
7656         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7657                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7658
7659         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7660         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7661         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7662
7663         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7664 }
7665
7666 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7667 {
7668         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7669 }
7670
7671 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7672                 struct x86_exception *fault)
7673 {
7674         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7675
7676         WARN_ON(!is_guest_mode(vcpu));
7677
7678         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7679         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7680                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7681                                   vmcs_read32(VM_EXIT_INTR_INFO),
7682                                   vmcs_readl(EXIT_QUALIFICATION));
7683         else
7684                 kvm_inject_page_fault(vcpu, fault);
7685 }
7686
7687 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7688 {
7689         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7690         struct vcpu_vmx *vmx = to_vmx(vcpu);
7691
7692         if (vcpu->arch.virtual_tsc_khz == 0)
7693                 return;
7694
7695         /* Make sure short timeouts reliably trigger an immediate vmexit.
7696          * hrtimer_start does not guarantee this. */
7697         if (preemption_timeout <= 1) {
7698                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7699                 return;
7700         }
7701
7702         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7703         preemption_timeout *= 1000000;
7704         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7705         hrtimer_start(&vmx->nested.preemption_timer,
7706                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7707 }
7708
7709 /*
7710  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7711  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7712  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7713  * guest in a way that will both be appropriate to L1's requests, and our
7714  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7715  * function also has additional necessary side-effects, like setting various
7716  * vcpu->arch fields.
7717  */
7718 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7719 {
7720         struct vcpu_vmx *vmx = to_vmx(vcpu);
7721         u32 exec_control;
7722
7723         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7724         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7725         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7726         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7727         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7728         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7729         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7730         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7731         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7732         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7733         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7734         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7735         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7736         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7737         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7738         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7739         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7740         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7741         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7742         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7743         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7744         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7745         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7746         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7747         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7748         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7749         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7750         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7751         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7752         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7753         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7754         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7755         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7756         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7757         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7758         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7759
7760         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7761         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7762                 vmcs12->vm_entry_intr_info_field);
7763         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7764                 vmcs12->vm_entry_exception_error_code);
7765         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7766                 vmcs12->vm_entry_instruction_len);
7767         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7768                 vmcs12->guest_interruptibility_info);
7769         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7770         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7771         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7772         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7773                 vmcs12->guest_pending_dbg_exceptions);
7774         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7775         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7776
7777         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7778
7779         exec_control = vmcs12->pin_based_vm_exec_control;
7780         exec_control |= vmcs_config.pin_based_exec_ctrl;
7781         exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
7782                           PIN_BASED_POSTED_INTR);
7783         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7784
7785         vmx->nested.preemption_timer_expired = false;
7786         if (nested_cpu_has_preemption_timer(vmcs12))
7787                 vmx_start_preemption_timer(vcpu);
7788
7789         /*
7790          * Whether page-faults are trapped is determined by a combination of
7791          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7792          * If enable_ept, L0 doesn't care about page faults and we should
7793          * set all of these to L1's desires. However, if !enable_ept, L0 does
7794          * care about (at least some) page faults, and because it is not easy
7795          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7796          * to exit on each and every L2 page fault. This is done by setting
7797          * MASK=MATCH=0 and (see below) EB.PF=1.
7798          * Note that below we don't need special code to set EB.PF beyond the
7799          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7800          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7801          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7802          *
7803          * A problem with this approach (when !enable_ept) is that L1 may be
7804          * injected with more page faults than it asked for. This could have
7805          * caused problems, but in practice existing hypervisors don't care.
7806          * To fix this, we will need to emulate the PFEC checking (on the L1
7807          * page tables), using walk_addr(), when injecting PFs to L1.
7808          */
7809         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7810                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7811         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7812                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7813
7814         if (cpu_has_secondary_exec_ctrls()) {
7815                 exec_control = vmx_secondary_exec_control(vmx);
7816                 if (!vmx->rdtscp_enabled)
7817                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7818                 /* Take the following fields only from vmcs12 */
7819                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7820                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
7821                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
7822                 if (nested_cpu_has(vmcs12,
7823                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7824                         exec_control |= vmcs12->secondary_vm_exec_control;
7825
7826                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7827                         /*
7828                          * Translate L1 physical address to host physical
7829                          * address for vmcs02. Keep the page pinned, so this
7830                          * physical address remains valid. We keep a reference
7831                          * to it so we can release it later.
7832                          */
7833                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7834                                 nested_release_page(vmx->nested.apic_access_page);
7835                         vmx->nested.apic_access_page =
7836                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7837                         /*
7838                          * If translation failed, no matter: This feature asks
7839                          * to exit when accessing the given address, and if it
7840                          * can never be accessed, this feature won't do
7841                          * anything anyway.
7842                          */
7843                         if (!vmx->nested.apic_access_page)
7844                                 exec_control &=
7845                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7846                         else
7847                                 vmcs_write64(APIC_ACCESS_ADDR,
7848                                   page_to_phys(vmx->nested.apic_access_page));
7849                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7850                         exec_control |=
7851                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7852                         vmcs_write64(APIC_ACCESS_ADDR,
7853                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7854                 }
7855
7856                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7857         }
7858
7859
7860         /*
7861          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7862          * Some constant fields are set here by vmx_set_constant_host_state().
7863          * Other fields are different per CPU, and will be set later when
7864          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7865          */
7866         vmx_set_constant_host_state(vmx);
7867
7868         /*
7869          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7870          * entry, but only if the current (host) sp changed from the value
7871          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7872          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7873          * here we just force the write to happen on entry.
7874          */
7875         vmx->host_rsp = 0;
7876
7877         exec_control = vmx_exec_control(vmx); /* L0's desires */
7878         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7879         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7880         exec_control &= ~CPU_BASED_TPR_SHADOW;
7881         exec_control |= vmcs12->cpu_based_vm_exec_control;
7882         /*
7883          * Merging of IO and MSR bitmaps not currently supported.
7884          * Rather, exit every time.
7885          */
7886         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7887         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7888         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7889
7890         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7891
7892         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7893          * bitwise-or of what L1 wants to trap for L2, and what we want to
7894          * trap. Note that CR0.TS also needs updating - we do this later.
7895          */
7896         update_exception_bitmap(vcpu);
7897         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7898         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7899
7900         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7901          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7902          * bits are further modified by vmx_set_efer() below.
7903          */
7904         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7905
7906         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7907          * emulated by vmx_set_efer(), below.
7908          */
7909         vm_entry_controls_init(vmx,
7910                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7911                         ~VM_ENTRY_IA32E_MODE) |
7912                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7913
7914         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7915                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7916                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7917         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7918                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7919
7920
7921         set_cr4_guest_host_mask(vmx);
7922
7923         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7924                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7925
7926         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7927                 vmcs_write64(TSC_OFFSET,
7928                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7929         else
7930                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7931
7932         if (enable_vpid) {
7933                 /*
7934                  * Trivially support vpid by letting L2s share their parent
7935                  * L1's vpid. TODO: move to a more elaborate solution, giving
7936                  * each L2 its own vpid and exposing the vpid feature to L1.
7937                  */
7938                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7939                 vmx_flush_tlb(vcpu);
7940         }
7941
7942         if (nested_cpu_has_ept(vmcs12)) {
7943                 kvm_mmu_unload(vcpu);
7944                 nested_ept_init_mmu_context(vcpu);
7945         }
7946
7947         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7948                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7949         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7950                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7951         else
7952                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7953         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7954         vmx_set_efer(vcpu, vcpu->arch.efer);
7955
7956         /*
7957          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7958          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7959          * The CR0_READ_SHADOW is what L2 should have expected to read given
7960          * the specifications by L1; It's not enough to take
7961          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7962          * have more bits than L1 expected.
7963          */
7964         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7965         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7966
7967         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7968         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7969
7970         /* shadow page tables on either EPT or shadow page tables */
7971         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7972         kvm_mmu_reset_context(vcpu);
7973
7974         if (!enable_ept)
7975                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7976
7977         /*
7978          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7979          */
7980         if (enable_ept) {
7981                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7982                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7983                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7984                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7985         }
7986
7987         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7988         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7989 }
7990
7991 /*
7992  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7993  * for running an L2 nested guest.
7994  */
7995 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7996 {
7997         struct vmcs12 *vmcs12;
7998         struct vcpu_vmx *vmx = to_vmx(vcpu);
7999         int cpu;
8000         struct loaded_vmcs *vmcs02;
8001         bool ia32e;
8002
8003         if (!nested_vmx_check_permission(vcpu) ||
8004             !nested_vmx_check_vmcs12(vcpu))
8005                 return 1;
8006
8007         skip_emulated_instruction(vcpu);
8008         vmcs12 = get_vmcs12(vcpu);
8009
8010         if (enable_shadow_vmcs)
8011                 copy_shadow_to_vmcs12(vmx);
8012
8013         /*
8014          * The nested entry process starts with enforcing various prerequisites
8015          * on vmcs12 as required by the Intel SDM, and act appropriately when
8016          * they fail: As the SDM explains, some conditions should cause the
8017          * instruction to fail, while others will cause the instruction to seem
8018          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8019          * To speed up the normal (success) code path, we should avoid checking
8020          * for misconfigurations which will anyway be caught by the processor
8021          * when using the merged vmcs02.
8022          */
8023         if (vmcs12->launch_state == launch) {
8024                 nested_vmx_failValid(vcpu,
8025                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8026                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8027                 return 1;
8028         }
8029
8030         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8031             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8032                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8033                 return 1;
8034         }
8035
8036         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8037                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8038                 /*TODO: Also verify bits beyond physical address width are 0*/
8039                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8040                 return 1;
8041         }
8042
8043         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8044                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8045                 /*TODO: Also verify bits beyond physical address width are 0*/
8046                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8047                 return 1;
8048         }
8049
8050         if (vmcs12->vm_entry_msr_load_count > 0 ||
8051             vmcs12->vm_exit_msr_load_count > 0 ||
8052             vmcs12->vm_exit_msr_store_count > 0) {
8053                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8054                                     __func__);
8055                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8056                 return 1;
8057         }
8058
8059         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8060               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8061             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8062               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8063             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8064               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8065             !vmx_control_verify(vmcs12->vm_exit_controls,
8066               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8067             !vmx_control_verify(vmcs12->vm_entry_controls,
8068               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8069         {
8070                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8071                 return 1;
8072         }
8073
8074         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8075             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8076                 nested_vmx_failValid(vcpu,
8077                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8078                 return 1;
8079         }
8080
8081         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8082             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8083                 nested_vmx_entry_failure(vcpu, vmcs12,
8084                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8085                 return 1;
8086         }
8087         if (vmcs12->vmcs_link_pointer != -1ull) {
8088                 nested_vmx_entry_failure(vcpu, vmcs12,
8089                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8090                 return 1;
8091         }
8092
8093         /*
8094          * If the load IA32_EFER VM-entry control is 1, the following checks
8095          * are performed on the field for the IA32_EFER MSR:
8096          * - Bits reserved in the IA32_EFER MSR must be 0.
8097          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8098          *   the IA-32e mode guest VM-exit control. It must also be identical
8099          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8100          *   CR0.PG) is 1.
8101          */
8102         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8103                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8104                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8105                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8106                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8107                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8108                         nested_vmx_entry_failure(vcpu, vmcs12,
8109                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8110                         return 1;
8111                 }
8112         }
8113
8114         /*
8115          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8116          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8117          * the values of the LMA and LME bits in the field must each be that of
8118          * the host address-space size VM-exit control.
8119          */
8120         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8121                 ia32e = (vmcs12->vm_exit_controls &
8122                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8123                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8124                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8125                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8126                         nested_vmx_entry_failure(vcpu, vmcs12,
8127                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8128                         return 1;
8129                 }
8130         }
8131
8132         /*
8133          * We're finally done with prerequisite checking, and can start with
8134          * the nested entry.
8135          */
8136
8137         vmcs02 = nested_get_current_vmcs02(vmx);
8138         if (!vmcs02)
8139                 return -ENOMEM;
8140
8141         enter_guest_mode(vcpu);
8142
8143         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8144
8145         cpu = get_cpu();
8146         vmx->loaded_vmcs = vmcs02;
8147         vmx_vcpu_put(vcpu);
8148         vmx_vcpu_load(vcpu, cpu);
8149         vcpu->cpu = cpu;
8150         put_cpu();
8151
8152         vmx_segment_cache_clear(vmx);
8153
8154         vmcs12->launch_state = 1;
8155
8156         prepare_vmcs02(vcpu, vmcs12);
8157
8158         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8159                 return kvm_emulate_halt(vcpu);
8160
8161         vmx->nested.nested_run_pending = 1;
8162
8163         /*
8164          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8165          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8166          * returned as far as L1 is concerned. It will only return (and set
8167          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8168          */
8169         return 1;
8170 }
8171
8172 /*
8173  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8174  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8175  * This function returns the new value we should put in vmcs12.guest_cr0.
8176  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8177  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8178  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8179  *     didn't trap the bit, because if L1 did, so would L0).
8180  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8181  *     been modified by L2, and L1 knows it. So just leave the old value of
8182  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8183  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8184  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8185  *     changed these bits, and therefore they need to be updated, but L0
8186  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8187  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8188  */
8189 static inline unsigned long
8190 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8191 {
8192         return
8193         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8194         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8195         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8196                         vcpu->arch.cr0_guest_owned_bits));
8197 }
8198
8199 static inline unsigned long
8200 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8201 {
8202         return
8203         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8204         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8205         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8206                         vcpu->arch.cr4_guest_owned_bits));
8207 }
8208
8209 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8210                                        struct vmcs12 *vmcs12)
8211 {
8212         u32 idt_vectoring;
8213         unsigned int nr;
8214
8215         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8216                 nr = vcpu->arch.exception.nr;
8217                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8218
8219                 if (kvm_exception_is_soft(nr)) {
8220                         vmcs12->vm_exit_instruction_len =
8221                                 vcpu->arch.event_exit_inst_len;
8222                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8223                 } else
8224                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8225
8226                 if (vcpu->arch.exception.has_error_code) {
8227                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8228                         vmcs12->idt_vectoring_error_code =
8229                                 vcpu->arch.exception.error_code;
8230                 }
8231
8232                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8233         } else if (vcpu->arch.nmi_injected) {
8234                 vmcs12->idt_vectoring_info_field =
8235                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8236         } else if (vcpu->arch.interrupt.pending) {
8237                 nr = vcpu->arch.interrupt.nr;
8238                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8239
8240                 if (vcpu->arch.interrupt.soft) {
8241                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8242                         vmcs12->vm_entry_instruction_len =
8243                                 vcpu->arch.event_exit_inst_len;
8244                 } else
8245                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8246
8247                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8248         }
8249 }
8250
8251 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8252 {
8253         struct vcpu_vmx *vmx = to_vmx(vcpu);
8254
8255         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8256             vmx->nested.preemption_timer_expired) {
8257                 if (vmx->nested.nested_run_pending)
8258                         return -EBUSY;
8259                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8260                 return 0;
8261         }
8262
8263         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8264                 if (vmx->nested.nested_run_pending ||
8265                     vcpu->arch.interrupt.pending)
8266                         return -EBUSY;
8267                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8268                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8269                                   INTR_INFO_VALID_MASK, 0);
8270                 /*
8271                  * The NMI-triggered VM exit counts as injection:
8272                  * clear this one and block further NMIs.
8273                  */
8274                 vcpu->arch.nmi_pending = 0;
8275                 vmx_set_nmi_mask(vcpu, true);
8276                 return 0;
8277         }
8278
8279         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8280             nested_exit_on_intr(vcpu)) {
8281                 if (vmx->nested.nested_run_pending)
8282                         return -EBUSY;
8283                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8284         }
8285
8286         return 0;
8287 }
8288
8289 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8290 {
8291         ktime_t remaining =
8292                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8293         u64 value;
8294
8295         if (ktime_to_ns(remaining) <= 0)
8296                 return 0;
8297
8298         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8299         do_div(value, 1000000);
8300         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8301 }
8302
8303 /*
8304  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8305  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8306  * and this function updates it to reflect the changes to the guest state while
8307  * L2 was running (and perhaps made some exits which were handled directly by L0
8308  * without going back to L1), and to reflect the exit reason.
8309  * Note that we do not have to copy here all VMCS fields, just those that
8310  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8311  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8312  * which already writes to vmcs12 directly.
8313  */
8314 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8315                            u32 exit_reason, u32 exit_intr_info,
8316                            unsigned long exit_qualification)
8317 {
8318         /* update guest state fields: */
8319         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8320         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8321
8322         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8323         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8324         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8325         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8326
8327         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8328         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8329         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8330         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8331         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8332         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8333         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8334         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8335         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8336         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8337         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8338         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8339         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8340         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8341         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8342         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8343         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8344         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8345         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8346         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8347         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8348         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8349         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8350         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8351         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8352         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8353         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8354         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8355         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8356         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8357         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8358         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8359         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8360         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8361         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8362         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8363
8364         vmcs12->guest_interruptibility_info =
8365                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8366         vmcs12->guest_pending_dbg_exceptions =
8367                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8368         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8369                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8370         else
8371                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8372
8373         if (nested_cpu_has_preemption_timer(vmcs12)) {
8374                 if (vmcs12->vm_exit_controls &
8375                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8376                         vmcs12->vmx_preemption_timer_value =
8377                                 vmx_get_preemption_timer_value(vcpu);
8378                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8379         }
8380
8381         /*
8382          * In some cases (usually, nested EPT), L2 is allowed to change its
8383          * own CR3 without exiting. If it has changed it, we must keep it.
8384          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8385          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8386          *
8387          * Additionally, restore L2's PDPTR to vmcs12.
8388          */
8389         if (enable_ept) {
8390                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8391                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8392                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8393                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8394                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8395         }
8396
8397         vmcs12->vm_entry_controls =
8398                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8399                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8400
8401         /* TODO: These cannot have changed unless we have MSR bitmaps and
8402          * the relevant bit asks not to trap the change */
8403         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8404         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8405                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8406         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8407                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8408         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8409         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8410         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8411         if (vmx_mpx_supported())
8412                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8413
8414         /* update exit information fields: */
8415
8416         vmcs12->vm_exit_reason = exit_reason;
8417         vmcs12->exit_qualification = exit_qualification;
8418
8419         vmcs12->vm_exit_intr_info = exit_intr_info;
8420         if ((vmcs12->vm_exit_intr_info &
8421              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8422             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8423                 vmcs12->vm_exit_intr_error_code =
8424                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8425         vmcs12->idt_vectoring_info_field = 0;
8426         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8427         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8428
8429         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8430                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8431                  * instead of reading the real value. */
8432                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8433
8434                 /*
8435                  * Transfer the event that L0 or L1 may wanted to inject into
8436                  * L2 to IDT_VECTORING_INFO_FIELD.
8437                  */
8438                 vmcs12_save_pending_event(vcpu, vmcs12);
8439         }
8440
8441         /*
8442          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8443          * preserved above and would only end up incorrectly in L1.
8444          */
8445         vcpu->arch.nmi_injected = false;
8446         kvm_clear_exception_queue(vcpu);
8447         kvm_clear_interrupt_queue(vcpu);
8448 }
8449
8450 /*
8451  * A part of what we need to when the nested L2 guest exits and we want to
8452  * run its L1 parent, is to reset L1's guest state to the host state specified
8453  * in vmcs12.
8454  * This function is to be called not only on normal nested exit, but also on
8455  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8456  * Failures During or After Loading Guest State").
8457  * This function should be called when the active VMCS is L1's (vmcs01).
8458  */
8459 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8460                                    struct vmcs12 *vmcs12)
8461 {
8462         struct kvm_segment seg;
8463
8464         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8465                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8466         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8467                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8468         else
8469                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8470         vmx_set_efer(vcpu, vcpu->arch.efer);
8471
8472         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8473         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8474         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8475         /*
8476          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8477          * actually changed, because it depends on the current state of
8478          * fpu_active (which may have changed).
8479          * Note that vmx_set_cr0 refers to efer set above.
8480          */
8481         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8482         /*
8483          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8484          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8485          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8486          */
8487         update_exception_bitmap(vcpu);
8488         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8489         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8490
8491         /*
8492          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8493          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8494          */
8495         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8496         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8497
8498         nested_ept_uninit_mmu_context(vcpu);
8499
8500         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8501         kvm_mmu_reset_context(vcpu);
8502
8503         if (!enable_ept)
8504                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8505
8506         if (enable_vpid) {
8507                 /*
8508                  * Trivially support vpid by letting L2s share their parent
8509                  * L1's vpid. TODO: move to a more elaborate solution, giving
8510                  * each L2 its own vpid and exposing the vpid feature to L1.
8511                  */
8512                 vmx_flush_tlb(vcpu);
8513         }
8514
8515
8516         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8517         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8518         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8519         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8520         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8521
8522         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8523         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8524                 vmcs_write64(GUEST_BNDCFGS, 0);
8525
8526         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8527                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8528                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8529         }
8530         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8531                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8532                         vmcs12->host_ia32_perf_global_ctrl);
8533
8534         /* Set L1 segment info according to Intel SDM
8535             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8536         seg = (struct kvm_segment) {
8537                 .base = 0,
8538                 .limit = 0xFFFFFFFF,
8539                 .selector = vmcs12->host_cs_selector,
8540                 .type = 11,
8541                 .present = 1,
8542                 .s = 1,
8543                 .g = 1
8544         };
8545         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8546                 seg.l = 1;
8547         else
8548                 seg.db = 1;
8549         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8550         seg = (struct kvm_segment) {
8551                 .base = 0,
8552                 .limit = 0xFFFFFFFF,
8553                 .type = 3,
8554                 .present = 1,
8555                 .s = 1,
8556                 .db = 1,
8557                 .g = 1
8558         };
8559         seg.selector = vmcs12->host_ds_selector;
8560         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8561         seg.selector = vmcs12->host_es_selector;
8562         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8563         seg.selector = vmcs12->host_ss_selector;
8564         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8565         seg.selector = vmcs12->host_fs_selector;
8566         seg.base = vmcs12->host_fs_base;
8567         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8568         seg.selector = vmcs12->host_gs_selector;
8569         seg.base = vmcs12->host_gs_base;
8570         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8571         seg = (struct kvm_segment) {
8572                 .base = vmcs12->host_tr_base,
8573                 .limit = 0x67,
8574                 .selector = vmcs12->host_tr_selector,
8575                 .type = 11,
8576                 .present = 1
8577         };
8578         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8579
8580         kvm_set_dr(vcpu, 7, 0x400);
8581         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8582 }
8583
8584 /*
8585  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8586  * and modify vmcs12 to make it see what it would expect to see there if
8587  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8588  */
8589 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8590                               u32 exit_intr_info,
8591                               unsigned long exit_qualification)
8592 {
8593         struct vcpu_vmx *vmx = to_vmx(vcpu);
8594         int cpu;
8595         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8596
8597         /* trying to cancel vmlaunch/vmresume is a bug */
8598         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8599
8600         leave_guest_mode(vcpu);
8601         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8602                        exit_qualification);
8603
8604         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8605                                        vmcs12->exit_qualification,
8606                                        vmcs12->idt_vectoring_info_field,
8607                                        vmcs12->vm_exit_intr_info,
8608                                        vmcs12->vm_exit_intr_error_code,
8609                                        KVM_ISA_VMX);
8610
8611         cpu = get_cpu();
8612         vmx->loaded_vmcs = &vmx->vmcs01;
8613         vmx_vcpu_put(vcpu);
8614         vmx_vcpu_load(vcpu, cpu);
8615         vcpu->cpu = cpu;
8616         put_cpu();
8617
8618         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8619         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8620         vmx_segment_cache_clear(vmx);
8621
8622         /* if no vmcs02 cache requested, remove the one we used */
8623         if (VMCS02_POOL_SIZE == 0)
8624                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8625
8626         load_vmcs12_host_state(vcpu, vmcs12);
8627
8628         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8629         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8630
8631         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8632         vmx->host_rsp = 0;
8633
8634         /* Unpin physical memory we referred to in vmcs02 */
8635         if (vmx->nested.apic_access_page) {
8636                 nested_release_page(vmx->nested.apic_access_page);
8637                 vmx->nested.apic_access_page = 0;
8638         }
8639
8640         /*
8641          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8642          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8643          * success or failure flag accordingly.
8644          */
8645         if (unlikely(vmx->fail)) {
8646                 vmx->fail = 0;
8647                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8648         } else
8649                 nested_vmx_succeed(vcpu);
8650         if (enable_shadow_vmcs)
8651                 vmx->nested.sync_shadow_vmcs = true;
8652
8653         /* in case we halted in L2 */
8654         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8655 }
8656
8657 /*
8658  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8659  */
8660 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8661 {
8662         if (is_guest_mode(vcpu))
8663                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8664         free_nested(to_vmx(vcpu));
8665 }
8666
8667 /*
8668  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8669  * 23.7 "VM-entry failures during or after loading guest state" (this also
8670  * lists the acceptable exit-reason and exit-qualification parameters).
8671  * It should only be called before L2 actually succeeded to run, and when
8672  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8673  */
8674 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8675                         struct vmcs12 *vmcs12,
8676                         u32 reason, unsigned long qualification)
8677 {
8678         load_vmcs12_host_state(vcpu, vmcs12);
8679         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8680         vmcs12->exit_qualification = qualification;
8681         nested_vmx_succeed(vcpu);
8682         if (enable_shadow_vmcs)
8683                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8684 }
8685
8686 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8687                                struct x86_instruction_info *info,
8688                                enum x86_intercept_stage stage)
8689 {
8690         return X86EMUL_CONTINUE;
8691 }
8692
8693 static struct kvm_x86_ops vmx_x86_ops = {
8694         .cpu_has_kvm_support = cpu_has_kvm_support,
8695         .disabled_by_bios = vmx_disabled_by_bios,
8696         .hardware_setup = hardware_setup,
8697         .hardware_unsetup = hardware_unsetup,
8698         .check_processor_compatibility = vmx_check_processor_compat,
8699         .hardware_enable = hardware_enable,
8700         .hardware_disable = hardware_disable,
8701         .cpu_has_accelerated_tpr = report_flexpriority,
8702
8703         .vcpu_create = vmx_create_vcpu,
8704         .vcpu_free = vmx_free_vcpu,
8705         .vcpu_reset = vmx_vcpu_reset,
8706
8707         .prepare_guest_switch = vmx_save_host_state,
8708         .vcpu_load = vmx_vcpu_load,
8709         .vcpu_put = vmx_vcpu_put,
8710
8711         .update_db_bp_intercept = update_exception_bitmap,
8712         .get_msr = vmx_get_msr,
8713         .set_msr = vmx_set_msr,
8714         .get_segment_base = vmx_get_segment_base,
8715         .get_segment = vmx_get_segment,
8716         .set_segment = vmx_set_segment,
8717         .get_cpl = vmx_get_cpl,
8718         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8719         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8720         .decache_cr3 = vmx_decache_cr3,
8721         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8722         .set_cr0 = vmx_set_cr0,
8723         .set_cr3 = vmx_set_cr3,
8724         .set_cr4 = vmx_set_cr4,
8725         .set_efer = vmx_set_efer,
8726         .get_idt = vmx_get_idt,
8727         .set_idt = vmx_set_idt,
8728         .get_gdt = vmx_get_gdt,
8729         .set_gdt = vmx_set_gdt,
8730         .get_dr6 = vmx_get_dr6,
8731         .set_dr6 = vmx_set_dr6,
8732         .set_dr7 = vmx_set_dr7,
8733         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8734         .cache_reg = vmx_cache_reg,
8735         .get_rflags = vmx_get_rflags,
8736         .set_rflags = vmx_set_rflags,
8737         .fpu_activate = vmx_fpu_activate,
8738         .fpu_deactivate = vmx_fpu_deactivate,
8739
8740         .tlb_flush = vmx_flush_tlb,
8741
8742         .run = vmx_vcpu_run,
8743         .handle_exit = vmx_handle_exit,
8744         .skip_emulated_instruction = skip_emulated_instruction,
8745         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8746         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8747         .patch_hypercall = vmx_patch_hypercall,
8748         .set_irq = vmx_inject_irq,
8749         .set_nmi = vmx_inject_nmi,
8750         .queue_exception = vmx_queue_exception,
8751         .cancel_injection = vmx_cancel_injection,
8752         .interrupt_allowed = vmx_interrupt_allowed,
8753         .nmi_allowed = vmx_nmi_allowed,
8754         .get_nmi_mask = vmx_get_nmi_mask,
8755         .set_nmi_mask = vmx_set_nmi_mask,
8756         .enable_nmi_window = enable_nmi_window,
8757         .enable_irq_window = enable_irq_window,
8758         .update_cr8_intercept = update_cr8_intercept,
8759         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8760         .vm_has_apicv = vmx_vm_has_apicv,
8761         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8762         .hwapic_irr_update = vmx_hwapic_irr_update,
8763         .hwapic_isr_update = vmx_hwapic_isr_update,
8764         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8765         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8766
8767         .set_tss_addr = vmx_set_tss_addr,
8768         .get_tdp_level = get_ept_level,
8769         .get_mt_mask = vmx_get_mt_mask,
8770
8771         .get_exit_info = vmx_get_exit_info,
8772
8773         .get_lpage_level = vmx_get_lpage_level,
8774
8775         .cpuid_update = vmx_cpuid_update,
8776
8777         .rdtscp_supported = vmx_rdtscp_supported,
8778         .invpcid_supported = vmx_invpcid_supported,
8779
8780         .set_supported_cpuid = vmx_set_supported_cpuid,
8781
8782         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8783
8784         .set_tsc_khz = vmx_set_tsc_khz,
8785         .read_tsc_offset = vmx_read_tsc_offset,
8786         .write_tsc_offset = vmx_write_tsc_offset,
8787         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8788         .compute_tsc_offset = vmx_compute_tsc_offset,
8789         .read_l1_tsc = vmx_read_l1_tsc,
8790
8791         .set_tdp_cr3 = vmx_set_cr3,
8792
8793         .check_intercept = vmx_check_intercept,
8794         .handle_external_intr = vmx_handle_external_intr,
8795         .mpx_supported = vmx_mpx_supported,
8796
8797         .check_nested_events = vmx_check_nested_events,
8798 };
8799
8800 static int __init vmx_init(void)
8801 {
8802         int r, i, msr;
8803
8804         rdmsrl_safe(MSR_EFER, &host_efer);
8805
8806         for (i = 0; i < NR_VMX_MSR; ++i)
8807                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8808
8809         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8810         if (!vmx_io_bitmap_a)
8811                 return -ENOMEM;
8812
8813         r = -ENOMEM;
8814
8815         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8816         if (!vmx_io_bitmap_b)
8817                 goto out;
8818
8819         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8820         if (!vmx_msr_bitmap_legacy)
8821                 goto out1;
8822
8823         vmx_msr_bitmap_legacy_x2apic =
8824                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8825         if (!vmx_msr_bitmap_legacy_x2apic)
8826                 goto out2;
8827
8828         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8829         if (!vmx_msr_bitmap_longmode)
8830                 goto out3;
8831
8832         vmx_msr_bitmap_longmode_x2apic =
8833                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8834         if (!vmx_msr_bitmap_longmode_x2apic)
8835                 goto out4;
8836         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8837         if (!vmx_vmread_bitmap)
8838                 goto out5;
8839
8840         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8841         if (!vmx_vmwrite_bitmap)
8842                 goto out6;
8843
8844         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8845         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8846
8847         /*
8848          * Allow direct access to the PC debug port (it is often used for I/O
8849          * delays, but the vmexits simply slow things down).
8850          */
8851         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8852         clear_bit(0x80, vmx_io_bitmap_a);
8853
8854         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8855
8856         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8857         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8858
8859         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8860
8861         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8862                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8863         if (r)
8864                 goto out7;
8865
8866 #ifdef CONFIG_KEXEC
8867         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8868                            crash_vmclear_local_loaded_vmcss);
8869 #endif
8870
8871         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8872         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8873         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8874         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8875         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8876         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8877         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8878
8879         memcpy(vmx_msr_bitmap_legacy_x2apic,
8880                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8881         memcpy(vmx_msr_bitmap_longmode_x2apic,
8882                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8883
8884         if (enable_apicv) {
8885                 for (msr = 0x800; msr <= 0x8ff; msr++)
8886                         vmx_disable_intercept_msr_read_x2apic(msr);
8887
8888                 /* According SDM, in x2apic mode, the whole id reg is used.
8889                  * But in KVM, it only use the highest eight bits. Need to
8890                  * intercept it */
8891                 vmx_enable_intercept_msr_read_x2apic(0x802);
8892                 /* TMCCT */
8893                 vmx_enable_intercept_msr_read_x2apic(0x839);
8894                 /* TPR */
8895                 vmx_disable_intercept_msr_write_x2apic(0x808);
8896                 /* EOI */
8897                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8898                 /* SELF-IPI */
8899                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8900         }
8901
8902         if (enable_ept) {
8903                 kvm_mmu_set_mask_ptes(0ull,
8904                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8905                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8906                         0ull, VMX_EPT_EXECUTABLE_MASK);
8907                 ept_set_mmio_spte_mask();
8908                 kvm_enable_tdp();
8909         } else
8910                 kvm_disable_tdp();
8911
8912         return 0;
8913
8914 out7:
8915         free_page((unsigned long)vmx_vmwrite_bitmap);
8916 out6:
8917         free_page((unsigned long)vmx_vmread_bitmap);
8918 out5:
8919         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8920 out4:
8921         free_page((unsigned long)vmx_msr_bitmap_longmode);
8922 out3:
8923         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8924 out2:
8925         free_page((unsigned long)vmx_msr_bitmap_legacy);
8926 out1:
8927         free_page((unsigned long)vmx_io_bitmap_b);
8928 out:
8929         free_page((unsigned long)vmx_io_bitmap_a);
8930         return r;
8931 }
8932
8933 static void __exit vmx_exit(void)
8934 {
8935         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8936         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8937         free_page((unsigned long)vmx_msr_bitmap_legacy);
8938         free_page((unsigned long)vmx_msr_bitmap_longmode);
8939         free_page((unsigned long)vmx_io_bitmap_b);
8940         free_page((unsigned long)vmx_io_bitmap_a);
8941         free_page((unsigned long)vmx_vmwrite_bitmap);
8942         free_page((unsigned long)vmx_vmread_bitmap);
8943
8944 #ifdef CONFIG_KEXEC
8945         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8946         synchronize_rcu();
8947 #endif
8948
8949         kvm_exit();
8950 }
8951
8952 module_init(vmx_init)
8953 module_exit(vmx_exit)