arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static u64 construct_eptp(unsigned long root_hpa);
 716 static void kvm_cpu_vmxon(u64 addr);
 717 static void kvm_cpu_vmxoff(void);
 718 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg);
 722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 729
 730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 732 /*
 733  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 734  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 735  */
 736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 738
 739 static unsigned long *vmx_io_bitmap_a;
 740 static unsigned long *vmx_io_bitmap_b;
 741 static unsigned long *vmx_msr_bitmap_legacy;
 742 static unsigned long *vmx_msr_bitmap_longmode;
 743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 745 static unsigned long *vmx_vmread_bitmap;
 746 static unsigned long *vmx_vmwrite_bitmap;
 747
 748 static bool cpu_has_load_ia32_efer;
 749 static bool cpu_has_load_perf_global_ctrl;
 750
 751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 752 static DEFINE_SPINLOCK(vmx_vpid_lock);
 753
 754 static struct vmcs_config {
 755         int size;
 756         int order;
 757         u32 revision_id;
 758         u32 pin_based_exec_ctrl;
 759         u32 cpu_based_exec_ctrl;
 760         u32 cpu_based_2nd_exec_ctrl;
 761         u32 vmexit_ctrl;
 762         u32 vmentry_ctrl;
 763 } vmcs_config;
 764
 765 static struct vmx_capability {
 766         u32 ept;
 767         u32 vpid;
 768 } vmx_capability;
 769
 770 #define VMX_SEGMENT_FIELD(seg)                                  \
 771         [VCPU_SREG_##seg] = {                                   \
 772                 .selector = GUEST_##seg##_SELECTOR,             \
 773                 .base = GUEST_##seg##_BASE,                     \
 774                 .limit = GUEST_##seg##_LIMIT,                   \
 775                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 776         }
 777
 778 static const struct kvm_vmx_segment_field {
 779         unsigned selector;
 780         unsigned base;
 781         unsigned limit;
 782         unsigned ar_bytes;
 783 } kvm_vmx_segment_fields[] = {
 784         VMX_SEGMENT_FIELD(CS),
 785         VMX_SEGMENT_FIELD(DS),
 786         VMX_SEGMENT_FIELD(ES),
 787         VMX_SEGMENT_FIELD(FS),
 788         VMX_SEGMENT_FIELD(GS),
 789         VMX_SEGMENT_FIELD(SS),
 790         VMX_SEGMENT_FIELD(TR),
 791         VMX_SEGMENT_FIELD(LDTR),
 792 };
 793
 794 static u64 host_efer;
 795
 796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 797
 798 /*
 799  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 800  * away by decrementing the array size.
 801  */
 802 static const u32 vmx_msr_index[] = {
 803 #ifdef CONFIG_X86_64
 804         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 805 #endif
 806         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 807 };
 808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 809
 810 static inline bool is_page_fault(u32 intr_info)
 811 {
 812         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 813                              INTR_INFO_VALID_MASK)) ==
 814                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 815 }
 816
 817 static inline bool is_no_device(u32 intr_info)
 818 {
 819         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 820                              INTR_INFO_VALID_MASK)) ==
 821                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 822 }
 823
 824 static inline bool is_invalid_opcode(u32 intr_info)
 825 {
 826         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 827                              INTR_INFO_VALID_MASK)) ==
 828                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 829 }
 830
 831 static inline bool is_external_interrupt(u32 intr_info)
 832 {
 833         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 834                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 835 }
 836
 837 static inline bool is_machine_check(u32 intr_info)
 838 {
 839         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 840                              INTR_INFO_VALID_MASK)) ==
 841                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 842 }
 843
 844 static inline bool cpu_has_vmx_msr_bitmap(void)
 845 {
 846         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 847 }
 848
 849 static inline bool cpu_has_vmx_tpr_shadow(void)
 850 {
 851         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 852 }
 853
 854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 855 {
 856         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 857 }
 858
 859 static inline bool cpu_has_secondary_exec_ctrls(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl &
 862                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 863 }
 864
 865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 869 }
 870
 871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 875 }
 876
 877 static inline bool cpu_has_vmx_apic_register_virt(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 881 }
 882
 883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 887 }
 888
 889 static inline bool cpu_has_vmx_posted_intr(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 892 }
 893
 894 static inline bool cpu_has_vmx_apicv(void)
 895 {
 896         return cpu_has_vmx_apic_register_virt() &&
 897                 cpu_has_vmx_virtual_intr_delivery() &&
 898                 cpu_has_vmx_posted_intr();
 899 }
 900
 901 static inline bool cpu_has_vmx_flexpriority(void)
 902 {
 903         return cpu_has_vmx_tpr_shadow() &&
 904                 cpu_has_vmx_virtualize_apic_accesses();
 905 }
 906
 907 static inline bool cpu_has_vmx_ept_execute_only(void)
 908 {
 909         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 910 }
 911
 912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 913 {
 914         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 915 }
 916
 917 static inline bool cpu_has_vmx_eptp_writeback(void)
 918 {
 919         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_2m_page(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_ept_1g_page(void)
 928 {
 929         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_ept_4levels(void)
 933 {
 934         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_ad_bits(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_AD_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_invept_context(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_invept_global(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_invvpid_single(void)
 953 {
 954         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invvpid_global(void)
 958 {
 959         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_ept(void)
 963 {
 964         return vmcs_config.cpu_based_2nd_exec_ctrl &
 965                 SECONDARY_EXEC_ENABLE_EPT;
 966 }
 967
 968 static inline bool cpu_has_vmx_unrestricted_guest(void)
 969 {
 970         return vmcs_config.cpu_based_2nd_exec_ctrl &
 971                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 972 }
 973
 974 static inline bool cpu_has_vmx_ple(void)
 975 {
 976         return vmcs_config.cpu_based_2nd_exec_ctrl &
 977                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 978 }
 979
 980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 981 {
 982         return flexpriority_enabled && irqchip_in_kernel(kvm);
 983 }
 984
 985 static inline bool cpu_has_vmx_vpid(void)
 986 {
 987         return vmcs_config.cpu_based_2nd_exec_ctrl &
 988                 SECONDARY_EXEC_ENABLE_VPID;
 989 }
 990
 991 static inline bool cpu_has_vmx_rdtscp(void)
 992 {
 993         return vmcs_config.cpu_based_2nd_exec_ctrl &
 994                 SECONDARY_EXEC_RDTSCP;
 995 }
 996
 997 static inline bool cpu_has_vmx_invpcid(void)
 998 {
 999         return vmcs_config.cpu_based_2nd_exec_ctrl &
1000                 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010         return vmcs_config.cpu_based_2nd_exec_ctrl &
1011                 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016         u64 vmx_msr;
1017         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018         /* check if the cpu supports writing r/o exit information fields */
1019         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020                 return false;
1021
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028         return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033         return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038         return (vmcs12->cpu_based_vm_exec_control &
1039                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040                 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1044         struct kvm_vcpu *vcpu)
1045 {
1046         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1047 }
1048
1049 static inline bool is_exception(u32 intr_info)
1050 {
1051         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1052                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1053 }
1054
1055 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1056 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1057                         struct vmcs12 *vmcs12,
1058                         u32 reason, unsigned long qualification);
1059
1060 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1061 {
1062         int i;
1063
1064         for (i = 0; i < vmx->nmsrs; ++i)
1065                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1066                         return i;
1067         return -1;
1068 }
1069
1070 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1071 {
1072     struct {
1073         u64 vpid : 16;
1074         u64 rsvd : 48;
1075         u64 gva;
1076     } operand = { vpid, 0, gva };
1077
1078     asm volatile (__ex(ASM_VMX_INVVPID)
1079                   /* CF==1 or ZF==1 --> rc = -1 */
1080                   "; ja 1f ; ud2 ; 1:"
1081                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1082 }
1083
1084 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1085 {
1086         struct {
1087                 u64 eptp, gpa;
1088         } operand = {eptp, gpa};
1089
1090         asm volatile (__ex(ASM_VMX_INVEPT)
1091                         /* CF==1 or ZF==1 --> rc = -1 */
1092                         "; ja 1f ; ud2 ; 1:\n"
1093                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1094 }
1095
1096 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1097 {
1098         int i;
1099
1100         i = __find_msr_index(vmx, msr);
1101         if (i >= 0)
1102                 return &vmx->guest_msrs[i];
1103         return NULL;
1104 }
1105
1106 static void vmcs_clear(struct vmcs *vmcs)
1107 {
1108         u64 phys_addr = __pa(vmcs);
1109         u8 error;
1110
1111         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1112                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1113                       : "cc", "memory");
1114         if (error)
1115                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1116                        vmcs, phys_addr);
1117 }
1118
1119 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1120 {
1121         vmcs_clear(loaded_vmcs->vmcs);
1122         loaded_vmcs->cpu = -1;
1123         loaded_vmcs->launched = 0;
1124 }
1125
1126 static void vmcs_load(struct vmcs *vmcs)
1127 {
1128         u64 phys_addr = __pa(vmcs);
1129         u8 error;
1130
1131         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1132                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1133                         : "cc", "memory");
1134         if (error)
1135                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1136                        vmcs, phys_addr);
1137 }
1138
1139 #ifdef CONFIG_KEXEC
1140 /*
1141  * This bitmap is used to indicate whether the vmclear
1142  * operation is enabled on all cpus. All disabled by
1143  * default.
1144  */
1145 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1146
1147 static inline void crash_enable_local_vmclear(int cpu)
1148 {
1149         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1150 }
1151
1152 static inline void crash_disable_local_vmclear(int cpu)
1153 {
1154         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1155 }
1156
1157 static inline int crash_local_vmclear_enabled(int cpu)
1158 {
1159         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1160 }
1161
1162 static void crash_vmclear_local_loaded_vmcss(void)
1163 {
1164         int cpu = raw_smp_processor_id();
1165         struct loaded_vmcs *v;
1166
1167         if (!crash_local_vmclear_enabled(cpu))
1168                 return;
1169
1170         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1171                             loaded_vmcss_on_cpu_link)
1172                 vmcs_clear(v->vmcs);
1173 }
1174 #else
1175 static inline void crash_enable_local_vmclear(int cpu) { }
1176 static inline void crash_disable_local_vmclear(int cpu) { }
1177 #endif /* CONFIG_KEXEC */
1178
1179 static void __loaded_vmcs_clear(void *arg)
1180 {
1181         struct loaded_vmcs *loaded_vmcs = arg;
1182         int cpu = raw_smp_processor_id();
1183
1184         if (loaded_vmcs->cpu != cpu)
1185                 return; /* vcpu migration can race with cpu offline */
1186         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1187                 per_cpu(current_vmcs, cpu) = NULL;
1188         crash_disable_local_vmclear(cpu);
1189         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1190
1191         /*
1192          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1193          * is before setting loaded_vmcs->vcpu to -1 which is done in
1194          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1195          * then adds the vmcs into percpu list before it is deleted.
1196          */
1197         smp_wmb();
1198
1199         loaded_vmcs_init(loaded_vmcs);
1200         crash_enable_local_vmclear(cpu);
1201 }
1202
1203 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1204 {
1205         int cpu = loaded_vmcs->cpu;
1206
1207         if (cpu != -1)
1208                 smp_call_function_single(cpu,
1209                          __loaded_vmcs_clear, loaded_vmcs, 1);
1210 }
1211
1212 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1213 {
1214         if (vmx->vpid == 0)
1215                 return;
1216
1217         if (cpu_has_vmx_invvpid_single())
1218                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1219 }
1220
1221 static inline void vpid_sync_vcpu_global(void)
1222 {
1223         if (cpu_has_vmx_invvpid_global())
1224                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1225 }
1226
1227 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1228 {
1229         if (cpu_has_vmx_invvpid_single())
1230                 vpid_sync_vcpu_single(vmx);
1231         else
1232                 vpid_sync_vcpu_global();
1233 }
1234
1235 static inline void ept_sync_global(void)
1236 {
1237         if (cpu_has_vmx_invept_global())
1238                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1239 }
1240
1241 static inline void ept_sync_context(u64 eptp)
1242 {
1243         if (enable_ept) {
1244                 if (cpu_has_vmx_invept_context())
1245                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1246                 else
1247                         ept_sync_global();
1248         }
1249 }
1250
1251 static __always_inline unsigned long vmcs_readl(unsigned long field)
1252 {
1253         unsigned long value;
1254
1255         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1256                       : "=a"(value) : "d"(field) : "cc");
1257         return value;
1258 }
1259
1260 static __always_inline u16 vmcs_read16(unsigned long field)
1261 {
1262         return vmcs_readl(field);
1263 }
1264
1265 static __always_inline u32 vmcs_read32(unsigned long field)
1266 {
1267         return vmcs_readl(field);
1268 }
1269
1270 static __always_inline u64 vmcs_read64(unsigned long field)
1271 {
1272 #ifdef CONFIG_X86_64
1273         return vmcs_readl(field);
1274 #else
1275         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1276 #endif
1277 }
1278
1279 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1280 {
1281         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1282                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1283         dump_stack();
1284 }
1285
1286 static void vmcs_writel(unsigned long field, unsigned long value)
1287 {
1288         u8 error;
1289
1290         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1291                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1292         if (unlikely(error))
1293                 vmwrite_error(field, value);
1294 }
1295
1296 static void vmcs_write16(unsigned long field, u16 value)
1297 {
1298         vmcs_writel(field, value);
1299 }
1300
1301 static void vmcs_write32(unsigned long field, u32 value)
1302 {
1303         vmcs_writel(field, value);
1304 }
1305
1306 static void vmcs_write64(unsigned long field, u64 value)
1307 {
1308         vmcs_writel(field, value);
1309 #ifndef CONFIG_X86_64
1310         asm volatile ("");
1311         vmcs_writel(field+1, value >> 32);
1312 #endif
1313 }
1314
1315 static void vmcs_clear_bits(unsigned long field, u32 mask)
1316 {
1317         vmcs_writel(field, vmcs_readl(field) & ~mask);
1318 }
1319
1320 static void vmcs_set_bits(unsigned long field, u32 mask)
1321 {
1322         vmcs_writel(field, vmcs_readl(field) | mask);
1323 }
1324
1325 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1326 {
1327         vmx->segment_cache.bitmask = 0;
1328 }
1329
1330 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1331                                        unsigned field)
1332 {
1333         bool ret;
1334         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1335
1336         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1337                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1338                 vmx->segment_cache.bitmask = 0;
1339         }
1340         ret = vmx->segment_cache.bitmask & mask;
1341         vmx->segment_cache.bitmask |= mask;
1342         return ret;
1343 }
1344
1345 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1346 {
1347         u16 *p = &vmx->segment_cache.seg[seg].selector;
1348
1349         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1350                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1351         return *p;
1352 }
1353
1354 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1355 {
1356         ulong *p = &vmx->segment_cache.seg[seg].base;
1357
1358         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1359                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1360         return *p;
1361 }
1362
1363 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1364 {
1365         u32 *p = &vmx->segment_cache.seg[seg].limit;
1366
1367         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1368                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1369         return *p;
1370 }
1371
1372 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1373 {
1374         u32 *p = &vmx->segment_cache.seg[seg].ar;
1375
1376         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1377                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1378         return *p;
1379 }
1380
1381 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1382 {
1383         u32 eb;
1384
1385         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1386              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1387         if ((vcpu->guest_debug &
1388              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1389             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1390                 eb |= 1u << BP_VECTOR;
1391         if (to_vmx(vcpu)->rmode.vm86_active)
1392                 eb = ~0;
1393         if (enable_ept)
1394                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1395         if (vcpu->fpu_active)
1396                 eb &= ~(1u << NM_VECTOR);
1397
1398         /* When we are running a nested L2 guest and L1 specified for it a
1399          * certain exception bitmap, we must trap the same exceptions and pass
1400          * them to L1. When running L2, we will only handle the exceptions
1401          * specified above if L1 did not want them.
1402          */
1403         if (is_guest_mode(vcpu))
1404                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1405
1406         vmcs_write32(EXCEPTION_BITMAP, eb);
1407 }
1408
1409 static void clear_atomic_switch_msr_special(unsigned long entry,
1410                 unsigned long exit)
1411 {
1412         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1413         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1414 }
1415
1416 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1417 {
1418         unsigned i;
1419         struct msr_autoload *m = &vmx->msr_autoload;
1420
1421         switch (msr) {
1422         case MSR_EFER:
1423                 if (cpu_has_load_ia32_efer) {
1424                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1425                                         VM_EXIT_LOAD_IA32_EFER);
1426                         return;
1427                 }
1428                 break;
1429         case MSR_CORE_PERF_GLOBAL_CTRL:
1430                 if (cpu_has_load_perf_global_ctrl) {
1431                         clear_atomic_switch_msr_special(
1432                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1433                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1434                         return;
1435                 }
1436                 break;
1437         }
1438
1439         for (i = 0; i < m->nr; ++i)
1440                 if (m->guest[i].index == msr)
1441                         break;
1442
1443         if (i == m->nr)
1444                 return;
1445         --m->nr;
1446         m->guest[i] = m->guest[m->nr];
1447         m->host[i] = m->host[m->nr];
1448         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1449         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1450 }
1451
1452 static void add_atomic_switch_msr_special(unsigned long entry,
1453                 unsigned long exit, unsigned long guest_val_vmcs,
1454                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1455 {
1456         vmcs_write64(guest_val_vmcs, guest_val);
1457         vmcs_write64(host_val_vmcs, host_val);
1458         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1459         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1460 }
1461
1462 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1463                                   u64 guest_val, u64 host_val)
1464 {
1465         unsigned i;
1466         struct msr_autoload *m = &vmx->msr_autoload;
1467
1468         switch (msr) {
1469         case MSR_EFER:
1470                 if (cpu_has_load_ia32_efer) {
1471                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1472                                         VM_EXIT_LOAD_IA32_EFER,
1473                                         GUEST_IA32_EFER,
1474                                         HOST_IA32_EFER,
1475                                         guest_val, host_val);
1476                         return;
1477                 }
1478                 break;
1479         case MSR_CORE_PERF_GLOBAL_CTRL:
1480                 if (cpu_has_load_perf_global_ctrl) {
1481                         add_atomic_switch_msr_special(
1482                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1483                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1484                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1485                                         HOST_IA32_PERF_GLOBAL_CTRL,
1486                                         guest_val, host_val);
1487                         return;
1488                 }
1489                 break;
1490         }
1491
1492         for (i = 0; i < m->nr; ++i)
1493                 if (m->guest[i].index == msr)
1494                         break;
1495
1496         if (i == NR_AUTOLOAD_MSRS) {
1497                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1498                                 "Can't add msr %x\n", msr);
1499                 return;
1500         } else if (i == m->nr) {
1501                 ++m->nr;
1502                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1503                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1504         }
1505
1506         m->guest[i].index = msr;
1507         m->guest[i].value = guest_val;
1508         m->host[i].index = msr;
1509         m->host[i].value = host_val;
1510 }
1511
1512 static void reload_tss(void)
1513 {
1514         /*
1515          * VT restores TR but not its size.  Useless.
1516          */
1517         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1518         struct desc_struct *descs;
1519
1520         descs = (void *)gdt->address;
1521         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1522         load_TR_desc();
1523 }
1524
1525 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1526 {
1527         u64 guest_efer;
1528         u64 ignore_bits;
1529
1530         guest_efer = vmx->vcpu.arch.efer;
1531
1532         /*
1533          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1534          * outside long mode
1535          */
1536         ignore_bits = EFER_NX | EFER_SCE;
1537 #ifdef CONFIG_X86_64
1538         ignore_bits |= EFER_LMA | EFER_LME;
1539         /* SCE is meaningful only in long mode on Intel */
1540         if (guest_efer & EFER_LMA)
1541                 ignore_bits &= ~(u64)EFER_SCE;
1542 #endif
1543         guest_efer &= ~ignore_bits;
1544         guest_efer |= host_efer & ignore_bits;
1545         vmx->guest_msrs[efer_offset].data = guest_efer;
1546         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1547
1548         clear_atomic_switch_msr(vmx, MSR_EFER);
1549         /* On ept, can't emulate nx, and must switch nx atomically */
1550         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1551                 guest_efer = vmx->vcpu.arch.efer;
1552                 if (!(guest_efer & EFER_LMA))
1553                         guest_efer &= ~EFER_LME;
1554                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1555                 return false;
1556         }
1557
1558         return true;
1559 }
1560
1561 static unsigned long segment_base(u16 selector)
1562 {
1563         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1564         struct desc_struct *d;
1565         unsigned long table_base;
1566         unsigned long v;
1567
1568         if (!(selector & ~3))
1569                 return 0;
1570
1571         table_base = gdt->address;
1572
1573         if (selector & 4) {           /* from ldt */
1574                 u16 ldt_selector = kvm_read_ldt();
1575
1576                 if (!(ldt_selector & ~3))
1577                         return 0;
1578
1579                 table_base = segment_base(ldt_selector);
1580         }
1581         d = (struct desc_struct *)(table_base + (selector & ~7));
1582         v = get_desc_base(d);
1583 #ifdef CONFIG_X86_64
1584        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1585                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1586 #endif
1587         return v;
1588 }
1589
1590 static inline unsigned long kvm_read_tr_base(void)
1591 {
1592         u16 tr;
1593         asm("str %0" : "=g"(tr));
1594         return segment_base(tr);
1595 }
1596
1597 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1598 {
1599         struct vcpu_vmx *vmx = to_vmx(vcpu);
1600         int i;
1601
1602         if (vmx->host_state.loaded)
1603                 return;
1604
1605         vmx->host_state.loaded = 1;
1606         /*
1607          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1608          * allow segment selectors with cpl > 0 or ti == 1.
1609          */
1610         vmx->host_state.ldt_sel = kvm_read_ldt();
1611         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1612         savesegment(fs, vmx->host_state.fs_sel);
1613         if (!(vmx->host_state.fs_sel & 7)) {
1614                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1615                 vmx->host_state.fs_reload_needed = 0;
1616         } else {
1617                 vmcs_write16(HOST_FS_SELECTOR, 0);
1618                 vmx->host_state.fs_reload_needed = 1;
1619         }
1620         savesegment(gs, vmx->host_state.gs_sel);
1621         if (!(vmx->host_state.gs_sel & 7))
1622                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1623         else {
1624                 vmcs_write16(HOST_GS_SELECTOR, 0);
1625                 vmx->host_state.gs_ldt_reload_needed = 1;
1626         }
1627
1628 #ifdef CONFIG_X86_64
1629         savesegment(ds, vmx->host_state.ds_sel);
1630         savesegment(es, vmx->host_state.es_sel);
1631 #endif
1632
1633 #ifdef CONFIG_X86_64
1634         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1635         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1636 #else
1637         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1638         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1639 #endif
1640
1641 #ifdef CONFIG_X86_64
1642         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1643         if (is_long_mode(&vmx->vcpu))
1644                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1645 #endif
1646         for (i = 0; i < vmx->save_nmsrs; ++i)
1647                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1648                                    vmx->guest_msrs[i].data,
1649                                    vmx->guest_msrs[i].mask);
1650 }
1651
1652 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1653 {
1654         if (!vmx->host_state.loaded)
1655                 return;
1656
1657         ++vmx->vcpu.stat.host_state_reload;
1658         vmx->host_state.loaded = 0;
1659 #ifdef CONFIG_X86_64
1660         if (is_long_mode(&vmx->vcpu))
1661                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1662 #endif
1663         if (vmx->host_state.gs_ldt_reload_needed) {
1664                 kvm_load_ldt(vmx->host_state.ldt_sel);
1665 #ifdef CONFIG_X86_64
1666                 load_gs_index(vmx->host_state.gs_sel);
1667 #else
1668                 loadsegment(gs, vmx->host_state.gs_sel);
1669 #endif
1670         }
1671         if (vmx->host_state.fs_reload_needed)
1672                 loadsegment(fs, vmx->host_state.fs_sel);
1673 #ifdef CONFIG_X86_64
1674         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1675                 loadsegment(ds, vmx->host_state.ds_sel);
1676                 loadsegment(es, vmx->host_state.es_sel);
1677         }
1678 #endif
1679         reload_tss();
1680 #ifdef CONFIG_X86_64
1681         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1682 #endif
1683         /*
1684          * If the FPU is not active (through the host task or
1685          * the guest vcpu), then restore the cr0.TS bit.
1686          */
1687         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1688                 stts();
1689         load_gdt(&__get_cpu_var(host_gdt));
1690 }
1691
1692 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1693 {
1694         preempt_disable();
1695         __vmx_load_host_state(vmx);
1696         preempt_enable();
1697 }
1698
1699 /*
1700  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1701  * vcpu mutex is already taken.
1702  */
1703 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1704 {
1705         struct vcpu_vmx *vmx = to_vmx(vcpu);
1706         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1707
1708         if (!vmm_exclusive)
1709                 kvm_cpu_vmxon(phys_addr);
1710         else if (vmx->loaded_vmcs->cpu != cpu)
1711                 loaded_vmcs_clear(vmx->loaded_vmcs);
1712
1713         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1714                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1715                 vmcs_load(vmx->loaded_vmcs->vmcs);
1716         }
1717
1718         if (vmx->loaded_vmcs->cpu != cpu) {
1719                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1720                 unsigned long sysenter_esp;
1721
1722                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1723                 local_irq_disable();
1724                 crash_disable_local_vmclear(cpu);
1725
1726                 /*
1727                  * Read loaded_vmcs->cpu should be before fetching
1728                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1729                  * See the comments in __loaded_vmcs_clear().
1730                  */
1731                 smp_rmb();
1732
1733                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1734                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1735                 crash_enable_local_vmclear(cpu);
1736                 local_irq_enable();
1737
1738                 /*
1739                  * Linux uses per-cpu TSS and GDT, so set these when switching
1740                  * processors.
1741                  */
1742                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1743                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1744
1745                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1746                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1747                 vmx->loaded_vmcs->cpu = cpu;
1748         }
1749 }
1750
1751 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1752 {
1753         __vmx_load_host_state(to_vmx(vcpu));
1754         if (!vmm_exclusive) {
1755                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1756                 vcpu->cpu = -1;
1757                 kvm_cpu_vmxoff();
1758         }
1759 }
1760
1761 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1762 {
1763         ulong cr0;
1764
1765         if (vcpu->fpu_active)
1766                 return;
1767         vcpu->fpu_active = 1;
1768         cr0 = vmcs_readl(GUEST_CR0);
1769         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1770         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1771         vmcs_writel(GUEST_CR0, cr0);
1772         update_exception_bitmap(vcpu);
1773         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1774         if (is_guest_mode(vcpu))
1775                 vcpu->arch.cr0_guest_owned_bits &=
1776                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1777         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1778 }
1779
1780 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1781
1782 /*
1783  * Return the cr0 value that a nested guest would read. This is a combination
1784  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1785  * its hypervisor (cr0_read_shadow).
1786  */
1787 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1788 {
1789         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1790                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1791 }
1792 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1793 {
1794         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1795                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1796 }
1797
1798 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1799 {
1800         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1801          * set this *before* calling this function.
1802          */
1803         vmx_decache_cr0_guest_bits(vcpu);
1804         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1805         update_exception_bitmap(vcpu);
1806         vcpu->arch.cr0_guest_owned_bits = 0;
1807         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1808         if (is_guest_mode(vcpu)) {
1809                 /*
1810                  * L1's specified read shadow might not contain the TS bit,
1811                  * so now that we turned on shadowing of this bit, we need to
1812                  * set this bit of the shadow. Like in nested_vmx_run we need
1813                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1814                  * up-to-date here because we just decached cr0.TS (and we'll
1815                  * only update vmcs12->guest_cr0 on nested exit).
1816                  */
1817                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1818                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1819                         (vcpu->arch.cr0 & X86_CR0_TS);
1820                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1821         } else
1822                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1823 }
1824
1825 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1826 {
1827         unsigned long rflags, save_rflags;
1828
1829         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1830                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1831                 rflags = vmcs_readl(GUEST_RFLAGS);
1832                 if (to_vmx(vcpu)->rmode.vm86_active) {
1833                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1834                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1835                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1836                 }
1837                 to_vmx(vcpu)->rflags = rflags;
1838         }
1839         return to_vmx(vcpu)->rflags;
1840 }
1841
1842 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1843 {
1844         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1845         to_vmx(vcpu)->rflags = rflags;
1846         if (to_vmx(vcpu)->rmode.vm86_active) {
1847                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1848                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1849         }
1850         vmcs_writel(GUEST_RFLAGS, rflags);
1851 }
1852
1853 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1854 {
1855         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1856         int ret = 0;
1857
1858         if (interruptibility & GUEST_INTR_STATE_STI)
1859                 ret |= KVM_X86_SHADOW_INT_STI;
1860         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1861                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1862
1863         return ret & mask;
1864 }
1865
1866 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1867 {
1868         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1869         u32 interruptibility = interruptibility_old;
1870
1871         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1872
1873         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1874                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1875         else if (mask & KVM_X86_SHADOW_INT_STI)
1876                 interruptibility |= GUEST_INTR_STATE_STI;
1877
1878         if ((interruptibility != interruptibility_old))
1879                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1880 }
1881
1882 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1883 {
1884         unsigned long rip;
1885
1886         rip = kvm_rip_read(vcpu);
1887         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1888         kvm_rip_write(vcpu, rip);
1889
1890         /* skipping an emulated instruction also counts */
1891         vmx_set_interrupt_shadow(vcpu, 0);
1892 }
1893
1894 /*
1895  * KVM wants to inject page-faults which it got to the guest. This function
1896  * checks whether in a nested guest, we need to inject them to L1 or L2.
1897  * This function assumes it is called with the exit reason in vmcs02 being
1898  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1899  * is running).
1900  */
1901 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1902 {
1903         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1904
1905         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1906         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1907                 return 0;
1908
1909         nested_vmx_vmexit(vcpu);
1910         return 1;
1911 }
1912
1913 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1914                                 bool has_error_code, u32 error_code,
1915                                 bool reinject)
1916 {
1917         struct vcpu_vmx *vmx = to_vmx(vcpu);
1918         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1919
1920         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1921             !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1922                 return;
1923
1924         if (has_error_code) {
1925                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1926                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927         }
1928
1929         if (vmx->rmode.vm86_active) {
1930                 int inc_eip = 0;
1931                 if (kvm_exception_is_soft(nr))
1932                         inc_eip = vcpu->arch.event_exit_inst_len;
1933                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1934                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1935                 return;
1936         }
1937
1938         if (kvm_exception_is_soft(nr)) {
1939                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940                              vmx->vcpu.arch.event_exit_inst_len);
1941                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942         } else
1943                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1946 }
1947
1948 static bool vmx_rdtscp_supported(void)
1949 {
1950         return cpu_has_vmx_rdtscp();
1951 }
1952
1953 static bool vmx_invpcid_supported(void)
1954 {
1955         return cpu_has_vmx_invpcid() && enable_ept;
1956 }
1957
1958 /*
1959  * Swap MSR entry in host/guest MSR entry array.
1960  */
1961 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1962 {
1963         struct shared_msr_entry tmp;
1964
1965         tmp = vmx->guest_msrs[to];
1966         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967         vmx->guest_msrs[from] = tmp;
1968 }
1969
1970 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971 {
1972         unsigned long *msr_bitmap;
1973
1974         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975                 if (is_long_mode(vcpu))
1976                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977                 else
1978                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979         } else {
1980                 if (is_long_mode(vcpu))
1981                         msr_bitmap = vmx_msr_bitmap_longmode;
1982                 else
1983                         msr_bitmap = vmx_msr_bitmap_legacy;
1984         }
1985
1986         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987 }
1988
1989 /*
1990  * Set up the vmcs to automatically save and restore system
1991  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1992  * mode, as fiddling with msrs is very expensive.
1993  */
1994 static void setup_msrs(struct vcpu_vmx *vmx)
1995 {
1996         int save_nmsrs, index;
1997
1998         save_nmsrs = 0;
1999 #ifdef CONFIG_X86_64
2000         if (is_long_mode(&vmx->vcpu)) {
2001                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2002                 if (index >= 0)
2003                         move_msr_up(vmx, index, save_nmsrs++);
2004                 index = __find_msr_index(vmx, MSR_LSTAR);
2005                 if (index >= 0)
2006                         move_msr_up(vmx, index, save_nmsrs++);
2007                 index = __find_msr_index(vmx, MSR_CSTAR);
2008                 if (index >= 0)
2009                         move_msr_up(vmx, index, save_nmsrs++);
2010                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011                 if (index >= 0 && vmx->rdtscp_enabled)
2012                         move_msr_up(vmx, index, save_nmsrs++);
2013                 /*
2014                  * MSR_STAR is only needed on long mode guests, and only
2015                  * if efer.sce is enabled.
2016                  */
2017                 index = __find_msr_index(vmx, MSR_STAR);
2018                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2019                         move_msr_up(vmx, index, save_nmsrs++);
2020         }
2021 #endif
2022         index = __find_msr_index(vmx, MSR_EFER);
2023         if (index >= 0 && update_transition_efer(vmx, index))
2024                 move_msr_up(vmx, index, save_nmsrs++);
2025
2026         vmx->save_nmsrs = save_nmsrs;
2027
2028         if (cpu_has_vmx_msr_bitmap())
2029                 vmx_set_msr_bitmap(&vmx->vcpu);
2030 }
2031
2032 /*
2033  * reads and returns guest's timestamp counter "register"
2034  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2035  */
2036 static u64 guest_read_tsc(void)
2037 {
2038         u64 host_tsc, tsc_offset;
2039
2040         rdtscll(host_tsc);
2041         tsc_offset = vmcs_read64(TSC_OFFSET);
2042         return host_tsc + tsc_offset;
2043 }
2044
2045 /*
2046  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047  * counter, even if a nested guest (L2) is currently running.
2048  */
2049 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2050 {
2051         u64 tsc_offset;
2052
2053         tsc_offset = is_guest_mode(vcpu) ?
2054                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055                 vmcs_read64(TSC_OFFSET);
2056         return host_tsc + tsc_offset;
2057 }
2058
2059 /*
2060  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2061  * software catchup for faster rates on slower CPUs.
2062  */
2063 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2064 {
2065         if (!scale)
2066                 return;
2067
2068         if (user_tsc_khz > tsc_khz) {
2069                 vcpu->arch.tsc_catchup = 1;
2070                 vcpu->arch.tsc_always_catchup = 1;
2071         } else
2072                 WARN(1, "user requested TSC rate below hardware speed\n");
2073 }
2074
2075 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076 {
2077         return vmcs_read64(TSC_OFFSET);
2078 }
2079
2080 /*
2081  * writes 'offset' into guest's timestamp counter offset register
2082  */
2083 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2084 {
2085         if (is_guest_mode(vcpu)) {
2086                 /*
2087                  * We're here if L1 chose not to trap WRMSR to TSC. According
2088                  * to the spec, this should set L1's TSC; The offset that L1
2089                  * set for L2 remains unchanged, and still needs to be added
2090                  * to the newly set TSC to get L2's TSC.
2091                  */
2092                 struct vmcs12 *vmcs12;
2093                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094                 /* recalculate vmcs02.TSC_OFFSET: */
2095                 vmcs12 = get_vmcs12(vcpu);
2096                 vmcs_write64(TSC_OFFSET, offset +
2097                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098                          vmcs12->tsc_offset : 0));
2099         } else {
2100                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101                                            vmcs_read64(TSC_OFFSET), offset);
2102                 vmcs_write64(TSC_OFFSET, offset);
2103         }
2104 }
2105
2106 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2107 {
2108         u64 offset = vmcs_read64(TSC_OFFSET);
2109
2110         vmcs_write64(TSC_OFFSET, offset + adjustment);
2111         if (is_guest_mode(vcpu)) {
2112                 /* Even when running L2, the adjustment needs to apply to L1 */
2113                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2114         } else
2115                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116                                            offset + adjustment);
2117 }
2118
2119 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120 {
2121         return target_tsc - native_read_tsc();
2122 }
2123
2124 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125 {
2126         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128 }
2129
2130 /*
2131  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133  * all guests if the "nested" module option is off, and can also be disabled
2134  * for a single guest by disabling its VMX cpuid bit.
2135  */
2136 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137 {
2138         return nested && guest_cpuid_has_vmx(vcpu);
2139 }
2140
2141 /*
2142  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143  * returned for the various VMX controls MSRs when nested VMX is enabled.
2144  * The same values should also be used to verify that vmcs12 control fields are
2145  * valid during nested entry from L1 to L2.
2146  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148  * bit in the high half is on if the corresponding bit in the control field
2149  * may be on. See also vmx_control_verify().
2150  * TODO: allow these variables to be modified (downgraded) by module options
2151  * or other means.
2152  */
2153 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2158 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2159 static __init void nested_vmx_setup_ctls_msrs(void)
2160 {
2161         /*
2162          * Note that as a general rule, the high half of the MSRs (bits in
2163          * the control fields which may be 1) should be initialized by the
2164          * intersection of the underlying hardware's MSR (i.e., features which
2165          * can be supported) and the list of features we want to expose -
2166          * because they are known to be properly supported in our code.
2167          * Also, usually, the low half of the MSRs (bits which must be 1) can
2168          * be set to 0, meaning that L1 may turn off any of these bits. The
2169          * reason is that if one of these bits is necessary, it will appear
2170          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2171          * fields of vmcs01 and vmcs02, will turn these bits off - and
2172          * nested_vmx_exit_handled() will not pass related exits to L1.
2173          * These rules have exceptions below.
2174          */
2175
2176         /* pin-based controls */
2177         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2178               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2179         /*
2180          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2181          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2182          */
2183         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2184         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2185                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2186                 PIN_BASED_VMX_PREEMPTION_TIMER;
2187         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2188
2189         /*
2190          * Exit controls
2191          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2192          * 17 must be 1.
2193          */
2194         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2195         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2196 #ifdef CONFIG_X86_64
2197         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2198 #else
2199         nested_vmx_exit_ctls_high = 0;
2200 #endif
2201         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2202
2203         /* entry controls */
2204         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2205                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2206         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2207         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2208         nested_vmx_entry_ctls_high &=
2209                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2210         nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2211
2212         /* cpu-based controls */
2213         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2214                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2215         nested_vmx_procbased_ctls_low = 0;
2216         nested_vmx_procbased_ctls_high &=
2217                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2218                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2219                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2220                 CPU_BASED_CR3_STORE_EXITING |
2221 #ifdef CONFIG_X86_64
2222                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2223 #endif
2224                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2225                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2226                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2227                 CPU_BASED_PAUSE_EXITING |
2228                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2229         /*
2230          * We can allow some features even when not supported by the
2231          * hardware. For example, L1 can specify an MSR bitmap - and we
2232          * can use it to avoid exits to L1 - even when L0 runs L2
2233          * without MSR bitmaps.
2234          */
2235         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2236
2237         /* secondary cpu-based controls */
2238         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2239                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2240         nested_vmx_secondary_ctls_low = 0;
2241         nested_vmx_secondary_ctls_high &=
2242                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2243                 SECONDARY_EXEC_WBINVD_EXITING;
2244
2245         /* miscellaneous data */
2246         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2247         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2248                 VMX_MISC_SAVE_EFER_LMA;
2249         nested_vmx_misc_high = 0;
2250 }
2251
2252 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2253 {
2254         /*
2255          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2256          */
2257         return ((control & high) | low) == control;
2258 }
2259
2260 static inline u64 vmx_control_msr(u32 low, u32 high)
2261 {
2262         return low | ((u64)high << 32);
2263 }
2264
2265 /*
2266  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2267  * also let it use VMX-specific MSRs.
2268  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2269  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2270  * like all other MSRs).
2271  */
2272 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2273 {
2274         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2275                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2276                 /*
2277                  * According to the spec, processors which do not support VMX
2278                  * should throw a #GP(0) when VMX capability MSRs are read.
2279                  */
2280                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2281                 return 1;
2282         }
2283
2284         switch (msr_index) {
2285         case MSR_IA32_FEATURE_CONTROL:
2286                 if (nested_vmx_allowed(vcpu)) {
2287                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2288                         break;
2289                 }
2290                 return 0;
2291         case MSR_IA32_VMX_BASIC:
2292                 /*
2293                  * This MSR reports some information about VMX support. We
2294                  * should return information about the VMX we emulate for the
2295                  * guest, and the VMCS structure we give it - not about the
2296                  * VMX support of the underlying hardware.
2297                  */
2298                 *pdata = VMCS12_REVISION |
2299                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2300                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2301                 break;
2302         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2303         case MSR_IA32_VMX_PINBASED_CTLS:
2304                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2305                                         nested_vmx_pinbased_ctls_high);
2306                 break;
2307         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2308         case MSR_IA32_VMX_PROCBASED_CTLS:
2309                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2310                                         nested_vmx_procbased_ctls_high);
2311                 break;
2312         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2313         case MSR_IA32_VMX_EXIT_CTLS:
2314                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2315                                         nested_vmx_exit_ctls_high);
2316                 break;
2317         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2318         case MSR_IA32_VMX_ENTRY_CTLS:
2319                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2320                                         nested_vmx_entry_ctls_high);
2321                 break;
2322         case MSR_IA32_VMX_MISC:
2323                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2324                                          nested_vmx_misc_high);
2325                 break;
2326         /*
2327          * These MSRs specify bits which the guest must keep fixed (on or off)
2328          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2329          * We picked the standard core2 setting.
2330          */
2331 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2332 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2333         case MSR_IA32_VMX_CR0_FIXED0:
2334                 *pdata = VMXON_CR0_ALWAYSON;
2335                 break;
2336         case MSR_IA32_VMX_CR0_FIXED1:
2337                 *pdata = -1ULL;
2338                 break;
2339         case MSR_IA32_VMX_CR4_FIXED0:
2340                 *pdata = VMXON_CR4_ALWAYSON;
2341                 break;
2342         case MSR_IA32_VMX_CR4_FIXED1:
2343                 *pdata = -1ULL;
2344                 break;
2345         case MSR_IA32_VMX_VMCS_ENUM:
2346                 *pdata = 0x1f;
2347                 break;
2348         case MSR_IA32_VMX_PROCBASED_CTLS2:
2349                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2350                                         nested_vmx_secondary_ctls_high);
2351                 break;
2352         case MSR_IA32_VMX_EPT_VPID_CAP:
2353                 /* Currently, no nested ept or nested vpid */
2354                 *pdata = 0;
2355                 break;
2356         default:
2357                 return 0;
2358         }
2359
2360         return 1;
2361 }
2362
2363 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2364 {
2365         u32 msr_index = msr_info->index;
2366         u64 data = msr_info->data;
2367         bool host_initialized = msr_info->host_initiated;
2368
2369         if (!nested_vmx_allowed(vcpu))
2370                 return 0;
2371
2372         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2373                 if (!host_initialized &&
2374                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2375                                 & FEATURE_CONTROL_LOCKED)
2376                         return 0;
2377                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2378                 return 1;
2379         }
2380
2381         /*
2382          * No need to treat VMX capability MSRs specially: If we don't handle
2383          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2384          */
2385         return 0;
2386 }
2387
2388 /*
2389  * Reads an msr value (of 'msr_index') into 'pdata'.
2390  * Returns 0 on success, non-0 otherwise.
2391  * Assumes vcpu_load() was already called.
2392  */
2393 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2394 {
2395         u64 data;
2396         struct shared_msr_entry *msr;
2397
2398         if (!pdata) {
2399                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2400                 return -EINVAL;
2401         }
2402
2403         switch (msr_index) {
2404 #ifdef CONFIG_X86_64
2405         case MSR_FS_BASE:
2406                 data = vmcs_readl(GUEST_FS_BASE);
2407                 break;
2408         case MSR_GS_BASE:
2409                 data = vmcs_readl(GUEST_GS_BASE);
2410                 break;
2411         case MSR_KERNEL_GS_BASE:
2412                 vmx_load_host_state(to_vmx(vcpu));
2413                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2414                 break;
2415 #endif
2416         case MSR_EFER:
2417                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2418         case MSR_IA32_TSC:
2419                 data = guest_read_tsc();
2420                 break;
2421         case MSR_IA32_SYSENTER_CS:
2422                 data = vmcs_read32(GUEST_SYSENTER_CS);
2423                 break;
2424         case MSR_IA32_SYSENTER_EIP:
2425                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2426                 break;
2427         case MSR_IA32_SYSENTER_ESP:
2428                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2429                 break;
2430         case MSR_TSC_AUX:
2431                 if (!to_vmx(vcpu)->rdtscp_enabled)
2432                         return 1;
2433                 /* Otherwise falls through */
2434         default:
2435                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2436                         return 0;
2437                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2438                 if (msr) {
2439                         data = msr->data;
2440                         break;
2441                 }
2442                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2443         }
2444
2445         *pdata = data;
2446         return 0;
2447 }
2448
2449 /*
2450  * Writes msr value into into the appropriate "register".
2451  * Returns 0 on success, non-0 otherwise.
2452  * Assumes vcpu_load() was already called.
2453  */
2454 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2455 {
2456         struct vcpu_vmx *vmx = to_vmx(vcpu);
2457         struct shared_msr_entry *msr;
2458         int ret = 0;
2459         u32 msr_index = msr_info->index;
2460         u64 data = msr_info->data;
2461
2462         switch (msr_index) {
2463         case MSR_EFER:
2464                 ret = kvm_set_msr_common(vcpu, msr_info);
2465                 break;
2466 #ifdef CONFIG_X86_64
2467         case MSR_FS_BASE:
2468                 vmx_segment_cache_clear(vmx);
2469                 vmcs_writel(GUEST_FS_BASE, data);
2470                 break;
2471         case MSR_GS_BASE:
2472                 vmx_segment_cache_clear(vmx);
2473                 vmcs_writel(GUEST_GS_BASE, data);
2474                 break;
2475         case MSR_KERNEL_GS_BASE:
2476                 vmx_load_host_state(vmx);
2477                 vmx->msr_guest_kernel_gs_base = data;
2478                 break;
2479 #endif
2480         case MSR_IA32_SYSENTER_CS:
2481                 vmcs_write32(GUEST_SYSENTER_CS, data);
2482                 break;
2483         case MSR_IA32_SYSENTER_EIP:
2484                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2485                 break;
2486         case MSR_IA32_SYSENTER_ESP:
2487                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2488                 break;
2489         case MSR_IA32_TSC:
2490                 kvm_write_tsc(vcpu, msr_info);
2491                 break;
2492         case MSR_IA32_CR_PAT:
2493                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2494                         vmcs_write64(GUEST_IA32_PAT, data);
2495                         vcpu->arch.pat = data;
2496                         break;
2497                 }
2498                 ret = kvm_set_msr_common(vcpu, msr_info);
2499                 break;
2500         case MSR_IA32_TSC_ADJUST:
2501                 ret = kvm_set_msr_common(vcpu, msr_info);
2502                 break;
2503         case MSR_TSC_AUX:
2504                 if (!vmx->rdtscp_enabled)
2505                         return 1;
2506                 /* Check reserved bit, higher 32 bits should be zero */
2507                 if ((data >> 32) != 0)
2508                         return 1;
2509                 /* Otherwise falls through */
2510         default:
2511                 if (vmx_set_vmx_msr(vcpu, msr_info))
2512                         break;
2513                 msr = find_msr_entry(vmx, msr_index);
2514                 if (msr) {
2515                         msr->data = data;
2516                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2517                                 preempt_disable();
2518                                 kvm_set_shared_msr(msr->index, msr->data,
2519                                                    msr->mask);
2520                                 preempt_enable();
2521                         }
2522                         break;
2523                 }
2524                 ret = kvm_set_msr_common(vcpu, msr_info);
2525         }
2526
2527         return ret;
2528 }
2529
2530 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2531 {
2532         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2533         switch (reg) {
2534         case VCPU_REGS_RSP:
2535                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2536                 break;
2537         case VCPU_REGS_RIP:
2538                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2539                 break;
2540         case VCPU_EXREG_PDPTR:
2541                 if (enable_ept)
2542                         ept_save_pdptrs(vcpu);
2543                 break;
2544         default:
2545                 break;
2546         }
2547 }
2548
2549 static __init int cpu_has_kvm_support(void)
2550 {
2551         return cpu_has_vmx();
2552 }
2553
2554 static __init int vmx_disabled_by_bios(void)
2555 {
2556         u64 msr;
2557
2558         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2559         if (msr & FEATURE_CONTROL_LOCKED) {
2560                 /* launched w/ TXT and VMX disabled */
2561                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2562                         && tboot_enabled())
2563                         return 1;
2564                 /* launched w/o TXT and VMX only enabled w/ TXT */
2565                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2566                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2567                         && !tboot_enabled()) {
2568                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2569                                 "activate TXT before enabling KVM\n");
2570                         return 1;
2571                 }
2572                 /* launched w/o TXT and VMX disabled */
2573                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2574                         && !tboot_enabled())
2575                         return 1;
2576         }
2577
2578         return 0;
2579 }
2580
2581 static void kvm_cpu_vmxon(u64 addr)
2582 {
2583         asm volatile (ASM_VMX_VMXON_RAX
2584                         : : "a"(&addr), "m"(addr)
2585                         : "memory", "cc");
2586 }
2587
2588 static int hardware_enable(void *garbage)
2589 {
2590         int cpu = raw_smp_processor_id();
2591         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2592         u64 old, test_bits;
2593
2594         if (read_cr4() & X86_CR4_VMXE)
2595                 return -EBUSY;
2596
2597         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2598
2599         /*
2600          * Now we can enable the vmclear operation in kdump
2601          * since the loaded_vmcss_on_cpu list on this cpu
2602          * has been initialized.
2603          *
2604          * Though the cpu is not in VMX operation now, there
2605          * is no problem to enable the vmclear operation
2606          * for the loaded_vmcss_on_cpu list is empty!
2607          */
2608         crash_enable_local_vmclear(cpu);
2609
2610         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2611
2612         test_bits = FEATURE_CONTROL_LOCKED;
2613         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2614         if (tboot_enabled())
2615                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2616
2617         if ((old & test_bits) != test_bits) {
2618                 /* enable and lock */
2619                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2620         }
2621         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2622
2623         if (vmm_exclusive) {
2624                 kvm_cpu_vmxon(phys_addr);
2625                 ept_sync_global();
2626         }
2627
2628         native_store_gdt(&__get_cpu_var(host_gdt));
2629
2630         return 0;
2631 }
2632
2633 static void vmclear_local_loaded_vmcss(void)
2634 {
2635         int cpu = raw_smp_processor_id();
2636         struct loaded_vmcs *v, *n;
2637
2638         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2639                                  loaded_vmcss_on_cpu_link)
2640                 __loaded_vmcs_clear(v);
2641 }
2642
2643
2644 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2645  * tricks.
2646  */
2647 static void kvm_cpu_vmxoff(void)
2648 {
2649         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2650 }
2651
2652 static void hardware_disable(void *garbage)
2653 {
2654         if (vmm_exclusive) {
2655                 vmclear_local_loaded_vmcss();
2656                 kvm_cpu_vmxoff();
2657         }
2658         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2659 }
2660
2661 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2662                                       u32 msr, u32 *result)
2663 {
2664         u32 vmx_msr_low, vmx_msr_high;
2665         u32 ctl = ctl_min | ctl_opt;
2666
2667         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2668
2669         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2670         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2671
2672         /* Ensure minimum (required) set of control bits are supported. */
2673         if (ctl_min & ~ctl)
2674                 return -EIO;
2675
2676         *result = ctl;
2677         return 0;
2678 }
2679
2680 static __init bool allow_1_setting(u32 msr, u32 ctl)
2681 {
2682         u32 vmx_msr_low, vmx_msr_high;
2683
2684         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2685         return vmx_msr_high & ctl;
2686 }
2687
2688 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2689 {
2690         u32 vmx_msr_low, vmx_msr_high;
2691         u32 min, opt, min2, opt2;
2692         u32 _pin_based_exec_control = 0;
2693         u32 _cpu_based_exec_control = 0;
2694         u32 _cpu_based_2nd_exec_control = 0;
2695         u32 _vmexit_control = 0;
2696         u32 _vmentry_control = 0;
2697
2698         min = CPU_BASED_HLT_EXITING |
2699 #ifdef CONFIG_X86_64
2700               CPU_BASED_CR8_LOAD_EXITING |
2701               CPU_BASED_CR8_STORE_EXITING |
2702 #endif
2703               CPU_BASED_CR3_LOAD_EXITING |
2704               CPU_BASED_CR3_STORE_EXITING |
2705               CPU_BASED_USE_IO_BITMAPS |
2706               CPU_BASED_MOV_DR_EXITING |
2707               CPU_BASED_USE_TSC_OFFSETING |
2708               CPU_BASED_MWAIT_EXITING |
2709               CPU_BASED_MONITOR_EXITING |
2710               CPU_BASED_INVLPG_EXITING |
2711               CPU_BASED_RDPMC_EXITING;
2712
2713         opt = CPU_BASED_TPR_SHADOW |
2714               CPU_BASED_USE_MSR_BITMAPS |
2715               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2716         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2717                                 &_cpu_based_exec_control) < 0)
2718                 return -EIO;
2719 #ifdef CONFIG_X86_64
2720         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2721                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2722                                            ~CPU_BASED_CR8_STORE_EXITING;
2723 #endif
2724         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2725                 min2 = 0;
2726                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2727                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2728                         SECONDARY_EXEC_WBINVD_EXITING |
2729                         SECONDARY_EXEC_ENABLE_VPID |
2730                         SECONDARY_EXEC_ENABLE_EPT |
2731                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2732                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2733                         SECONDARY_EXEC_RDTSCP |
2734                         SECONDARY_EXEC_ENABLE_INVPCID |
2735                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2736                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2737                         SECONDARY_EXEC_SHADOW_VMCS;
2738                 if (adjust_vmx_controls(min2, opt2,
2739                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2740                                         &_cpu_based_2nd_exec_control) < 0)
2741                         return -EIO;
2742         }
2743 #ifndef CONFIG_X86_64
2744         if (!(_cpu_based_2nd_exec_control &
2745                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2746                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2747 #endif
2748
2749         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2750                 _cpu_based_2nd_exec_control &= ~(
2751                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2752                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2753                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2754
2755         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2756                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2757                    enabled */
2758                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2759                                              CPU_BASED_CR3_STORE_EXITING |
2760                                              CPU_BASED_INVLPG_EXITING);
2761                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2762                       vmx_capability.ept, vmx_capability.vpid);
2763         }
2764
2765         min = 0;
2766 #ifdef CONFIG_X86_64
2767         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2768 #endif
2769         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2770                 VM_EXIT_ACK_INTR_ON_EXIT;
2771         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2772                                 &_vmexit_control) < 0)
2773                 return -EIO;
2774
2775         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2776         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2777         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2778                                 &_pin_based_exec_control) < 0)
2779                 return -EIO;
2780
2781         if (!(_cpu_based_2nd_exec_control &
2782                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2783                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2784                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2785
2786         min = 0;
2787         opt = VM_ENTRY_LOAD_IA32_PAT;
2788         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2789                                 &_vmentry_control) < 0)
2790                 return -EIO;
2791
2792         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2793
2794         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2795         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2796                 return -EIO;
2797
2798 #ifdef CONFIG_X86_64
2799         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2800         if (vmx_msr_high & (1u<<16))
2801                 return -EIO;
2802 #endif
2803
2804         /* Require Write-Back (WB) memory type for VMCS accesses. */
2805         if (((vmx_msr_high >> 18) & 15) != 6)
2806                 return -EIO;
2807
2808         vmcs_conf->size = vmx_msr_high & 0x1fff;
2809         vmcs_conf->order = get_order(vmcs_config.size);
2810         vmcs_conf->revision_id = vmx_msr_low;
2811
2812         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2813         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2814         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2815         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2816         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2817
2818         cpu_has_load_ia32_efer =
2819                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2820                                 VM_ENTRY_LOAD_IA32_EFER)
2821                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2822                                    VM_EXIT_LOAD_IA32_EFER);
2823
2824         cpu_has_load_perf_global_ctrl =
2825                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2826                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2827                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2828                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2829
2830         /*
2831          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2832          * but due to arrata below it can't be used. Workaround is to use
2833          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2834          *
2835          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2836          *
2837          * AAK155             (model 26)
2838          * AAP115             (model 30)
2839          * AAT100             (model 37)
2840          * BC86,AAY89,BD102   (model 44)
2841          * BA97               (model 46)
2842          *
2843          */
2844         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2845                 switch (boot_cpu_data.x86_model) {
2846                 case 26:
2847                 case 30:
2848                 case 37:
2849                 case 44:
2850                 case 46:
2851                         cpu_has_load_perf_global_ctrl = false;
2852                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2853                                         "does not work properly. Using workaround\n");
2854                         break;
2855                 default:
2856                         break;
2857                 }
2858         }
2859
2860         return 0;
2861 }
2862
2863 static struct vmcs *alloc_vmcs_cpu(int cpu)
2864 {
2865         int node = cpu_to_node(cpu);
2866         struct page *pages;
2867         struct vmcs *vmcs;
2868
2869         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2870         if (!pages)
2871                 return NULL;
2872         vmcs = page_address(pages);
2873         memset(vmcs, 0, vmcs_config.size);
2874         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2875         return vmcs;
2876 }
2877
2878 static struct vmcs *alloc_vmcs(void)
2879 {
2880         return alloc_vmcs_cpu(raw_smp_processor_id());
2881 }
2882
2883 static void free_vmcs(struct vmcs *vmcs)
2884 {
2885         free_pages((unsigned long)vmcs, vmcs_config.order);
2886 }
2887
2888 /*
2889  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2890  */
2891 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2892 {
2893         if (!loaded_vmcs->vmcs)
2894                 return;
2895         loaded_vmcs_clear(loaded_vmcs);
2896         free_vmcs(loaded_vmcs->vmcs);
2897         loaded_vmcs->vmcs = NULL;
2898 }
2899
2900 static void free_kvm_area(void)
2901 {
2902         int cpu;
2903
2904         for_each_possible_cpu(cpu) {
2905                 free_vmcs(per_cpu(vmxarea, cpu));
2906                 per_cpu(vmxarea, cpu) = NULL;
2907         }
2908 }
2909
2910 static __init int alloc_kvm_area(void)
2911 {
2912         int cpu;
2913
2914         for_each_possible_cpu(cpu) {
2915                 struct vmcs *vmcs;
2916
2917                 vmcs = alloc_vmcs_cpu(cpu);
2918                 if (!vmcs) {
2919                         free_kvm_area();
2920                         return -ENOMEM;
2921                 }
2922
2923                 per_cpu(vmxarea, cpu) = vmcs;
2924         }
2925         return 0;
2926 }
2927
2928 static __init int hardware_setup(void)
2929 {
2930         if (setup_vmcs_config(&vmcs_config) < 0)
2931                 return -EIO;
2932
2933         if (boot_cpu_has(X86_FEATURE_NX))
2934                 kvm_enable_efer_bits(EFER_NX);
2935
2936         if (!cpu_has_vmx_vpid())
2937                 enable_vpid = 0;
2938         if (!cpu_has_vmx_shadow_vmcs())
2939                 enable_shadow_vmcs = 0;
2940
2941         if (!cpu_has_vmx_ept() ||
2942             !cpu_has_vmx_ept_4levels()) {
2943                 enable_ept = 0;
2944                 enable_unrestricted_guest = 0;
2945                 enable_ept_ad_bits = 0;
2946         }
2947
2948         if (!cpu_has_vmx_ept_ad_bits())
2949                 enable_ept_ad_bits = 0;
2950
2951         if (!cpu_has_vmx_unrestricted_guest())
2952                 enable_unrestricted_guest = 0;
2953
2954         if (!cpu_has_vmx_flexpriority())
2955                 flexpriority_enabled = 0;
2956
2957         if (!cpu_has_vmx_tpr_shadow())
2958                 kvm_x86_ops->update_cr8_intercept = NULL;
2959
2960         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2961                 kvm_disable_largepages();
2962
2963         if (!cpu_has_vmx_ple())
2964                 ple_gap = 0;
2965
2966         if (!cpu_has_vmx_apicv())
2967                 enable_apicv = 0;
2968
2969         if (enable_apicv)
2970                 kvm_x86_ops->update_cr8_intercept = NULL;
2971         else {
2972                 kvm_x86_ops->hwapic_irr_update = NULL;
2973                 kvm_x86_ops->deliver_posted_interrupt = NULL;
2974                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2975         }
2976
2977         if (nested)
2978                 nested_vmx_setup_ctls_msrs();
2979
2980         return alloc_kvm_area();
2981 }
2982
2983 static __exit void hardware_unsetup(void)
2984 {
2985         free_kvm_area();
2986 }
2987
2988 static bool emulation_required(struct kvm_vcpu *vcpu)
2989 {
2990         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2991 }
2992
2993 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2994                 struct kvm_segment *save)
2995 {
2996         if (!emulate_invalid_guest_state) {
2997                 /*
2998                  * CS and SS RPL should be equal during guest entry according
2999                  * to VMX spec, but in reality it is not always so. Since vcpu
3000                  * is in the middle of the transition from real mode to
3001                  * protected mode it is safe to assume that RPL 0 is a good
3002                  * default value.
3003                  */
3004                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3005                         save->selector &= ~SELECTOR_RPL_MASK;
3006                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3007                 save->s = 1;
3008         }
3009         vmx_set_segment(vcpu, save, seg);
3010 }
3011
3012 static void enter_pmode(struct kvm_vcpu *vcpu)
3013 {
3014         unsigned long flags;
3015         struct vcpu_vmx *vmx = to_vmx(vcpu);
3016
3017         /*
3018          * Update real mode segment cache. It may be not up-to-date if sement
3019          * register was written while vcpu was in a guest mode.
3020          */
3021         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3027
3028         vmx->rmode.vm86_active = 0;
3029
3030         vmx_segment_cache_clear(vmx);
3031
3032         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3033
3034         flags = vmcs_readl(GUEST_RFLAGS);
3035         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3036         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3037         vmcs_writel(GUEST_RFLAGS, flags);
3038
3039         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3040                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3041
3042         update_exception_bitmap(vcpu);
3043
3044         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3045         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3046         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3047         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3048         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3049         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3050
3051         /* CPL is always 0 when CPU enters protected mode */
3052         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3053         vmx->cpl = 0;
3054 }
3055
3056 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3057 {
3058         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3059         struct kvm_segment var = *save;
3060
3061         var.dpl = 0x3;
3062         if (seg == VCPU_SREG_CS)
3063                 var.type = 0x3;
3064
3065         if (!emulate_invalid_guest_state) {
3066                 var.selector = var.base >> 4;
3067                 var.base = var.base & 0xffff0;
3068                 var.limit = 0xffff;
3069                 var.g = 0;
3070                 var.db = 0;
3071                 var.present = 1;
3072                 var.s = 1;
3073                 var.l = 0;
3074                 var.unusable = 0;
3075                 var.type = 0x3;
3076                 var.avl = 0;
3077                 if (save->base & 0xf)
3078                         printk_once(KERN_WARNING "kvm: segment base is not "
3079                                         "paragraph aligned when entering "
3080                                         "protected mode (seg=%d)", seg);
3081         }
3082
3083         vmcs_write16(sf->selector, var.selector);
3084         vmcs_write32(sf->base, var.base);
3085         vmcs_write32(sf->limit, var.limit);
3086         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3087 }
3088
3089 static void enter_rmode(struct kvm_vcpu *vcpu)
3090 {
3091         unsigned long flags;
3092         struct vcpu_vmx *vmx = to_vmx(vcpu);
3093
3094         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3095         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3096         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3097         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3098         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3099         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3100         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3101
3102         vmx->rmode.vm86_active = 1;
3103
3104         /*
3105          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3106          * vcpu. Warn the user that an update is overdue.
3107          */
3108         if (!vcpu->kvm->arch.tss_addr)
3109                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3110                              "called before entering vcpu\n");
3111
3112         vmx_segment_cache_clear(vmx);
3113
3114         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3115         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3116         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3117
3118         flags = vmcs_readl(GUEST_RFLAGS);
3119         vmx->rmode.save_rflags = flags;
3120
3121         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3122
3123         vmcs_writel(GUEST_RFLAGS, flags);
3124         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3125         update_exception_bitmap(vcpu);
3126
3127         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3128         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3129         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3130         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3131         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3132         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3133
3134         kvm_mmu_reset_context(vcpu);
3135 }
3136
3137 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3138 {
3139         struct vcpu_vmx *vmx = to_vmx(vcpu);
3140         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3141
3142         if (!msr)
3143                 return;
3144
3145         /*
3146          * Force kernel_gs_base reloading before EFER changes, as control
3147          * of this msr depends on is_long_mode().
3148          */
3149         vmx_load_host_state(to_vmx(vcpu));
3150         vcpu->arch.efer = efer;
3151         if (efer & EFER_LMA) {
3152                 vmcs_write32(VM_ENTRY_CONTROLS,
3153                              vmcs_read32(VM_ENTRY_CONTROLS) |
3154                              VM_ENTRY_IA32E_MODE);
3155                 msr->data = efer;
3156         } else {
3157                 vmcs_write32(VM_ENTRY_CONTROLS,
3158                              vmcs_read32(VM_ENTRY_CONTROLS) &
3159                              ~VM_ENTRY_IA32E_MODE);
3160
3161                 msr->data = efer & ~EFER_LME;
3162         }
3163         setup_msrs(vmx);
3164 }
3165
3166 #ifdef CONFIG_X86_64
3167
3168 static void enter_lmode(struct kvm_vcpu *vcpu)
3169 {
3170         u32 guest_tr_ar;
3171
3172         vmx_segment_cache_clear(to_vmx(vcpu));
3173
3174         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3175         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3176                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3177                                      __func__);
3178                 vmcs_write32(GUEST_TR_AR_BYTES,
3179                              (guest_tr_ar & ~AR_TYPE_MASK)
3180                              | AR_TYPE_BUSY_64_TSS);
3181         }
3182         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3183 }
3184
3185 static void exit_lmode(struct kvm_vcpu *vcpu)
3186 {
3187         vmcs_write32(VM_ENTRY_CONTROLS,
3188                      vmcs_read32(VM_ENTRY_CONTROLS)
3189                      & ~VM_ENTRY_IA32E_MODE);
3190         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3191 }
3192
3193 #endif
3194
3195 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3196 {
3197         vpid_sync_context(to_vmx(vcpu));
3198         if (enable_ept) {
3199                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3200                         return;
3201                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3202         }
3203 }
3204
3205 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3206 {
3207         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3208
3209         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3210         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3211 }
3212
3213 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3214 {
3215         if (enable_ept && is_paging(vcpu))
3216                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3217         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3218 }
3219
3220 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3221 {
3222         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3223
3224         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3225         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3226 }
3227
3228 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3229 {
3230         if (!test_bit(VCPU_EXREG_PDPTR,
3231                       (unsigned long *)&vcpu->arch.regs_dirty))
3232                 return;
3233
3234         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3235                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3236                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3237                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3238                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3239         }
3240 }
3241
3242 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3243 {
3244         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3245                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3246                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3247                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3248                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3249         }
3250
3251         __set_bit(VCPU_EXREG_PDPTR,
3252                   (unsigned long *)&vcpu->arch.regs_avail);
3253         __set_bit(VCPU_EXREG_PDPTR,
3254                   (unsigned long *)&vcpu->arch.regs_dirty);
3255 }
3256
3257 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3258
3259 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3260                                         unsigned long cr0,
3261                                         struct kvm_vcpu *vcpu)
3262 {
3263         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3264                 vmx_decache_cr3(vcpu);
3265         if (!(cr0 & X86_CR0_PG)) {
3266                 /* From paging/starting to nonpaging */
3267                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3268                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3269                              (CPU_BASED_CR3_LOAD_EXITING |
3270                               CPU_BASED_CR3_STORE_EXITING));
3271                 vcpu->arch.cr0 = cr0;
3272                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3273         } else if (!is_paging(vcpu)) {
3274                 /* From nonpaging to paging */
3275                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3276                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3277                              ~(CPU_BASED_CR3_LOAD_EXITING |
3278                                CPU_BASED_CR3_STORE_EXITING));
3279                 vcpu->arch.cr0 = cr0;
3280                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3281         }
3282
3283         if (!(cr0 & X86_CR0_WP))
3284                 *hw_cr0 &= ~X86_CR0_WP;
3285 }
3286
3287 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3288 {
3289         struct vcpu_vmx *vmx = to_vmx(vcpu);
3290         unsigned long hw_cr0;
3291
3292         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3293         if (enable_unrestricted_guest)
3294                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3295         else {
3296                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3297
3298                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3299                         enter_pmode(vcpu);
3300
3301                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3302                         enter_rmode(vcpu);
3303         }
3304
3305 #ifdef CONFIG_X86_64
3306         if (vcpu->arch.efer & EFER_LME) {
3307                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3308                         enter_lmode(vcpu);
3309                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3310                         exit_lmode(vcpu);
3311         }
3312 #endif
3313
3314         if (enable_ept)
3315                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3316
3317         if (!vcpu->fpu_active)
3318                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3319
3320         vmcs_writel(CR0_READ_SHADOW, cr0);
3321         vmcs_writel(GUEST_CR0, hw_cr0);
3322         vcpu->arch.cr0 = cr0;
3323
3324         /* depends on vcpu->arch.cr0 to be set to a new value */
3325         vmx->emulation_required = emulation_required(vcpu);
3326 }
3327
3328 static u64 construct_eptp(unsigned long root_hpa)
3329 {
3330         u64 eptp;
3331
3332         /* TODO write the value reading from MSR */
3333         eptp = VMX_EPT_DEFAULT_MT |
3334                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3335         if (enable_ept_ad_bits)
3336                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3337         eptp |= (root_hpa & PAGE_MASK);
3338
3339         return eptp;
3340 }
3341
3342 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3343 {
3344         unsigned long guest_cr3;
3345         u64 eptp;
3346
3347         guest_cr3 = cr3;
3348         if (enable_ept) {
3349                 eptp = construct_eptp(cr3);
3350                 vmcs_write64(EPT_POINTER, eptp);
3351                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3352                         vcpu->kvm->arch.ept_identity_map_addr;
3353                 ept_load_pdptrs(vcpu);
3354         }
3355
3356         vmx_flush_tlb(vcpu);
3357         vmcs_writel(GUEST_CR3, guest_cr3);
3358 }
3359
3360 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3361 {
3362         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3363                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3364
3365         if (cr4 & X86_CR4_VMXE) {
3366                 /*
3367                  * To use VMXON (and later other VMX instructions), a guest
3368                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3369                  * So basically the check on whether to allow nested VMX
3370                  * is here.
3371                  */
3372                 if (!nested_vmx_allowed(vcpu))
3373                         return 1;
3374         }
3375         if (to_vmx(vcpu)->nested.vmxon &&
3376             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3377                 return 1;
3378
3379         vcpu->arch.cr4 = cr4;
3380         if (enable_ept) {
3381                 if (!is_paging(vcpu)) {
3382                         hw_cr4 &= ~X86_CR4_PAE;
3383                         hw_cr4 |= X86_CR4_PSE;
3384                         /*
3385                          * SMEP is disabled if CPU is in non-paging mode in
3386                          * hardware. However KVM always uses paging mode to
3387                          * emulate guest non-paging mode with TDP.
3388                          * To emulate this behavior, SMEP needs to be manually
3389                          * disabled when guest switches to non-paging mode.
3390                          */
3391                         hw_cr4 &= ~X86_CR4_SMEP;
3392                 } else if (!(cr4 & X86_CR4_PAE)) {
3393                         hw_cr4 &= ~X86_CR4_PAE;
3394                 }
3395         }
3396
3397         vmcs_writel(CR4_READ_SHADOW, cr4);
3398         vmcs_writel(GUEST_CR4, hw_cr4);
3399         return 0;
3400 }
3401
3402 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3403                             struct kvm_segment *var, int seg)
3404 {
3405         struct vcpu_vmx *vmx = to_vmx(vcpu);
3406         u32 ar;
3407
3408         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3409                 *var = vmx->rmode.segs[seg];
3410                 if (seg == VCPU_SREG_TR
3411                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3412                         return;
3413                 var->base = vmx_read_guest_seg_base(vmx, seg);
3414                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3415                 return;
3416         }
3417         var->base = vmx_read_guest_seg_base(vmx, seg);
3418         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3419         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3420         ar = vmx_read_guest_seg_ar(vmx, seg);
3421         var->unusable = (ar >> 16) & 1;
3422         var->type = ar & 15;
3423         var->s = (ar >> 4) & 1;
3424         var->dpl = (ar >> 5) & 3;
3425         /*
3426          * Some userspaces do not preserve unusable property. Since usable
3427          * segment has to be present according to VMX spec we can use present
3428          * property to amend userspace bug by making unusable segment always
3429          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3430          * segment as unusable.
3431          */
3432         var->present = !var->unusable;
3433         var->avl = (ar >> 12) & 1;
3434         var->l = (ar >> 13) & 1;
3435         var->db = (ar >> 14) & 1;
3436         var->g = (ar >> 15) & 1;
3437 }
3438
3439 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3440 {
3441         struct kvm_segment s;
3442
3443         if (to_vmx(vcpu)->rmode.vm86_active) {
3444                 vmx_get_segment(vcpu, &s, seg);
3445                 return s.base;
3446         }
3447         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3448 }
3449
3450 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3451 {
3452         struct vcpu_vmx *vmx = to_vmx(vcpu);
3453
3454         if (!is_protmode(vcpu))
3455                 return 0;
3456
3457         if (!is_long_mode(vcpu)
3458             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3459                 return 3;
3460
3461         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3462                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3463                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3464         }
3465
3466         return vmx->cpl;
3467 }
3468
3469
3470 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3471 {
3472         u32 ar;
3473
3474         if (var->unusable || !var->present)
3475                 ar = 1 << 16;
3476         else {
3477                 ar = var->type & 15;
3478                 ar |= (var->s & 1) << 4;
3479                 ar |= (var->dpl & 3) << 5;
3480                 ar |= (var->present & 1) << 7;
3481                 ar |= (var->avl & 1) << 12;
3482                 ar |= (var->l & 1) << 13;
3483                 ar |= (var->db & 1) << 14;
3484                 ar |= (var->g & 1) << 15;
3485         }
3486
3487         return ar;
3488 }
3489
3490 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3491                             struct kvm_segment *var, int seg)
3492 {
3493         struct vcpu_vmx *vmx = to_vmx(vcpu);
3494         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3495
3496         vmx_segment_cache_clear(vmx);
3497         if (seg == VCPU_SREG_CS)
3498                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3499
3500         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3501                 vmx->rmode.segs[seg] = *var;
3502                 if (seg == VCPU_SREG_TR)
3503                         vmcs_write16(sf->selector, var->selector);
3504                 else if (var->s)
3505                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3506                 goto out;
3507         }
3508
3509         vmcs_writel(sf->base, var->base);
3510         vmcs_write32(sf->limit, var->limit);
3511         vmcs_write16(sf->selector, var->selector);
3512
3513         /*
3514          *   Fix the "Accessed" bit in AR field of segment registers for older
3515          * qemu binaries.
3516          *   IA32 arch specifies that at the time of processor reset the
3517          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3518          * is setting it to 0 in the userland code. This causes invalid guest
3519          * state vmexit when "unrestricted guest" mode is turned on.
3520          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3521          * tree. Newer qemu binaries with that qemu fix would not need this
3522          * kvm hack.
3523          */
3524         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3525                 var->type |= 0x1; /* Accessed */
3526
3527         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3528
3529 out:
3530         vmx->emulation_required |= emulation_required(vcpu);
3531 }
3532
3533 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3534 {
3535         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3536
3537         *db = (ar >> 14) & 1;
3538         *l = (ar >> 13) & 1;
3539 }
3540
3541 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3542 {
3543         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3544         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3545 }
3546
3547 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3548 {
3549         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3550         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3551 }
3552
3553 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3554 {
3555         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3556         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3557 }
3558
3559 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3560 {
3561         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3562         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3563 }
3564
3565 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3566 {
3567         struct kvm_segment var;
3568         u32 ar;
3569
3570         vmx_get_segment(vcpu, &var, seg);
3571         var.dpl = 0x3;
3572         if (seg == VCPU_SREG_CS)
3573                 var.type = 0x3;
3574         ar = vmx_segment_access_rights(&var);
3575
3576         if (var.base != (var.selector << 4))
3577                 return false;
3578         if (var.limit != 0xffff)
3579                 return false;
3580         if (ar != 0xf3)
3581                 return false;
3582
3583         return true;
3584 }
3585
3586 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3587 {
3588         struct kvm_segment cs;
3589         unsigned int cs_rpl;
3590
3591         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3592         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3593
3594         if (cs.unusable)
3595                 return false;
3596         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3597                 return false;
3598         if (!cs.s)
3599                 return false;
3600         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3601                 if (cs.dpl > cs_rpl)
3602                         return false;
3603         } else {
3604                 if (cs.dpl != cs_rpl)
3605                         return false;
3606         }
3607         if (!cs.present)
3608                 return false;
3609
3610         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3611         return true;
3612 }
3613
3614 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3615 {
3616         struct kvm_segment ss;
3617         unsigned int ss_rpl;
3618
3619         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3620         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3621
3622         if (ss.unusable)
3623                 return true;
3624         if (ss.type != 3 && ss.type != 7)
3625                 return false;
3626         if (!ss.s)
3627                 return false;
3628         if (ss.dpl != ss_rpl) /* DPL != RPL */
3629                 return false;
3630         if (!ss.present)
3631                 return false;
3632
3633         return true;
3634 }
3635
3636 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3637 {
3638         struct kvm_segment var;
3639         unsigned int rpl;
3640
3641         vmx_get_segment(vcpu, &var, seg);
3642         rpl = var.selector & SELECTOR_RPL_MASK;
3643
3644         if (var.unusable)
3645                 return true;
3646         if (!var.s)
3647                 return false;
3648         if (!var.present)
3649                 return false;
3650         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3651                 if (var.dpl < rpl) /* DPL < RPL */
3652                         return false;
3653         }
3654
3655         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3656          * rights flags
3657          */
3658         return true;
3659 }
3660
3661 static bool tr_valid(struct kvm_vcpu *vcpu)
3662 {
3663         struct kvm_segment tr;
3664
3665         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3666
3667         if (tr.unusable)
3668                 return false;
3669         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3670                 return false;
3671         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3672                 return false;
3673         if (!tr.present)
3674                 return false;
3675
3676         return true;
3677 }
3678
3679 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3680 {
3681         struct kvm_segment ldtr;
3682
3683         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3684
3685         if (ldtr.unusable)
3686                 return true;
3687         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3688                 return false;
3689         if (ldtr.type != 2)
3690                 return false;
3691         if (!ldtr.present)
3692                 return false;
3693
3694         return true;
3695 }
3696
3697 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3698 {
3699         struct kvm_segment cs, ss;
3700
3701         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3702         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3703
3704         return ((cs.selector & SELECTOR_RPL_MASK) ==
3705                  (ss.selector & SELECTOR_RPL_MASK));
3706 }
3707
3708 /*
3709  * Check if guest state is valid. Returns true if valid, false if
3710  * not.
3711  * We assume that registers are always usable
3712  */
3713 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3714 {
3715         if (enable_unrestricted_guest)
3716                 return true;
3717
3718         /* real mode guest state checks */
3719         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3720                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3721                         return false;
3722                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3723                         return false;
3724                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3725                         return false;
3726                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3727                         return false;
3728                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3729                         return false;
3730                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3731                         return false;
3732         } else {
3733         /* protected mode guest state checks */
3734                 if (!cs_ss_rpl_check(vcpu))
3735                         return false;
3736                 if (!code_segment_valid(vcpu))
3737                         return false;
3738                 if (!stack_segment_valid(vcpu))
3739                         return false;
3740                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3741                         return false;
3742                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3743                         return false;
3744                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3745                         return false;
3746                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3747                         return false;
3748                 if (!tr_valid(vcpu))
3749                         return false;
3750                 if (!ldtr_valid(vcpu))
3751                         return false;
3752         }
3753         /* TODO:
3754          * - Add checks on RIP
3755          * - Add checks on RFLAGS
3756          */
3757
3758         return true;
3759 }
3760
3761 static int init_rmode_tss(struct kvm *kvm)
3762 {
3763         gfn_t fn;
3764         u16 data = 0;
3765         int r, idx, ret = 0;
3766
3767         idx = srcu_read_lock(&kvm->srcu);
3768         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3769         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3770         if (r < 0)
3771                 goto out;
3772         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3773         r = kvm_write_guest_page(kvm, fn++, &data,
3774                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3775         if (r < 0)
3776                 goto out;
3777         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3778         if (r < 0)
3779                 goto out;
3780         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3781         if (r < 0)
3782                 goto out;
3783         data = ~0;
3784         r = kvm_write_guest_page(kvm, fn, &data,
3785                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3786                                  sizeof(u8));
3787         if (r < 0)
3788                 goto out;
3789
3790         ret = 1;
3791 out:
3792         srcu_read_unlock(&kvm->srcu, idx);
3793         return ret;
3794 }
3795
3796 static int init_rmode_identity_map(struct kvm *kvm)
3797 {
3798         int i, idx, r, ret;
3799         pfn_t identity_map_pfn;
3800         u32 tmp;
3801
3802         if (!enable_ept)
3803                 return 1;
3804         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3805                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3806                         "haven't been allocated!\n");
3807                 return 0;
3808         }
3809         if (likely(kvm->arch.ept_identity_pagetable_done))
3810                 return 1;
3811         ret = 0;
3812         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3813         idx = srcu_read_lock(&kvm->srcu);
3814         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3815         if (r < 0)
3816                 goto out;
3817         /* Set up identity-mapping pagetable for EPT in real mode */
3818         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3819                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3820                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3821                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3822                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3823                 if (r < 0)
3824                         goto out;
3825         }
3826         kvm->arch.ept_identity_pagetable_done = true;
3827         ret = 1;
3828 out:
3829         srcu_read_unlock(&kvm->srcu, idx);
3830         return ret;
3831 }
3832
3833 static void seg_setup(int seg)
3834 {
3835         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3836         unsigned int ar;
3837
3838         vmcs_write16(sf->selector, 0);
3839         vmcs_writel(sf->base, 0);
3840         vmcs_write32(sf->limit, 0xffff);
3841         ar = 0x93;
3842         if (seg == VCPU_SREG_CS)
3843                 ar |= 0x08; /* code segment */
3844
3845         vmcs_write32(sf->ar_bytes, ar);
3846 }
3847
3848 static int alloc_apic_access_page(struct kvm *kvm)
3849 {
3850         struct page *page;
3851         struct kvm_userspace_memory_region kvm_userspace_mem;
3852         int r = 0;
3853
3854         mutex_lock(&kvm->slots_lock);
3855         if (kvm->arch.apic_access_page)
3856                 goto out;
3857         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3858         kvm_userspace_mem.flags = 0;
3859         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3860         kvm_userspace_mem.memory_size = PAGE_SIZE;
3861         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3862         if (r)
3863                 goto out;
3864
3865         page = gfn_to_page(kvm, 0xfee00);
3866         if (is_error_page(page)) {
3867                 r = -EFAULT;
3868                 goto out;
3869         }
3870
3871         kvm->arch.apic_access_page = page;
3872 out:
3873         mutex_unlock(&kvm->slots_lock);
3874         return r;
3875 }
3876
3877 static int alloc_identity_pagetable(struct kvm *kvm)
3878 {
3879         struct page *page;
3880         struct kvm_userspace_memory_region kvm_userspace_mem;
3881         int r = 0;
3882
3883         mutex_lock(&kvm->slots_lock);
3884         if (kvm->arch.ept_identity_pagetable)
3885                 goto out;
3886         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3887         kvm_userspace_mem.flags = 0;
3888         kvm_userspace_mem.guest_phys_addr =
3889                 kvm->arch.ept_identity_map_addr;
3890         kvm_userspace_mem.memory_size = PAGE_SIZE;
3891         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3892         if (r)
3893                 goto out;
3894
3895         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3896         if (is_error_page(page)) {
3897                 r = -EFAULT;
3898                 goto out;
3899         }
3900
3901         kvm->arch.ept_identity_pagetable = page;
3902 out:
3903         mutex_unlock(&kvm->slots_lock);
3904         return r;
3905 }
3906
3907 static void allocate_vpid(struct vcpu_vmx *vmx)
3908 {
3909         int vpid;
3910
3911         vmx->vpid = 0;
3912         if (!enable_vpid)
3913                 return;
3914         spin_lock(&vmx_vpid_lock);
3915         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3916         if (vpid < VMX_NR_VPIDS) {
3917                 vmx->vpid = vpid;
3918                 __set_bit(vpid, vmx_vpid_bitmap);
3919         }
3920         spin_unlock(&vmx_vpid_lock);
3921 }
3922
3923 static void free_vpid(struct vcpu_vmx *vmx)
3924 {
3925         if (!enable_vpid)
3926                 return;
3927         spin_lock(&vmx_vpid_lock);
3928         if (vmx->vpid != 0)
3929                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3930         spin_unlock(&vmx_vpid_lock);
3931 }
3932
3933 #define MSR_TYPE_R      1
3934 #define MSR_TYPE_W      2
3935 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3936                                                 u32 msr, int type)
3937 {
3938         int f = sizeof(unsigned long);
3939
3940         if (!cpu_has_vmx_msr_bitmap())
3941                 return;
3942
3943         /*
3944          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3945          * have the write-low and read-high bitmap offsets the wrong way round.
3946          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3947          */
3948         if (msr <= 0x1fff) {
3949                 if (type & MSR_TYPE_R)
3950                         /* read-low */
3951                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3952
3953                 if (type & MSR_TYPE_W)
3954                         /* write-low */
3955                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3956
3957         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3958                 msr &= 0x1fff;
3959                 if (type & MSR_TYPE_R)
3960                         /* read-high */
3961                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3962
3963                 if (type & MSR_TYPE_W)
3964                         /* write-high */
3965                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3966
3967         }
3968 }
3969
3970 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3971                                                 u32 msr, int type)
3972 {
3973         int f = sizeof(unsigned long);
3974
3975         if (!cpu_has_vmx_msr_bitmap())
3976                 return;
3977
3978         /*
3979          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3980          * have the write-low and read-high bitmap offsets the wrong way round.
3981          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3982          */
3983         if (msr <= 0x1fff) {
3984                 if (type & MSR_TYPE_R)
3985                         /* read-low */
3986                         __set_bit(msr, msr_bitmap + 0x000 / f);
3987
3988                 if (type & MSR_TYPE_W)
3989                         /* write-low */
3990                         __set_bit(msr, msr_bitmap + 0x800 / f);
3991
3992         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3993                 msr &= 0x1fff;
3994                 if (type & MSR_TYPE_R)
3995                         /* read-high */
3996                         __set_bit(msr, msr_bitmap + 0x400 / f);
3997
3998                 if (type & MSR_TYPE_W)
3999                         /* write-high */
4000                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4001
4002         }
4003 }
4004
4005 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4006 {
4007         if (!longmode_only)
4008                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4009                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4010         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4011                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4012 }
4013
4014 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4015 {
4016         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4017                         msr, MSR_TYPE_R);
4018         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4019                         msr, MSR_TYPE_R);
4020 }
4021
4022 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4023 {
4024         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4025                         msr, MSR_TYPE_R);
4026         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4027                         msr, MSR_TYPE_R);
4028 }
4029
4030 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4031 {
4032         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4033                         msr, MSR_TYPE_W);
4034         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4035                         msr, MSR_TYPE_W);
4036 }
4037
4038 static int vmx_vm_has_apicv(struct kvm *kvm)
4039 {
4040         return enable_apicv && irqchip_in_kernel(kvm);
4041 }
4042
4043 /*
4044  * Send interrupt to vcpu via posted interrupt way.
4045  * 1. If target vcpu is running(non-root mode), send posted interrupt
4046  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4047  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4048  * interrupt from PIR in next vmentry.
4049  */
4050 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4051 {
4052         struct vcpu_vmx *vmx = to_vmx(vcpu);
4053         int r;
4054
4055         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4056                 return;
4057
4058         r = pi_test_and_set_on(&vmx->pi_desc);
4059         kvm_make_request(KVM_REQ_EVENT, vcpu);
4060 #ifdef CONFIG_SMP
4061         if (!r && (vcpu->mode == IN_GUEST_MODE))
4062                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4063                                 POSTED_INTR_VECTOR);
4064         else
4065 #endif
4066                 kvm_vcpu_kick(vcpu);
4067 }
4068
4069 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4070 {
4071         struct vcpu_vmx *vmx = to_vmx(vcpu);
4072
4073         if (!pi_test_and_clear_on(&vmx->pi_desc))
4074                 return;
4075
4076         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4077 }
4078
4079 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4080 {
4081         return;
4082 }
4083
4084 /*
4085  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4086  * will not change in the lifetime of the guest.
4087  * Note that host-state that does change is set elsewhere. E.g., host-state
4088  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4089  */
4090 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4091 {
4092         u32 low32, high32;
4093         unsigned long tmpl;
4094         struct desc_ptr dt;
4095
4096         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4097         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4098         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4099
4100         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4101 #ifdef CONFIG_X86_64
4102         /*
4103          * Load null selectors, so we can avoid reloading them in
4104          * __vmx_load_host_state(), in case userspace uses the null selectors
4105          * too (the expected case).
4106          */
4107         vmcs_write16(HOST_DS_SELECTOR, 0);
4108         vmcs_write16(HOST_ES_SELECTOR, 0);
4109 #else
4110         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4111         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4112 #endif
4113         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4114         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4115
4116         native_store_idt(&dt);
4117         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4118         vmx->host_idt_base = dt.address;
4119
4120         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4121
4122         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4123         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4124         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4125         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4126
4127         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4128                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4129                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4130         }
4131 }
4132
4133 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4134 {
4135         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4136         if (enable_ept)
4137                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4138         if (is_guest_mode(&vmx->vcpu))
4139                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4140                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4141         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4142 }
4143
4144 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4145 {
4146         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4147
4148         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4149                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4150         return pin_based_exec_ctrl;
4151 }
4152
4153 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4154 {
4155         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4156         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4157                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4158 #ifdef CONFIG_X86_64
4159                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4160                                 CPU_BASED_CR8_LOAD_EXITING;
4161 #endif
4162         }
4163         if (!enable_ept)
4164                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4165                                 CPU_BASED_CR3_LOAD_EXITING  |
4166                                 CPU_BASED_INVLPG_EXITING;
4167         return exec_control;
4168 }
4169
4170 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4171 {
4172         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4173         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4174                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4175         if (vmx->vpid == 0)
4176                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4177         if (!enable_ept) {
4178                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4179                 enable_unrestricted_guest = 0;
4180                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4181                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4182         }
4183         if (!enable_unrestricted_guest)
4184                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4185         if (!ple_gap)
4186                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4187         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4188                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4189                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4190         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4191         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4192            (handle_vmptrld).
4193            We can NOT enable shadow_vmcs here because we don't have yet
4194            a current VMCS12
4195         */
4196         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4197         return exec_control;
4198 }
4199
4200 static void ept_set_mmio_spte_mask(void)
4201 {
4202         /*
4203          * EPT Misconfigurations can be generated if the value of bits 2:0
4204          * of an EPT paging-structure entry is 110b (write/execute).
4205          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4206          * spte.
4207          */
4208         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4209 }
4210
4211 /*
4212  * Sets up the vmcs for emulated real mode.
4213  */
4214 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4215 {
4216 #ifdef CONFIG_X86_64
4217         unsigned long a;
4218 #endif
4219         int i;
4220
4221         /* I/O */
4222         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4223         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4224
4225         if (enable_shadow_vmcs) {
4226                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4227                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4228         }
4229         if (cpu_has_vmx_msr_bitmap())
4230                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4231
4232         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4233
4234         /* Control */
4235         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4236
4237         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4238
4239         if (cpu_has_secondary_exec_ctrls()) {
4240                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4241                                 vmx_secondary_exec_control(vmx));
4242         }
4243
4244         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4245                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4246                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4247                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4248                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4249
4250                 vmcs_write16(GUEST_INTR_STATUS, 0);
4251
4252                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4253                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4254         }
4255
4256         if (ple_gap) {
4257                 vmcs_write32(PLE_GAP, ple_gap);
4258                 vmcs_write32(PLE_WINDOW, ple_window);
4259         }
4260
4261         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4262         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4263         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4264
4265         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4266         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4267         vmx_set_constant_host_state(vmx);
4268 #ifdef CONFIG_X86_64
4269         rdmsrl(MSR_FS_BASE, a);
4270         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4271         rdmsrl(MSR_GS_BASE, a);
4272         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4273 #else
4274         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4275         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4276 #endif
4277
4278         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4279         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4280         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4281         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4282         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4283
4284         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4285                 u32 msr_low, msr_high;
4286                 u64 host_pat;
4287                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4288                 host_pat = msr_low | ((u64) msr_high << 32);
4289                 /* Write the default value follow host pat */
4290                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4291                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4292                 vmx->vcpu.arch.pat = host_pat;
4293         }
4294
4295         for (i = 0; i < NR_VMX_MSR; ++i) {
4296                 u32 index = vmx_msr_index[i];
4297                 u32 data_low, data_high;
4298                 int j = vmx->nmsrs;
4299
4300                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4301                         continue;
4302                 if (wrmsr_safe(index, data_low, data_high) < 0)
4303                         continue;
4304                 vmx->guest_msrs[j].index = i;
4305                 vmx->guest_msrs[j].data = 0;
4306                 vmx->guest_msrs[j].mask = -1ull;
4307                 ++vmx->nmsrs;
4308         }
4309
4310         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4311
4312         /* 22.2.1, 20.8.1 */
4313         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4314
4315         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4316         set_cr4_guest_host_mask(vmx);
4317
4318         return 0;
4319 }
4320
4321 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4322 {
4323         struct vcpu_vmx *vmx = to_vmx(vcpu);
4324         u64 msr;
4325
4326         vmx->rmode.vm86_active = 0;
4327
4328         vmx->soft_vnmi_blocked = 0;
4329
4330         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4331         kvm_set_cr8(&vmx->vcpu, 0);
4332         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4333         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4334                 msr |= MSR_IA32_APICBASE_BSP;
4335         kvm_set_apic_base(&vmx->vcpu, msr);
4336
4337         vmx_segment_cache_clear(vmx);
4338
4339         seg_setup(VCPU_SREG_CS);
4340         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4341         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4342
4343         seg_setup(VCPU_SREG_DS);
4344         seg_setup(VCPU_SREG_ES);
4345         seg_setup(VCPU_SREG_FS);
4346         seg_setup(VCPU_SREG_GS);
4347         seg_setup(VCPU_SREG_SS);
4348
4349         vmcs_write16(GUEST_TR_SELECTOR, 0);
4350         vmcs_writel(GUEST_TR_BASE, 0);
4351         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4352         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4353
4354         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4355         vmcs_writel(GUEST_LDTR_BASE, 0);
4356         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4357         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4358
4359         vmcs_write32(GUEST_SYSENTER_CS, 0);
4360         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4361         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4362
4363         vmcs_writel(GUEST_RFLAGS, 0x02);
4364         kvm_rip_write(vcpu, 0xfff0);
4365
4366         vmcs_writel(GUEST_GDTR_BASE, 0);
4367         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4368
4369         vmcs_writel(GUEST_IDTR_BASE, 0);
4370         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4371
4372         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4373         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4374         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4375
4376         /* Special registers */
4377         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4378
4379         setup_msrs(vmx);
4380
4381         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4382
4383         if (cpu_has_vmx_tpr_shadow()) {
4384                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4385                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4386                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4387                                      __pa(vmx->vcpu.arch.apic->regs));
4388                 vmcs_write32(TPR_THRESHOLD, 0);
4389         }
4390
4391         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4392                 vmcs_write64(APIC_ACCESS_ADDR,
4393                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4394
4395         if (vmx_vm_has_apicv(vcpu->kvm))
4396                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4397
4398         if (vmx->vpid != 0)
4399                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4400
4401         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4402         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4403         vmx_set_cr4(&vmx->vcpu, 0);
4404         vmx_set_efer(&vmx->vcpu, 0);
4405         vmx_fpu_activate(&vmx->vcpu);
4406         update_exception_bitmap(&vmx->vcpu);
4407
4408         vpid_sync_context(vmx);
4409 }
4410
4411 /*
4412  * In nested virtualization, check if L1 asked to exit on external interrupts.
4413  * For most existing hypervisors, this will always return true.
4414  */
4415 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4416 {
4417         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4418                 PIN_BASED_EXT_INTR_MASK;
4419 }
4420
4421 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4422 {
4423         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4424                 PIN_BASED_NMI_EXITING;
4425 }
4426
4427 static int enable_irq_window(struct kvm_vcpu *vcpu)
4428 {
4429         u32 cpu_based_vm_exec_control;
4430
4431         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4432                 /*
4433                  * We get here if vmx_interrupt_allowed() said we can't
4434                  * inject to L1 now because L2 must run. The caller will have
4435                  * to make L2 exit right after entry, so we can inject to L1
4436                  * more promptly.
4437                  */
4438                 return -EBUSY;
4439
4440         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4441         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4442         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4443         return 0;
4444 }
4445
4446 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4447 {
4448         u32 cpu_based_vm_exec_control;
4449
4450         if (!cpu_has_virtual_nmis())
4451                 return enable_irq_window(vcpu);
4452
4453         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4454                 return enable_irq_window(vcpu);
4455
4456         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4457         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4458         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4459         return 0;
4460 }
4461
4462 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4463 {
4464         struct vcpu_vmx *vmx = to_vmx(vcpu);
4465         uint32_t intr;
4466         int irq = vcpu->arch.interrupt.nr;
4467
4468         trace_kvm_inj_virq(irq);
4469
4470         ++vcpu->stat.irq_injections;
4471         if (vmx->rmode.vm86_active) {
4472                 int inc_eip = 0;
4473                 if (vcpu->arch.interrupt.soft)
4474                         inc_eip = vcpu->arch.event_exit_inst_len;
4475                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4476                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4477                 return;
4478         }
4479         intr = irq | INTR_INFO_VALID_MASK;
4480         if (vcpu->arch.interrupt.soft) {
4481                 intr |= INTR_TYPE_SOFT_INTR;
4482                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4483                              vmx->vcpu.arch.event_exit_inst_len);
4484         } else
4485                 intr |= INTR_TYPE_EXT_INTR;
4486         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4487 }
4488
4489 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4490 {
4491         struct vcpu_vmx *vmx = to_vmx(vcpu);
4492
4493         if (is_guest_mode(vcpu))
4494                 return;
4495
4496         if (!cpu_has_virtual_nmis()) {
4497                 /*
4498                  * Tracking the NMI-blocked state in software is built upon
4499                  * finding the next open IRQ window. This, in turn, depends on
4500                  * well-behaving guests: They have to keep IRQs disabled at
4501                  * least as long as the NMI handler runs. Otherwise we may
4502                  * cause NMI nesting, maybe breaking the guest. But as this is
4503                  * highly unlikely, we can live with the residual risk.
4504                  */
4505                 vmx->soft_vnmi_blocked = 1;
4506                 vmx->vnmi_blocked_time = 0;
4507         }
4508
4509         ++vcpu->stat.nmi_injections;
4510         vmx->nmi_known_unmasked = false;
4511         if (vmx->rmode.vm86_active) {
4512                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4513                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4514                 return;
4515         }
4516         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4517                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4518 }
4519
4520 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4521 {
4522         if (!cpu_has_virtual_nmis())
4523                 return to_vmx(vcpu)->soft_vnmi_blocked;
4524         if (to_vmx(vcpu)->nmi_known_unmasked)
4525                 return false;
4526         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4527 }
4528
4529 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4530 {
4531         struct vcpu_vmx *vmx = to_vmx(vcpu);
4532
4533         if (!cpu_has_virtual_nmis()) {
4534                 if (vmx->soft_vnmi_blocked != masked) {
4535                         vmx->soft_vnmi_blocked = masked;
4536                         vmx->vnmi_blocked_time = 0;
4537                 }
4538         } else {
4539                 vmx->nmi_known_unmasked = !masked;
4540                 if (masked)
4541                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4542                                       GUEST_INTR_STATE_NMI);
4543                 else
4544                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4545                                         GUEST_INTR_STATE_NMI);
4546         }
4547 }
4548
4549 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4550 {
4551         if (is_guest_mode(vcpu)) {
4552                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4553
4554                 if (to_vmx(vcpu)->nested.nested_run_pending)
4555                         return 0;
4556                 if (nested_exit_on_nmi(vcpu)) {
4557                         nested_vmx_vmexit(vcpu);
4558                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4559                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4560                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4561                         /*
4562                          * The NMI-triggered VM exit counts as injection:
4563                          * clear this one and block further NMIs.
4564                          */
4565                         vcpu->arch.nmi_pending = 0;
4566                         vmx_set_nmi_mask(vcpu, true);
4567                         return 0;
4568                 }
4569         }
4570
4571         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4572                 return 0;
4573
4574         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4575                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4576                    | GUEST_INTR_STATE_NMI));
4577 }
4578
4579 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4580 {
4581         if (is_guest_mode(vcpu)) {
4582                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4583
4584                 if (to_vmx(vcpu)->nested.nested_run_pending)
4585                         return 0;
4586                 if (nested_exit_on_intr(vcpu)) {
4587                         nested_vmx_vmexit(vcpu);
4588                         vmcs12->vm_exit_reason =
4589                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4590                         vmcs12->vm_exit_intr_info = 0;
4591                         /*
4592                          * fall through to normal code, but now in L1, not L2
4593                          */
4594                 }
4595         }
4596
4597         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4598                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4599                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4600 }
4601
4602 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4603 {
4604         int ret;
4605         struct kvm_userspace_memory_region tss_mem = {
4606                 .slot = TSS_PRIVATE_MEMSLOT,
4607                 .guest_phys_addr = addr,
4608                 .memory_size = PAGE_SIZE * 3,
4609                 .flags = 0,
4610         };
4611
4612         ret = kvm_set_memory_region(kvm, &tss_mem);
4613         if (ret)
4614                 return ret;
4615         kvm->arch.tss_addr = addr;
4616         if (!init_rmode_tss(kvm))
4617                 return  -ENOMEM;
4618
4619         return 0;
4620 }
4621
4622 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4623 {
4624         switch (vec) {
4625         case BP_VECTOR:
4626                 /*
4627                  * Update instruction length as we may reinject the exception
4628                  * from user space while in guest debugging mode.
4629                  */
4630                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4631                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4632                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4633                         return false;
4634                 /* fall through */
4635         case DB_VECTOR:
4636                 if (vcpu->guest_debug &
4637                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4638                         return false;
4639                 /* fall through */
4640         case DE_VECTOR:
4641         case OF_VECTOR:
4642         case BR_VECTOR:
4643         case UD_VECTOR:
4644         case DF_VECTOR:
4645         case SS_VECTOR:
4646         case GP_VECTOR:
4647         case MF_VECTOR:
4648                 return true;
4649         break;
4650         }
4651         return false;
4652 }
4653
4654 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4655                                   int vec, u32 err_code)
4656 {
4657         /*
4658          * Instruction with address size override prefix opcode 0x67
4659          * Cause the #SS fault with 0 error code in VM86 mode.
4660          */
4661         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4662                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4663                         if (vcpu->arch.halt_request) {
4664                                 vcpu->arch.halt_request = 0;
4665                                 return kvm_emulate_halt(vcpu);
4666                         }
4667                         return 1;
4668                 }
4669                 return 0;
4670         }
4671
4672         /*
4673          * Forward all other exceptions that are valid in real mode.
4674          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4675          *        the required debugging infrastructure rework.
4676          */
4677         kvm_queue_exception(vcpu, vec);
4678         return 1;
4679 }
4680
4681 /*
4682  * Trigger machine check on the host. We assume all the MSRs are already set up
4683  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4684  * We pass a fake environment to the machine check handler because we want
4685  * the guest to be always treated like user space, no matter what context
4686  * it used internally.
4687  */
4688 static void kvm_machine_check(void)
4689 {
4690 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4691         struct pt_regs regs = {
4692                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4693                 .flags = X86_EFLAGS_IF,
4694         };
4695
4696         do_machine_check(&regs, 0);
4697 #endif
4698 }
4699
4700 static int handle_machine_check(struct kvm_vcpu *vcpu)
4701 {
4702         /* already handled by vcpu_run */
4703         return 1;
4704 }
4705
4706 static int handle_exception(struct kvm_vcpu *vcpu)
4707 {
4708         struct vcpu_vmx *vmx = to_vmx(vcpu);
4709         struct kvm_run *kvm_run = vcpu->run;
4710         u32 intr_info, ex_no, error_code;
4711         unsigned long cr2, rip, dr6;
4712         u32 vect_info;
4713         enum emulation_result er;
4714
4715         vect_info = vmx->idt_vectoring_info;
4716         intr_info = vmx->exit_intr_info;
4717
4718         if (is_machine_check(intr_info))
4719                 return handle_machine_check(vcpu);
4720
4721         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4722                 return 1;  /* already handled by vmx_vcpu_run() */
4723
4724         if (is_no_device(intr_info)) {
4725                 vmx_fpu_activate(vcpu);
4726                 return 1;
4727         }
4728
4729         if (is_invalid_opcode(intr_info)) {
4730                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4731                 if (er != EMULATE_DONE)
4732                         kvm_queue_exception(vcpu, UD_VECTOR);
4733                 return 1;
4734         }
4735
4736         error_code = 0;
4737         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4738                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4739
4740         /*
4741          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4742          * MMIO, it is better to report an internal error.
4743          * See the comments in vmx_handle_exit.
4744          */
4745         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4746             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4747                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4748                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4749                 vcpu->run->internal.ndata = 2;
4750                 vcpu->run->internal.data[0] = vect_info;
4751                 vcpu->run->internal.data[1] = intr_info;
4752                 return 0;
4753         }
4754
4755         if (is_page_fault(intr_info)) {
4756                 /* EPT won't cause page fault directly */
4757                 BUG_ON(enable_ept);
4758                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4759                 trace_kvm_page_fault(cr2, error_code);
4760
4761                 if (kvm_event_needs_reinjection(vcpu))
4762                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4763                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4764         }
4765
4766         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4767
4768         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4769                 return handle_rmode_exception(vcpu, ex_no, error_code);
4770
4771         switch (ex_no) {
4772         case DB_VECTOR:
4773                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4774                 if (!(vcpu->guest_debug &
4775                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4776                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4777                         kvm_queue_exception(vcpu, DB_VECTOR);
4778                         return 1;
4779                 }
4780                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4781                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4782                 /* fall through */
4783         case BP_VECTOR:
4784                 /*
4785                  * Update instruction length as we may reinject #BP from
4786                  * user space while in guest debugging mode. Reading it for
4787                  * #DB as well causes no harm, it is not used in that case.
4788                  */
4789                 vmx->vcpu.arch.event_exit_inst_len =
4790                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4791                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4792                 rip = kvm_rip_read(vcpu);
4793                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4794                 kvm_run->debug.arch.exception = ex_no;
4795                 break;
4796         default:
4797                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4798                 kvm_run->ex.exception = ex_no;
4799                 kvm_run->ex.error_code = error_code;
4800                 break;
4801         }
4802         return 0;
4803 }
4804
4805 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4806 {
4807         ++vcpu->stat.irq_exits;
4808         return 1;
4809 }
4810
4811 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4812 {
4813         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4814         return 0;
4815 }
4816
4817 static int handle_io(struct kvm_vcpu *vcpu)
4818 {
4819         unsigned long exit_qualification;
4820         int size, in, string;
4821         unsigned port;
4822
4823         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4824         string = (exit_qualification & 16) != 0;
4825         in = (exit_qualification & 8) != 0;
4826
4827         ++vcpu->stat.io_exits;
4828
4829         if (string || in)
4830                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4831
4832         port = exit_qualification >> 16;
4833         size = (exit_qualification & 7) + 1;
4834         skip_emulated_instruction(vcpu);
4835
4836         return kvm_fast_pio_out(vcpu, size, port);
4837 }
4838
4839 static void
4840 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4841 {
4842         /*
4843          * Patch in the VMCALL instruction:
4844          */
4845         hypercall[0] = 0x0f;
4846         hypercall[1] = 0x01;
4847         hypercall[2] = 0xc1;
4848 }
4849
4850 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4851 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4852 {
4853         if (is_guest_mode(vcpu)) {
4854                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4855                 unsigned long orig_val = val;
4856
4857                 /*
4858                  * We get here when L2 changed cr0 in a way that did not change
4859                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4860                  * but did change L0 shadowed bits. So we first calculate the
4861                  * effective cr0 value that L1 would like to write into the
4862                  * hardware. It consists of the L2-owned bits from the new
4863                  * value combined with the L1-owned bits from L1's guest_cr0.
4864                  */
4865                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4866                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4867
4868                 /* TODO: will have to take unrestricted guest mode into
4869                  * account */
4870                 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4871                         return 1;
4872
4873                 if (kvm_set_cr0(vcpu, val))
4874                         return 1;
4875                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4876                 return 0;
4877         } else {
4878                 if (to_vmx(vcpu)->nested.vmxon &&
4879                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4880                         return 1;
4881                 return kvm_set_cr0(vcpu, val);
4882         }
4883 }
4884
4885 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4886 {
4887         if (is_guest_mode(vcpu)) {
4888                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4889                 unsigned long orig_val = val;
4890
4891                 /* analogously to handle_set_cr0 */
4892                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4893                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4894                 if (kvm_set_cr4(vcpu, val))
4895                         return 1;
4896                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4897                 return 0;
4898         } else
4899                 return kvm_set_cr4(vcpu, val);
4900 }
4901
4902 /* called to set cr0 as approriate for clts instruction exit. */
4903 static void handle_clts(struct kvm_vcpu *vcpu)
4904 {
4905         if (is_guest_mode(vcpu)) {
4906                 /*
4907                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4908                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4909                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4910                  */
4911                 vmcs_writel(CR0_READ_SHADOW,
4912                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4913                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4914         } else
4915                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4916 }
4917
4918 static int handle_cr(struct kvm_vcpu *vcpu)
4919 {
4920         unsigned long exit_qualification, val;
4921         int cr;
4922         int reg;
4923         int err;
4924
4925         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4926         cr = exit_qualification & 15;
4927         reg = (exit_qualification >> 8) & 15;
4928         switch ((exit_qualification >> 4) & 3) {
4929         case 0: /* mov to cr */
4930                 val = kvm_register_read(vcpu, reg);
4931                 trace_kvm_cr_write(cr, val);
4932                 switch (cr) {
4933                 case 0:
4934                         err = handle_set_cr0(vcpu, val);
4935                         kvm_complete_insn_gp(vcpu, err);
4936                         return 1;
4937                 case 3:
4938                         err = kvm_set_cr3(vcpu, val);
4939                         kvm_complete_insn_gp(vcpu, err);
4940                         return 1;
4941                 case 4:
4942                         err = handle_set_cr4(vcpu, val);
4943                         kvm_complete_insn_gp(vcpu, err);
4944                         return 1;
4945                 case 8: {
4946                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4947                                 u8 cr8 = kvm_register_read(vcpu, reg);
4948                                 err = kvm_set_cr8(vcpu, cr8);
4949                                 kvm_complete_insn_gp(vcpu, err);
4950                                 if (irqchip_in_kernel(vcpu->kvm))
4951                                         return 1;
4952                                 if (cr8_prev <= cr8)
4953                                         return 1;
4954                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4955                                 return 0;
4956                         }
4957                 }
4958                 break;
4959         case 2: /* clts */
4960                 handle_clts(vcpu);
4961                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4962                 skip_emulated_instruction(vcpu);
4963                 vmx_fpu_activate(vcpu);
4964                 return 1;
4965         case 1: /*mov from cr*/
4966                 switch (cr) {
4967                 case 3:
4968                         val = kvm_read_cr3(vcpu);
4969                         kvm_register_write(vcpu, reg, val);
4970                         trace_kvm_cr_read(cr, val);
4971                         skip_emulated_instruction(vcpu);
4972                         return 1;
4973                 case 8:
4974                         val = kvm_get_cr8(vcpu);
4975                         kvm_register_write(vcpu, reg, val);
4976                         trace_kvm_cr_read(cr, val);
4977                         skip_emulated_instruction(vcpu);
4978                         return 1;
4979                 }
4980                 break;
4981         case 3: /* lmsw */
4982                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4983                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4984                 kvm_lmsw(vcpu, val);
4985
4986                 skip_emulated_instruction(vcpu);
4987                 return 1;
4988         default:
4989                 break;
4990         }
4991         vcpu->run->exit_reason = 0;
4992         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4993                (int)(exit_qualification >> 4) & 3, cr);
4994         return 0;
4995 }
4996
4997 static int handle_dr(struct kvm_vcpu *vcpu)
4998 {
4999         unsigned long exit_qualification;
5000         int dr, reg;
5001
5002         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5003         if (!kvm_require_cpl(vcpu, 0))
5004                 return 1;
5005         dr = vmcs_readl(GUEST_DR7);
5006         if (dr & DR7_GD) {
5007                 /*
5008                  * As the vm-exit takes precedence over the debug trap, we
5009                  * need to emulate the latter, either for the host or the
5010                  * guest debugging itself.
5011                  */
5012                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5013                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5014                         vcpu->run->debug.arch.dr7 = dr;
5015                         vcpu->run->debug.arch.pc =
5016                                 vmcs_readl(GUEST_CS_BASE) +
5017                                 vmcs_readl(GUEST_RIP);
5018                         vcpu->run->debug.arch.exception = DB_VECTOR;
5019                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5020                         return 0;
5021                 } else {
5022                         vcpu->arch.dr7 &= ~DR7_GD;
5023                         vcpu->arch.dr6 |= DR6_BD;
5024                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5025                         kvm_queue_exception(vcpu, DB_VECTOR);
5026                         return 1;
5027                 }
5028         }
5029
5030         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5031         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5032         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5033         if (exit_qualification & TYPE_MOV_FROM_DR) {
5034                 unsigned long val;
5035                 if (!kvm_get_dr(vcpu, dr, &val))
5036                         kvm_register_write(vcpu, reg, val);
5037         } else
5038                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5039         skip_emulated_instruction(vcpu);
5040         return 1;
5041 }
5042
5043 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5044 {
5045         vmcs_writel(GUEST_DR7, val);
5046 }
5047
5048 static int handle_cpuid(struct kvm_vcpu *vcpu)
5049 {
5050         kvm_emulate_cpuid(vcpu);
5051         return 1;
5052 }
5053
5054 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5055 {
5056         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5057         u64 data;
5058
5059         if (vmx_get_msr(vcpu, ecx, &data)) {
5060                 trace_kvm_msr_read_ex(ecx);
5061                 kvm_inject_gp(vcpu, 0);
5062                 return 1;
5063         }
5064
5065         trace_kvm_msr_read(ecx, data);
5066
5067         /* FIXME: handling of bits 32:63 of rax, rdx */
5068         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5069         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5070         skip_emulated_instruction(vcpu);
5071         return 1;
5072 }
5073
5074 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5075 {
5076         struct msr_data msr;
5077         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5078         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5079                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5080
5081         msr.data = data;
5082         msr.index = ecx;
5083         msr.host_initiated = false;
5084         if (vmx_set_msr(vcpu, &msr) != 0) {
5085                 trace_kvm_msr_write_ex(ecx, data);
5086                 kvm_inject_gp(vcpu, 0);
5087                 return 1;
5088         }
5089
5090         trace_kvm_msr_write(ecx, data);
5091         skip_emulated_instruction(vcpu);
5092         return 1;
5093 }
5094
5095 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5096 {
5097         kvm_make_request(KVM_REQ_EVENT, vcpu);
5098         return 1;
5099 }
5100
5101 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5102 {
5103         u32 cpu_based_vm_exec_control;
5104
5105         /* clear pending irq */
5106         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5107         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5108         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5109
5110         kvm_make_request(KVM_REQ_EVENT, vcpu);
5111
5112         ++vcpu->stat.irq_window_exits;
5113
5114         /*
5115          * If the user space waits to inject interrupts, exit as soon as
5116          * possible
5117          */
5118         if (!irqchip_in_kernel(vcpu->kvm) &&
5119             vcpu->run->request_interrupt_window &&
5120             !kvm_cpu_has_interrupt(vcpu)) {
5121                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5122                 return 0;
5123         }
5124         return 1;
5125 }
5126
5127 static int handle_halt(struct kvm_vcpu *vcpu)
5128 {
5129         skip_emulated_instruction(vcpu);
5130         return kvm_emulate_halt(vcpu);
5131 }
5132
5133 static int handle_vmcall(struct kvm_vcpu *vcpu)
5134 {
5135         skip_emulated_instruction(vcpu);
5136         kvm_emulate_hypercall(vcpu);
5137         return 1;
5138 }
5139
5140 static int handle_invd(struct kvm_vcpu *vcpu)
5141 {
5142         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5143 }
5144
5145 static int handle_invlpg(struct kvm_vcpu *vcpu)
5146 {
5147         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5148
5149         kvm_mmu_invlpg(vcpu, exit_qualification);
5150         skip_emulated_instruction(vcpu);
5151         return 1;
5152 }
5153
5154 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5155 {
5156         int err;
5157
5158         err = kvm_rdpmc(vcpu);
5159         kvm_complete_insn_gp(vcpu, err);
5160
5161         return 1;
5162 }
5163
5164 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5165 {
5166         skip_emulated_instruction(vcpu);
5167         kvm_emulate_wbinvd(vcpu);
5168         return 1;
5169 }
5170
5171 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5172 {
5173         u64 new_bv = kvm_read_edx_eax(vcpu);
5174         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5175
5176         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5177                 skip_emulated_instruction(vcpu);
5178         return 1;
5179 }
5180
5181 static int handle_apic_access(struct kvm_vcpu *vcpu)
5182 {
5183         if (likely(fasteoi)) {
5184                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5185                 int access_type, offset;
5186
5187                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5188                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5189                 /*
5190                  * Sane guest uses MOV to write EOI, with written value
5191                  * not cared. So make a short-circuit here by avoiding
5192                  * heavy instruction emulation.
5193                  */
5194                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5195                     (offset == APIC_EOI)) {
5196                         kvm_lapic_set_eoi(vcpu);
5197                         skip_emulated_instruction(vcpu);
5198                         return 1;
5199                 }
5200         }
5201         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5202 }
5203
5204 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5205 {
5206         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5207         int vector = exit_qualification & 0xff;
5208
5209         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5210         kvm_apic_set_eoi_accelerated(vcpu, vector);
5211         return 1;
5212 }
5213
5214 static int handle_apic_write(struct kvm_vcpu *vcpu)
5215 {
5216         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5217         u32 offset = exit_qualification & 0xfff;
5218
5219         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5220         kvm_apic_write_nodecode(vcpu, offset);
5221         return 1;
5222 }
5223
5224 static int handle_task_switch(struct kvm_vcpu *vcpu)
5225 {
5226         struct vcpu_vmx *vmx = to_vmx(vcpu);
5227         unsigned long exit_qualification;
5228         bool has_error_code = false;
5229         u32 error_code = 0;
5230         u16 tss_selector;
5231         int reason, type, idt_v, idt_index;
5232
5233         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5234         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5235         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5236
5237         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5238
5239         reason = (u32)exit_qualification >> 30;
5240         if (reason == TASK_SWITCH_GATE && idt_v) {
5241                 switch (type) {
5242                 case INTR_TYPE_NMI_INTR:
5243                         vcpu->arch.nmi_injected = false;
5244                         vmx_set_nmi_mask(vcpu, true);
5245                         break;
5246                 case INTR_TYPE_EXT_INTR:
5247                 case INTR_TYPE_SOFT_INTR:
5248                         kvm_clear_interrupt_queue(vcpu);
5249                         break;
5250                 case INTR_TYPE_HARD_EXCEPTION:
5251                         if (vmx->idt_vectoring_info &
5252                             VECTORING_INFO_DELIVER_CODE_MASK) {
5253                                 has_error_code = true;
5254                                 error_code =
5255                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5256                         }
5257                         /* fall through */
5258                 case INTR_TYPE_SOFT_EXCEPTION:
5259                         kvm_clear_exception_queue(vcpu);
5260                         break;
5261                 default:
5262                         break;
5263                 }
5264         }
5265         tss_selector = exit_qualification;
5266
5267         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5268                        type != INTR_TYPE_EXT_INTR &&
5269                        type != INTR_TYPE_NMI_INTR))
5270                 skip_emulated_instruction(vcpu);
5271
5272         if (kvm_task_switch(vcpu, tss_selector,
5273                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5274                             has_error_code, error_code) == EMULATE_FAIL) {
5275                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5276                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5277                 vcpu->run->internal.ndata = 0;
5278                 return 0;
5279         }
5280
5281         /* clear all local breakpoint enable flags */
5282         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5283
5284         /*
5285          * TODO: What about debug traps on tss switch?
5286          *       Are we supposed to inject them and update dr6?
5287          */
5288
5289         return 1;
5290 }
5291
5292 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5293 {
5294         unsigned long exit_qualification;
5295         gpa_t gpa;
5296         u32 error_code;
5297         int gla_validity;
5298
5299         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5300
5301         gla_validity = (exit_qualification >> 7) & 0x3;
5302         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5303                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5304                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5305                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5306                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5307                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5308                         (long unsigned int)exit_qualification);
5309                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5310                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5311                 return 0;
5312         }
5313
5314         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5315         trace_kvm_page_fault(gpa, exit_qualification);
5316
5317         /* It is a write fault? */
5318         error_code = exit_qualification & (1U << 1);
5319         /* ept page table is present? */
5320         error_code |= (exit_qualification >> 3) & 0x1;
5321
5322         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5323 }
5324
5325 static u64 ept_rsvd_mask(u64 spte, int level)
5326 {
5327         int i;
5328         u64 mask = 0;
5329
5330         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5331                 mask |= (1ULL << i);
5332
5333         if (level > 2)
5334                 /* bits 7:3 reserved */
5335                 mask |= 0xf8;
5336         else if (level == 2) {
5337                 if (spte & (1ULL << 7))
5338                         /* 2MB ref, bits 20:12 reserved */
5339                         mask |= 0x1ff000;
5340                 else
5341                         /* bits 6:3 reserved */
5342                         mask |= 0x78;
5343         }
5344
5345         return mask;
5346 }
5347
5348 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5349                                        int level)
5350 {
5351         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5352
5353         /* 010b (write-only) */
5354         WARN_ON((spte & 0x7) == 0x2);
5355
5356         /* 110b (write/execute) */
5357         WARN_ON((spte & 0x7) == 0x6);
5358
5359         /* 100b (execute-only) and value not supported by logical processor */
5360         if (!cpu_has_vmx_ept_execute_only())
5361                 WARN_ON((spte & 0x7) == 0x4);
5362
5363         /* not 000b */
5364         if ((spte & 0x7)) {
5365                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5366
5367                 if (rsvd_bits != 0) {
5368                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5369                                          __func__, rsvd_bits);
5370                         WARN_ON(1);
5371                 }
5372
5373                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5374                         u64 ept_mem_type = (spte & 0x38) >> 3;
5375
5376                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5377                             ept_mem_type == 7) {
5378                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5379                                                 __func__, ept_mem_type);
5380                                 WARN_ON(1);
5381                         }
5382                 }
5383         }
5384 }
5385
5386 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5387 {
5388         u64 sptes[4];
5389         int nr_sptes, i, ret;
5390         gpa_t gpa;
5391
5392         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5393
5394         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5395         if (likely(ret == RET_MMIO_PF_EMULATE))
5396                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5397                                               EMULATE_DONE;
5398
5399         if (unlikely(ret == RET_MMIO_PF_INVALID))
5400                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5401
5402         if (unlikely(ret == RET_MMIO_PF_RETRY))
5403                 return 1;
5404
5405         /* It is the real ept misconfig */
5406         printk(KERN_ERR "EPT: Misconfiguration.\n");
5407         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5408
5409         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5410
5411         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5412                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5413
5414         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5415         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5416
5417         return 0;
5418 }
5419
5420 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5421 {
5422         u32 cpu_based_vm_exec_control;
5423
5424         /* clear pending NMI */
5425         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5426         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5427         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5428         ++vcpu->stat.nmi_window_exits;
5429         kvm_make_request(KVM_REQ_EVENT, vcpu);
5430
5431         return 1;
5432 }
5433
5434 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5435 {
5436         struct vcpu_vmx *vmx = to_vmx(vcpu);
5437         enum emulation_result err = EMULATE_DONE;
5438         int ret = 1;
5439         u32 cpu_exec_ctrl;
5440         bool intr_window_requested;
5441         unsigned count = 130;
5442
5443         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5444         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5445
5446         while (!guest_state_valid(vcpu) && count-- != 0) {
5447                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5448                         return handle_interrupt_window(&vmx->vcpu);
5449
5450                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5451                         return 1;
5452
5453                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5454
5455                 if (err == EMULATE_USER_EXIT) {
5456                         ret = 0;
5457                         goto out;
5458                 }
5459
5460                 if (err != EMULATE_DONE) {
5461                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5462                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5463                         vcpu->run->internal.ndata = 0;
5464                         return 0;
5465                 }
5466
5467                 if (vcpu->arch.halt_request) {
5468                         vcpu->arch.halt_request = 0;
5469                         ret = kvm_emulate_halt(vcpu);
5470                         goto out;
5471                 }
5472
5473                 if (signal_pending(current))
5474                         goto out;
5475                 if (need_resched())
5476                         schedule();
5477         }
5478
5479         vmx->emulation_required = emulation_required(vcpu);
5480 out:
5481         return ret;
5482 }
5483
5484 /*
5485  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5486  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5487  */
5488 static int handle_pause(struct kvm_vcpu *vcpu)
5489 {
5490         skip_emulated_instruction(vcpu);
5491         kvm_vcpu_on_spin(vcpu);
5492
5493         return 1;
5494 }
5495
5496 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5497 {
5498         kvm_queue_exception(vcpu, UD_VECTOR);
5499         return 1;
5500 }
5501
5502 /*
5503  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5504  * We could reuse a single VMCS for all the L2 guests, but we also want the
5505  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5506  * allows keeping them loaded on the processor, and in the future will allow
5507  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5508  * every entry if they never change.
5509  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5510  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5511  *
5512  * The following functions allocate and free a vmcs02 in this pool.
5513  */
5514
5515 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5516 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5517 {
5518         struct vmcs02_list *item;
5519         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5520                 if (item->vmptr == vmx->nested.current_vmptr) {
5521                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5522                         return &item->vmcs02;
5523                 }
5524
5525         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5526                 /* Recycle the least recently used VMCS. */
5527                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5528                         struct vmcs02_list, list);
5529                 item->vmptr = vmx->nested.current_vmptr;
5530                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5531                 return &item->vmcs02;
5532         }
5533
5534         /* Create a new VMCS */
5535         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5536         if (!item)
5537                 return NULL;
5538         item->vmcs02.vmcs = alloc_vmcs();
5539         if (!item->vmcs02.vmcs) {
5540                 kfree(item);
5541                 return NULL;
5542         }
5543         loaded_vmcs_init(&item->vmcs02);
5544         item->vmptr = vmx->nested.current_vmptr;
5545         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5546         vmx->nested.vmcs02_num++;
5547         return &item->vmcs02;
5548 }
5549
5550 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5551 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5552 {
5553         struct vmcs02_list *item;
5554         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5555                 if (item->vmptr == vmptr) {
5556                         free_loaded_vmcs(&item->vmcs02);
5557                         list_del(&item->list);
5558                         kfree(item);
5559                         vmx->nested.vmcs02_num--;
5560                         return;
5561                 }
5562 }
5563
5564 /*
5565  * Free all VMCSs saved for this vcpu, except the one pointed by
5566  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5567  * currently used, if running L2), and vmcs01 when running L2.
5568  */
5569 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5570 {
5571         struct vmcs02_list *item, *n;
5572         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5573                 if (vmx->loaded_vmcs != &item->vmcs02)
5574                         free_loaded_vmcs(&item->vmcs02);
5575                 list_del(&item->list);
5576                 kfree(item);
5577         }
5578         vmx->nested.vmcs02_num = 0;
5579
5580         if (vmx->loaded_vmcs != &vmx->vmcs01)
5581                 free_loaded_vmcs(&vmx->vmcs01);
5582 }
5583
5584 /*
5585  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5586  * set the success or error code of an emulated VMX instruction, as specified
5587  * by Vol 2B, VMX Instruction Reference, "Conventions".
5588  */
5589 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5590 {
5591         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5592                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5593                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5594 }
5595
5596 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5597 {
5598         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5599                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5600                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5601                         | X86_EFLAGS_CF);
5602 }
5603
5604 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5605                                         u32 vm_instruction_error)
5606 {
5607         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5608                 /*
5609                  * failValid writes the error number to the current VMCS, which
5610                  * can't be done there isn't a current VMCS.
5611                  */
5612                 nested_vmx_failInvalid(vcpu);
5613                 return;
5614         }
5615         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5616                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5617                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5618                         | X86_EFLAGS_ZF);
5619         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5620         /*
5621          * We don't need to force a shadow sync because
5622          * VM_INSTRUCTION_ERROR is not shadowed
5623          */
5624 }
5625
5626 /*
5627  * Emulate the VMXON instruction.
5628  * Currently, we just remember that VMX is active, and do not save or even
5629  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5630  * do not currently need to store anything in that guest-allocated memory
5631  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5632  * argument is different from the VMXON pointer (which the spec says they do).
5633  */
5634 static int handle_vmon(struct kvm_vcpu *vcpu)
5635 {
5636         struct kvm_segment cs;
5637         struct vcpu_vmx *vmx = to_vmx(vcpu);
5638         struct vmcs *shadow_vmcs;
5639         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5640                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5641
5642         /* The Intel VMX Instruction Reference lists a bunch of bits that
5643          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5644          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5645          * Otherwise, we should fail with #UD. We test these now:
5646          */
5647         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5648             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5649             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5650                 kvm_queue_exception(vcpu, UD_VECTOR);
5651                 return 1;
5652         }
5653
5654         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5655         if (is_long_mode(vcpu) && !cs.l) {
5656                 kvm_queue_exception(vcpu, UD_VECTOR);
5657                 return 1;
5658         }
5659
5660         if (vmx_get_cpl(vcpu)) {
5661                 kvm_inject_gp(vcpu, 0);
5662                 return 1;
5663         }
5664         if (vmx->nested.vmxon) {
5665                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5666                 skip_emulated_instruction(vcpu);
5667                 return 1;
5668         }
5669
5670         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5671                         != VMXON_NEEDED_FEATURES) {
5672                 kvm_inject_gp(vcpu, 0);
5673                 return 1;
5674         }
5675
5676         if (enable_shadow_vmcs) {
5677                 shadow_vmcs = alloc_vmcs();
5678                 if (!shadow_vmcs)
5679                         return -ENOMEM;
5680                 /* mark vmcs as shadow */
5681                 shadow_vmcs->revision_id |= (1u << 31);
5682                 /* init shadow vmcs */
5683                 vmcs_clear(shadow_vmcs);
5684                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5685         }
5686
5687         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5688         vmx->nested.vmcs02_num = 0;
5689
5690         vmx->nested.vmxon = true;
5691
5692         skip_emulated_instruction(vcpu);
5693         nested_vmx_succeed(vcpu);
5694         return 1;
5695 }
5696
5697 /*
5698  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5699  * for running VMX instructions (except VMXON, whose prerequisites are
5700  * slightly different). It also specifies what exception to inject otherwise.
5701  */
5702 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5703 {
5704         struct kvm_segment cs;
5705         struct vcpu_vmx *vmx = to_vmx(vcpu);
5706
5707         if (!vmx->nested.vmxon) {
5708                 kvm_queue_exception(vcpu, UD_VECTOR);
5709                 return 0;
5710         }
5711
5712         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5713         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5714             (is_long_mode(vcpu) && !cs.l)) {
5715                 kvm_queue_exception(vcpu, UD_VECTOR);
5716                 return 0;
5717         }
5718
5719         if (vmx_get_cpl(vcpu)) {
5720                 kvm_inject_gp(vcpu, 0);
5721                 return 0;
5722         }
5723
5724         return 1;
5725 }
5726
5727 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5728 {
5729         u32 exec_control;
5730         if (enable_shadow_vmcs) {
5731                 if (vmx->nested.current_vmcs12 != NULL) {
5732                         /* copy to memory all shadowed fields in case
5733                            they were modified */
5734                         copy_shadow_to_vmcs12(vmx);
5735                         vmx->nested.sync_shadow_vmcs = false;
5736                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5737                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5738                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5739                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5740                 }
5741         }
5742         kunmap(vmx->nested.current_vmcs12_page);
5743         nested_release_page(vmx->nested.current_vmcs12_page);
5744 }
5745
5746 /*
5747  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5748  * just stops using VMX.
5749  */
5750 static void free_nested(struct vcpu_vmx *vmx)
5751 {
5752         if (!vmx->nested.vmxon)
5753                 return;
5754         vmx->nested.vmxon = false;
5755         if (vmx->nested.current_vmptr != -1ull) {
5756                 nested_release_vmcs12(vmx);
5757                 vmx->nested.current_vmptr = -1ull;
5758                 vmx->nested.current_vmcs12 = NULL;
5759         }
5760         if (enable_shadow_vmcs)
5761                 free_vmcs(vmx->nested.current_shadow_vmcs);
5762         /* Unpin physical memory we referred to in current vmcs02 */
5763         if (vmx->nested.apic_access_page) {
5764                 nested_release_page(vmx->nested.apic_access_page);
5765                 vmx->nested.apic_access_page = 0;
5766         }
5767
5768         nested_free_all_saved_vmcss(vmx);
5769 }
5770
5771 /* Emulate the VMXOFF instruction */
5772 static int handle_vmoff(struct kvm_vcpu *vcpu)
5773 {
5774         if (!nested_vmx_check_permission(vcpu))
5775                 return 1;
5776         free_nested(to_vmx(vcpu));
5777         skip_emulated_instruction(vcpu);
5778         nested_vmx_succeed(vcpu);
5779         return 1;
5780 }
5781
5782 /*
5783  * Decode the memory-address operand of a vmx instruction, as recorded on an
5784  * exit caused by such an instruction (run by a guest hypervisor).
5785  * On success, returns 0. When the operand is invalid, returns 1 and throws
5786  * #UD or #GP.
5787  */
5788 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5789                                  unsigned long exit_qualification,
5790                                  u32 vmx_instruction_info, gva_t *ret)
5791 {
5792         /*
5793          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5794          * Execution", on an exit, vmx_instruction_info holds most of the
5795          * addressing components of the operand. Only the displacement part
5796          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5797          * For how an actual address is calculated from all these components,
5798          * refer to Vol. 1, "Operand Addressing".
5799          */
5800         int  scaling = vmx_instruction_info & 3;
5801         int  addr_size = (vmx_instruction_info >> 7) & 7;
5802         bool is_reg = vmx_instruction_info & (1u << 10);
5803         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5804         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5805         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5806         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5807         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5808
5809         if (is_reg) {
5810                 kvm_queue_exception(vcpu, UD_VECTOR);
5811                 return 1;
5812         }
5813
5814         /* Addr = segment_base + offset */
5815         /* offset = base + [index * scale] + displacement */
5816         *ret = vmx_get_segment_base(vcpu, seg_reg);
5817         if (base_is_valid)
5818                 *ret += kvm_register_read(vcpu, base_reg);
5819         if (index_is_valid)
5820                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5821         *ret += exit_qualification; /* holds the displacement */
5822
5823         if (addr_size == 1) /* 32 bit */
5824                 *ret &= 0xffffffff;
5825
5826         /*
5827          * TODO: throw #GP (and return 1) in various cases that the VM*
5828          * instructions require it - e.g., offset beyond segment limit,
5829          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5830          * address, and so on. Currently these are not checked.
5831          */
5832         return 0;
5833 }
5834
5835 /* Emulate the VMCLEAR instruction */
5836 static int handle_vmclear(struct kvm_vcpu *vcpu)
5837 {
5838         struct vcpu_vmx *vmx = to_vmx(vcpu);
5839         gva_t gva;
5840         gpa_t vmptr;
5841         struct vmcs12 *vmcs12;
5842         struct page *page;
5843         struct x86_exception e;
5844
5845         if (!nested_vmx_check_permission(vcpu))
5846                 return 1;
5847
5848         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5849                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5850                 return 1;
5851
5852         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5853                                 sizeof(vmptr), &e)) {
5854                 kvm_inject_page_fault(vcpu, &e);
5855                 return 1;
5856         }
5857
5858         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5859                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5860                 skip_emulated_instruction(vcpu);
5861                 return 1;
5862         }
5863
5864         if (vmptr == vmx->nested.current_vmptr) {
5865                 nested_release_vmcs12(vmx);
5866                 vmx->nested.current_vmptr = -1ull;
5867                 vmx->nested.current_vmcs12 = NULL;
5868         }
5869
5870         page = nested_get_page(vcpu, vmptr);
5871         if (page == NULL) {
5872                 /*
5873                  * For accurate processor emulation, VMCLEAR beyond available
5874                  * physical memory should do nothing at all. However, it is
5875                  * possible that a nested vmx bug, not a guest hypervisor bug,
5876                  * resulted in this case, so let's shut down before doing any
5877                  * more damage:
5878                  */
5879                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5880                 return 1;
5881         }
5882         vmcs12 = kmap(page);
5883         vmcs12->launch_state = 0;
5884         kunmap(page);
5885         nested_release_page(page);
5886
5887         nested_free_vmcs02(vmx, vmptr);
5888
5889         skip_emulated_instruction(vcpu);
5890         nested_vmx_succeed(vcpu);
5891         return 1;
5892 }
5893
5894 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5895
5896 /* Emulate the VMLAUNCH instruction */
5897 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5898 {
5899         return nested_vmx_run(vcpu, true);
5900 }
5901
5902 /* Emulate the VMRESUME instruction */
5903 static int handle_vmresume(struct kvm_vcpu *vcpu)
5904 {
5905
5906         return nested_vmx_run(vcpu, false);
5907 }
5908
5909 enum vmcs_field_type {
5910         VMCS_FIELD_TYPE_U16 = 0,
5911         VMCS_FIELD_TYPE_U64 = 1,
5912         VMCS_FIELD_TYPE_U32 = 2,
5913         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5914 };
5915
5916 static inline int vmcs_field_type(unsigned long field)
5917 {
5918         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5919                 return VMCS_FIELD_TYPE_U32;
5920         return (field >> 13) & 0x3 ;
5921 }
5922
5923 static inline int vmcs_field_readonly(unsigned long field)
5924 {
5925         return (((field >> 10) & 0x3) == 1);
5926 }
5927
5928 /*
5929  * Read a vmcs12 field. Since these can have varying lengths and we return
5930  * one type, we chose the biggest type (u64) and zero-extend the return value
5931  * to that size. Note that the caller, handle_vmread, might need to use only
5932  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5933  * 64-bit fields are to be returned).
5934  */
5935 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5936                                         unsigned long field, u64 *ret)
5937 {
5938         short offset = vmcs_field_to_offset(field);
5939         char *p;
5940
5941         if (offset < 0)
5942                 return 0;
5943
5944         p = ((char *)(get_vmcs12(vcpu))) + offset;
5945
5946         switch (vmcs_field_type(field)) {
5947         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5948                 *ret = *((natural_width *)p);
5949                 return 1;
5950         case VMCS_FIELD_TYPE_U16:
5951                 *ret = *((u16 *)p);
5952                 return 1;
5953         case VMCS_FIELD_TYPE_U32:
5954                 *ret = *((u32 *)p);
5955                 return 1;
5956         case VMCS_FIELD_TYPE_U64:
5957                 *ret = *((u64 *)p);
5958                 return 1;
5959         default:
5960                 return 0; /* can never happen. */
5961         }
5962 }
5963
5964
5965 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5966                                     unsigned long field, u64 field_value){
5967         short offset = vmcs_field_to_offset(field);
5968         char *p = ((char *) get_vmcs12(vcpu)) + offset;
5969         if (offset < 0)
5970                 return false;
5971
5972         switch (vmcs_field_type(field)) {
5973         case VMCS_FIELD_TYPE_U16:
5974                 *(u16 *)p = field_value;
5975                 return true;
5976         case VMCS_FIELD_TYPE_U32:
5977                 *(u32 *)p = field_value;
5978                 return true;
5979         case VMCS_FIELD_TYPE_U64:
5980                 *(u64 *)p = field_value;
5981                 return true;
5982         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5983                 *(natural_width *)p = field_value;
5984                 return true;
5985         default:
5986                 return false; /* can never happen. */
5987         }
5988
5989 }
5990
5991 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5992 {
5993         int i;
5994         unsigned long field;
5995         u64 field_value;
5996         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5997         const unsigned long *fields = shadow_read_write_fields;
5998         const int num_fields = max_shadow_read_write_fields;
5999
6000         vmcs_load(shadow_vmcs);
6001
6002         for (i = 0; i < num_fields; i++) {
6003                 field = fields[i];
6004                 switch (vmcs_field_type(field)) {
6005                 case VMCS_FIELD_TYPE_U16:
6006                         field_value = vmcs_read16(field);
6007                         break;
6008                 case VMCS_FIELD_TYPE_U32:
6009                         field_value = vmcs_read32(field);
6010                         break;
6011                 case VMCS_FIELD_TYPE_U64:
6012                         field_value = vmcs_read64(field);
6013                         break;
6014                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6015                         field_value = vmcs_readl(field);
6016                         break;
6017                 }
6018                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6019         }
6020
6021         vmcs_clear(shadow_vmcs);
6022         vmcs_load(vmx->loaded_vmcs->vmcs);
6023 }
6024
6025 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6026 {
6027         const unsigned long *fields[] = {
6028                 shadow_read_write_fields,
6029                 shadow_read_only_fields
6030         };
6031         const int max_fields[] = {
6032                 max_shadow_read_write_fields,
6033                 max_shadow_read_only_fields
6034         };
6035         int i, q;
6036         unsigned long field;
6037         u64 field_value = 0;
6038         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6039
6040         vmcs_load(shadow_vmcs);
6041
6042         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6043                 for (i = 0; i < max_fields[q]; i++) {
6044                         field = fields[q][i];
6045                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6046
6047                         switch (vmcs_field_type(field)) {
6048                         case VMCS_FIELD_TYPE_U16:
6049                                 vmcs_write16(field, (u16)field_value);
6050                                 break;
6051                         case VMCS_FIELD_TYPE_U32:
6052                                 vmcs_write32(field, (u32)field_value);
6053                                 break;
6054                         case VMCS_FIELD_TYPE_U64:
6055                                 vmcs_write64(field, (u64)field_value);
6056                                 break;
6057                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6058                                 vmcs_writel(field, (long)field_value);
6059                                 break;
6060                         }
6061                 }
6062         }
6063
6064         vmcs_clear(shadow_vmcs);
6065         vmcs_load(vmx->loaded_vmcs->vmcs);
6066 }
6067
6068 /*
6069  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6070  * used before) all generate the same failure when it is missing.
6071  */
6072 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6073 {
6074         struct vcpu_vmx *vmx = to_vmx(vcpu);
6075         if (vmx->nested.current_vmptr == -1ull) {
6076                 nested_vmx_failInvalid(vcpu);
6077                 skip_emulated_instruction(vcpu);
6078                 return 0;
6079         }
6080         return 1;
6081 }
6082
6083 static int handle_vmread(struct kvm_vcpu *vcpu)
6084 {
6085         unsigned long field;
6086         u64 field_value;
6087         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6088         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6089         gva_t gva = 0;
6090
6091         if (!nested_vmx_check_permission(vcpu) ||
6092             !nested_vmx_check_vmcs12(vcpu))
6093                 return 1;
6094
6095         /* Decode instruction info and find the field to read */
6096         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6097         /* Read the field, zero-extended to a u64 field_value */
6098         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6099                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6100                 skip_emulated_instruction(vcpu);
6101                 return 1;
6102         }
6103         /*
6104          * Now copy part of this value to register or memory, as requested.
6105          * Note that the number of bits actually copied is 32 or 64 depending
6106          * on the guest's mode (32 or 64 bit), not on the given field's length.
6107          */
6108         if (vmx_instruction_info & (1u << 10)) {
6109                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6110                         field_value);
6111         } else {
6112                 if (get_vmx_mem_address(vcpu, exit_qualification,
6113                                 vmx_instruction_info, &gva))
6114                         return 1;
6115                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6116                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6117                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6118         }
6119
6120         nested_vmx_succeed(vcpu);
6121         skip_emulated_instruction(vcpu);
6122         return 1;
6123 }
6124
6125
6126 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6127 {
6128         unsigned long field;
6129         gva_t gva;
6130         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6131         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6132         /* The value to write might be 32 or 64 bits, depending on L1's long
6133          * mode, and eventually we need to write that into a field of several
6134          * possible lengths. The code below first zero-extends the value to 64
6135          * bit (field_value), and then copies only the approriate number of
6136          * bits into the vmcs12 field.
6137          */
6138         u64 field_value = 0;
6139         struct x86_exception e;
6140
6141         if (!nested_vmx_check_permission(vcpu) ||
6142             !nested_vmx_check_vmcs12(vcpu))
6143                 return 1;
6144
6145         if (vmx_instruction_info & (1u << 10))
6146                 field_value = kvm_register_read(vcpu,
6147                         (((vmx_instruction_info) >> 3) & 0xf));
6148         else {
6149                 if (get_vmx_mem_address(vcpu, exit_qualification,
6150                                 vmx_instruction_info, &gva))
6151                         return 1;
6152                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6153                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6154                         kvm_inject_page_fault(vcpu, &e);
6155                         return 1;
6156                 }
6157         }
6158
6159
6160         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6161         if (vmcs_field_readonly(field)) {
6162                 nested_vmx_failValid(vcpu,
6163                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6164                 skip_emulated_instruction(vcpu);
6165                 return 1;
6166         }
6167
6168         if (!vmcs12_write_any(vcpu, field, field_value)) {
6169                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6170                 skip_emulated_instruction(vcpu);
6171                 return 1;
6172         }
6173
6174         nested_vmx_succeed(vcpu);
6175         skip_emulated_instruction(vcpu);
6176         return 1;
6177 }
6178
6179 /* Emulate the VMPTRLD instruction */
6180 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6181 {
6182         struct vcpu_vmx *vmx = to_vmx(vcpu);
6183         gva_t gva;
6184         gpa_t vmptr;
6185         struct x86_exception e;
6186         u32 exec_control;
6187
6188         if (!nested_vmx_check_permission(vcpu))
6189                 return 1;
6190
6191         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6192                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6193                 return 1;
6194
6195         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6196                                 sizeof(vmptr), &e)) {
6197                 kvm_inject_page_fault(vcpu, &e);
6198                 return 1;
6199         }
6200
6201         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6202                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6203                 skip_emulated_instruction(vcpu);
6204                 return 1;
6205         }
6206
6207         if (vmx->nested.current_vmptr != vmptr) {
6208                 struct vmcs12 *new_vmcs12;
6209                 struct page *page;
6210                 page = nested_get_page(vcpu, vmptr);
6211                 if (page == NULL) {
6212                         nested_vmx_failInvalid(vcpu);
6213                         skip_emulated_instruction(vcpu);
6214                         return 1;
6215                 }
6216                 new_vmcs12 = kmap(page);
6217                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6218                         kunmap(page);
6219                         nested_release_page_clean(page);
6220                         nested_vmx_failValid(vcpu,
6221                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6222                         skip_emulated_instruction(vcpu);
6223                         return 1;
6224                 }
6225                 if (vmx->nested.current_vmptr != -1ull)
6226                         nested_release_vmcs12(vmx);
6227
6228                 vmx->nested.current_vmptr = vmptr;
6229                 vmx->nested.current_vmcs12 = new_vmcs12;
6230                 vmx->nested.current_vmcs12_page = page;
6231                 if (enable_shadow_vmcs) {
6232                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6233                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6234                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6235                         vmcs_write64(VMCS_LINK_POINTER,
6236                                      __pa(vmx->nested.current_shadow_vmcs));
6237                         vmx->nested.sync_shadow_vmcs = true;
6238                 }
6239         }
6240
6241         nested_vmx_succeed(vcpu);
6242         skip_emulated_instruction(vcpu);
6243         return 1;
6244 }
6245
6246 /* Emulate the VMPTRST instruction */
6247 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6248 {
6249         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6250         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6251         gva_t vmcs_gva;
6252         struct x86_exception e;
6253
6254         if (!nested_vmx_check_permission(vcpu))
6255                 return 1;
6256
6257         if (get_vmx_mem_address(vcpu, exit_qualification,
6258                         vmx_instruction_info, &vmcs_gva))
6259                 return 1;
6260         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6261         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6262                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6263                                  sizeof(u64), &e)) {
6264                 kvm_inject_page_fault(vcpu, &e);
6265                 return 1;
6266         }
6267         nested_vmx_succeed(vcpu);
6268         skip_emulated_instruction(vcpu);
6269         return 1;
6270 }
6271
6272 /*
6273  * The exit handlers return 1 if the exit was handled fully and guest execution
6274  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6275  * to be done to userspace and return 0.
6276  */
6277 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6278         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6279         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6280         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6281         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6282         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6283         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6284         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6285         [EXIT_REASON_CPUID]                   = handle_cpuid,
6286         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6287         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6288         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6289         [EXIT_REASON_HLT]                     = handle_halt,
6290         [EXIT_REASON_INVD]                    = handle_invd,
6291         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6292         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6293         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6294         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6295         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6296         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6297         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6298         [EXIT_REASON_VMREAD]                  = handle_vmread,
6299         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6300         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6301         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6302         [EXIT_REASON_VMON]                    = handle_vmon,
6303         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6304         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6305         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6306         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6307         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6308         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6309         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6310         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6311         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6312         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6313         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6314         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6315         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6316 };
6317
6318 static const int kvm_vmx_max_exit_handlers =
6319         ARRAY_SIZE(kvm_vmx_exit_handlers);
6320
6321 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6322                                        struct vmcs12 *vmcs12)
6323 {
6324         unsigned long exit_qualification;
6325         gpa_t bitmap, last_bitmap;
6326         unsigned int port;
6327         int size;
6328         u8 b;
6329
6330         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6331                 return 1;
6332
6333         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6334                 return 0;
6335
6336         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6337
6338         port = exit_qualification >> 16;
6339         size = (exit_qualification & 7) + 1;
6340
6341         last_bitmap = (gpa_t)-1;
6342         b = -1;
6343
6344         while (size > 0) {
6345                 if (port < 0x8000)
6346                         bitmap = vmcs12->io_bitmap_a;
6347                 else if (port < 0x10000)
6348                         bitmap = vmcs12->io_bitmap_b;
6349                 else
6350                         return 1;
6351                 bitmap += (port & 0x7fff) / 8;
6352
6353                 if (last_bitmap != bitmap)
6354                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6355                                 return 1;
6356                 if (b & (1 << (port & 7)))
6357                         return 1;
6358
6359                 port++;
6360                 size--;
6361                 last_bitmap = bitmap;
6362         }
6363
6364         return 0;
6365 }
6366
6367 /*
6368  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6369  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6370  * disinterest in the current event (read or write a specific MSR) by using an
6371  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6372  */
6373 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6374         struct vmcs12 *vmcs12, u32 exit_reason)
6375 {
6376         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6377         gpa_t bitmap;
6378
6379         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6380                 return 1;
6381
6382         /*
6383          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6384          * for the four combinations of read/write and low/high MSR numbers.
6385          * First we need to figure out which of the four to use:
6386          */
6387         bitmap = vmcs12->msr_bitmap;
6388         if (exit_reason == EXIT_REASON_MSR_WRITE)
6389                 bitmap += 2048;
6390         if (msr_index >= 0xc0000000) {
6391                 msr_index -= 0xc0000000;
6392                 bitmap += 1024;
6393         }
6394
6395         /* Then read the msr_index'th bit from this bitmap: */
6396         if (msr_index < 1024*8) {
6397                 unsigned char b;
6398                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6399                         return 1;
6400                 return 1 & (b >> (msr_index & 7));
6401         } else
6402                 return 1; /* let L1 handle the wrong parameter */
6403 }
6404
6405 /*
6406  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6407  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6408  * intercept (via guest_host_mask etc.) the current event.
6409  */
6410 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6411         struct vmcs12 *vmcs12)
6412 {
6413         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6414         int cr = exit_qualification & 15;
6415         int reg = (exit_qualification >> 8) & 15;
6416         unsigned long val = kvm_register_read(vcpu, reg);
6417
6418         switch ((exit_qualification >> 4) & 3) {
6419         case 0: /* mov to cr */
6420                 switch (cr) {
6421                 case 0:
6422                         if (vmcs12->cr0_guest_host_mask &
6423                             (val ^ vmcs12->cr0_read_shadow))
6424                                 return 1;
6425                         break;
6426                 case 3:
6427                         if ((vmcs12->cr3_target_count >= 1 &&
6428                                         vmcs12->cr3_target_value0 == val) ||
6429                                 (vmcs12->cr3_target_count >= 2 &&
6430                                         vmcs12->cr3_target_value1 == val) ||
6431                                 (vmcs12->cr3_target_count >= 3 &&
6432                                         vmcs12->cr3_target_value2 == val) ||
6433                                 (vmcs12->cr3_target_count >= 4 &&
6434                                         vmcs12->cr3_target_value3 == val))
6435                                 return 0;
6436                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6437                                 return 1;
6438                         break;
6439                 case 4:
6440                         if (vmcs12->cr4_guest_host_mask &
6441                             (vmcs12->cr4_read_shadow ^ val))
6442                                 return 1;
6443                         break;
6444                 case 8:
6445                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6446                                 return 1;
6447                         break;
6448                 }
6449                 break;
6450         case 2: /* clts */
6451                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6452                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6453                         return 1;
6454                 break;
6455         case 1: /* mov from cr */
6456                 switch (cr) {
6457                 case 3:
6458                         if (vmcs12->cpu_based_vm_exec_control &
6459                             CPU_BASED_CR3_STORE_EXITING)
6460                                 return 1;
6461                         break;
6462                 case 8:
6463                         if (vmcs12->cpu_based_vm_exec_control &
6464                             CPU_BASED_CR8_STORE_EXITING)
6465                                 return 1;
6466                         break;
6467                 }
6468                 break;
6469         case 3: /* lmsw */
6470                 /*
6471                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6472                  * cr0. Other attempted changes are ignored, with no exit.
6473                  */
6474                 if (vmcs12->cr0_guest_host_mask & 0xe &
6475                     (val ^ vmcs12->cr0_read_shadow))
6476                         return 1;
6477                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6478                     !(vmcs12->cr0_read_shadow & 0x1) &&
6479                     (val & 0x1))
6480                         return 1;
6481                 break;
6482         }
6483         return 0;
6484 }
6485
6486 /*
6487  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6488  * should handle it ourselves in L0 (and then continue L2). Only call this
6489  * when in is_guest_mode (L2).
6490  */
6491 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6492 {
6493         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6494         struct vcpu_vmx *vmx = to_vmx(vcpu);
6495         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6496         u32 exit_reason = vmx->exit_reason;
6497
6498         if (vmx->nested.nested_run_pending)
6499                 return 0;
6500
6501         if (unlikely(vmx->fail)) {
6502                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6503                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6504                 return 1;
6505         }
6506
6507         switch (exit_reason) {
6508         case EXIT_REASON_EXCEPTION_NMI:
6509                 if (!is_exception(intr_info))
6510                         return 0;
6511                 else if (is_page_fault(intr_info))
6512                         return enable_ept;
6513                 return vmcs12->exception_bitmap &
6514                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6515         case EXIT_REASON_EXTERNAL_INTERRUPT:
6516                 return 0;
6517         case EXIT_REASON_TRIPLE_FAULT:
6518                 return 1;
6519         case EXIT_REASON_PENDING_INTERRUPT:
6520                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6521         case EXIT_REASON_NMI_WINDOW:
6522                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6523         case EXIT_REASON_TASK_SWITCH:
6524                 return 1;
6525         case EXIT_REASON_CPUID:
6526                 return 1;
6527         case EXIT_REASON_HLT:
6528                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6529         case EXIT_REASON_INVD:
6530                 return 1;
6531         case EXIT_REASON_INVLPG:
6532                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6533         case EXIT_REASON_RDPMC:
6534                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6535         case EXIT_REASON_RDTSC:
6536                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6537         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6538         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6539         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6540         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6541         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6542                 /*
6543                  * VMX instructions trap unconditionally. This allows L1 to
6544                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6545                  */
6546                 return 1;
6547         case EXIT_REASON_CR_ACCESS:
6548                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6549         case EXIT_REASON_DR_ACCESS:
6550                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6551         case EXIT_REASON_IO_INSTRUCTION:
6552                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6553         case EXIT_REASON_MSR_READ:
6554         case EXIT_REASON_MSR_WRITE:
6555                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6556         case EXIT_REASON_INVALID_STATE:
6557                 return 1;
6558         case EXIT_REASON_MWAIT_INSTRUCTION:
6559                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6560         case EXIT_REASON_MONITOR_INSTRUCTION:
6561                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6562         case EXIT_REASON_PAUSE_INSTRUCTION:
6563                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6564                         nested_cpu_has2(vmcs12,
6565                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6566         case EXIT_REASON_MCE_DURING_VMENTRY:
6567                 return 0;
6568         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6569                 return 1;
6570         case EXIT_REASON_APIC_ACCESS:
6571                 return nested_cpu_has2(vmcs12,
6572                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6573         case EXIT_REASON_EPT_VIOLATION:
6574         case EXIT_REASON_EPT_MISCONFIG:
6575                 return 0;
6576         case EXIT_REASON_PREEMPTION_TIMER:
6577                 return vmcs12->pin_based_vm_exec_control &
6578                         PIN_BASED_VMX_PREEMPTION_TIMER;
6579         case EXIT_REASON_WBINVD:
6580                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6581         case EXIT_REASON_XSETBV:
6582                 return 1;
6583         default:
6584                 return 1;
6585         }
6586 }
6587
6588 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6589 {
6590         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6591         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6592 }
6593
6594 /*
6595  * The guest has exited.  See if we can fix it or if we need userspace
6596  * assistance.
6597  */
6598 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6599 {
6600         struct vcpu_vmx *vmx = to_vmx(vcpu);
6601         u32 exit_reason = vmx->exit_reason;
6602         u32 vectoring_info = vmx->idt_vectoring_info;
6603
6604         /* If guest state is invalid, start emulating */
6605         if (vmx->emulation_required)
6606                 return handle_invalid_guest_state(vcpu);
6607
6608         /*
6609          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6610          * we did not inject a still-pending event to L1 now because of
6611          * nested_run_pending, we need to re-enable this bit.
6612          */
6613         if (vmx->nested.nested_run_pending)
6614                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6615
6616         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6617             exit_reason == EXIT_REASON_VMRESUME))
6618                 vmx->nested.nested_run_pending = 1;
6619         else
6620                 vmx->nested.nested_run_pending = 0;
6621
6622         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6623                 nested_vmx_vmexit(vcpu);
6624                 return 1;
6625         }
6626
6627         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6628                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6629                 vcpu->run->fail_entry.hardware_entry_failure_reason
6630                         = exit_reason;
6631                 return 0;
6632         }
6633
6634         if (unlikely(vmx->fail)) {
6635                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6636                 vcpu->run->fail_entry.hardware_entry_failure_reason
6637                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6638                 return 0;
6639         }
6640
6641         /*
6642          * Note:
6643          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6644          * delivery event since it indicates guest is accessing MMIO.
6645          * The vm-exit can be triggered again after return to guest that
6646          * will cause infinite loop.
6647          */
6648         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6649                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6650                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6651                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6652                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6653                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6654                 vcpu->run->internal.ndata = 2;
6655                 vcpu->run->internal.data[0] = vectoring_info;
6656                 vcpu->run->internal.data[1] = exit_reason;
6657                 return 0;
6658         }
6659
6660         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6661             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6662                                         get_vmcs12(vcpu), vcpu)))) {
6663                 if (vmx_interrupt_allowed(vcpu)) {
6664                         vmx->soft_vnmi_blocked = 0;
6665                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6666                            vcpu->arch.nmi_pending) {
6667                         /*
6668                          * This CPU don't support us in finding the end of an
6669                          * NMI-blocked window if the guest runs with IRQs
6670                          * disabled. So we pull the trigger after 1 s of
6671                          * futile waiting, but inform the user about this.
6672                          */
6673                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6674                                "state on VCPU %d after 1 s timeout\n",
6675                                __func__, vcpu->vcpu_id);
6676                         vmx->soft_vnmi_blocked = 0;
6677                 }
6678         }
6679
6680         if (exit_reason < kvm_vmx_max_exit_handlers
6681             && kvm_vmx_exit_handlers[exit_reason])
6682                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6683         else {
6684                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6685                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6686         }
6687         return 0;
6688 }
6689
6690 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6691 {
6692         if (irr == -1 || tpr < irr) {
6693                 vmcs_write32(TPR_THRESHOLD, 0);
6694                 return;
6695         }
6696
6697         vmcs_write32(TPR_THRESHOLD, irr);
6698 }
6699
6700 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6701 {
6702         u32 sec_exec_control;
6703
6704         /*
6705          * There is not point to enable virtualize x2apic without enable
6706          * apicv
6707          */
6708         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6709                                 !vmx_vm_has_apicv(vcpu->kvm))
6710                 return;
6711
6712         if (!vm_need_tpr_shadow(vcpu->kvm))
6713                 return;
6714
6715         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6716
6717         if (set) {
6718                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6719                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6720         } else {
6721                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6722                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6723         }
6724         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6725
6726         vmx_set_msr_bitmap(vcpu);
6727 }
6728
6729 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6730 {
6731         u16 status;
6732         u8 old;
6733
6734         if (!vmx_vm_has_apicv(kvm))
6735                 return;
6736
6737         if (isr == -1)
6738                 isr = 0;
6739
6740         status = vmcs_read16(GUEST_INTR_STATUS);
6741         old = status >> 8;
6742         if (isr != old) {
6743                 status &= 0xff;
6744                 status |= isr << 8;
6745                 vmcs_write16(GUEST_INTR_STATUS, status);
6746         }
6747 }
6748
6749 static void vmx_set_rvi(int vector)
6750 {
6751         u16 status;
6752         u8 old;
6753
6754         status = vmcs_read16(GUEST_INTR_STATUS);
6755         old = (u8)status & 0xff;
6756         if ((u8)vector != old) {
6757                 status &= ~0xff;
6758                 status |= (u8)vector;
6759                 vmcs_write16(GUEST_INTR_STATUS, status);
6760         }
6761 }
6762
6763 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6764 {
6765         if (max_irr == -1)
6766                 return;
6767
6768         vmx_set_rvi(max_irr);
6769 }
6770
6771 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6772 {
6773         if (!vmx_vm_has_apicv(vcpu->kvm))
6774                 return;
6775
6776         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6777         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6778         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6779         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6780 }
6781
6782 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6783 {
6784         u32 exit_intr_info;
6785
6786         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6787               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6788                 return;
6789
6790         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6791         exit_intr_info = vmx->exit_intr_info;
6792
6793         /* Handle machine checks before interrupts are enabled */
6794         if (is_machine_check(exit_intr_info))
6795                 kvm_machine_check();
6796
6797         /* We need to handle NMIs before interrupts are enabled */
6798         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6799             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6800                 kvm_before_handle_nmi(&vmx->vcpu);
6801                 asm("int $2");
6802                 kvm_after_handle_nmi(&vmx->vcpu);
6803         }
6804 }
6805
6806 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6807 {
6808         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6809
6810         /*
6811          * If external interrupt exists, IF bit is set in rflags/eflags on the
6812          * interrupt stack frame, and interrupt will be enabled on a return
6813          * from interrupt handler.
6814          */
6815         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6816                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6817                 unsigned int vector;
6818                 unsigned long entry;
6819                 gate_desc *desc;
6820                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6821 #ifdef CONFIG_X86_64
6822                 unsigned long tmp;
6823 #endif
6824
6825                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6826                 desc = (gate_desc *)vmx->host_idt_base + vector;
6827                 entry = gate_offset(*desc);
6828                 asm volatile(
6829 #ifdef CONFIG_X86_64
6830                         "mov %%" _ASM_SP ", %[sp]\n\t"
6831                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6832                         "push $%c[ss]\n\t"
6833                         "push %[sp]\n\t"
6834 #endif
6835                         "pushf\n\t"
6836                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6837                         __ASM_SIZE(push) " $%c[cs]\n\t"
6838                         "call *%[entry]\n\t"
6839                         :
6840 #ifdef CONFIG_X86_64
6841                         [sp]"=&r"(tmp)
6842 #endif
6843                         :
6844                         [entry]"r"(entry),
6845                         [ss]"i"(__KERNEL_DS),
6846                         [cs]"i"(__KERNEL_CS)
6847                         );
6848         } else
6849                 local_irq_enable();
6850 }
6851
6852 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6853 {
6854         u32 exit_intr_info;
6855         bool unblock_nmi;
6856         u8 vector;
6857         bool idtv_info_valid;
6858
6859         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6860
6861         if (cpu_has_virtual_nmis()) {
6862                 if (vmx->nmi_known_unmasked)
6863                         return;
6864                 /*
6865                  * Can't use vmx->exit_intr_info since we're not sure what
6866                  * the exit reason is.
6867                  */
6868                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6869                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6870                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6871                 /*
6872                  * SDM 3: 27.7.1.2 (September 2008)
6873                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6874                  * a guest IRET fault.
6875                  * SDM 3: 23.2.2 (September 2008)
6876                  * Bit 12 is undefined in any of the following cases:
6877                  *  If the VM exit sets the valid bit in the IDT-vectoring
6878                  *   information field.
6879                  *  If the VM exit is due to a double fault.
6880                  */
6881                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6882                     vector != DF_VECTOR && !idtv_info_valid)
6883                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6884                                       GUEST_INTR_STATE_NMI);
6885                 else
6886                         vmx->nmi_known_unmasked =
6887                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6888                                   & GUEST_INTR_STATE_NMI);
6889         } else if (unlikely(vmx->soft_vnmi_blocked))
6890                 vmx->vnmi_blocked_time +=
6891                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6892 }
6893
6894 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6895                                       u32 idt_vectoring_info,
6896                                       int instr_len_field,
6897                                       int error_code_field)
6898 {
6899         u8 vector;
6900         int type;
6901         bool idtv_info_valid;
6902
6903         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6904
6905         vcpu->arch.nmi_injected = false;
6906         kvm_clear_exception_queue(vcpu);
6907         kvm_clear_interrupt_queue(vcpu);
6908
6909         if (!idtv_info_valid)
6910                 return;
6911
6912         kvm_make_request(KVM_REQ_EVENT, vcpu);
6913
6914         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6915         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6916
6917         switch (type) {
6918         case INTR_TYPE_NMI_INTR:
6919                 vcpu->arch.nmi_injected = true;
6920                 /*
6921                  * SDM 3: 27.7.1.2 (September 2008)
6922                  * Clear bit "block by NMI" before VM entry if a NMI
6923                  * delivery faulted.
6924                  */
6925                 vmx_set_nmi_mask(vcpu, false);
6926                 break;
6927         case INTR_TYPE_SOFT_EXCEPTION:
6928                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6929                 /* fall through */
6930         case INTR_TYPE_HARD_EXCEPTION:
6931                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6932                         u32 err = vmcs_read32(error_code_field);
6933                         kvm_queue_exception_e(vcpu, vector, err);
6934                 } else
6935                         kvm_queue_exception(vcpu, vector);
6936                 break;
6937         case INTR_TYPE_SOFT_INTR:
6938                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6939                 /* fall through */
6940         case INTR_TYPE_EXT_INTR:
6941                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6942                 break;
6943         default:
6944                 break;
6945         }
6946 }
6947
6948 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6949 {
6950         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6951                                   VM_EXIT_INSTRUCTION_LEN,
6952                                   IDT_VECTORING_ERROR_CODE);
6953 }
6954
6955 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6956 {
6957         __vmx_complete_interrupts(vcpu,
6958                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6959                                   VM_ENTRY_INSTRUCTION_LEN,
6960                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6961
6962         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6963 }
6964
6965 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6966 {
6967         int i, nr_msrs;
6968         struct perf_guest_switch_msr *msrs;
6969
6970         msrs = perf_guest_get_msrs(&nr_msrs);
6971
6972         if (!msrs)
6973                 return;
6974
6975         for (i = 0; i < nr_msrs; i++)
6976                 if (msrs[i].host == msrs[i].guest)
6977                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6978                 else
6979                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6980                                         msrs[i].host);
6981 }
6982
6983 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6984 {
6985         struct vcpu_vmx *vmx = to_vmx(vcpu);
6986         unsigned long debugctlmsr;
6987
6988         /* Record the guest's net vcpu time for enforced NMI injections. */
6989         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6990                 vmx->entry_time = ktime_get();
6991
6992         /* Don't enter VMX if guest state is invalid, let the exit handler
6993            start emulation until we arrive back to a valid state */
6994         if (vmx->emulation_required)
6995                 return;
6996
6997         if (vmx->nested.sync_shadow_vmcs) {
6998                 copy_vmcs12_to_shadow(vmx);
6999                 vmx->nested.sync_shadow_vmcs = false;
7000         }
7001
7002         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7003                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7004         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7005                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7006
7007         /* When single-stepping over STI and MOV SS, we must clear the
7008          * corresponding interruptibility bits in the guest state. Otherwise
7009          * vmentry fails as it then expects bit 14 (BS) in pending debug
7010          * exceptions being set, but that's not correct for the guest debugging
7011          * case. */
7012         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7013                 vmx_set_interrupt_shadow(vcpu, 0);
7014
7015         atomic_switch_perf_msrs(vmx);
7016         debugctlmsr = get_debugctlmsr();
7017
7018         vmx->__launched = vmx->loaded_vmcs->launched;
7019         asm(
7020                 /* Store host registers */
7021                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7022                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7023                 "push %%" _ASM_CX " \n\t"
7024                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7025                 "je 1f \n\t"
7026                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7027                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7028                 "1: \n\t"
7029                 /* Reload cr2 if changed */
7030                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7031                 "mov %%cr2, %%" _ASM_DX " \n\t"
7032                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7033                 "je 2f \n\t"
7034                 "mov %%" _ASM_AX", %%cr2 \n\t"
7035                 "2: \n\t"
7036                 /* Check if vmlaunch of vmresume is needed */
7037                 "cmpl $0, %c[launched](%0) \n\t"
7038                 /* Load guest registers.  Don't clobber flags. */
7039                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7040                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7041                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7042                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7043                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7044                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7045 #ifdef CONFIG_X86_64
7046                 "mov %c[r8](%0),  %%r8  \n\t"
7047                 "mov %c[r9](%0),  %%r9  \n\t"
7048                 "mov %c[r10](%0), %%r10 \n\t"
7049                 "mov %c[r11](%0), %%r11 \n\t"
7050                 "mov %c[r12](%0), %%r12 \n\t"
7051                 "mov %c[r13](%0), %%r13 \n\t"
7052                 "mov %c[r14](%0), %%r14 \n\t"
7053                 "mov %c[r15](%0), %%r15 \n\t"
7054 #endif
7055                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7056
7057                 /* Enter guest mode */
7058                 "jne 1f \n\t"
7059                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7060                 "jmp 2f \n\t"
7061                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7062                 "2: "
7063                 /* Save guest registers, load host registers, keep flags */
7064                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7065                 "pop %0 \n\t"
7066                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7067                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7068                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7069                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7070                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7071                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7072                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7073 #ifdef CONFIG_X86_64
7074                 "mov %%r8,  %c[r8](%0) \n\t"
7075                 "mov %%r9,  %c[r9](%0) \n\t"
7076                 "mov %%r10, %c[r10](%0) \n\t"
7077                 "mov %%r11, %c[r11](%0) \n\t"
7078                 "mov %%r12, %c[r12](%0) \n\t"
7079                 "mov %%r13, %c[r13](%0) \n\t"
7080                 "mov %%r14, %c[r14](%0) \n\t"
7081                 "mov %%r15, %c[r15](%0) \n\t"
7082 #endif
7083                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7084                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7085
7086                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7087                 "setbe %c[fail](%0) \n\t"
7088                 ".pushsection .rodata \n\t"
7089                 ".global vmx_return \n\t"
7090                 "vmx_return: " _ASM_PTR " 2b \n\t"
7091                 ".popsection"
7092               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7093                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7094                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7095                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7096                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7097                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7098                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7099                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7100                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7101                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7102                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7103 #ifdef CONFIG_X86_64
7104                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7105                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7106                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7107                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7108                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7109                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7110                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7111                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7112 #endif
7113                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7114                 [wordsize]"i"(sizeof(ulong))
7115               : "cc", "memory"
7116 #ifdef CONFIG_X86_64
7117                 , "rax", "rbx", "rdi", "rsi"
7118                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7119 #else
7120                 , "eax", "ebx", "edi", "esi"
7121 #endif
7122               );
7123
7124         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7125         if (debugctlmsr)
7126                 update_debugctlmsr(debugctlmsr);
7127
7128 #ifndef CONFIG_X86_64
7129         /*
7130          * The sysexit path does not restore ds/es, so we must set them to
7131          * a reasonable value ourselves.
7132          *
7133          * We can't defer this to vmx_load_host_state() since that function
7134          * may be executed in interrupt context, which saves and restore segments
7135          * around it, nullifying its effect.
7136          */
7137         loadsegment(ds, __USER_DS);
7138         loadsegment(es, __USER_DS);
7139 #endif
7140
7141         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7142                                   | (1 << VCPU_EXREG_RFLAGS)
7143                                   | (1 << VCPU_EXREG_CPL)
7144                                   | (1 << VCPU_EXREG_PDPTR)
7145                                   | (1 << VCPU_EXREG_SEGMENTS)
7146                                   | (1 << VCPU_EXREG_CR3));
7147         vcpu->arch.regs_dirty = 0;
7148
7149         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7150
7151         vmx->loaded_vmcs->launched = 1;
7152
7153         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7154         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7155
7156         vmx_complete_atomic_exit(vmx);
7157         vmx_recover_nmi_blocking(vmx);
7158         vmx_complete_interrupts(vmx);
7159 }
7160
7161 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7162 {
7163         struct vcpu_vmx *vmx = to_vmx(vcpu);
7164
7165         free_vpid(vmx);
7166         free_nested(vmx);
7167         free_loaded_vmcs(vmx->loaded_vmcs);
7168         kfree(vmx->guest_msrs);
7169         kvm_vcpu_uninit(vcpu);
7170         kmem_cache_free(kvm_vcpu_cache, vmx);
7171 }
7172
7173 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7174 {
7175         int err;
7176         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7177         int cpu;
7178
7179         if (!vmx)
7180                 return ERR_PTR(-ENOMEM);
7181
7182         allocate_vpid(vmx);
7183
7184         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7185         if (err)
7186                 goto free_vcpu;
7187
7188         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7189         err = -ENOMEM;
7190         if (!vmx->guest_msrs) {
7191                 goto uninit_vcpu;
7192         }
7193
7194         vmx->loaded_vmcs = &vmx->vmcs01;
7195         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7196         if (!vmx->loaded_vmcs->vmcs)
7197                 goto free_msrs;
7198         if (!vmm_exclusive)
7199                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7200         loaded_vmcs_init(vmx->loaded_vmcs);
7201         if (!vmm_exclusive)
7202                 kvm_cpu_vmxoff();
7203
7204         cpu = get_cpu();
7205         vmx_vcpu_load(&vmx->vcpu, cpu);
7206         vmx->vcpu.cpu = cpu;
7207         err = vmx_vcpu_setup(vmx);
7208         vmx_vcpu_put(&vmx->vcpu);
7209         put_cpu();
7210         if (err)
7211                 goto free_vmcs;
7212         if (vm_need_virtualize_apic_accesses(kvm)) {
7213                 err = alloc_apic_access_page(kvm);
7214                 if (err)
7215                         goto free_vmcs;
7216         }
7217
7218         if (enable_ept) {
7219                 if (!kvm->arch.ept_identity_map_addr)
7220                         kvm->arch.ept_identity_map_addr =
7221                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7222                 err = -ENOMEM;
7223                 if (alloc_identity_pagetable(kvm) != 0)
7224                         goto free_vmcs;
7225                 if (!init_rmode_identity_map(kvm))
7226                         goto free_vmcs;
7227         }
7228
7229         vmx->nested.current_vmptr = -1ull;
7230         vmx->nested.current_vmcs12 = NULL;
7231
7232         return &vmx->vcpu;
7233
7234 free_vmcs:
7235         free_loaded_vmcs(vmx->loaded_vmcs);
7236 free_msrs:
7237         kfree(vmx->guest_msrs);
7238 uninit_vcpu:
7239         kvm_vcpu_uninit(&vmx->vcpu);
7240 free_vcpu:
7241         free_vpid(vmx);
7242         kmem_cache_free(kvm_vcpu_cache, vmx);
7243         return ERR_PTR(err);
7244 }
7245
7246 static void __init vmx_check_processor_compat(void *rtn)
7247 {
7248         struct vmcs_config vmcs_conf;
7249
7250         *(int *)rtn = 0;
7251         if (setup_vmcs_config(&vmcs_conf) < 0)
7252                 *(int *)rtn = -EIO;
7253         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7254                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7255                                 smp_processor_id());
7256                 *(int *)rtn = -EIO;
7257         }
7258 }
7259
7260 static int get_ept_level(void)
7261 {
7262         return VMX_EPT_DEFAULT_GAW + 1;
7263 }
7264
7265 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7266 {
7267         u64 ret;
7268
7269         /* For VT-d and EPT combination
7270          * 1. MMIO: always map as UC
7271          * 2. EPT with VT-d:
7272          *   a. VT-d without snooping control feature: can't guarantee the
7273          *      result, try to trust guest.
7274          *   b. VT-d with snooping control feature: snooping control feature of
7275          *      VT-d engine can guarantee the cache correctness. Just set it
7276          *      to WB to keep consistent with host. So the same as item 3.
7277          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7278          *    consistent with host MTRR
7279          */
7280         if (is_mmio)
7281                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7282         else if (vcpu->kvm->arch.iommu_domain &&
7283                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7284                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7285                       VMX_EPT_MT_EPTE_SHIFT;
7286         else
7287                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7288                         | VMX_EPT_IPAT_BIT;
7289
7290         return ret;
7291 }
7292
7293 static int vmx_get_lpage_level(void)
7294 {
7295         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7296                 return PT_DIRECTORY_LEVEL;
7297         else
7298                 /* For shadow and EPT supported 1GB page */
7299                 return PT_PDPE_LEVEL;
7300 }
7301
7302 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7303 {
7304         struct kvm_cpuid_entry2 *best;
7305         struct vcpu_vmx *vmx = to_vmx(vcpu);
7306         u32 exec_control;
7307
7308         vmx->rdtscp_enabled = false;
7309         if (vmx_rdtscp_supported()) {
7310                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7311                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7312                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7313                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7314                                 vmx->rdtscp_enabled = true;
7315                         else {
7316                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7317                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7318                                                 exec_control);
7319                         }
7320                 }
7321         }
7322
7323         /* Exposing INVPCID only when PCID is exposed */
7324         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7325         if (vmx_invpcid_supported() &&
7326             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7327             guest_cpuid_has_pcid(vcpu)) {
7328                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7329                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7330                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7331                              exec_control);
7332         } else {
7333                 if (cpu_has_secondary_exec_ctrls()) {
7334                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7335                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7336                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7337                                      exec_control);
7338                 }
7339                 if (best)
7340                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7341         }
7342 }
7343
7344 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7345 {
7346         if (func == 1 && nested)
7347                 entry->ecx |= bit(X86_FEATURE_VMX);
7348 }
7349
7350 /*
7351  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7352  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7353  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7354  * guest in a way that will both be appropriate to L1's requests, and our
7355  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7356  * function also has additional necessary side-effects, like setting various
7357  * vcpu->arch fields.
7358  */
7359 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7360 {
7361         struct vcpu_vmx *vmx = to_vmx(vcpu);
7362         u32 exec_control;
7363
7364         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7365         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7366         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7367         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7368         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7369         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7370         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7371         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7372         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7373         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7374         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7375         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7376         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7377         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7378         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7379         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7380         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7381         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7382         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7383         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7384         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7385         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7386         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7387         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7388         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7389         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7390         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7391         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7392         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7393         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7394         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7395         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7396         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7397         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7398         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7399         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7400
7401         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7402         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7403                 vmcs12->vm_entry_intr_info_field);
7404         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7405                 vmcs12->vm_entry_exception_error_code);
7406         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7407                 vmcs12->vm_entry_instruction_len);
7408         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7409                 vmcs12->guest_interruptibility_info);
7410         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7411         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7412         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7413         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7414                 vmcs12->guest_pending_dbg_exceptions);
7415         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7416         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7417
7418         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7419
7420         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7421                 (vmcs_config.pin_based_exec_ctrl |
7422                  vmcs12->pin_based_vm_exec_control));
7423
7424         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7425                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7426                              vmcs12->vmx_preemption_timer_value);
7427
7428         /*
7429          * Whether page-faults are trapped is determined by a combination of
7430          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7431          * If enable_ept, L0 doesn't care about page faults and we should
7432          * set all of these to L1's desires. However, if !enable_ept, L0 does
7433          * care about (at least some) page faults, and because it is not easy
7434          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7435          * to exit on each and every L2 page fault. This is done by setting
7436          * MASK=MATCH=0 and (see below) EB.PF=1.
7437          * Note that below we don't need special code to set EB.PF beyond the
7438          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7439          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7440          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7441          *
7442          * A problem with this approach (when !enable_ept) is that L1 may be
7443          * injected with more page faults than it asked for. This could have
7444          * caused problems, but in practice existing hypervisors don't care.
7445          * To fix this, we will need to emulate the PFEC checking (on the L1
7446          * page tables), using walk_addr(), when injecting PFs to L1.
7447          */
7448         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7449                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7450         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7451                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7452
7453         if (cpu_has_secondary_exec_ctrls()) {
7454                 u32 exec_control = vmx_secondary_exec_control(vmx);
7455                 if (!vmx->rdtscp_enabled)
7456                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7457                 /* Take the following fields only from vmcs12 */
7458                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7459                 if (nested_cpu_has(vmcs12,
7460                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7461                         exec_control |= vmcs12->secondary_vm_exec_control;
7462
7463                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7464                         /*
7465                          * Translate L1 physical address to host physical
7466                          * address for vmcs02. Keep the page pinned, so this
7467                          * physical address remains valid. We keep a reference
7468                          * to it so we can release it later.
7469                          */
7470                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7471                                 nested_release_page(vmx->nested.apic_access_page);
7472                         vmx->nested.apic_access_page =
7473                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7474                         /*
7475                          * If translation failed, no matter: This feature asks
7476                          * to exit when accessing the given address, and if it
7477                          * can never be accessed, this feature won't do
7478                          * anything anyway.
7479                          */
7480                         if (!vmx->nested.apic_access_page)
7481                                 exec_control &=
7482                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7483                         else
7484                                 vmcs_write64(APIC_ACCESS_ADDR,
7485                                   page_to_phys(vmx->nested.apic_access_page));
7486                 }
7487
7488                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7489         }
7490
7491
7492         /*
7493          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7494          * Some constant fields are set here by vmx_set_constant_host_state().
7495          * Other fields are different per CPU, and will be set later when
7496          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7497          */
7498         vmx_set_constant_host_state(vmx);
7499
7500         /*
7501          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7502          * entry, but only if the current (host) sp changed from the value
7503          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7504          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7505          * here we just force the write to happen on entry.
7506          */
7507         vmx->host_rsp = 0;
7508
7509         exec_control = vmx_exec_control(vmx); /* L0's desires */
7510         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7511         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7512         exec_control &= ~CPU_BASED_TPR_SHADOW;
7513         exec_control |= vmcs12->cpu_based_vm_exec_control;
7514         /*
7515          * Merging of IO and MSR bitmaps not currently supported.
7516          * Rather, exit every time.
7517          */
7518         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7519         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7520         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7521
7522         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7523
7524         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7525          * bitwise-or of what L1 wants to trap for L2, and what we want to
7526          * trap. Note that CR0.TS also needs updating - we do this later.
7527          */
7528         update_exception_bitmap(vcpu);
7529         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7530         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7531
7532         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7533         vmcs_write32(VM_EXIT_CONTROLS,
7534                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7535         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7536                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7537
7538         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7539                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7540         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7541                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7542
7543
7544         set_cr4_guest_host_mask(vmx);
7545
7546         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7547                 vmcs_write64(TSC_OFFSET,
7548                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7549         else
7550                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7551
7552         if (enable_vpid) {
7553                 /*
7554                  * Trivially support vpid by letting L2s share their parent
7555                  * L1's vpid. TODO: move to a more elaborate solution, giving
7556                  * each L2 its own vpid and exposing the vpid feature to L1.
7557                  */
7558                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7559                 vmx_flush_tlb(vcpu);
7560         }
7561
7562         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7563                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7564         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7565                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7566         else
7567                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7568         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7569         vmx_set_efer(vcpu, vcpu->arch.efer);
7570
7571         /*
7572          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7573          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7574          * The CR0_READ_SHADOW is what L2 should have expected to read given
7575          * the specifications by L1; It's not enough to take
7576          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7577          * have more bits than L1 expected.
7578          */
7579         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7580         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7581
7582         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7583         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7584
7585         /* shadow page tables on either EPT or shadow page tables */
7586         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7587         kvm_mmu_reset_context(vcpu);
7588
7589         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7590         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7591 }
7592
7593 /*
7594  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7595  * for running an L2 nested guest.
7596  */
7597 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7598 {
7599         struct vmcs12 *vmcs12;
7600         struct vcpu_vmx *vmx = to_vmx(vcpu);
7601         int cpu;
7602         struct loaded_vmcs *vmcs02;
7603         bool ia32e;
7604
7605         if (!nested_vmx_check_permission(vcpu) ||
7606             !nested_vmx_check_vmcs12(vcpu))
7607                 return 1;
7608
7609         skip_emulated_instruction(vcpu);
7610         vmcs12 = get_vmcs12(vcpu);
7611
7612         if (enable_shadow_vmcs)
7613                 copy_shadow_to_vmcs12(vmx);
7614
7615         /*
7616          * The nested entry process starts with enforcing various prerequisites
7617          * on vmcs12 as required by the Intel SDM, and act appropriately when
7618          * they fail: As the SDM explains, some conditions should cause the
7619          * instruction to fail, while others will cause the instruction to seem
7620          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7621          * To speed up the normal (success) code path, we should avoid checking
7622          * for misconfigurations which will anyway be caught by the processor
7623          * when using the merged vmcs02.
7624          */
7625         if (vmcs12->launch_state == launch) {
7626                 nested_vmx_failValid(vcpu,
7627                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7628                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7629                 return 1;
7630         }
7631
7632         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7633                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7634                 return 1;
7635         }
7636
7637         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7638                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7639                 /*TODO: Also verify bits beyond physical address width are 0*/
7640                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7641                 return 1;
7642         }
7643
7644         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7645                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7646                 /*TODO: Also verify bits beyond physical address width are 0*/
7647                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7648                 return 1;
7649         }
7650
7651         if (vmcs12->vm_entry_msr_load_count > 0 ||
7652             vmcs12->vm_exit_msr_load_count > 0 ||
7653             vmcs12->vm_exit_msr_store_count > 0) {
7654                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7655                                     __func__);
7656                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7657                 return 1;
7658         }
7659
7660         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7661               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7662             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7663               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7664             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7665               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7666             !vmx_control_verify(vmcs12->vm_exit_controls,
7667               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7668             !vmx_control_verify(vmcs12->vm_entry_controls,
7669               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7670         {
7671                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7672                 return 1;
7673         }
7674
7675         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7676             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7677                 nested_vmx_failValid(vcpu,
7678                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7679                 return 1;
7680         }
7681
7682         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7683             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7684                 nested_vmx_entry_failure(vcpu, vmcs12,
7685                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7686                 return 1;
7687         }
7688         if (vmcs12->vmcs_link_pointer != -1ull) {
7689                 nested_vmx_entry_failure(vcpu, vmcs12,
7690                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7691                 return 1;
7692         }
7693
7694         /*
7695          * If the load IA32_EFER VM-entry control is 1, the following checks
7696          * are performed on the field for the IA32_EFER MSR:
7697          * - Bits reserved in the IA32_EFER MSR must be 0.
7698          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7699          *   the IA-32e mode guest VM-exit control. It must also be identical
7700          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7701          *   CR0.PG) is 1.
7702          */
7703         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7704                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7705                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7706                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7707                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7708                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7709                         nested_vmx_entry_failure(vcpu, vmcs12,
7710                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7711                         return 1;
7712                 }
7713         }
7714
7715         /*
7716          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7717          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7718          * the values of the LMA and LME bits in the field must each be that of
7719          * the host address-space size VM-exit control.
7720          */
7721         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7722                 ia32e = (vmcs12->vm_exit_controls &
7723                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7724                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7725                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7726                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7727                         nested_vmx_entry_failure(vcpu, vmcs12,
7728                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7729                         return 1;
7730                 }
7731         }
7732
7733         /*
7734          * We're finally done with prerequisite checking, and can start with
7735          * the nested entry.
7736          */
7737
7738         vmcs02 = nested_get_current_vmcs02(vmx);
7739         if (!vmcs02)
7740                 return -ENOMEM;
7741
7742         enter_guest_mode(vcpu);
7743
7744         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7745
7746         cpu = get_cpu();
7747         vmx->loaded_vmcs = vmcs02;
7748         vmx_vcpu_put(vcpu);
7749         vmx_vcpu_load(vcpu, cpu);
7750         vcpu->cpu = cpu;
7751         put_cpu();
7752
7753         vmx_segment_cache_clear(vmx);
7754
7755         vmcs12->launch_state = 1;
7756
7757         prepare_vmcs02(vcpu, vmcs12);
7758
7759         /*
7760          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7761          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7762          * returned as far as L1 is concerned. It will only return (and set
7763          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7764          */
7765         return 1;
7766 }
7767
7768 /*
7769  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7770  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7771  * This function returns the new value we should put in vmcs12.guest_cr0.
7772  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7773  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7774  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7775  *     didn't trap the bit, because if L1 did, so would L0).
7776  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7777  *     been modified by L2, and L1 knows it. So just leave the old value of
7778  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7779  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7780  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7781  *     changed these bits, and therefore they need to be updated, but L0
7782  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7783  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7784  */
7785 static inline unsigned long
7786 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7787 {
7788         return
7789         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7790         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7791         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7792                         vcpu->arch.cr0_guest_owned_bits));
7793 }
7794
7795 static inline unsigned long
7796 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7797 {
7798         return
7799         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7800         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7801         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7802                         vcpu->arch.cr4_guest_owned_bits));
7803 }
7804
7805 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7806                                        struct vmcs12 *vmcs12)
7807 {
7808         u32 idt_vectoring;
7809         unsigned int nr;
7810
7811         if (vcpu->arch.exception.pending) {
7812                 nr = vcpu->arch.exception.nr;
7813                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7814
7815                 if (kvm_exception_is_soft(nr)) {
7816                         vmcs12->vm_exit_instruction_len =
7817                                 vcpu->arch.event_exit_inst_len;
7818                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7819                 } else
7820                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7821
7822                 if (vcpu->arch.exception.has_error_code) {
7823                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7824                         vmcs12->idt_vectoring_error_code =
7825                                 vcpu->arch.exception.error_code;
7826                 }
7827
7828                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7829         } else if (vcpu->arch.nmi_pending) {
7830                 vmcs12->idt_vectoring_info_field =
7831                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7832         } else if (vcpu->arch.interrupt.pending) {
7833                 nr = vcpu->arch.interrupt.nr;
7834                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7835
7836                 if (vcpu->arch.interrupt.soft) {
7837                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
7838                         vmcs12->vm_entry_instruction_len =
7839                                 vcpu->arch.event_exit_inst_len;
7840                 } else
7841                         idt_vectoring |= INTR_TYPE_EXT_INTR;
7842
7843                 vmcs12->idt_vectoring_info_field = idt_vectoring;
7844         }
7845 }
7846
7847 /*
7848  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7849  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7850  * and this function updates it to reflect the changes to the guest state while
7851  * L2 was running (and perhaps made some exits which were handled directly by L0
7852  * without going back to L1), and to reflect the exit reason.
7853  * Note that we do not have to copy here all VMCS fields, just those that
7854  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7855  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7856  * which already writes to vmcs12 directly.
7857  */
7858 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7859 {
7860         /* update guest state fields: */
7861         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7862         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7863
7864         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7865         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7866         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7867         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7868
7869         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7870         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7871         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7872         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7873         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7874         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7875         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7876         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7877         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7878         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7879         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7880         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7881         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7882         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7883         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7884         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7885         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7886         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7887         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7888         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7889         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7890         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7891         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7892         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7893         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7894         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7895         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7896         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7897         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7898         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7899         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7900         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7901         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7902         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7903         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7904         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7905
7906         vmcs12->guest_interruptibility_info =
7907                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7908         vmcs12->guest_pending_dbg_exceptions =
7909                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7910
7911         vmcs12->vm_entry_controls =
7912                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7913                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7914
7915         /* TODO: These cannot have changed unless we have MSR bitmaps and
7916          * the relevant bit asks not to trap the change */
7917         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7918         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
7919                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7920         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7921         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7922         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7923
7924         /* update exit information fields: */
7925
7926         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7927         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7928
7929         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7930         if ((vmcs12->vm_exit_intr_info &
7931              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7932             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7933                 vmcs12->vm_exit_intr_error_code =
7934                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7935         vmcs12->idt_vectoring_info_field = 0;
7936         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7937         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7938
7939         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7940                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7941                  * instead of reading the real value. */
7942                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7943
7944                 /*
7945                  * Transfer the event that L0 or L1 may wanted to inject into
7946                  * L2 to IDT_VECTORING_INFO_FIELD.
7947                  */
7948                 vmcs12_save_pending_event(vcpu, vmcs12);
7949         }
7950
7951         /*
7952          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7953          * preserved above and would only end up incorrectly in L1.
7954          */
7955         vcpu->arch.nmi_injected = false;
7956         kvm_clear_exception_queue(vcpu);
7957         kvm_clear_interrupt_queue(vcpu);
7958 }
7959
7960 /*
7961  * A part of what we need to when the nested L2 guest exits and we want to
7962  * run its L1 parent, is to reset L1's guest state to the host state specified
7963  * in vmcs12.
7964  * This function is to be called not only on normal nested exit, but also on
7965  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7966  * Failures During or After Loading Guest State").
7967  * This function should be called when the active VMCS is L1's (vmcs01).
7968  */
7969 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7970                                    struct vmcs12 *vmcs12)
7971 {
7972         struct kvm_segment seg;
7973
7974         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7975                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7976         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7977                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7978         else
7979                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7980         vmx_set_efer(vcpu, vcpu->arch.efer);
7981
7982         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7983         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7984         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
7985         /*
7986          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7987          * actually changed, because it depends on the current state of
7988          * fpu_active (which may have changed).
7989          * Note that vmx_set_cr0 refers to efer set above.
7990          */
7991         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7992         /*
7993          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7994          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7995          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7996          */
7997         update_exception_bitmap(vcpu);
7998         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7999         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8000
8001         /*
8002          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8003          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8004          */
8005         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8006         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8007
8008         /* shadow page tables on either EPT or shadow page tables */
8009         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8010         kvm_mmu_reset_context(vcpu);
8011
8012         if (enable_vpid) {
8013                 /*
8014                  * Trivially support vpid by letting L2s share their parent
8015                  * L1's vpid. TODO: move to a more elaborate solution, giving
8016                  * each L2 its own vpid and exposing the vpid feature to L1.
8017                  */
8018                 vmx_flush_tlb(vcpu);
8019         }
8020
8021
8022         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8023         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8024         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8025         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8026         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8027
8028         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8029                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8030         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8031                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8032                         vmcs12->host_ia32_perf_global_ctrl);
8033
8034         /* Set L1 segment info according to Intel SDM
8035             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8036         seg = (struct kvm_segment) {
8037                 .base = 0,
8038                 .limit = 0xFFFFFFFF,
8039                 .selector = vmcs12->host_cs_selector,
8040                 .type = 11,
8041                 .present = 1,
8042                 .s = 1,
8043                 .g = 1
8044         };
8045         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8046                 seg.l = 1;
8047         else
8048                 seg.db = 1;
8049         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8050         seg = (struct kvm_segment) {
8051                 .base = 0,
8052                 .limit = 0xFFFFFFFF,
8053                 .type = 3,
8054                 .present = 1,
8055                 .s = 1,
8056                 .db = 1,
8057                 .g = 1
8058         };
8059         seg.selector = vmcs12->host_ds_selector;
8060         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8061         seg.selector = vmcs12->host_es_selector;
8062         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8063         seg.selector = vmcs12->host_ss_selector;
8064         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8065         seg.selector = vmcs12->host_fs_selector;
8066         seg.base = vmcs12->host_fs_base;
8067         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8068         seg.selector = vmcs12->host_gs_selector;
8069         seg.base = vmcs12->host_gs_base;
8070         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8071         seg = (struct kvm_segment) {
8072                 .base = vmcs12->host_tr_base,
8073                 .limit = 0x67,
8074                 .selector = vmcs12->host_tr_selector,
8075                 .type = 11,
8076                 .present = 1
8077         };
8078         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8079
8080         kvm_set_dr(vcpu, 7, 0x400);
8081         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8082 }
8083
8084 /*
8085  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8086  * and modify vmcs12 to make it see what it would expect to see there if
8087  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8088  */
8089 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8090 {
8091         struct vcpu_vmx *vmx = to_vmx(vcpu);
8092         int cpu;
8093         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8094
8095         /* trying to cancel vmlaunch/vmresume is a bug */
8096         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8097
8098         leave_guest_mode(vcpu);
8099         prepare_vmcs12(vcpu, vmcs12);
8100
8101         cpu = get_cpu();
8102         vmx->loaded_vmcs = &vmx->vmcs01;
8103         vmx_vcpu_put(vcpu);
8104         vmx_vcpu_load(vcpu, cpu);
8105         vcpu->cpu = cpu;
8106         put_cpu();
8107
8108         vmx_segment_cache_clear(vmx);
8109
8110         /* if no vmcs02 cache requested, remove the one we used */
8111         if (VMCS02_POOL_SIZE == 0)
8112                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8113
8114         load_vmcs12_host_state(vcpu, vmcs12);
8115
8116         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8117         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8118
8119         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8120         vmx->host_rsp = 0;
8121
8122         /* Unpin physical memory we referred to in vmcs02 */
8123         if (vmx->nested.apic_access_page) {
8124                 nested_release_page(vmx->nested.apic_access_page);
8125                 vmx->nested.apic_access_page = 0;
8126         }
8127
8128         /*
8129          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8130          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8131          * success or failure flag accordingly.
8132          */
8133         if (unlikely(vmx->fail)) {
8134                 vmx->fail = 0;
8135                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8136         } else
8137                 nested_vmx_succeed(vcpu);
8138         if (enable_shadow_vmcs)
8139                 vmx->nested.sync_shadow_vmcs = true;
8140 }
8141
8142 /*
8143  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8144  * 23.7 "VM-entry failures during or after loading guest state" (this also
8145  * lists the acceptable exit-reason and exit-qualification parameters).
8146  * It should only be called before L2 actually succeeded to run, and when
8147  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8148  */
8149 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8150                         struct vmcs12 *vmcs12,
8151                         u32 reason, unsigned long qualification)
8152 {
8153         load_vmcs12_host_state(vcpu, vmcs12);
8154         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8155         vmcs12->exit_qualification = qualification;
8156         nested_vmx_succeed(vcpu);
8157         if (enable_shadow_vmcs)
8158                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8159 }
8160
8161 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8162                                struct x86_instruction_info *info,
8163                                enum x86_intercept_stage stage)
8164 {
8165         return X86EMUL_CONTINUE;
8166 }
8167
8168 static struct kvm_x86_ops vmx_x86_ops = {
8169         .cpu_has_kvm_support = cpu_has_kvm_support,
8170         .disabled_by_bios = vmx_disabled_by_bios,
8171         .hardware_setup = hardware_setup,
8172         .hardware_unsetup = hardware_unsetup,
8173         .check_processor_compatibility = vmx_check_processor_compat,
8174         .hardware_enable = hardware_enable,
8175         .hardware_disable = hardware_disable,
8176         .cpu_has_accelerated_tpr = report_flexpriority,
8177
8178         .vcpu_create = vmx_create_vcpu,
8179         .vcpu_free = vmx_free_vcpu,
8180         .vcpu_reset = vmx_vcpu_reset,
8181
8182         .prepare_guest_switch = vmx_save_host_state,
8183         .vcpu_load = vmx_vcpu_load,
8184         .vcpu_put = vmx_vcpu_put,
8185
8186         .update_db_bp_intercept = update_exception_bitmap,
8187         .get_msr = vmx_get_msr,
8188         .set_msr = vmx_set_msr,
8189         .get_segment_base = vmx_get_segment_base,
8190         .get_segment = vmx_get_segment,
8191         .set_segment = vmx_set_segment,
8192         .get_cpl = vmx_get_cpl,
8193         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8194         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8195         .decache_cr3 = vmx_decache_cr3,
8196         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8197         .set_cr0 = vmx_set_cr0,
8198         .set_cr3 = vmx_set_cr3,
8199         .set_cr4 = vmx_set_cr4,
8200         .set_efer = vmx_set_efer,
8201         .get_idt = vmx_get_idt,
8202         .set_idt = vmx_set_idt,
8203         .get_gdt = vmx_get_gdt,
8204         .set_gdt = vmx_set_gdt,
8205         .set_dr7 = vmx_set_dr7,
8206         .cache_reg = vmx_cache_reg,
8207         .get_rflags = vmx_get_rflags,
8208         .set_rflags = vmx_set_rflags,
8209         .fpu_activate = vmx_fpu_activate,
8210         .fpu_deactivate = vmx_fpu_deactivate,
8211
8212         .tlb_flush = vmx_flush_tlb,
8213
8214         .run = vmx_vcpu_run,
8215         .handle_exit = vmx_handle_exit,
8216         .skip_emulated_instruction = skip_emulated_instruction,
8217         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8218         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8219         .patch_hypercall = vmx_patch_hypercall,
8220         .set_irq = vmx_inject_irq,
8221         .set_nmi = vmx_inject_nmi,
8222         .queue_exception = vmx_queue_exception,
8223         .cancel_injection = vmx_cancel_injection,
8224         .interrupt_allowed = vmx_interrupt_allowed,
8225         .nmi_allowed = vmx_nmi_allowed,
8226         .get_nmi_mask = vmx_get_nmi_mask,
8227         .set_nmi_mask = vmx_set_nmi_mask,
8228         .enable_nmi_window = enable_nmi_window,
8229         .enable_irq_window = enable_irq_window,
8230         .update_cr8_intercept = update_cr8_intercept,
8231         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8232         .vm_has_apicv = vmx_vm_has_apicv,
8233         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8234         .hwapic_irr_update = vmx_hwapic_irr_update,
8235         .hwapic_isr_update = vmx_hwapic_isr_update,
8236         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8237         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8238
8239         .set_tss_addr = vmx_set_tss_addr,
8240         .get_tdp_level = get_ept_level,
8241         .get_mt_mask = vmx_get_mt_mask,
8242
8243         .get_exit_info = vmx_get_exit_info,
8244
8245         .get_lpage_level = vmx_get_lpage_level,
8246
8247         .cpuid_update = vmx_cpuid_update,
8248
8249         .rdtscp_supported = vmx_rdtscp_supported,
8250         .invpcid_supported = vmx_invpcid_supported,
8251
8252         .set_supported_cpuid = vmx_set_supported_cpuid,
8253
8254         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8255
8256         .set_tsc_khz = vmx_set_tsc_khz,
8257         .read_tsc_offset = vmx_read_tsc_offset,
8258         .write_tsc_offset = vmx_write_tsc_offset,
8259         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8260         .compute_tsc_offset = vmx_compute_tsc_offset,
8261         .read_l1_tsc = vmx_read_l1_tsc,
8262
8263         .set_tdp_cr3 = vmx_set_cr3,
8264
8265         .check_intercept = vmx_check_intercept,
8266         .handle_external_intr = vmx_handle_external_intr,
8267 };
8268
8269 static int __init vmx_init(void)
8270 {
8271         int r, i, msr;
8272
8273         rdmsrl_safe(MSR_EFER, &host_efer);
8274
8275         for (i = 0; i < NR_VMX_MSR; ++i)
8276                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8277
8278         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8279         if (!vmx_io_bitmap_a)
8280                 return -ENOMEM;
8281
8282         r = -ENOMEM;
8283
8284         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8285         if (!vmx_io_bitmap_b)
8286                 goto out;
8287
8288         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8289         if (!vmx_msr_bitmap_legacy)
8290                 goto out1;
8291
8292         vmx_msr_bitmap_legacy_x2apic =
8293                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8294         if (!vmx_msr_bitmap_legacy_x2apic)
8295                 goto out2;
8296
8297         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8298         if (!vmx_msr_bitmap_longmode)
8299                 goto out3;
8300
8301         vmx_msr_bitmap_longmode_x2apic =
8302                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8303         if (!vmx_msr_bitmap_longmode_x2apic)
8304                 goto out4;
8305         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8306         if (!vmx_vmread_bitmap)
8307                 goto out5;
8308
8309         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8310         if (!vmx_vmwrite_bitmap)
8311                 goto out6;
8312
8313         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8314         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8315         /* shadowed read/write fields */
8316         for (i = 0; i < max_shadow_read_write_fields; i++) {
8317                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8318                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8319         }
8320         /* shadowed read only fields */
8321         for (i = 0; i < max_shadow_read_only_fields; i++)
8322                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8323
8324         /*
8325          * Allow direct access to the PC debug port (it is often used for I/O
8326          * delays, but the vmexits simply slow things down).
8327          */
8328         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8329         clear_bit(0x80, vmx_io_bitmap_a);
8330
8331         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8332
8333         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8334         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8335
8336         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8337
8338         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8339                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8340         if (r)
8341                 goto out7;
8342
8343 #ifdef CONFIG_KEXEC
8344         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8345                            crash_vmclear_local_loaded_vmcss);
8346 #endif
8347
8348         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8349         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8350         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8351         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8352         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8353         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8354         memcpy(vmx_msr_bitmap_legacy_x2apic,
8355                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8356         memcpy(vmx_msr_bitmap_longmode_x2apic,
8357                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8358
8359         if (enable_apicv) {
8360                 for (msr = 0x800; msr <= 0x8ff; msr++)
8361                         vmx_disable_intercept_msr_read_x2apic(msr);
8362
8363                 /* According SDM, in x2apic mode, the whole id reg is used.
8364                  * But in KVM, it only use the highest eight bits. Need to
8365                  * intercept it */
8366                 vmx_enable_intercept_msr_read_x2apic(0x802);
8367                 /* TMCCT */
8368                 vmx_enable_intercept_msr_read_x2apic(0x839);
8369                 /* TPR */
8370                 vmx_disable_intercept_msr_write_x2apic(0x808);
8371                 /* EOI */
8372                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8373                 /* SELF-IPI */
8374                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8375         }
8376
8377         if (enable_ept) {
8378                 kvm_mmu_set_mask_ptes(0ull,
8379                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8380                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8381                         0ull, VMX_EPT_EXECUTABLE_MASK);
8382                 ept_set_mmio_spte_mask();
8383                 kvm_enable_tdp();
8384         } else
8385                 kvm_disable_tdp();
8386
8387         return 0;
8388
8389 out7:
8390         free_page((unsigned long)vmx_vmwrite_bitmap);
8391 out6:
8392         free_page((unsigned long)vmx_vmread_bitmap);
8393 out5:
8394         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8395 out4:
8396         free_page((unsigned long)vmx_msr_bitmap_longmode);
8397 out3:
8398         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8399 out2:
8400         free_page((unsigned long)vmx_msr_bitmap_legacy);
8401 out1:
8402         free_page((unsigned long)vmx_io_bitmap_b);
8403 out:
8404         free_page((unsigned long)vmx_io_bitmap_a);
8405         return r;
8406 }
8407
8408 static void __exit vmx_exit(void)
8409 {
8410         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8411         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8412         free_page((unsigned long)vmx_msr_bitmap_legacy);
8413         free_page((unsigned long)vmx_msr_bitmap_longmode);
8414         free_page((unsigned long)vmx_io_bitmap_b);
8415         free_page((unsigned long)vmx_io_bitmap_a);
8416         free_page((unsigned long)vmx_vmwrite_bitmap);
8417         free_page((unsigned long)vmx_vmread_bitmap);
8418
8419 #ifdef CONFIG_KEXEC
8420         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8421         synchronize_rcu();
8422 #endif
8423
8424         kvm_exit();
8425 }
8426
8427 module_init(vmx_init)
8428 module_exit(vmx_exit)