arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 111 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 112 #define KVM_VM_CR0_ALWAYS_ON                                            \
 113         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 114 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 115         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 116          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 117
 118 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 119 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 120
 121 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 122
 123 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 124
 125 /*
 126  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 127  * ple_gap:    upper bound on the amount of time between two successive
 128  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 129  *             According to test, this time is usually smaller than 128 cycles.
 130  * ple_window: upper bound on the amount of time a guest is allowed to execute
 131  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 132  *             less than 2^12 cycles
 133  * Time is measured based on a counter that runs at the same rate as the TSC,
 134  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 135  */
 136 #define KVM_VMX_DEFAULT_PLE_GAP           128
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 141                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 142
 143 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 144 module_param(ple_gap, int, S_IRUGO);
 145
 146 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 147 module_param(ple_window, int, S_IRUGO);
 148
 149 /* Default doubles per-vcpu window every exit. */
 150 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 151 module_param(ple_window_grow, int, S_IRUGO);
 152
 153 /* Default resets per-vcpu window every exit to ple_window. */
 154 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 155 module_param(ple_window_shrink, int, S_IRUGO);
 156
 157 /* Default is to compute the maximum so we can never overflow. */
 158 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 159 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 160 module_param(ple_window_max, int, S_IRUGO);
 161
 162 extern const ulong vmx_return;
 163
 164 #define NR_AUTOLOAD_MSRS 8
 165 #define VMCS02_POOL_SIZE 1
 166
 167 struct vmcs {
 168         u32 revision_id;
 169         u32 abort;
 170         char data[0];
 171 };
 172
 173 /*
 174  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 175  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 176  * loaded on this CPU (so we can clear them if the CPU goes down).
 177  */
 178 struct loaded_vmcs {
 179         struct vmcs *vmcs;
 180         int cpu;
 181         int launched;
 182         struct list_head loaded_vmcss_on_cpu_link;
 183 };
 184
 185 struct shared_msr_entry {
 186         unsigned index;
 187         u64 data;
 188         u64 mask;
 189 };
 190
 191 /*
 192  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 193  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 194  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 195  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 196  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 197  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 198  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 199  * underlying hardware which will be used to run L2.
 200  * This structure is packed to ensure that its layout is identical across
 201  * machines (necessary for live migration).
 202  * If there are changes in this struct, VMCS12_REVISION must be changed.
 203  */
 204 typedef u64 natural_width;
 205 struct __packed vmcs12 {
 206         /* According to the Intel spec, a VMCS region must start with the
 207          * following two fields. Then follow implementation-specific data.
 208          */
 209         u32 revision_id;
 210         u32 abort;
 211
 212         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 213         u32 padding[7]; /* room for future expansion */
 214
 215         u64 io_bitmap_a;
 216         u64 io_bitmap_b;
 217         u64 msr_bitmap;
 218         u64 vm_exit_msr_store_addr;
 219         u64 vm_exit_msr_load_addr;
 220         u64 vm_entry_msr_load_addr;
 221         u64 tsc_offset;
 222         u64 virtual_apic_page_addr;
 223         u64 apic_access_addr;
 224         u64 posted_intr_desc_addr;
 225         u64 ept_pointer;
 226         u64 eoi_exit_bitmap0;
 227         u64 eoi_exit_bitmap1;
 228         u64 eoi_exit_bitmap2;
 229         u64 eoi_exit_bitmap3;
 230         u64 xss_exit_bitmap;
 231         u64 guest_physical_address;
 232         u64 vmcs_link_pointer;
 233         u64 guest_ia32_debugctl;
 234         u64 guest_ia32_pat;
 235         u64 guest_ia32_efer;
 236         u64 guest_ia32_perf_global_ctrl;
 237         u64 guest_pdptr0;
 238         u64 guest_pdptr1;
 239         u64 guest_pdptr2;
 240         u64 guest_pdptr3;
 241         u64 guest_bndcfgs;
 242         u64 host_ia32_pat;
 243         u64 host_ia32_efer;
 244         u64 host_ia32_perf_global_ctrl;
 245         u64 padding64[8]; /* room for future expansion */
 246         /*
 247          * To allow migration of L1 (complete with its L2 guests) between
 248          * machines of different natural widths (32 or 64 bit), we cannot have
 249          * unsigned long fields with no explict size. We use u64 (aliased
 250          * natural_width) instead. Luckily, x86 is little-endian.
 251          */
 252         natural_width cr0_guest_host_mask;
 253         natural_width cr4_guest_host_mask;
 254         natural_width cr0_read_shadow;
 255         natural_width cr4_read_shadow;
 256         natural_width cr3_target_value0;
 257         natural_width cr3_target_value1;
 258         natural_width cr3_target_value2;
 259         natural_width cr3_target_value3;
 260         natural_width exit_qualification;
 261         natural_width guest_linear_address;
 262         natural_width guest_cr0;
 263         natural_width guest_cr3;
 264         natural_width guest_cr4;
 265         natural_width guest_es_base;
 266         natural_width guest_cs_base;
 267         natural_width guest_ss_base;
 268         natural_width guest_ds_base;
 269         natural_width guest_fs_base;
 270         natural_width guest_gs_base;
 271         natural_width guest_ldtr_base;
 272         natural_width guest_tr_base;
 273         natural_width guest_gdtr_base;
 274         natural_width guest_idtr_base;
 275         natural_width guest_dr7;
 276         natural_width guest_rsp;
 277         natural_width guest_rip;
 278         natural_width guest_rflags;
 279         natural_width guest_pending_dbg_exceptions;
 280         natural_width guest_sysenter_esp;
 281         natural_width guest_sysenter_eip;
 282         natural_width host_cr0;
 283         natural_width host_cr3;
 284         natural_width host_cr4;
 285         natural_width host_fs_base;
 286         natural_width host_gs_base;
 287         natural_width host_tr_base;
 288         natural_width host_gdtr_base;
 289         natural_width host_idtr_base;
 290         natural_width host_ia32_sysenter_esp;
 291         natural_width host_ia32_sysenter_eip;
 292         natural_width host_rsp;
 293         natural_width host_rip;
 294         natural_width paddingl[8]; /* room for future expansion */
 295         u32 pin_based_vm_exec_control;
 296         u32 cpu_based_vm_exec_control;
 297         u32 exception_bitmap;
 298         u32 page_fault_error_code_mask;
 299         u32 page_fault_error_code_match;
 300         u32 cr3_target_count;
 301         u32 vm_exit_controls;
 302         u32 vm_exit_msr_store_count;
 303         u32 vm_exit_msr_load_count;
 304         u32 vm_entry_controls;
 305         u32 vm_entry_msr_load_count;
 306         u32 vm_entry_intr_info_field;
 307         u32 vm_entry_exception_error_code;
 308         u32 vm_entry_instruction_len;
 309         u32 tpr_threshold;
 310         u32 secondary_vm_exec_control;
 311         u32 vm_instruction_error;
 312         u32 vm_exit_reason;
 313         u32 vm_exit_intr_info;
 314         u32 vm_exit_intr_error_code;
 315         u32 idt_vectoring_info_field;
 316         u32 idt_vectoring_error_code;
 317         u32 vm_exit_instruction_len;
 318         u32 vmx_instruction_info;
 319         u32 guest_es_limit;
 320         u32 guest_cs_limit;
 321         u32 guest_ss_limit;
 322         u32 guest_ds_limit;
 323         u32 guest_fs_limit;
 324         u32 guest_gs_limit;
 325         u32 guest_ldtr_limit;
 326         u32 guest_tr_limit;
 327         u32 guest_gdtr_limit;
 328         u32 guest_idtr_limit;
 329         u32 guest_es_ar_bytes;
 330         u32 guest_cs_ar_bytes;
 331         u32 guest_ss_ar_bytes;
 332         u32 guest_ds_ar_bytes;
 333         u32 guest_fs_ar_bytes;
 334         u32 guest_gs_ar_bytes;
 335         u32 guest_ldtr_ar_bytes;
 336         u32 guest_tr_ar_bytes;
 337         u32 guest_interruptibility_info;
 338         u32 guest_activity_state;
 339         u32 guest_sysenter_cs;
 340         u32 host_ia32_sysenter_cs;
 341         u32 vmx_preemption_timer_value;
 342         u32 padding32[7]; /* room for future expansion */
 343         u16 virtual_processor_id;
 344         u16 posted_intr_nv;
 345         u16 guest_es_selector;
 346         u16 guest_cs_selector;
 347         u16 guest_ss_selector;
 348         u16 guest_ds_selector;
 349         u16 guest_fs_selector;
 350         u16 guest_gs_selector;
 351         u16 guest_ldtr_selector;
 352         u16 guest_tr_selector;
 353         u16 guest_intr_status;
 354         u16 host_es_selector;
 355         u16 host_cs_selector;
 356         u16 host_ss_selector;
 357         u16 host_ds_selector;
 358         u16 host_fs_selector;
 359         u16 host_gs_selector;
 360         u16 host_tr_selector;
 361 };
 362
 363 /*
 364  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 365  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 366  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 367  */
 368 #define VMCS12_REVISION 0x11e57ed0
 369
 370 /*
 371  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 372  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 373  * current implementation, 4K are reserved to avoid future complications.
 374  */
 375 #define VMCS12_SIZE 0x1000
 376
 377 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 378 struct vmcs02_list {
 379         struct list_head list;
 380         gpa_t vmptr;
 381         struct loaded_vmcs vmcs02;
 382 };
 383
 384 /*
 385  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 386  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 387  */
 388 struct nested_vmx {
 389         /* Has the level1 guest done vmxon? */
 390         bool vmxon;
 391         gpa_t vmxon_ptr;
 392
 393         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 394         gpa_t current_vmptr;
 395         /* The host-usable pointer to the above */
 396         struct page *current_vmcs12_page;
 397         struct vmcs12 *current_vmcs12;
 398         struct vmcs *current_shadow_vmcs;
 399         /*
 400          * Indicates if the shadow vmcs must be updated with the
 401          * data hold by vmcs12
 402          */
 403         bool sync_shadow_vmcs;
 404
 405         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 406         struct list_head vmcs02_pool;
 407         int vmcs02_num;
 408         u64 vmcs01_tsc_offset;
 409         /* L2 must run next, and mustn't decide to exit to L1. */
 410         bool nested_run_pending;
 411         /*
 412          * Guest pages referred to in vmcs02 with host-physical pointers, so
 413          * we must keep them pinned while L2 runs.
 414          */
 415         struct page *apic_access_page;
 416         struct page *virtual_apic_page;
 417         struct page *pi_desc_page;
 418         struct pi_desc *pi_desc;
 419         bool pi_pending;
 420         u16 posted_intr_nv;
 421         u64 msr_ia32_feature_control;
 422
 423         struct hrtimer preemption_timer;
 424         bool preemption_timer_expired;
 425
 426         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 427         u64 vmcs01_debugctl;
 428
 429         u16 vpid02;
 430         u16 last_vpid;
 431
 432         u32 nested_vmx_procbased_ctls_low;
 433         u32 nested_vmx_procbased_ctls_high;
 434         u32 nested_vmx_true_procbased_ctls_low;
 435         u32 nested_vmx_secondary_ctls_low;
 436         u32 nested_vmx_secondary_ctls_high;
 437         u32 nested_vmx_pinbased_ctls_low;
 438         u32 nested_vmx_pinbased_ctls_high;
 439         u32 nested_vmx_exit_ctls_low;
 440         u32 nested_vmx_exit_ctls_high;
 441         u32 nested_vmx_true_exit_ctls_low;
 442         u32 nested_vmx_entry_ctls_low;
 443         u32 nested_vmx_entry_ctls_high;
 444         u32 nested_vmx_true_entry_ctls_low;
 445         u32 nested_vmx_misc_low;
 446         u32 nested_vmx_misc_high;
 447         u32 nested_vmx_ept_caps;
 448         u32 nested_vmx_vpid_caps;
 449 };
 450
 451 #define POSTED_INTR_ON  0
 452 #define POSTED_INTR_SN  1
 453
 454 /* Posted-Interrupt Descriptor */
 455 struct pi_desc {
 456         u32 pir[8];     /* Posted interrupt requested */
 457         union {
 458                 struct {
 459                                 /* bit 256 - Outstanding Notification */
 460                         u16     on      : 1,
 461                                 /* bit 257 - Suppress Notification */
 462                                 sn      : 1,
 463                                 /* bit 271:258 - Reserved */
 464                                 rsvd_1  : 14;
 465                                 /* bit 279:272 - Notification Vector */
 466                         u8      nv;
 467                                 /* bit 287:280 - Reserved */
 468                         u8      rsvd_2;
 469                                 /* bit 319:288 - Notification Destination */
 470                         u32     ndst;
 471                 };
 472                 u64 control;
 473         };
 474         u32 rsvd[6];
 475 } __aligned(64);
 476
 477 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 478 {
 479         return test_and_set_bit(POSTED_INTR_ON,
 480                         (unsigned long *)&pi_desc->control);
 481 }
 482
 483 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 484 {
 485         return test_and_clear_bit(POSTED_INTR_ON,
 486                         (unsigned long *)&pi_desc->control);
 487 }
 488
 489 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 490 {
 491         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 492 }
 493
 494 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 495 {
 496         return clear_bit(POSTED_INTR_SN,
 497                         (unsigned long *)&pi_desc->control);
 498 }
 499
 500 static inline void pi_set_sn(struct pi_desc *pi_desc)
 501 {
 502         return set_bit(POSTED_INTR_SN,
 503                         (unsigned long *)&pi_desc->control);
 504 }
 505
 506 static inline int pi_test_on(struct pi_desc *pi_desc)
 507 {
 508         return test_bit(POSTED_INTR_ON,
 509                         (unsigned long *)&pi_desc->control);
 510 }
 511
 512 static inline int pi_test_sn(struct pi_desc *pi_desc)
 513 {
 514         return test_bit(POSTED_INTR_SN,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 struct vcpu_vmx {
 519         struct kvm_vcpu       vcpu;
 520         unsigned long         host_rsp;
 521         u8                    fail;
 522         bool                  nmi_known_unmasked;
 523         u32                   exit_intr_info;
 524         u32                   idt_vectoring_info;
 525         ulong                 rflags;
 526         struct shared_msr_entry *guest_msrs;
 527         int                   nmsrs;
 528         int                   save_nmsrs;
 529         unsigned long         host_idt_base;
 530 #ifdef CONFIG_X86_64
 531         u64                   msr_host_kernel_gs_base;
 532         u64                   msr_guest_kernel_gs_base;
 533 #endif
 534         u32 vm_entry_controls_shadow;
 535         u32 vm_exit_controls_shadow;
 536         /*
 537          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 538          * non-nested (L1) guest, it always points to vmcs01. For a nested
 539          * guest (L2), it points to a different VMCS.
 540          */
 541         struct loaded_vmcs    vmcs01;
 542         struct loaded_vmcs   *loaded_vmcs;
 543         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 544         struct msr_autoload {
 545                 unsigned nr;
 546                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 547                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 548         } msr_autoload;
 549         struct {
 550                 int           loaded;
 551                 u16           fs_sel, gs_sel, ldt_sel;
 552 #ifdef CONFIG_X86_64
 553                 u16           ds_sel, es_sel;
 554 #endif
 555                 int           gs_ldt_reload_needed;
 556                 int           fs_reload_needed;
 557                 u64           msr_host_bndcfgs;
 558                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 559         } host_state;
 560         struct {
 561                 int vm86_active;
 562                 ulong save_rflags;
 563                 struct kvm_segment segs[8];
 564         } rmode;
 565         struct {
 566                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 567                 struct kvm_save_segment {
 568                         u16 selector;
 569                         unsigned long base;
 570                         u32 limit;
 571                         u32 ar;
 572                 } seg[8];
 573         } segment_cache;
 574         int vpid;
 575         bool emulation_required;
 576
 577         /* Support for vnmi-less CPUs */
 578         int soft_vnmi_blocked;
 579         ktime_t entry_time;
 580         s64 vnmi_blocked_time;
 581         u32 exit_reason;
 582
 583         /* Posted interrupt descriptor */
 584         struct pi_desc pi_desc;
 585
 586         /* Support for a guest hypervisor (nested VMX) */
 587         struct nested_vmx nested;
 588
 589         /* Dynamic PLE window. */
 590         int ple_window;
 591         bool ple_window_dirty;
 592
 593         /* Support for PML */
 594 #define PML_ENTITY_NUM          512
 595         struct page *pml_pg;
 596 };
 597
 598 enum segment_cache_field {
 599         SEG_FIELD_SEL = 0,
 600         SEG_FIELD_BASE = 1,
 601         SEG_FIELD_LIMIT = 2,
 602         SEG_FIELD_AR = 3,
 603
 604         SEG_FIELD_NR = 4
 605 };
 606
 607 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 608 {
 609         return container_of(vcpu, struct vcpu_vmx, vcpu);
 610 }
 611
 612 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 613 {
 614         return &(to_vmx(vcpu)->pi_desc);
 615 }
 616
 617 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 618 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 619 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 620                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 621
 622
 623 static unsigned long shadow_read_only_fields[] = {
 624         /*
 625          * We do NOT shadow fields that are modified when L0
 626          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 627          * VMXON...) executed by L1.
 628          * For example, VM_INSTRUCTION_ERROR is read
 629          * by L1 if a vmx instruction fails (part of the error path).
 630          * Note the code assumes this logic. If for some reason
 631          * we start shadowing these fields then we need to
 632          * force a shadow sync when L0 emulates vmx instructions
 633          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 634          * by nested_vmx_failValid)
 635          */
 636         VM_EXIT_REASON,
 637         VM_EXIT_INTR_INFO,
 638         VM_EXIT_INSTRUCTION_LEN,
 639         IDT_VECTORING_INFO_FIELD,
 640         IDT_VECTORING_ERROR_CODE,
 641         VM_EXIT_INTR_ERROR_CODE,
 642         EXIT_QUALIFICATION,
 643         GUEST_LINEAR_ADDRESS,
 644         GUEST_PHYSICAL_ADDRESS
 645 };
 646 static int max_shadow_read_only_fields =
 647         ARRAY_SIZE(shadow_read_only_fields);
 648
 649 static unsigned long shadow_read_write_fields[] = {
 650         TPR_THRESHOLD,
 651         GUEST_RIP,
 652         GUEST_RSP,
 653         GUEST_CR0,
 654         GUEST_CR3,
 655         GUEST_CR4,
 656         GUEST_INTERRUPTIBILITY_INFO,
 657         GUEST_RFLAGS,
 658         GUEST_CS_SELECTOR,
 659         GUEST_CS_AR_BYTES,
 660         GUEST_CS_LIMIT,
 661         GUEST_CS_BASE,
 662         GUEST_ES_BASE,
 663         GUEST_BNDCFGS,
 664         CR0_GUEST_HOST_MASK,
 665         CR0_READ_SHADOW,
 666         CR4_READ_SHADOW,
 667         TSC_OFFSET,
 668         EXCEPTION_BITMAP,
 669         CPU_BASED_VM_EXEC_CONTROL,
 670         VM_ENTRY_EXCEPTION_ERROR_CODE,
 671         VM_ENTRY_INTR_INFO_FIELD,
 672         VM_ENTRY_INSTRUCTION_LEN,
 673         VM_ENTRY_EXCEPTION_ERROR_CODE,
 674         HOST_FS_BASE,
 675         HOST_GS_BASE,
 676         HOST_FS_SELECTOR,
 677         HOST_GS_SELECTOR
 678 };
 679 static int max_shadow_read_write_fields =
 680         ARRAY_SIZE(shadow_read_write_fields);
 681
 682 static const unsigned short vmcs_field_to_offset_table[] = {
 683         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 684         FIELD(POSTED_INTR_NV, posted_intr_nv),
 685         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 686         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 687         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 688         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 689         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 690         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 691         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 692         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 693         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 694         FIELD(HOST_ES_SELECTOR, host_es_selector),
 695         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 696         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 697         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 698         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 699         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 700         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 701         FIELD64(IO_BITMAP_A, io_bitmap_a),
 702         FIELD64(IO_BITMAP_B, io_bitmap_b),
 703         FIELD64(MSR_BITMAP, msr_bitmap),
 704         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 705         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 706         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 707         FIELD64(TSC_OFFSET, tsc_offset),
 708         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 709         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 710         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 711         FIELD64(EPT_POINTER, ept_pointer),
 712         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 713         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 714         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 715         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 716         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 717         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 718         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 719         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 720         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 721         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 722         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 723         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 724         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 725         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 726         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 727         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 728         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 729         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 730         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 731         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 732         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 733         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 734         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 735         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 736         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 737         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 738         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 739         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 740         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 741         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 742         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 743         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 744         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 745         FIELD(TPR_THRESHOLD, tpr_threshold),
 746         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 747         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 748         FIELD(VM_EXIT_REASON, vm_exit_reason),
 749         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 750         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 751         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 752         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 753         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 754         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 755         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 756         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 757         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 758         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 759         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 760         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 761         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 762         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 763         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 764         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 765         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 766         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 767         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 768         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 769         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 770         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 771         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 772         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 773         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 774         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 775         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 776         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 777         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 778         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 779         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 780         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 781         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 782         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 783         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 784         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 785         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 786         FIELD(EXIT_QUALIFICATION, exit_qualification),
 787         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 788         FIELD(GUEST_CR0, guest_cr0),
 789         FIELD(GUEST_CR3, guest_cr3),
 790         FIELD(GUEST_CR4, guest_cr4),
 791         FIELD(GUEST_ES_BASE, guest_es_base),
 792         FIELD(GUEST_CS_BASE, guest_cs_base),
 793         FIELD(GUEST_SS_BASE, guest_ss_base),
 794         FIELD(GUEST_DS_BASE, guest_ds_base),
 795         FIELD(GUEST_FS_BASE, guest_fs_base),
 796         FIELD(GUEST_GS_BASE, guest_gs_base),
 797         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 798         FIELD(GUEST_TR_BASE, guest_tr_base),
 799         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 800         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 801         FIELD(GUEST_DR7, guest_dr7),
 802         FIELD(GUEST_RSP, guest_rsp),
 803         FIELD(GUEST_RIP, guest_rip),
 804         FIELD(GUEST_RFLAGS, guest_rflags),
 805         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 806         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 807         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 808         FIELD(HOST_CR0, host_cr0),
 809         FIELD(HOST_CR3, host_cr3),
 810         FIELD(HOST_CR4, host_cr4),
 811         FIELD(HOST_FS_BASE, host_fs_base),
 812         FIELD(HOST_GS_BASE, host_gs_base),
 813         FIELD(HOST_TR_BASE, host_tr_base),
 814         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 815         FIELD(HOST_IDTR_BASE, host_idtr_base),
 816         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 817         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 818         FIELD(HOST_RSP, host_rsp),
 819         FIELD(HOST_RIP, host_rip),
 820 };
 821
 822 static inline short vmcs_field_to_offset(unsigned long field)
 823 {
 824         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 825
 826         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 827             vmcs_field_to_offset_table[field] == 0)
 828                 return -ENOENT;
 829
 830         return vmcs_field_to_offset_table[field];
 831 }
 832
 833 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 834 {
 835         return to_vmx(vcpu)->nested.current_vmcs12;
 836 }
 837
 838 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 839 {
 840         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 841         if (is_error_page(page))
 842                 return NULL;
 843
 844         return page;
 845 }
 846
 847 static void nested_release_page(struct page *page)
 848 {
 849         kvm_release_page_dirty(page);
 850 }
 851
 852 static void nested_release_page_clean(struct page *page)
 853 {
 854         kvm_release_page_clean(page);
 855 }
 856
 857 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 858 static u64 construct_eptp(unsigned long root_hpa);
 859 static void kvm_cpu_vmxon(u64 addr);
 860 static void kvm_cpu_vmxoff(void);
 861 static bool vmx_mpx_supported(void);
 862 static bool vmx_xsaves_supported(void);
 863 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 864 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 865 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 866                             struct kvm_segment *var, int seg);
 867 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 868                             struct kvm_segment *var, int seg);
 869 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 870 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 871 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 872 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 873 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 874 static int alloc_identity_pagetable(struct kvm *kvm);
 875
 876 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 877 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 878 /*
 879  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 880  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 881  */
 882 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 883 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 884
 885 /*
 886  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 887  * can find which vCPU should be waken up.
 888  */
 889 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 890 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 891
 892 static unsigned long *vmx_io_bitmap_a;
 893 static unsigned long *vmx_io_bitmap_b;
 894 static unsigned long *vmx_msr_bitmap_legacy;
 895 static unsigned long *vmx_msr_bitmap_longmode;
 896 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 897 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 898 static unsigned long *vmx_msr_bitmap_nested;
 899 static unsigned long *vmx_vmread_bitmap;
 900 static unsigned long *vmx_vmwrite_bitmap;
 901
 902 static bool cpu_has_load_ia32_efer;
 903 static bool cpu_has_load_perf_global_ctrl;
 904
 905 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 906 static DEFINE_SPINLOCK(vmx_vpid_lock);
 907
 908 static struct vmcs_config {
 909         int size;
 910         int order;
 911         u32 revision_id;
 912         u32 pin_based_exec_ctrl;
 913         u32 cpu_based_exec_ctrl;
 914         u32 cpu_based_2nd_exec_ctrl;
 915         u32 vmexit_ctrl;
 916         u32 vmentry_ctrl;
 917 } vmcs_config;
 918
 919 static struct vmx_capability {
 920         u32 ept;
 921         u32 vpid;
 922 } vmx_capability;
 923
 924 #define VMX_SEGMENT_FIELD(seg)                                  \
 925         [VCPU_SREG_##seg] = {                                   \
 926                 .selector = GUEST_##seg##_SELECTOR,             \
 927                 .base = GUEST_##seg##_BASE,                     \
 928                 .limit = GUEST_##seg##_LIMIT,                   \
 929                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 930         }
 931
 932 static const struct kvm_vmx_segment_field {
 933         unsigned selector;
 934         unsigned base;
 935         unsigned limit;
 936         unsigned ar_bytes;
 937 } kvm_vmx_segment_fields[] = {
 938         VMX_SEGMENT_FIELD(CS),
 939         VMX_SEGMENT_FIELD(DS),
 940         VMX_SEGMENT_FIELD(ES),
 941         VMX_SEGMENT_FIELD(FS),
 942         VMX_SEGMENT_FIELD(GS),
 943         VMX_SEGMENT_FIELD(SS),
 944         VMX_SEGMENT_FIELD(TR),
 945         VMX_SEGMENT_FIELD(LDTR),
 946 };
 947
 948 static u64 host_efer;
 949
 950 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 951
 952 /*
 953  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 954  * away by decrementing the array size.
 955  */
 956 static const u32 vmx_msr_index[] = {
 957 #ifdef CONFIG_X86_64
 958         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 959 #endif
 960         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 961 };
 962
 963 static inline bool is_page_fault(u32 intr_info)
 964 {
 965         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 966                              INTR_INFO_VALID_MASK)) ==
 967                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 968 }
 969
 970 static inline bool is_no_device(u32 intr_info)
 971 {
 972         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 973                              INTR_INFO_VALID_MASK)) ==
 974                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 975 }
 976
 977 static inline bool is_invalid_opcode(u32 intr_info)
 978 {
 979         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 980                              INTR_INFO_VALID_MASK)) ==
 981                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 982 }
 983
 984 static inline bool is_external_interrupt(u32 intr_info)
 985 {
 986         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 987                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 988 }
 989
 990 static inline bool is_machine_check(u32 intr_info)
 991 {
 992         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 993                              INTR_INFO_VALID_MASK)) ==
 994                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 995 }
 996
 997 static inline bool cpu_has_vmx_msr_bitmap(void)
 998 {
 999         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1000 }
1001
1002 static inline bool cpu_has_vmx_tpr_shadow(void)
1003 {
1004         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1005 }
1006
1007 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1008 {
1009         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1010 }
1011
1012 static inline bool cpu_has_secondary_exec_ctrls(void)
1013 {
1014         return vmcs_config.cpu_based_exec_ctrl &
1015                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1016 }
1017
1018 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1019 {
1020         return vmcs_config.cpu_based_2nd_exec_ctrl &
1021                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1022 }
1023
1024 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1025 {
1026         return vmcs_config.cpu_based_2nd_exec_ctrl &
1027                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1028 }
1029
1030 static inline bool cpu_has_vmx_apic_register_virt(void)
1031 {
1032         return vmcs_config.cpu_based_2nd_exec_ctrl &
1033                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1034 }
1035
1036 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1037 {
1038         return vmcs_config.cpu_based_2nd_exec_ctrl &
1039                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1040 }
1041
1042 static inline bool cpu_has_vmx_posted_intr(void)
1043 {
1044         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1045                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1046 }
1047
1048 static inline bool cpu_has_vmx_apicv(void)
1049 {
1050         return cpu_has_vmx_apic_register_virt() &&
1051                 cpu_has_vmx_virtual_intr_delivery() &&
1052                 cpu_has_vmx_posted_intr();
1053 }
1054
1055 static inline bool cpu_has_vmx_flexpriority(void)
1056 {
1057         return cpu_has_vmx_tpr_shadow() &&
1058                 cpu_has_vmx_virtualize_apic_accesses();
1059 }
1060
1061 static inline bool cpu_has_vmx_ept_execute_only(void)
1062 {
1063         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1064 }
1065
1066 static inline bool cpu_has_vmx_ept_2m_page(void)
1067 {
1068         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1069 }
1070
1071 static inline bool cpu_has_vmx_ept_1g_page(void)
1072 {
1073         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1074 }
1075
1076 static inline bool cpu_has_vmx_ept_4levels(void)
1077 {
1078         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1079 }
1080
1081 static inline bool cpu_has_vmx_ept_ad_bits(void)
1082 {
1083         return vmx_capability.ept & VMX_EPT_AD_BIT;
1084 }
1085
1086 static inline bool cpu_has_vmx_invept_context(void)
1087 {
1088         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1089 }
1090
1091 static inline bool cpu_has_vmx_invept_global(void)
1092 {
1093         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1094 }
1095
1096 static inline bool cpu_has_vmx_invvpid_single(void)
1097 {
1098         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1099 }
1100
1101 static inline bool cpu_has_vmx_invvpid_global(void)
1102 {
1103         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1104 }
1105
1106 static inline bool cpu_has_vmx_ept(void)
1107 {
1108         return vmcs_config.cpu_based_2nd_exec_ctrl &
1109                 SECONDARY_EXEC_ENABLE_EPT;
1110 }
1111
1112 static inline bool cpu_has_vmx_unrestricted_guest(void)
1113 {
1114         return vmcs_config.cpu_based_2nd_exec_ctrl &
1115                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1116 }
1117
1118 static inline bool cpu_has_vmx_ple(void)
1119 {
1120         return vmcs_config.cpu_based_2nd_exec_ctrl &
1121                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1122 }
1123
1124 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1125 {
1126         return flexpriority_enabled && lapic_in_kernel(vcpu);
1127 }
1128
1129 static inline bool cpu_has_vmx_vpid(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_ENABLE_VPID;
1133 }
1134
1135 static inline bool cpu_has_vmx_rdtscp(void)
1136 {
1137         return vmcs_config.cpu_based_2nd_exec_ctrl &
1138                 SECONDARY_EXEC_RDTSCP;
1139 }
1140
1141 static inline bool cpu_has_vmx_invpcid(void)
1142 {
1143         return vmcs_config.cpu_based_2nd_exec_ctrl &
1144                 SECONDARY_EXEC_ENABLE_INVPCID;
1145 }
1146
1147 static inline bool cpu_has_virtual_nmis(void)
1148 {
1149         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1150 }
1151
1152 static inline bool cpu_has_vmx_wbinvd_exit(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_WBINVD_EXITING;
1156 }
1157
1158 static inline bool cpu_has_vmx_shadow_vmcs(void)
1159 {
1160         u64 vmx_msr;
1161         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1162         /* check if the cpu supports writing r/o exit information fields */
1163         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1164                 return false;
1165
1166         return vmcs_config.cpu_based_2nd_exec_ctrl &
1167                 SECONDARY_EXEC_SHADOW_VMCS;
1168 }
1169
1170 static inline bool cpu_has_vmx_pml(void)
1171 {
1172         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1173 }
1174
1175 static inline bool report_flexpriority(void)
1176 {
1177         return flexpriority_enabled;
1178 }
1179
1180 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1181 {
1182         return vmcs12->cpu_based_vm_exec_control & bit;
1183 }
1184
1185 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1186 {
1187         return (vmcs12->cpu_based_vm_exec_control &
1188                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1189                 (vmcs12->secondary_vm_exec_control & bit);
1190 }
1191
1192 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1193 {
1194         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1195 }
1196
1197 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1198 {
1199         return vmcs12->pin_based_vm_exec_control &
1200                 PIN_BASED_VMX_PREEMPTION_TIMER;
1201 }
1202
1203 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1204 {
1205         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1206 }
1207
1208 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1209 {
1210         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1211                 vmx_xsaves_supported();
1212 }
1213
1214 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1215 {
1216         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1217 }
1218
1219 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1220 {
1221         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1222 }
1223
1224 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1225 {
1226         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1227 }
1228
1229 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1230 {
1231         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1232 }
1233
1234 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1235 {
1236         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1237 }
1238
1239 static inline bool is_exception(u32 intr_info)
1240 {
1241         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1242                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1243 }
1244
1245 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1246                               u32 exit_intr_info,
1247                               unsigned long exit_qualification);
1248 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1249                         struct vmcs12 *vmcs12,
1250                         u32 reason, unsigned long qualification);
1251
1252 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1253 {
1254         int i;
1255
1256         for (i = 0; i < vmx->nmsrs; ++i)
1257                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1258                         return i;
1259         return -1;
1260 }
1261
1262 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1263 {
1264     struct {
1265         u64 vpid : 16;
1266         u64 rsvd : 48;
1267         u64 gva;
1268     } operand = { vpid, 0, gva };
1269
1270     asm volatile (__ex(ASM_VMX_INVVPID)
1271                   /* CF==1 or ZF==1 --> rc = -1 */
1272                   "; ja 1f ; ud2 ; 1:"
1273                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1274 }
1275
1276 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1277 {
1278         struct {
1279                 u64 eptp, gpa;
1280         } operand = {eptp, gpa};
1281
1282         asm volatile (__ex(ASM_VMX_INVEPT)
1283                         /* CF==1 or ZF==1 --> rc = -1 */
1284                         "; ja 1f ; ud2 ; 1:\n"
1285                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1286 }
1287
1288 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1289 {
1290         int i;
1291
1292         i = __find_msr_index(vmx, msr);
1293         if (i >= 0)
1294                 return &vmx->guest_msrs[i];
1295         return NULL;
1296 }
1297
1298 static void vmcs_clear(struct vmcs *vmcs)
1299 {
1300         u64 phys_addr = __pa(vmcs);
1301         u8 error;
1302
1303         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1304                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1305                       : "cc", "memory");
1306         if (error)
1307                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1308                        vmcs, phys_addr);
1309 }
1310
1311 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1312 {
1313         vmcs_clear(loaded_vmcs->vmcs);
1314         loaded_vmcs->cpu = -1;
1315         loaded_vmcs->launched = 0;
1316 }
1317
1318 static void vmcs_load(struct vmcs *vmcs)
1319 {
1320         u64 phys_addr = __pa(vmcs);
1321         u8 error;
1322
1323         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1324                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1325                         : "cc", "memory");
1326         if (error)
1327                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1328                        vmcs, phys_addr);
1329 }
1330
1331 #ifdef CONFIG_KEXEC_CORE
1332 /*
1333  * This bitmap is used to indicate whether the vmclear
1334  * operation is enabled on all cpus. All disabled by
1335  * default.
1336  */
1337 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1338
1339 static inline void crash_enable_local_vmclear(int cpu)
1340 {
1341         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1342 }
1343
1344 static inline void crash_disable_local_vmclear(int cpu)
1345 {
1346         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1347 }
1348
1349 static inline int crash_local_vmclear_enabled(int cpu)
1350 {
1351         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 }
1353
1354 static void crash_vmclear_local_loaded_vmcss(void)
1355 {
1356         int cpu = raw_smp_processor_id();
1357         struct loaded_vmcs *v;
1358
1359         if (!crash_local_vmclear_enabled(cpu))
1360                 return;
1361
1362         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1363                             loaded_vmcss_on_cpu_link)
1364                 vmcs_clear(v->vmcs);
1365 }
1366 #else
1367 static inline void crash_enable_local_vmclear(int cpu) { }
1368 static inline void crash_disable_local_vmclear(int cpu) { }
1369 #endif /* CONFIG_KEXEC_CORE */
1370
1371 static void __loaded_vmcs_clear(void *arg)
1372 {
1373         struct loaded_vmcs *loaded_vmcs = arg;
1374         int cpu = raw_smp_processor_id();
1375
1376         if (loaded_vmcs->cpu != cpu)
1377                 return; /* vcpu migration can race with cpu offline */
1378         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1379                 per_cpu(current_vmcs, cpu) = NULL;
1380         crash_disable_local_vmclear(cpu);
1381         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1382
1383         /*
1384          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1385          * is before setting loaded_vmcs->vcpu to -1 which is done in
1386          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1387          * then adds the vmcs into percpu list before it is deleted.
1388          */
1389         smp_wmb();
1390
1391         loaded_vmcs_init(loaded_vmcs);
1392         crash_enable_local_vmclear(cpu);
1393 }
1394
1395 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1396 {
1397         int cpu = loaded_vmcs->cpu;
1398
1399         if (cpu != -1)
1400                 smp_call_function_single(cpu,
1401                          __loaded_vmcs_clear, loaded_vmcs, 1);
1402 }
1403
1404 static inline void vpid_sync_vcpu_single(int vpid)
1405 {
1406         if (vpid == 0)
1407                 return;
1408
1409         if (cpu_has_vmx_invvpid_single())
1410                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1411 }
1412
1413 static inline void vpid_sync_vcpu_global(void)
1414 {
1415         if (cpu_has_vmx_invvpid_global())
1416                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1417 }
1418
1419 static inline void vpid_sync_context(int vpid)
1420 {
1421         if (cpu_has_vmx_invvpid_single())
1422                 vpid_sync_vcpu_single(vpid);
1423         else
1424                 vpid_sync_vcpu_global();
1425 }
1426
1427 static inline void ept_sync_global(void)
1428 {
1429         if (cpu_has_vmx_invept_global())
1430                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1431 }
1432
1433 static inline void ept_sync_context(u64 eptp)
1434 {
1435         if (enable_ept) {
1436                 if (cpu_has_vmx_invept_context())
1437                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1438                 else
1439                         ept_sync_global();
1440         }
1441 }
1442
1443 static __always_inline unsigned long vmcs_readl(unsigned long field)
1444 {
1445         unsigned long value;
1446
1447         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1448                       : "=a"(value) : "d"(field) : "cc");
1449         return value;
1450 }
1451
1452 static __always_inline u16 vmcs_read16(unsigned long field)
1453 {
1454         return vmcs_readl(field);
1455 }
1456
1457 static __always_inline u32 vmcs_read32(unsigned long field)
1458 {
1459         return vmcs_readl(field);
1460 }
1461
1462 static __always_inline u64 vmcs_read64(unsigned long field)
1463 {
1464 #ifdef CONFIG_X86_64
1465         return vmcs_readl(field);
1466 #else
1467         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1468 #endif
1469 }
1470
1471 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1472 {
1473         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1474                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1475         dump_stack();
1476 }
1477
1478 static void vmcs_writel(unsigned long field, unsigned long value)
1479 {
1480         u8 error;
1481
1482         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1483                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1484         if (unlikely(error))
1485                 vmwrite_error(field, value);
1486 }
1487
1488 static void vmcs_write16(unsigned long field, u16 value)
1489 {
1490         vmcs_writel(field, value);
1491 }
1492
1493 static void vmcs_write32(unsigned long field, u32 value)
1494 {
1495         vmcs_writel(field, value);
1496 }
1497
1498 static void vmcs_write64(unsigned long field, u64 value)
1499 {
1500         vmcs_writel(field, value);
1501 #ifndef CONFIG_X86_64
1502         asm volatile ("");
1503         vmcs_writel(field+1, value >> 32);
1504 #endif
1505 }
1506
1507 static void vmcs_clear_bits(unsigned long field, u32 mask)
1508 {
1509         vmcs_writel(field, vmcs_readl(field) & ~mask);
1510 }
1511
1512 static void vmcs_set_bits(unsigned long field, u32 mask)
1513 {
1514         vmcs_writel(field, vmcs_readl(field) | mask);
1515 }
1516
1517 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1518 {
1519         vmcs_write32(VM_ENTRY_CONTROLS, val);
1520         vmx->vm_entry_controls_shadow = val;
1521 }
1522
1523 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1524 {
1525         if (vmx->vm_entry_controls_shadow != val)
1526                 vm_entry_controls_init(vmx, val);
1527 }
1528
1529 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1530 {
1531         return vmx->vm_entry_controls_shadow;
1532 }
1533
1534
1535 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1536 {
1537         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1538 }
1539
1540 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1541 {
1542         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1543 }
1544
1545 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1546 {
1547         vmcs_write32(VM_EXIT_CONTROLS, val);
1548         vmx->vm_exit_controls_shadow = val;
1549 }
1550
1551 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1552 {
1553         if (vmx->vm_exit_controls_shadow != val)
1554                 vm_exit_controls_init(vmx, val);
1555 }
1556
1557 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1558 {
1559         return vmx->vm_exit_controls_shadow;
1560 }
1561
1562
1563 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1564 {
1565         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1566 }
1567
1568 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1569 {
1570         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1571 }
1572
1573 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1574 {
1575         vmx->segment_cache.bitmask = 0;
1576 }
1577
1578 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1579                                        unsigned field)
1580 {
1581         bool ret;
1582         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1583
1584         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1585                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1586                 vmx->segment_cache.bitmask = 0;
1587         }
1588         ret = vmx->segment_cache.bitmask & mask;
1589         vmx->segment_cache.bitmask |= mask;
1590         return ret;
1591 }
1592
1593 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1594 {
1595         u16 *p = &vmx->segment_cache.seg[seg].selector;
1596
1597         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1598                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1599         return *p;
1600 }
1601
1602 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1603 {
1604         ulong *p = &vmx->segment_cache.seg[seg].base;
1605
1606         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1607                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1608         return *p;
1609 }
1610
1611 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1612 {
1613         u32 *p = &vmx->segment_cache.seg[seg].limit;
1614
1615         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1616                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1617         return *p;
1618 }
1619
1620 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1621 {
1622         u32 *p = &vmx->segment_cache.seg[seg].ar;
1623
1624         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1625                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1626         return *p;
1627 }
1628
1629 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1630 {
1631         u32 eb;
1632
1633         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1634              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1635         if ((vcpu->guest_debug &
1636              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1637             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1638                 eb |= 1u << BP_VECTOR;
1639         if (to_vmx(vcpu)->rmode.vm86_active)
1640                 eb = ~0;
1641         if (enable_ept)
1642                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1643         if (vcpu->fpu_active)
1644                 eb &= ~(1u << NM_VECTOR);
1645
1646         /* When we are running a nested L2 guest and L1 specified for it a
1647          * certain exception bitmap, we must trap the same exceptions and pass
1648          * them to L1. When running L2, we will only handle the exceptions
1649          * specified above if L1 did not want them.
1650          */
1651         if (is_guest_mode(vcpu))
1652                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1653
1654         vmcs_write32(EXCEPTION_BITMAP, eb);
1655 }
1656
1657 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1658                 unsigned long entry, unsigned long exit)
1659 {
1660         vm_entry_controls_clearbit(vmx, entry);
1661         vm_exit_controls_clearbit(vmx, exit);
1662 }
1663
1664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1665 {
1666         unsigned i;
1667         struct msr_autoload *m = &vmx->msr_autoload;
1668
1669         switch (msr) {
1670         case MSR_EFER:
1671                 if (cpu_has_load_ia32_efer) {
1672                         clear_atomic_switch_msr_special(vmx,
1673                                         VM_ENTRY_LOAD_IA32_EFER,
1674                                         VM_EXIT_LOAD_IA32_EFER);
1675                         return;
1676                 }
1677                 break;
1678         case MSR_CORE_PERF_GLOBAL_CTRL:
1679                 if (cpu_has_load_perf_global_ctrl) {
1680                         clear_atomic_switch_msr_special(vmx,
1681                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1682                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1683                         return;
1684                 }
1685                 break;
1686         }
1687
1688         for (i = 0; i < m->nr; ++i)
1689                 if (m->guest[i].index == msr)
1690                         break;
1691
1692         if (i == m->nr)
1693                 return;
1694         --m->nr;
1695         m->guest[i] = m->guest[m->nr];
1696         m->host[i] = m->host[m->nr];
1697         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1698         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1699 }
1700
1701 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1702                 unsigned long entry, unsigned long exit,
1703                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1704                 u64 guest_val, u64 host_val)
1705 {
1706         vmcs_write64(guest_val_vmcs, guest_val);
1707         vmcs_write64(host_val_vmcs, host_val);
1708         vm_entry_controls_setbit(vmx, entry);
1709         vm_exit_controls_setbit(vmx, exit);
1710 }
1711
1712 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1713                                   u64 guest_val, u64 host_val)
1714 {
1715         unsigned i;
1716         struct msr_autoload *m = &vmx->msr_autoload;
1717
1718         switch (msr) {
1719         case MSR_EFER:
1720                 if (cpu_has_load_ia32_efer) {
1721                         add_atomic_switch_msr_special(vmx,
1722                                         VM_ENTRY_LOAD_IA32_EFER,
1723                                         VM_EXIT_LOAD_IA32_EFER,
1724                                         GUEST_IA32_EFER,
1725                                         HOST_IA32_EFER,
1726                                         guest_val, host_val);
1727                         return;
1728                 }
1729                 break;
1730         case MSR_CORE_PERF_GLOBAL_CTRL:
1731                 if (cpu_has_load_perf_global_ctrl) {
1732                         add_atomic_switch_msr_special(vmx,
1733                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1734                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1735                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1736                                         HOST_IA32_PERF_GLOBAL_CTRL,
1737                                         guest_val, host_val);
1738                         return;
1739                 }
1740                 break;
1741         }
1742
1743         for (i = 0; i < m->nr; ++i)
1744                 if (m->guest[i].index == msr)
1745                         break;
1746
1747         if (i == NR_AUTOLOAD_MSRS) {
1748                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1749                                 "Can't add msr %x\n", msr);
1750                 return;
1751         } else if (i == m->nr) {
1752                 ++m->nr;
1753                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1754                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1755         }
1756
1757         m->guest[i].index = msr;
1758         m->guest[i].value = guest_val;
1759         m->host[i].index = msr;
1760         m->host[i].value = host_val;
1761 }
1762
1763 static void reload_tss(void)
1764 {
1765         /*
1766          * VT restores TR but not its size.  Useless.
1767          */
1768         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1769         struct desc_struct *descs;
1770
1771         descs = (void *)gdt->address;
1772         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1773         load_TR_desc();
1774 }
1775
1776 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1777 {
1778         u64 guest_efer;
1779         u64 ignore_bits;
1780
1781         guest_efer = vmx->vcpu.arch.efer;
1782
1783         /*
1784          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1785          * outside long mode
1786          */
1787         ignore_bits = EFER_NX | EFER_SCE;
1788 #ifdef CONFIG_X86_64
1789         ignore_bits |= EFER_LMA | EFER_LME;
1790         /* SCE is meaningful only in long mode on Intel */
1791         if (guest_efer & EFER_LMA)
1792                 ignore_bits &= ~(u64)EFER_SCE;
1793 #endif
1794         guest_efer &= ~ignore_bits;
1795         guest_efer |= host_efer & ignore_bits;
1796         vmx->guest_msrs[efer_offset].data = guest_efer;
1797         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1798
1799         clear_atomic_switch_msr(vmx, MSR_EFER);
1800
1801         /*
1802          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1803          * On CPUs that support "load IA32_EFER", always switch EFER
1804          * atomically, since it's faster than switching it manually.
1805          */
1806         if (cpu_has_load_ia32_efer ||
1807             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1808                 guest_efer = vmx->vcpu.arch.efer;
1809                 if (!(guest_efer & EFER_LMA))
1810                         guest_efer &= ~EFER_LME;
1811                 if (guest_efer != host_efer)
1812                         add_atomic_switch_msr(vmx, MSR_EFER,
1813                                               guest_efer, host_efer);
1814                 return false;
1815         }
1816
1817         return true;
1818 }
1819
1820 static unsigned long segment_base(u16 selector)
1821 {
1822         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1823         struct desc_struct *d;
1824         unsigned long table_base;
1825         unsigned long v;
1826
1827         if (!(selector & ~3))
1828                 return 0;
1829
1830         table_base = gdt->address;
1831
1832         if (selector & 4) {           /* from ldt */
1833                 u16 ldt_selector = kvm_read_ldt();
1834
1835                 if (!(ldt_selector & ~3))
1836                         return 0;
1837
1838                 table_base = segment_base(ldt_selector);
1839         }
1840         d = (struct desc_struct *)(table_base + (selector & ~7));
1841         v = get_desc_base(d);
1842 #ifdef CONFIG_X86_64
1843        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1844                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1845 #endif
1846         return v;
1847 }
1848
1849 static inline unsigned long kvm_read_tr_base(void)
1850 {
1851         u16 tr;
1852         asm("str %0" : "=g"(tr));
1853         return segment_base(tr);
1854 }
1855
1856 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1857 {
1858         struct vcpu_vmx *vmx = to_vmx(vcpu);
1859         int i;
1860
1861         if (vmx->host_state.loaded)
1862                 return;
1863
1864         vmx->host_state.loaded = 1;
1865         /*
1866          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1867          * allow segment selectors with cpl > 0 or ti == 1.
1868          */
1869         vmx->host_state.ldt_sel = kvm_read_ldt();
1870         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1871         savesegment(fs, vmx->host_state.fs_sel);
1872         if (!(vmx->host_state.fs_sel & 7)) {
1873                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1874                 vmx->host_state.fs_reload_needed = 0;
1875         } else {
1876                 vmcs_write16(HOST_FS_SELECTOR, 0);
1877                 vmx->host_state.fs_reload_needed = 1;
1878         }
1879         savesegment(gs, vmx->host_state.gs_sel);
1880         if (!(vmx->host_state.gs_sel & 7))
1881                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1882         else {
1883                 vmcs_write16(HOST_GS_SELECTOR, 0);
1884                 vmx->host_state.gs_ldt_reload_needed = 1;
1885         }
1886
1887 #ifdef CONFIG_X86_64
1888         savesegment(ds, vmx->host_state.ds_sel);
1889         savesegment(es, vmx->host_state.es_sel);
1890 #endif
1891
1892 #ifdef CONFIG_X86_64
1893         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1894         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1895 #else
1896         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1897         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1898 #endif
1899
1900 #ifdef CONFIG_X86_64
1901         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1902         if (is_long_mode(&vmx->vcpu))
1903                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1904 #endif
1905         if (boot_cpu_has(X86_FEATURE_MPX))
1906                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1907         for (i = 0; i < vmx->save_nmsrs; ++i)
1908                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1909                                    vmx->guest_msrs[i].data,
1910                                    vmx->guest_msrs[i].mask);
1911 }
1912
1913 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1914 {
1915         if (!vmx->host_state.loaded)
1916                 return;
1917
1918         ++vmx->vcpu.stat.host_state_reload;
1919         vmx->host_state.loaded = 0;
1920 #ifdef CONFIG_X86_64
1921         if (is_long_mode(&vmx->vcpu))
1922                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1923 #endif
1924         if (vmx->host_state.gs_ldt_reload_needed) {
1925                 kvm_load_ldt(vmx->host_state.ldt_sel);
1926 #ifdef CONFIG_X86_64
1927                 load_gs_index(vmx->host_state.gs_sel);
1928 #else
1929                 loadsegment(gs, vmx->host_state.gs_sel);
1930 #endif
1931         }
1932         if (vmx->host_state.fs_reload_needed)
1933                 loadsegment(fs, vmx->host_state.fs_sel);
1934 #ifdef CONFIG_X86_64
1935         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1936                 loadsegment(ds, vmx->host_state.ds_sel);
1937                 loadsegment(es, vmx->host_state.es_sel);
1938         }
1939 #endif
1940         reload_tss();
1941 #ifdef CONFIG_X86_64
1942         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1943 #endif
1944         if (vmx->host_state.msr_host_bndcfgs)
1945                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1946         /*
1947          * If the FPU is not active (through the host task or
1948          * the guest vcpu), then restore the cr0.TS bit.
1949          */
1950         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1951                 stts();
1952         load_gdt(this_cpu_ptr(&host_gdt));
1953 }
1954
1955 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1956 {
1957         preempt_disable();
1958         __vmx_load_host_state(vmx);
1959         preempt_enable();
1960 }
1961
1962 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1963 {
1964         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1965         struct pi_desc old, new;
1966         unsigned int dest;
1967
1968         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1969                 !irq_remapping_cap(IRQ_POSTING_CAP))
1970                 return;
1971
1972         do {
1973                 old.control = new.control = pi_desc->control;
1974
1975                 /*
1976                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1977                  * are two possible cases:
1978                  * 1. After running 'pre_block', context switch
1979                  *    happened. For this case, 'sn' was set in
1980                  *    vmx_vcpu_put(), so we need to clear it here.
1981                  * 2. After running 'pre_block', we were blocked,
1982                  *    and woken up by some other guy. For this case,
1983                  *    we don't need to do anything, 'pi_post_block'
1984                  *    will do everything for us. However, we cannot
1985                  *    check whether it is case #1 or case #2 here
1986                  *    (maybe, not needed), so we also clear sn here,
1987                  *    I think it is not a big deal.
1988                  */
1989                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1990                         if (vcpu->cpu != cpu) {
1991                                 dest = cpu_physical_id(cpu);
1992
1993                                 if (x2apic_enabled())
1994                                         new.ndst = dest;
1995                                 else
1996                                         new.ndst = (dest << 8) & 0xFF00;
1997                         }
1998
1999                         /* set 'NV' to 'notification vector' */
2000                         new.nv = POSTED_INTR_VECTOR;
2001                 }
2002
2003                 /* Allow posting non-urgent interrupts */
2004                 new.sn = 0;
2005         } while (cmpxchg(&pi_desc->control, old.control,
2006                         new.control) != old.control);
2007 }
2008 /*
2009  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2010  * vcpu mutex is already taken.
2011  */
2012 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2013 {
2014         struct vcpu_vmx *vmx = to_vmx(vcpu);
2015         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2016
2017         if (!vmm_exclusive)
2018                 kvm_cpu_vmxon(phys_addr);
2019         else if (vmx->loaded_vmcs->cpu != cpu)
2020                 loaded_vmcs_clear(vmx->loaded_vmcs);
2021
2022         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2023                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2024                 vmcs_load(vmx->loaded_vmcs->vmcs);
2025         }
2026
2027         if (vmx->loaded_vmcs->cpu != cpu) {
2028                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2029                 unsigned long sysenter_esp;
2030
2031                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2032                 local_irq_disable();
2033                 crash_disable_local_vmclear(cpu);
2034
2035                 /*
2036                  * Read loaded_vmcs->cpu should be before fetching
2037                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2038                  * See the comments in __loaded_vmcs_clear().
2039                  */
2040                 smp_rmb();
2041
2042                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2043                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2044                 crash_enable_local_vmclear(cpu);
2045                 local_irq_enable();
2046
2047                 /*
2048                  * Linux uses per-cpu TSS and GDT, so set these when switching
2049                  * processors.
2050                  */
2051                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2052                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2053
2054                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2055                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2056                 vmx->loaded_vmcs->cpu = cpu;
2057         }
2058
2059         vmx_vcpu_pi_load(vcpu, cpu);
2060 }
2061
2062 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2063 {
2064         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2065
2066         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2067                 !irq_remapping_cap(IRQ_POSTING_CAP))
2068                 return;
2069
2070         /* Set SN when the vCPU is preempted */
2071         if (vcpu->preempted)
2072                 pi_set_sn(pi_desc);
2073 }
2074
2075 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2076 {
2077         vmx_vcpu_pi_put(vcpu);
2078
2079         __vmx_load_host_state(to_vmx(vcpu));
2080         if (!vmm_exclusive) {
2081                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2082                 vcpu->cpu = -1;
2083                 kvm_cpu_vmxoff();
2084         }
2085 }
2086
2087 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2088 {
2089         ulong cr0;
2090
2091         if (vcpu->fpu_active)
2092                 return;
2093         vcpu->fpu_active = 1;
2094         cr0 = vmcs_readl(GUEST_CR0);
2095         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2096         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2097         vmcs_writel(GUEST_CR0, cr0);
2098         update_exception_bitmap(vcpu);
2099         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2100         if (is_guest_mode(vcpu))
2101                 vcpu->arch.cr0_guest_owned_bits &=
2102                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2103         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2104 }
2105
2106 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2107
2108 /*
2109  * Return the cr0 value that a nested guest would read. This is a combination
2110  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2111  * its hypervisor (cr0_read_shadow).
2112  */
2113 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2114 {
2115         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2116                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2117 }
2118 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2119 {
2120         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2121                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2122 }
2123
2124 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2125 {
2126         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2127          * set this *before* calling this function.
2128          */
2129         vmx_decache_cr0_guest_bits(vcpu);
2130         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2131         update_exception_bitmap(vcpu);
2132         vcpu->arch.cr0_guest_owned_bits = 0;
2133         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2134         if (is_guest_mode(vcpu)) {
2135                 /*
2136                  * L1's specified read shadow might not contain the TS bit,
2137                  * so now that we turned on shadowing of this bit, we need to
2138                  * set this bit of the shadow. Like in nested_vmx_run we need
2139                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2140                  * up-to-date here because we just decached cr0.TS (and we'll
2141                  * only update vmcs12->guest_cr0 on nested exit).
2142                  */
2143                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2144                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2145                         (vcpu->arch.cr0 & X86_CR0_TS);
2146                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2147         } else
2148                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2149 }
2150
2151 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2152 {
2153         unsigned long rflags, save_rflags;
2154
2155         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2156                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2157                 rflags = vmcs_readl(GUEST_RFLAGS);
2158                 if (to_vmx(vcpu)->rmode.vm86_active) {
2159                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2160                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2161                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2162                 }
2163                 to_vmx(vcpu)->rflags = rflags;
2164         }
2165         return to_vmx(vcpu)->rflags;
2166 }
2167
2168 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2169 {
2170         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2171         to_vmx(vcpu)->rflags = rflags;
2172         if (to_vmx(vcpu)->rmode.vm86_active) {
2173                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2174                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2175         }
2176         vmcs_writel(GUEST_RFLAGS, rflags);
2177 }
2178
2179 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2180 {
2181         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2182         int ret = 0;
2183
2184         if (interruptibility & GUEST_INTR_STATE_STI)
2185                 ret |= KVM_X86_SHADOW_INT_STI;
2186         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2187                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2188
2189         return ret;
2190 }
2191
2192 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2193 {
2194         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2195         u32 interruptibility = interruptibility_old;
2196
2197         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2198
2199         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2200                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2201         else if (mask & KVM_X86_SHADOW_INT_STI)
2202                 interruptibility |= GUEST_INTR_STATE_STI;
2203
2204         if ((interruptibility != interruptibility_old))
2205                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2206 }
2207
2208 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2209 {
2210         unsigned long rip;
2211
2212         rip = kvm_rip_read(vcpu);
2213         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2214         kvm_rip_write(vcpu, rip);
2215
2216         /* skipping an emulated instruction also counts */
2217         vmx_set_interrupt_shadow(vcpu, 0);
2218 }
2219
2220 /*
2221  * KVM wants to inject page-faults which it got to the guest. This function
2222  * checks whether in a nested guest, we need to inject them to L1 or L2.
2223  */
2224 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2225 {
2226         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2227
2228         if (!(vmcs12->exception_bitmap & (1u << nr)))
2229                 return 0;
2230
2231         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2232                           vmcs_read32(VM_EXIT_INTR_INFO),
2233                           vmcs_readl(EXIT_QUALIFICATION));
2234         return 1;
2235 }
2236
2237 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2238                                 bool has_error_code, u32 error_code,
2239                                 bool reinject)
2240 {
2241         struct vcpu_vmx *vmx = to_vmx(vcpu);
2242         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2243
2244         if (!reinject && is_guest_mode(vcpu) &&
2245             nested_vmx_check_exception(vcpu, nr))
2246                 return;
2247
2248         if (has_error_code) {
2249                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2250                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2251         }
2252
2253         if (vmx->rmode.vm86_active) {
2254                 int inc_eip = 0;
2255                 if (kvm_exception_is_soft(nr))
2256                         inc_eip = vcpu->arch.event_exit_inst_len;
2257                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2258                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2259                 return;
2260         }
2261
2262         if (kvm_exception_is_soft(nr)) {
2263                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2264                              vmx->vcpu.arch.event_exit_inst_len);
2265                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2266         } else
2267                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2268
2269         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2270 }
2271
2272 static bool vmx_rdtscp_supported(void)
2273 {
2274         return cpu_has_vmx_rdtscp();
2275 }
2276
2277 static bool vmx_invpcid_supported(void)
2278 {
2279         return cpu_has_vmx_invpcid() && enable_ept;
2280 }
2281
2282 /*
2283  * Swap MSR entry in host/guest MSR entry array.
2284  */
2285 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2286 {
2287         struct shared_msr_entry tmp;
2288
2289         tmp = vmx->guest_msrs[to];
2290         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2291         vmx->guest_msrs[from] = tmp;
2292 }
2293
2294 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2295 {
2296         unsigned long *msr_bitmap;
2297
2298         if (is_guest_mode(vcpu))
2299                 msr_bitmap = vmx_msr_bitmap_nested;
2300         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2301                 if (is_long_mode(vcpu))
2302                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2303                 else
2304                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2305         } else {
2306                 if (is_long_mode(vcpu))
2307                         msr_bitmap = vmx_msr_bitmap_longmode;
2308                 else
2309                         msr_bitmap = vmx_msr_bitmap_legacy;
2310         }
2311
2312         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2313 }
2314
2315 /*
2316  * Set up the vmcs to automatically save and restore system
2317  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2318  * mode, as fiddling with msrs is very expensive.
2319  */
2320 static void setup_msrs(struct vcpu_vmx *vmx)
2321 {
2322         int save_nmsrs, index;
2323
2324         save_nmsrs = 0;
2325 #ifdef CONFIG_X86_64
2326         if (is_long_mode(&vmx->vcpu)) {
2327                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2328                 if (index >= 0)
2329                         move_msr_up(vmx, index, save_nmsrs++);
2330                 index = __find_msr_index(vmx, MSR_LSTAR);
2331                 if (index >= 0)
2332                         move_msr_up(vmx, index, save_nmsrs++);
2333                 index = __find_msr_index(vmx, MSR_CSTAR);
2334                 if (index >= 0)
2335                         move_msr_up(vmx, index, save_nmsrs++);
2336                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2337                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2338                         move_msr_up(vmx, index, save_nmsrs++);
2339                 /*
2340                  * MSR_STAR is only needed on long mode guests, and only
2341                  * if efer.sce is enabled.
2342                  */
2343                 index = __find_msr_index(vmx, MSR_STAR);
2344                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2345                         move_msr_up(vmx, index, save_nmsrs++);
2346         }
2347 #endif
2348         index = __find_msr_index(vmx, MSR_EFER);
2349         if (index >= 0 && update_transition_efer(vmx, index))
2350                 move_msr_up(vmx, index, save_nmsrs++);
2351
2352         vmx->save_nmsrs = save_nmsrs;
2353
2354         if (cpu_has_vmx_msr_bitmap())
2355                 vmx_set_msr_bitmap(&vmx->vcpu);
2356 }
2357
2358 /*
2359  * reads and returns guest's timestamp counter "register"
2360  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2361  */
2362 static u64 guest_read_tsc(void)
2363 {
2364         u64 host_tsc, tsc_offset;
2365
2366         host_tsc = rdtsc();
2367         tsc_offset = vmcs_read64(TSC_OFFSET);
2368         return host_tsc + tsc_offset;
2369 }
2370
2371 /*
2372  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2373  * counter, even if a nested guest (L2) is currently running.
2374  */
2375 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2376 {
2377         u64 tsc_offset;
2378
2379         tsc_offset = is_guest_mode(vcpu) ?
2380                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2381                 vmcs_read64(TSC_OFFSET);
2382         return host_tsc + tsc_offset;
2383 }
2384
2385 /*
2386  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2387  * software catchup for faster rates on slower CPUs.
2388  */
2389 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2390 {
2391         if (!scale)
2392                 return;
2393
2394         if (user_tsc_khz > tsc_khz) {
2395                 vcpu->arch.tsc_catchup = 1;
2396                 vcpu->arch.tsc_always_catchup = 1;
2397         } else
2398                 WARN(1, "user requested TSC rate below hardware speed\n");
2399 }
2400
2401 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2402 {
2403         return vmcs_read64(TSC_OFFSET);
2404 }
2405
2406 /*
2407  * writes 'offset' into guest's timestamp counter offset register
2408  */
2409 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2410 {
2411         if (is_guest_mode(vcpu)) {
2412                 /*
2413                  * We're here if L1 chose not to trap WRMSR to TSC. According
2414                  * to the spec, this should set L1's TSC; The offset that L1
2415                  * set for L2 remains unchanged, and still needs to be added
2416                  * to the newly set TSC to get L2's TSC.
2417                  */
2418                 struct vmcs12 *vmcs12;
2419                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2420                 /* recalculate vmcs02.TSC_OFFSET: */
2421                 vmcs12 = get_vmcs12(vcpu);
2422                 vmcs_write64(TSC_OFFSET, offset +
2423                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2424                          vmcs12->tsc_offset : 0));
2425         } else {
2426                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2427                                            vmcs_read64(TSC_OFFSET), offset);
2428                 vmcs_write64(TSC_OFFSET, offset);
2429         }
2430 }
2431
2432 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2433 {
2434         u64 offset = vmcs_read64(TSC_OFFSET);
2435
2436         vmcs_write64(TSC_OFFSET, offset + adjustment);
2437         if (is_guest_mode(vcpu)) {
2438                 /* Even when running L2, the adjustment needs to apply to L1 */
2439                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2440         } else
2441                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2442                                            offset + adjustment);
2443 }
2444
2445 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2446 {
2447         return target_tsc - rdtsc();
2448 }
2449
2450 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2451 {
2452         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2453         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2454 }
2455
2456 /*
2457  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2458  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2459  * all guests if the "nested" module option is off, and can also be disabled
2460  * for a single guest by disabling its VMX cpuid bit.
2461  */
2462 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2463 {
2464         return nested && guest_cpuid_has_vmx(vcpu);
2465 }
2466
2467 /*
2468  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2469  * returned for the various VMX controls MSRs when nested VMX is enabled.
2470  * The same values should also be used to verify that vmcs12 control fields are
2471  * valid during nested entry from L1 to L2.
2472  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2473  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2474  * bit in the high half is on if the corresponding bit in the control field
2475  * may be on. See also vmx_control_verify().
2476  */
2477 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2478 {
2479         /*
2480          * Note that as a general rule, the high half of the MSRs (bits in
2481          * the control fields which may be 1) should be initialized by the
2482          * intersection of the underlying hardware's MSR (i.e., features which
2483          * can be supported) and the list of features we want to expose -
2484          * because they are known to be properly supported in our code.
2485          * Also, usually, the low half of the MSRs (bits which must be 1) can
2486          * be set to 0, meaning that L1 may turn off any of these bits. The
2487          * reason is that if one of these bits is necessary, it will appear
2488          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2489          * fields of vmcs01 and vmcs02, will turn these bits off - and
2490          * nested_vmx_exit_handled() will not pass related exits to L1.
2491          * These rules have exceptions below.
2492          */
2493
2494         /* pin-based controls */
2495         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2496                 vmx->nested.nested_vmx_pinbased_ctls_low,
2497                 vmx->nested.nested_vmx_pinbased_ctls_high);
2498         vmx->nested.nested_vmx_pinbased_ctls_low |=
2499                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2500         vmx->nested.nested_vmx_pinbased_ctls_high &=
2501                 PIN_BASED_EXT_INTR_MASK |
2502                 PIN_BASED_NMI_EXITING |
2503                 PIN_BASED_VIRTUAL_NMIS;
2504         vmx->nested.nested_vmx_pinbased_ctls_high |=
2505                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2506                 PIN_BASED_VMX_PREEMPTION_TIMER;
2507         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2508                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2509                         PIN_BASED_POSTED_INTR;
2510
2511         /* exit controls */
2512         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2513                 vmx->nested.nested_vmx_exit_ctls_low,
2514                 vmx->nested.nested_vmx_exit_ctls_high);
2515         vmx->nested.nested_vmx_exit_ctls_low =
2516                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2517
2518         vmx->nested.nested_vmx_exit_ctls_high &=
2519 #ifdef CONFIG_X86_64
2520                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2521 #endif
2522                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2523         vmx->nested.nested_vmx_exit_ctls_high |=
2524                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2525                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2526                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2527
2528         if (vmx_mpx_supported())
2529                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2530
2531         /* We support free control of debug control saving. */
2532         vmx->nested.nested_vmx_true_exit_ctls_low =
2533                 vmx->nested.nested_vmx_exit_ctls_low &
2534                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2535
2536         /* entry controls */
2537         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2538                 vmx->nested.nested_vmx_entry_ctls_low,
2539                 vmx->nested.nested_vmx_entry_ctls_high);
2540         vmx->nested.nested_vmx_entry_ctls_low =
2541                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2542         vmx->nested.nested_vmx_entry_ctls_high &=
2543 #ifdef CONFIG_X86_64
2544                 VM_ENTRY_IA32E_MODE |
2545 #endif
2546                 VM_ENTRY_LOAD_IA32_PAT;
2547         vmx->nested.nested_vmx_entry_ctls_high |=
2548                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2549         if (vmx_mpx_supported())
2550                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2551
2552         /* We support free control of debug control loading. */
2553         vmx->nested.nested_vmx_true_entry_ctls_low =
2554                 vmx->nested.nested_vmx_entry_ctls_low &
2555                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2556
2557         /* cpu-based controls */
2558         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2559                 vmx->nested.nested_vmx_procbased_ctls_low,
2560                 vmx->nested.nested_vmx_procbased_ctls_high);
2561         vmx->nested.nested_vmx_procbased_ctls_low =
2562                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2563         vmx->nested.nested_vmx_procbased_ctls_high &=
2564                 CPU_BASED_VIRTUAL_INTR_PENDING |
2565                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2566                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2567                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2568                 CPU_BASED_CR3_STORE_EXITING |
2569 #ifdef CONFIG_X86_64
2570                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2571 #endif
2572                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2573                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2574                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2575                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2576                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2577         /*
2578          * We can allow some features even when not supported by the
2579          * hardware. For example, L1 can specify an MSR bitmap - and we
2580          * can use it to avoid exits to L1 - even when L0 runs L2
2581          * without MSR bitmaps.
2582          */
2583         vmx->nested.nested_vmx_procbased_ctls_high |=
2584                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2585                 CPU_BASED_USE_MSR_BITMAPS;
2586
2587         /* We support free control of CR3 access interception. */
2588         vmx->nested.nested_vmx_true_procbased_ctls_low =
2589                 vmx->nested.nested_vmx_procbased_ctls_low &
2590                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2591
2592         /* secondary cpu-based controls */
2593         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2594                 vmx->nested.nested_vmx_secondary_ctls_low,
2595                 vmx->nested.nested_vmx_secondary_ctls_high);
2596         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2597         vmx->nested.nested_vmx_secondary_ctls_high &=
2598                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2599                 SECONDARY_EXEC_RDTSCP |
2600                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2601                 SECONDARY_EXEC_ENABLE_VPID |
2602                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2603                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2604                 SECONDARY_EXEC_WBINVD_EXITING |
2605                 SECONDARY_EXEC_XSAVES |
2606                 SECONDARY_EXEC_PCOMMIT;
2607
2608         if (enable_ept) {
2609                 /* nested EPT: emulate EPT also to L1 */
2610                 vmx->nested.nested_vmx_secondary_ctls_high |=
2611                         SECONDARY_EXEC_ENABLE_EPT;
2612                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2613                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2614                          VMX_EPT_INVEPT_BIT;
2615                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2616                 /*
2617                  * For nested guests, we don't do anything specific
2618                  * for single context invalidation. Hence, only advertise
2619                  * support for global context invalidation.
2620                  */
2621                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2622         } else
2623                 vmx->nested.nested_vmx_ept_caps = 0;
2624
2625         if (enable_vpid)
2626                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2627                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2628         else
2629                 vmx->nested.nested_vmx_vpid_caps = 0;
2630
2631         if (enable_unrestricted_guest)
2632                 vmx->nested.nested_vmx_secondary_ctls_high |=
2633                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2634
2635         /* miscellaneous data */
2636         rdmsr(MSR_IA32_VMX_MISC,
2637                 vmx->nested.nested_vmx_misc_low,
2638                 vmx->nested.nested_vmx_misc_high);
2639         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2640         vmx->nested.nested_vmx_misc_low |=
2641                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2642                 VMX_MISC_ACTIVITY_HLT;
2643         vmx->nested.nested_vmx_misc_high = 0;
2644 }
2645
2646 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2647 {
2648         /*
2649          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2650          */
2651         return ((control & high) | low) == control;
2652 }
2653
2654 static inline u64 vmx_control_msr(u32 low, u32 high)
2655 {
2656         return low | ((u64)high << 32);
2657 }
2658
2659 /* Returns 0 on success, non-0 otherwise. */
2660 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2661 {
2662         struct vcpu_vmx *vmx = to_vmx(vcpu);
2663
2664         switch (msr_index) {
2665         case MSR_IA32_VMX_BASIC:
2666                 /*
2667                  * This MSR reports some information about VMX support. We
2668                  * should return information about the VMX we emulate for the
2669                  * guest, and the VMCS structure we give it - not about the
2670                  * VMX support of the underlying hardware.
2671                  */
2672                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2673                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2674                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2675                 break;
2676         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2677         case MSR_IA32_VMX_PINBASED_CTLS:
2678                 *pdata = vmx_control_msr(
2679                         vmx->nested.nested_vmx_pinbased_ctls_low,
2680                         vmx->nested.nested_vmx_pinbased_ctls_high);
2681                 break;
2682         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2683                 *pdata = vmx_control_msr(
2684                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2685                         vmx->nested.nested_vmx_procbased_ctls_high);
2686                 break;
2687         case MSR_IA32_VMX_PROCBASED_CTLS:
2688                 *pdata = vmx_control_msr(
2689                         vmx->nested.nested_vmx_procbased_ctls_low,
2690                         vmx->nested.nested_vmx_procbased_ctls_high);
2691                 break;
2692         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2693                 *pdata = vmx_control_msr(
2694                         vmx->nested.nested_vmx_true_exit_ctls_low,
2695                         vmx->nested.nested_vmx_exit_ctls_high);
2696                 break;
2697         case MSR_IA32_VMX_EXIT_CTLS:
2698                 *pdata = vmx_control_msr(
2699                         vmx->nested.nested_vmx_exit_ctls_low,
2700                         vmx->nested.nested_vmx_exit_ctls_high);
2701                 break;
2702         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2703                 *pdata = vmx_control_msr(
2704                         vmx->nested.nested_vmx_true_entry_ctls_low,
2705                         vmx->nested.nested_vmx_entry_ctls_high);
2706                 break;
2707         case MSR_IA32_VMX_ENTRY_CTLS:
2708                 *pdata = vmx_control_msr(
2709                         vmx->nested.nested_vmx_entry_ctls_low,
2710                         vmx->nested.nested_vmx_entry_ctls_high);
2711                 break;
2712         case MSR_IA32_VMX_MISC:
2713                 *pdata = vmx_control_msr(
2714                         vmx->nested.nested_vmx_misc_low,
2715                         vmx->nested.nested_vmx_misc_high);
2716                 break;
2717         /*
2718          * These MSRs specify bits which the guest must keep fixed (on or off)
2719          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2720          * We picked the standard core2 setting.
2721          */
2722 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2723 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2724         case MSR_IA32_VMX_CR0_FIXED0:
2725                 *pdata = VMXON_CR0_ALWAYSON;
2726                 break;
2727         case MSR_IA32_VMX_CR0_FIXED1:
2728                 *pdata = -1ULL;
2729                 break;
2730         case MSR_IA32_VMX_CR4_FIXED0:
2731                 *pdata = VMXON_CR4_ALWAYSON;
2732                 break;
2733         case MSR_IA32_VMX_CR4_FIXED1:
2734                 *pdata = -1ULL;
2735                 break;
2736         case MSR_IA32_VMX_VMCS_ENUM:
2737                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2738                 break;
2739         case MSR_IA32_VMX_PROCBASED_CTLS2:
2740                 *pdata = vmx_control_msr(
2741                         vmx->nested.nested_vmx_secondary_ctls_low,
2742                         vmx->nested.nested_vmx_secondary_ctls_high);
2743                 break;
2744         case MSR_IA32_VMX_EPT_VPID_CAP:
2745                 /* Currently, no nested vpid support */
2746                 *pdata = vmx->nested.nested_vmx_ept_caps |
2747                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2748                 break;
2749         default:
2750                 return 1;
2751         }
2752
2753         return 0;
2754 }
2755
2756 /*
2757  * Reads an msr value (of 'msr_index') into 'pdata'.
2758  * Returns 0 on success, non-0 otherwise.
2759  * Assumes vcpu_load() was already called.
2760  */
2761 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2762 {
2763         struct shared_msr_entry *msr;
2764
2765         switch (msr_info->index) {
2766 #ifdef CONFIG_X86_64
2767         case MSR_FS_BASE:
2768                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2769                 break;
2770         case MSR_GS_BASE:
2771                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2772                 break;
2773         case MSR_KERNEL_GS_BASE:
2774                 vmx_load_host_state(to_vmx(vcpu));
2775                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2776                 break;
2777 #endif
2778         case MSR_EFER:
2779                 return kvm_get_msr_common(vcpu, msr_info);
2780         case MSR_IA32_TSC:
2781                 msr_info->data = guest_read_tsc();
2782                 break;
2783         case MSR_IA32_SYSENTER_CS:
2784                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2785                 break;
2786         case MSR_IA32_SYSENTER_EIP:
2787                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2788                 break;
2789         case MSR_IA32_SYSENTER_ESP:
2790                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2791                 break;
2792         case MSR_IA32_BNDCFGS:
2793                 if (!vmx_mpx_supported())
2794                         return 1;
2795                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2796                 break;
2797         case MSR_IA32_FEATURE_CONTROL:
2798                 if (!nested_vmx_allowed(vcpu))
2799                         return 1;
2800                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2801                 break;
2802         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2803                 if (!nested_vmx_allowed(vcpu))
2804                         return 1;
2805                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2806         case MSR_IA32_XSS:
2807                 if (!vmx_xsaves_supported())
2808                         return 1;
2809                 msr_info->data = vcpu->arch.ia32_xss;
2810                 break;
2811         case MSR_TSC_AUX:
2812                 if (!guest_cpuid_has_rdtscp(vcpu))
2813                         return 1;
2814                 /* Otherwise falls through */
2815         default:
2816                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2817                 if (msr) {
2818                         msr_info->data = msr->data;
2819                         break;
2820                 }
2821                 return kvm_get_msr_common(vcpu, msr_info);
2822         }
2823
2824         return 0;
2825 }
2826
2827 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2828
2829 /*
2830  * Writes msr value into into the appropriate "register".
2831  * Returns 0 on success, non-0 otherwise.
2832  * Assumes vcpu_load() was already called.
2833  */
2834 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2835 {
2836         struct vcpu_vmx *vmx = to_vmx(vcpu);
2837         struct shared_msr_entry *msr;
2838         int ret = 0;
2839         u32 msr_index = msr_info->index;
2840         u64 data = msr_info->data;
2841
2842         switch (msr_index) {
2843         case MSR_EFER:
2844                 ret = kvm_set_msr_common(vcpu, msr_info);
2845                 break;
2846 #ifdef CONFIG_X86_64
2847         case MSR_FS_BASE:
2848                 vmx_segment_cache_clear(vmx);
2849                 vmcs_writel(GUEST_FS_BASE, data);
2850                 break;
2851         case MSR_GS_BASE:
2852                 vmx_segment_cache_clear(vmx);
2853                 vmcs_writel(GUEST_GS_BASE, data);
2854                 break;
2855         case MSR_KERNEL_GS_BASE:
2856                 vmx_load_host_state(vmx);
2857                 vmx->msr_guest_kernel_gs_base = data;
2858                 break;
2859 #endif
2860         case MSR_IA32_SYSENTER_CS:
2861                 vmcs_write32(GUEST_SYSENTER_CS, data);
2862                 break;
2863         case MSR_IA32_SYSENTER_EIP:
2864                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2865                 break;
2866         case MSR_IA32_SYSENTER_ESP:
2867                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2868                 break;
2869         case MSR_IA32_BNDCFGS:
2870                 if (!vmx_mpx_supported())
2871                         return 1;
2872                 vmcs_write64(GUEST_BNDCFGS, data);
2873                 break;
2874         case MSR_IA32_TSC:
2875                 kvm_write_tsc(vcpu, msr_info);
2876                 break;
2877         case MSR_IA32_CR_PAT:
2878                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2879                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2880                                 return 1;
2881                         vmcs_write64(GUEST_IA32_PAT, data);
2882                         vcpu->arch.pat = data;
2883                         break;
2884                 }
2885                 ret = kvm_set_msr_common(vcpu, msr_info);
2886                 break;
2887         case MSR_IA32_TSC_ADJUST:
2888                 ret = kvm_set_msr_common(vcpu, msr_info);
2889                 break;
2890         case MSR_IA32_FEATURE_CONTROL:
2891                 if (!nested_vmx_allowed(vcpu) ||
2892                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2893                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2894                         return 1;
2895                 vmx->nested.msr_ia32_feature_control = data;
2896                 if (msr_info->host_initiated && data == 0)
2897                         vmx_leave_nested(vcpu);
2898                 break;
2899         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2900                 return 1; /* they are read-only */
2901         case MSR_IA32_XSS:
2902                 if (!vmx_xsaves_supported())
2903                         return 1;
2904                 /*
2905                  * The only supported bit as of Skylake is bit 8, but
2906                  * it is not supported on KVM.
2907                  */
2908                 if (data != 0)
2909                         return 1;
2910                 vcpu->arch.ia32_xss = data;
2911                 if (vcpu->arch.ia32_xss != host_xss)
2912                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2913                                 vcpu->arch.ia32_xss, host_xss);
2914                 else
2915                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2916                 break;
2917         case MSR_TSC_AUX:
2918                 if (!guest_cpuid_has_rdtscp(vcpu))
2919                         return 1;
2920                 /* Check reserved bit, higher 32 bits should be zero */
2921                 if ((data >> 32) != 0)
2922                         return 1;
2923                 /* Otherwise falls through */
2924         default:
2925                 msr = find_msr_entry(vmx, msr_index);
2926                 if (msr) {
2927                         u64 old_msr_data = msr->data;
2928                         msr->data = data;
2929                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2930                                 preempt_disable();
2931                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2932                                                          msr->mask);
2933                                 preempt_enable();
2934                                 if (ret)
2935                                         msr->data = old_msr_data;
2936                         }
2937                         break;
2938                 }
2939                 ret = kvm_set_msr_common(vcpu, msr_info);
2940         }
2941
2942         return ret;
2943 }
2944
2945 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2946 {
2947         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2948         switch (reg) {
2949         case VCPU_REGS_RSP:
2950                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2951                 break;
2952         case VCPU_REGS_RIP:
2953                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2954                 break;
2955         case VCPU_EXREG_PDPTR:
2956                 if (enable_ept)
2957                         ept_save_pdptrs(vcpu);
2958                 break;
2959         default:
2960                 break;
2961         }
2962 }
2963
2964 static __init int cpu_has_kvm_support(void)
2965 {
2966         return cpu_has_vmx();
2967 }
2968
2969 static __init int vmx_disabled_by_bios(void)
2970 {
2971         u64 msr;
2972
2973         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2974         if (msr & FEATURE_CONTROL_LOCKED) {
2975                 /* launched w/ TXT and VMX disabled */
2976                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2977                         && tboot_enabled())
2978                         return 1;
2979                 /* launched w/o TXT and VMX only enabled w/ TXT */
2980                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2981                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2982                         && !tboot_enabled()) {
2983                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2984                                 "activate TXT before enabling KVM\n");
2985                         return 1;
2986                 }
2987                 /* launched w/o TXT and VMX disabled */
2988                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2989                         && !tboot_enabled())
2990                         return 1;
2991         }
2992
2993         return 0;
2994 }
2995
2996 static void kvm_cpu_vmxon(u64 addr)
2997 {
2998         asm volatile (ASM_VMX_VMXON_RAX
2999                         : : "a"(&addr), "m"(addr)
3000                         : "memory", "cc");
3001 }
3002
3003 static int hardware_enable(void)
3004 {
3005         int cpu = raw_smp_processor_id();
3006         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3007         u64 old, test_bits;
3008
3009         if (cr4_read_shadow() & X86_CR4_VMXE)
3010                 return -EBUSY;
3011
3012         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3013         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3014         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3015
3016         /*
3017          * Now we can enable the vmclear operation in kdump
3018          * since the loaded_vmcss_on_cpu list on this cpu
3019          * has been initialized.
3020          *
3021          * Though the cpu is not in VMX operation now, there
3022          * is no problem to enable the vmclear operation
3023          * for the loaded_vmcss_on_cpu list is empty!
3024          */
3025         crash_enable_local_vmclear(cpu);
3026
3027         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3028
3029         test_bits = FEATURE_CONTROL_LOCKED;
3030         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3031         if (tboot_enabled())
3032                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3033
3034         if ((old & test_bits) != test_bits) {
3035                 /* enable and lock */
3036                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3037         }
3038         cr4_set_bits(X86_CR4_VMXE);
3039
3040         if (vmm_exclusive) {
3041                 kvm_cpu_vmxon(phys_addr);
3042                 ept_sync_global();
3043         }
3044
3045         native_store_gdt(this_cpu_ptr(&host_gdt));
3046
3047         return 0;
3048 }
3049
3050 static void vmclear_local_loaded_vmcss(void)
3051 {
3052         int cpu = raw_smp_processor_id();
3053         struct loaded_vmcs *v, *n;
3054
3055         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3056                                  loaded_vmcss_on_cpu_link)
3057                 __loaded_vmcs_clear(v);
3058 }
3059
3060
3061 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3062  * tricks.
3063  */
3064 static void kvm_cpu_vmxoff(void)
3065 {
3066         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3067 }
3068
3069 static void hardware_disable(void)
3070 {
3071         if (vmm_exclusive) {
3072                 vmclear_local_loaded_vmcss();
3073                 kvm_cpu_vmxoff();
3074         }
3075         cr4_clear_bits(X86_CR4_VMXE);
3076 }
3077
3078 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3079                                       u32 msr, u32 *result)
3080 {
3081         u32 vmx_msr_low, vmx_msr_high;
3082         u32 ctl = ctl_min | ctl_opt;
3083
3084         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3085
3086         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3087         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3088
3089         /* Ensure minimum (required) set of control bits are supported. */
3090         if (ctl_min & ~ctl)
3091                 return -EIO;
3092
3093         *result = ctl;
3094         return 0;
3095 }
3096
3097 static __init bool allow_1_setting(u32 msr, u32 ctl)
3098 {
3099         u32 vmx_msr_low, vmx_msr_high;
3100
3101         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3102         return vmx_msr_high & ctl;
3103 }
3104
3105 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3106 {
3107         u32 vmx_msr_low, vmx_msr_high;
3108         u32 min, opt, min2, opt2;
3109         u32 _pin_based_exec_control = 0;
3110         u32 _cpu_based_exec_control = 0;
3111         u32 _cpu_based_2nd_exec_control = 0;
3112         u32 _vmexit_control = 0;
3113         u32 _vmentry_control = 0;
3114
3115         min = CPU_BASED_HLT_EXITING |
3116 #ifdef CONFIG_X86_64
3117               CPU_BASED_CR8_LOAD_EXITING |
3118               CPU_BASED_CR8_STORE_EXITING |
3119 #endif
3120               CPU_BASED_CR3_LOAD_EXITING |
3121               CPU_BASED_CR3_STORE_EXITING |
3122               CPU_BASED_USE_IO_BITMAPS |
3123               CPU_BASED_MOV_DR_EXITING |
3124               CPU_BASED_USE_TSC_OFFSETING |
3125               CPU_BASED_MWAIT_EXITING |
3126               CPU_BASED_MONITOR_EXITING |
3127               CPU_BASED_INVLPG_EXITING |
3128               CPU_BASED_RDPMC_EXITING;
3129
3130         opt = CPU_BASED_TPR_SHADOW |
3131               CPU_BASED_USE_MSR_BITMAPS |
3132               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3133         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3134                                 &_cpu_based_exec_control) < 0)
3135                 return -EIO;
3136 #ifdef CONFIG_X86_64
3137         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3138                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3139                                            ~CPU_BASED_CR8_STORE_EXITING;
3140 #endif
3141         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3142                 min2 = 0;
3143                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3144                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3145                         SECONDARY_EXEC_WBINVD_EXITING |
3146                         SECONDARY_EXEC_ENABLE_VPID |
3147                         SECONDARY_EXEC_ENABLE_EPT |
3148                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3149                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3150                         SECONDARY_EXEC_RDTSCP |
3151                         SECONDARY_EXEC_ENABLE_INVPCID |
3152                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3153                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3154                         SECONDARY_EXEC_SHADOW_VMCS |
3155                         SECONDARY_EXEC_XSAVES |
3156                         SECONDARY_EXEC_ENABLE_PML |
3157                         SECONDARY_EXEC_PCOMMIT;
3158                 if (adjust_vmx_controls(min2, opt2,
3159                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3160                                         &_cpu_based_2nd_exec_control) < 0)
3161                         return -EIO;
3162         }
3163 #ifndef CONFIG_X86_64
3164         if (!(_cpu_based_2nd_exec_control &
3165                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3166                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3167 #endif
3168
3169         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3170                 _cpu_based_2nd_exec_control &= ~(
3171                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3172                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3173                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3174
3175         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3176                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3177                    enabled */
3178                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3179                                              CPU_BASED_CR3_STORE_EXITING |
3180                                              CPU_BASED_INVLPG_EXITING);
3181                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3182                       vmx_capability.ept, vmx_capability.vpid);
3183         }
3184
3185         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3186 #ifdef CONFIG_X86_64
3187         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3188 #endif
3189         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3190                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3191         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3192                                 &_vmexit_control) < 0)
3193                 return -EIO;
3194
3195         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3196         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3197         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3198                                 &_pin_based_exec_control) < 0)
3199                 return -EIO;
3200
3201         if (!(_cpu_based_2nd_exec_control &
3202                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3203                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3204                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3205
3206         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3207         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3208         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3209                                 &_vmentry_control) < 0)
3210                 return -EIO;
3211
3212         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3213
3214         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3215         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3216                 return -EIO;
3217
3218 #ifdef CONFIG_X86_64
3219         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3220         if (vmx_msr_high & (1u<<16))
3221                 return -EIO;
3222 #endif
3223
3224         /* Require Write-Back (WB) memory type for VMCS accesses. */
3225         if (((vmx_msr_high >> 18) & 15) != 6)
3226                 return -EIO;
3227
3228         vmcs_conf->size = vmx_msr_high & 0x1fff;
3229         vmcs_conf->order = get_order(vmcs_config.size);
3230         vmcs_conf->revision_id = vmx_msr_low;
3231
3232         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3233         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3234         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3235         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3236         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3237
3238         cpu_has_load_ia32_efer =
3239                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3240                                 VM_ENTRY_LOAD_IA32_EFER)
3241                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3242                                    VM_EXIT_LOAD_IA32_EFER);
3243
3244         cpu_has_load_perf_global_ctrl =
3245                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3246                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3247                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3248                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3249
3250         /*
3251          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3252          * but due to arrata below it can't be used. Workaround is to use
3253          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3254          *
3255          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3256          *
3257          * AAK155             (model 26)
3258          * AAP115             (model 30)
3259          * AAT100             (model 37)
3260          * BC86,AAY89,BD102   (model 44)
3261          * BA97               (model 46)
3262          *
3263          */
3264         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3265                 switch (boot_cpu_data.x86_model) {
3266                 case 26:
3267                 case 30:
3268                 case 37:
3269                 case 44:
3270                 case 46:
3271                         cpu_has_load_perf_global_ctrl = false;
3272                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3273                                         "does not work properly. Using workaround\n");
3274                         break;
3275                 default:
3276                         break;
3277                 }
3278         }
3279
3280         if (cpu_has_xsaves)
3281                 rdmsrl(MSR_IA32_XSS, host_xss);
3282
3283         return 0;
3284 }
3285
3286 static struct vmcs *alloc_vmcs_cpu(int cpu)
3287 {
3288         int node = cpu_to_node(cpu);
3289         struct page *pages;
3290         struct vmcs *vmcs;
3291
3292         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3293         if (!pages)
3294                 return NULL;
3295         vmcs = page_address(pages);
3296         memset(vmcs, 0, vmcs_config.size);
3297         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3298         return vmcs;
3299 }
3300
3301 static struct vmcs *alloc_vmcs(void)
3302 {
3303         return alloc_vmcs_cpu(raw_smp_processor_id());
3304 }
3305
3306 static void free_vmcs(struct vmcs *vmcs)
3307 {
3308         free_pages((unsigned long)vmcs, vmcs_config.order);
3309 }
3310
3311 /*
3312  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3313  */
3314 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3315 {
3316         if (!loaded_vmcs->vmcs)
3317                 return;
3318         loaded_vmcs_clear(loaded_vmcs);
3319         free_vmcs(loaded_vmcs->vmcs);
3320         loaded_vmcs->vmcs = NULL;
3321 }
3322
3323 static void free_kvm_area(void)
3324 {
3325         int cpu;
3326
3327         for_each_possible_cpu(cpu) {
3328                 free_vmcs(per_cpu(vmxarea, cpu));
3329                 per_cpu(vmxarea, cpu) = NULL;
3330         }
3331 }
3332
3333 static void init_vmcs_shadow_fields(void)
3334 {
3335         int i, j;
3336
3337         /* No checks for read only fields yet */
3338
3339         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3340                 switch (shadow_read_write_fields[i]) {
3341                 case GUEST_BNDCFGS:
3342                         if (!vmx_mpx_supported())
3343                                 continue;
3344                         break;
3345                 default:
3346                         break;
3347                 }
3348
3349                 if (j < i)
3350                         shadow_read_write_fields[j] =
3351                                 shadow_read_write_fields[i];
3352                 j++;
3353         }
3354         max_shadow_read_write_fields = j;
3355
3356         /* shadowed fields guest access without vmexit */
3357         for (i = 0; i < max_shadow_read_write_fields; i++) {
3358                 clear_bit(shadow_read_write_fields[i],
3359                           vmx_vmwrite_bitmap);
3360                 clear_bit(shadow_read_write_fields[i],
3361                           vmx_vmread_bitmap);
3362         }
3363         for (i = 0; i < max_shadow_read_only_fields; i++)
3364                 clear_bit(shadow_read_only_fields[i],
3365                           vmx_vmread_bitmap);
3366 }
3367
3368 static __init int alloc_kvm_area(void)
3369 {
3370         int cpu;
3371
3372         for_each_possible_cpu(cpu) {
3373                 struct vmcs *vmcs;
3374
3375                 vmcs = alloc_vmcs_cpu(cpu);
3376                 if (!vmcs) {
3377                         free_kvm_area();
3378                         return -ENOMEM;
3379                 }
3380
3381                 per_cpu(vmxarea, cpu) = vmcs;
3382         }
3383         return 0;
3384 }
3385
3386 static bool emulation_required(struct kvm_vcpu *vcpu)
3387 {
3388         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3389 }
3390
3391 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3392                 struct kvm_segment *save)
3393 {
3394         if (!emulate_invalid_guest_state) {
3395                 /*
3396                  * CS and SS RPL should be equal during guest entry according
3397                  * to VMX spec, but in reality it is not always so. Since vcpu
3398                  * is in the middle of the transition from real mode to
3399                  * protected mode it is safe to assume that RPL 0 is a good
3400                  * default value.
3401                  */
3402                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3403                         save->selector &= ~SEGMENT_RPL_MASK;
3404                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3405                 save->s = 1;
3406         }
3407         vmx_set_segment(vcpu, save, seg);
3408 }
3409
3410 static void enter_pmode(struct kvm_vcpu *vcpu)
3411 {
3412         unsigned long flags;
3413         struct vcpu_vmx *vmx = to_vmx(vcpu);
3414
3415         /*
3416          * Update real mode segment cache. It may be not up-to-date if sement
3417          * register was written while vcpu was in a guest mode.
3418          */
3419         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3420         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3421         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3422         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3423         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3424         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3425
3426         vmx->rmode.vm86_active = 0;
3427
3428         vmx_segment_cache_clear(vmx);
3429
3430         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3431
3432         flags = vmcs_readl(GUEST_RFLAGS);
3433         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3434         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3435         vmcs_writel(GUEST_RFLAGS, flags);
3436
3437         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3438                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3439
3440         update_exception_bitmap(vcpu);
3441
3442         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3443         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3444         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3445         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3446         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3447         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3448 }
3449
3450 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3451 {
3452         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3453         struct kvm_segment var = *save;
3454
3455         var.dpl = 0x3;
3456         if (seg == VCPU_SREG_CS)
3457                 var.type = 0x3;
3458
3459         if (!emulate_invalid_guest_state) {
3460                 var.selector = var.base >> 4;
3461                 var.base = var.base & 0xffff0;
3462                 var.limit = 0xffff;
3463                 var.g = 0;
3464                 var.db = 0;
3465                 var.present = 1;
3466                 var.s = 1;
3467                 var.l = 0;
3468                 var.unusable = 0;
3469                 var.type = 0x3;
3470                 var.avl = 0;
3471                 if (save->base & 0xf)
3472                         printk_once(KERN_WARNING "kvm: segment base is not "
3473                                         "paragraph aligned when entering "
3474                                         "protected mode (seg=%d)", seg);
3475         }
3476
3477         vmcs_write16(sf->selector, var.selector);
3478         vmcs_write32(sf->base, var.base);
3479         vmcs_write32(sf->limit, var.limit);
3480         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3481 }
3482
3483 static void enter_rmode(struct kvm_vcpu *vcpu)
3484 {
3485         unsigned long flags;
3486         struct vcpu_vmx *vmx = to_vmx(vcpu);
3487
3488         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3489         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3490         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3491         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3492         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3493         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3494         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3495
3496         vmx->rmode.vm86_active = 1;
3497
3498         /*
3499          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3500          * vcpu. Warn the user that an update is overdue.
3501          */
3502         if (!vcpu->kvm->arch.tss_addr)
3503                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3504                              "called before entering vcpu\n");
3505
3506         vmx_segment_cache_clear(vmx);
3507
3508         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3509         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3510         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3511
3512         flags = vmcs_readl(GUEST_RFLAGS);
3513         vmx->rmode.save_rflags = flags;
3514
3515         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3516
3517         vmcs_writel(GUEST_RFLAGS, flags);
3518         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3519         update_exception_bitmap(vcpu);
3520
3521         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3522         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3523         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3524         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3525         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3526         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3527
3528         kvm_mmu_reset_context(vcpu);
3529 }
3530
3531 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3532 {
3533         struct vcpu_vmx *vmx = to_vmx(vcpu);
3534         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3535
3536         if (!msr)
3537                 return;
3538
3539         /*
3540          * Force kernel_gs_base reloading before EFER changes, as control
3541          * of this msr depends on is_long_mode().
3542          */
3543         vmx_load_host_state(to_vmx(vcpu));
3544         vcpu->arch.efer = efer;
3545         if (efer & EFER_LMA) {
3546                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3547                 msr->data = efer;
3548         } else {
3549                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3550
3551                 msr->data = efer & ~EFER_LME;
3552         }
3553         setup_msrs(vmx);
3554 }
3555
3556 #ifdef CONFIG_X86_64
3557
3558 static void enter_lmode(struct kvm_vcpu *vcpu)
3559 {
3560         u32 guest_tr_ar;
3561
3562         vmx_segment_cache_clear(to_vmx(vcpu));
3563
3564         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3565         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3566                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3567                                      __func__);
3568                 vmcs_write32(GUEST_TR_AR_BYTES,
3569                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3570                              | VMX_AR_TYPE_BUSY_64_TSS);
3571         }
3572         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3573 }
3574
3575 static void exit_lmode(struct kvm_vcpu *vcpu)
3576 {
3577         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3578         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3579 }
3580
3581 #endif
3582
3583 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3584 {
3585         vpid_sync_context(vpid);
3586         if (enable_ept) {
3587                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3588                         return;
3589                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3590         }
3591 }
3592
3593 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3594 {
3595         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3596 }
3597
3598 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3599 {
3600         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3601
3602         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3603         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3604 }
3605
3606 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3607 {
3608         if (enable_ept && is_paging(vcpu))
3609                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3610         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3611 }
3612
3613 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3614 {
3615         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3616
3617         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3618         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3619 }
3620
3621 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3622 {
3623         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3624
3625         if (!test_bit(VCPU_EXREG_PDPTR,
3626                       (unsigned long *)&vcpu->arch.regs_dirty))
3627                 return;
3628
3629         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3630                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3631                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3632                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3633                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3634         }
3635 }
3636
3637 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3638 {
3639         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3640
3641         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3642                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3643                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3644                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3645                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3646         }
3647
3648         __set_bit(VCPU_EXREG_PDPTR,
3649                   (unsigned long *)&vcpu->arch.regs_avail);
3650         __set_bit(VCPU_EXREG_PDPTR,
3651                   (unsigned long *)&vcpu->arch.regs_dirty);
3652 }
3653
3654 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3655
3656 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3657                                         unsigned long cr0,
3658                                         struct kvm_vcpu *vcpu)
3659 {
3660         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3661                 vmx_decache_cr3(vcpu);
3662         if (!(cr0 & X86_CR0_PG)) {
3663                 /* From paging/starting to nonpaging */
3664                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3665                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3666                              (CPU_BASED_CR3_LOAD_EXITING |
3667                               CPU_BASED_CR3_STORE_EXITING));
3668                 vcpu->arch.cr0 = cr0;
3669                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3670         } else if (!is_paging(vcpu)) {
3671                 /* From nonpaging to paging */
3672                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3673                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3674                              ~(CPU_BASED_CR3_LOAD_EXITING |
3675                                CPU_BASED_CR3_STORE_EXITING));
3676                 vcpu->arch.cr0 = cr0;
3677                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3678         }
3679
3680         if (!(cr0 & X86_CR0_WP))
3681                 *hw_cr0 &= ~X86_CR0_WP;
3682 }
3683
3684 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3685 {
3686         struct vcpu_vmx *vmx = to_vmx(vcpu);
3687         unsigned long hw_cr0;
3688
3689         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3690         if (enable_unrestricted_guest)
3691                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3692         else {
3693                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3694
3695                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3696                         enter_pmode(vcpu);
3697
3698                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3699                         enter_rmode(vcpu);
3700         }
3701
3702 #ifdef CONFIG_X86_64
3703         if (vcpu->arch.efer & EFER_LME) {
3704                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3705                         enter_lmode(vcpu);
3706                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3707                         exit_lmode(vcpu);
3708         }
3709 #endif
3710
3711         if (enable_ept)
3712                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3713
3714         if (!vcpu->fpu_active)
3715                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3716
3717         vmcs_writel(CR0_READ_SHADOW, cr0);
3718         vmcs_writel(GUEST_CR0, hw_cr0);
3719         vcpu->arch.cr0 = cr0;
3720
3721         /* depends on vcpu->arch.cr0 to be set to a new value */
3722         vmx->emulation_required = emulation_required(vcpu);
3723 }
3724
3725 static u64 construct_eptp(unsigned long root_hpa)
3726 {
3727         u64 eptp;
3728
3729         /* TODO write the value reading from MSR */
3730         eptp = VMX_EPT_DEFAULT_MT |
3731                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3732         if (enable_ept_ad_bits)
3733                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3734         eptp |= (root_hpa & PAGE_MASK);
3735
3736         return eptp;
3737 }
3738
3739 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3740 {
3741         unsigned long guest_cr3;
3742         u64 eptp;
3743
3744         guest_cr3 = cr3;
3745         if (enable_ept) {
3746                 eptp = construct_eptp(cr3);
3747                 vmcs_write64(EPT_POINTER, eptp);
3748                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3749                         guest_cr3 = kvm_read_cr3(vcpu);
3750                 else
3751                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3752                 ept_load_pdptrs(vcpu);
3753         }
3754
3755         vmx_flush_tlb(vcpu);
3756         vmcs_writel(GUEST_CR3, guest_cr3);
3757 }
3758
3759 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3760 {
3761         /*
3762          * Pass through host's Machine Check Enable value to hw_cr4, which
3763          * is in force while we are in guest mode.  Do not let guests control
3764          * this bit, even if host CR4.MCE == 0.
3765          */
3766         unsigned long hw_cr4 =
3767                 (cr4_read_shadow() & X86_CR4_MCE) |
3768                 (cr4 & ~X86_CR4_MCE) |
3769                 (to_vmx(vcpu)->rmode.vm86_active ?
3770                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3771
3772         if (cr4 & X86_CR4_VMXE) {
3773                 /*
3774                  * To use VMXON (and later other VMX instructions), a guest
3775                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3776                  * So basically the check on whether to allow nested VMX
3777                  * is here.
3778                  */
3779                 if (!nested_vmx_allowed(vcpu))
3780                         return 1;
3781         }
3782         if (to_vmx(vcpu)->nested.vmxon &&
3783             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3784                 return 1;
3785
3786         vcpu->arch.cr4 = cr4;
3787         if (enable_ept) {
3788                 if (!is_paging(vcpu)) {
3789                         hw_cr4 &= ~X86_CR4_PAE;
3790                         hw_cr4 |= X86_CR4_PSE;
3791                 } else if (!(cr4 & X86_CR4_PAE)) {
3792                         hw_cr4 &= ~X86_CR4_PAE;
3793                 }
3794         }
3795
3796         if (!enable_unrestricted_guest && !is_paging(vcpu))
3797                 /*
3798                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3799                  * hardware.  However KVM always uses paging mode without
3800                  * unrestricted guest.
3801                  * To emulate this behavior, SMEP/SMAP needs to be manually
3802                  * disabled when guest switches to non-paging mode.
3803                  */
3804                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3805
3806         vmcs_writel(CR4_READ_SHADOW, cr4);
3807         vmcs_writel(GUEST_CR4, hw_cr4);
3808         return 0;
3809 }
3810
3811 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3812                             struct kvm_segment *var, int seg)
3813 {
3814         struct vcpu_vmx *vmx = to_vmx(vcpu);
3815         u32 ar;
3816
3817         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3818                 *var = vmx->rmode.segs[seg];
3819                 if (seg == VCPU_SREG_TR
3820                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3821                         return;
3822                 var->base = vmx_read_guest_seg_base(vmx, seg);
3823                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3824                 return;
3825         }
3826         var->base = vmx_read_guest_seg_base(vmx, seg);
3827         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3828         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3829         ar = vmx_read_guest_seg_ar(vmx, seg);
3830         var->unusable = (ar >> 16) & 1;
3831         var->type = ar & 15;
3832         var->s = (ar >> 4) & 1;
3833         var->dpl = (ar >> 5) & 3;
3834         /*
3835          * Some userspaces do not preserve unusable property. Since usable
3836          * segment has to be present according to VMX spec we can use present
3837          * property to amend userspace bug by making unusable segment always
3838          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3839          * segment as unusable.
3840          */
3841         var->present = !var->unusable;
3842         var->avl = (ar >> 12) & 1;
3843         var->l = (ar >> 13) & 1;
3844         var->db = (ar >> 14) & 1;
3845         var->g = (ar >> 15) & 1;
3846 }
3847
3848 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3849 {
3850         struct kvm_segment s;
3851
3852         if (to_vmx(vcpu)->rmode.vm86_active) {
3853                 vmx_get_segment(vcpu, &s, seg);
3854                 return s.base;
3855         }
3856         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3857 }
3858
3859 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3860 {
3861         struct vcpu_vmx *vmx = to_vmx(vcpu);
3862
3863         if (unlikely(vmx->rmode.vm86_active))
3864                 return 0;
3865         else {
3866                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3867                 return VMX_AR_DPL(ar);
3868         }
3869 }
3870
3871 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3872 {
3873         u32 ar;
3874
3875         if (var->unusable || !var->present)
3876                 ar = 1 << 16;
3877         else {
3878                 ar = var->type & 15;
3879                 ar |= (var->s & 1) << 4;
3880                 ar |= (var->dpl & 3) << 5;
3881                 ar |= (var->present & 1) << 7;
3882                 ar |= (var->avl & 1) << 12;
3883                 ar |= (var->l & 1) << 13;
3884                 ar |= (var->db & 1) << 14;
3885                 ar |= (var->g & 1) << 15;
3886         }
3887
3888         return ar;
3889 }
3890
3891 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3892                             struct kvm_segment *var, int seg)
3893 {
3894         struct vcpu_vmx *vmx = to_vmx(vcpu);
3895         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3896
3897         vmx_segment_cache_clear(vmx);
3898
3899         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3900                 vmx->rmode.segs[seg] = *var;
3901                 if (seg == VCPU_SREG_TR)
3902                         vmcs_write16(sf->selector, var->selector);
3903                 else if (var->s)
3904                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3905                 goto out;
3906         }
3907
3908         vmcs_writel(sf->base, var->base);
3909         vmcs_write32(sf->limit, var->limit);
3910         vmcs_write16(sf->selector, var->selector);
3911
3912         /*
3913          *   Fix the "Accessed" bit in AR field of segment registers for older
3914          * qemu binaries.
3915          *   IA32 arch specifies that at the time of processor reset the
3916          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3917          * is setting it to 0 in the userland code. This causes invalid guest
3918          * state vmexit when "unrestricted guest" mode is turned on.
3919          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3920          * tree. Newer qemu binaries with that qemu fix would not need this
3921          * kvm hack.
3922          */
3923         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3924                 var->type |= 0x1; /* Accessed */
3925
3926         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3927
3928 out:
3929         vmx->emulation_required = emulation_required(vcpu);
3930 }
3931
3932 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3933 {
3934         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3935
3936         *db = (ar >> 14) & 1;
3937         *l = (ar >> 13) & 1;
3938 }
3939
3940 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3941 {
3942         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3943         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3944 }
3945
3946 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3947 {
3948         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3949         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3950 }
3951
3952 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3953 {
3954         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3955         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3956 }
3957
3958 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3959 {
3960         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3961         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3962 }
3963
3964 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3965 {
3966         struct kvm_segment var;
3967         u32 ar;
3968
3969         vmx_get_segment(vcpu, &var, seg);
3970         var.dpl = 0x3;
3971         if (seg == VCPU_SREG_CS)
3972                 var.type = 0x3;
3973         ar = vmx_segment_access_rights(&var);
3974
3975         if (var.base != (var.selector << 4))
3976                 return false;
3977         if (var.limit != 0xffff)
3978                 return false;
3979         if (ar != 0xf3)
3980                 return false;
3981
3982         return true;
3983 }
3984
3985 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3986 {
3987         struct kvm_segment cs;
3988         unsigned int cs_rpl;
3989
3990         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3991         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3992
3993         if (cs.unusable)
3994                 return false;
3995         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3996                 return false;
3997         if (!cs.s)
3998                 return false;
3999         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4000                 if (cs.dpl > cs_rpl)
4001                         return false;
4002         } else {
4003                 if (cs.dpl != cs_rpl)
4004                         return false;
4005         }
4006         if (!cs.present)
4007                 return false;
4008
4009         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4010         return true;
4011 }
4012
4013 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4014 {
4015         struct kvm_segment ss;
4016         unsigned int ss_rpl;
4017
4018         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4019         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4020
4021         if (ss.unusable)
4022                 return true;
4023         if (ss.type != 3 && ss.type != 7)
4024                 return false;
4025         if (!ss.s)
4026                 return false;
4027         if (ss.dpl != ss_rpl) /* DPL != RPL */
4028                 return false;
4029         if (!ss.present)
4030                 return false;
4031
4032         return true;
4033 }
4034
4035 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4036 {
4037         struct kvm_segment var;
4038         unsigned int rpl;
4039
4040         vmx_get_segment(vcpu, &var, seg);
4041         rpl = var.selector & SEGMENT_RPL_MASK;
4042
4043         if (var.unusable)
4044                 return true;
4045         if (!var.s)
4046                 return false;
4047         if (!var.present)
4048                 return false;
4049         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4050                 if (var.dpl < rpl) /* DPL < RPL */
4051                         return false;
4052         }
4053
4054         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4055          * rights flags
4056          */
4057         return true;
4058 }
4059
4060 static bool tr_valid(struct kvm_vcpu *vcpu)
4061 {
4062         struct kvm_segment tr;
4063
4064         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4065
4066         if (tr.unusable)
4067                 return false;
4068         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4069                 return false;
4070         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4071                 return false;
4072         if (!tr.present)
4073                 return false;
4074
4075         return true;
4076 }
4077
4078 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4079 {
4080         struct kvm_segment ldtr;
4081
4082         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4083
4084         if (ldtr.unusable)
4085                 return true;
4086         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4087                 return false;
4088         if (ldtr.type != 2)
4089                 return false;
4090         if (!ldtr.present)
4091                 return false;
4092
4093         return true;
4094 }
4095
4096 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4097 {
4098         struct kvm_segment cs, ss;
4099
4100         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4101         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4102
4103         return ((cs.selector & SEGMENT_RPL_MASK) ==
4104                  (ss.selector & SEGMENT_RPL_MASK));
4105 }
4106
4107 /*
4108  * Check if guest state is valid. Returns true if valid, false if
4109  * not.
4110  * We assume that registers are always usable
4111  */
4112 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4113 {
4114         if (enable_unrestricted_guest)
4115                 return true;
4116
4117         /* real mode guest state checks */
4118         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4119                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4120                         return false;
4121                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4122                         return false;
4123                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4124                         return false;
4125                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4126                         return false;
4127                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4128                         return false;
4129                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4130                         return false;
4131         } else {
4132         /* protected mode guest state checks */
4133                 if (!cs_ss_rpl_check(vcpu))
4134                         return false;
4135                 if (!code_segment_valid(vcpu))
4136                         return false;
4137                 if (!stack_segment_valid(vcpu))
4138                         return false;
4139                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4140                         return false;
4141                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4142                         return false;
4143                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4144                         return false;
4145                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4146                         return false;
4147                 if (!tr_valid(vcpu))
4148                         return false;
4149                 if (!ldtr_valid(vcpu))
4150                         return false;
4151         }
4152         /* TODO:
4153          * - Add checks on RIP
4154          * - Add checks on RFLAGS
4155          */
4156
4157         return true;
4158 }
4159
4160 static int init_rmode_tss(struct kvm *kvm)
4161 {
4162         gfn_t fn;
4163         u16 data = 0;
4164         int idx, r;
4165
4166         idx = srcu_read_lock(&kvm->srcu);
4167         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4168         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4169         if (r < 0)
4170                 goto out;
4171         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4172         r = kvm_write_guest_page(kvm, fn++, &data,
4173                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4174         if (r < 0)
4175                 goto out;
4176         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4177         if (r < 0)
4178                 goto out;
4179         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4180         if (r < 0)
4181                 goto out;
4182         data = ~0;
4183         r = kvm_write_guest_page(kvm, fn, &data,
4184                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4185                                  sizeof(u8));
4186 out:
4187         srcu_read_unlock(&kvm->srcu, idx);
4188         return r;
4189 }
4190
4191 static int init_rmode_identity_map(struct kvm *kvm)
4192 {
4193         int i, idx, r = 0;
4194         pfn_t identity_map_pfn;
4195         u32 tmp;
4196
4197         if (!enable_ept)
4198                 return 0;
4199
4200         /* Protect kvm->arch.ept_identity_pagetable_done. */
4201         mutex_lock(&kvm->slots_lock);
4202
4203         if (likely(kvm->arch.ept_identity_pagetable_done))
4204                 goto out2;
4205
4206         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4207
4208         r = alloc_identity_pagetable(kvm);
4209         if (r < 0)
4210                 goto out2;
4211
4212         idx = srcu_read_lock(&kvm->srcu);
4213         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4214         if (r < 0)
4215                 goto out;
4216         /* Set up identity-mapping pagetable for EPT in real mode */
4217         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4218                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4219                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4220                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4221                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4222                 if (r < 0)
4223                         goto out;
4224         }
4225         kvm->arch.ept_identity_pagetable_done = true;
4226
4227 out:
4228         srcu_read_unlock(&kvm->srcu, idx);
4229
4230 out2:
4231         mutex_unlock(&kvm->slots_lock);
4232         return r;
4233 }
4234
4235 static void seg_setup(int seg)
4236 {
4237         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4238         unsigned int ar;
4239
4240         vmcs_write16(sf->selector, 0);
4241         vmcs_writel(sf->base, 0);
4242         vmcs_write32(sf->limit, 0xffff);
4243         ar = 0x93;
4244         if (seg == VCPU_SREG_CS)
4245                 ar |= 0x08; /* code segment */
4246
4247         vmcs_write32(sf->ar_bytes, ar);
4248 }
4249
4250 static int alloc_apic_access_page(struct kvm *kvm)
4251 {
4252         struct page *page;
4253         int r = 0;
4254
4255         mutex_lock(&kvm->slots_lock);
4256         if (kvm->arch.apic_access_page_done)
4257                 goto out;
4258         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4259                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4260         if (r)
4261                 goto out;
4262
4263         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4264         if (is_error_page(page)) {
4265                 r = -EFAULT;
4266                 goto out;
4267         }
4268
4269         /*
4270          * Do not pin the page in memory, so that memory hot-unplug
4271          * is able to migrate it.
4272          */
4273         put_page(page);
4274         kvm->arch.apic_access_page_done = true;
4275 out:
4276         mutex_unlock(&kvm->slots_lock);
4277         return r;
4278 }
4279
4280 static int alloc_identity_pagetable(struct kvm *kvm)
4281 {
4282         /* Called with kvm->slots_lock held. */
4283
4284         int r = 0;
4285
4286         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4287
4288         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4289                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4290
4291         return r;
4292 }
4293
4294 static int allocate_vpid(void)
4295 {
4296         int vpid;
4297
4298         if (!enable_vpid)
4299                 return 0;
4300         spin_lock(&vmx_vpid_lock);
4301         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4302         if (vpid < VMX_NR_VPIDS)
4303                 __set_bit(vpid, vmx_vpid_bitmap);
4304         else
4305                 vpid = 0;
4306         spin_unlock(&vmx_vpid_lock);
4307         return vpid;
4308 }
4309
4310 static void free_vpid(int vpid)
4311 {
4312         if (!enable_vpid || vpid == 0)
4313                 return;
4314         spin_lock(&vmx_vpid_lock);
4315         __clear_bit(vpid, vmx_vpid_bitmap);
4316         spin_unlock(&vmx_vpid_lock);
4317 }
4318
4319 #define MSR_TYPE_R      1
4320 #define MSR_TYPE_W      2
4321 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4322                                                 u32 msr, int type)
4323 {
4324         int f = sizeof(unsigned long);
4325
4326         if (!cpu_has_vmx_msr_bitmap())
4327                 return;
4328
4329         /*
4330          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4331          * have the write-low and read-high bitmap offsets the wrong way round.
4332          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4333          */
4334         if (msr <= 0x1fff) {
4335                 if (type & MSR_TYPE_R)
4336                         /* read-low */
4337                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4338
4339                 if (type & MSR_TYPE_W)
4340                         /* write-low */
4341                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4342
4343         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4344                 msr &= 0x1fff;
4345                 if (type & MSR_TYPE_R)
4346                         /* read-high */
4347                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4348
4349                 if (type & MSR_TYPE_W)
4350                         /* write-high */
4351                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4352
4353         }
4354 }
4355
4356 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4357                                                 u32 msr, int type)
4358 {
4359         int f = sizeof(unsigned long);
4360
4361         if (!cpu_has_vmx_msr_bitmap())
4362                 return;
4363
4364         /*
4365          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4366          * have the write-low and read-high bitmap offsets the wrong way round.
4367          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4368          */
4369         if (msr <= 0x1fff) {
4370                 if (type & MSR_TYPE_R)
4371                         /* read-low */
4372                         __set_bit(msr, msr_bitmap + 0x000 / f);
4373
4374                 if (type & MSR_TYPE_W)
4375                         /* write-low */
4376                         __set_bit(msr, msr_bitmap + 0x800 / f);
4377
4378         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4379                 msr &= 0x1fff;
4380                 if (type & MSR_TYPE_R)
4381                         /* read-high */
4382                         __set_bit(msr, msr_bitmap + 0x400 / f);
4383
4384                 if (type & MSR_TYPE_W)
4385                         /* write-high */
4386                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4387
4388         }
4389 }
4390
4391 /*
4392  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4393  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4394  */
4395 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4396                                                unsigned long *msr_bitmap_nested,
4397                                                u32 msr, int type)
4398 {
4399         int f = sizeof(unsigned long);
4400
4401         if (!cpu_has_vmx_msr_bitmap()) {
4402                 WARN_ON(1);
4403                 return;
4404         }
4405
4406         /*
4407          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4408          * have the write-low and read-high bitmap offsets the wrong way round.
4409          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4410          */
4411         if (msr <= 0x1fff) {
4412                 if (type & MSR_TYPE_R &&
4413                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4414                         /* read-low */
4415                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4416
4417                 if (type & MSR_TYPE_W &&
4418                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4419                         /* write-low */
4420                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4421
4422         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4423                 msr &= 0x1fff;
4424                 if (type & MSR_TYPE_R &&
4425                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4426                         /* read-high */
4427                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4428
4429                 if (type & MSR_TYPE_W &&
4430                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4431                         /* write-high */
4432                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4433
4434         }
4435 }
4436
4437 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4438 {
4439         if (!longmode_only)
4440                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4441                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4442         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4443                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4444 }
4445
4446 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4447 {
4448         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4449                         msr, MSR_TYPE_R);
4450         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4451                         msr, MSR_TYPE_R);
4452 }
4453
4454 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4455 {
4456         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4457                         msr, MSR_TYPE_R);
4458         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4459                         msr, MSR_TYPE_R);
4460 }
4461
4462 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4463 {
4464         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4465                         msr, MSR_TYPE_W);
4466         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4467                         msr, MSR_TYPE_W);
4468 }
4469
4470 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4471 {
4472         return enable_apicv && lapic_in_kernel(vcpu);
4473 }
4474
4475 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4476 {
4477         struct vcpu_vmx *vmx = to_vmx(vcpu);
4478         int max_irr;
4479         void *vapic_page;
4480         u16 status;
4481
4482         if (vmx->nested.pi_desc &&
4483             vmx->nested.pi_pending) {
4484                 vmx->nested.pi_pending = false;
4485                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4486                         return 0;
4487
4488                 max_irr = find_last_bit(
4489                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4490
4491                 if (max_irr == 256)
4492                         return 0;
4493
4494                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4495                 if (!vapic_page) {
4496                         WARN_ON(1);
4497                         return -ENOMEM;
4498                 }
4499                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4500                 kunmap(vmx->nested.virtual_apic_page);
4501
4502                 status = vmcs_read16(GUEST_INTR_STATUS);
4503                 if ((u8)max_irr > ((u8)status & 0xff)) {
4504                         status &= ~0xff;
4505                         status |= (u8)max_irr;
4506                         vmcs_write16(GUEST_INTR_STATUS, status);
4507                 }
4508         }
4509         return 0;
4510 }
4511
4512 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4513 {
4514 #ifdef CONFIG_SMP
4515         if (vcpu->mode == IN_GUEST_MODE) {
4516                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4517
4518                 /*
4519                  * Currently, we don't support urgent interrupt,
4520                  * all interrupts are recognized as non-urgent
4521                  * interrupt, so we cannot post interrupts when
4522                  * 'SN' is set.
4523                  *
4524                  * If the vcpu is in guest mode, it means it is
4525                  * running instead of being scheduled out and
4526                  * waiting in the run queue, and that's the only
4527                  * case when 'SN' is set currently, warning if
4528                  * 'SN' is set.
4529                  */
4530                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4531
4532                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4533                                 POSTED_INTR_VECTOR);
4534                 return true;
4535         }
4536 #endif
4537         return false;
4538 }
4539
4540 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4541                                                 int vector)
4542 {
4543         struct vcpu_vmx *vmx = to_vmx(vcpu);
4544
4545         if (is_guest_mode(vcpu) &&
4546             vector == vmx->nested.posted_intr_nv) {
4547                 /* the PIR and ON have been set by L1. */
4548                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4549                 /*
4550                  * If a posted intr is not recognized by hardware,
4551                  * we will accomplish it in the next vmentry.
4552                  */
4553                 vmx->nested.pi_pending = true;
4554                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4555                 return 0;
4556         }
4557         return -1;
4558 }
4559 /*
4560  * Send interrupt to vcpu via posted interrupt way.
4561  * 1. If target vcpu is running(non-root mode), send posted interrupt
4562  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4563  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4564  * interrupt from PIR in next vmentry.
4565  */
4566 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4567 {
4568         struct vcpu_vmx *vmx = to_vmx(vcpu);
4569         int r;
4570
4571         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4572         if (!r)
4573                 return;
4574
4575         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4576                 return;
4577
4578         r = pi_test_and_set_on(&vmx->pi_desc);
4579         kvm_make_request(KVM_REQ_EVENT, vcpu);
4580         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4581                 kvm_vcpu_kick(vcpu);
4582 }
4583
4584 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4585 {
4586         struct vcpu_vmx *vmx = to_vmx(vcpu);
4587
4588         if (!pi_test_and_clear_on(&vmx->pi_desc))
4589                 return;
4590
4591         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4592 }
4593
4594 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4595 {
4596         return;
4597 }
4598
4599 /*
4600  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4601  * will not change in the lifetime of the guest.
4602  * Note that host-state that does change is set elsewhere. E.g., host-state
4603  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4604  */
4605 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4606 {
4607         u32 low32, high32;
4608         unsigned long tmpl;
4609         struct desc_ptr dt;
4610         unsigned long cr4;
4611
4612         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4613         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4614
4615         /* Save the most likely value for this task's CR4 in the VMCS. */
4616         cr4 = cr4_read_shadow();
4617         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4618         vmx->host_state.vmcs_host_cr4 = cr4;
4619
4620         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4621 #ifdef CONFIG_X86_64
4622         /*
4623          * Load null selectors, so we can avoid reloading them in
4624          * __vmx_load_host_state(), in case userspace uses the null selectors
4625          * too (the expected case).
4626          */
4627         vmcs_write16(HOST_DS_SELECTOR, 0);
4628         vmcs_write16(HOST_ES_SELECTOR, 0);
4629 #else
4630         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4631         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4632 #endif
4633         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4634         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4635
4636         native_store_idt(&dt);
4637         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4638         vmx->host_idt_base = dt.address;
4639
4640         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4641
4642         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4643         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4644         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4645         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4646
4647         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4648                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4649                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4650         }
4651 }
4652
4653 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4654 {
4655         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4656         if (enable_ept)
4657                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4658         if (is_guest_mode(&vmx->vcpu))
4659                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4660                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4661         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4662 }
4663
4664 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4665 {
4666         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4667
4668         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4669                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4670         return pin_based_exec_ctrl;
4671 }
4672
4673 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4674 {
4675         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4676
4677         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4678                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4679
4680         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4681                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4682 #ifdef CONFIG_X86_64
4683                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4684                                 CPU_BASED_CR8_LOAD_EXITING;
4685 #endif
4686         }
4687         if (!enable_ept)
4688                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4689                                 CPU_BASED_CR3_LOAD_EXITING  |
4690                                 CPU_BASED_INVLPG_EXITING;
4691         return exec_control;
4692 }
4693
4694 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4695 {
4696         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4697         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4698                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4699         if (vmx->vpid == 0)
4700                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4701         if (!enable_ept) {
4702                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4703                 enable_unrestricted_guest = 0;
4704                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4705                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4706         }
4707         if (!enable_unrestricted_guest)
4708                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4709         if (!ple_gap)
4710                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4711         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4712                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4713                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4714         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4715         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4716            (handle_vmptrld).
4717            We can NOT enable shadow_vmcs here because we don't have yet
4718            a current VMCS12
4719         */
4720         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4721
4722         if (!enable_pml)
4723                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4724
4725         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4726         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4727
4728         return exec_control;
4729 }
4730
4731 static void ept_set_mmio_spte_mask(void)
4732 {
4733         /*
4734          * EPT Misconfigurations can be generated if the value of bits 2:0
4735          * of an EPT paging-structure entry is 110b (write/execute).
4736          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4737          * spte.
4738          */
4739         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4740 }
4741
4742 #define VMX_XSS_EXIT_BITMAP 0
4743 /*
4744  * Sets up the vmcs for emulated real mode.
4745  */
4746 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4747 {
4748 #ifdef CONFIG_X86_64
4749         unsigned long a;
4750 #endif
4751         int i;
4752
4753         /* I/O */
4754         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4755         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4756
4757         if (enable_shadow_vmcs) {
4758                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4759                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4760         }
4761         if (cpu_has_vmx_msr_bitmap())
4762                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4763
4764         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4765
4766         /* Control */
4767         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4768
4769         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4770
4771         if (cpu_has_secondary_exec_ctrls())
4772                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4773                                 vmx_secondary_exec_control(vmx));
4774
4775         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4776                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4777                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4778                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4779                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4780
4781                 vmcs_write16(GUEST_INTR_STATUS, 0);
4782
4783                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4784                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4785         }
4786
4787         if (ple_gap) {
4788                 vmcs_write32(PLE_GAP, ple_gap);
4789                 vmx->ple_window = ple_window;
4790                 vmx->ple_window_dirty = true;
4791         }
4792
4793         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4794         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4795         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4796
4797         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4798         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4799         vmx_set_constant_host_state(vmx);
4800 #ifdef CONFIG_X86_64
4801         rdmsrl(MSR_FS_BASE, a);
4802         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4803         rdmsrl(MSR_GS_BASE, a);
4804         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4805 #else
4806         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4807         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4808 #endif
4809
4810         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4811         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4812         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4813         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4814         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4815
4816         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4817                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4818
4819         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4820                 u32 index = vmx_msr_index[i];
4821                 u32 data_low, data_high;
4822                 int j = vmx->nmsrs;
4823
4824                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4825                         continue;
4826                 if (wrmsr_safe(index, data_low, data_high) < 0)
4827                         continue;
4828                 vmx->guest_msrs[j].index = i;
4829                 vmx->guest_msrs[j].data = 0;
4830                 vmx->guest_msrs[j].mask = -1ull;
4831                 ++vmx->nmsrs;
4832         }
4833
4834
4835         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4836
4837         /* 22.2.1, 20.8.1 */
4838         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4839
4840         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4841         set_cr4_guest_host_mask(vmx);
4842
4843         if (vmx_xsaves_supported())
4844                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4845
4846         return 0;
4847 }
4848
4849 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4850 {
4851         struct vcpu_vmx *vmx = to_vmx(vcpu);
4852         struct msr_data apic_base_msr;
4853         u64 cr0;
4854
4855         vmx->rmode.vm86_active = 0;
4856
4857         vmx->soft_vnmi_blocked = 0;
4858
4859         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4860         kvm_set_cr8(vcpu, 0);
4861
4862         if (!init_event) {
4863                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4864                                      MSR_IA32_APICBASE_ENABLE;
4865                 if (kvm_vcpu_is_reset_bsp(vcpu))
4866                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4867                 apic_base_msr.host_initiated = true;
4868                 kvm_set_apic_base(vcpu, &apic_base_msr);
4869         }
4870
4871         vmx_segment_cache_clear(vmx);
4872
4873         seg_setup(VCPU_SREG_CS);
4874         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4875         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4876
4877         seg_setup(VCPU_SREG_DS);
4878         seg_setup(VCPU_SREG_ES);
4879         seg_setup(VCPU_SREG_FS);
4880         seg_setup(VCPU_SREG_GS);
4881         seg_setup(VCPU_SREG_SS);
4882
4883         vmcs_write16(GUEST_TR_SELECTOR, 0);
4884         vmcs_writel(GUEST_TR_BASE, 0);
4885         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4886         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4887
4888         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4889         vmcs_writel(GUEST_LDTR_BASE, 0);
4890         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4891         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4892
4893         if (!init_event) {
4894                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4895                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4896                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4897                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4898         }
4899
4900         vmcs_writel(GUEST_RFLAGS, 0x02);
4901         kvm_rip_write(vcpu, 0xfff0);
4902
4903         vmcs_writel(GUEST_GDTR_BASE, 0);
4904         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4905
4906         vmcs_writel(GUEST_IDTR_BASE, 0);
4907         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4908
4909         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4910         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4911         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4912
4913         setup_msrs(vmx);
4914
4915         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4916
4917         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4918                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4919                 if (cpu_need_tpr_shadow(vcpu))
4920                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4921                                      __pa(vcpu->arch.apic->regs));
4922                 vmcs_write32(TPR_THRESHOLD, 0);
4923         }
4924
4925         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4926
4927         if (vmx_cpu_uses_apicv(vcpu))
4928                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4929
4930         if (vmx->vpid != 0)
4931                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4932
4933         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4934         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4935         vmx->vcpu.arch.cr0 = cr0;
4936         vmx_set_cr4(vcpu, 0);
4937         vmx_set_efer(vcpu, 0);
4938         vmx_fpu_activate(vcpu);
4939         update_exception_bitmap(vcpu);
4940
4941         vpid_sync_context(vmx->vpid);
4942 }
4943
4944 /*
4945  * In nested virtualization, check if L1 asked to exit on external interrupts.
4946  * For most existing hypervisors, this will always return true.
4947  */
4948 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4949 {
4950         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4951                 PIN_BASED_EXT_INTR_MASK;
4952 }
4953
4954 /*
4955  * In nested virtualization, check if L1 has set
4956  * VM_EXIT_ACK_INTR_ON_EXIT
4957  */
4958 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4959 {
4960         return get_vmcs12(vcpu)->vm_exit_controls &
4961                 VM_EXIT_ACK_INTR_ON_EXIT;
4962 }
4963
4964 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4965 {
4966         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4967                 PIN_BASED_NMI_EXITING;
4968 }
4969
4970 static void enable_irq_window(struct kvm_vcpu *vcpu)
4971 {
4972         u32 cpu_based_vm_exec_control;
4973
4974         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4975         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4976         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4977 }
4978
4979 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4980 {
4981         u32 cpu_based_vm_exec_control;
4982
4983         if (!cpu_has_virtual_nmis() ||
4984             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4985                 enable_irq_window(vcpu);
4986                 return;
4987         }
4988
4989         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4990         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4991         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4992 }
4993
4994 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4995 {
4996         struct vcpu_vmx *vmx = to_vmx(vcpu);
4997         uint32_t intr;
4998         int irq = vcpu->arch.interrupt.nr;
4999
5000         trace_kvm_inj_virq(irq);
5001
5002         ++vcpu->stat.irq_injections;
5003         if (vmx->rmode.vm86_active) {
5004                 int inc_eip = 0;
5005                 if (vcpu->arch.interrupt.soft)
5006                         inc_eip = vcpu->arch.event_exit_inst_len;
5007                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5008                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5009                 return;
5010         }
5011         intr = irq | INTR_INFO_VALID_MASK;
5012         if (vcpu->arch.interrupt.soft) {
5013                 intr |= INTR_TYPE_SOFT_INTR;
5014                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5015                              vmx->vcpu.arch.event_exit_inst_len);
5016         } else
5017                 intr |= INTR_TYPE_EXT_INTR;
5018         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5019 }
5020
5021 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5022 {
5023         struct vcpu_vmx *vmx = to_vmx(vcpu);
5024
5025         if (is_guest_mode(vcpu))
5026                 return;
5027
5028         if (!cpu_has_virtual_nmis()) {
5029                 /*
5030                  * Tracking the NMI-blocked state in software is built upon
5031                  * finding the next open IRQ window. This, in turn, depends on
5032                  * well-behaving guests: They have to keep IRQs disabled at
5033                  * least as long as the NMI handler runs. Otherwise we may
5034                  * cause NMI nesting, maybe breaking the guest. But as this is
5035                  * highly unlikely, we can live with the residual risk.
5036                  */
5037                 vmx->soft_vnmi_blocked = 1;
5038                 vmx->vnmi_blocked_time = 0;
5039         }
5040
5041         ++vcpu->stat.nmi_injections;
5042         vmx->nmi_known_unmasked = false;
5043         if (vmx->rmode.vm86_active) {
5044                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5045                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5046                 return;
5047         }
5048         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5049                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5050 }
5051
5052 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5053 {
5054         if (!cpu_has_virtual_nmis())
5055                 return to_vmx(vcpu)->soft_vnmi_blocked;
5056         if (to_vmx(vcpu)->nmi_known_unmasked)
5057                 return false;
5058         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5059 }
5060
5061 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5062 {
5063         struct vcpu_vmx *vmx = to_vmx(vcpu);
5064
5065         if (!cpu_has_virtual_nmis()) {
5066                 if (vmx->soft_vnmi_blocked != masked) {
5067                         vmx->soft_vnmi_blocked = masked;
5068                         vmx->vnmi_blocked_time = 0;
5069                 }
5070         } else {
5071                 vmx->nmi_known_unmasked = !masked;
5072                 if (masked)
5073                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5074                                       GUEST_INTR_STATE_NMI);
5075                 else
5076                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5077                                         GUEST_INTR_STATE_NMI);
5078         }
5079 }
5080
5081 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5082 {
5083         if (to_vmx(vcpu)->nested.nested_run_pending)
5084                 return 0;
5085
5086         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5087                 return 0;
5088
5089         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5090                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5091                    | GUEST_INTR_STATE_NMI));
5092 }
5093
5094 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5095 {
5096         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5097                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5098                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5099                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5100 }
5101
5102 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5103 {
5104         int ret;
5105
5106         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5107                                     PAGE_SIZE * 3);
5108         if (ret)
5109                 return ret;
5110         kvm->arch.tss_addr = addr;
5111         return init_rmode_tss(kvm);
5112 }
5113
5114 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5115 {
5116         switch (vec) {
5117         case BP_VECTOR:
5118                 /*
5119                  * Update instruction length as we may reinject the exception
5120                  * from user space while in guest debugging mode.
5121                  */
5122                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5123                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5124                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5125                         return false;
5126                 /* fall through */
5127         case DB_VECTOR:
5128                 if (vcpu->guest_debug &
5129                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5130                         return false;
5131                 /* fall through */
5132         case DE_VECTOR:
5133         case OF_VECTOR:
5134         case BR_VECTOR:
5135         case UD_VECTOR:
5136         case DF_VECTOR:
5137         case SS_VECTOR:
5138         case GP_VECTOR:
5139         case MF_VECTOR:
5140                 return true;
5141         break;
5142         }
5143         return false;
5144 }
5145
5146 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5147                                   int vec, u32 err_code)
5148 {
5149         /*
5150          * Instruction with address size override prefix opcode 0x67
5151          * Cause the #SS fault with 0 error code in VM86 mode.
5152          */
5153         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5154                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5155                         if (vcpu->arch.halt_request) {
5156                                 vcpu->arch.halt_request = 0;
5157                                 return kvm_vcpu_halt(vcpu);
5158                         }
5159                         return 1;
5160                 }
5161                 return 0;
5162         }
5163
5164         /*
5165          * Forward all other exceptions that are valid in real mode.
5166          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5167          *        the required debugging infrastructure rework.
5168          */
5169         kvm_queue_exception(vcpu, vec);
5170         return 1;
5171 }
5172
5173 /*
5174  * Trigger machine check on the host. We assume all the MSRs are already set up
5175  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5176  * We pass a fake environment to the machine check handler because we want
5177  * the guest to be always treated like user space, no matter what context
5178  * it used internally.
5179  */
5180 static void kvm_machine_check(void)
5181 {
5182 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5183         struct pt_regs regs = {
5184                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5185                 .flags = X86_EFLAGS_IF,
5186         };
5187
5188         do_machine_check(&regs, 0);
5189 #endif
5190 }
5191
5192 static int handle_machine_check(struct kvm_vcpu *vcpu)
5193 {
5194         /* already handled by vcpu_run */
5195         return 1;
5196 }
5197
5198 static int handle_exception(struct kvm_vcpu *vcpu)
5199 {
5200         struct vcpu_vmx *vmx = to_vmx(vcpu);
5201         struct kvm_run *kvm_run = vcpu->run;
5202         u32 intr_info, ex_no, error_code;
5203         unsigned long cr2, rip, dr6;
5204         u32 vect_info;
5205         enum emulation_result er;
5206
5207         vect_info = vmx->idt_vectoring_info;
5208         intr_info = vmx->exit_intr_info;
5209
5210         if (is_machine_check(intr_info))
5211                 return handle_machine_check(vcpu);
5212
5213         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5214                 return 1;  /* already handled by vmx_vcpu_run() */
5215
5216         if (is_no_device(intr_info)) {
5217                 vmx_fpu_activate(vcpu);
5218                 return 1;
5219         }
5220
5221         if (is_invalid_opcode(intr_info)) {
5222                 if (is_guest_mode(vcpu)) {
5223                         kvm_queue_exception(vcpu, UD_VECTOR);
5224                         return 1;
5225                 }
5226                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5227                 if (er != EMULATE_DONE)
5228                         kvm_queue_exception(vcpu, UD_VECTOR);
5229                 return 1;
5230         }
5231
5232         error_code = 0;
5233         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5234                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5235
5236         /*
5237          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5238          * MMIO, it is better to report an internal error.
5239          * See the comments in vmx_handle_exit.
5240          */
5241         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5242             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5243                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5244                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5245                 vcpu->run->internal.ndata = 3;
5246                 vcpu->run->internal.data[0] = vect_info;
5247                 vcpu->run->internal.data[1] = intr_info;
5248                 vcpu->run->internal.data[2] = error_code;
5249                 return 0;
5250         }
5251
5252         if (is_page_fault(intr_info)) {
5253                 /* EPT won't cause page fault directly */
5254                 BUG_ON(enable_ept);
5255                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5256                 trace_kvm_page_fault(cr2, error_code);
5257
5258                 if (kvm_event_needs_reinjection(vcpu))
5259                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5260                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5261         }
5262
5263         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5264
5265         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5266                 return handle_rmode_exception(vcpu, ex_no, error_code);
5267
5268         switch (ex_no) {
5269         case DB_VECTOR:
5270                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5271                 if (!(vcpu->guest_debug &
5272                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5273                         vcpu->arch.dr6 &= ~15;
5274                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5275                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5276                                 skip_emulated_instruction(vcpu);
5277
5278                         kvm_queue_exception(vcpu, DB_VECTOR);
5279                         return 1;
5280                 }
5281                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5282                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5283                 /* fall through */
5284         case BP_VECTOR:
5285                 /*
5286                  * Update instruction length as we may reinject #BP from
5287                  * user space while in guest debugging mode. Reading it for
5288                  * #DB as well causes no harm, it is not used in that case.
5289                  */
5290                 vmx->vcpu.arch.event_exit_inst_len =
5291                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5292                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5293                 rip = kvm_rip_read(vcpu);
5294                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5295                 kvm_run->debug.arch.exception = ex_no;
5296                 break;
5297         default:
5298                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5299                 kvm_run->ex.exception = ex_no;
5300                 kvm_run->ex.error_code = error_code;
5301                 break;
5302         }
5303         return 0;
5304 }
5305
5306 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5307 {
5308         ++vcpu->stat.irq_exits;
5309         return 1;
5310 }
5311
5312 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5313 {
5314         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5315         return 0;
5316 }
5317
5318 static int handle_io(struct kvm_vcpu *vcpu)
5319 {
5320         unsigned long exit_qualification;
5321         int size, in, string;
5322         unsigned port;
5323
5324         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5325         string = (exit_qualification & 16) != 0;
5326         in = (exit_qualification & 8) != 0;
5327
5328         ++vcpu->stat.io_exits;
5329
5330         if (string || in)
5331                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5332
5333         port = exit_qualification >> 16;
5334         size = (exit_qualification & 7) + 1;
5335         skip_emulated_instruction(vcpu);
5336
5337         return kvm_fast_pio_out(vcpu, size, port);
5338 }
5339
5340 static void
5341 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5342 {
5343         /*
5344          * Patch in the VMCALL instruction:
5345          */
5346         hypercall[0] = 0x0f;
5347         hypercall[1] = 0x01;
5348         hypercall[2] = 0xc1;
5349 }
5350
5351 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5352 {
5353         unsigned long always_on = VMXON_CR0_ALWAYSON;
5354         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5355
5356         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5357                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5358             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5359                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5360         return (val & always_on) == always_on;
5361 }
5362
5363 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5364 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5365 {
5366         if (is_guest_mode(vcpu)) {
5367                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5368                 unsigned long orig_val = val;
5369
5370                 /*
5371                  * We get here when L2 changed cr0 in a way that did not change
5372                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5373                  * but did change L0 shadowed bits. So we first calculate the
5374                  * effective cr0 value that L1 would like to write into the
5375                  * hardware. It consists of the L2-owned bits from the new
5376                  * value combined with the L1-owned bits from L1's guest_cr0.
5377                  */
5378                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5379                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5380
5381                 if (!nested_cr0_valid(vcpu, val))
5382                         return 1;
5383
5384                 if (kvm_set_cr0(vcpu, val))
5385                         return 1;
5386                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5387                 return 0;
5388         } else {
5389                 if (to_vmx(vcpu)->nested.vmxon &&
5390                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5391                         return 1;
5392                 return kvm_set_cr0(vcpu, val);
5393         }
5394 }
5395
5396 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5397 {
5398         if (is_guest_mode(vcpu)) {
5399                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5400                 unsigned long orig_val = val;
5401
5402                 /* analogously to handle_set_cr0 */
5403                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5404                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5405                 if (kvm_set_cr4(vcpu, val))
5406                         return 1;
5407                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5408                 return 0;
5409         } else
5410                 return kvm_set_cr4(vcpu, val);
5411 }
5412
5413 /* called to set cr0 as approriate for clts instruction exit. */
5414 static void handle_clts(struct kvm_vcpu *vcpu)
5415 {
5416         if (is_guest_mode(vcpu)) {
5417                 /*
5418                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5419                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5420                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5421                  */
5422                 vmcs_writel(CR0_READ_SHADOW,
5423                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5424                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5425         } else
5426                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5427 }
5428
5429 static int handle_cr(struct kvm_vcpu *vcpu)
5430 {
5431         unsigned long exit_qualification, val;
5432         int cr;
5433         int reg;
5434         int err;
5435
5436         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5437         cr = exit_qualification & 15;
5438         reg = (exit_qualification >> 8) & 15;
5439         switch ((exit_qualification >> 4) & 3) {
5440         case 0: /* mov to cr */
5441                 val = kvm_register_readl(vcpu, reg);
5442                 trace_kvm_cr_write(cr, val);
5443                 switch (cr) {
5444                 case 0:
5445                         err = handle_set_cr0(vcpu, val);
5446                         kvm_complete_insn_gp(vcpu, err);
5447                         return 1;
5448                 case 3:
5449                         err = kvm_set_cr3(vcpu, val);
5450                         kvm_complete_insn_gp(vcpu, err);
5451                         return 1;
5452                 case 4:
5453                         err = handle_set_cr4(vcpu, val);
5454                         kvm_complete_insn_gp(vcpu, err);
5455                         return 1;
5456                 case 8: {
5457                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5458                                 u8 cr8 = (u8)val;
5459                                 err = kvm_set_cr8(vcpu, cr8);
5460                                 kvm_complete_insn_gp(vcpu, err);
5461                                 if (lapic_in_kernel(vcpu))
5462                                         return 1;
5463                                 if (cr8_prev <= cr8)
5464                                         return 1;
5465                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5466                                 return 0;
5467                         }
5468                 }
5469                 break;
5470         case 2: /* clts */
5471                 handle_clts(vcpu);
5472                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5473                 skip_emulated_instruction(vcpu);
5474                 vmx_fpu_activate(vcpu);
5475                 return 1;
5476         case 1: /*mov from cr*/
5477                 switch (cr) {
5478                 case 3:
5479                         val = kvm_read_cr3(vcpu);
5480                         kvm_register_write(vcpu, reg, val);
5481                         trace_kvm_cr_read(cr, val);
5482                         skip_emulated_instruction(vcpu);
5483                         return 1;
5484                 case 8:
5485                         val = kvm_get_cr8(vcpu);
5486                         kvm_register_write(vcpu, reg, val);
5487                         trace_kvm_cr_read(cr, val);
5488                         skip_emulated_instruction(vcpu);
5489                         return 1;
5490                 }
5491                 break;
5492         case 3: /* lmsw */
5493                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5494                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5495                 kvm_lmsw(vcpu, val);
5496
5497                 skip_emulated_instruction(vcpu);
5498                 return 1;
5499         default:
5500                 break;
5501         }
5502         vcpu->run->exit_reason = 0;
5503         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5504                (int)(exit_qualification >> 4) & 3, cr);
5505         return 0;
5506 }
5507
5508 static int handle_dr(struct kvm_vcpu *vcpu)
5509 {
5510         unsigned long exit_qualification;
5511         int dr, dr7, reg;
5512
5513         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5514         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5515
5516         /* First, if DR does not exist, trigger UD */
5517         if (!kvm_require_dr(vcpu, dr))
5518                 return 1;
5519
5520         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5521         if (!kvm_require_cpl(vcpu, 0))
5522                 return 1;
5523         dr7 = vmcs_readl(GUEST_DR7);
5524         if (dr7 & DR7_GD) {
5525                 /*
5526                  * As the vm-exit takes precedence over the debug trap, we
5527                  * need to emulate the latter, either for the host or the
5528                  * guest debugging itself.
5529                  */
5530                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5531                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5532                         vcpu->run->debug.arch.dr7 = dr7;
5533                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5534                         vcpu->run->debug.arch.exception = DB_VECTOR;
5535                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5536                         return 0;
5537                 } else {
5538                         vcpu->arch.dr6 &= ~15;
5539                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5540                         kvm_queue_exception(vcpu, DB_VECTOR);
5541                         return 1;
5542                 }
5543         }
5544
5545         if (vcpu->guest_debug == 0) {
5546                 u32 cpu_based_vm_exec_control;
5547
5548                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5549                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5550                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5551
5552                 /*
5553                  * No more DR vmexits; force a reload of the debug registers
5554                  * and reenter on this instruction.  The next vmexit will
5555                  * retrieve the full state of the debug registers.
5556                  */
5557                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5558                 return 1;
5559         }
5560
5561         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5562         if (exit_qualification & TYPE_MOV_FROM_DR) {
5563                 unsigned long val;
5564
5565                 if (kvm_get_dr(vcpu, dr, &val))
5566                         return 1;
5567                 kvm_register_write(vcpu, reg, val);
5568         } else
5569                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5570                         return 1;
5571
5572         skip_emulated_instruction(vcpu);
5573         return 1;
5574 }
5575
5576 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5577 {
5578         return vcpu->arch.dr6;
5579 }
5580
5581 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5582 {
5583 }
5584
5585 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5586 {
5587         u32 cpu_based_vm_exec_control;
5588
5589         get_debugreg(vcpu->arch.db[0], 0);
5590         get_debugreg(vcpu->arch.db[1], 1);
5591         get_debugreg(vcpu->arch.db[2], 2);
5592         get_debugreg(vcpu->arch.db[3], 3);
5593         get_debugreg(vcpu->arch.dr6, 6);
5594         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5595
5596         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5597
5598         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5599         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5600         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5601 }
5602
5603 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5604 {
5605         vmcs_writel(GUEST_DR7, val);
5606 }
5607
5608 static int handle_cpuid(struct kvm_vcpu *vcpu)
5609 {
5610         kvm_emulate_cpuid(vcpu);
5611         return 1;
5612 }
5613
5614 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5615 {
5616         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5617         struct msr_data msr_info;
5618
5619         msr_info.index = ecx;
5620         msr_info.host_initiated = false;
5621         if (vmx_get_msr(vcpu, &msr_info)) {
5622                 trace_kvm_msr_read_ex(ecx);
5623                 kvm_inject_gp(vcpu, 0);
5624                 return 1;
5625         }
5626
5627         trace_kvm_msr_read(ecx, msr_info.data);
5628
5629         /* FIXME: handling of bits 32:63 of rax, rdx */
5630         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5631         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5632         skip_emulated_instruction(vcpu);
5633         return 1;
5634 }
5635
5636 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5637 {
5638         struct msr_data msr;
5639         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5640         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5641                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5642
5643         msr.data = data;
5644         msr.index = ecx;
5645         msr.host_initiated = false;
5646         if (kvm_set_msr(vcpu, &msr) != 0) {
5647                 trace_kvm_msr_write_ex(ecx, data);
5648                 kvm_inject_gp(vcpu, 0);
5649                 return 1;
5650         }
5651
5652         trace_kvm_msr_write(ecx, data);
5653         skip_emulated_instruction(vcpu);
5654         return 1;
5655 }
5656
5657 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5658 {
5659         kvm_make_request(KVM_REQ_EVENT, vcpu);
5660         return 1;
5661 }
5662
5663 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5664 {
5665         u32 cpu_based_vm_exec_control;
5666
5667         /* clear pending irq */
5668         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5669         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5670         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5671
5672         kvm_make_request(KVM_REQ_EVENT, vcpu);
5673
5674         ++vcpu->stat.irq_window_exits;
5675         return 1;
5676 }
5677
5678 static int handle_halt(struct kvm_vcpu *vcpu)
5679 {
5680         return kvm_emulate_halt(vcpu);
5681 }
5682
5683 static int handle_vmcall(struct kvm_vcpu *vcpu)
5684 {
5685         kvm_emulate_hypercall(vcpu);
5686         return 1;
5687 }
5688
5689 static int handle_invd(struct kvm_vcpu *vcpu)
5690 {
5691         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5692 }
5693
5694 static int handle_invlpg(struct kvm_vcpu *vcpu)
5695 {
5696         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5697
5698         kvm_mmu_invlpg(vcpu, exit_qualification);
5699         skip_emulated_instruction(vcpu);
5700         return 1;
5701 }
5702
5703 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5704 {
5705         int err;
5706
5707         err = kvm_rdpmc(vcpu);
5708         kvm_complete_insn_gp(vcpu, err);
5709
5710         return 1;
5711 }
5712
5713 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5714 {
5715         kvm_emulate_wbinvd(vcpu);
5716         return 1;
5717 }
5718
5719 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5720 {
5721         u64 new_bv = kvm_read_edx_eax(vcpu);
5722         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5723
5724         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5725                 skip_emulated_instruction(vcpu);
5726         return 1;
5727 }
5728
5729 static int handle_xsaves(struct kvm_vcpu *vcpu)
5730 {
5731         skip_emulated_instruction(vcpu);
5732         WARN(1, "this should never happen\n");
5733         return 1;
5734 }
5735
5736 static int handle_xrstors(struct kvm_vcpu *vcpu)
5737 {
5738         skip_emulated_instruction(vcpu);
5739         WARN(1, "this should never happen\n");
5740         return 1;
5741 }
5742
5743 static int handle_apic_access(struct kvm_vcpu *vcpu)
5744 {
5745         if (likely(fasteoi)) {
5746                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5747                 int access_type, offset;
5748
5749                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5750                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5751                 /*
5752                  * Sane guest uses MOV to write EOI, with written value
5753                  * not cared. So make a short-circuit here by avoiding
5754                  * heavy instruction emulation.
5755                  */
5756                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5757                     (offset == APIC_EOI)) {
5758                         kvm_lapic_set_eoi(vcpu);
5759                         skip_emulated_instruction(vcpu);
5760                         return 1;
5761                 }
5762         }
5763         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5764 }
5765
5766 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5767 {
5768         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5769         int vector = exit_qualification & 0xff;
5770
5771         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5772         kvm_apic_set_eoi_accelerated(vcpu, vector);
5773         return 1;
5774 }
5775
5776 static int handle_apic_write(struct kvm_vcpu *vcpu)
5777 {
5778         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5779         u32 offset = exit_qualification & 0xfff;
5780
5781         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5782         kvm_apic_write_nodecode(vcpu, offset);
5783         return 1;
5784 }
5785
5786 static int handle_task_switch(struct kvm_vcpu *vcpu)
5787 {
5788         struct vcpu_vmx *vmx = to_vmx(vcpu);
5789         unsigned long exit_qualification;
5790         bool has_error_code = false;
5791         u32 error_code = 0;
5792         u16 tss_selector;
5793         int reason, type, idt_v, idt_index;
5794
5795         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5796         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5797         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5798
5799         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5800
5801         reason = (u32)exit_qualification >> 30;
5802         if (reason == TASK_SWITCH_GATE && idt_v) {
5803                 switch (type) {
5804                 case INTR_TYPE_NMI_INTR:
5805                         vcpu->arch.nmi_injected = false;
5806                         vmx_set_nmi_mask(vcpu, true);
5807                         break;
5808                 case INTR_TYPE_EXT_INTR:
5809                 case INTR_TYPE_SOFT_INTR:
5810                         kvm_clear_interrupt_queue(vcpu);
5811                         break;
5812                 case INTR_TYPE_HARD_EXCEPTION:
5813                         if (vmx->idt_vectoring_info &
5814                             VECTORING_INFO_DELIVER_CODE_MASK) {
5815                                 has_error_code = true;
5816                                 error_code =
5817                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5818                         }
5819                         /* fall through */
5820                 case INTR_TYPE_SOFT_EXCEPTION:
5821                         kvm_clear_exception_queue(vcpu);
5822                         break;
5823                 default:
5824                         break;
5825                 }
5826         }
5827         tss_selector = exit_qualification;
5828
5829         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5830                        type != INTR_TYPE_EXT_INTR &&
5831                        type != INTR_TYPE_NMI_INTR))
5832                 skip_emulated_instruction(vcpu);
5833
5834         if (kvm_task_switch(vcpu, tss_selector,
5835                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5836                             has_error_code, error_code) == EMULATE_FAIL) {
5837                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5838                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5839                 vcpu->run->internal.ndata = 0;
5840                 return 0;
5841         }
5842
5843         /*
5844          * TODO: What about debug traps on tss switch?
5845          *       Are we supposed to inject them and update dr6?
5846          */
5847
5848         return 1;
5849 }
5850
5851 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5852 {
5853         unsigned long exit_qualification;
5854         gpa_t gpa;
5855         u32 error_code;
5856         int gla_validity;
5857
5858         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5859
5860         gla_validity = (exit_qualification >> 7) & 0x3;
5861         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5862                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5863                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5864                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5865                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5866                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5867                         (long unsigned int)exit_qualification);
5868                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5869                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5870                 return 0;
5871         }
5872
5873         /*
5874          * EPT violation happened while executing iret from NMI,
5875          * "blocked by NMI" bit has to be set before next VM entry.
5876          * There are errata that may cause this bit to not be set:
5877          * AAK134, BY25.
5878          */
5879         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5880                         cpu_has_virtual_nmis() &&
5881                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5882                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5883
5884         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5885         trace_kvm_page_fault(gpa, exit_qualification);
5886
5887         /* It is a write fault? */
5888         error_code = exit_qualification & PFERR_WRITE_MASK;
5889         /* It is a fetch fault? */
5890         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5891         /* ept page table is present? */
5892         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5893
5894         vcpu->arch.exit_qualification = exit_qualification;
5895
5896         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5897 }
5898
5899 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5900 {
5901         int ret;
5902         gpa_t gpa;
5903
5904         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5905         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5906                 skip_emulated_instruction(vcpu);
5907                 trace_kvm_fast_mmio(gpa);
5908                 return 1;
5909         }
5910
5911         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5912         if (likely(ret == RET_MMIO_PF_EMULATE))
5913                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5914                                               EMULATE_DONE;
5915
5916         if (unlikely(ret == RET_MMIO_PF_INVALID))
5917                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5918
5919         if (unlikely(ret == RET_MMIO_PF_RETRY))
5920                 return 1;
5921
5922         /* It is the real ept misconfig */
5923         WARN_ON(1);
5924
5925         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5926         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5927
5928         return 0;
5929 }
5930
5931 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5932 {
5933         u32 cpu_based_vm_exec_control;
5934
5935         /* clear pending NMI */
5936         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5937         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5938         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5939         ++vcpu->stat.nmi_window_exits;
5940         kvm_make_request(KVM_REQ_EVENT, vcpu);
5941
5942         return 1;
5943 }
5944
5945 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5946 {
5947         struct vcpu_vmx *vmx = to_vmx(vcpu);
5948         enum emulation_result err = EMULATE_DONE;
5949         int ret = 1;
5950         u32 cpu_exec_ctrl;
5951         bool intr_window_requested;
5952         unsigned count = 130;
5953
5954         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5955         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5956
5957         while (vmx->emulation_required && count-- != 0) {
5958                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5959                         return handle_interrupt_window(&vmx->vcpu);
5960
5961                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5962                         return 1;
5963
5964                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5965
5966                 if (err == EMULATE_USER_EXIT) {
5967                         ++vcpu->stat.mmio_exits;
5968                         ret = 0;
5969                         goto out;
5970                 }
5971
5972                 if (err != EMULATE_DONE) {
5973                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5974                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5975                         vcpu->run->internal.ndata = 0;
5976                         return 0;
5977                 }
5978
5979                 if (vcpu->arch.halt_request) {
5980                         vcpu->arch.halt_request = 0;
5981                         ret = kvm_vcpu_halt(vcpu);
5982                         goto out;
5983                 }
5984
5985                 if (signal_pending(current))
5986                         goto out;
5987                 if (need_resched())
5988                         schedule();
5989         }
5990
5991 out:
5992         return ret;
5993 }
5994
5995 static int __grow_ple_window(int val)
5996 {
5997         if (ple_window_grow < 1)
5998                 return ple_window;
5999
6000         val = min(val, ple_window_actual_max);
6001
6002         if (ple_window_grow < ple_window)
6003                 val *= ple_window_grow;
6004         else
6005                 val += ple_window_grow;
6006
6007         return val;
6008 }
6009
6010 static int __shrink_ple_window(int val, int modifier, int minimum)
6011 {
6012         if (modifier < 1)
6013                 return ple_window;
6014
6015         if (modifier < ple_window)
6016                 val /= modifier;
6017         else
6018                 val -= modifier;
6019
6020         return max(val, minimum);
6021 }
6022
6023 static void grow_ple_window(struct kvm_vcpu *vcpu)
6024 {
6025         struct vcpu_vmx *vmx = to_vmx(vcpu);
6026         int old = vmx->ple_window;
6027
6028         vmx->ple_window = __grow_ple_window(old);
6029
6030         if (vmx->ple_window != old)
6031                 vmx->ple_window_dirty = true;
6032
6033         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6034 }
6035
6036 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6037 {
6038         struct vcpu_vmx *vmx = to_vmx(vcpu);
6039         int old = vmx->ple_window;
6040
6041         vmx->ple_window = __shrink_ple_window(old,
6042                                               ple_window_shrink, ple_window);
6043
6044         if (vmx->ple_window != old)
6045                 vmx->ple_window_dirty = true;
6046
6047         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6048 }
6049
6050 /*
6051  * ple_window_actual_max is computed to be one grow_ple_window() below
6052  * ple_window_max. (See __grow_ple_window for the reason.)
6053  * This prevents overflows, because ple_window_max is int.
6054  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6055  * this process.
6056  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6057  */
6058 static void update_ple_window_actual_max(void)
6059 {
6060         ple_window_actual_max =
6061                         __shrink_ple_window(max(ple_window_max, ple_window),
6062                                             ple_window_grow, INT_MIN);
6063 }
6064
6065 /*
6066  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6067  */
6068 static void wakeup_handler(void)
6069 {
6070         struct kvm_vcpu *vcpu;
6071         int cpu = smp_processor_id();
6072
6073         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6074         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6075                         blocked_vcpu_list) {
6076                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6077
6078                 if (pi_test_on(pi_desc) == 1)
6079                         kvm_vcpu_kick(vcpu);
6080         }
6081         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6082 }
6083
6084 static __init int hardware_setup(void)
6085 {
6086         int r = -ENOMEM, i, msr;
6087
6088         rdmsrl_safe(MSR_EFER, &host_efer);
6089
6090         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6091                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6092
6093         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6094         if (!vmx_io_bitmap_a)
6095                 return r;
6096
6097         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6098         if (!vmx_io_bitmap_b)
6099                 goto out;
6100
6101         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6102         if (!vmx_msr_bitmap_legacy)
6103                 goto out1;
6104
6105         vmx_msr_bitmap_legacy_x2apic =
6106                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6107         if (!vmx_msr_bitmap_legacy_x2apic)
6108                 goto out2;
6109
6110         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6111         if (!vmx_msr_bitmap_longmode)
6112                 goto out3;
6113
6114         vmx_msr_bitmap_longmode_x2apic =
6115                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6116         if (!vmx_msr_bitmap_longmode_x2apic)
6117                 goto out4;
6118
6119         if (nested) {
6120                 vmx_msr_bitmap_nested =
6121                         (unsigned long *)__get_free_page(GFP_KERNEL);
6122                 if (!vmx_msr_bitmap_nested)
6123                         goto out5;
6124         }
6125
6126         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6127         if (!vmx_vmread_bitmap)
6128                 goto out6;
6129
6130         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6131         if (!vmx_vmwrite_bitmap)
6132                 goto out7;
6133
6134         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6135         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6136
6137         /*
6138          * Allow direct access to the PC debug port (it is often used for I/O
6139          * delays, but the vmexits simply slow things down).
6140          */
6141         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6142         clear_bit(0x80, vmx_io_bitmap_a);
6143
6144         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6145
6146         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6147         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6148         if (nested)
6149                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6150
6151         if (setup_vmcs_config(&vmcs_config) < 0) {
6152                 r = -EIO;
6153                 goto out8;
6154         }
6155
6156         if (boot_cpu_has(X86_FEATURE_NX))
6157                 kvm_enable_efer_bits(EFER_NX);
6158
6159         if (!cpu_has_vmx_vpid())
6160                 enable_vpid = 0;
6161         if (!cpu_has_vmx_shadow_vmcs())
6162                 enable_shadow_vmcs = 0;
6163         if (enable_shadow_vmcs)
6164                 init_vmcs_shadow_fields();
6165
6166         if (!cpu_has_vmx_ept() ||
6167             !cpu_has_vmx_ept_4levels()) {
6168                 enable_ept = 0;
6169                 enable_unrestricted_guest = 0;
6170                 enable_ept_ad_bits = 0;
6171         }
6172
6173         if (!cpu_has_vmx_ept_ad_bits())
6174                 enable_ept_ad_bits = 0;
6175
6176         if (!cpu_has_vmx_unrestricted_guest())
6177                 enable_unrestricted_guest = 0;
6178
6179         if (!cpu_has_vmx_flexpriority())
6180                 flexpriority_enabled = 0;
6181
6182         /*
6183          * set_apic_access_page_addr() is used to reload apic access
6184          * page upon invalidation.  No need to do anything if not
6185          * using the APIC_ACCESS_ADDR VMCS field.
6186          */
6187         if (!flexpriority_enabled)
6188                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6189
6190         if (!cpu_has_vmx_tpr_shadow())
6191                 kvm_x86_ops->update_cr8_intercept = NULL;
6192
6193         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6194                 kvm_disable_largepages();
6195
6196         if (!cpu_has_vmx_ple())
6197                 ple_gap = 0;
6198
6199         if (!cpu_has_vmx_apicv())
6200                 enable_apicv = 0;
6201
6202         if (enable_apicv)
6203                 kvm_x86_ops->update_cr8_intercept = NULL;
6204         else {
6205                 kvm_x86_ops->hwapic_irr_update = NULL;
6206                 kvm_x86_ops->hwapic_isr_update = NULL;
6207                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6208                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6209         }
6210
6211         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6212         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6213         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6214         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6215         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6216         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6217         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6218
6219         memcpy(vmx_msr_bitmap_legacy_x2apic,
6220                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6221         memcpy(vmx_msr_bitmap_longmode_x2apic,
6222                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6223
6224         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6225
6226         if (enable_apicv) {
6227                 for (msr = 0x800; msr <= 0x8ff; msr++)
6228                         vmx_disable_intercept_msr_read_x2apic(msr);
6229
6230                 /* According SDM, in x2apic mode, the whole id reg is used.
6231                  * But in KVM, it only use the highest eight bits. Need to
6232                  * intercept it */
6233                 vmx_enable_intercept_msr_read_x2apic(0x802);
6234                 /* TMCCT */
6235                 vmx_enable_intercept_msr_read_x2apic(0x839);
6236                 /* TPR */
6237                 vmx_disable_intercept_msr_write_x2apic(0x808);
6238                 /* EOI */
6239                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6240                 /* SELF-IPI */
6241                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6242         }
6243
6244         if (enable_ept) {
6245                 kvm_mmu_set_mask_ptes(0ull,
6246                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6247                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6248                         0ull, VMX_EPT_EXECUTABLE_MASK);
6249                 ept_set_mmio_spte_mask();
6250                 kvm_enable_tdp();
6251         } else
6252                 kvm_disable_tdp();
6253
6254         update_ple_window_actual_max();
6255
6256         /*
6257          * Only enable PML when hardware supports PML feature, and both EPT
6258          * and EPT A/D bit features are enabled -- PML depends on them to work.
6259          */
6260         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6261                 enable_pml = 0;
6262
6263         if (!enable_pml) {
6264                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6265                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6266                 kvm_x86_ops->flush_log_dirty = NULL;
6267                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6268         }
6269
6270         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6271
6272         return alloc_kvm_area();
6273
6274 out8:
6275         free_page((unsigned long)vmx_vmwrite_bitmap);
6276 out7:
6277         free_page((unsigned long)vmx_vmread_bitmap);
6278 out6:
6279         if (nested)
6280                 free_page((unsigned long)vmx_msr_bitmap_nested);
6281 out5:
6282         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6283 out4:
6284         free_page((unsigned long)vmx_msr_bitmap_longmode);
6285 out3:
6286         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6287 out2:
6288         free_page((unsigned long)vmx_msr_bitmap_legacy);
6289 out1:
6290         free_page((unsigned long)vmx_io_bitmap_b);
6291 out:
6292         free_page((unsigned long)vmx_io_bitmap_a);
6293
6294     return r;
6295 }
6296
6297 static __exit void hardware_unsetup(void)
6298 {
6299         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6300         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6301         free_page((unsigned long)vmx_msr_bitmap_legacy);
6302         free_page((unsigned long)vmx_msr_bitmap_longmode);
6303         free_page((unsigned long)vmx_io_bitmap_b);
6304         free_page((unsigned long)vmx_io_bitmap_a);
6305         free_page((unsigned long)vmx_vmwrite_bitmap);
6306         free_page((unsigned long)vmx_vmread_bitmap);
6307         if (nested)
6308                 free_page((unsigned long)vmx_msr_bitmap_nested);
6309
6310         free_kvm_area();
6311 }
6312
6313 /*
6314  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6315  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6316  */
6317 static int handle_pause(struct kvm_vcpu *vcpu)
6318 {
6319         if (ple_gap)
6320                 grow_ple_window(vcpu);
6321
6322         skip_emulated_instruction(vcpu);
6323         kvm_vcpu_on_spin(vcpu);
6324
6325         return 1;
6326 }
6327
6328 static int handle_nop(struct kvm_vcpu *vcpu)
6329 {
6330         skip_emulated_instruction(vcpu);
6331         return 1;
6332 }
6333
6334 static int handle_mwait(struct kvm_vcpu *vcpu)
6335 {
6336         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6337         return handle_nop(vcpu);
6338 }
6339
6340 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6341 {
6342         return 1;
6343 }
6344
6345 static int handle_monitor(struct kvm_vcpu *vcpu)
6346 {
6347         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6348         return handle_nop(vcpu);
6349 }
6350
6351 /*
6352  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6353  * We could reuse a single VMCS for all the L2 guests, but we also want the
6354  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6355  * allows keeping them loaded on the processor, and in the future will allow
6356  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6357  * every entry if they never change.
6358  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6359  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6360  *
6361  * The following functions allocate and free a vmcs02 in this pool.
6362  */
6363
6364 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6365 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6366 {
6367         struct vmcs02_list *item;
6368         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6369                 if (item->vmptr == vmx->nested.current_vmptr) {
6370                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6371                         return &item->vmcs02;
6372                 }
6373
6374         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6375                 /* Recycle the least recently used VMCS. */
6376                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6377                         struct vmcs02_list, list);
6378                 item->vmptr = vmx->nested.current_vmptr;
6379                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6380                 return &item->vmcs02;
6381         }
6382
6383         /* Create a new VMCS */
6384         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6385         if (!item)
6386                 return NULL;
6387         item->vmcs02.vmcs = alloc_vmcs();
6388         if (!item->vmcs02.vmcs) {
6389                 kfree(item);
6390                 return NULL;
6391         }
6392         loaded_vmcs_init(&item->vmcs02);
6393         item->vmptr = vmx->nested.current_vmptr;
6394         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6395         vmx->nested.vmcs02_num++;
6396         return &item->vmcs02;
6397 }
6398
6399 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6400 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6401 {
6402         struct vmcs02_list *item;
6403         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6404                 if (item->vmptr == vmptr) {
6405                         free_loaded_vmcs(&item->vmcs02);
6406                         list_del(&item->list);
6407                         kfree(item);
6408                         vmx->nested.vmcs02_num--;
6409                         return;
6410                 }
6411 }
6412
6413 /*
6414  * Free all VMCSs saved for this vcpu, except the one pointed by
6415  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6416  * must be &vmx->vmcs01.
6417  */
6418 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6419 {
6420         struct vmcs02_list *item, *n;
6421
6422         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6423         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6424                 /*
6425                  * Something will leak if the above WARN triggers.  Better than
6426                  * a use-after-free.
6427                  */
6428                 if (vmx->loaded_vmcs == &item->vmcs02)
6429                         continue;
6430
6431                 free_loaded_vmcs(&item->vmcs02);
6432                 list_del(&item->list);
6433                 kfree(item);
6434                 vmx->nested.vmcs02_num--;
6435         }
6436 }
6437
6438 /*
6439  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6440  * set the success or error code of an emulated VMX instruction, as specified
6441  * by Vol 2B, VMX Instruction Reference, "Conventions".
6442  */
6443 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6444 {
6445         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6446                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6447                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6448 }
6449
6450 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6451 {
6452         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6453                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6454                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6455                         | X86_EFLAGS_CF);
6456 }
6457
6458 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6459                                         u32 vm_instruction_error)
6460 {
6461         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6462                 /*
6463                  * failValid writes the error number to the current VMCS, which
6464                  * can't be done there isn't a current VMCS.
6465                  */
6466                 nested_vmx_failInvalid(vcpu);
6467                 return;
6468         }
6469         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6470                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6471                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6472                         | X86_EFLAGS_ZF);
6473         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6474         /*
6475          * We don't need to force a shadow sync because
6476          * VM_INSTRUCTION_ERROR is not shadowed
6477          */
6478 }
6479
6480 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6481 {
6482         /* TODO: not to reset guest simply here. */
6483         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6484         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6485 }
6486
6487 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6488 {
6489         struct vcpu_vmx *vmx =
6490                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6491
6492         vmx->nested.preemption_timer_expired = true;
6493         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6494         kvm_vcpu_kick(&vmx->vcpu);
6495
6496         return HRTIMER_NORESTART;
6497 }
6498
6499 /*
6500  * Decode the memory-address operand of a vmx instruction, as recorded on an
6501  * exit caused by such an instruction (run by a guest hypervisor).
6502  * On success, returns 0. When the operand is invalid, returns 1 and throws
6503  * #UD or #GP.
6504  */
6505 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6506                                  unsigned long exit_qualification,
6507                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6508 {
6509         gva_t off;
6510         bool exn;
6511         struct kvm_segment s;
6512
6513         /*
6514          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6515          * Execution", on an exit, vmx_instruction_info holds most of the
6516          * addressing components of the operand. Only the displacement part
6517          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6518          * For how an actual address is calculated from all these components,
6519          * refer to Vol. 1, "Operand Addressing".
6520          */
6521         int  scaling = vmx_instruction_info & 3;
6522         int  addr_size = (vmx_instruction_info >> 7) & 7;
6523         bool is_reg = vmx_instruction_info & (1u << 10);
6524         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6525         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6526         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6527         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6528         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6529
6530         if (is_reg) {
6531                 kvm_queue_exception(vcpu, UD_VECTOR);
6532                 return 1;
6533         }
6534
6535         /* Addr = segment_base + offset */
6536         /* offset = base + [index * scale] + displacement */
6537         off = exit_qualification; /* holds the displacement */
6538         if (base_is_valid)
6539                 off += kvm_register_read(vcpu, base_reg);
6540         if (index_is_valid)
6541                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6542         vmx_get_segment(vcpu, &s, seg_reg);
6543         *ret = s.base + off;
6544
6545         if (addr_size == 1) /* 32 bit */
6546                 *ret &= 0xffffffff;
6547
6548         /* Checks for #GP/#SS exceptions. */
6549         exn = false;
6550         if (is_protmode(vcpu)) {
6551                 /* Protected mode: apply checks for segment validity in the
6552                  * following order:
6553                  * - segment type check (#GP(0) may be thrown)
6554                  * - usability check (#GP(0)/#SS(0))
6555                  * - limit check (#GP(0)/#SS(0))
6556                  */
6557                 if (wr)
6558                         /* #GP(0) if the destination operand is located in a
6559                          * read-only data segment or any code segment.
6560                          */
6561                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6562                 else
6563                         /* #GP(0) if the source operand is located in an
6564                          * execute-only code segment
6565                          */
6566                         exn = ((s.type & 0xa) == 8);
6567         }
6568         if (exn) {
6569                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6570                 return 1;
6571         }
6572         if (is_long_mode(vcpu)) {
6573                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6574                  * non-canonical form. This is an only check for long mode.
6575                  */
6576                 exn = is_noncanonical_address(*ret);
6577         } else if (is_protmode(vcpu)) {
6578                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6579                  */
6580                 exn = (s.unusable != 0);
6581                 /* Protected mode: #GP(0)/#SS(0) if the memory
6582                  * operand is outside the segment limit.
6583                  */
6584                 exn = exn || (off + sizeof(u64) > s.limit);
6585         }
6586         if (exn) {
6587                 kvm_queue_exception_e(vcpu,
6588                                       seg_reg == VCPU_SREG_SS ?
6589                                                 SS_VECTOR : GP_VECTOR,
6590                                       0);
6591                 return 1;
6592         }
6593
6594         return 0;
6595 }
6596
6597 /*
6598  * This function performs the various checks including
6599  * - if it's 4KB aligned
6600  * - No bits beyond the physical address width are set
6601  * - Returns 0 on success or else 1
6602  * (Intel SDM Section 30.3)
6603  */
6604 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6605                                   gpa_t *vmpointer)
6606 {
6607         gva_t gva;
6608         gpa_t vmptr;
6609         struct x86_exception e;
6610         struct page *page;
6611         struct vcpu_vmx *vmx = to_vmx(vcpu);
6612         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6613
6614         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6615                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6616                 return 1;
6617
6618         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6619                                 sizeof(vmptr), &e)) {
6620                 kvm_inject_page_fault(vcpu, &e);
6621                 return 1;
6622         }
6623
6624         switch (exit_reason) {
6625         case EXIT_REASON_VMON:
6626                 /*
6627                  * SDM 3: 24.11.5
6628                  * The first 4 bytes of VMXON region contain the supported
6629                  * VMCS revision identifier
6630                  *
6631                  * Note - IA32_VMX_BASIC[48] will never be 1
6632                  * for the nested case;
6633                  * which replaces physical address width with 32
6634                  *
6635                  */
6636                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6637                         nested_vmx_failInvalid(vcpu);
6638                         skip_emulated_instruction(vcpu);
6639                         return 1;
6640                 }
6641
6642                 page = nested_get_page(vcpu, vmptr);
6643                 if (page == NULL ||
6644                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6645                         nested_vmx_failInvalid(vcpu);
6646                         kunmap(page);
6647                         skip_emulated_instruction(vcpu);
6648                         return 1;
6649                 }
6650                 kunmap(page);
6651                 vmx->nested.vmxon_ptr = vmptr;
6652                 break;
6653         case EXIT_REASON_VMCLEAR:
6654                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6655                         nested_vmx_failValid(vcpu,
6656                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6657                         skip_emulated_instruction(vcpu);
6658                         return 1;
6659                 }
6660
6661                 if (vmptr == vmx->nested.vmxon_ptr) {
6662                         nested_vmx_failValid(vcpu,
6663                                              VMXERR_VMCLEAR_VMXON_POINTER);
6664                         skip_emulated_instruction(vcpu);
6665                         return 1;
6666                 }
6667                 break;
6668         case EXIT_REASON_VMPTRLD:
6669                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6670                         nested_vmx_failValid(vcpu,
6671                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6672                         skip_emulated_instruction(vcpu);
6673                         return 1;
6674                 }
6675
6676                 if (vmptr == vmx->nested.vmxon_ptr) {
6677                         nested_vmx_failValid(vcpu,
6678                                              VMXERR_VMCLEAR_VMXON_POINTER);
6679                         skip_emulated_instruction(vcpu);
6680                         return 1;
6681                 }
6682                 break;
6683         default:
6684                 return 1; /* shouldn't happen */
6685         }
6686
6687         if (vmpointer)
6688                 *vmpointer = vmptr;
6689         return 0;
6690 }
6691
6692 /*
6693  * Emulate the VMXON instruction.
6694  * Currently, we just remember that VMX is active, and do not save or even
6695  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6696  * do not currently need to store anything in that guest-allocated memory
6697  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6698  * argument is different from the VMXON pointer (which the spec says they do).
6699  */
6700 static int handle_vmon(struct kvm_vcpu *vcpu)
6701 {
6702         struct kvm_segment cs;
6703         struct vcpu_vmx *vmx = to_vmx(vcpu);
6704         struct vmcs *shadow_vmcs;
6705         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6706                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6707
6708         /* The Intel VMX Instruction Reference lists a bunch of bits that
6709          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6710          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6711          * Otherwise, we should fail with #UD. We test these now:
6712          */
6713         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6714             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6715             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6716                 kvm_queue_exception(vcpu, UD_VECTOR);
6717                 return 1;
6718         }
6719
6720         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6721         if (is_long_mode(vcpu) && !cs.l) {
6722                 kvm_queue_exception(vcpu, UD_VECTOR);
6723                 return 1;
6724         }
6725
6726         if (vmx_get_cpl(vcpu)) {
6727                 kvm_inject_gp(vcpu, 0);
6728                 return 1;
6729         }
6730
6731         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6732                 return 1;
6733
6734         if (vmx->nested.vmxon) {
6735                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6736                 skip_emulated_instruction(vcpu);
6737                 return 1;
6738         }
6739
6740         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6741                         != VMXON_NEEDED_FEATURES) {
6742                 kvm_inject_gp(vcpu, 0);
6743                 return 1;
6744         }
6745
6746         if (enable_shadow_vmcs) {
6747                 shadow_vmcs = alloc_vmcs();
6748                 if (!shadow_vmcs)
6749                         return -ENOMEM;
6750                 /* mark vmcs as shadow */
6751                 shadow_vmcs->revision_id |= (1u << 31);
6752                 /* init shadow vmcs */
6753                 vmcs_clear(shadow_vmcs);
6754                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6755         }
6756
6757         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6758         vmx->nested.vmcs02_num = 0;
6759
6760         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6761                      HRTIMER_MODE_REL);
6762         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6763
6764         vmx->nested.vmxon = true;
6765
6766         skip_emulated_instruction(vcpu);
6767         nested_vmx_succeed(vcpu);
6768         return 1;
6769 }
6770
6771 /*
6772  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6773  * for running VMX instructions (except VMXON, whose prerequisites are
6774  * slightly different). It also specifies what exception to inject otherwise.
6775  */
6776 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6777 {
6778         struct kvm_segment cs;
6779         struct vcpu_vmx *vmx = to_vmx(vcpu);
6780
6781         if (!vmx->nested.vmxon) {
6782                 kvm_queue_exception(vcpu, UD_VECTOR);
6783                 return 0;
6784         }
6785
6786         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6787         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6788             (is_long_mode(vcpu) && !cs.l)) {
6789                 kvm_queue_exception(vcpu, UD_VECTOR);
6790                 return 0;
6791         }
6792
6793         if (vmx_get_cpl(vcpu)) {
6794                 kvm_inject_gp(vcpu, 0);
6795                 return 0;
6796         }
6797
6798         return 1;
6799 }
6800
6801 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6802 {
6803         if (vmx->nested.current_vmptr == -1ull)
6804                 return;
6805
6806         /* current_vmptr and current_vmcs12 are always set/reset together */
6807         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6808                 return;
6809
6810         if (enable_shadow_vmcs) {
6811                 /* copy to memory all shadowed fields in case
6812                    they were modified */
6813                 copy_shadow_to_vmcs12(vmx);
6814                 vmx->nested.sync_shadow_vmcs = false;
6815                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6816                                 SECONDARY_EXEC_SHADOW_VMCS);
6817                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6818         }
6819         vmx->nested.posted_intr_nv = -1;
6820         kunmap(vmx->nested.current_vmcs12_page);
6821         nested_release_page(vmx->nested.current_vmcs12_page);
6822         vmx->nested.current_vmptr = -1ull;
6823         vmx->nested.current_vmcs12 = NULL;
6824 }
6825
6826 /*
6827  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6828  * just stops using VMX.
6829  */
6830 static void free_nested(struct vcpu_vmx *vmx)
6831 {
6832         if (!vmx->nested.vmxon)
6833                 return;
6834
6835         vmx->nested.vmxon = false;
6836         free_vpid(vmx->nested.vpid02);
6837         nested_release_vmcs12(vmx);
6838         if (enable_shadow_vmcs)
6839                 free_vmcs(vmx->nested.current_shadow_vmcs);
6840         /* Unpin physical memory we referred to in current vmcs02 */
6841         if (vmx->nested.apic_access_page) {
6842                 nested_release_page(vmx->nested.apic_access_page);
6843                 vmx->nested.apic_access_page = NULL;
6844         }
6845         if (vmx->nested.virtual_apic_page) {
6846                 nested_release_page(vmx->nested.virtual_apic_page);
6847                 vmx->nested.virtual_apic_page = NULL;
6848         }
6849         if (vmx->nested.pi_desc_page) {
6850                 kunmap(vmx->nested.pi_desc_page);
6851                 nested_release_page(vmx->nested.pi_desc_page);
6852                 vmx->nested.pi_desc_page = NULL;
6853                 vmx->nested.pi_desc = NULL;
6854         }
6855
6856         nested_free_all_saved_vmcss(vmx);
6857 }
6858
6859 /* Emulate the VMXOFF instruction */
6860 static int handle_vmoff(struct kvm_vcpu *vcpu)
6861 {
6862         if (!nested_vmx_check_permission(vcpu))
6863                 return 1;
6864         free_nested(to_vmx(vcpu));
6865         skip_emulated_instruction(vcpu);
6866         nested_vmx_succeed(vcpu);
6867         return 1;
6868 }
6869
6870 /* Emulate the VMCLEAR instruction */
6871 static int handle_vmclear(struct kvm_vcpu *vcpu)
6872 {
6873         struct vcpu_vmx *vmx = to_vmx(vcpu);
6874         gpa_t vmptr;
6875         struct vmcs12 *vmcs12;
6876         struct page *page;
6877
6878         if (!nested_vmx_check_permission(vcpu))
6879                 return 1;
6880
6881         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6882                 return 1;
6883
6884         if (vmptr == vmx->nested.current_vmptr)
6885                 nested_release_vmcs12(vmx);
6886
6887         page = nested_get_page(vcpu, vmptr);
6888         if (page == NULL) {
6889                 /*
6890                  * For accurate processor emulation, VMCLEAR beyond available
6891                  * physical memory should do nothing at all. However, it is
6892                  * possible that a nested vmx bug, not a guest hypervisor bug,
6893                  * resulted in this case, so let's shut down before doing any
6894                  * more damage:
6895                  */
6896                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6897                 return 1;
6898         }
6899         vmcs12 = kmap(page);
6900         vmcs12->launch_state = 0;
6901         kunmap(page);
6902         nested_release_page(page);
6903
6904         nested_free_vmcs02(vmx, vmptr);
6905
6906         skip_emulated_instruction(vcpu);
6907         nested_vmx_succeed(vcpu);
6908         return 1;
6909 }
6910
6911 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6912
6913 /* Emulate the VMLAUNCH instruction */
6914 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6915 {
6916         return nested_vmx_run(vcpu, true);
6917 }
6918
6919 /* Emulate the VMRESUME instruction */
6920 static int handle_vmresume(struct kvm_vcpu *vcpu)
6921 {
6922
6923         return nested_vmx_run(vcpu, false);
6924 }
6925
6926 enum vmcs_field_type {
6927         VMCS_FIELD_TYPE_U16 = 0,
6928         VMCS_FIELD_TYPE_U64 = 1,
6929         VMCS_FIELD_TYPE_U32 = 2,
6930         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6931 };
6932
6933 static inline int vmcs_field_type(unsigned long field)
6934 {
6935         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6936                 return VMCS_FIELD_TYPE_U32;
6937         return (field >> 13) & 0x3 ;
6938 }
6939
6940 static inline int vmcs_field_readonly(unsigned long field)
6941 {
6942         return (((field >> 10) & 0x3) == 1);
6943 }
6944
6945 /*
6946  * Read a vmcs12 field. Since these can have varying lengths and we return
6947  * one type, we chose the biggest type (u64) and zero-extend the return value
6948  * to that size. Note that the caller, handle_vmread, might need to use only
6949  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6950  * 64-bit fields are to be returned).
6951  */
6952 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6953                                   unsigned long field, u64 *ret)
6954 {
6955         short offset = vmcs_field_to_offset(field);
6956         char *p;
6957
6958         if (offset < 0)
6959                 return offset;
6960
6961         p = ((char *)(get_vmcs12(vcpu))) + offset;
6962
6963         switch (vmcs_field_type(field)) {
6964         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6965                 *ret = *((natural_width *)p);
6966                 return 0;
6967         case VMCS_FIELD_TYPE_U16:
6968                 *ret = *((u16 *)p);
6969                 return 0;
6970         case VMCS_FIELD_TYPE_U32:
6971                 *ret = *((u32 *)p);
6972                 return 0;
6973         case VMCS_FIELD_TYPE_U64:
6974                 *ret = *((u64 *)p);
6975                 return 0;
6976         default:
6977                 WARN_ON(1);
6978                 return -ENOENT;
6979         }
6980 }
6981
6982
6983 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6984                                    unsigned long field, u64 field_value){
6985         short offset = vmcs_field_to_offset(field);
6986         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6987         if (offset < 0)
6988                 return offset;
6989
6990         switch (vmcs_field_type(field)) {
6991         case VMCS_FIELD_TYPE_U16:
6992                 *(u16 *)p = field_value;
6993                 return 0;
6994         case VMCS_FIELD_TYPE_U32:
6995                 *(u32 *)p = field_value;
6996                 return 0;
6997         case VMCS_FIELD_TYPE_U64:
6998                 *(u64 *)p = field_value;
6999                 return 0;
7000         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7001                 *(natural_width *)p = field_value;
7002                 return 0;
7003         default:
7004                 WARN_ON(1);
7005                 return -ENOENT;
7006         }
7007
7008 }
7009
7010 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7011 {
7012         int i;
7013         unsigned long field;
7014         u64 field_value;
7015         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7016         const unsigned long *fields = shadow_read_write_fields;
7017         const int num_fields = max_shadow_read_write_fields;
7018
7019         preempt_disable();
7020
7021         vmcs_load(shadow_vmcs);
7022
7023         for (i = 0; i < num_fields; i++) {
7024                 field = fields[i];
7025                 switch (vmcs_field_type(field)) {
7026                 case VMCS_FIELD_TYPE_U16:
7027                         field_value = vmcs_read16(field);
7028                         break;
7029                 case VMCS_FIELD_TYPE_U32:
7030                         field_value = vmcs_read32(field);
7031                         break;
7032                 case VMCS_FIELD_TYPE_U64:
7033                         field_value = vmcs_read64(field);
7034                         break;
7035                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7036                         field_value = vmcs_readl(field);
7037                         break;
7038                 default:
7039                         WARN_ON(1);
7040                         continue;
7041                 }
7042                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7043         }
7044
7045         vmcs_clear(shadow_vmcs);
7046         vmcs_load(vmx->loaded_vmcs->vmcs);
7047
7048         preempt_enable();
7049 }
7050
7051 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7052 {
7053         const unsigned long *fields[] = {
7054                 shadow_read_write_fields,
7055                 shadow_read_only_fields
7056         };
7057         const int max_fields[] = {
7058                 max_shadow_read_write_fields,
7059                 max_shadow_read_only_fields
7060         };
7061         int i, q;
7062         unsigned long field;
7063         u64 field_value = 0;
7064         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7065
7066         vmcs_load(shadow_vmcs);
7067
7068         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7069                 for (i = 0; i < max_fields[q]; i++) {
7070                         field = fields[q][i];
7071                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7072
7073                         switch (vmcs_field_type(field)) {
7074                         case VMCS_FIELD_TYPE_U16:
7075                                 vmcs_write16(field, (u16)field_value);
7076                                 break;
7077                         case VMCS_FIELD_TYPE_U32:
7078                                 vmcs_write32(field, (u32)field_value);
7079                                 break;
7080                         case VMCS_FIELD_TYPE_U64:
7081                                 vmcs_write64(field, (u64)field_value);
7082                                 break;
7083                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7084                                 vmcs_writel(field, (long)field_value);
7085                                 break;
7086                         default:
7087                                 WARN_ON(1);
7088                                 break;
7089                         }
7090                 }
7091         }
7092
7093         vmcs_clear(shadow_vmcs);
7094         vmcs_load(vmx->loaded_vmcs->vmcs);
7095 }
7096
7097 /*
7098  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7099  * used before) all generate the same failure when it is missing.
7100  */
7101 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7102 {
7103         struct vcpu_vmx *vmx = to_vmx(vcpu);
7104         if (vmx->nested.current_vmptr == -1ull) {
7105                 nested_vmx_failInvalid(vcpu);
7106                 skip_emulated_instruction(vcpu);
7107                 return 0;
7108         }
7109         return 1;
7110 }
7111
7112 static int handle_vmread(struct kvm_vcpu *vcpu)
7113 {
7114         unsigned long field;
7115         u64 field_value;
7116         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7117         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7118         gva_t gva = 0;
7119
7120         if (!nested_vmx_check_permission(vcpu) ||
7121             !nested_vmx_check_vmcs12(vcpu))
7122                 return 1;
7123
7124         /* Decode instruction info and find the field to read */
7125         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7126         /* Read the field, zero-extended to a u64 field_value */
7127         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7128                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7129                 skip_emulated_instruction(vcpu);
7130                 return 1;
7131         }
7132         /*
7133          * Now copy part of this value to register or memory, as requested.
7134          * Note that the number of bits actually copied is 32 or 64 depending
7135          * on the guest's mode (32 or 64 bit), not on the given field's length.
7136          */
7137         if (vmx_instruction_info & (1u << 10)) {
7138                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7139                         field_value);
7140         } else {
7141                 if (get_vmx_mem_address(vcpu, exit_qualification,
7142                                 vmx_instruction_info, true, &gva))
7143                         return 1;
7144                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7145                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7146                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7147         }
7148
7149         nested_vmx_succeed(vcpu);
7150         skip_emulated_instruction(vcpu);
7151         return 1;
7152 }
7153
7154
7155 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7156 {
7157         unsigned long field;
7158         gva_t gva;
7159         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7160         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7161         /* The value to write might be 32 or 64 bits, depending on L1's long
7162          * mode, and eventually we need to write that into a field of several
7163          * possible lengths. The code below first zero-extends the value to 64
7164          * bit (field_value), and then copies only the approriate number of
7165          * bits into the vmcs12 field.
7166          */
7167         u64 field_value = 0;
7168         struct x86_exception e;
7169
7170         if (!nested_vmx_check_permission(vcpu) ||
7171             !nested_vmx_check_vmcs12(vcpu))
7172                 return 1;
7173
7174         if (vmx_instruction_info & (1u << 10))
7175                 field_value = kvm_register_readl(vcpu,
7176                         (((vmx_instruction_info) >> 3) & 0xf));
7177         else {
7178                 if (get_vmx_mem_address(vcpu, exit_qualification,
7179                                 vmx_instruction_info, false, &gva))
7180                         return 1;
7181                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7182                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7183                         kvm_inject_page_fault(vcpu, &e);
7184                         return 1;
7185                 }
7186         }
7187
7188
7189         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7190         if (vmcs_field_readonly(field)) {
7191                 nested_vmx_failValid(vcpu,
7192                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7193                 skip_emulated_instruction(vcpu);
7194                 return 1;
7195         }
7196
7197         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7198                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7199                 skip_emulated_instruction(vcpu);
7200                 return 1;
7201         }
7202
7203         nested_vmx_succeed(vcpu);
7204         skip_emulated_instruction(vcpu);
7205         return 1;
7206 }
7207
7208 /* Emulate the VMPTRLD instruction */
7209 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7210 {
7211         struct vcpu_vmx *vmx = to_vmx(vcpu);
7212         gpa_t vmptr;
7213
7214         if (!nested_vmx_check_permission(vcpu))
7215                 return 1;
7216
7217         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7218                 return 1;
7219
7220         if (vmx->nested.current_vmptr != vmptr) {
7221                 struct vmcs12 *new_vmcs12;
7222                 struct page *page;
7223                 page = nested_get_page(vcpu, vmptr);
7224                 if (page == NULL) {
7225                         nested_vmx_failInvalid(vcpu);
7226                         skip_emulated_instruction(vcpu);
7227                         return 1;
7228                 }
7229                 new_vmcs12 = kmap(page);
7230                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7231                         kunmap(page);
7232                         nested_release_page_clean(page);
7233                         nested_vmx_failValid(vcpu,
7234                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7235                         skip_emulated_instruction(vcpu);
7236                         return 1;
7237                 }
7238
7239                 nested_release_vmcs12(vmx);
7240                 vmx->nested.current_vmptr = vmptr;
7241                 vmx->nested.current_vmcs12 = new_vmcs12;
7242                 vmx->nested.current_vmcs12_page = page;
7243                 if (enable_shadow_vmcs) {
7244                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7245                                       SECONDARY_EXEC_SHADOW_VMCS);
7246                         vmcs_write64(VMCS_LINK_POINTER,
7247                                      __pa(vmx->nested.current_shadow_vmcs));
7248                         vmx->nested.sync_shadow_vmcs = true;
7249                 }
7250         }
7251
7252         nested_vmx_succeed(vcpu);
7253         skip_emulated_instruction(vcpu);
7254         return 1;
7255 }
7256
7257 /* Emulate the VMPTRST instruction */
7258 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7259 {
7260         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7261         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7262         gva_t vmcs_gva;
7263         struct x86_exception e;
7264
7265         if (!nested_vmx_check_permission(vcpu))
7266                 return 1;
7267
7268         if (get_vmx_mem_address(vcpu, exit_qualification,
7269                         vmx_instruction_info, true, &vmcs_gva))
7270                 return 1;
7271         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7272         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7273                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7274                                  sizeof(u64), &e)) {
7275                 kvm_inject_page_fault(vcpu, &e);
7276                 return 1;
7277         }
7278         nested_vmx_succeed(vcpu);
7279         skip_emulated_instruction(vcpu);
7280         return 1;
7281 }
7282
7283 /* Emulate the INVEPT instruction */
7284 static int handle_invept(struct kvm_vcpu *vcpu)
7285 {
7286         struct vcpu_vmx *vmx = to_vmx(vcpu);
7287         u32 vmx_instruction_info, types;
7288         unsigned long type;
7289         gva_t gva;
7290         struct x86_exception e;
7291         struct {
7292                 u64 eptp, gpa;
7293         } operand;
7294
7295         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7296               SECONDARY_EXEC_ENABLE_EPT) ||
7297             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7298                 kvm_queue_exception(vcpu, UD_VECTOR);
7299                 return 1;
7300         }
7301
7302         if (!nested_vmx_check_permission(vcpu))
7303                 return 1;
7304
7305         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7306                 kvm_queue_exception(vcpu, UD_VECTOR);
7307                 return 1;
7308         }
7309
7310         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7311         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7312
7313         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7314
7315         if (!(types & (1UL << type))) {
7316                 nested_vmx_failValid(vcpu,
7317                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7318                 return 1;
7319         }
7320
7321         /* According to the Intel VMX instruction reference, the memory
7322          * operand is read even if it isn't needed (e.g., for type==global)
7323          */
7324         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7325                         vmx_instruction_info, false, &gva))
7326                 return 1;
7327         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7328                                 sizeof(operand), &e)) {
7329                 kvm_inject_page_fault(vcpu, &e);
7330                 return 1;
7331         }
7332
7333         switch (type) {
7334         case VMX_EPT_EXTENT_GLOBAL:
7335                 kvm_mmu_sync_roots(vcpu);
7336                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7337                 nested_vmx_succeed(vcpu);
7338                 break;
7339         default:
7340                 /* Trap single context invalidation invept calls */
7341                 BUG_ON(1);
7342                 break;
7343         }
7344
7345         skip_emulated_instruction(vcpu);
7346         return 1;
7347 }
7348
7349 static int handle_invvpid(struct kvm_vcpu *vcpu)
7350 {
7351         struct vcpu_vmx *vmx = to_vmx(vcpu);
7352         u32 vmx_instruction_info;
7353         unsigned long type, types;
7354         gva_t gva;
7355         struct x86_exception e;
7356         int vpid;
7357
7358         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7359               SECONDARY_EXEC_ENABLE_VPID) ||
7360                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7361                 kvm_queue_exception(vcpu, UD_VECTOR);
7362                 return 1;
7363         }
7364
7365         if (!nested_vmx_check_permission(vcpu))
7366                 return 1;
7367
7368         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7369         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7370
7371         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7372
7373         if (!(types & (1UL << type))) {
7374                 nested_vmx_failValid(vcpu,
7375                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7376                 return 1;
7377         }
7378
7379         /* according to the intel vmx instruction reference, the memory
7380          * operand is read even if it isn't needed (e.g., for type==global)
7381          */
7382         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7383                         vmx_instruction_info, false, &gva))
7384                 return 1;
7385         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7386                                 sizeof(u32), &e)) {
7387                 kvm_inject_page_fault(vcpu, &e);
7388                 return 1;
7389         }
7390
7391         switch (type) {
7392         case VMX_VPID_EXTENT_ALL_CONTEXT:
7393                 if (get_vmcs12(vcpu)->virtual_processor_id == 0) {
7394                         nested_vmx_failValid(vcpu,
7395                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7396                         return 1;
7397                 }
7398                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7399                 nested_vmx_succeed(vcpu);
7400                 break;
7401         default:
7402                 /* Trap single context invalidation invvpid calls */
7403                 BUG_ON(1);
7404                 break;
7405         }
7406
7407         skip_emulated_instruction(vcpu);
7408         return 1;
7409 }
7410
7411 static int handle_pml_full(struct kvm_vcpu *vcpu)
7412 {
7413         unsigned long exit_qualification;
7414
7415         trace_kvm_pml_full(vcpu->vcpu_id);
7416
7417         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7418
7419         /*
7420          * PML buffer FULL happened while executing iret from NMI,
7421          * "blocked by NMI" bit has to be set before next VM entry.
7422          */
7423         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7424                         cpu_has_virtual_nmis() &&
7425                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7426                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7427                                 GUEST_INTR_STATE_NMI);
7428
7429         /*
7430          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7431          * here.., and there's no userspace involvement needed for PML.
7432          */
7433         return 1;
7434 }
7435
7436 static int handle_pcommit(struct kvm_vcpu *vcpu)
7437 {
7438         /* we never catch pcommit instruct for L1 guest. */
7439         WARN_ON(1);
7440         return 1;
7441 }
7442
7443 /*
7444  * The exit handlers return 1 if the exit was handled fully and guest execution
7445  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7446  * to be done to userspace and return 0.
7447  */
7448 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7449         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7450         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7451         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7452         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7453         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7454         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7455         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7456         [EXIT_REASON_CPUID]                   = handle_cpuid,
7457         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7458         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7459         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7460         [EXIT_REASON_HLT]                     = handle_halt,
7461         [EXIT_REASON_INVD]                    = handle_invd,
7462         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7463         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7464         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7465         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7466         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7467         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7468         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7469         [EXIT_REASON_VMREAD]                  = handle_vmread,
7470         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7471         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7472         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7473         [EXIT_REASON_VMON]                    = handle_vmon,
7474         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7475         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7476         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7477         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7478         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7479         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7480         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7481         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7482         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7483         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7484         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7485         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7486         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7487         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7488         [EXIT_REASON_INVEPT]                  = handle_invept,
7489         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7490         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7491         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7492         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7493         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7494 };
7495
7496 static const int kvm_vmx_max_exit_handlers =
7497         ARRAY_SIZE(kvm_vmx_exit_handlers);
7498
7499 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7500                                        struct vmcs12 *vmcs12)
7501 {
7502         unsigned long exit_qualification;
7503         gpa_t bitmap, last_bitmap;
7504         unsigned int port;
7505         int size;
7506         u8 b;
7507
7508         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7509                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7510
7511         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7512
7513         port = exit_qualification >> 16;
7514         size = (exit_qualification & 7) + 1;
7515
7516         last_bitmap = (gpa_t)-1;
7517         b = -1;
7518
7519         while (size > 0) {
7520                 if (port < 0x8000)
7521                         bitmap = vmcs12->io_bitmap_a;
7522                 else if (port < 0x10000)
7523                         bitmap = vmcs12->io_bitmap_b;
7524                 else
7525                         return true;
7526                 bitmap += (port & 0x7fff) / 8;
7527
7528                 if (last_bitmap != bitmap)
7529                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7530                                 return true;
7531                 if (b & (1 << (port & 7)))
7532                         return true;
7533
7534                 port++;
7535                 size--;
7536                 last_bitmap = bitmap;
7537         }
7538
7539         return false;
7540 }
7541
7542 /*
7543  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7544  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7545  * disinterest in the current event (read or write a specific MSR) by using an
7546  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7547  */
7548 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7549         struct vmcs12 *vmcs12, u32 exit_reason)
7550 {
7551         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7552         gpa_t bitmap;
7553
7554         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7555                 return true;
7556
7557         /*
7558          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7559          * for the four combinations of read/write and low/high MSR numbers.
7560          * First we need to figure out which of the four to use:
7561          */
7562         bitmap = vmcs12->msr_bitmap;
7563         if (exit_reason == EXIT_REASON_MSR_WRITE)
7564                 bitmap += 2048;
7565         if (msr_index >= 0xc0000000) {
7566                 msr_index -= 0xc0000000;
7567                 bitmap += 1024;
7568         }
7569
7570         /* Then read the msr_index'th bit from this bitmap: */
7571         if (msr_index < 1024*8) {
7572                 unsigned char b;
7573                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7574                         return true;
7575                 return 1 & (b >> (msr_index & 7));
7576         } else
7577                 return true; /* let L1 handle the wrong parameter */
7578 }
7579
7580 /*
7581  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7582  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7583  * intercept (via guest_host_mask etc.) the current event.
7584  */
7585 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7586         struct vmcs12 *vmcs12)
7587 {
7588         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7589         int cr = exit_qualification & 15;
7590         int reg = (exit_qualification >> 8) & 15;
7591         unsigned long val = kvm_register_readl(vcpu, reg);
7592
7593         switch ((exit_qualification >> 4) & 3) {
7594         case 0: /* mov to cr */
7595                 switch (cr) {
7596                 case 0:
7597                         if (vmcs12->cr0_guest_host_mask &
7598                             (val ^ vmcs12->cr0_read_shadow))
7599                                 return true;
7600                         break;
7601                 case 3:
7602                         if ((vmcs12->cr3_target_count >= 1 &&
7603                                         vmcs12->cr3_target_value0 == val) ||
7604                                 (vmcs12->cr3_target_count >= 2 &&
7605                                         vmcs12->cr3_target_value1 == val) ||
7606                                 (vmcs12->cr3_target_count >= 3 &&
7607                                         vmcs12->cr3_target_value2 == val) ||
7608                                 (vmcs12->cr3_target_count >= 4 &&
7609                                         vmcs12->cr3_target_value3 == val))
7610                                 return false;
7611                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7612                                 return true;
7613                         break;
7614                 case 4:
7615                         if (vmcs12->cr4_guest_host_mask &
7616                             (vmcs12->cr4_read_shadow ^ val))
7617                                 return true;
7618                         break;
7619                 case 8:
7620                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7621                                 return true;
7622                         break;
7623                 }
7624                 break;
7625         case 2: /* clts */
7626                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7627                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7628                         return true;
7629                 break;
7630         case 1: /* mov from cr */
7631                 switch (cr) {
7632                 case 3:
7633                         if (vmcs12->cpu_based_vm_exec_control &
7634                             CPU_BASED_CR3_STORE_EXITING)
7635                                 return true;
7636                         break;
7637                 case 8:
7638                         if (vmcs12->cpu_based_vm_exec_control &
7639                             CPU_BASED_CR8_STORE_EXITING)
7640                                 return true;
7641                         break;
7642                 }
7643                 break;
7644         case 3: /* lmsw */
7645                 /*
7646                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7647                  * cr0. Other attempted changes are ignored, with no exit.
7648                  */
7649                 if (vmcs12->cr0_guest_host_mask & 0xe &
7650                     (val ^ vmcs12->cr0_read_shadow))
7651                         return true;
7652                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7653                     !(vmcs12->cr0_read_shadow & 0x1) &&
7654                     (val & 0x1))
7655                         return true;
7656                 break;
7657         }
7658         return false;
7659 }
7660
7661 /*
7662  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7663  * should handle it ourselves in L0 (and then continue L2). Only call this
7664  * when in is_guest_mode (L2).
7665  */
7666 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7667 {
7668         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7669         struct vcpu_vmx *vmx = to_vmx(vcpu);
7670         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7671         u32 exit_reason = vmx->exit_reason;
7672
7673         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7674                                 vmcs_readl(EXIT_QUALIFICATION),
7675                                 vmx->idt_vectoring_info,
7676                                 intr_info,
7677                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7678                                 KVM_ISA_VMX);
7679
7680         if (vmx->nested.nested_run_pending)
7681                 return false;
7682
7683         if (unlikely(vmx->fail)) {
7684                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7685                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7686                 return true;
7687         }
7688
7689         switch (exit_reason) {
7690         case EXIT_REASON_EXCEPTION_NMI:
7691                 if (!is_exception(intr_info))
7692                         return false;
7693                 else if (is_page_fault(intr_info))
7694                         return enable_ept;
7695                 else if (is_no_device(intr_info) &&
7696                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7697                         return false;
7698                 return vmcs12->exception_bitmap &
7699                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7700         case EXIT_REASON_EXTERNAL_INTERRUPT:
7701                 return false;
7702         case EXIT_REASON_TRIPLE_FAULT:
7703                 return true;
7704         case EXIT_REASON_PENDING_INTERRUPT:
7705                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7706         case EXIT_REASON_NMI_WINDOW:
7707                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7708         case EXIT_REASON_TASK_SWITCH:
7709                 return true;
7710         case EXIT_REASON_CPUID:
7711                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7712                         return false;
7713                 return true;
7714         case EXIT_REASON_HLT:
7715                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7716         case EXIT_REASON_INVD:
7717                 return true;
7718         case EXIT_REASON_INVLPG:
7719                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7720         case EXIT_REASON_RDPMC:
7721                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7722         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7723                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7724         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7725         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7726         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7727         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7728         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7729         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7730                 /*
7731                  * VMX instructions trap unconditionally. This allows L1 to
7732                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7733                  */
7734                 return true;
7735         case EXIT_REASON_CR_ACCESS:
7736                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7737         case EXIT_REASON_DR_ACCESS:
7738                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7739         case EXIT_REASON_IO_INSTRUCTION:
7740                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7741         case EXIT_REASON_MSR_READ:
7742         case EXIT_REASON_MSR_WRITE:
7743                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7744         case EXIT_REASON_INVALID_STATE:
7745                 return true;
7746         case EXIT_REASON_MWAIT_INSTRUCTION:
7747                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7748         case EXIT_REASON_MONITOR_TRAP_FLAG:
7749                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7750         case EXIT_REASON_MONITOR_INSTRUCTION:
7751                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7752         case EXIT_REASON_PAUSE_INSTRUCTION:
7753                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7754                         nested_cpu_has2(vmcs12,
7755                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7756         case EXIT_REASON_MCE_DURING_VMENTRY:
7757                 return false;
7758         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7759                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7760         case EXIT_REASON_APIC_ACCESS:
7761                 return nested_cpu_has2(vmcs12,
7762                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7763         case EXIT_REASON_APIC_WRITE:
7764         case EXIT_REASON_EOI_INDUCED:
7765                 /* apic_write and eoi_induced should exit unconditionally. */
7766                 return true;
7767         case EXIT_REASON_EPT_VIOLATION:
7768                 /*
7769                  * L0 always deals with the EPT violation. If nested EPT is
7770                  * used, and the nested mmu code discovers that the address is
7771                  * missing in the guest EPT table (EPT12), the EPT violation
7772                  * will be injected with nested_ept_inject_page_fault()
7773                  */
7774                 return false;
7775         case EXIT_REASON_EPT_MISCONFIG:
7776                 /*
7777                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7778                  * table (shadow on EPT) or a merged EPT table that L0 built
7779                  * (EPT on EPT). So any problems with the structure of the
7780                  * table is L0's fault.
7781                  */
7782                 return false;
7783         case EXIT_REASON_WBINVD:
7784                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7785         case EXIT_REASON_XSETBV:
7786                 return true;
7787         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7788                 /*
7789                  * This should never happen, since it is not possible to
7790                  * set XSS to a non-zero value---neither in L1 nor in L2.
7791                  * If if it were, XSS would have to be checked against
7792                  * the XSS exit bitmap in vmcs12.
7793                  */
7794                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7795         case EXIT_REASON_PCOMMIT:
7796                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7797         default:
7798                 return true;
7799         }
7800 }
7801
7802 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7803 {
7804         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7805         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7806 }
7807
7808 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7809 {
7810         struct page *pml_pg;
7811
7812         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7813         if (!pml_pg)
7814                 return -ENOMEM;
7815
7816         vmx->pml_pg = pml_pg;
7817
7818         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7819         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7820
7821         return 0;
7822 }
7823
7824 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7825 {
7826         if (vmx->pml_pg) {
7827                 __free_page(vmx->pml_pg);
7828                 vmx->pml_pg = NULL;
7829         }
7830 }
7831
7832 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7833 {
7834         struct vcpu_vmx *vmx = to_vmx(vcpu);
7835         u64 *pml_buf;
7836         u16 pml_idx;
7837
7838         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7839
7840         /* Do nothing if PML buffer is empty */
7841         if (pml_idx == (PML_ENTITY_NUM - 1))
7842                 return;
7843
7844         /* PML index always points to next available PML buffer entity */
7845         if (pml_idx >= PML_ENTITY_NUM)
7846                 pml_idx = 0;
7847         else
7848                 pml_idx++;
7849
7850         pml_buf = page_address(vmx->pml_pg);
7851         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7852                 u64 gpa;
7853
7854                 gpa = pml_buf[pml_idx];
7855                 WARN_ON(gpa & (PAGE_SIZE - 1));
7856                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7857         }
7858
7859         /* reset PML index */
7860         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7861 }
7862
7863 /*
7864  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7865  * Called before reporting dirty_bitmap to userspace.
7866  */
7867 static void kvm_flush_pml_buffers(struct kvm *kvm)
7868 {
7869         int i;
7870         struct kvm_vcpu *vcpu;
7871         /*
7872          * We only need to kick vcpu out of guest mode here, as PML buffer
7873          * is flushed at beginning of all VMEXITs, and it's obvious that only
7874          * vcpus running in guest are possible to have unflushed GPAs in PML
7875          * buffer.
7876          */
7877         kvm_for_each_vcpu(i, vcpu, kvm)
7878                 kvm_vcpu_kick(vcpu);
7879 }
7880
7881 static void vmx_dump_sel(char *name, uint32_t sel)
7882 {
7883         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7884                name, vmcs_read32(sel),
7885                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7886                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7887                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7888 }
7889
7890 static void vmx_dump_dtsel(char *name, uint32_t limit)
7891 {
7892         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7893                name, vmcs_read32(limit),
7894                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7895 }
7896
7897 static void dump_vmcs(void)
7898 {
7899         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7900         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7901         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7902         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7903         u32 secondary_exec_control = 0;
7904         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7905         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7906         int i, n;
7907
7908         if (cpu_has_secondary_exec_ctrls())
7909                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7910
7911         pr_err("*** Guest State ***\n");
7912         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7913                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7914                vmcs_readl(CR0_GUEST_HOST_MASK));
7915         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7916                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7917         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7918         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7919             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7920         {
7921                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7922                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7923                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7924                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7925         }
7926         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7927                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7928         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7929                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7930         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7931                vmcs_readl(GUEST_SYSENTER_ESP),
7932                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7933         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7934         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7935         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7936         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7937         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7938         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7939         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7940         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7941         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7942         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7943         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7944             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7945                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7946                        efer, vmcs_readl(GUEST_IA32_PAT));
7947         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7948                vmcs_readl(GUEST_IA32_DEBUGCTL),
7949                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7950         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7951                 pr_err("PerfGlobCtl = 0x%016lx\n",
7952                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7953         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7954                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7955         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7956                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7957                vmcs_read32(GUEST_ACTIVITY_STATE));
7958         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7959                 pr_err("InterruptStatus = %04x\n",
7960                        vmcs_read16(GUEST_INTR_STATUS));
7961
7962         pr_err("*** Host State ***\n");
7963         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7964                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7965         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7966                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7967                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7968                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7969                vmcs_read16(HOST_TR_SELECTOR));
7970         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7971                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7972                vmcs_readl(HOST_TR_BASE));
7973         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7974                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7975         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7976                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7977                vmcs_readl(HOST_CR4));
7978         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7979                vmcs_readl(HOST_IA32_SYSENTER_ESP),
7980                vmcs_read32(HOST_IA32_SYSENTER_CS),
7981                vmcs_readl(HOST_IA32_SYSENTER_EIP));
7982         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7983                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
7984                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7985         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7986                 pr_err("PerfGlobCtl = 0x%016lx\n",
7987                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7988
7989         pr_err("*** Control State ***\n");
7990         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7991                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7992         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7993         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7994                vmcs_read32(EXCEPTION_BITMAP),
7995                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7996                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7997         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7998                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7999                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8000                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8001         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8002                vmcs_read32(VM_EXIT_INTR_INFO),
8003                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8004                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8005         pr_err("        reason=%08x qualification=%016lx\n",
8006                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8007         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8008                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8009                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8010         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8011         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8012                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8013         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8014                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8015         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8016                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8017         n = vmcs_read32(CR3_TARGET_COUNT);
8018         for (i = 0; i + 1 < n; i += 4)
8019                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8020                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8021                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8022         if (i < n)
8023                 pr_err("CR3 target%u=%016lx\n",
8024                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8025         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8026                 pr_err("PLE Gap=%08x Window=%08x\n",
8027                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8028         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8029                 pr_err("Virtual processor ID = 0x%04x\n",
8030                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8031 }
8032
8033 /*
8034  * The guest has exited.  See if we can fix it or if we need userspace
8035  * assistance.
8036  */
8037 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8038 {
8039         struct vcpu_vmx *vmx = to_vmx(vcpu);
8040         u32 exit_reason = vmx->exit_reason;
8041         u32 vectoring_info = vmx->idt_vectoring_info;
8042
8043         /*
8044          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8045          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8046          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8047          * mode as if vcpus is in root mode, the PML buffer must has been
8048          * flushed already.
8049          */
8050         if (enable_pml)
8051                 vmx_flush_pml_buffer(vcpu);
8052
8053         /* If guest state is invalid, start emulating */
8054         if (vmx->emulation_required)
8055                 return handle_invalid_guest_state(vcpu);
8056
8057         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8058                 nested_vmx_vmexit(vcpu, exit_reason,
8059                                   vmcs_read32(VM_EXIT_INTR_INFO),
8060                                   vmcs_readl(EXIT_QUALIFICATION));
8061                 return 1;
8062         }
8063
8064         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8065                 dump_vmcs();
8066                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8067                 vcpu->run->fail_entry.hardware_entry_failure_reason
8068                         = exit_reason;
8069                 return 0;
8070         }
8071
8072         if (unlikely(vmx->fail)) {
8073                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8074                 vcpu->run->fail_entry.hardware_entry_failure_reason
8075                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8076                 return 0;
8077         }
8078
8079         /*
8080          * Note:
8081          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8082          * delivery event since it indicates guest is accessing MMIO.
8083          * The vm-exit can be triggered again after return to guest that
8084          * will cause infinite loop.
8085          */
8086         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8087                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8088                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8089                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8090                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8091                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8092                 vcpu->run->internal.ndata = 2;
8093                 vcpu->run->internal.data[0] = vectoring_info;
8094                 vcpu->run->internal.data[1] = exit_reason;
8095                 return 0;
8096         }
8097
8098         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8099             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8100                                         get_vmcs12(vcpu))))) {
8101                 if (vmx_interrupt_allowed(vcpu)) {
8102                         vmx->soft_vnmi_blocked = 0;
8103                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8104                            vcpu->arch.nmi_pending) {
8105                         /*
8106                          * This CPU don't support us in finding the end of an
8107                          * NMI-blocked window if the guest runs with IRQs
8108                          * disabled. So we pull the trigger after 1 s of
8109                          * futile waiting, but inform the user about this.
8110                          */
8111                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8112                                "state on VCPU %d after 1 s timeout\n",
8113                                __func__, vcpu->vcpu_id);
8114                         vmx->soft_vnmi_blocked = 0;
8115                 }
8116         }
8117
8118         if (exit_reason < kvm_vmx_max_exit_handlers
8119             && kvm_vmx_exit_handlers[exit_reason])
8120                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8121         else {
8122                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8123                 kvm_queue_exception(vcpu, UD_VECTOR);
8124                 return 1;
8125         }
8126 }
8127
8128 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8129 {
8130         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8131
8132         if (is_guest_mode(vcpu) &&
8133                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8134                 return;
8135
8136         if (irr == -1 || tpr < irr) {
8137                 vmcs_write32(TPR_THRESHOLD, 0);
8138                 return;
8139         }
8140
8141         vmcs_write32(TPR_THRESHOLD, irr);
8142 }
8143
8144 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8145 {
8146         u32 sec_exec_control;
8147
8148         /*
8149          * There is not point to enable virtualize x2apic without enable
8150          * apicv
8151          */
8152         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8153                                 !vmx_cpu_uses_apicv(vcpu))
8154                 return;
8155
8156         if (!cpu_need_tpr_shadow(vcpu))
8157                 return;
8158
8159         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8160
8161         if (set) {
8162                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8163                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8164         } else {
8165                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8166                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8167         }
8168         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8169
8170         vmx_set_msr_bitmap(vcpu);
8171 }
8172
8173 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8174 {
8175         struct vcpu_vmx *vmx = to_vmx(vcpu);
8176
8177         /*
8178          * Currently we do not handle the nested case where L2 has an
8179          * APIC access page of its own; that page is still pinned.
8180          * Hence, we skip the case where the VCPU is in guest mode _and_
8181          * L1 prepared an APIC access page for L2.
8182          *
8183          * For the case where L1 and L2 share the same APIC access page
8184          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8185          * in the vmcs12), this function will only update either the vmcs01
8186          * or the vmcs02.  If the former, the vmcs02 will be updated by
8187          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8188          * the next L2->L1 exit.
8189          */
8190         if (!is_guest_mode(vcpu) ||
8191             !nested_cpu_has2(vmx->nested.current_vmcs12,
8192                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8193                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8194 }
8195
8196 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8197 {
8198         u16 status;
8199         u8 old;
8200
8201         if (isr == -1)
8202                 isr = 0;
8203
8204         status = vmcs_read16(GUEST_INTR_STATUS);
8205         old = status >> 8;
8206         if (isr != old) {
8207                 status &= 0xff;
8208                 status |= isr << 8;
8209                 vmcs_write16(GUEST_INTR_STATUS, status);
8210         }
8211 }
8212
8213 static void vmx_set_rvi(int vector)
8214 {
8215         u16 status;
8216         u8 old;
8217
8218         if (vector == -1)
8219                 vector = 0;
8220
8221         status = vmcs_read16(GUEST_INTR_STATUS);
8222         old = (u8)status & 0xff;
8223         if ((u8)vector != old) {
8224                 status &= ~0xff;
8225                 status |= (u8)vector;
8226                 vmcs_write16(GUEST_INTR_STATUS, status);
8227         }
8228 }
8229
8230 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8231 {
8232         if (!is_guest_mode(vcpu)) {
8233                 vmx_set_rvi(max_irr);
8234                 return;
8235         }
8236
8237         if (max_irr == -1)
8238                 return;
8239
8240         /*
8241          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8242          * handles it.
8243          */
8244         if (nested_exit_on_intr(vcpu))
8245                 return;
8246
8247         /*
8248          * Else, fall back to pre-APICv interrupt injection since L2
8249          * is run without virtual interrupt delivery.
8250          */
8251         if (!kvm_event_needs_reinjection(vcpu) &&
8252             vmx_interrupt_allowed(vcpu)) {
8253                 kvm_queue_interrupt(vcpu, max_irr, false);
8254                 vmx_inject_irq(vcpu);
8255         }
8256 }
8257
8258 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8259 {
8260         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8261         if (!vmx_cpu_uses_apicv(vcpu))
8262                 return;
8263
8264         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8265         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8266         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8267         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8268 }
8269
8270 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8271 {
8272         u32 exit_intr_info;
8273
8274         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8275               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8276                 return;
8277
8278         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8279         exit_intr_info = vmx->exit_intr_info;
8280
8281         /* Handle machine checks before interrupts are enabled */
8282         if (is_machine_check(exit_intr_info))
8283                 kvm_machine_check();
8284
8285         /* We need to handle NMIs before interrupts are enabled */
8286         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8287             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8288                 kvm_before_handle_nmi(&vmx->vcpu);
8289                 asm("int $2");
8290                 kvm_after_handle_nmi(&vmx->vcpu);
8291         }
8292 }
8293
8294 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8295 {
8296         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8297
8298         /*
8299          * If external interrupt exists, IF bit is set in rflags/eflags on the
8300          * interrupt stack frame, and interrupt will be enabled on a return
8301          * from interrupt handler.
8302          */
8303         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8304                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8305                 unsigned int vector;
8306                 unsigned long entry;
8307                 gate_desc *desc;
8308                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8309 #ifdef CONFIG_X86_64
8310                 unsigned long tmp;
8311 #endif
8312
8313                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8314                 desc = (gate_desc *)vmx->host_idt_base + vector;
8315                 entry = gate_offset(*desc);
8316                 asm volatile(
8317 #ifdef CONFIG_X86_64
8318                         "mov %%" _ASM_SP ", %[sp]\n\t"
8319                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8320                         "push $%c[ss]\n\t"
8321                         "push %[sp]\n\t"
8322 #endif
8323                         "pushf\n\t"
8324                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8325                         __ASM_SIZE(push) " $%c[cs]\n\t"
8326                         "call *%[entry]\n\t"
8327                         :
8328 #ifdef CONFIG_X86_64
8329                         [sp]"=&r"(tmp)
8330 #endif
8331                         :
8332                         [entry]"r"(entry),
8333                         [ss]"i"(__KERNEL_DS),
8334                         [cs]"i"(__KERNEL_CS)
8335                         );
8336         } else
8337                 local_irq_enable();
8338 }
8339
8340 static bool vmx_has_high_real_mode_segbase(void)
8341 {
8342         return enable_unrestricted_guest || emulate_invalid_guest_state;
8343 }
8344
8345 static bool vmx_mpx_supported(void)
8346 {
8347         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8348                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8349 }
8350
8351 static bool vmx_xsaves_supported(void)
8352 {
8353         return vmcs_config.cpu_based_2nd_exec_ctrl &
8354                 SECONDARY_EXEC_XSAVES;
8355 }
8356
8357 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8358 {
8359         u32 exit_intr_info;
8360         bool unblock_nmi;
8361         u8 vector;
8362         bool idtv_info_valid;
8363
8364         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8365
8366         if (cpu_has_virtual_nmis()) {
8367                 if (vmx->nmi_known_unmasked)
8368                         return;
8369                 /*
8370                  * Can't use vmx->exit_intr_info since we're not sure what
8371                  * the exit reason is.
8372                  */
8373                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8374                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8375                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8376                 /*
8377                  * SDM 3: 27.7.1.2 (September 2008)
8378                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8379                  * a guest IRET fault.
8380                  * SDM 3: 23.2.2 (September 2008)
8381                  * Bit 12 is undefined in any of the following cases:
8382                  *  If the VM exit sets the valid bit in the IDT-vectoring
8383                  *   information field.
8384                  *  If the VM exit is due to a double fault.
8385                  */
8386                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8387                     vector != DF_VECTOR && !idtv_info_valid)
8388                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8389                                       GUEST_INTR_STATE_NMI);
8390                 else
8391                         vmx->nmi_known_unmasked =
8392                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8393                                   & GUEST_INTR_STATE_NMI);
8394         } else if (unlikely(vmx->soft_vnmi_blocked))
8395                 vmx->vnmi_blocked_time +=
8396                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8397 }
8398
8399 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8400                                       u32 idt_vectoring_info,
8401                                       int instr_len_field,
8402                                       int error_code_field)
8403 {
8404         u8 vector;
8405         int type;
8406         bool idtv_info_valid;
8407
8408         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8409
8410         vcpu->arch.nmi_injected = false;
8411         kvm_clear_exception_queue(vcpu);
8412         kvm_clear_interrupt_queue(vcpu);
8413
8414         if (!idtv_info_valid)
8415                 return;
8416
8417         kvm_make_request(KVM_REQ_EVENT, vcpu);
8418
8419         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8420         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8421
8422         switch (type) {
8423         case INTR_TYPE_NMI_INTR:
8424                 vcpu->arch.nmi_injected = true;
8425                 /*
8426                  * SDM 3: 27.7.1.2 (September 2008)
8427                  * Clear bit "block by NMI" before VM entry if a NMI
8428                  * delivery faulted.
8429                  */
8430                 vmx_set_nmi_mask(vcpu, false);
8431                 break;
8432         case INTR_TYPE_SOFT_EXCEPTION:
8433                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8434                 /* fall through */
8435         case INTR_TYPE_HARD_EXCEPTION:
8436                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8437                         u32 err = vmcs_read32(error_code_field);
8438                         kvm_requeue_exception_e(vcpu, vector, err);
8439                 } else
8440                         kvm_requeue_exception(vcpu, vector);
8441                 break;
8442         case INTR_TYPE_SOFT_INTR:
8443                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8444                 /* fall through */
8445         case INTR_TYPE_EXT_INTR:
8446                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8447                 break;
8448         default:
8449                 break;
8450         }
8451 }
8452
8453 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8454 {
8455         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8456                                   VM_EXIT_INSTRUCTION_LEN,
8457                                   IDT_VECTORING_ERROR_CODE);
8458 }
8459
8460 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8461 {
8462         __vmx_complete_interrupts(vcpu,
8463                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8464                                   VM_ENTRY_INSTRUCTION_LEN,
8465                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8466
8467         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8468 }
8469
8470 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8471 {
8472         int i, nr_msrs;
8473         struct perf_guest_switch_msr *msrs;
8474
8475         msrs = perf_guest_get_msrs(&nr_msrs);
8476
8477         if (!msrs)
8478                 return;
8479
8480         for (i = 0; i < nr_msrs; i++)
8481                 if (msrs[i].host == msrs[i].guest)
8482                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8483                 else
8484                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8485                                         msrs[i].host);
8486 }
8487
8488 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8489 {
8490         struct vcpu_vmx *vmx = to_vmx(vcpu);
8491         unsigned long debugctlmsr, cr4;
8492
8493         /* Record the guest's net vcpu time for enforced NMI injections. */
8494         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8495                 vmx->entry_time = ktime_get();
8496
8497         /* Don't enter VMX if guest state is invalid, let the exit handler
8498            start emulation until we arrive back to a valid state */
8499         if (vmx->emulation_required)
8500                 return;
8501
8502         if (vmx->ple_window_dirty) {
8503                 vmx->ple_window_dirty = false;
8504                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8505         }
8506
8507         if (vmx->nested.sync_shadow_vmcs) {
8508                 copy_vmcs12_to_shadow(vmx);
8509                 vmx->nested.sync_shadow_vmcs = false;
8510         }
8511
8512         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8513                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8514         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8515                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8516
8517         cr4 = cr4_read_shadow();
8518         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8519                 vmcs_writel(HOST_CR4, cr4);
8520                 vmx->host_state.vmcs_host_cr4 = cr4;
8521         }
8522
8523         /* When single-stepping over STI and MOV SS, we must clear the
8524          * corresponding interruptibility bits in the guest state. Otherwise
8525          * vmentry fails as it then expects bit 14 (BS) in pending debug
8526          * exceptions being set, but that's not correct for the guest debugging
8527          * case. */
8528         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8529                 vmx_set_interrupt_shadow(vcpu, 0);
8530
8531         atomic_switch_perf_msrs(vmx);
8532         debugctlmsr = get_debugctlmsr();
8533
8534         vmx->__launched = vmx->loaded_vmcs->launched;
8535         asm(
8536                 /* Store host registers */
8537                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8538                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8539                 "push %%" _ASM_CX " \n\t"
8540                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8541                 "je 1f \n\t"
8542                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8543                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8544                 "1: \n\t"
8545                 /* Reload cr2 if changed */
8546                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8547                 "mov %%cr2, %%" _ASM_DX " \n\t"
8548                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8549                 "je 2f \n\t"
8550                 "mov %%" _ASM_AX", %%cr2 \n\t"
8551                 "2: \n\t"
8552                 /* Check if vmlaunch of vmresume is needed */
8553                 "cmpl $0, %c[launched](%0) \n\t"
8554                 /* Load guest registers.  Don't clobber flags. */
8555                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8556                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8557                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8558                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8559                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8560                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8561 #ifdef CONFIG_X86_64
8562                 "mov %c[r8](%0),  %%r8  \n\t"
8563                 "mov %c[r9](%0),  %%r9  \n\t"
8564                 "mov %c[r10](%0), %%r10 \n\t"
8565                 "mov %c[r11](%0), %%r11 \n\t"
8566                 "mov %c[r12](%0), %%r12 \n\t"
8567                 "mov %c[r13](%0), %%r13 \n\t"
8568                 "mov %c[r14](%0), %%r14 \n\t"
8569                 "mov %c[r15](%0), %%r15 \n\t"
8570 #endif
8571                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8572
8573                 /* Enter guest mode */
8574                 "jne 1f \n\t"
8575                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8576                 "jmp 2f \n\t"
8577                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8578                 "2: "
8579                 /* Save guest registers, load host registers, keep flags */
8580                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8581                 "pop %0 \n\t"
8582                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8583                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8584                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8585                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8586                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8587                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8588                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8589 #ifdef CONFIG_X86_64
8590                 "mov %%r8,  %c[r8](%0) \n\t"
8591                 "mov %%r9,  %c[r9](%0) \n\t"
8592                 "mov %%r10, %c[r10](%0) \n\t"
8593                 "mov %%r11, %c[r11](%0) \n\t"
8594                 "mov %%r12, %c[r12](%0) \n\t"
8595                 "mov %%r13, %c[r13](%0) \n\t"
8596                 "mov %%r14, %c[r14](%0) \n\t"
8597                 "mov %%r15, %c[r15](%0) \n\t"
8598 #endif
8599                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8600                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8601
8602                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8603                 "setbe %c[fail](%0) \n\t"
8604                 ".pushsection .rodata \n\t"
8605                 ".global vmx_return \n\t"
8606                 "vmx_return: " _ASM_PTR " 2b \n\t"
8607                 ".popsection"
8608               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8609                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8610                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8611                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8612                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8613                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8614                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8615                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8616                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8617                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8618                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8619 #ifdef CONFIG_X86_64
8620                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8621                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8622                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8623                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8624                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8625                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8626                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8627                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8628 #endif
8629                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8630                 [wordsize]"i"(sizeof(ulong))
8631               : "cc", "memory"
8632 #ifdef CONFIG_X86_64
8633                 , "rax", "rbx", "rdi", "rsi"
8634                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8635 #else
8636                 , "eax", "ebx", "edi", "esi"
8637 #endif
8638               );
8639
8640         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8641         if (debugctlmsr)
8642                 update_debugctlmsr(debugctlmsr);
8643
8644 #ifndef CONFIG_X86_64
8645         /*
8646          * The sysexit path does not restore ds/es, so we must set them to
8647          * a reasonable value ourselves.
8648          *
8649          * We can't defer this to vmx_load_host_state() since that function
8650          * may be executed in interrupt context, which saves and restore segments
8651          * around it, nullifying its effect.
8652          */
8653         loadsegment(ds, __USER_DS);
8654         loadsegment(es, __USER_DS);
8655 #endif
8656
8657         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8658                                   | (1 << VCPU_EXREG_RFLAGS)
8659                                   | (1 << VCPU_EXREG_PDPTR)
8660                                   | (1 << VCPU_EXREG_SEGMENTS)
8661                                   | (1 << VCPU_EXREG_CR3));
8662         vcpu->arch.regs_dirty = 0;
8663
8664         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8665
8666         vmx->loaded_vmcs->launched = 1;
8667
8668         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8669         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8670
8671         /*
8672          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8673          * we did not inject a still-pending event to L1 now because of
8674          * nested_run_pending, we need to re-enable this bit.
8675          */
8676         if (vmx->nested.nested_run_pending)
8677                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8678
8679         vmx->nested.nested_run_pending = 0;
8680
8681         vmx_complete_atomic_exit(vmx);
8682         vmx_recover_nmi_blocking(vmx);
8683         vmx_complete_interrupts(vmx);
8684 }
8685
8686 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8687 {
8688         struct vcpu_vmx *vmx = to_vmx(vcpu);
8689         int cpu;
8690
8691         if (vmx->loaded_vmcs == &vmx->vmcs01)
8692                 return;
8693
8694         cpu = get_cpu();
8695         vmx->loaded_vmcs = &vmx->vmcs01;
8696         vmx_vcpu_put(vcpu);
8697         vmx_vcpu_load(vcpu, cpu);
8698         vcpu->cpu = cpu;
8699         put_cpu();
8700 }
8701
8702 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8703 {
8704         struct vcpu_vmx *vmx = to_vmx(vcpu);
8705
8706         if (enable_pml)
8707                 vmx_destroy_pml_buffer(vmx);
8708         free_vpid(vmx->vpid);
8709         leave_guest_mode(vcpu);
8710         vmx_load_vmcs01(vcpu);
8711         free_nested(vmx);
8712         free_loaded_vmcs(vmx->loaded_vmcs);
8713         kfree(vmx->guest_msrs);
8714         kvm_vcpu_uninit(vcpu);
8715         kmem_cache_free(kvm_vcpu_cache, vmx);
8716 }
8717
8718 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8719 {
8720         int err;
8721         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8722         int cpu;
8723
8724         if (!vmx)
8725                 return ERR_PTR(-ENOMEM);
8726
8727         vmx->vpid = allocate_vpid();
8728
8729         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8730         if (err)
8731                 goto free_vcpu;
8732
8733         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8734         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8735                      > PAGE_SIZE);
8736
8737         err = -ENOMEM;
8738         if (!vmx->guest_msrs) {
8739                 goto uninit_vcpu;
8740         }
8741
8742         vmx->loaded_vmcs = &vmx->vmcs01;
8743         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8744         if (!vmx->loaded_vmcs->vmcs)
8745                 goto free_msrs;
8746         if (!vmm_exclusive)
8747                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8748         loaded_vmcs_init(vmx->loaded_vmcs);
8749         if (!vmm_exclusive)
8750                 kvm_cpu_vmxoff();
8751
8752         cpu = get_cpu();
8753         vmx_vcpu_load(&vmx->vcpu, cpu);
8754         vmx->vcpu.cpu = cpu;
8755         err = vmx_vcpu_setup(vmx);
8756         vmx_vcpu_put(&vmx->vcpu);
8757         put_cpu();
8758         if (err)
8759                 goto free_vmcs;
8760         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8761                 err = alloc_apic_access_page(kvm);
8762                 if (err)
8763                         goto free_vmcs;
8764         }
8765
8766         if (enable_ept) {
8767                 if (!kvm->arch.ept_identity_map_addr)
8768                         kvm->arch.ept_identity_map_addr =
8769                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8770                 err = init_rmode_identity_map(kvm);
8771                 if (err)
8772                         goto free_vmcs;
8773         }
8774
8775         if (nested) {
8776                 nested_vmx_setup_ctls_msrs(vmx);
8777                 vmx->nested.vpid02 = allocate_vpid();
8778         }
8779
8780         vmx->nested.posted_intr_nv = -1;
8781         vmx->nested.current_vmptr = -1ull;
8782         vmx->nested.current_vmcs12 = NULL;
8783
8784         /*
8785          * If PML is turned on, failure on enabling PML just results in failure
8786          * of creating the vcpu, therefore we can simplify PML logic (by
8787          * avoiding dealing with cases, such as enabling PML partially on vcpus
8788          * for the guest, etc.
8789          */
8790         if (enable_pml) {
8791                 err = vmx_create_pml_buffer(vmx);
8792                 if (err)
8793                         goto free_vmcs;
8794         }
8795
8796         return &vmx->vcpu;
8797
8798 free_vmcs:
8799         free_vpid(vmx->nested.vpid02);
8800         free_loaded_vmcs(vmx->loaded_vmcs);
8801 free_msrs:
8802         kfree(vmx->guest_msrs);
8803 uninit_vcpu:
8804         kvm_vcpu_uninit(&vmx->vcpu);
8805 free_vcpu:
8806         free_vpid(vmx->vpid);
8807         kmem_cache_free(kvm_vcpu_cache, vmx);
8808         return ERR_PTR(err);
8809 }
8810
8811 static void __init vmx_check_processor_compat(void *rtn)
8812 {
8813         struct vmcs_config vmcs_conf;
8814
8815         *(int *)rtn = 0;
8816         if (setup_vmcs_config(&vmcs_conf) < 0)
8817                 *(int *)rtn = -EIO;
8818         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8819                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8820                                 smp_processor_id());
8821                 *(int *)rtn = -EIO;
8822         }
8823 }
8824
8825 static int get_ept_level(void)
8826 {
8827         return VMX_EPT_DEFAULT_GAW + 1;
8828 }
8829
8830 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8831 {
8832         u8 cache;
8833         u64 ipat = 0;
8834
8835         /* For VT-d and EPT combination
8836          * 1. MMIO: always map as UC
8837          * 2. EPT with VT-d:
8838          *   a. VT-d without snooping control feature: can't guarantee the
8839          *      result, try to trust guest.
8840          *   b. VT-d with snooping control feature: snooping control feature of
8841          *      VT-d engine can guarantee the cache correctness. Just set it
8842          *      to WB to keep consistent with host. So the same as item 3.
8843          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8844          *    consistent with host MTRR
8845          */
8846         if (is_mmio) {
8847                 cache = MTRR_TYPE_UNCACHABLE;
8848                 goto exit;
8849         }
8850
8851         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8852                 ipat = VMX_EPT_IPAT_BIT;
8853                 cache = MTRR_TYPE_WRBACK;
8854                 goto exit;
8855         }
8856
8857         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8858                 ipat = VMX_EPT_IPAT_BIT;
8859                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8860                         cache = MTRR_TYPE_WRBACK;
8861                 else
8862                         cache = MTRR_TYPE_UNCACHABLE;
8863                 goto exit;
8864         }
8865
8866         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8867
8868 exit:
8869         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8870 }
8871
8872 static int vmx_get_lpage_level(void)
8873 {
8874         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8875                 return PT_DIRECTORY_LEVEL;
8876         else
8877                 /* For shadow and EPT supported 1GB page */
8878                 return PT_PDPE_LEVEL;
8879 }
8880
8881 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8882 {
8883         /*
8884          * These bits in the secondary execution controls field
8885          * are dynamic, the others are mostly based on the hypervisor
8886          * architecture and the guest's CPUID.  Do not touch the
8887          * dynamic bits.
8888          */
8889         u32 mask =
8890                 SECONDARY_EXEC_SHADOW_VMCS |
8891                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8892                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8893
8894         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8895
8896         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8897                      (new_ctl & ~mask) | (cur_ctl & mask));
8898 }
8899
8900 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8901 {
8902         struct kvm_cpuid_entry2 *best;
8903         struct vcpu_vmx *vmx = to_vmx(vcpu);
8904         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8905
8906         if (vmx_rdtscp_supported()) {
8907                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8908                 if (!rdtscp_enabled)
8909                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8910
8911                 if (nested) {
8912                         if (rdtscp_enabled)
8913                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8914                                         SECONDARY_EXEC_RDTSCP;
8915                         else
8916                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8917                                         ~SECONDARY_EXEC_RDTSCP;
8918                 }
8919         }
8920
8921         /* Exposing INVPCID only when PCID is exposed */
8922         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8923         if (vmx_invpcid_supported() &&
8924             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8925             !guest_cpuid_has_pcid(vcpu))) {
8926                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8927
8928                 if (best)
8929                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8930         }
8931
8932         vmcs_set_secondary_exec_control(secondary_exec_ctl);
8933
8934         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8935                 if (guest_cpuid_has_pcommit(vcpu))
8936                         vmx->nested.nested_vmx_secondary_ctls_high |=
8937                                 SECONDARY_EXEC_PCOMMIT;
8938                 else
8939                         vmx->nested.nested_vmx_secondary_ctls_high &=
8940                                 ~SECONDARY_EXEC_PCOMMIT;
8941         }
8942 }
8943
8944 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8945 {
8946         if (func == 1 && nested)
8947                 entry->ecx |= bit(X86_FEATURE_VMX);
8948 }
8949
8950 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8951                 struct x86_exception *fault)
8952 {
8953         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8954         u32 exit_reason;
8955
8956         if (fault->error_code & PFERR_RSVD_MASK)
8957                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8958         else
8959                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8960         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8961         vmcs12->guest_physical_address = fault->address;
8962 }
8963
8964 /* Callbacks for nested_ept_init_mmu_context: */
8965
8966 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8967 {
8968         /* return the page table to be shadowed - in our case, EPT12 */
8969         return get_vmcs12(vcpu)->ept_pointer;
8970 }
8971
8972 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8973 {
8974         WARN_ON(mmu_is_nested(vcpu));
8975         kvm_init_shadow_ept_mmu(vcpu,
8976                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8977                         VMX_EPT_EXECUTE_ONLY_BIT);
8978         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8979         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8980         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8981
8982         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8983 }
8984
8985 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8986 {
8987         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8988 }
8989
8990 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8991                                             u16 error_code)
8992 {
8993         bool inequality, bit;
8994
8995         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8996         inequality =
8997                 (error_code & vmcs12->page_fault_error_code_mask) !=
8998                  vmcs12->page_fault_error_code_match;
8999         return inequality ^ bit;
9000 }
9001
9002 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9003                 struct x86_exception *fault)
9004 {
9005         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9006
9007         WARN_ON(!is_guest_mode(vcpu));
9008
9009         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9010                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9011                                   vmcs_read32(VM_EXIT_INTR_INFO),
9012                                   vmcs_readl(EXIT_QUALIFICATION));
9013         else
9014                 kvm_inject_page_fault(vcpu, fault);
9015 }
9016
9017 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9018                                         struct vmcs12 *vmcs12)
9019 {
9020         struct vcpu_vmx *vmx = to_vmx(vcpu);
9021         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9022
9023         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9024                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9025                     vmcs12->apic_access_addr >> maxphyaddr)
9026                         return false;
9027
9028                 /*
9029                  * Translate L1 physical address to host physical
9030                  * address for vmcs02. Keep the page pinned, so this
9031                  * physical address remains valid. We keep a reference
9032                  * to it so we can release it later.
9033                  */
9034                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9035                         nested_release_page(vmx->nested.apic_access_page);
9036                 vmx->nested.apic_access_page =
9037                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9038         }
9039
9040         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9041                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9042                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9043                         return false;
9044
9045                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9046                         nested_release_page(vmx->nested.virtual_apic_page);
9047                 vmx->nested.virtual_apic_page =
9048                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9049
9050                 /*
9051                  * Failing the vm entry is _not_ what the processor does
9052                  * but it's basically the only possibility we have.
9053                  * We could still enter the guest if CR8 load exits are
9054                  * enabled, CR8 store exits are enabled, and virtualize APIC
9055                  * access is disabled; in this case the processor would never
9056                  * use the TPR shadow and we could simply clear the bit from
9057                  * the execution control.  But such a configuration is useless,
9058                  * so let's keep the code simple.
9059                  */
9060                 if (!vmx->nested.virtual_apic_page)
9061                         return false;
9062         }
9063
9064         if (nested_cpu_has_posted_intr(vmcs12)) {
9065                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9066                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9067                         return false;
9068
9069                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9070                         kunmap(vmx->nested.pi_desc_page);
9071                         nested_release_page(vmx->nested.pi_desc_page);
9072                 }
9073                 vmx->nested.pi_desc_page =
9074                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9075                 if (!vmx->nested.pi_desc_page)
9076                         return false;
9077
9078                 vmx->nested.pi_desc =
9079                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9080                 if (!vmx->nested.pi_desc) {
9081                         nested_release_page_clean(vmx->nested.pi_desc_page);
9082                         return false;
9083                 }
9084                 vmx->nested.pi_desc =
9085                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9086                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9087                         (PAGE_SIZE - 1)));
9088         }
9089
9090         return true;
9091 }
9092
9093 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9094 {
9095         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9096         struct vcpu_vmx *vmx = to_vmx(vcpu);
9097
9098         if (vcpu->arch.virtual_tsc_khz == 0)
9099                 return;
9100
9101         /* Make sure short timeouts reliably trigger an immediate vmexit.
9102          * hrtimer_start does not guarantee this. */
9103         if (preemption_timeout <= 1) {
9104                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9105                 return;
9106         }
9107
9108         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9109         preemption_timeout *= 1000000;
9110         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9111         hrtimer_start(&vmx->nested.preemption_timer,
9112                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9113 }
9114
9115 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9116                                                 struct vmcs12 *vmcs12)
9117 {
9118         int maxphyaddr;
9119         u64 addr;
9120
9121         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9122                 return 0;
9123
9124         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9125                 WARN_ON(1);
9126                 return -EINVAL;
9127         }
9128         maxphyaddr = cpuid_maxphyaddr(vcpu);
9129
9130         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9131            ((addr + PAGE_SIZE) >> maxphyaddr))
9132                 return -EINVAL;
9133
9134         return 0;
9135 }
9136
9137 /*
9138  * Merge L0's and L1's MSR bitmap, return false to indicate that
9139  * we do not use the hardware.
9140  */
9141 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9142                                                struct vmcs12 *vmcs12)
9143 {
9144         int msr;
9145         struct page *page;
9146         unsigned long *msr_bitmap;
9147
9148         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9149                 return false;
9150
9151         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9152         if (!page) {
9153                 WARN_ON(1);
9154                 return false;
9155         }
9156         msr_bitmap = (unsigned long *)kmap(page);
9157         if (!msr_bitmap) {
9158                 nested_release_page_clean(page);
9159                 WARN_ON(1);
9160                 return false;
9161         }
9162
9163         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9164                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9165                         for (msr = 0x800; msr <= 0x8ff; msr++)
9166                                 nested_vmx_disable_intercept_for_msr(
9167                                         msr_bitmap,
9168                                         vmx_msr_bitmap_nested,
9169                                         msr, MSR_TYPE_R);
9170                 /* TPR is allowed */
9171                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9172                                 vmx_msr_bitmap_nested,
9173                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9174                                 MSR_TYPE_R | MSR_TYPE_W);
9175                 if (nested_cpu_has_vid(vmcs12)) {
9176                         /* EOI and self-IPI are allowed */
9177                         nested_vmx_disable_intercept_for_msr(
9178                                 msr_bitmap,
9179                                 vmx_msr_bitmap_nested,
9180                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9181                                 MSR_TYPE_W);
9182                         nested_vmx_disable_intercept_for_msr(
9183                                 msr_bitmap,
9184                                 vmx_msr_bitmap_nested,
9185                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9186                                 MSR_TYPE_W);
9187                 }
9188         } else {
9189                 /*
9190                  * Enable reading intercept of all the x2apic
9191                  * MSRs. We should not rely on vmcs12 to do any
9192                  * optimizations here, it may have been modified
9193                  * by L1.
9194                  */
9195                 for (msr = 0x800; msr <= 0x8ff; msr++)
9196                         __vmx_enable_intercept_for_msr(
9197                                 vmx_msr_bitmap_nested,
9198                                 msr,
9199                                 MSR_TYPE_R);
9200
9201                 __vmx_enable_intercept_for_msr(
9202                                 vmx_msr_bitmap_nested,
9203                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9204                                 MSR_TYPE_W);
9205                 __vmx_enable_intercept_for_msr(
9206                                 vmx_msr_bitmap_nested,
9207                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9208                                 MSR_TYPE_W);
9209                 __vmx_enable_intercept_for_msr(
9210                                 vmx_msr_bitmap_nested,
9211                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9212                                 MSR_TYPE_W);
9213         }
9214         kunmap(page);
9215         nested_release_page_clean(page);
9216
9217         return true;
9218 }
9219
9220 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9221                                            struct vmcs12 *vmcs12)
9222 {
9223         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9224             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9225             !nested_cpu_has_vid(vmcs12) &&
9226             !nested_cpu_has_posted_intr(vmcs12))
9227                 return 0;
9228
9229         /*
9230          * If virtualize x2apic mode is enabled,
9231          * virtualize apic access must be disabled.
9232          */
9233         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9234             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9235                 return -EINVAL;
9236
9237         /*
9238          * If virtual interrupt delivery is enabled,
9239          * we must exit on external interrupts.
9240          */
9241         if (nested_cpu_has_vid(vmcs12) &&
9242            !nested_exit_on_intr(vcpu))
9243                 return -EINVAL;
9244
9245         /*
9246          * bits 15:8 should be zero in posted_intr_nv,
9247          * the descriptor address has been already checked
9248          * in nested_get_vmcs12_pages.
9249          */
9250         if (nested_cpu_has_posted_intr(vmcs12) &&
9251            (!nested_cpu_has_vid(vmcs12) ||
9252             !nested_exit_intr_ack_set(vcpu) ||
9253             vmcs12->posted_intr_nv & 0xff00))
9254                 return -EINVAL;
9255
9256         /* tpr shadow is needed by all apicv features. */
9257         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9258                 return -EINVAL;
9259
9260         return 0;
9261 }
9262
9263 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9264                                        unsigned long count_field,
9265                                        unsigned long addr_field)
9266 {
9267         int maxphyaddr;
9268         u64 count, addr;
9269
9270         if (vmcs12_read_any(vcpu, count_field, &count) ||
9271             vmcs12_read_any(vcpu, addr_field, &addr)) {
9272                 WARN_ON(1);
9273                 return -EINVAL;
9274         }
9275         if (count == 0)
9276                 return 0;
9277         maxphyaddr = cpuid_maxphyaddr(vcpu);
9278         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9279             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9280                 pr_warn_ratelimited(
9281                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9282                         addr_field, maxphyaddr, count, addr);
9283                 return -EINVAL;
9284         }
9285         return 0;
9286 }
9287
9288 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9289                                                 struct vmcs12 *vmcs12)
9290 {
9291         if (vmcs12->vm_exit_msr_load_count == 0 &&
9292             vmcs12->vm_exit_msr_store_count == 0 &&
9293             vmcs12->vm_entry_msr_load_count == 0)
9294                 return 0; /* Fast path */
9295         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9296                                         VM_EXIT_MSR_LOAD_ADDR) ||
9297             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9298                                         VM_EXIT_MSR_STORE_ADDR) ||
9299             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9300                                         VM_ENTRY_MSR_LOAD_ADDR))
9301                 return -EINVAL;
9302         return 0;
9303 }
9304
9305 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9306                                        struct vmx_msr_entry *e)
9307 {
9308         /* x2APIC MSR accesses are not allowed */
9309         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9310                 return -EINVAL;
9311         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9312             e->index == MSR_IA32_UCODE_REV)
9313                 return -EINVAL;
9314         if (e->reserved != 0)
9315                 return -EINVAL;
9316         return 0;
9317 }
9318
9319 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9320                                      struct vmx_msr_entry *e)
9321 {
9322         if (e->index == MSR_FS_BASE ||
9323             e->index == MSR_GS_BASE ||
9324             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9325             nested_vmx_msr_check_common(vcpu, e))
9326                 return -EINVAL;
9327         return 0;
9328 }
9329
9330 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9331                                       struct vmx_msr_entry *e)
9332 {
9333         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9334             nested_vmx_msr_check_common(vcpu, e))
9335                 return -EINVAL;
9336         return 0;
9337 }
9338
9339 /*
9340  * Load guest's/host's msr at nested entry/exit.
9341  * return 0 for success, entry index for failure.
9342  */
9343 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9344 {
9345         u32 i;
9346         struct vmx_msr_entry e;
9347         struct msr_data msr;
9348
9349         msr.host_initiated = false;
9350         for (i = 0; i < count; i++) {
9351                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9352                                         &e, sizeof(e))) {
9353                         pr_warn_ratelimited(
9354                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9355                                 __func__, i, gpa + i * sizeof(e));
9356                         goto fail;
9357                 }
9358                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9359                         pr_warn_ratelimited(
9360                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9361                                 __func__, i, e.index, e.reserved);
9362                         goto fail;
9363                 }
9364                 msr.index = e.index;
9365                 msr.data = e.value;
9366                 if (kvm_set_msr(vcpu, &msr)) {
9367                         pr_warn_ratelimited(
9368                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9369                                 __func__, i, e.index, e.value);
9370                         goto fail;
9371                 }
9372         }
9373         return 0;
9374 fail:
9375         return i + 1;
9376 }
9377
9378 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9379 {
9380         u32 i;
9381         struct vmx_msr_entry e;
9382
9383         for (i = 0; i < count; i++) {
9384                 struct msr_data msr_info;
9385                 if (kvm_vcpu_read_guest(vcpu,
9386                                         gpa + i * sizeof(e),
9387                                         &e, 2 * sizeof(u32))) {
9388                         pr_warn_ratelimited(
9389                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9390                                 __func__, i, gpa + i * sizeof(e));
9391                         return -EINVAL;
9392                 }
9393                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9394                         pr_warn_ratelimited(
9395                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9396                                 __func__, i, e.index, e.reserved);
9397                         return -EINVAL;
9398                 }
9399                 msr_info.host_initiated = false;
9400                 msr_info.index = e.index;
9401                 if (kvm_get_msr(vcpu, &msr_info)) {
9402                         pr_warn_ratelimited(
9403                                 "%s cannot read MSR (%u, 0x%x)\n",
9404                                 __func__, i, e.index);
9405                         return -EINVAL;
9406                 }
9407                 if (kvm_vcpu_write_guest(vcpu,
9408                                          gpa + i * sizeof(e) +
9409                                              offsetof(struct vmx_msr_entry, value),
9410                                          &msr_info.data, sizeof(msr_info.data))) {
9411                         pr_warn_ratelimited(
9412                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9413                                 __func__, i, e.index, msr_info.data);
9414                         return -EINVAL;
9415                 }
9416         }
9417         return 0;
9418 }
9419
9420 /*
9421  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9422  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9423  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9424  * guest in a way that will both be appropriate to L1's requests, and our
9425  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9426  * function also has additional necessary side-effects, like setting various
9427  * vcpu->arch fields.
9428  */
9429 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9430 {
9431         struct vcpu_vmx *vmx = to_vmx(vcpu);
9432         u32 exec_control;
9433
9434         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9435         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9436         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9437         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9438         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9439         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9440         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9441         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9442         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9443         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9444         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9445         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9446         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9447         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9448         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9449         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9450         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9451         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9452         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9453         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9454         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9455         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9456         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9457         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9458         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9459         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9460         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9461         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9462         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9463         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9464         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9465         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9466         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9467         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9468         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9469         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9470
9471         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9472                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9473                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9474         } else {
9475                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9476                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9477         }
9478         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9479                 vmcs12->vm_entry_intr_info_field);
9480         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9481                 vmcs12->vm_entry_exception_error_code);
9482         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9483                 vmcs12->vm_entry_instruction_len);
9484         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9485                 vmcs12->guest_interruptibility_info);
9486         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9487         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9488         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9489                 vmcs12->guest_pending_dbg_exceptions);
9490         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9491         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9492
9493         if (nested_cpu_has_xsaves(vmcs12))
9494                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9495         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9496
9497         exec_control = vmcs12->pin_based_vm_exec_control;
9498         exec_control |= vmcs_config.pin_based_exec_ctrl;
9499         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9500
9501         if (nested_cpu_has_posted_intr(vmcs12)) {
9502                 /*
9503                  * Note that we use L0's vector here and in
9504                  * vmx_deliver_nested_posted_interrupt.
9505                  */
9506                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9507                 vmx->nested.pi_pending = false;
9508                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9509                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9510                         page_to_phys(vmx->nested.pi_desc_page) +
9511                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9512                         (PAGE_SIZE - 1)));
9513         } else
9514                 exec_control &= ~PIN_BASED_POSTED_INTR;
9515
9516         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9517
9518         vmx->nested.preemption_timer_expired = false;
9519         if (nested_cpu_has_preemption_timer(vmcs12))
9520                 vmx_start_preemption_timer(vcpu);
9521
9522         /*
9523          * Whether page-faults are trapped is determined by a combination of
9524          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9525          * If enable_ept, L0 doesn't care about page faults and we should
9526          * set all of these to L1's desires. However, if !enable_ept, L0 does
9527          * care about (at least some) page faults, and because it is not easy
9528          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9529          * to exit on each and every L2 page fault. This is done by setting
9530          * MASK=MATCH=0 and (see below) EB.PF=1.
9531          * Note that below we don't need special code to set EB.PF beyond the
9532          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9533          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9534          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9535          *
9536          * A problem with this approach (when !enable_ept) is that L1 may be
9537          * injected with more page faults than it asked for. This could have
9538          * caused problems, but in practice existing hypervisors don't care.
9539          * To fix this, we will need to emulate the PFEC checking (on the L1
9540          * page tables), using walk_addr(), when injecting PFs to L1.
9541          */
9542         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9543                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9544         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9545                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9546
9547         if (cpu_has_secondary_exec_ctrls()) {
9548                 exec_control = vmx_secondary_exec_control(vmx);
9549
9550                 /* Take the following fields only from vmcs12 */
9551                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9552                                   SECONDARY_EXEC_RDTSCP |
9553                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9554                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9555                                   SECONDARY_EXEC_PCOMMIT);
9556                 if (nested_cpu_has(vmcs12,
9557                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9558                         exec_control |= vmcs12->secondary_vm_exec_control;
9559
9560                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9561                         /*
9562                          * If translation failed, no matter: This feature asks
9563                          * to exit when accessing the given address, and if it
9564                          * can never be accessed, this feature won't do
9565                          * anything anyway.
9566                          */
9567                         if (!vmx->nested.apic_access_page)
9568                                 exec_control &=
9569                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9570                         else
9571                                 vmcs_write64(APIC_ACCESS_ADDR,
9572                                   page_to_phys(vmx->nested.apic_access_page));
9573                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9574                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9575                         exec_control |=
9576                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9577                         kvm_vcpu_reload_apic_access_page(vcpu);
9578                 }
9579
9580                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9581                         vmcs_write64(EOI_EXIT_BITMAP0,
9582                                 vmcs12->eoi_exit_bitmap0);
9583                         vmcs_write64(EOI_EXIT_BITMAP1,
9584                                 vmcs12->eoi_exit_bitmap1);
9585                         vmcs_write64(EOI_EXIT_BITMAP2,
9586                                 vmcs12->eoi_exit_bitmap2);
9587                         vmcs_write64(EOI_EXIT_BITMAP3,
9588                                 vmcs12->eoi_exit_bitmap3);
9589                         vmcs_write16(GUEST_INTR_STATUS,
9590                                 vmcs12->guest_intr_status);
9591                 }
9592
9593                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9594         }
9595
9596
9597         /*
9598          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9599          * Some constant fields are set here by vmx_set_constant_host_state().
9600          * Other fields are different per CPU, and will be set later when
9601          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9602          */
9603         vmx_set_constant_host_state(vmx);
9604
9605         /*
9606          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9607          * entry, but only if the current (host) sp changed from the value
9608          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9609          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9610          * here we just force the write to happen on entry.
9611          */
9612         vmx->host_rsp = 0;
9613
9614         exec_control = vmx_exec_control(vmx); /* L0's desires */
9615         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9616         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9617         exec_control &= ~CPU_BASED_TPR_SHADOW;
9618         exec_control |= vmcs12->cpu_based_vm_exec_control;
9619
9620         if (exec_control & CPU_BASED_TPR_SHADOW) {
9621                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9622                                 page_to_phys(vmx->nested.virtual_apic_page));
9623                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9624         }
9625
9626         if (cpu_has_vmx_msr_bitmap() &&
9627             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9628                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9629                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9630         } else
9631                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9632
9633         /*
9634          * Merging of IO bitmap not currently supported.
9635          * Rather, exit every time.
9636          */
9637         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9638         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9639
9640         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9641
9642         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9643          * bitwise-or of what L1 wants to trap for L2, and what we want to
9644          * trap. Note that CR0.TS also needs updating - we do this later.
9645          */
9646         update_exception_bitmap(vcpu);
9647         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9648         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9649
9650         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9651          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9652          * bits are further modified by vmx_set_efer() below.
9653          */
9654         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9655
9656         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9657          * emulated by vmx_set_efer(), below.
9658          */
9659         vm_entry_controls_init(vmx,
9660                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9661                         ~VM_ENTRY_IA32E_MODE) |
9662                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9663
9664         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9665                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9666                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9667         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9668                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9669
9670
9671         set_cr4_guest_host_mask(vmx);
9672
9673         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9674                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9675
9676         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9677                 vmcs_write64(TSC_OFFSET,
9678                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9679         else
9680                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9681
9682         if (enable_vpid) {
9683                 /*
9684                  * There is no direct mapping between vpid02 and vpid12, the
9685                  * vpid02 is per-vCPU for L0 and reused while the value of
9686                  * vpid12 is changed w/ one invvpid during nested vmentry.
9687                  * The vpid12 is allocated by L1 for L2, so it will not
9688                  * influence global bitmap(for vpid01 and vpid02 allocation)
9689                  * even if spawn a lot of nested vCPUs.
9690                  */
9691                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9692                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9693                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9694                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9695                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9696                         }
9697                 } else {
9698                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9699                         vmx_flush_tlb(vcpu);
9700                 }
9701
9702         }
9703
9704         if (nested_cpu_has_ept(vmcs12)) {
9705                 kvm_mmu_unload(vcpu);
9706                 nested_ept_init_mmu_context(vcpu);
9707         }
9708
9709         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9710                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9711         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9712                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9713         else
9714                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9715         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9716         vmx_set_efer(vcpu, vcpu->arch.efer);
9717
9718         /*
9719          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9720          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9721          * The CR0_READ_SHADOW is what L2 should have expected to read given
9722          * the specifications by L1; It's not enough to take
9723          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9724          * have more bits than L1 expected.
9725          */
9726         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9727         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9728
9729         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9730         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9731
9732         /* shadow page tables on either EPT or shadow page tables */
9733         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9734         kvm_mmu_reset_context(vcpu);
9735
9736         if (!enable_ept)
9737                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9738
9739         /*
9740          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9741          */
9742         if (enable_ept) {
9743                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9744                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9745                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9746                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9747         }
9748
9749         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9750         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9751 }
9752
9753 /*
9754  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9755  * for running an L2 nested guest.
9756  */
9757 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9758 {
9759         struct vmcs12 *vmcs12;
9760         struct vcpu_vmx *vmx = to_vmx(vcpu);
9761         int cpu;
9762         struct loaded_vmcs *vmcs02;
9763         bool ia32e;
9764         u32 msr_entry_idx;
9765
9766         if (!nested_vmx_check_permission(vcpu) ||
9767             !nested_vmx_check_vmcs12(vcpu))
9768                 return 1;
9769
9770         skip_emulated_instruction(vcpu);
9771         vmcs12 = get_vmcs12(vcpu);
9772
9773         if (enable_shadow_vmcs)
9774                 copy_shadow_to_vmcs12(vmx);
9775
9776         /*
9777          * The nested entry process starts with enforcing various prerequisites
9778          * on vmcs12 as required by the Intel SDM, and act appropriately when
9779          * they fail: As the SDM explains, some conditions should cause the
9780          * instruction to fail, while others will cause the instruction to seem
9781          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9782          * To speed up the normal (success) code path, we should avoid checking
9783          * for misconfigurations which will anyway be caught by the processor
9784          * when using the merged vmcs02.
9785          */
9786         if (vmcs12->launch_state == launch) {
9787                 nested_vmx_failValid(vcpu,
9788                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9789                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9790                 return 1;
9791         }
9792
9793         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9794             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9795                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9796                 return 1;
9797         }
9798
9799         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9800                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9801                 return 1;
9802         }
9803
9804         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9805                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9806                 return 1;
9807         }
9808
9809         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9810                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9811                 return 1;
9812         }
9813
9814         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9815                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9816                 return 1;
9817         }
9818
9819         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9820                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9821                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9822             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9823                                 vmx->nested.nested_vmx_secondary_ctls_low,
9824                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9825             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9826                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9827                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9828             !vmx_control_verify(vmcs12->vm_exit_controls,
9829                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9830                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9831             !vmx_control_verify(vmcs12->vm_entry_controls,
9832                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9833                                 vmx->nested.nested_vmx_entry_ctls_high))
9834         {
9835                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9836                 return 1;
9837         }
9838
9839         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9840             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9841                 nested_vmx_failValid(vcpu,
9842                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9843                 return 1;
9844         }
9845
9846         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9847             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9848                 nested_vmx_entry_failure(vcpu, vmcs12,
9849                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9850                 return 1;
9851         }
9852         if (vmcs12->vmcs_link_pointer != -1ull) {
9853                 nested_vmx_entry_failure(vcpu, vmcs12,
9854                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9855                 return 1;
9856         }
9857
9858         /*
9859          * If the load IA32_EFER VM-entry control is 1, the following checks
9860          * are performed on the field for the IA32_EFER MSR:
9861          * - Bits reserved in the IA32_EFER MSR must be 0.
9862          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9863          *   the IA-32e mode guest VM-exit control. It must also be identical
9864          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9865          *   CR0.PG) is 1.
9866          */
9867         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9868                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9869                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9870                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9871                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9872                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9873                         nested_vmx_entry_failure(vcpu, vmcs12,
9874                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9875                         return 1;
9876                 }
9877         }
9878
9879         /*
9880          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9881          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9882          * the values of the LMA and LME bits in the field must each be that of
9883          * the host address-space size VM-exit control.
9884          */
9885         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9886                 ia32e = (vmcs12->vm_exit_controls &
9887                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9888                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9889                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9890                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9891                         nested_vmx_entry_failure(vcpu, vmcs12,
9892                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9893                         return 1;
9894                 }
9895         }
9896
9897         /*
9898          * We're finally done with prerequisite checking, and can start with
9899          * the nested entry.
9900          */
9901
9902         vmcs02 = nested_get_current_vmcs02(vmx);
9903         if (!vmcs02)
9904                 return -ENOMEM;
9905
9906         enter_guest_mode(vcpu);
9907
9908         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9909
9910         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9911                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9912
9913         cpu = get_cpu();
9914         vmx->loaded_vmcs = vmcs02;
9915         vmx_vcpu_put(vcpu);
9916         vmx_vcpu_load(vcpu, cpu);
9917         vcpu->cpu = cpu;
9918         put_cpu();
9919
9920         vmx_segment_cache_clear(vmx);
9921
9922         prepare_vmcs02(vcpu, vmcs12);
9923
9924         msr_entry_idx = nested_vmx_load_msr(vcpu,
9925                                             vmcs12->vm_entry_msr_load_addr,
9926                                             vmcs12->vm_entry_msr_load_count);
9927         if (msr_entry_idx) {
9928                 leave_guest_mode(vcpu);
9929                 vmx_load_vmcs01(vcpu);
9930                 nested_vmx_entry_failure(vcpu, vmcs12,
9931                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9932                 return 1;
9933         }
9934
9935         vmcs12->launch_state = 1;
9936
9937         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9938                 return kvm_vcpu_halt(vcpu);
9939
9940         vmx->nested.nested_run_pending = 1;
9941
9942         /*
9943          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9944          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9945          * returned as far as L1 is concerned. It will only return (and set
9946          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9947          */
9948         return 1;
9949 }
9950
9951 /*
9952  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9953  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9954  * This function returns the new value we should put in vmcs12.guest_cr0.
9955  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9956  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9957  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9958  *     didn't trap the bit, because if L1 did, so would L0).
9959  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9960  *     been modified by L2, and L1 knows it. So just leave the old value of
9961  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9962  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9963  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9964  *     changed these bits, and therefore they need to be updated, but L0
9965  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9966  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9967  */
9968 static inline unsigned long
9969 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9970 {
9971         return
9972         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9973         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9974         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9975                         vcpu->arch.cr0_guest_owned_bits));
9976 }
9977
9978 static inline unsigned long
9979 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9980 {
9981         return
9982         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9983         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9984         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9985                         vcpu->arch.cr4_guest_owned_bits));
9986 }
9987
9988 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9989                                        struct vmcs12 *vmcs12)
9990 {
9991         u32 idt_vectoring;
9992         unsigned int nr;
9993
9994         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9995                 nr = vcpu->arch.exception.nr;
9996                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9997
9998                 if (kvm_exception_is_soft(nr)) {
9999                         vmcs12->vm_exit_instruction_len =
10000                                 vcpu->arch.event_exit_inst_len;
10001                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10002                 } else
10003                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10004
10005                 if (vcpu->arch.exception.has_error_code) {
10006                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10007                         vmcs12->idt_vectoring_error_code =
10008                                 vcpu->arch.exception.error_code;
10009                 }
10010
10011                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10012         } else if (vcpu->arch.nmi_injected) {
10013                 vmcs12->idt_vectoring_info_field =
10014                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10015         } else if (vcpu->arch.interrupt.pending) {
10016                 nr = vcpu->arch.interrupt.nr;
10017                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10018
10019                 if (vcpu->arch.interrupt.soft) {
10020                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10021                         vmcs12->vm_entry_instruction_len =
10022                                 vcpu->arch.event_exit_inst_len;
10023                 } else
10024                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10025
10026                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10027         }
10028 }
10029
10030 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10031 {
10032         struct vcpu_vmx *vmx = to_vmx(vcpu);
10033
10034         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10035             vmx->nested.preemption_timer_expired) {
10036                 if (vmx->nested.nested_run_pending)
10037                         return -EBUSY;
10038                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10039                 return 0;
10040         }
10041
10042         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10043                 if (vmx->nested.nested_run_pending ||
10044                     vcpu->arch.interrupt.pending)
10045                         return -EBUSY;
10046                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10047                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10048                                   INTR_INFO_VALID_MASK, 0);
10049                 /*
10050                  * The NMI-triggered VM exit counts as injection:
10051                  * clear this one and block further NMIs.
10052                  */
10053                 vcpu->arch.nmi_pending = 0;
10054                 vmx_set_nmi_mask(vcpu, true);
10055                 return 0;
10056         }
10057
10058         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10059             nested_exit_on_intr(vcpu)) {
10060                 if (vmx->nested.nested_run_pending)
10061                         return -EBUSY;
10062                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10063                 return 0;
10064         }
10065
10066         return vmx_complete_nested_posted_interrupt(vcpu);
10067 }
10068
10069 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10070 {
10071         ktime_t remaining =
10072                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10073         u64 value;
10074
10075         if (ktime_to_ns(remaining) <= 0)
10076                 return 0;
10077
10078         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10079         do_div(value, 1000000);
10080         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10081 }
10082
10083 /*
10084  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10085  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10086  * and this function updates it to reflect the changes to the guest state while
10087  * L2 was running (and perhaps made some exits which were handled directly by L0
10088  * without going back to L1), and to reflect the exit reason.
10089  * Note that we do not have to copy here all VMCS fields, just those that
10090  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10091  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10092  * which already writes to vmcs12 directly.
10093  */
10094 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10095                            u32 exit_reason, u32 exit_intr_info,
10096                            unsigned long exit_qualification)
10097 {
10098         /* update guest state fields: */
10099         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10100         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10101
10102         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10103         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10104         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10105
10106         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10107         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10108         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10109         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10110         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10111         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10112         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10113         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10114         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10115         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10116         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10117         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10118         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10119         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10120         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10121         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10122         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10123         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10124         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10125         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10126         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10127         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10128         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10129         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10130         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10131         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10132         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10133         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10134         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10135         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10136         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10137         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10138         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10139         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10140         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10141         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10142
10143         vmcs12->guest_interruptibility_info =
10144                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10145         vmcs12->guest_pending_dbg_exceptions =
10146                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10147         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10148                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10149         else
10150                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10151
10152         if (nested_cpu_has_preemption_timer(vmcs12)) {
10153                 if (vmcs12->vm_exit_controls &
10154                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10155                         vmcs12->vmx_preemption_timer_value =
10156                                 vmx_get_preemption_timer_value(vcpu);
10157                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10158         }
10159
10160         /*
10161          * In some cases (usually, nested EPT), L2 is allowed to change its
10162          * own CR3 without exiting. If it has changed it, we must keep it.
10163          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10164          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10165          *
10166          * Additionally, restore L2's PDPTR to vmcs12.
10167          */
10168         if (enable_ept) {
10169                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10170                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10171                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10172                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10173                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10174         }
10175
10176         if (nested_cpu_has_vid(vmcs12))
10177                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10178
10179         vmcs12->vm_entry_controls =
10180                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10181                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10182
10183         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10184                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10185                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10186         }
10187
10188         /* TODO: These cannot have changed unless we have MSR bitmaps and
10189          * the relevant bit asks not to trap the change */
10190         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10191                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10192         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10193                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10194         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10195         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10196         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10197         if (vmx_mpx_supported())
10198                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10199         if (nested_cpu_has_xsaves(vmcs12))
10200                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10201
10202         /* update exit information fields: */
10203
10204         vmcs12->vm_exit_reason = exit_reason;
10205         vmcs12->exit_qualification = exit_qualification;
10206
10207         vmcs12->vm_exit_intr_info = exit_intr_info;
10208         if ((vmcs12->vm_exit_intr_info &
10209              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10210             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10211                 vmcs12->vm_exit_intr_error_code =
10212                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10213         vmcs12->idt_vectoring_info_field = 0;
10214         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10215         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10216
10217         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10218                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10219                  * instead of reading the real value. */
10220                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10221
10222                 /*
10223                  * Transfer the event that L0 or L1 may wanted to inject into
10224                  * L2 to IDT_VECTORING_INFO_FIELD.
10225                  */
10226                 vmcs12_save_pending_event(vcpu, vmcs12);
10227         }
10228
10229         /*
10230          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10231          * preserved above and would only end up incorrectly in L1.
10232          */
10233         vcpu->arch.nmi_injected = false;
10234         kvm_clear_exception_queue(vcpu);
10235         kvm_clear_interrupt_queue(vcpu);
10236 }
10237
10238 /*
10239  * A part of what we need to when the nested L2 guest exits and we want to
10240  * run its L1 parent, is to reset L1's guest state to the host state specified
10241  * in vmcs12.
10242  * This function is to be called not only on normal nested exit, but also on
10243  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10244  * Failures During or After Loading Guest State").
10245  * This function should be called when the active VMCS is L1's (vmcs01).
10246  */
10247 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10248                                    struct vmcs12 *vmcs12)
10249 {
10250         struct kvm_segment seg;
10251
10252         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10253                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10254         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10255                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10256         else
10257                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10258         vmx_set_efer(vcpu, vcpu->arch.efer);
10259
10260         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10261         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10262         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10263         /*
10264          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10265          * actually changed, because it depends on the current state of
10266          * fpu_active (which may have changed).
10267          * Note that vmx_set_cr0 refers to efer set above.
10268          */
10269         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10270         /*
10271          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10272          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10273          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10274          */
10275         update_exception_bitmap(vcpu);
10276         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10277         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10278
10279         /*
10280          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10281          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10282          */
10283         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10284         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10285
10286         nested_ept_uninit_mmu_context(vcpu);
10287
10288         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10289         kvm_mmu_reset_context(vcpu);
10290
10291         if (!enable_ept)
10292                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10293
10294         if (enable_vpid) {
10295                 /*
10296                  * Trivially support vpid by letting L2s share their parent
10297                  * L1's vpid. TODO: move to a more elaborate solution, giving
10298                  * each L2 its own vpid and exposing the vpid feature to L1.
10299                  */
10300                 vmx_flush_tlb(vcpu);
10301         }
10302
10303
10304         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10305         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10306         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10307         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10308         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10309
10310         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10311         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10312                 vmcs_write64(GUEST_BNDCFGS, 0);
10313
10314         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10315                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10316                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10317         }
10318         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10319                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10320                         vmcs12->host_ia32_perf_global_ctrl);
10321
10322         /* Set L1 segment info according to Intel SDM
10323             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10324         seg = (struct kvm_segment) {
10325                 .base = 0,
10326                 .limit = 0xFFFFFFFF,
10327                 .selector = vmcs12->host_cs_selector,
10328                 .type = 11,
10329                 .present = 1,
10330                 .s = 1,
10331                 .g = 1
10332         };
10333         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10334                 seg.l = 1;
10335         else
10336                 seg.db = 1;
10337         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10338         seg = (struct kvm_segment) {
10339                 .base = 0,
10340                 .limit = 0xFFFFFFFF,
10341                 .type = 3,
10342                 .present = 1,
10343                 .s = 1,
10344                 .db = 1,
10345                 .g = 1
10346         };
10347         seg.selector = vmcs12->host_ds_selector;
10348         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10349         seg.selector = vmcs12->host_es_selector;
10350         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10351         seg.selector = vmcs12->host_ss_selector;
10352         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10353         seg.selector = vmcs12->host_fs_selector;
10354         seg.base = vmcs12->host_fs_base;
10355         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10356         seg.selector = vmcs12->host_gs_selector;
10357         seg.base = vmcs12->host_gs_base;
10358         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10359         seg = (struct kvm_segment) {
10360                 .base = vmcs12->host_tr_base,
10361                 .limit = 0x67,
10362                 .selector = vmcs12->host_tr_selector,
10363                 .type = 11,
10364                 .present = 1
10365         };
10366         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10367
10368         kvm_set_dr(vcpu, 7, 0x400);
10369         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10370
10371         if (cpu_has_vmx_msr_bitmap())
10372                 vmx_set_msr_bitmap(vcpu);
10373
10374         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10375                                 vmcs12->vm_exit_msr_load_count))
10376                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10377 }
10378
10379 /*
10380  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10381  * and modify vmcs12 to make it see what it would expect to see there if
10382  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10383  */
10384 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10385                               u32 exit_intr_info,
10386                               unsigned long exit_qualification)
10387 {
10388         struct vcpu_vmx *vmx = to_vmx(vcpu);
10389         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10390
10391         /* trying to cancel vmlaunch/vmresume is a bug */
10392         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10393
10394         leave_guest_mode(vcpu);
10395         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10396                        exit_qualification);
10397
10398         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10399                                  vmcs12->vm_exit_msr_store_count))
10400                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10401
10402         vmx_load_vmcs01(vcpu);
10403
10404         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10405             && nested_exit_intr_ack_set(vcpu)) {
10406                 int irq = kvm_cpu_get_interrupt(vcpu);
10407                 WARN_ON(irq < 0);
10408                 vmcs12->vm_exit_intr_info = irq |
10409                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10410         }
10411
10412         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10413                                        vmcs12->exit_qualification,
10414                                        vmcs12->idt_vectoring_info_field,
10415                                        vmcs12->vm_exit_intr_info,
10416                                        vmcs12->vm_exit_intr_error_code,
10417                                        KVM_ISA_VMX);
10418
10419         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10420         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10421         vmx_segment_cache_clear(vmx);
10422
10423         /* if no vmcs02 cache requested, remove the one we used */
10424         if (VMCS02_POOL_SIZE == 0)
10425                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10426
10427         load_vmcs12_host_state(vcpu, vmcs12);
10428
10429         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10430         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10431
10432         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10433         vmx->host_rsp = 0;
10434
10435         /* Unpin physical memory we referred to in vmcs02 */
10436         if (vmx->nested.apic_access_page) {
10437                 nested_release_page(vmx->nested.apic_access_page);
10438                 vmx->nested.apic_access_page = NULL;
10439         }
10440         if (vmx->nested.virtual_apic_page) {
10441                 nested_release_page(vmx->nested.virtual_apic_page);
10442                 vmx->nested.virtual_apic_page = NULL;
10443         }
10444         if (vmx->nested.pi_desc_page) {
10445                 kunmap(vmx->nested.pi_desc_page);
10446                 nested_release_page(vmx->nested.pi_desc_page);
10447                 vmx->nested.pi_desc_page = NULL;
10448                 vmx->nested.pi_desc = NULL;
10449         }
10450
10451         /*
10452          * We are now running in L2, mmu_notifier will force to reload the
10453          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10454          */
10455         kvm_vcpu_reload_apic_access_page(vcpu);
10456
10457         /*
10458          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10459          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10460          * success or failure flag accordingly.
10461          */
10462         if (unlikely(vmx->fail)) {
10463                 vmx->fail = 0;
10464                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10465         } else
10466                 nested_vmx_succeed(vcpu);
10467         if (enable_shadow_vmcs)
10468                 vmx->nested.sync_shadow_vmcs = true;
10469
10470         /* in case we halted in L2 */
10471         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10472 }
10473
10474 /*
10475  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10476  */
10477 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10478 {
10479         if (is_guest_mode(vcpu))
10480                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10481         free_nested(to_vmx(vcpu));
10482 }
10483
10484 /*
10485  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10486  * 23.7 "VM-entry failures during or after loading guest state" (this also
10487  * lists the acceptable exit-reason and exit-qualification parameters).
10488  * It should only be called before L2 actually succeeded to run, and when
10489  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10490  */
10491 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10492                         struct vmcs12 *vmcs12,
10493                         u32 reason, unsigned long qualification)
10494 {
10495         load_vmcs12_host_state(vcpu, vmcs12);
10496         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10497         vmcs12->exit_qualification = qualification;
10498         nested_vmx_succeed(vcpu);
10499         if (enable_shadow_vmcs)
10500                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10501 }
10502
10503 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10504                                struct x86_instruction_info *info,
10505                                enum x86_intercept_stage stage)
10506 {
10507         return X86EMUL_CONTINUE;
10508 }
10509
10510 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10511 {
10512         if (ple_gap)
10513                 shrink_ple_window(vcpu);
10514 }
10515
10516 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10517                                      struct kvm_memory_slot *slot)
10518 {
10519         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10520         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10521 }
10522
10523 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10524                                        struct kvm_memory_slot *slot)
10525 {
10526         kvm_mmu_slot_set_dirty(kvm, slot);
10527 }
10528
10529 static void vmx_flush_log_dirty(struct kvm *kvm)
10530 {
10531         kvm_flush_pml_buffers(kvm);
10532 }
10533
10534 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10535                                            struct kvm_memory_slot *memslot,
10536                                            gfn_t offset, unsigned long mask)
10537 {
10538         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10539 }
10540
10541 /*
10542  * This routine does the following things for vCPU which is going
10543  * to be blocked if VT-d PI is enabled.
10544  * - Store the vCPU to the wakeup list, so when interrupts happen
10545  *   we can find the right vCPU to wake up.
10546  * - Change the Posted-interrupt descriptor as below:
10547  *      'NDST' <-- vcpu->pre_pcpu
10548  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10549  * - If 'ON' is set during this process, which means at least one
10550  *   interrupt is posted for this vCPU, we cannot block it, in
10551  *   this case, return 1, otherwise, return 0.
10552  *
10553  */
10554 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10555 {
10556         unsigned long flags;
10557         unsigned int dest;
10558         struct pi_desc old, new;
10559         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10560
10561         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10562                 !irq_remapping_cap(IRQ_POSTING_CAP))
10563                 return 0;
10564
10565         vcpu->pre_pcpu = vcpu->cpu;
10566         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10567                           vcpu->pre_pcpu), flags);
10568         list_add_tail(&vcpu->blocked_vcpu_list,
10569                       &per_cpu(blocked_vcpu_on_cpu,
10570                       vcpu->pre_pcpu));
10571         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10572                                vcpu->pre_pcpu), flags);
10573
10574         do {
10575                 old.control = new.control = pi_desc->control;
10576
10577                 /*
10578                  * We should not block the vCPU if
10579                  * an interrupt is posted for it.
10580                  */
10581                 if (pi_test_on(pi_desc) == 1) {
10582                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10583                                           vcpu->pre_pcpu), flags);
10584                         list_del(&vcpu->blocked_vcpu_list);
10585                         spin_unlock_irqrestore(
10586                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10587                                         vcpu->pre_pcpu), flags);
10588                         vcpu->pre_pcpu = -1;
10589
10590                         return 1;
10591                 }
10592
10593                 WARN((pi_desc->sn == 1),
10594                      "Warning: SN field of posted-interrupts "
10595                      "is set before blocking\n");
10596
10597                 /*
10598                  * Since vCPU can be preempted during this process,
10599                  * vcpu->cpu could be different with pre_pcpu, we
10600                  * need to set pre_pcpu as the destination of wakeup
10601                  * notification event, then we can find the right vCPU
10602                  * to wakeup in wakeup handler if interrupts happen
10603                  * when the vCPU is in blocked state.
10604                  */
10605                 dest = cpu_physical_id(vcpu->pre_pcpu);
10606
10607                 if (x2apic_enabled())
10608                         new.ndst = dest;
10609                 else
10610                         new.ndst = (dest << 8) & 0xFF00;
10611
10612                 /* set 'NV' to 'wakeup vector' */
10613                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10614         } while (cmpxchg(&pi_desc->control, old.control,
10615                         new.control) != old.control);
10616
10617         return 0;
10618 }
10619
10620 static void vmx_post_block(struct kvm_vcpu *vcpu)
10621 {
10622         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10623         struct pi_desc old, new;
10624         unsigned int dest;
10625         unsigned long flags;
10626
10627         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10628                 !irq_remapping_cap(IRQ_POSTING_CAP))
10629                 return;
10630
10631         do {
10632                 old.control = new.control = pi_desc->control;
10633
10634                 dest = cpu_physical_id(vcpu->cpu);
10635
10636                 if (x2apic_enabled())
10637                         new.ndst = dest;
10638                 else
10639                         new.ndst = (dest << 8) & 0xFF00;
10640
10641                 /* Allow posting non-urgent interrupts */
10642                 new.sn = 0;
10643
10644                 /* set 'NV' to 'notification vector' */
10645                 new.nv = POSTED_INTR_VECTOR;
10646         } while (cmpxchg(&pi_desc->control, old.control,
10647                         new.control) != old.control);
10648
10649         if(vcpu->pre_pcpu != -1) {
10650                 spin_lock_irqsave(
10651                         &per_cpu(blocked_vcpu_on_cpu_lock,
10652                         vcpu->pre_pcpu), flags);
10653                 list_del(&vcpu->blocked_vcpu_list);
10654                 spin_unlock_irqrestore(
10655                         &per_cpu(blocked_vcpu_on_cpu_lock,
10656                         vcpu->pre_pcpu), flags);
10657                 vcpu->pre_pcpu = -1;
10658         }
10659 }
10660
10661 /*
10662  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10663  *
10664  * @kvm: kvm
10665  * @host_irq: host irq of the interrupt
10666  * @guest_irq: gsi of the interrupt
10667  * @set: set or unset PI
10668  * returns 0 on success, < 0 on failure
10669  */
10670 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10671                               uint32_t guest_irq, bool set)
10672 {
10673         struct kvm_kernel_irq_routing_entry *e;
10674         struct kvm_irq_routing_table *irq_rt;
10675         struct kvm_lapic_irq irq;
10676         struct kvm_vcpu *vcpu;
10677         struct vcpu_data vcpu_info;
10678         int idx, ret = -EINVAL;
10679
10680         if (!kvm_arch_has_assigned_device(kvm) ||
10681                 !irq_remapping_cap(IRQ_POSTING_CAP))
10682                 return 0;
10683
10684         idx = srcu_read_lock(&kvm->irq_srcu);
10685         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10686         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10687
10688         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10689                 if (e->type != KVM_IRQ_ROUTING_MSI)
10690                         continue;
10691                 /*
10692                  * VT-d PI cannot support posting multicast/broadcast
10693                  * interrupts to a vCPU, we still use interrupt remapping
10694                  * for these kind of interrupts.
10695                  *
10696                  * For lowest-priority interrupts, we only support
10697                  * those with single CPU as the destination, e.g. user
10698                  * configures the interrupts via /proc/irq or uses
10699                  * irqbalance to make the interrupts single-CPU.
10700                  *
10701                  * We will support full lowest-priority interrupt later.
10702                  */
10703
10704                 kvm_set_msi_irq(e, &irq);
10705                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10706                         continue;
10707
10708                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10709                 vcpu_info.vector = irq.vector;
10710
10711                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10712                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10713
10714                 if (set)
10715                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10716                 else {
10717                         /* suppress notification event before unposting */
10718                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10719                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10720                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10721                 }
10722
10723                 if (ret < 0) {
10724                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10725                                         __func__);
10726                         goto out;
10727                 }
10728         }
10729
10730         ret = 0;
10731 out:
10732         srcu_read_unlock(&kvm->irq_srcu, idx);
10733         return ret;
10734 }
10735
10736 static struct kvm_x86_ops vmx_x86_ops = {
10737         .cpu_has_kvm_support = cpu_has_kvm_support,
10738         .disabled_by_bios = vmx_disabled_by_bios,
10739         .hardware_setup = hardware_setup,
10740         .hardware_unsetup = hardware_unsetup,
10741         .check_processor_compatibility = vmx_check_processor_compat,
10742         .hardware_enable = hardware_enable,
10743         .hardware_disable = hardware_disable,
10744         .cpu_has_accelerated_tpr = report_flexpriority,
10745         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10746
10747         .vcpu_create = vmx_create_vcpu,
10748         .vcpu_free = vmx_free_vcpu,
10749         .vcpu_reset = vmx_vcpu_reset,
10750
10751         .prepare_guest_switch = vmx_save_host_state,
10752         .vcpu_load = vmx_vcpu_load,
10753         .vcpu_put = vmx_vcpu_put,
10754
10755         .update_db_bp_intercept = update_exception_bitmap,
10756         .get_msr = vmx_get_msr,
10757         .set_msr = vmx_set_msr,
10758         .get_segment_base = vmx_get_segment_base,
10759         .get_segment = vmx_get_segment,
10760         .set_segment = vmx_set_segment,
10761         .get_cpl = vmx_get_cpl,
10762         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10763         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10764         .decache_cr3 = vmx_decache_cr3,
10765         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10766         .set_cr0 = vmx_set_cr0,
10767         .set_cr3 = vmx_set_cr3,
10768         .set_cr4 = vmx_set_cr4,
10769         .set_efer = vmx_set_efer,
10770         .get_idt = vmx_get_idt,
10771         .set_idt = vmx_set_idt,
10772         .get_gdt = vmx_get_gdt,
10773         .set_gdt = vmx_set_gdt,
10774         .get_dr6 = vmx_get_dr6,
10775         .set_dr6 = vmx_set_dr6,
10776         .set_dr7 = vmx_set_dr7,
10777         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10778         .cache_reg = vmx_cache_reg,
10779         .get_rflags = vmx_get_rflags,
10780         .set_rflags = vmx_set_rflags,
10781         .fpu_activate = vmx_fpu_activate,
10782         .fpu_deactivate = vmx_fpu_deactivate,
10783
10784         .tlb_flush = vmx_flush_tlb,
10785
10786         .run = vmx_vcpu_run,
10787         .handle_exit = vmx_handle_exit,
10788         .skip_emulated_instruction = skip_emulated_instruction,
10789         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10790         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10791         .patch_hypercall = vmx_patch_hypercall,
10792         .set_irq = vmx_inject_irq,
10793         .set_nmi = vmx_inject_nmi,
10794         .queue_exception = vmx_queue_exception,
10795         .cancel_injection = vmx_cancel_injection,
10796         .interrupt_allowed = vmx_interrupt_allowed,
10797         .nmi_allowed = vmx_nmi_allowed,
10798         .get_nmi_mask = vmx_get_nmi_mask,
10799         .set_nmi_mask = vmx_set_nmi_mask,
10800         .enable_nmi_window = enable_nmi_window,
10801         .enable_irq_window = enable_irq_window,
10802         .update_cr8_intercept = update_cr8_intercept,
10803         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10804         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10805         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10806         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10807         .hwapic_irr_update = vmx_hwapic_irr_update,
10808         .hwapic_isr_update = vmx_hwapic_isr_update,
10809         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10810         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10811
10812         .set_tss_addr = vmx_set_tss_addr,
10813         .get_tdp_level = get_ept_level,
10814         .get_mt_mask = vmx_get_mt_mask,
10815
10816         .get_exit_info = vmx_get_exit_info,
10817
10818         .get_lpage_level = vmx_get_lpage_level,
10819
10820         .cpuid_update = vmx_cpuid_update,
10821
10822         .rdtscp_supported = vmx_rdtscp_supported,
10823         .invpcid_supported = vmx_invpcid_supported,
10824
10825         .set_supported_cpuid = vmx_set_supported_cpuid,
10826
10827         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10828
10829         .set_tsc_khz = vmx_set_tsc_khz,
10830         .read_tsc_offset = vmx_read_tsc_offset,
10831         .write_tsc_offset = vmx_write_tsc_offset,
10832         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10833         .compute_tsc_offset = vmx_compute_tsc_offset,
10834         .read_l1_tsc = vmx_read_l1_tsc,
10835
10836         .set_tdp_cr3 = vmx_set_cr3,
10837
10838         .check_intercept = vmx_check_intercept,
10839         .handle_external_intr = vmx_handle_external_intr,
10840         .mpx_supported = vmx_mpx_supported,
10841         .xsaves_supported = vmx_xsaves_supported,
10842
10843         .check_nested_events = vmx_check_nested_events,
10844
10845         .sched_in = vmx_sched_in,
10846
10847         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10848         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10849         .flush_log_dirty = vmx_flush_log_dirty,
10850         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10851
10852         .pre_block = vmx_pre_block,
10853         .post_block = vmx_post_block,
10854
10855         .pmu_ops = &intel_pmu_ops,
10856
10857         .update_pi_irte = vmx_update_pi_irte,
10858 };
10859
10860 static int __init vmx_init(void)
10861 {
10862         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10863                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10864         if (r)
10865                 return r;
10866
10867 #ifdef CONFIG_KEXEC_CORE
10868         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10869                            crash_vmclear_local_loaded_vmcss);
10870 #endif
10871
10872         return 0;
10873 }
10874
10875 static void __exit vmx_exit(void)
10876 {
10877 #ifdef CONFIG_KEXEC_CORE
10878         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10879         synchronize_rcu();
10880 #endif
10881
10882         kvm_exit();
10883 }
10884
10885 module_init(vmx_init)
10886 module_exit(vmx_exit)