arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 111 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 112 #define KVM_VM_CR0_ALWAYS_ON                                            \
 113         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 114 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 115         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 116          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 117
 118 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 119 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 120
 121 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 122
 123 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 124
 125 /*
 126  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 127  * ple_gap:    upper bound on the amount of time between two successive
 128  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 129  *             According to test, this time is usually smaller than 128 cycles.
 130  * ple_window: upper bound on the amount of time a guest is allowed to execute
 131  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 132  *             less than 2^12 cycles
 133  * Time is measured based on a counter that runs at the same rate as the TSC,
 134  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 135  */
 136 #define KVM_VMX_DEFAULT_PLE_GAP           128
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 141                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 142
 143 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 144 module_param(ple_gap, int, S_IRUGO);
 145
 146 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 147 module_param(ple_window, int, S_IRUGO);
 148
 149 /* Default doubles per-vcpu window every exit. */
 150 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 151 module_param(ple_window_grow, int, S_IRUGO);
 152
 153 /* Default resets per-vcpu window every exit to ple_window. */
 154 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 155 module_param(ple_window_shrink, int, S_IRUGO);
 156
 157 /* Default is to compute the maximum so we can never overflow. */
 158 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 159 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 160 module_param(ple_window_max, int, S_IRUGO);
 161
 162 extern const ulong vmx_return;
 163
 164 #define NR_AUTOLOAD_MSRS 8
 165 #define VMCS02_POOL_SIZE 1
 166
 167 struct vmcs {
 168         u32 revision_id;
 169         u32 abort;
 170         char data[0];
 171 };
 172
 173 /*
 174  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 175  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 176  * loaded on this CPU (so we can clear them if the CPU goes down).
 177  */
 178 struct loaded_vmcs {
 179         struct vmcs *vmcs;
 180         int cpu;
 181         int launched;
 182         struct list_head loaded_vmcss_on_cpu_link;
 183 };
 184
 185 struct shared_msr_entry {
 186         unsigned index;
 187         u64 data;
 188         u64 mask;
 189 };
 190
 191 /*
 192  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 193  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 194  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 195  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 196  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 197  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 198  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 199  * underlying hardware which will be used to run L2.
 200  * This structure is packed to ensure that its layout is identical across
 201  * machines (necessary for live migration).
 202  * If there are changes in this struct, VMCS12_REVISION must be changed.
 203  */
 204 typedef u64 natural_width;
 205 struct __packed vmcs12 {
 206         /* According to the Intel spec, a VMCS region must start with the
 207          * following two fields. Then follow implementation-specific data.
 208          */
 209         u32 revision_id;
 210         u32 abort;
 211
 212         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 213         u32 padding[7]; /* room for future expansion */
 214
 215         u64 io_bitmap_a;
 216         u64 io_bitmap_b;
 217         u64 msr_bitmap;
 218         u64 vm_exit_msr_store_addr;
 219         u64 vm_exit_msr_load_addr;
 220         u64 vm_entry_msr_load_addr;
 221         u64 tsc_offset;
 222         u64 virtual_apic_page_addr;
 223         u64 apic_access_addr;
 224         u64 posted_intr_desc_addr;
 225         u64 ept_pointer;
 226         u64 eoi_exit_bitmap0;
 227         u64 eoi_exit_bitmap1;
 228         u64 eoi_exit_bitmap2;
 229         u64 eoi_exit_bitmap3;
 230         u64 xss_exit_bitmap;
 231         u64 guest_physical_address;
 232         u64 vmcs_link_pointer;
 233         u64 guest_ia32_debugctl;
 234         u64 guest_ia32_pat;
 235         u64 guest_ia32_efer;
 236         u64 guest_ia32_perf_global_ctrl;
 237         u64 guest_pdptr0;
 238         u64 guest_pdptr1;
 239         u64 guest_pdptr2;
 240         u64 guest_pdptr3;
 241         u64 guest_bndcfgs;
 242         u64 host_ia32_pat;
 243         u64 host_ia32_efer;
 244         u64 host_ia32_perf_global_ctrl;
 245         u64 padding64[8]; /* room for future expansion */
 246         /*
 247          * To allow migration of L1 (complete with its L2 guests) between
 248          * machines of different natural widths (32 or 64 bit), we cannot have
 249          * unsigned long fields with no explict size. We use u64 (aliased
 250          * natural_width) instead. Luckily, x86 is little-endian.
 251          */
 252         natural_width cr0_guest_host_mask;
 253         natural_width cr4_guest_host_mask;
 254         natural_width cr0_read_shadow;
 255         natural_width cr4_read_shadow;
 256         natural_width cr3_target_value0;
 257         natural_width cr3_target_value1;
 258         natural_width cr3_target_value2;
 259         natural_width cr3_target_value3;
 260         natural_width exit_qualification;
 261         natural_width guest_linear_address;
 262         natural_width guest_cr0;
 263         natural_width guest_cr3;
 264         natural_width guest_cr4;
 265         natural_width guest_es_base;
 266         natural_width guest_cs_base;
 267         natural_width guest_ss_base;
 268         natural_width guest_ds_base;
 269         natural_width guest_fs_base;
 270         natural_width guest_gs_base;
 271         natural_width guest_ldtr_base;
 272         natural_width guest_tr_base;
 273         natural_width guest_gdtr_base;
 274         natural_width guest_idtr_base;
 275         natural_width guest_dr7;
 276         natural_width guest_rsp;
 277         natural_width guest_rip;
 278         natural_width guest_rflags;
 279         natural_width guest_pending_dbg_exceptions;
 280         natural_width guest_sysenter_esp;
 281         natural_width guest_sysenter_eip;
 282         natural_width host_cr0;
 283         natural_width host_cr3;
 284         natural_width host_cr4;
 285         natural_width host_fs_base;
 286         natural_width host_gs_base;
 287         natural_width host_tr_base;
 288         natural_width host_gdtr_base;
 289         natural_width host_idtr_base;
 290         natural_width host_ia32_sysenter_esp;
 291         natural_width host_ia32_sysenter_eip;
 292         natural_width host_rsp;
 293         natural_width host_rip;
 294         natural_width paddingl[8]; /* room for future expansion */
 295         u32 pin_based_vm_exec_control;
 296         u32 cpu_based_vm_exec_control;
 297         u32 exception_bitmap;
 298         u32 page_fault_error_code_mask;
 299         u32 page_fault_error_code_match;
 300         u32 cr3_target_count;
 301         u32 vm_exit_controls;
 302         u32 vm_exit_msr_store_count;
 303         u32 vm_exit_msr_load_count;
 304         u32 vm_entry_controls;
 305         u32 vm_entry_msr_load_count;
 306         u32 vm_entry_intr_info_field;
 307         u32 vm_entry_exception_error_code;
 308         u32 vm_entry_instruction_len;
 309         u32 tpr_threshold;
 310         u32 secondary_vm_exec_control;
 311         u32 vm_instruction_error;
 312         u32 vm_exit_reason;
 313         u32 vm_exit_intr_info;
 314         u32 vm_exit_intr_error_code;
 315         u32 idt_vectoring_info_field;
 316         u32 idt_vectoring_error_code;
 317         u32 vm_exit_instruction_len;
 318         u32 vmx_instruction_info;
 319         u32 guest_es_limit;
 320         u32 guest_cs_limit;
 321         u32 guest_ss_limit;
 322         u32 guest_ds_limit;
 323         u32 guest_fs_limit;
 324         u32 guest_gs_limit;
 325         u32 guest_ldtr_limit;
 326         u32 guest_tr_limit;
 327         u32 guest_gdtr_limit;
 328         u32 guest_idtr_limit;
 329         u32 guest_es_ar_bytes;
 330         u32 guest_cs_ar_bytes;
 331         u32 guest_ss_ar_bytes;
 332         u32 guest_ds_ar_bytes;
 333         u32 guest_fs_ar_bytes;
 334         u32 guest_gs_ar_bytes;
 335         u32 guest_ldtr_ar_bytes;
 336         u32 guest_tr_ar_bytes;
 337         u32 guest_interruptibility_info;
 338         u32 guest_activity_state;
 339         u32 guest_sysenter_cs;
 340         u32 host_ia32_sysenter_cs;
 341         u32 vmx_preemption_timer_value;
 342         u32 padding32[7]; /* room for future expansion */
 343         u16 virtual_processor_id;
 344         u16 posted_intr_nv;
 345         u16 guest_es_selector;
 346         u16 guest_cs_selector;
 347         u16 guest_ss_selector;
 348         u16 guest_ds_selector;
 349         u16 guest_fs_selector;
 350         u16 guest_gs_selector;
 351         u16 guest_ldtr_selector;
 352         u16 guest_tr_selector;
 353         u16 guest_intr_status;
 354         u16 host_es_selector;
 355         u16 host_cs_selector;
 356         u16 host_ss_selector;
 357         u16 host_ds_selector;
 358         u16 host_fs_selector;
 359         u16 host_gs_selector;
 360         u16 host_tr_selector;
 361 };
 362
 363 /*
 364  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 365  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 366  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 367  */
 368 #define VMCS12_REVISION 0x11e57ed0
 369
 370 /*
 371  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 372  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 373  * current implementation, 4K are reserved to avoid future complications.
 374  */
 375 #define VMCS12_SIZE 0x1000
 376
 377 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 378 struct vmcs02_list {
 379         struct list_head list;
 380         gpa_t vmptr;
 381         struct loaded_vmcs vmcs02;
 382 };
 383
 384 /*
 385  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 386  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 387  */
 388 struct nested_vmx {
 389         /* Has the level1 guest done vmxon? */
 390         bool vmxon;
 391         gpa_t vmxon_ptr;
 392
 393         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 394         gpa_t current_vmptr;
 395         /* The host-usable pointer to the above */
 396         struct page *current_vmcs12_page;
 397         struct vmcs12 *current_vmcs12;
 398         struct vmcs *current_shadow_vmcs;
 399         /*
 400          * Indicates if the shadow vmcs must be updated with the
 401          * data hold by vmcs12
 402          */
 403         bool sync_shadow_vmcs;
 404
 405         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 406         struct list_head vmcs02_pool;
 407         int vmcs02_num;
 408         u64 vmcs01_tsc_offset;
 409         /* L2 must run next, and mustn't decide to exit to L1. */
 410         bool nested_run_pending;
 411         /*
 412          * Guest pages referred to in vmcs02 with host-physical pointers, so
 413          * we must keep them pinned while L2 runs.
 414          */
 415         struct page *apic_access_page;
 416         struct page *virtual_apic_page;
 417         struct page *pi_desc_page;
 418         struct pi_desc *pi_desc;
 419         bool pi_pending;
 420         u16 posted_intr_nv;
 421         u64 msr_ia32_feature_control;
 422
 423         struct hrtimer preemption_timer;
 424         bool preemption_timer_expired;
 425
 426         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 427         u64 vmcs01_debugctl;
 428
 429         u32 nested_vmx_procbased_ctls_low;
 430         u32 nested_vmx_procbased_ctls_high;
 431         u32 nested_vmx_true_procbased_ctls_low;
 432         u32 nested_vmx_secondary_ctls_low;
 433         u32 nested_vmx_secondary_ctls_high;
 434         u32 nested_vmx_pinbased_ctls_low;
 435         u32 nested_vmx_pinbased_ctls_high;
 436         u32 nested_vmx_exit_ctls_low;
 437         u32 nested_vmx_exit_ctls_high;
 438         u32 nested_vmx_true_exit_ctls_low;
 439         u32 nested_vmx_entry_ctls_low;
 440         u32 nested_vmx_entry_ctls_high;
 441         u32 nested_vmx_true_entry_ctls_low;
 442         u32 nested_vmx_misc_low;
 443         u32 nested_vmx_misc_high;
 444         u32 nested_vmx_ept_caps;
 445         u32 nested_vmx_vpid_caps;
 446 };
 447
 448 #define POSTED_INTR_ON  0
 449 #define POSTED_INTR_SN  1
 450
 451 /* Posted-Interrupt Descriptor */
 452 struct pi_desc {
 453         u32 pir[8];     /* Posted interrupt requested */
 454         union {
 455                 struct {
 456                                 /* bit 256 - Outstanding Notification */
 457                         u16     on      : 1,
 458                                 /* bit 257 - Suppress Notification */
 459                                 sn      : 1,
 460                                 /* bit 271:258 - Reserved */
 461                                 rsvd_1  : 14;
 462                                 /* bit 279:272 - Notification Vector */
 463                         u8      nv;
 464                                 /* bit 287:280 - Reserved */
 465                         u8      rsvd_2;
 466                                 /* bit 319:288 - Notification Destination */
 467                         u32     ndst;
 468                 };
 469                 u64 control;
 470         };
 471         u32 rsvd[6];
 472 } __aligned(64);
 473
 474 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 475 {
 476         return test_and_set_bit(POSTED_INTR_ON,
 477                         (unsigned long *)&pi_desc->control);
 478 }
 479
 480 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_clear_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 487 {
 488         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 489 }
 490
 491 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 492 {
 493         return clear_bit(POSTED_INTR_SN,
 494                         (unsigned long *)&pi_desc->control);
 495 }
 496
 497 static inline void pi_set_sn(struct pi_desc *pi_desc)
 498 {
 499         return set_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline int pi_test_on(struct pi_desc *pi_desc)
 504 {
 505         return test_bit(POSTED_INTR_ON,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_sn(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_SN,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 struct vcpu_vmx {
 516         struct kvm_vcpu       vcpu;
 517         unsigned long         host_rsp;
 518         u8                    fail;
 519         bool                  nmi_known_unmasked;
 520         u32                   exit_intr_info;
 521         u32                   idt_vectoring_info;
 522         ulong                 rflags;
 523         struct shared_msr_entry *guest_msrs;
 524         int                   nmsrs;
 525         int                   save_nmsrs;
 526         unsigned long         host_idt_base;
 527 #ifdef CONFIG_X86_64
 528         u64                   msr_host_kernel_gs_base;
 529         u64                   msr_guest_kernel_gs_base;
 530 #endif
 531         u32 vm_entry_controls_shadow;
 532         u32 vm_exit_controls_shadow;
 533         /*
 534          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 535          * non-nested (L1) guest, it always points to vmcs01. For a nested
 536          * guest (L2), it points to a different VMCS.
 537          */
 538         struct loaded_vmcs    vmcs01;
 539         struct loaded_vmcs   *loaded_vmcs;
 540         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 541         struct msr_autoload {
 542                 unsigned nr;
 543                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 544                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 545         } msr_autoload;
 546         struct {
 547                 int           loaded;
 548                 u16           fs_sel, gs_sel, ldt_sel;
 549 #ifdef CONFIG_X86_64
 550                 u16           ds_sel, es_sel;
 551 #endif
 552                 int           gs_ldt_reload_needed;
 553                 int           fs_reload_needed;
 554                 u64           msr_host_bndcfgs;
 555                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 556         } host_state;
 557         struct {
 558                 int vm86_active;
 559                 ulong save_rflags;
 560                 struct kvm_segment segs[8];
 561         } rmode;
 562         struct {
 563                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 564                 struct kvm_save_segment {
 565                         u16 selector;
 566                         unsigned long base;
 567                         u32 limit;
 568                         u32 ar;
 569                 } seg[8];
 570         } segment_cache;
 571         int vpid;
 572         bool emulation_required;
 573
 574         /* Support for vnmi-less CPUs */
 575         int soft_vnmi_blocked;
 576         ktime_t entry_time;
 577         s64 vnmi_blocked_time;
 578         u32 exit_reason;
 579
 580         /* Posted interrupt descriptor */
 581         struct pi_desc pi_desc;
 582
 583         /* Support for a guest hypervisor (nested VMX) */
 584         struct nested_vmx nested;
 585
 586         /* Dynamic PLE window. */
 587         int ple_window;
 588         bool ple_window_dirty;
 589
 590         /* Support for PML */
 591 #define PML_ENTITY_NUM          512
 592         struct page *pml_pg;
 593 };
 594
 595 enum segment_cache_field {
 596         SEG_FIELD_SEL = 0,
 597         SEG_FIELD_BASE = 1,
 598         SEG_FIELD_LIMIT = 2,
 599         SEG_FIELD_AR = 3,
 600
 601         SEG_FIELD_NR = 4
 602 };
 603
 604 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 605 {
 606         return container_of(vcpu, struct vcpu_vmx, vcpu);
 607 }
 608
 609 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 610 {
 611         return &(to_vmx(vcpu)->pi_desc);
 612 }
 613
 614 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 615 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 616 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 617                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 618
 619
 620 static unsigned long shadow_read_only_fields[] = {
 621         /*
 622          * We do NOT shadow fields that are modified when L0
 623          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 624          * VMXON...) executed by L1.
 625          * For example, VM_INSTRUCTION_ERROR is read
 626          * by L1 if a vmx instruction fails (part of the error path).
 627          * Note the code assumes this logic. If for some reason
 628          * we start shadowing these fields then we need to
 629          * force a shadow sync when L0 emulates vmx instructions
 630          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 631          * by nested_vmx_failValid)
 632          */
 633         VM_EXIT_REASON,
 634         VM_EXIT_INTR_INFO,
 635         VM_EXIT_INSTRUCTION_LEN,
 636         IDT_VECTORING_INFO_FIELD,
 637         IDT_VECTORING_ERROR_CODE,
 638         VM_EXIT_INTR_ERROR_CODE,
 639         EXIT_QUALIFICATION,
 640         GUEST_LINEAR_ADDRESS,
 641         GUEST_PHYSICAL_ADDRESS
 642 };
 643 static int max_shadow_read_only_fields =
 644         ARRAY_SIZE(shadow_read_only_fields);
 645
 646 static unsigned long shadow_read_write_fields[] = {
 647         TPR_THRESHOLD,
 648         GUEST_RIP,
 649         GUEST_RSP,
 650         GUEST_CR0,
 651         GUEST_CR3,
 652         GUEST_CR4,
 653         GUEST_INTERRUPTIBILITY_INFO,
 654         GUEST_RFLAGS,
 655         GUEST_CS_SELECTOR,
 656         GUEST_CS_AR_BYTES,
 657         GUEST_CS_LIMIT,
 658         GUEST_CS_BASE,
 659         GUEST_ES_BASE,
 660         GUEST_BNDCFGS,
 661         CR0_GUEST_HOST_MASK,
 662         CR0_READ_SHADOW,
 663         CR4_READ_SHADOW,
 664         TSC_OFFSET,
 665         EXCEPTION_BITMAP,
 666         CPU_BASED_VM_EXEC_CONTROL,
 667         VM_ENTRY_EXCEPTION_ERROR_CODE,
 668         VM_ENTRY_INTR_INFO_FIELD,
 669         VM_ENTRY_INSTRUCTION_LEN,
 670         VM_ENTRY_EXCEPTION_ERROR_CODE,
 671         HOST_FS_BASE,
 672         HOST_GS_BASE,
 673         HOST_FS_SELECTOR,
 674         HOST_GS_SELECTOR
 675 };
 676 static int max_shadow_read_write_fields =
 677         ARRAY_SIZE(shadow_read_write_fields);
 678
 679 static const unsigned short vmcs_field_to_offset_table[] = {
 680         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 681         FIELD(POSTED_INTR_NV, posted_intr_nv),
 682         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 683         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 684         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 685         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 686         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 687         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 688         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 689         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 690         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 691         FIELD(HOST_ES_SELECTOR, host_es_selector),
 692         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 693         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 694         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 695         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 696         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 697         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 698         FIELD64(IO_BITMAP_A, io_bitmap_a),
 699         FIELD64(IO_BITMAP_B, io_bitmap_b),
 700         FIELD64(MSR_BITMAP, msr_bitmap),
 701         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 702         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 703         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 704         FIELD64(TSC_OFFSET, tsc_offset),
 705         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 706         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 707         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 708         FIELD64(EPT_POINTER, ept_pointer),
 709         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 710         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 711         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 712         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 713         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 714         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 715         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 716         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 717         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 718         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 719         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 720         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 721         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 722         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 723         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 724         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 725         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 726         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 727         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 728         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 729         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 730         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 731         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 732         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 733         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 734         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 735         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 736         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 737         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 738         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 739         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 740         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 741         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 742         FIELD(TPR_THRESHOLD, tpr_threshold),
 743         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 744         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 745         FIELD(VM_EXIT_REASON, vm_exit_reason),
 746         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 747         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 748         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 749         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 750         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 751         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 752         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 753         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 754         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 755         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 756         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 757         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 758         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 759         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 760         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 761         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 762         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 763         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 764         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 765         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 766         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 767         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 768         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 769         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 770         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 771         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 772         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 773         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 774         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 775         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 776         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 777         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 778         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 779         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 780         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 781         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 782         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 783         FIELD(EXIT_QUALIFICATION, exit_qualification),
 784         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 785         FIELD(GUEST_CR0, guest_cr0),
 786         FIELD(GUEST_CR3, guest_cr3),
 787         FIELD(GUEST_CR4, guest_cr4),
 788         FIELD(GUEST_ES_BASE, guest_es_base),
 789         FIELD(GUEST_CS_BASE, guest_cs_base),
 790         FIELD(GUEST_SS_BASE, guest_ss_base),
 791         FIELD(GUEST_DS_BASE, guest_ds_base),
 792         FIELD(GUEST_FS_BASE, guest_fs_base),
 793         FIELD(GUEST_GS_BASE, guest_gs_base),
 794         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 795         FIELD(GUEST_TR_BASE, guest_tr_base),
 796         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 797         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 798         FIELD(GUEST_DR7, guest_dr7),
 799         FIELD(GUEST_RSP, guest_rsp),
 800         FIELD(GUEST_RIP, guest_rip),
 801         FIELD(GUEST_RFLAGS, guest_rflags),
 802         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 803         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 804         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 805         FIELD(HOST_CR0, host_cr0),
 806         FIELD(HOST_CR3, host_cr3),
 807         FIELD(HOST_CR4, host_cr4),
 808         FIELD(HOST_FS_BASE, host_fs_base),
 809         FIELD(HOST_GS_BASE, host_gs_base),
 810         FIELD(HOST_TR_BASE, host_tr_base),
 811         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 812         FIELD(HOST_IDTR_BASE, host_idtr_base),
 813         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 814         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 815         FIELD(HOST_RSP, host_rsp),
 816         FIELD(HOST_RIP, host_rip),
 817 };
 818
 819 static inline short vmcs_field_to_offset(unsigned long field)
 820 {
 821         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 822
 823         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 824             vmcs_field_to_offset_table[field] == 0)
 825                 return -ENOENT;
 826
 827         return vmcs_field_to_offset_table[field];
 828 }
 829
 830 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 831 {
 832         return to_vmx(vcpu)->nested.current_vmcs12;
 833 }
 834
 835 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 836 {
 837         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 838         if (is_error_page(page))
 839                 return NULL;
 840
 841         return page;
 842 }
 843
 844 static void nested_release_page(struct page *page)
 845 {
 846         kvm_release_page_dirty(page);
 847 }
 848
 849 static void nested_release_page_clean(struct page *page)
 850 {
 851         kvm_release_page_clean(page);
 852 }
 853
 854 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 855 static u64 construct_eptp(unsigned long root_hpa);
 856 static void kvm_cpu_vmxon(u64 addr);
 857 static void kvm_cpu_vmxoff(void);
 858 static bool vmx_mpx_supported(void);
 859 static bool vmx_xsaves_supported(void);
 860 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 861 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 862 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 863                             struct kvm_segment *var, int seg);
 864 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 865                             struct kvm_segment *var, int seg);
 866 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 867 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 868 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 869 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 870 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 871 static int alloc_identity_pagetable(struct kvm *kvm);
 872
 873 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 874 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 875 /*
 876  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 877  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 878  */
 879 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 880 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 881
 882 /*
 883  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 884  * can find which vCPU should be waken up.
 885  */
 886 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 887 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 888
 889 static unsigned long *vmx_io_bitmap_a;
 890 static unsigned long *vmx_io_bitmap_b;
 891 static unsigned long *vmx_msr_bitmap_legacy;
 892 static unsigned long *vmx_msr_bitmap_longmode;
 893 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 894 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 895 static unsigned long *vmx_msr_bitmap_nested;
 896 static unsigned long *vmx_vmread_bitmap;
 897 static unsigned long *vmx_vmwrite_bitmap;
 898
 899 static bool cpu_has_load_ia32_efer;
 900 static bool cpu_has_load_perf_global_ctrl;
 901
 902 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 903 static DEFINE_SPINLOCK(vmx_vpid_lock);
 904
 905 static struct vmcs_config {
 906         int size;
 907         int order;
 908         u32 revision_id;
 909         u32 pin_based_exec_ctrl;
 910         u32 cpu_based_exec_ctrl;
 911         u32 cpu_based_2nd_exec_ctrl;
 912         u32 vmexit_ctrl;
 913         u32 vmentry_ctrl;
 914 } vmcs_config;
 915
 916 static struct vmx_capability {
 917         u32 ept;
 918         u32 vpid;
 919 } vmx_capability;
 920
 921 #define VMX_SEGMENT_FIELD(seg)                                  \
 922         [VCPU_SREG_##seg] = {                                   \
 923                 .selector = GUEST_##seg##_SELECTOR,             \
 924                 .base = GUEST_##seg##_BASE,                     \
 925                 .limit = GUEST_##seg##_LIMIT,                   \
 926                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 927         }
 928
 929 static const struct kvm_vmx_segment_field {
 930         unsigned selector;
 931         unsigned base;
 932         unsigned limit;
 933         unsigned ar_bytes;
 934 } kvm_vmx_segment_fields[] = {
 935         VMX_SEGMENT_FIELD(CS),
 936         VMX_SEGMENT_FIELD(DS),
 937         VMX_SEGMENT_FIELD(ES),
 938         VMX_SEGMENT_FIELD(FS),
 939         VMX_SEGMENT_FIELD(GS),
 940         VMX_SEGMENT_FIELD(SS),
 941         VMX_SEGMENT_FIELD(TR),
 942         VMX_SEGMENT_FIELD(LDTR),
 943 };
 944
 945 static u64 host_efer;
 946
 947 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 948
 949 /*
 950  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 951  * away by decrementing the array size.
 952  */
 953 static const u32 vmx_msr_index[] = {
 954 #ifdef CONFIG_X86_64
 955         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 956 #endif
 957         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 958 };
 959
 960 static inline bool is_page_fault(u32 intr_info)
 961 {
 962         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 963                              INTR_INFO_VALID_MASK)) ==
 964                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 965 }
 966
 967 static inline bool is_no_device(u32 intr_info)
 968 {
 969         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 970                              INTR_INFO_VALID_MASK)) ==
 971                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 972 }
 973
 974 static inline bool is_invalid_opcode(u32 intr_info)
 975 {
 976         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 977                              INTR_INFO_VALID_MASK)) ==
 978                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 979 }
 980
 981 static inline bool is_external_interrupt(u32 intr_info)
 982 {
 983         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 984                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 985 }
 986
 987 static inline bool is_machine_check(u32 intr_info)
 988 {
 989         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 990                              INTR_INFO_VALID_MASK)) ==
 991                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 992 }
 993
 994 static inline bool cpu_has_vmx_msr_bitmap(void)
 995 {
 996         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 997 }
 998
 999 static inline bool cpu_has_vmx_tpr_shadow(void)
1000 {
1001         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1002 }
1003
1004 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1005 {
1006         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1007 }
1008
1009 static inline bool cpu_has_secondary_exec_ctrls(void)
1010 {
1011         return vmcs_config.cpu_based_exec_ctrl &
1012                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1013 }
1014
1015 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1016 {
1017         return vmcs_config.cpu_based_2nd_exec_ctrl &
1018                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1019 }
1020
1021 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1022 {
1023         return vmcs_config.cpu_based_2nd_exec_ctrl &
1024                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1025 }
1026
1027 static inline bool cpu_has_vmx_apic_register_virt(void)
1028 {
1029         return vmcs_config.cpu_based_2nd_exec_ctrl &
1030                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1031 }
1032
1033 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1034 {
1035         return vmcs_config.cpu_based_2nd_exec_ctrl &
1036                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1037 }
1038
1039 static inline bool cpu_has_vmx_posted_intr(void)
1040 {
1041         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1042                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1043 }
1044
1045 static inline bool cpu_has_vmx_apicv(void)
1046 {
1047         return cpu_has_vmx_apic_register_virt() &&
1048                 cpu_has_vmx_virtual_intr_delivery() &&
1049                 cpu_has_vmx_posted_intr();
1050 }
1051
1052 static inline bool cpu_has_vmx_flexpriority(void)
1053 {
1054         return cpu_has_vmx_tpr_shadow() &&
1055                 cpu_has_vmx_virtualize_apic_accesses();
1056 }
1057
1058 static inline bool cpu_has_vmx_ept_execute_only(void)
1059 {
1060         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1061 }
1062
1063 static inline bool cpu_has_vmx_ept_2m_page(void)
1064 {
1065         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1066 }
1067
1068 static inline bool cpu_has_vmx_ept_1g_page(void)
1069 {
1070         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1071 }
1072
1073 static inline bool cpu_has_vmx_ept_4levels(void)
1074 {
1075         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_ad_bits(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_AD_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_invept_context(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_invept_global(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_invvpid_single(void)
1094 {
1095         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_invvpid_global(void)
1099 {
1100         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_ept(void)
1104 {
1105         return vmcs_config.cpu_based_2nd_exec_ctrl &
1106                 SECONDARY_EXEC_ENABLE_EPT;
1107 }
1108
1109 static inline bool cpu_has_vmx_unrestricted_guest(void)
1110 {
1111         return vmcs_config.cpu_based_2nd_exec_ctrl &
1112                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1113 }
1114
1115 static inline bool cpu_has_vmx_ple(void)
1116 {
1117         return vmcs_config.cpu_based_2nd_exec_ctrl &
1118                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1119 }
1120
1121 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1122 {
1123         return flexpriority_enabled && lapic_in_kernel(vcpu);
1124 }
1125
1126 static inline bool cpu_has_vmx_vpid(void)
1127 {
1128         return vmcs_config.cpu_based_2nd_exec_ctrl &
1129                 SECONDARY_EXEC_ENABLE_VPID;
1130 }
1131
1132 static inline bool cpu_has_vmx_rdtscp(void)
1133 {
1134         return vmcs_config.cpu_based_2nd_exec_ctrl &
1135                 SECONDARY_EXEC_RDTSCP;
1136 }
1137
1138 static inline bool cpu_has_vmx_invpcid(void)
1139 {
1140         return vmcs_config.cpu_based_2nd_exec_ctrl &
1141                 SECONDARY_EXEC_ENABLE_INVPCID;
1142 }
1143
1144 static inline bool cpu_has_virtual_nmis(void)
1145 {
1146         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1147 }
1148
1149 static inline bool cpu_has_vmx_wbinvd_exit(void)
1150 {
1151         return vmcs_config.cpu_based_2nd_exec_ctrl &
1152                 SECONDARY_EXEC_WBINVD_EXITING;
1153 }
1154
1155 static inline bool cpu_has_vmx_shadow_vmcs(void)
1156 {
1157         u64 vmx_msr;
1158         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1159         /* check if the cpu supports writing r/o exit information fields */
1160         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1161                 return false;
1162
1163         return vmcs_config.cpu_based_2nd_exec_ctrl &
1164                 SECONDARY_EXEC_SHADOW_VMCS;
1165 }
1166
1167 static inline bool cpu_has_vmx_pml(void)
1168 {
1169         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1170 }
1171
1172 static inline bool report_flexpriority(void)
1173 {
1174         return flexpriority_enabled;
1175 }
1176
1177 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1178 {
1179         return vmcs12->cpu_based_vm_exec_control & bit;
1180 }
1181
1182 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1183 {
1184         return (vmcs12->cpu_based_vm_exec_control &
1185                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1186                 (vmcs12->secondary_vm_exec_control & bit);
1187 }
1188
1189 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1190 {
1191         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1192 }
1193
1194 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1195 {
1196         return vmcs12->pin_based_vm_exec_control &
1197                 PIN_BASED_VMX_PREEMPTION_TIMER;
1198 }
1199
1200 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1201 {
1202         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1203 }
1204
1205 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1206 {
1207         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1208                 vmx_xsaves_supported();
1209 }
1210
1211 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1212 {
1213         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1214 }
1215
1216 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1217 {
1218         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1219 }
1220
1221 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1222 {
1223         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1224 }
1225
1226 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1227 {
1228         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1229 }
1230
1231 static inline bool is_exception(u32 intr_info)
1232 {
1233         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1234                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1235 }
1236
1237 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1238                               u32 exit_intr_info,
1239                               unsigned long exit_qualification);
1240 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1241                         struct vmcs12 *vmcs12,
1242                         u32 reason, unsigned long qualification);
1243
1244 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1245 {
1246         int i;
1247
1248         for (i = 0; i < vmx->nmsrs; ++i)
1249                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1250                         return i;
1251         return -1;
1252 }
1253
1254 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1255 {
1256     struct {
1257         u64 vpid : 16;
1258         u64 rsvd : 48;
1259         u64 gva;
1260     } operand = { vpid, 0, gva };
1261
1262     asm volatile (__ex(ASM_VMX_INVVPID)
1263                   /* CF==1 or ZF==1 --> rc = -1 */
1264                   "; ja 1f ; ud2 ; 1:"
1265                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1266 }
1267
1268 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1269 {
1270         struct {
1271                 u64 eptp, gpa;
1272         } operand = {eptp, gpa};
1273
1274         asm volatile (__ex(ASM_VMX_INVEPT)
1275                         /* CF==1 or ZF==1 --> rc = -1 */
1276                         "; ja 1f ; ud2 ; 1:\n"
1277                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1278 }
1279
1280 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1281 {
1282         int i;
1283
1284         i = __find_msr_index(vmx, msr);
1285         if (i >= 0)
1286                 return &vmx->guest_msrs[i];
1287         return NULL;
1288 }
1289
1290 static void vmcs_clear(struct vmcs *vmcs)
1291 {
1292         u64 phys_addr = __pa(vmcs);
1293         u8 error;
1294
1295         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1296                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1297                       : "cc", "memory");
1298         if (error)
1299                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1300                        vmcs, phys_addr);
1301 }
1302
1303 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1304 {
1305         vmcs_clear(loaded_vmcs->vmcs);
1306         loaded_vmcs->cpu = -1;
1307         loaded_vmcs->launched = 0;
1308 }
1309
1310 static void vmcs_load(struct vmcs *vmcs)
1311 {
1312         u64 phys_addr = __pa(vmcs);
1313         u8 error;
1314
1315         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1316                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1317                         : "cc", "memory");
1318         if (error)
1319                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1320                        vmcs, phys_addr);
1321 }
1322
1323 #ifdef CONFIG_KEXEC_CORE
1324 /*
1325  * This bitmap is used to indicate whether the vmclear
1326  * operation is enabled on all cpus. All disabled by
1327  * default.
1328  */
1329 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1330
1331 static inline void crash_enable_local_vmclear(int cpu)
1332 {
1333         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1334 }
1335
1336 static inline void crash_disable_local_vmclear(int cpu)
1337 {
1338         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1339 }
1340
1341 static inline int crash_local_vmclear_enabled(int cpu)
1342 {
1343         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1344 }
1345
1346 static void crash_vmclear_local_loaded_vmcss(void)
1347 {
1348         int cpu = raw_smp_processor_id();
1349         struct loaded_vmcs *v;
1350
1351         if (!crash_local_vmclear_enabled(cpu))
1352                 return;
1353
1354         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1355                             loaded_vmcss_on_cpu_link)
1356                 vmcs_clear(v->vmcs);
1357 }
1358 #else
1359 static inline void crash_enable_local_vmclear(int cpu) { }
1360 static inline void crash_disable_local_vmclear(int cpu) { }
1361 #endif /* CONFIG_KEXEC_CORE */
1362
1363 static void __loaded_vmcs_clear(void *arg)
1364 {
1365         struct loaded_vmcs *loaded_vmcs = arg;
1366         int cpu = raw_smp_processor_id();
1367
1368         if (loaded_vmcs->cpu != cpu)
1369                 return; /* vcpu migration can race with cpu offline */
1370         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1371                 per_cpu(current_vmcs, cpu) = NULL;
1372         crash_disable_local_vmclear(cpu);
1373         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1374
1375         /*
1376          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1377          * is before setting loaded_vmcs->vcpu to -1 which is done in
1378          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1379          * then adds the vmcs into percpu list before it is deleted.
1380          */
1381         smp_wmb();
1382
1383         loaded_vmcs_init(loaded_vmcs);
1384         crash_enable_local_vmclear(cpu);
1385 }
1386
1387 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1388 {
1389         int cpu = loaded_vmcs->cpu;
1390
1391         if (cpu != -1)
1392                 smp_call_function_single(cpu,
1393                          __loaded_vmcs_clear, loaded_vmcs, 1);
1394 }
1395
1396 static inline void vpid_sync_vcpu_single(int vpid)
1397 {
1398         if (vpid == 0)
1399                 return;
1400
1401         if (cpu_has_vmx_invvpid_single())
1402                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1403 }
1404
1405 static inline void vpid_sync_vcpu_global(void)
1406 {
1407         if (cpu_has_vmx_invvpid_global())
1408                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1409 }
1410
1411 static inline void vpid_sync_context(int vpid)
1412 {
1413         if (cpu_has_vmx_invvpid_single())
1414                 vpid_sync_vcpu_single(vpid);
1415         else
1416                 vpid_sync_vcpu_global();
1417 }
1418
1419 static inline void ept_sync_global(void)
1420 {
1421         if (cpu_has_vmx_invept_global())
1422                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1423 }
1424
1425 static inline void ept_sync_context(u64 eptp)
1426 {
1427         if (enable_ept) {
1428                 if (cpu_has_vmx_invept_context())
1429                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1430                 else
1431                         ept_sync_global();
1432         }
1433 }
1434
1435 static __always_inline unsigned long vmcs_readl(unsigned long field)
1436 {
1437         unsigned long value;
1438
1439         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1440                       : "=a"(value) : "d"(field) : "cc");
1441         return value;
1442 }
1443
1444 static __always_inline u16 vmcs_read16(unsigned long field)
1445 {
1446         return vmcs_readl(field);
1447 }
1448
1449 static __always_inline u32 vmcs_read32(unsigned long field)
1450 {
1451         return vmcs_readl(field);
1452 }
1453
1454 static __always_inline u64 vmcs_read64(unsigned long field)
1455 {
1456 #ifdef CONFIG_X86_64
1457         return vmcs_readl(field);
1458 #else
1459         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1460 #endif
1461 }
1462
1463 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1464 {
1465         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1466                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1467         dump_stack();
1468 }
1469
1470 static void vmcs_writel(unsigned long field, unsigned long value)
1471 {
1472         u8 error;
1473
1474         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1475                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1476         if (unlikely(error))
1477                 vmwrite_error(field, value);
1478 }
1479
1480 static void vmcs_write16(unsigned long field, u16 value)
1481 {
1482         vmcs_writel(field, value);
1483 }
1484
1485 static void vmcs_write32(unsigned long field, u32 value)
1486 {
1487         vmcs_writel(field, value);
1488 }
1489
1490 static void vmcs_write64(unsigned long field, u64 value)
1491 {
1492         vmcs_writel(field, value);
1493 #ifndef CONFIG_X86_64
1494         asm volatile ("");
1495         vmcs_writel(field+1, value >> 32);
1496 #endif
1497 }
1498
1499 static void vmcs_clear_bits(unsigned long field, u32 mask)
1500 {
1501         vmcs_writel(field, vmcs_readl(field) & ~mask);
1502 }
1503
1504 static void vmcs_set_bits(unsigned long field, u32 mask)
1505 {
1506         vmcs_writel(field, vmcs_readl(field) | mask);
1507 }
1508
1509 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1510 {
1511         vmcs_write32(VM_ENTRY_CONTROLS, val);
1512         vmx->vm_entry_controls_shadow = val;
1513 }
1514
1515 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1516 {
1517         if (vmx->vm_entry_controls_shadow != val)
1518                 vm_entry_controls_init(vmx, val);
1519 }
1520
1521 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1522 {
1523         return vmx->vm_entry_controls_shadow;
1524 }
1525
1526
1527 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1528 {
1529         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1530 }
1531
1532 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1533 {
1534         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1535 }
1536
1537 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1538 {
1539         vmcs_write32(VM_EXIT_CONTROLS, val);
1540         vmx->vm_exit_controls_shadow = val;
1541 }
1542
1543 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1544 {
1545         if (vmx->vm_exit_controls_shadow != val)
1546                 vm_exit_controls_init(vmx, val);
1547 }
1548
1549 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1550 {
1551         return vmx->vm_exit_controls_shadow;
1552 }
1553
1554
1555 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1556 {
1557         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1558 }
1559
1560 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1561 {
1562         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1563 }
1564
1565 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1566 {
1567         vmx->segment_cache.bitmask = 0;
1568 }
1569
1570 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1571                                        unsigned field)
1572 {
1573         bool ret;
1574         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1575
1576         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1577                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1578                 vmx->segment_cache.bitmask = 0;
1579         }
1580         ret = vmx->segment_cache.bitmask & mask;
1581         vmx->segment_cache.bitmask |= mask;
1582         return ret;
1583 }
1584
1585 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1586 {
1587         u16 *p = &vmx->segment_cache.seg[seg].selector;
1588
1589         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1590                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1591         return *p;
1592 }
1593
1594 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1595 {
1596         ulong *p = &vmx->segment_cache.seg[seg].base;
1597
1598         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1599                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1600         return *p;
1601 }
1602
1603 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1604 {
1605         u32 *p = &vmx->segment_cache.seg[seg].limit;
1606
1607         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1608                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1609         return *p;
1610 }
1611
1612 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1613 {
1614         u32 *p = &vmx->segment_cache.seg[seg].ar;
1615
1616         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1617                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1618         return *p;
1619 }
1620
1621 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1622 {
1623         u32 eb;
1624
1625         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1626              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1627         if ((vcpu->guest_debug &
1628              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1629             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1630                 eb |= 1u << BP_VECTOR;
1631         if (to_vmx(vcpu)->rmode.vm86_active)
1632                 eb = ~0;
1633         if (enable_ept)
1634                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1635         if (vcpu->fpu_active)
1636                 eb &= ~(1u << NM_VECTOR);
1637
1638         /* When we are running a nested L2 guest and L1 specified for it a
1639          * certain exception bitmap, we must trap the same exceptions and pass
1640          * them to L1. When running L2, we will only handle the exceptions
1641          * specified above if L1 did not want them.
1642          */
1643         if (is_guest_mode(vcpu))
1644                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1645
1646         vmcs_write32(EXCEPTION_BITMAP, eb);
1647 }
1648
1649 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1650                 unsigned long entry, unsigned long exit)
1651 {
1652         vm_entry_controls_clearbit(vmx, entry);
1653         vm_exit_controls_clearbit(vmx, exit);
1654 }
1655
1656 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1657 {
1658         unsigned i;
1659         struct msr_autoload *m = &vmx->msr_autoload;
1660
1661         switch (msr) {
1662         case MSR_EFER:
1663                 if (cpu_has_load_ia32_efer) {
1664                         clear_atomic_switch_msr_special(vmx,
1665                                         VM_ENTRY_LOAD_IA32_EFER,
1666                                         VM_EXIT_LOAD_IA32_EFER);
1667                         return;
1668                 }
1669                 break;
1670         case MSR_CORE_PERF_GLOBAL_CTRL:
1671                 if (cpu_has_load_perf_global_ctrl) {
1672                         clear_atomic_switch_msr_special(vmx,
1673                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1674                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1675                         return;
1676                 }
1677                 break;
1678         }
1679
1680         for (i = 0; i < m->nr; ++i)
1681                 if (m->guest[i].index == msr)
1682                         break;
1683
1684         if (i == m->nr)
1685                 return;
1686         --m->nr;
1687         m->guest[i] = m->guest[m->nr];
1688         m->host[i] = m->host[m->nr];
1689         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691 }
1692
1693 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1694                 unsigned long entry, unsigned long exit,
1695                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1696                 u64 guest_val, u64 host_val)
1697 {
1698         vmcs_write64(guest_val_vmcs, guest_val);
1699         vmcs_write64(host_val_vmcs, host_val);
1700         vm_entry_controls_setbit(vmx, entry);
1701         vm_exit_controls_setbit(vmx, exit);
1702 }
1703
1704 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1705                                   u64 guest_val, u64 host_val)
1706 {
1707         unsigned i;
1708         struct msr_autoload *m = &vmx->msr_autoload;
1709
1710         switch (msr) {
1711         case MSR_EFER:
1712                 if (cpu_has_load_ia32_efer) {
1713                         add_atomic_switch_msr_special(vmx,
1714                                         VM_ENTRY_LOAD_IA32_EFER,
1715                                         VM_EXIT_LOAD_IA32_EFER,
1716                                         GUEST_IA32_EFER,
1717                                         HOST_IA32_EFER,
1718                                         guest_val, host_val);
1719                         return;
1720                 }
1721                 break;
1722         case MSR_CORE_PERF_GLOBAL_CTRL:
1723                 if (cpu_has_load_perf_global_ctrl) {
1724                         add_atomic_switch_msr_special(vmx,
1725                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1726                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1727                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1728                                         HOST_IA32_PERF_GLOBAL_CTRL,
1729                                         guest_val, host_val);
1730                         return;
1731                 }
1732                 break;
1733         }
1734
1735         for (i = 0; i < m->nr; ++i)
1736                 if (m->guest[i].index == msr)
1737                         break;
1738
1739         if (i == NR_AUTOLOAD_MSRS) {
1740                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1741                                 "Can't add msr %x\n", msr);
1742                 return;
1743         } else if (i == m->nr) {
1744                 ++m->nr;
1745                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1746                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1747         }
1748
1749         m->guest[i].index = msr;
1750         m->guest[i].value = guest_val;
1751         m->host[i].index = msr;
1752         m->host[i].value = host_val;
1753 }
1754
1755 static void reload_tss(void)
1756 {
1757         /*
1758          * VT restores TR but not its size.  Useless.
1759          */
1760         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1761         struct desc_struct *descs;
1762
1763         descs = (void *)gdt->address;
1764         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1765         load_TR_desc();
1766 }
1767
1768 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1769 {
1770         u64 guest_efer;
1771         u64 ignore_bits;
1772
1773         guest_efer = vmx->vcpu.arch.efer;
1774
1775         /*
1776          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1777          * outside long mode
1778          */
1779         ignore_bits = EFER_NX | EFER_SCE;
1780 #ifdef CONFIG_X86_64
1781         ignore_bits |= EFER_LMA | EFER_LME;
1782         /* SCE is meaningful only in long mode on Intel */
1783         if (guest_efer & EFER_LMA)
1784                 ignore_bits &= ~(u64)EFER_SCE;
1785 #endif
1786         guest_efer &= ~ignore_bits;
1787         guest_efer |= host_efer & ignore_bits;
1788         vmx->guest_msrs[efer_offset].data = guest_efer;
1789         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1790
1791         clear_atomic_switch_msr(vmx, MSR_EFER);
1792
1793         /*
1794          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1795          * On CPUs that support "load IA32_EFER", always switch EFER
1796          * atomically, since it's faster than switching it manually.
1797          */
1798         if (cpu_has_load_ia32_efer ||
1799             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1800                 guest_efer = vmx->vcpu.arch.efer;
1801                 if (!(guest_efer & EFER_LMA))
1802                         guest_efer &= ~EFER_LME;
1803                 if (guest_efer != host_efer)
1804                         add_atomic_switch_msr(vmx, MSR_EFER,
1805                                               guest_efer, host_efer);
1806                 return false;
1807         }
1808
1809         return true;
1810 }
1811
1812 static unsigned long segment_base(u16 selector)
1813 {
1814         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1815         struct desc_struct *d;
1816         unsigned long table_base;
1817         unsigned long v;
1818
1819         if (!(selector & ~3))
1820                 return 0;
1821
1822         table_base = gdt->address;
1823
1824         if (selector & 4) {           /* from ldt */
1825                 u16 ldt_selector = kvm_read_ldt();
1826
1827                 if (!(ldt_selector & ~3))
1828                         return 0;
1829
1830                 table_base = segment_base(ldt_selector);
1831         }
1832         d = (struct desc_struct *)(table_base + (selector & ~7));
1833         v = get_desc_base(d);
1834 #ifdef CONFIG_X86_64
1835        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1836                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1837 #endif
1838         return v;
1839 }
1840
1841 static inline unsigned long kvm_read_tr_base(void)
1842 {
1843         u16 tr;
1844         asm("str %0" : "=g"(tr));
1845         return segment_base(tr);
1846 }
1847
1848 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1849 {
1850         struct vcpu_vmx *vmx = to_vmx(vcpu);
1851         int i;
1852
1853         if (vmx->host_state.loaded)
1854                 return;
1855
1856         vmx->host_state.loaded = 1;
1857         /*
1858          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1859          * allow segment selectors with cpl > 0 or ti == 1.
1860          */
1861         vmx->host_state.ldt_sel = kvm_read_ldt();
1862         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1863         savesegment(fs, vmx->host_state.fs_sel);
1864         if (!(vmx->host_state.fs_sel & 7)) {
1865                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1866                 vmx->host_state.fs_reload_needed = 0;
1867         } else {
1868                 vmcs_write16(HOST_FS_SELECTOR, 0);
1869                 vmx->host_state.fs_reload_needed = 1;
1870         }
1871         savesegment(gs, vmx->host_state.gs_sel);
1872         if (!(vmx->host_state.gs_sel & 7))
1873                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1874         else {
1875                 vmcs_write16(HOST_GS_SELECTOR, 0);
1876                 vmx->host_state.gs_ldt_reload_needed = 1;
1877         }
1878
1879 #ifdef CONFIG_X86_64
1880         savesegment(ds, vmx->host_state.ds_sel);
1881         savesegment(es, vmx->host_state.es_sel);
1882 #endif
1883
1884 #ifdef CONFIG_X86_64
1885         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1886         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1887 #else
1888         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1889         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1890 #endif
1891
1892 #ifdef CONFIG_X86_64
1893         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1894         if (is_long_mode(&vmx->vcpu))
1895                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1896 #endif
1897         if (boot_cpu_has(X86_FEATURE_MPX))
1898                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1899         for (i = 0; i < vmx->save_nmsrs; ++i)
1900                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1901                                    vmx->guest_msrs[i].data,
1902                                    vmx->guest_msrs[i].mask);
1903 }
1904
1905 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1906 {
1907         if (!vmx->host_state.loaded)
1908                 return;
1909
1910         ++vmx->vcpu.stat.host_state_reload;
1911         vmx->host_state.loaded = 0;
1912 #ifdef CONFIG_X86_64
1913         if (is_long_mode(&vmx->vcpu))
1914                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1915 #endif
1916         if (vmx->host_state.gs_ldt_reload_needed) {
1917                 kvm_load_ldt(vmx->host_state.ldt_sel);
1918 #ifdef CONFIG_X86_64
1919                 load_gs_index(vmx->host_state.gs_sel);
1920 #else
1921                 loadsegment(gs, vmx->host_state.gs_sel);
1922 #endif
1923         }
1924         if (vmx->host_state.fs_reload_needed)
1925                 loadsegment(fs, vmx->host_state.fs_sel);
1926 #ifdef CONFIG_X86_64
1927         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1928                 loadsegment(ds, vmx->host_state.ds_sel);
1929                 loadsegment(es, vmx->host_state.es_sel);
1930         }
1931 #endif
1932         reload_tss();
1933 #ifdef CONFIG_X86_64
1934         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1935 #endif
1936         if (vmx->host_state.msr_host_bndcfgs)
1937                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1938         /*
1939          * If the FPU is not active (through the host task or
1940          * the guest vcpu), then restore the cr0.TS bit.
1941          */
1942         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1943                 stts();
1944         load_gdt(this_cpu_ptr(&host_gdt));
1945 }
1946
1947 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1948 {
1949         preempt_disable();
1950         __vmx_load_host_state(vmx);
1951         preempt_enable();
1952 }
1953
1954 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1955 {
1956         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1957         struct pi_desc old, new;
1958         unsigned int dest;
1959
1960         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1961                 !irq_remapping_cap(IRQ_POSTING_CAP))
1962                 return;
1963
1964         do {
1965                 old.control = new.control = pi_desc->control;
1966
1967                 /*
1968                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1969                  * are two possible cases:
1970                  * 1. After running 'pre_block', context switch
1971                  *    happened. For this case, 'sn' was set in
1972                  *    vmx_vcpu_put(), so we need to clear it here.
1973                  * 2. After running 'pre_block', we were blocked,
1974                  *    and woken up by some other guy. For this case,
1975                  *    we don't need to do anything, 'pi_post_block'
1976                  *    will do everything for us. However, we cannot
1977                  *    check whether it is case #1 or case #2 here
1978                  *    (maybe, not needed), so we also clear sn here,
1979                  *    I think it is not a big deal.
1980                  */
1981                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1982                         if (vcpu->cpu != cpu) {
1983                                 dest = cpu_physical_id(cpu);
1984
1985                                 if (x2apic_enabled())
1986                                         new.ndst = dest;
1987                                 else
1988                                         new.ndst = (dest << 8) & 0xFF00;
1989                         }
1990
1991                         /* set 'NV' to 'notification vector' */
1992                         new.nv = POSTED_INTR_VECTOR;
1993                 }
1994
1995                 /* Allow posting non-urgent interrupts */
1996                 new.sn = 0;
1997         } while (cmpxchg(&pi_desc->control, old.control,
1998                         new.control) != old.control);
1999 }
2000 /*
2001  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2002  * vcpu mutex is already taken.
2003  */
2004 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2005 {
2006         struct vcpu_vmx *vmx = to_vmx(vcpu);
2007         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2008
2009         if (!vmm_exclusive)
2010                 kvm_cpu_vmxon(phys_addr);
2011         else if (vmx->loaded_vmcs->cpu != cpu)
2012                 loaded_vmcs_clear(vmx->loaded_vmcs);
2013
2014         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2015                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2016                 vmcs_load(vmx->loaded_vmcs->vmcs);
2017         }
2018
2019         if (vmx->loaded_vmcs->cpu != cpu) {
2020                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2021                 unsigned long sysenter_esp;
2022
2023                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2024                 local_irq_disable();
2025                 crash_disable_local_vmclear(cpu);
2026
2027                 /*
2028                  * Read loaded_vmcs->cpu should be before fetching
2029                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2030                  * See the comments in __loaded_vmcs_clear().
2031                  */
2032                 smp_rmb();
2033
2034                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2035                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2036                 crash_enable_local_vmclear(cpu);
2037                 local_irq_enable();
2038
2039                 /*
2040                  * Linux uses per-cpu TSS and GDT, so set these when switching
2041                  * processors.
2042                  */
2043                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2044                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2045
2046                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2047                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2048                 vmx->loaded_vmcs->cpu = cpu;
2049         }
2050
2051         vmx_vcpu_pi_load(vcpu, cpu);
2052 }
2053
2054 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2055 {
2056         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2057
2058         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2059                 !irq_remapping_cap(IRQ_POSTING_CAP))
2060                 return;
2061
2062         /* Set SN when the vCPU is preempted */
2063         if (vcpu->preempted)
2064                 pi_set_sn(pi_desc);
2065 }
2066
2067 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2068 {
2069         vmx_vcpu_pi_put(vcpu);
2070
2071         __vmx_load_host_state(to_vmx(vcpu));
2072         if (!vmm_exclusive) {
2073                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2074                 vcpu->cpu = -1;
2075                 kvm_cpu_vmxoff();
2076         }
2077 }
2078
2079 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2080 {
2081         ulong cr0;
2082
2083         if (vcpu->fpu_active)
2084                 return;
2085         vcpu->fpu_active = 1;
2086         cr0 = vmcs_readl(GUEST_CR0);
2087         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2088         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2089         vmcs_writel(GUEST_CR0, cr0);
2090         update_exception_bitmap(vcpu);
2091         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2092         if (is_guest_mode(vcpu))
2093                 vcpu->arch.cr0_guest_owned_bits &=
2094                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2095         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2096 }
2097
2098 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2099
2100 /*
2101  * Return the cr0 value that a nested guest would read. This is a combination
2102  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2103  * its hypervisor (cr0_read_shadow).
2104  */
2105 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2106 {
2107         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2108                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2109 }
2110 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2111 {
2112         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2113                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2114 }
2115
2116 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2117 {
2118         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2119          * set this *before* calling this function.
2120          */
2121         vmx_decache_cr0_guest_bits(vcpu);
2122         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2123         update_exception_bitmap(vcpu);
2124         vcpu->arch.cr0_guest_owned_bits = 0;
2125         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2126         if (is_guest_mode(vcpu)) {
2127                 /*
2128                  * L1's specified read shadow might not contain the TS bit,
2129                  * so now that we turned on shadowing of this bit, we need to
2130                  * set this bit of the shadow. Like in nested_vmx_run we need
2131                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2132                  * up-to-date here because we just decached cr0.TS (and we'll
2133                  * only update vmcs12->guest_cr0 on nested exit).
2134                  */
2135                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2136                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2137                         (vcpu->arch.cr0 & X86_CR0_TS);
2138                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2139         } else
2140                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2141 }
2142
2143 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2144 {
2145         unsigned long rflags, save_rflags;
2146
2147         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2148                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2149                 rflags = vmcs_readl(GUEST_RFLAGS);
2150                 if (to_vmx(vcpu)->rmode.vm86_active) {
2151                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2152                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2153                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2154                 }
2155                 to_vmx(vcpu)->rflags = rflags;
2156         }
2157         return to_vmx(vcpu)->rflags;
2158 }
2159
2160 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2161 {
2162         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2163         to_vmx(vcpu)->rflags = rflags;
2164         if (to_vmx(vcpu)->rmode.vm86_active) {
2165                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2166                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2167         }
2168         vmcs_writel(GUEST_RFLAGS, rflags);
2169 }
2170
2171 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2172 {
2173         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2174         int ret = 0;
2175
2176         if (interruptibility & GUEST_INTR_STATE_STI)
2177                 ret |= KVM_X86_SHADOW_INT_STI;
2178         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2179                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2180
2181         return ret;
2182 }
2183
2184 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2185 {
2186         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2187         u32 interruptibility = interruptibility_old;
2188
2189         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2190
2191         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2192                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2193         else if (mask & KVM_X86_SHADOW_INT_STI)
2194                 interruptibility |= GUEST_INTR_STATE_STI;
2195
2196         if ((interruptibility != interruptibility_old))
2197                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2198 }
2199
2200 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2201 {
2202         unsigned long rip;
2203
2204         rip = kvm_rip_read(vcpu);
2205         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2206         kvm_rip_write(vcpu, rip);
2207
2208         /* skipping an emulated instruction also counts */
2209         vmx_set_interrupt_shadow(vcpu, 0);
2210 }
2211
2212 /*
2213  * KVM wants to inject page-faults which it got to the guest. This function
2214  * checks whether in a nested guest, we need to inject them to L1 or L2.
2215  */
2216 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2217 {
2218         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2219
2220         if (!(vmcs12->exception_bitmap & (1u << nr)))
2221                 return 0;
2222
2223         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2224                           vmcs_read32(VM_EXIT_INTR_INFO),
2225                           vmcs_readl(EXIT_QUALIFICATION));
2226         return 1;
2227 }
2228
2229 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2230                                 bool has_error_code, u32 error_code,
2231                                 bool reinject)
2232 {
2233         struct vcpu_vmx *vmx = to_vmx(vcpu);
2234         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2235
2236         if (!reinject && is_guest_mode(vcpu) &&
2237             nested_vmx_check_exception(vcpu, nr))
2238                 return;
2239
2240         if (has_error_code) {
2241                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2242                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2243         }
2244
2245         if (vmx->rmode.vm86_active) {
2246                 int inc_eip = 0;
2247                 if (kvm_exception_is_soft(nr))
2248                         inc_eip = vcpu->arch.event_exit_inst_len;
2249                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2250                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2251                 return;
2252         }
2253
2254         if (kvm_exception_is_soft(nr)) {
2255                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2256                              vmx->vcpu.arch.event_exit_inst_len);
2257                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2258         } else
2259                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2260
2261         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2262 }
2263
2264 static bool vmx_rdtscp_supported(void)
2265 {
2266         return cpu_has_vmx_rdtscp();
2267 }
2268
2269 static bool vmx_invpcid_supported(void)
2270 {
2271         return cpu_has_vmx_invpcid() && enable_ept;
2272 }
2273
2274 /*
2275  * Swap MSR entry in host/guest MSR entry array.
2276  */
2277 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2278 {
2279         struct shared_msr_entry tmp;
2280
2281         tmp = vmx->guest_msrs[to];
2282         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2283         vmx->guest_msrs[from] = tmp;
2284 }
2285
2286 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2287 {
2288         unsigned long *msr_bitmap;
2289
2290         if (is_guest_mode(vcpu))
2291                 msr_bitmap = vmx_msr_bitmap_nested;
2292         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2293                 if (is_long_mode(vcpu))
2294                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2295                 else
2296                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2297         } else {
2298                 if (is_long_mode(vcpu))
2299                         msr_bitmap = vmx_msr_bitmap_longmode;
2300                 else
2301                         msr_bitmap = vmx_msr_bitmap_legacy;
2302         }
2303
2304         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2305 }
2306
2307 /*
2308  * Set up the vmcs to automatically save and restore system
2309  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2310  * mode, as fiddling with msrs is very expensive.
2311  */
2312 static void setup_msrs(struct vcpu_vmx *vmx)
2313 {
2314         int save_nmsrs, index;
2315
2316         save_nmsrs = 0;
2317 #ifdef CONFIG_X86_64
2318         if (is_long_mode(&vmx->vcpu)) {
2319                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2320                 if (index >= 0)
2321                         move_msr_up(vmx, index, save_nmsrs++);
2322                 index = __find_msr_index(vmx, MSR_LSTAR);
2323                 if (index >= 0)
2324                         move_msr_up(vmx, index, save_nmsrs++);
2325                 index = __find_msr_index(vmx, MSR_CSTAR);
2326                 if (index >= 0)
2327                         move_msr_up(vmx, index, save_nmsrs++);
2328                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2329                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2330                         move_msr_up(vmx, index, save_nmsrs++);
2331                 /*
2332                  * MSR_STAR is only needed on long mode guests, and only
2333                  * if efer.sce is enabled.
2334                  */
2335                 index = __find_msr_index(vmx, MSR_STAR);
2336                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2337                         move_msr_up(vmx, index, save_nmsrs++);
2338         }
2339 #endif
2340         index = __find_msr_index(vmx, MSR_EFER);
2341         if (index >= 0 && update_transition_efer(vmx, index))
2342                 move_msr_up(vmx, index, save_nmsrs++);
2343
2344         vmx->save_nmsrs = save_nmsrs;
2345
2346         if (cpu_has_vmx_msr_bitmap())
2347                 vmx_set_msr_bitmap(&vmx->vcpu);
2348 }
2349
2350 /*
2351  * reads and returns guest's timestamp counter "register"
2352  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2353  */
2354 static u64 guest_read_tsc(void)
2355 {
2356         u64 host_tsc, tsc_offset;
2357
2358         host_tsc = rdtsc();
2359         tsc_offset = vmcs_read64(TSC_OFFSET);
2360         return host_tsc + tsc_offset;
2361 }
2362
2363 /*
2364  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2365  * counter, even if a nested guest (L2) is currently running.
2366  */
2367 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2368 {
2369         u64 tsc_offset;
2370
2371         tsc_offset = is_guest_mode(vcpu) ?
2372                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2373                 vmcs_read64(TSC_OFFSET);
2374         return host_tsc + tsc_offset;
2375 }
2376
2377 /*
2378  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2379  * software catchup for faster rates on slower CPUs.
2380  */
2381 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2382 {
2383         if (!scale)
2384                 return;
2385
2386         if (user_tsc_khz > tsc_khz) {
2387                 vcpu->arch.tsc_catchup = 1;
2388                 vcpu->arch.tsc_always_catchup = 1;
2389         } else
2390                 WARN(1, "user requested TSC rate below hardware speed\n");
2391 }
2392
2393 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2394 {
2395         return vmcs_read64(TSC_OFFSET);
2396 }
2397
2398 /*
2399  * writes 'offset' into guest's timestamp counter offset register
2400  */
2401 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2402 {
2403         if (is_guest_mode(vcpu)) {
2404                 /*
2405                  * We're here if L1 chose not to trap WRMSR to TSC. According
2406                  * to the spec, this should set L1's TSC; The offset that L1
2407                  * set for L2 remains unchanged, and still needs to be added
2408                  * to the newly set TSC to get L2's TSC.
2409                  */
2410                 struct vmcs12 *vmcs12;
2411                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2412                 /* recalculate vmcs02.TSC_OFFSET: */
2413                 vmcs12 = get_vmcs12(vcpu);
2414                 vmcs_write64(TSC_OFFSET, offset +
2415                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2416                          vmcs12->tsc_offset : 0));
2417         } else {
2418                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2419                                            vmcs_read64(TSC_OFFSET), offset);
2420                 vmcs_write64(TSC_OFFSET, offset);
2421         }
2422 }
2423
2424 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2425 {
2426         u64 offset = vmcs_read64(TSC_OFFSET);
2427
2428         vmcs_write64(TSC_OFFSET, offset + adjustment);
2429         if (is_guest_mode(vcpu)) {
2430                 /* Even when running L2, the adjustment needs to apply to L1 */
2431                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2432         } else
2433                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2434                                            offset + adjustment);
2435 }
2436
2437 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2438 {
2439         return target_tsc - rdtsc();
2440 }
2441
2442 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2443 {
2444         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2445         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2446 }
2447
2448 /*
2449  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2450  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2451  * all guests if the "nested" module option is off, and can also be disabled
2452  * for a single guest by disabling its VMX cpuid bit.
2453  */
2454 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2455 {
2456         return nested && guest_cpuid_has_vmx(vcpu);
2457 }
2458
2459 /*
2460  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2461  * returned for the various VMX controls MSRs when nested VMX is enabled.
2462  * The same values should also be used to verify that vmcs12 control fields are
2463  * valid during nested entry from L1 to L2.
2464  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2465  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2466  * bit in the high half is on if the corresponding bit in the control field
2467  * may be on. See also vmx_control_verify().
2468  */
2469 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2470 {
2471         /*
2472          * Note that as a general rule, the high half of the MSRs (bits in
2473          * the control fields which may be 1) should be initialized by the
2474          * intersection of the underlying hardware's MSR (i.e., features which
2475          * can be supported) and the list of features we want to expose -
2476          * because they are known to be properly supported in our code.
2477          * Also, usually, the low half of the MSRs (bits which must be 1) can
2478          * be set to 0, meaning that L1 may turn off any of these bits. The
2479          * reason is that if one of these bits is necessary, it will appear
2480          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2481          * fields of vmcs01 and vmcs02, will turn these bits off - and
2482          * nested_vmx_exit_handled() will not pass related exits to L1.
2483          * These rules have exceptions below.
2484          */
2485
2486         /* pin-based controls */
2487         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2488                 vmx->nested.nested_vmx_pinbased_ctls_low,
2489                 vmx->nested.nested_vmx_pinbased_ctls_high);
2490         vmx->nested.nested_vmx_pinbased_ctls_low |=
2491                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2492         vmx->nested.nested_vmx_pinbased_ctls_high &=
2493                 PIN_BASED_EXT_INTR_MASK |
2494                 PIN_BASED_NMI_EXITING |
2495                 PIN_BASED_VIRTUAL_NMIS;
2496         vmx->nested.nested_vmx_pinbased_ctls_high |=
2497                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2498                 PIN_BASED_VMX_PREEMPTION_TIMER;
2499         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2500                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2501                         PIN_BASED_POSTED_INTR;
2502
2503         /* exit controls */
2504         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2505                 vmx->nested.nested_vmx_exit_ctls_low,
2506                 vmx->nested.nested_vmx_exit_ctls_high);
2507         vmx->nested.nested_vmx_exit_ctls_low =
2508                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2509
2510         vmx->nested.nested_vmx_exit_ctls_high &=
2511 #ifdef CONFIG_X86_64
2512                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2513 #endif
2514                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2515         vmx->nested.nested_vmx_exit_ctls_high |=
2516                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2517                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2518                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2519
2520         if (vmx_mpx_supported())
2521                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2522
2523         /* We support free control of debug control saving. */
2524         vmx->nested.nested_vmx_true_exit_ctls_low =
2525                 vmx->nested.nested_vmx_exit_ctls_low &
2526                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2527
2528         /* entry controls */
2529         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2530                 vmx->nested.nested_vmx_entry_ctls_low,
2531                 vmx->nested.nested_vmx_entry_ctls_high);
2532         vmx->nested.nested_vmx_entry_ctls_low =
2533                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2534         vmx->nested.nested_vmx_entry_ctls_high &=
2535 #ifdef CONFIG_X86_64
2536                 VM_ENTRY_IA32E_MODE |
2537 #endif
2538                 VM_ENTRY_LOAD_IA32_PAT;
2539         vmx->nested.nested_vmx_entry_ctls_high |=
2540                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2541         if (vmx_mpx_supported())
2542                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2543
2544         /* We support free control of debug control loading. */
2545         vmx->nested.nested_vmx_true_entry_ctls_low =
2546                 vmx->nested.nested_vmx_entry_ctls_low &
2547                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2548
2549         /* cpu-based controls */
2550         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2551                 vmx->nested.nested_vmx_procbased_ctls_low,
2552                 vmx->nested.nested_vmx_procbased_ctls_high);
2553         vmx->nested.nested_vmx_procbased_ctls_low =
2554                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2555         vmx->nested.nested_vmx_procbased_ctls_high &=
2556                 CPU_BASED_VIRTUAL_INTR_PENDING |
2557                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2558                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2559                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2560                 CPU_BASED_CR3_STORE_EXITING |
2561 #ifdef CONFIG_X86_64
2562                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2563 #endif
2564                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2565                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2566                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2567                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2568                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2569         /*
2570          * We can allow some features even when not supported by the
2571          * hardware. For example, L1 can specify an MSR bitmap - and we
2572          * can use it to avoid exits to L1 - even when L0 runs L2
2573          * without MSR bitmaps.
2574          */
2575         vmx->nested.nested_vmx_procbased_ctls_high |=
2576                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2577                 CPU_BASED_USE_MSR_BITMAPS;
2578
2579         /* We support free control of CR3 access interception. */
2580         vmx->nested.nested_vmx_true_procbased_ctls_low =
2581                 vmx->nested.nested_vmx_procbased_ctls_low &
2582                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2583
2584         /* secondary cpu-based controls */
2585         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2586                 vmx->nested.nested_vmx_secondary_ctls_low,
2587                 vmx->nested.nested_vmx_secondary_ctls_high);
2588         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2589         vmx->nested.nested_vmx_secondary_ctls_high &=
2590                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2591                 SECONDARY_EXEC_RDTSCP |
2592                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2593                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2594                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2595                 SECONDARY_EXEC_WBINVD_EXITING |
2596                 SECONDARY_EXEC_XSAVES |
2597                 SECONDARY_EXEC_PCOMMIT;
2598
2599         if (enable_ept) {
2600                 /* nested EPT: emulate EPT also to L1 */
2601                 vmx->nested.nested_vmx_secondary_ctls_high |=
2602                         SECONDARY_EXEC_ENABLE_EPT;
2603                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2604                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2605                          VMX_EPT_INVEPT_BIT;
2606                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2607                 /*
2608                  * For nested guests, we don't do anything specific
2609                  * for single context invalidation. Hence, only advertise
2610                  * support for global context invalidation.
2611                  */
2612                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2613         } else
2614                 vmx->nested.nested_vmx_ept_caps = 0;
2615
2616         vmx->nested.nested_vmx_vpid_caps = 0;
2617
2618         if (enable_unrestricted_guest)
2619                 vmx->nested.nested_vmx_secondary_ctls_high |=
2620                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2621
2622         /* miscellaneous data */
2623         rdmsr(MSR_IA32_VMX_MISC,
2624                 vmx->nested.nested_vmx_misc_low,
2625                 vmx->nested.nested_vmx_misc_high);
2626         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2627         vmx->nested.nested_vmx_misc_low |=
2628                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2629                 VMX_MISC_ACTIVITY_HLT;
2630         vmx->nested.nested_vmx_misc_high = 0;
2631 }
2632
2633 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2634 {
2635         /*
2636          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2637          */
2638         return ((control & high) | low) == control;
2639 }
2640
2641 static inline u64 vmx_control_msr(u32 low, u32 high)
2642 {
2643         return low | ((u64)high << 32);
2644 }
2645
2646 /* Returns 0 on success, non-0 otherwise. */
2647 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2648 {
2649         struct vcpu_vmx *vmx = to_vmx(vcpu);
2650
2651         switch (msr_index) {
2652         case MSR_IA32_VMX_BASIC:
2653                 /*
2654                  * This MSR reports some information about VMX support. We
2655                  * should return information about the VMX we emulate for the
2656                  * guest, and the VMCS structure we give it - not about the
2657                  * VMX support of the underlying hardware.
2658                  */
2659                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2660                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2661                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2662                 break;
2663         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2664         case MSR_IA32_VMX_PINBASED_CTLS:
2665                 *pdata = vmx_control_msr(
2666                         vmx->nested.nested_vmx_pinbased_ctls_low,
2667                         vmx->nested.nested_vmx_pinbased_ctls_high);
2668                 break;
2669         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2670                 *pdata = vmx_control_msr(
2671                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2672                         vmx->nested.nested_vmx_procbased_ctls_high);
2673                 break;
2674         case MSR_IA32_VMX_PROCBASED_CTLS:
2675                 *pdata = vmx_control_msr(
2676                         vmx->nested.nested_vmx_procbased_ctls_low,
2677                         vmx->nested.nested_vmx_procbased_ctls_high);
2678                 break;
2679         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2680                 *pdata = vmx_control_msr(
2681                         vmx->nested.nested_vmx_true_exit_ctls_low,
2682                         vmx->nested.nested_vmx_exit_ctls_high);
2683                 break;
2684         case MSR_IA32_VMX_EXIT_CTLS:
2685                 *pdata = vmx_control_msr(
2686                         vmx->nested.nested_vmx_exit_ctls_low,
2687                         vmx->nested.nested_vmx_exit_ctls_high);
2688                 break;
2689         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2690                 *pdata = vmx_control_msr(
2691                         vmx->nested.nested_vmx_true_entry_ctls_low,
2692                         vmx->nested.nested_vmx_entry_ctls_high);
2693                 break;
2694         case MSR_IA32_VMX_ENTRY_CTLS:
2695                 *pdata = vmx_control_msr(
2696                         vmx->nested.nested_vmx_entry_ctls_low,
2697                         vmx->nested.nested_vmx_entry_ctls_high);
2698                 break;
2699         case MSR_IA32_VMX_MISC:
2700                 *pdata = vmx_control_msr(
2701                         vmx->nested.nested_vmx_misc_low,
2702                         vmx->nested.nested_vmx_misc_high);
2703                 break;
2704         /*
2705          * These MSRs specify bits which the guest must keep fixed (on or off)
2706          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2707          * We picked the standard core2 setting.
2708          */
2709 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2710 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2711         case MSR_IA32_VMX_CR0_FIXED0:
2712                 *pdata = VMXON_CR0_ALWAYSON;
2713                 break;
2714         case MSR_IA32_VMX_CR0_FIXED1:
2715                 *pdata = -1ULL;
2716                 break;
2717         case MSR_IA32_VMX_CR4_FIXED0:
2718                 *pdata = VMXON_CR4_ALWAYSON;
2719                 break;
2720         case MSR_IA32_VMX_CR4_FIXED1:
2721                 *pdata = -1ULL;
2722                 break;
2723         case MSR_IA32_VMX_VMCS_ENUM:
2724                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2725                 break;
2726         case MSR_IA32_VMX_PROCBASED_CTLS2:
2727                 *pdata = vmx_control_msr(
2728                         vmx->nested.nested_vmx_secondary_ctls_low,
2729                         vmx->nested.nested_vmx_secondary_ctls_high);
2730                 break;
2731         case MSR_IA32_VMX_EPT_VPID_CAP:
2732                 /* Currently, no nested vpid support */
2733                 *pdata = vmx->nested.nested_vmx_ept_caps;
2734                 break;
2735         default:
2736                 return 1;
2737         }
2738
2739         return 0;
2740 }
2741
2742 /*
2743  * Reads an msr value (of 'msr_index') into 'pdata'.
2744  * Returns 0 on success, non-0 otherwise.
2745  * Assumes vcpu_load() was already called.
2746  */
2747 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2748 {
2749         struct shared_msr_entry *msr;
2750
2751         switch (msr_info->index) {
2752 #ifdef CONFIG_X86_64
2753         case MSR_FS_BASE:
2754                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2755                 break;
2756         case MSR_GS_BASE:
2757                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2758                 break;
2759         case MSR_KERNEL_GS_BASE:
2760                 vmx_load_host_state(to_vmx(vcpu));
2761                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2762                 break;
2763 #endif
2764         case MSR_EFER:
2765                 return kvm_get_msr_common(vcpu, msr_info);
2766         case MSR_IA32_TSC:
2767                 msr_info->data = guest_read_tsc();
2768                 break;
2769         case MSR_IA32_SYSENTER_CS:
2770                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2771                 break;
2772         case MSR_IA32_SYSENTER_EIP:
2773                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2774                 break;
2775         case MSR_IA32_SYSENTER_ESP:
2776                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2777                 break;
2778         case MSR_IA32_BNDCFGS:
2779                 if (!vmx_mpx_supported())
2780                         return 1;
2781                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2782                 break;
2783         case MSR_IA32_FEATURE_CONTROL:
2784                 if (!nested_vmx_allowed(vcpu))
2785                         return 1;
2786                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2787                 break;
2788         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2789                 if (!nested_vmx_allowed(vcpu))
2790                         return 1;
2791                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2792         case MSR_IA32_XSS:
2793                 if (!vmx_xsaves_supported())
2794                         return 1;
2795                 msr_info->data = vcpu->arch.ia32_xss;
2796                 break;
2797         case MSR_TSC_AUX:
2798                 if (!guest_cpuid_has_rdtscp(vcpu))
2799                         return 1;
2800                 /* Otherwise falls through */
2801         default:
2802                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2803                 if (msr) {
2804                         msr_info->data = msr->data;
2805                         break;
2806                 }
2807                 return kvm_get_msr_common(vcpu, msr_info);
2808         }
2809
2810         return 0;
2811 }
2812
2813 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2814
2815 /*
2816  * Writes msr value into into the appropriate "register".
2817  * Returns 0 on success, non-0 otherwise.
2818  * Assumes vcpu_load() was already called.
2819  */
2820 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2821 {
2822         struct vcpu_vmx *vmx = to_vmx(vcpu);
2823         struct shared_msr_entry *msr;
2824         int ret = 0;
2825         u32 msr_index = msr_info->index;
2826         u64 data = msr_info->data;
2827
2828         switch (msr_index) {
2829         case MSR_EFER:
2830                 ret = kvm_set_msr_common(vcpu, msr_info);
2831                 break;
2832 #ifdef CONFIG_X86_64
2833         case MSR_FS_BASE:
2834                 vmx_segment_cache_clear(vmx);
2835                 vmcs_writel(GUEST_FS_BASE, data);
2836                 break;
2837         case MSR_GS_BASE:
2838                 vmx_segment_cache_clear(vmx);
2839                 vmcs_writel(GUEST_GS_BASE, data);
2840                 break;
2841         case MSR_KERNEL_GS_BASE:
2842                 vmx_load_host_state(vmx);
2843                 vmx->msr_guest_kernel_gs_base = data;
2844                 break;
2845 #endif
2846         case MSR_IA32_SYSENTER_CS:
2847                 vmcs_write32(GUEST_SYSENTER_CS, data);
2848                 break;
2849         case MSR_IA32_SYSENTER_EIP:
2850                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2851                 break;
2852         case MSR_IA32_SYSENTER_ESP:
2853                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2854                 break;
2855         case MSR_IA32_BNDCFGS:
2856                 if (!vmx_mpx_supported())
2857                         return 1;
2858                 vmcs_write64(GUEST_BNDCFGS, data);
2859                 break;
2860         case MSR_IA32_TSC:
2861                 kvm_write_tsc(vcpu, msr_info);
2862                 break;
2863         case MSR_IA32_CR_PAT:
2864                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2865                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2866                                 return 1;
2867                         vmcs_write64(GUEST_IA32_PAT, data);
2868                         vcpu->arch.pat = data;
2869                         break;
2870                 }
2871                 ret = kvm_set_msr_common(vcpu, msr_info);
2872                 break;
2873         case MSR_IA32_TSC_ADJUST:
2874                 ret = kvm_set_msr_common(vcpu, msr_info);
2875                 break;
2876         case MSR_IA32_FEATURE_CONTROL:
2877                 if (!nested_vmx_allowed(vcpu) ||
2878                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2879                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2880                         return 1;
2881                 vmx->nested.msr_ia32_feature_control = data;
2882                 if (msr_info->host_initiated && data == 0)
2883                         vmx_leave_nested(vcpu);
2884                 break;
2885         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2886                 return 1; /* they are read-only */
2887         case MSR_IA32_XSS:
2888                 if (!vmx_xsaves_supported())
2889                         return 1;
2890                 /*
2891                  * The only supported bit as of Skylake is bit 8, but
2892                  * it is not supported on KVM.
2893                  */
2894                 if (data != 0)
2895                         return 1;
2896                 vcpu->arch.ia32_xss = data;
2897                 if (vcpu->arch.ia32_xss != host_xss)
2898                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2899                                 vcpu->arch.ia32_xss, host_xss);
2900                 else
2901                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2902                 break;
2903         case MSR_TSC_AUX:
2904                 if (!guest_cpuid_has_rdtscp(vcpu))
2905                         return 1;
2906                 /* Check reserved bit, higher 32 bits should be zero */
2907                 if ((data >> 32) != 0)
2908                         return 1;
2909                 /* Otherwise falls through */
2910         default:
2911                 msr = find_msr_entry(vmx, msr_index);
2912                 if (msr) {
2913                         u64 old_msr_data = msr->data;
2914                         msr->data = data;
2915                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2916                                 preempt_disable();
2917                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2918                                                          msr->mask);
2919                                 preempt_enable();
2920                                 if (ret)
2921                                         msr->data = old_msr_data;
2922                         }
2923                         break;
2924                 }
2925                 ret = kvm_set_msr_common(vcpu, msr_info);
2926         }
2927
2928         return ret;
2929 }
2930
2931 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2932 {
2933         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2934         switch (reg) {
2935         case VCPU_REGS_RSP:
2936                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2937                 break;
2938         case VCPU_REGS_RIP:
2939                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2940                 break;
2941         case VCPU_EXREG_PDPTR:
2942                 if (enable_ept)
2943                         ept_save_pdptrs(vcpu);
2944                 break;
2945         default:
2946                 break;
2947         }
2948 }
2949
2950 static __init int cpu_has_kvm_support(void)
2951 {
2952         return cpu_has_vmx();
2953 }
2954
2955 static __init int vmx_disabled_by_bios(void)
2956 {
2957         u64 msr;
2958
2959         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2960         if (msr & FEATURE_CONTROL_LOCKED) {
2961                 /* launched w/ TXT and VMX disabled */
2962                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2963                         && tboot_enabled())
2964                         return 1;
2965                 /* launched w/o TXT and VMX only enabled w/ TXT */
2966                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2967                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2968                         && !tboot_enabled()) {
2969                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2970                                 "activate TXT before enabling KVM\n");
2971                         return 1;
2972                 }
2973                 /* launched w/o TXT and VMX disabled */
2974                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2975                         && !tboot_enabled())
2976                         return 1;
2977         }
2978
2979         return 0;
2980 }
2981
2982 static void kvm_cpu_vmxon(u64 addr)
2983 {
2984         asm volatile (ASM_VMX_VMXON_RAX
2985                         : : "a"(&addr), "m"(addr)
2986                         : "memory", "cc");
2987 }
2988
2989 static int hardware_enable(void)
2990 {
2991         int cpu = raw_smp_processor_id();
2992         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2993         u64 old, test_bits;
2994
2995         if (cr4_read_shadow() & X86_CR4_VMXE)
2996                 return -EBUSY;
2997
2998         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2999         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3000         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3001
3002         /*
3003          * Now we can enable the vmclear operation in kdump
3004          * since the loaded_vmcss_on_cpu list on this cpu
3005          * has been initialized.
3006          *
3007          * Though the cpu is not in VMX operation now, there
3008          * is no problem to enable the vmclear operation
3009          * for the loaded_vmcss_on_cpu list is empty!
3010          */
3011         crash_enable_local_vmclear(cpu);
3012
3013         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3014
3015         test_bits = FEATURE_CONTROL_LOCKED;
3016         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3017         if (tboot_enabled())
3018                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3019
3020         if ((old & test_bits) != test_bits) {
3021                 /* enable and lock */
3022                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3023         }
3024         cr4_set_bits(X86_CR4_VMXE);
3025
3026         if (vmm_exclusive) {
3027                 kvm_cpu_vmxon(phys_addr);
3028                 ept_sync_global();
3029         }
3030
3031         native_store_gdt(this_cpu_ptr(&host_gdt));
3032
3033         return 0;
3034 }
3035
3036 static void vmclear_local_loaded_vmcss(void)
3037 {
3038         int cpu = raw_smp_processor_id();
3039         struct loaded_vmcs *v, *n;
3040
3041         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3042                                  loaded_vmcss_on_cpu_link)
3043                 __loaded_vmcs_clear(v);
3044 }
3045
3046
3047 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3048  * tricks.
3049  */
3050 static void kvm_cpu_vmxoff(void)
3051 {
3052         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3053 }
3054
3055 static void hardware_disable(void)
3056 {
3057         if (vmm_exclusive) {
3058                 vmclear_local_loaded_vmcss();
3059                 kvm_cpu_vmxoff();
3060         }
3061         cr4_clear_bits(X86_CR4_VMXE);
3062 }
3063
3064 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3065                                       u32 msr, u32 *result)
3066 {
3067         u32 vmx_msr_low, vmx_msr_high;
3068         u32 ctl = ctl_min | ctl_opt;
3069
3070         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3071
3072         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3073         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3074
3075         /* Ensure minimum (required) set of control bits are supported. */
3076         if (ctl_min & ~ctl)
3077                 return -EIO;
3078
3079         *result = ctl;
3080         return 0;
3081 }
3082
3083 static __init bool allow_1_setting(u32 msr, u32 ctl)
3084 {
3085         u32 vmx_msr_low, vmx_msr_high;
3086
3087         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3088         return vmx_msr_high & ctl;
3089 }
3090
3091 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3092 {
3093         u32 vmx_msr_low, vmx_msr_high;
3094         u32 min, opt, min2, opt2;
3095         u32 _pin_based_exec_control = 0;
3096         u32 _cpu_based_exec_control = 0;
3097         u32 _cpu_based_2nd_exec_control = 0;
3098         u32 _vmexit_control = 0;
3099         u32 _vmentry_control = 0;
3100
3101         min = CPU_BASED_HLT_EXITING |
3102 #ifdef CONFIG_X86_64
3103               CPU_BASED_CR8_LOAD_EXITING |
3104               CPU_BASED_CR8_STORE_EXITING |
3105 #endif
3106               CPU_BASED_CR3_LOAD_EXITING |
3107               CPU_BASED_CR3_STORE_EXITING |
3108               CPU_BASED_USE_IO_BITMAPS |
3109               CPU_BASED_MOV_DR_EXITING |
3110               CPU_BASED_USE_TSC_OFFSETING |
3111               CPU_BASED_MWAIT_EXITING |
3112               CPU_BASED_MONITOR_EXITING |
3113               CPU_BASED_INVLPG_EXITING |
3114               CPU_BASED_RDPMC_EXITING;
3115
3116         opt = CPU_BASED_TPR_SHADOW |
3117               CPU_BASED_USE_MSR_BITMAPS |
3118               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3119         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3120                                 &_cpu_based_exec_control) < 0)
3121                 return -EIO;
3122 #ifdef CONFIG_X86_64
3123         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3124                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3125                                            ~CPU_BASED_CR8_STORE_EXITING;
3126 #endif
3127         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3128                 min2 = 0;
3129                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3130                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3131                         SECONDARY_EXEC_WBINVD_EXITING |
3132                         SECONDARY_EXEC_ENABLE_VPID |
3133                         SECONDARY_EXEC_ENABLE_EPT |
3134                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3135                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3136                         SECONDARY_EXEC_RDTSCP |
3137                         SECONDARY_EXEC_ENABLE_INVPCID |
3138                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3139                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3140                         SECONDARY_EXEC_SHADOW_VMCS |
3141                         SECONDARY_EXEC_XSAVES |
3142                         SECONDARY_EXEC_ENABLE_PML |
3143                         SECONDARY_EXEC_PCOMMIT;
3144                 if (adjust_vmx_controls(min2, opt2,
3145                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3146                                         &_cpu_based_2nd_exec_control) < 0)
3147                         return -EIO;
3148         }
3149 #ifndef CONFIG_X86_64
3150         if (!(_cpu_based_2nd_exec_control &
3151                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3152                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3153 #endif
3154
3155         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3156                 _cpu_based_2nd_exec_control &= ~(
3157                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3158                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3159                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3160
3161         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3162                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3163                    enabled */
3164                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3165                                              CPU_BASED_CR3_STORE_EXITING |
3166                                              CPU_BASED_INVLPG_EXITING);
3167                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3168                       vmx_capability.ept, vmx_capability.vpid);
3169         }
3170
3171         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3172 #ifdef CONFIG_X86_64
3173         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3174 #endif
3175         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3176                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3177         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3178                                 &_vmexit_control) < 0)
3179                 return -EIO;
3180
3181         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3182         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3183         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3184                                 &_pin_based_exec_control) < 0)
3185                 return -EIO;
3186
3187         if (!(_cpu_based_2nd_exec_control &
3188                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3189                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3190                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3191
3192         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3193         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3194         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3195                                 &_vmentry_control) < 0)
3196                 return -EIO;
3197
3198         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3199
3200         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3201         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3202                 return -EIO;
3203
3204 #ifdef CONFIG_X86_64
3205         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3206         if (vmx_msr_high & (1u<<16))
3207                 return -EIO;
3208 #endif
3209
3210         /* Require Write-Back (WB) memory type for VMCS accesses. */
3211         if (((vmx_msr_high >> 18) & 15) != 6)
3212                 return -EIO;
3213
3214         vmcs_conf->size = vmx_msr_high & 0x1fff;
3215         vmcs_conf->order = get_order(vmcs_config.size);
3216         vmcs_conf->revision_id = vmx_msr_low;
3217
3218         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3219         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3220         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3221         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3222         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3223
3224         cpu_has_load_ia32_efer =
3225                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3226                                 VM_ENTRY_LOAD_IA32_EFER)
3227                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3228                                    VM_EXIT_LOAD_IA32_EFER);
3229
3230         cpu_has_load_perf_global_ctrl =
3231                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3232                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3233                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3234                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3235
3236         /*
3237          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3238          * but due to arrata below it can't be used. Workaround is to use
3239          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3240          *
3241          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3242          *
3243          * AAK155             (model 26)
3244          * AAP115             (model 30)
3245          * AAT100             (model 37)
3246          * BC86,AAY89,BD102   (model 44)
3247          * BA97               (model 46)
3248          *
3249          */
3250         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3251                 switch (boot_cpu_data.x86_model) {
3252                 case 26:
3253                 case 30:
3254                 case 37:
3255                 case 44:
3256                 case 46:
3257                         cpu_has_load_perf_global_ctrl = false;
3258                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3259                                         "does not work properly. Using workaround\n");
3260                         break;
3261                 default:
3262                         break;
3263                 }
3264         }
3265
3266         if (cpu_has_xsaves)
3267                 rdmsrl(MSR_IA32_XSS, host_xss);
3268
3269         return 0;
3270 }
3271
3272 static struct vmcs *alloc_vmcs_cpu(int cpu)
3273 {
3274         int node = cpu_to_node(cpu);
3275         struct page *pages;
3276         struct vmcs *vmcs;
3277
3278         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3279         if (!pages)
3280                 return NULL;
3281         vmcs = page_address(pages);
3282         memset(vmcs, 0, vmcs_config.size);
3283         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3284         return vmcs;
3285 }
3286
3287 static struct vmcs *alloc_vmcs(void)
3288 {
3289         return alloc_vmcs_cpu(raw_smp_processor_id());
3290 }
3291
3292 static void free_vmcs(struct vmcs *vmcs)
3293 {
3294         free_pages((unsigned long)vmcs, vmcs_config.order);
3295 }
3296
3297 /*
3298  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3299  */
3300 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3301 {
3302         if (!loaded_vmcs->vmcs)
3303                 return;
3304         loaded_vmcs_clear(loaded_vmcs);
3305         free_vmcs(loaded_vmcs->vmcs);
3306         loaded_vmcs->vmcs = NULL;
3307 }
3308
3309 static void free_kvm_area(void)
3310 {
3311         int cpu;
3312
3313         for_each_possible_cpu(cpu) {
3314                 free_vmcs(per_cpu(vmxarea, cpu));
3315                 per_cpu(vmxarea, cpu) = NULL;
3316         }
3317 }
3318
3319 static void init_vmcs_shadow_fields(void)
3320 {
3321         int i, j;
3322
3323         /* No checks for read only fields yet */
3324
3325         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3326                 switch (shadow_read_write_fields[i]) {
3327                 case GUEST_BNDCFGS:
3328                         if (!vmx_mpx_supported())
3329                                 continue;
3330                         break;
3331                 default:
3332                         break;
3333                 }
3334
3335                 if (j < i)
3336                         shadow_read_write_fields[j] =
3337                                 shadow_read_write_fields[i];
3338                 j++;
3339         }
3340         max_shadow_read_write_fields = j;
3341
3342         /* shadowed fields guest access without vmexit */
3343         for (i = 0; i < max_shadow_read_write_fields; i++) {
3344                 clear_bit(shadow_read_write_fields[i],
3345                           vmx_vmwrite_bitmap);
3346                 clear_bit(shadow_read_write_fields[i],
3347                           vmx_vmread_bitmap);
3348         }
3349         for (i = 0; i < max_shadow_read_only_fields; i++)
3350                 clear_bit(shadow_read_only_fields[i],
3351                           vmx_vmread_bitmap);
3352 }
3353
3354 static __init int alloc_kvm_area(void)
3355 {
3356         int cpu;
3357
3358         for_each_possible_cpu(cpu) {
3359                 struct vmcs *vmcs;
3360
3361                 vmcs = alloc_vmcs_cpu(cpu);
3362                 if (!vmcs) {
3363                         free_kvm_area();
3364                         return -ENOMEM;
3365                 }
3366
3367                 per_cpu(vmxarea, cpu) = vmcs;
3368         }
3369         return 0;
3370 }
3371
3372 static bool emulation_required(struct kvm_vcpu *vcpu)
3373 {
3374         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3375 }
3376
3377 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3378                 struct kvm_segment *save)
3379 {
3380         if (!emulate_invalid_guest_state) {
3381                 /*
3382                  * CS and SS RPL should be equal during guest entry according
3383                  * to VMX spec, but in reality it is not always so. Since vcpu
3384                  * is in the middle of the transition from real mode to
3385                  * protected mode it is safe to assume that RPL 0 is a good
3386                  * default value.
3387                  */
3388                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3389                         save->selector &= ~SEGMENT_RPL_MASK;
3390                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3391                 save->s = 1;
3392         }
3393         vmx_set_segment(vcpu, save, seg);
3394 }
3395
3396 static void enter_pmode(struct kvm_vcpu *vcpu)
3397 {
3398         unsigned long flags;
3399         struct vcpu_vmx *vmx = to_vmx(vcpu);
3400
3401         /*
3402          * Update real mode segment cache. It may be not up-to-date if sement
3403          * register was written while vcpu was in a guest mode.
3404          */
3405         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3406         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3407         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3408         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3409         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3410         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3411
3412         vmx->rmode.vm86_active = 0;
3413
3414         vmx_segment_cache_clear(vmx);
3415
3416         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3417
3418         flags = vmcs_readl(GUEST_RFLAGS);
3419         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3420         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3421         vmcs_writel(GUEST_RFLAGS, flags);
3422
3423         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3424                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3425
3426         update_exception_bitmap(vcpu);
3427
3428         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3429         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3430         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3431         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3432         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3433         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3434 }
3435
3436 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3437 {
3438         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3439         struct kvm_segment var = *save;
3440
3441         var.dpl = 0x3;
3442         if (seg == VCPU_SREG_CS)
3443                 var.type = 0x3;
3444
3445         if (!emulate_invalid_guest_state) {
3446                 var.selector = var.base >> 4;
3447                 var.base = var.base & 0xffff0;
3448                 var.limit = 0xffff;
3449                 var.g = 0;
3450                 var.db = 0;
3451                 var.present = 1;
3452                 var.s = 1;
3453                 var.l = 0;
3454                 var.unusable = 0;
3455                 var.type = 0x3;
3456                 var.avl = 0;
3457                 if (save->base & 0xf)
3458                         printk_once(KERN_WARNING "kvm: segment base is not "
3459                                         "paragraph aligned when entering "
3460                                         "protected mode (seg=%d)", seg);
3461         }
3462
3463         vmcs_write16(sf->selector, var.selector);
3464         vmcs_write32(sf->base, var.base);
3465         vmcs_write32(sf->limit, var.limit);
3466         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3467 }
3468
3469 static void enter_rmode(struct kvm_vcpu *vcpu)
3470 {
3471         unsigned long flags;
3472         struct vcpu_vmx *vmx = to_vmx(vcpu);
3473
3474         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3475         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3476         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3477         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3478         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3479         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3480         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3481
3482         vmx->rmode.vm86_active = 1;
3483
3484         /*
3485          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3486          * vcpu. Warn the user that an update is overdue.
3487          */
3488         if (!vcpu->kvm->arch.tss_addr)
3489                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3490                              "called before entering vcpu\n");
3491
3492         vmx_segment_cache_clear(vmx);
3493
3494         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3495         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3496         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3497
3498         flags = vmcs_readl(GUEST_RFLAGS);
3499         vmx->rmode.save_rflags = flags;
3500
3501         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3502
3503         vmcs_writel(GUEST_RFLAGS, flags);
3504         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3505         update_exception_bitmap(vcpu);
3506
3507         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3508         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3509         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3510         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3511         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3512         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3513
3514         kvm_mmu_reset_context(vcpu);
3515 }
3516
3517 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3518 {
3519         struct vcpu_vmx *vmx = to_vmx(vcpu);
3520         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3521
3522         if (!msr)
3523                 return;
3524
3525         /*
3526          * Force kernel_gs_base reloading before EFER changes, as control
3527          * of this msr depends on is_long_mode().
3528          */
3529         vmx_load_host_state(to_vmx(vcpu));
3530         vcpu->arch.efer = efer;
3531         if (efer & EFER_LMA) {
3532                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3533                 msr->data = efer;
3534         } else {
3535                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3536
3537                 msr->data = efer & ~EFER_LME;
3538         }
3539         setup_msrs(vmx);
3540 }
3541
3542 #ifdef CONFIG_X86_64
3543
3544 static void enter_lmode(struct kvm_vcpu *vcpu)
3545 {
3546         u32 guest_tr_ar;
3547
3548         vmx_segment_cache_clear(to_vmx(vcpu));
3549
3550         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3551         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3552                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3553                                      __func__);
3554                 vmcs_write32(GUEST_TR_AR_BYTES,
3555                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3556                              | VMX_AR_TYPE_BUSY_64_TSS);
3557         }
3558         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3559 }
3560
3561 static void exit_lmode(struct kvm_vcpu *vcpu)
3562 {
3563         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3564         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3565 }
3566
3567 #endif
3568
3569 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3570 {
3571         vpid_sync_context(vpid);
3572         if (enable_ept) {
3573                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3574                         return;
3575                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3576         }
3577 }
3578
3579 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3580 {
3581         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3582 }
3583
3584 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3585 {
3586         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3587
3588         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3589         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3590 }
3591
3592 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3593 {
3594         if (enable_ept && is_paging(vcpu))
3595                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3596         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3597 }
3598
3599 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3600 {
3601         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3602
3603         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3604         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3605 }
3606
3607 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3608 {
3609         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3610
3611         if (!test_bit(VCPU_EXREG_PDPTR,
3612                       (unsigned long *)&vcpu->arch.regs_dirty))
3613                 return;
3614
3615         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3616                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3617                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3618                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3619                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3620         }
3621 }
3622
3623 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3624 {
3625         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3626
3627         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3628                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3629                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3630                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3631                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3632         }
3633
3634         __set_bit(VCPU_EXREG_PDPTR,
3635                   (unsigned long *)&vcpu->arch.regs_avail);
3636         __set_bit(VCPU_EXREG_PDPTR,
3637                   (unsigned long *)&vcpu->arch.regs_dirty);
3638 }
3639
3640 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3641
3642 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3643                                         unsigned long cr0,
3644                                         struct kvm_vcpu *vcpu)
3645 {
3646         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3647                 vmx_decache_cr3(vcpu);
3648         if (!(cr0 & X86_CR0_PG)) {
3649                 /* From paging/starting to nonpaging */
3650                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3651                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3652                              (CPU_BASED_CR3_LOAD_EXITING |
3653                               CPU_BASED_CR3_STORE_EXITING));
3654                 vcpu->arch.cr0 = cr0;
3655                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3656         } else if (!is_paging(vcpu)) {
3657                 /* From nonpaging to paging */
3658                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3659                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3660                              ~(CPU_BASED_CR3_LOAD_EXITING |
3661                                CPU_BASED_CR3_STORE_EXITING));
3662                 vcpu->arch.cr0 = cr0;
3663                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3664         }
3665
3666         if (!(cr0 & X86_CR0_WP))
3667                 *hw_cr0 &= ~X86_CR0_WP;
3668 }
3669
3670 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3671 {
3672         struct vcpu_vmx *vmx = to_vmx(vcpu);
3673         unsigned long hw_cr0;
3674
3675         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3676         if (enable_unrestricted_guest)
3677                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3678         else {
3679                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3680
3681                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3682                         enter_pmode(vcpu);
3683
3684                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3685                         enter_rmode(vcpu);
3686         }
3687
3688 #ifdef CONFIG_X86_64
3689         if (vcpu->arch.efer & EFER_LME) {
3690                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3691                         enter_lmode(vcpu);
3692                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3693                         exit_lmode(vcpu);
3694         }
3695 #endif
3696
3697         if (enable_ept)
3698                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3699
3700         if (!vcpu->fpu_active)
3701                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3702
3703         vmcs_writel(CR0_READ_SHADOW, cr0);
3704         vmcs_writel(GUEST_CR0, hw_cr0);
3705         vcpu->arch.cr0 = cr0;
3706
3707         /* depends on vcpu->arch.cr0 to be set to a new value */
3708         vmx->emulation_required = emulation_required(vcpu);
3709 }
3710
3711 static u64 construct_eptp(unsigned long root_hpa)
3712 {
3713         u64 eptp;
3714
3715         /* TODO write the value reading from MSR */
3716         eptp = VMX_EPT_DEFAULT_MT |
3717                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3718         if (enable_ept_ad_bits)
3719                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3720         eptp |= (root_hpa & PAGE_MASK);
3721
3722         return eptp;
3723 }
3724
3725 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3726 {
3727         unsigned long guest_cr3;
3728         u64 eptp;
3729
3730         guest_cr3 = cr3;
3731         if (enable_ept) {
3732                 eptp = construct_eptp(cr3);
3733                 vmcs_write64(EPT_POINTER, eptp);
3734                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3735                         guest_cr3 = kvm_read_cr3(vcpu);
3736                 else
3737                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3738                 ept_load_pdptrs(vcpu);
3739         }
3740
3741         vmx_flush_tlb(vcpu);
3742         vmcs_writel(GUEST_CR3, guest_cr3);
3743 }
3744
3745 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3746 {
3747         /*
3748          * Pass through host's Machine Check Enable value to hw_cr4, which
3749          * is in force while we are in guest mode.  Do not let guests control
3750          * this bit, even if host CR4.MCE == 0.
3751          */
3752         unsigned long hw_cr4 =
3753                 (cr4_read_shadow() & X86_CR4_MCE) |
3754                 (cr4 & ~X86_CR4_MCE) |
3755                 (to_vmx(vcpu)->rmode.vm86_active ?
3756                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3757
3758         if (cr4 & X86_CR4_VMXE) {
3759                 /*
3760                  * To use VMXON (and later other VMX instructions), a guest
3761                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3762                  * So basically the check on whether to allow nested VMX
3763                  * is here.
3764                  */
3765                 if (!nested_vmx_allowed(vcpu))
3766                         return 1;
3767         }
3768         if (to_vmx(vcpu)->nested.vmxon &&
3769             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3770                 return 1;
3771
3772         vcpu->arch.cr4 = cr4;
3773         if (enable_ept) {
3774                 if (!is_paging(vcpu)) {
3775                         hw_cr4 &= ~X86_CR4_PAE;
3776                         hw_cr4 |= X86_CR4_PSE;
3777                         /*
3778                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3779                          * in hardware. However KVM always uses paging mode to
3780                          * emulate guest non-paging mode with TDP.
3781                          * To emulate this behavior, SMEP/SMAP needs to be
3782                          * manually disabled when guest switches to non-paging
3783                          * mode.
3784                          */
3785                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3786                 } else if (!(cr4 & X86_CR4_PAE)) {
3787                         hw_cr4 &= ~X86_CR4_PAE;
3788                 }
3789         }
3790
3791         vmcs_writel(CR4_READ_SHADOW, cr4);
3792         vmcs_writel(GUEST_CR4, hw_cr4);
3793         return 0;
3794 }
3795
3796 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3797                             struct kvm_segment *var, int seg)
3798 {
3799         struct vcpu_vmx *vmx = to_vmx(vcpu);
3800         u32 ar;
3801
3802         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3803                 *var = vmx->rmode.segs[seg];
3804                 if (seg == VCPU_SREG_TR
3805                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3806                         return;
3807                 var->base = vmx_read_guest_seg_base(vmx, seg);
3808                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3809                 return;
3810         }
3811         var->base = vmx_read_guest_seg_base(vmx, seg);
3812         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3813         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3814         ar = vmx_read_guest_seg_ar(vmx, seg);
3815         var->unusable = (ar >> 16) & 1;
3816         var->type = ar & 15;
3817         var->s = (ar >> 4) & 1;
3818         var->dpl = (ar >> 5) & 3;
3819         /*
3820          * Some userspaces do not preserve unusable property. Since usable
3821          * segment has to be present according to VMX spec we can use present
3822          * property to amend userspace bug by making unusable segment always
3823          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3824          * segment as unusable.
3825          */
3826         var->present = !var->unusable;
3827         var->avl = (ar >> 12) & 1;
3828         var->l = (ar >> 13) & 1;
3829         var->db = (ar >> 14) & 1;
3830         var->g = (ar >> 15) & 1;
3831 }
3832
3833 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3834 {
3835         struct kvm_segment s;
3836
3837         if (to_vmx(vcpu)->rmode.vm86_active) {
3838                 vmx_get_segment(vcpu, &s, seg);
3839                 return s.base;
3840         }
3841         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3842 }
3843
3844 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3845 {
3846         struct vcpu_vmx *vmx = to_vmx(vcpu);
3847
3848         if (unlikely(vmx->rmode.vm86_active))
3849                 return 0;
3850         else {
3851                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3852                 return VMX_AR_DPL(ar);
3853         }
3854 }
3855
3856 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3857 {
3858         u32 ar;
3859
3860         if (var->unusable || !var->present)
3861                 ar = 1 << 16;
3862         else {
3863                 ar = var->type & 15;
3864                 ar |= (var->s & 1) << 4;
3865                 ar |= (var->dpl & 3) << 5;
3866                 ar |= (var->present & 1) << 7;
3867                 ar |= (var->avl & 1) << 12;
3868                 ar |= (var->l & 1) << 13;
3869                 ar |= (var->db & 1) << 14;
3870                 ar |= (var->g & 1) << 15;
3871         }
3872
3873         return ar;
3874 }
3875
3876 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3877                             struct kvm_segment *var, int seg)
3878 {
3879         struct vcpu_vmx *vmx = to_vmx(vcpu);
3880         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3881
3882         vmx_segment_cache_clear(vmx);
3883
3884         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3885                 vmx->rmode.segs[seg] = *var;
3886                 if (seg == VCPU_SREG_TR)
3887                         vmcs_write16(sf->selector, var->selector);
3888                 else if (var->s)
3889                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3890                 goto out;
3891         }
3892
3893         vmcs_writel(sf->base, var->base);
3894         vmcs_write32(sf->limit, var->limit);
3895         vmcs_write16(sf->selector, var->selector);
3896
3897         /*
3898          *   Fix the "Accessed" bit in AR field of segment registers for older
3899          * qemu binaries.
3900          *   IA32 arch specifies that at the time of processor reset the
3901          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3902          * is setting it to 0 in the userland code. This causes invalid guest
3903          * state vmexit when "unrestricted guest" mode is turned on.
3904          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3905          * tree. Newer qemu binaries with that qemu fix would not need this
3906          * kvm hack.
3907          */
3908         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3909                 var->type |= 0x1; /* Accessed */
3910
3911         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3912
3913 out:
3914         vmx->emulation_required = emulation_required(vcpu);
3915 }
3916
3917 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3918 {
3919         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3920
3921         *db = (ar >> 14) & 1;
3922         *l = (ar >> 13) & 1;
3923 }
3924
3925 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3926 {
3927         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3928         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3929 }
3930
3931 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3932 {
3933         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3934         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3935 }
3936
3937 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3938 {
3939         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3940         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3941 }
3942
3943 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3944 {
3945         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3946         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3947 }
3948
3949 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3950 {
3951         struct kvm_segment var;
3952         u32 ar;
3953
3954         vmx_get_segment(vcpu, &var, seg);
3955         var.dpl = 0x3;
3956         if (seg == VCPU_SREG_CS)
3957                 var.type = 0x3;
3958         ar = vmx_segment_access_rights(&var);
3959
3960         if (var.base != (var.selector << 4))
3961                 return false;
3962         if (var.limit != 0xffff)
3963                 return false;
3964         if (ar != 0xf3)
3965                 return false;
3966
3967         return true;
3968 }
3969
3970 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3971 {
3972         struct kvm_segment cs;
3973         unsigned int cs_rpl;
3974
3975         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3976         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3977
3978         if (cs.unusable)
3979                 return false;
3980         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3981                 return false;
3982         if (!cs.s)
3983                 return false;
3984         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3985                 if (cs.dpl > cs_rpl)
3986                         return false;
3987         } else {
3988                 if (cs.dpl != cs_rpl)
3989                         return false;
3990         }
3991         if (!cs.present)
3992                 return false;
3993
3994         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3995         return true;
3996 }
3997
3998 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3999 {
4000         struct kvm_segment ss;
4001         unsigned int ss_rpl;
4002
4003         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4004         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4005
4006         if (ss.unusable)
4007                 return true;
4008         if (ss.type != 3 && ss.type != 7)
4009                 return false;
4010         if (!ss.s)
4011                 return false;
4012         if (ss.dpl != ss_rpl) /* DPL != RPL */
4013                 return false;
4014         if (!ss.present)
4015                 return false;
4016
4017         return true;
4018 }
4019
4020 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4021 {
4022         struct kvm_segment var;
4023         unsigned int rpl;
4024
4025         vmx_get_segment(vcpu, &var, seg);
4026         rpl = var.selector & SEGMENT_RPL_MASK;
4027
4028         if (var.unusable)
4029                 return true;
4030         if (!var.s)
4031                 return false;
4032         if (!var.present)
4033                 return false;
4034         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4035                 if (var.dpl < rpl) /* DPL < RPL */
4036                         return false;
4037         }
4038
4039         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4040          * rights flags
4041          */
4042         return true;
4043 }
4044
4045 static bool tr_valid(struct kvm_vcpu *vcpu)
4046 {
4047         struct kvm_segment tr;
4048
4049         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4050
4051         if (tr.unusable)
4052                 return false;
4053         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4054                 return false;
4055         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4056                 return false;
4057         if (!tr.present)
4058                 return false;
4059
4060         return true;
4061 }
4062
4063 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4064 {
4065         struct kvm_segment ldtr;
4066
4067         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4068
4069         if (ldtr.unusable)
4070                 return true;
4071         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4072                 return false;
4073         if (ldtr.type != 2)
4074                 return false;
4075         if (!ldtr.present)
4076                 return false;
4077
4078         return true;
4079 }
4080
4081 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4082 {
4083         struct kvm_segment cs, ss;
4084
4085         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4086         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4087
4088         return ((cs.selector & SEGMENT_RPL_MASK) ==
4089                  (ss.selector & SEGMENT_RPL_MASK));
4090 }
4091
4092 /*
4093  * Check if guest state is valid. Returns true if valid, false if
4094  * not.
4095  * We assume that registers are always usable
4096  */
4097 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4098 {
4099         if (enable_unrestricted_guest)
4100                 return true;
4101
4102         /* real mode guest state checks */
4103         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4104                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4105                         return false;
4106                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4107                         return false;
4108                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4109                         return false;
4110                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4111                         return false;
4112                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4113                         return false;
4114                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4115                         return false;
4116         } else {
4117         /* protected mode guest state checks */
4118                 if (!cs_ss_rpl_check(vcpu))
4119                         return false;
4120                 if (!code_segment_valid(vcpu))
4121                         return false;
4122                 if (!stack_segment_valid(vcpu))
4123                         return false;
4124                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4125                         return false;
4126                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4127                         return false;
4128                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4129                         return false;
4130                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4131                         return false;
4132                 if (!tr_valid(vcpu))
4133                         return false;
4134                 if (!ldtr_valid(vcpu))
4135                         return false;
4136         }
4137         /* TODO:
4138          * - Add checks on RIP
4139          * - Add checks on RFLAGS
4140          */
4141
4142         return true;
4143 }
4144
4145 static int init_rmode_tss(struct kvm *kvm)
4146 {
4147         gfn_t fn;
4148         u16 data = 0;
4149         int idx, r;
4150
4151         idx = srcu_read_lock(&kvm->srcu);
4152         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4153         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4154         if (r < 0)
4155                 goto out;
4156         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4157         r = kvm_write_guest_page(kvm, fn++, &data,
4158                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4159         if (r < 0)
4160                 goto out;
4161         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4162         if (r < 0)
4163                 goto out;
4164         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4165         if (r < 0)
4166                 goto out;
4167         data = ~0;
4168         r = kvm_write_guest_page(kvm, fn, &data,
4169                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4170                                  sizeof(u8));
4171 out:
4172         srcu_read_unlock(&kvm->srcu, idx);
4173         return r;
4174 }
4175
4176 static int init_rmode_identity_map(struct kvm *kvm)
4177 {
4178         int i, idx, r = 0;
4179         pfn_t identity_map_pfn;
4180         u32 tmp;
4181
4182         if (!enable_ept)
4183                 return 0;
4184
4185         /* Protect kvm->arch.ept_identity_pagetable_done. */
4186         mutex_lock(&kvm->slots_lock);
4187
4188         if (likely(kvm->arch.ept_identity_pagetable_done))
4189                 goto out2;
4190
4191         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4192
4193         r = alloc_identity_pagetable(kvm);
4194         if (r < 0)
4195                 goto out2;
4196
4197         idx = srcu_read_lock(&kvm->srcu);
4198         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4199         if (r < 0)
4200                 goto out;
4201         /* Set up identity-mapping pagetable for EPT in real mode */
4202         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4203                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4204                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4205                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4206                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4207                 if (r < 0)
4208                         goto out;
4209         }
4210         kvm->arch.ept_identity_pagetable_done = true;
4211
4212 out:
4213         srcu_read_unlock(&kvm->srcu, idx);
4214
4215 out2:
4216         mutex_unlock(&kvm->slots_lock);
4217         return r;
4218 }
4219
4220 static void seg_setup(int seg)
4221 {
4222         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4223         unsigned int ar;
4224
4225         vmcs_write16(sf->selector, 0);
4226         vmcs_writel(sf->base, 0);
4227         vmcs_write32(sf->limit, 0xffff);
4228         ar = 0x93;
4229         if (seg == VCPU_SREG_CS)
4230                 ar |= 0x08; /* code segment */
4231
4232         vmcs_write32(sf->ar_bytes, ar);
4233 }
4234
4235 static int alloc_apic_access_page(struct kvm *kvm)
4236 {
4237         struct page *page;
4238         int r = 0;
4239
4240         mutex_lock(&kvm->slots_lock);
4241         if (kvm->arch.apic_access_page_done)
4242                 goto out;
4243         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4244                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4245         if (r)
4246                 goto out;
4247
4248         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4249         if (is_error_page(page)) {
4250                 r = -EFAULT;
4251                 goto out;
4252         }
4253
4254         /*
4255          * Do not pin the page in memory, so that memory hot-unplug
4256          * is able to migrate it.
4257          */
4258         put_page(page);
4259         kvm->arch.apic_access_page_done = true;
4260 out:
4261         mutex_unlock(&kvm->slots_lock);
4262         return r;
4263 }
4264
4265 static int alloc_identity_pagetable(struct kvm *kvm)
4266 {
4267         /* Called with kvm->slots_lock held. */
4268
4269         int r = 0;
4270
4271         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4272
4273         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4274                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4275
4276         return r;
4277 }
4278
4279 static int allocate_vpid(void)
4280 {
4281         int vpid;
4282
4283         if (!enable_vpid)
4284                 return 0;
4285         spin_lock(&vmx_vpid_lock);
4286         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4287         if (vpid < VMX_NR_VPIDS)
4288                 __set_bit(vpid, vmx_vpid_bitmap);
4289         else
4290                 vpid = 0;
4291         spin_unlock(&vmx_vpid_lock);
4292         return vpid;
4293 }
4294
4295 static void free_vpid(int vpid)
4296 {
4297         if (!enable_vpid || vpid == 0)
4298                 return;
4299         spin_lock(&vmx_vpid_lock);
4300         __clear_bit(vpid, vmx_vpid_bitmap);
4301         spin_unlock(&vmx_vpid_lock);
4302 }
4303
4304 #define MSR_TYPE_R      1
4305 #define MSR_TYPE_W      2
4306 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4307                                                 u32 msr, int type)
4308 {
4309         int f = sizeof(unsigned long);
4310
4311         if (!cpu_has_vmx_msr_bitmap())
4312                 return;
4313
4314         /*
4315          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4316          * have the write-low and read-high bitmap offsets the wrong way round.
4317          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4318          */
4319         if (msr <= 0x1fff) {
4320                 if (type & MSR_TYPE_R)
4321                         /* read-low */
4322                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4323
4324                 if (type & MSR_TYPE_W)
4325                         /* write-low */
4326                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4327
4328         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4329                 msr &= 0x1fff;
4330                 if (type & MSR_TYPE_R)
4331                         /* read-high */
4332                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4333
4334                 if (type & MSR_TYPE_W)
4335                         /* write-high */
4336                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4337
4338         }
4339 }
4340
4341 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4342                                                 u32 msr, int type)
4343 {
4344         int f = sizeof(unsigned long);
4345
4346         if (!cpu_has_vmx_msr_bitmap())
4347                 return;
4348
4349         /*
4350          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4351          * have the write-low and read-high bitmap offsets the wrong way round.
4352          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4353          */
4354         if (msr <= 0x1fff) {
4355                 if (type & MSR_TYPE_R)
4356                         /* read-low */
4357                         __set_bit(msr, msr_bitmap + 0x000 / f);
4358
4359                 if (type & MSR_TYPE_W)
4360                         /* write-low */
4361                         __set_bit(msr, msr_bitmap + 0x800 / f);
4362
4363         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4364                 msr &= 0x1fff;
4365                 if (type & MSR_TYPE_R)
4366                         /* read-high */
4367                         __set_bit(msr, msr_bitmap + 0x400 / f);
4368
4369                 if (type & MSR_TYPE_W)
4370                         /* write-high */
4371                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4372
4373         }
4374 }
4375
4376 /*
4377  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4378  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4379  */
4380 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4381                                                unsigned long *msr_bitmap_nested,
4382                                                u32 msr, int type)
4383 {
4384         int f = sizeof(unsigned long);
4385
4386         if (!cpu_has_vmx_msr_bitmap()) {
4387                 WARN_ON(1);
4388                 return;
4389         }
4390
4391         /*
4392          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4393          * have the write-low and read-high bitmap offsets the wrong way round.
4394          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4395          */
4396         if (msr <= 0x1fff) {
4397                 if (type & MSR_TYPE_R &&
4398                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4399                         /* read-low */
4400                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4401
4402                 if (type & MSR_TYPE_W &&
4403                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4404                         /* write-low */
4405                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4406
4407         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4408                 msr &= 0x1fff;
4409                 if (type & MSR_TYPE_R &&
4410                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4411                         /* read-high */
4412                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4413
4414                 if (type & MSR_TYPE_W &&
4415                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4416                         /* write-high */
4417                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4418
4419         }
4420 }
4421
4422 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4423 {
4424         if (!longmode_only)
4425                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4426                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4427         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4428                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4429 }
4430
4431 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4432 {
4433         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4434                         msr, MSR_TYPE_R);
4435         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4436                         msr, MSR_TYPE_R);
4437 }
4438
4439 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4440 {
4441         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4442                         msr, MSR_TYPE_R);
4443         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4444                         msr, MSR_TYPE_R);
4445 }
4446
4447 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4448 {
4449         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4450                         msr, MSR_TYPE_W);
4451         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4452                         msr, MSR_TYPE_W);
4453 }
4454
4455 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4456 {
4457         return enable_apicv && lapic_in_kernel(vcpu);
4458 }
4459
4460 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4461 {
4462         struct vcpu_vmx *vmx = to_vmx(vcpu);
4463         int max_irr;
4464         void *vapic_page;
4465         u16 status;
4466
4467         if (vmx->nested.pi_desc &&
4468             vmx->nested.pi_pending) {
4469                 vmx->nested.pi_pending = false;
4470                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4471                         return 0;
4472
4473                 max_irr = find_last_bit(
4474                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4475
4476                 if (max_irr == 256)
4477                         return 0;
4478
4479                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4480                 if (!vapic_page) {
4481                         WARN_ON(1);
4482                         return -ENOMEM;
4483                 }
4484                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4485                 kunmap(vmx->nested.virtual_apic_page);
4486
4487                 status = vmcs_read16(GUEST_INTR_STATUS);
4488                 if ((u8)max_irr > ((u8)status & 0xff)) {
4489                         status &= ~0xff;
4490                         status |= (u8)max_irr;
4491                         vmcs_write16(GUEST_INTR_STATUS, status);
4492                 }
4493         }
4494         return 0;
4495 }
4496
4497 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4498 {
4499 #ifdef CONFIG_SMP
4500         if (vcpu->mode == IN_GUEST_MODE) {
4501                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4502
4503                 /*
4504                  * Currently, we don't support urgent interrupt,
4505                  * all interrupts are recognized as non-urgent
4506                  * interrupt, so we cannot post interrupts when
4507                  * 'SN' is set.
4508                  *
4509                  * If the vcpu is in guest mode, it means it is
4510                  * running instead of being scheduled out and
4511                  * waiting in the run queue, and that's the only
4512                  * case when 'SN' is set currently, warning if
4513                  * 'SN' is set.
4514                  */
4515                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4516
4517                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4518                                 POSTED_INTR_VECTOR);
4519                 return true;
4520         }
4521 #endif
4522         return false;
4523 }
4524
4525 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4526                                                 int vector)
4527 {
4528         struct vcpu_vmx *vmx = to_vmx(vcpu);
4529
4530         if (is_guest_mode(vcpu) &&
4531             vector == vmx->nested.posted_intr_nv) {
4532                 /* the PIR and ON have been set by L1. */
4533                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4534                 /*
4535                  * If a posted intr is not recognized by hardware,
4536                  * we will accomplish it in the next vmentry.
4537                  */
4538                 vmx->nested.pi_pending = true;
4539                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4540                 return 0;
4541         }
4542         return -1;
4543 }
4544 /*
4545  * Send interrupt to vcpu via posted interrupt way.
4546  * 1. If target vcpu is running(non-root mode), send posted interrupt
4547  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4548  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4549  * interrupt from PIR in next vmentry.
4550  */
4551 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4552 {
4553         struct vcpu_vmx *vmx = to_vmx(vcpu);
4554         int r;
4555
4556         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4557         if (!r)
4558                 return;
4559
4560         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4561                 return;
4562
4563         r = pi_test_and_set_on(&vmx->pi_desc);
4564         kvm_make_request(KVM_REQ_EVENT, vcpu);
4565         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4566                 kvm_vcpu_kick(vcpu);
4567 }
4568
4569 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4570 {
4571         struct vcpu_vmx *vmx = to_vmx(vcpu);
4572
4573         if (!pi_test_and_clear_on(&vmx->pi_desc))
4574                 return;
4575
4576         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4577 }
4578
4579 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4580 {
4581         return;
4582 }
4583
4584 /*
4585  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4586  * will not change in the lifetime of the guest.
4587  * Note that host-state that does change is set elsewhere. E.g., host-state
4588  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4589  */
4590 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4591 {
4592         u32 low32, high32;
4593         unsigned long tmpl;
4594         struct desc_ptr dt;
4595         unsigned long cr4;
4596
4597         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4598         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4599
4600         /* Save the most likely value for this task's CR4 in the VMCS. */
4601         cr4 = cr4_read_shadow();
4602         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4603         vmx->host_state.vmcs_host_cr4 = cr4;
4604
4605         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4606 #ifdef CONFIG_X86_64
4607         /*
4608          * Load null selectors, so we can avoid reloading them in
4609          * __vmx_load_host_state(), in case userspace uses the null selectors
4610          * too (the expected case).
4611          */
4612         vmcs_write16(HOST_DS_SELECTOR, 0);
4613         vmcs_write16(HOST_ES_SELECTOR, 0);
4614 #else
4615         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4616         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4617 #endif
4618         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4619         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4620
4621         native_store_idt(&dt);
4622         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4623         vmx->host_idt_base = dt.address;
4624
4625         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4626
4627         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4628         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4629         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4630         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4631
4632         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4633                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4634                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4635         }
4636 }
4637
4638 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4639 {
4640         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4641         if (enable_ept)
4642                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4643         if (is_guest_mode(&vmx->vcpu))
4644                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4645                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4646         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4647 }
4648
4649 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4650 {
4651         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4652
4653         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4654                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4655         return pin_based_exec_ctrl;
4656 }
4657
4658 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4659 {
4660         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4661
4662         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4663                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4664
4665         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4666                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4667 #ifdef CONFIG_X86_64
4668                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4669                                 CPU_BASED_CR8_LOAD_EXITING;
4670 #endif
4671         }
4672         if (!enable_ept)
4673                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4674                                 CPU_BASED_CR3_LOAD_EXITING  |
4675                                 CPU_BASED_INVLPG_EXITING;
4676         return exec_control;
4677 }
4678
4679 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4680 {
4681         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4682         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4683                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4684         if (vmx->vpid == 0)
4685                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4686         if (!enable_ept) {
4687                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4688                 enable_unrestricted_guest = 0;
4689                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4690                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4691         }
4692         if (!enable_unrestricted_guest)
4693                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4694         if (!ple_gap)
4695                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4696         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4697                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4698                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4699         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4700         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4701            (handle_vmptrld).
4702            We can NOT enable shadow_vmcs here because we don't have yet
4703            a current VMCS12
4704         */
4705         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4706         /* PML is enabled/disabled in creating/destorying vcpu */
4707         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4708
4709         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4710         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4711
4712         return exec_control;
4713 }
4714
4715 static void ept_set_mmio_spte_mask(void)
4716 {
4717         /*
4718          * EPT Misconfigurations can be generated if the value of bits 2:0
4719          * of an EPT paging-structure entry is 110b (write/execute).
4720          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4721          * spte.
4722          */
4723         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4724 }
4725
4726 #define VMX_XSS_EXIT_BITMAP 0
4727 /*
4728  * Sets up the vmcs for emulated real mode.
4729  */
4730 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4731 {
4732 #ifdef CONFIG_X86_64
4733         unsigned long a;
4734 #endif
4735         int i;
4736
4737         /* I/O */
4738         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4739         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4740
4741         if (enable_shadow_vmcs) {
4742                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4743                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4744         }
4745         if (cpu_has_vmx_msr_bitmap())
4746                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4747
4748         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4749
4750         /* Control */
4751         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4752
4753         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4754
4755         if (cpu_has_secondary_exec_ctrls())
4756                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4757                                 vmx_secondary_exec_control(vmx));
4758
4759         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4760                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4761                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4762                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4763                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4764
4765                 vmcs_write16(GUEST_INTR_STATUS, 0);
4766
4767                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4768                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4769         }
4770
4771         if (ple_gap) {
4772                 vmcs_write32(PLE_GAP, ple_gap);
4773                 vmx->ple_window = ple_window;
4774                 vmx->ple_window_dirty = true;
4775         }
4776
4777         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4778         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4779         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4780
4781         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4782         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4783         vmx_set_constant_host_state(vmx);
4784 #ifdef CONFIG_X86_64
4785         rdmsrl(MSR_FS_BASE, a);
4786         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4787         rdmsrl(MSR_GS_BASE, a);
4788         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4789 #else
4790         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4791         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4792 #endif
4793
4794         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4795         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4796         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4797         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4798         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4799
4800         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4801                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4802
4803         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4804                 u32 index = vmx_msr_index[i];
4805                 u32 data_low, data_high;
4806                 int j = vmx->nmsrs;
4807
4808                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4809                         continue;
4810                 if (wrmsr_safe(index, data_low, data_high) < 0)
4811                         continue;
4812                 vmx->guest_msrs[j].index = i;
4813                 vmx->guest_msrs[j].data = 0;
4814                 vmx->guest_msrs[j].mask = -1ull;
4815                 ++vmx->nmsrs;
4816         }
4817
4818
4819         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4820
4821         /* 22.2.1, 20.8.1 */
4822         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4823
4824         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4825         set_cr4_guest_host_mask(vmx);
4826
4827         if (vmx_xsaves_supported())
4828                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4829
4830         return 0;
4831 }
4832
4833 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4834 {
4835         struct vcpu_vmx *vmx = to_vmx(vcpu);
4836         struct msr_data apic_base_msr;
4837         u64 cr0;
4838
4839         vmx->rmode.vm86_active = 0;
4840
4841         vmx->soft_vnmi_blocked = 0;
4842
4843         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4844         kvm_set_cr8(vcpu, 0);
4845
4846         if (!init_event) {
4847                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4848                                      MSR_IA32_APICBASE_ENABLE;
4849                 if (kvm_vcpu_is_reset_bsp(vcpu))
4850                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4851                 apic_base_msr.host_initiated = true;
4852                 kvm_set_apic_base(vcpu, &apic_base_msr);
4853         }
4854
4855         vmx_segment_cache_clear(vmx);
4856
4857         seg_setup(VCPU_SREG_CS);
4858         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4859         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4860
4861         seg_setup(VCPU_SREG_DS);
4862         seg_setup(VCPU_SREG_ES);
4863         seg_setup(VCPU_SREG_FS);
4864         seg_setup(VCPU_SREG_GS);
4865         seg_setup(VCPU_SREG_SS);
4866
4867         vmcs_write16(GUEST_TR_SELECTOR, 0);
4868         vmcs_writel(GUEST_TR_BASE, 0);
4869         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4870         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4871
4872         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4873         vmcs_writel(GUEST_LDTR_BASE, 0);
4874         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4875         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4876
4877         if (!init_event) {
4878                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4879                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4880                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4881                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4882         }
4883
4884         vmcs_writel(GUEST_RFLAGS, 0x02);
4885         kvm_rip_write(vcpu, 0xfff0);
4886
4887         vmcs_writel(GUEST_GDTR_BASE, 0);
4888         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4889
4890         vmcs_writel(GUEST_IDTR_BASE, 0);
4891         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4892
4893         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4894         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4895         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4896
4897         setup_msrs(vmx);
4898
4899         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4900
4901         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4902                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4903                 if (cpu_need_tpr_shadow(vcpu))
4904                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4905                                      __pa(vcpu->arch.apic->regs));
4906                 vmcs_write32(TPR_THRESHOLD, 0);
4907         }
4908
4909         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4910
4911         if (vmx_cpu_uses_apicv(vcpu))
4912                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4913
4914         if (vmx->vpid != 0)
4915                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4916
4917         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4918         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4919         vmx->vcpu.arch.cr0 = cr0;
4920         vmx_set_cr4(vcpu, 0);
4921         if (!init_event)
4922                 vmx_set_efer(vcpu, 0);
4923         vmx_fpu_activate(vcpu);
4924         update_exception_bitmap(vcpu);
4925
4926         vpid_sync_context(vmx->vpid);
4927 }
4928
4929 /*
4930  * In nested virtualization, check if L1 asked to exit on external interrupts.
4931  * For most existing hypervisors, this will always return true.
4932  */
4933 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4934 {
4935         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4936                 PIN_BASED_EXT_INTR_MASK;
4937 }
4938
4939 /*
4940  * In nested virtualization, check if L1 has set
4941  * VM_EXIT_ACK_INTR_ON_EXIT
4942  */
4943 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4944 {
4945         return get_vmcs12(vcpu)->vm_exit_controls &
4946                 VM_EXIT_ACK_INTR_ON_EXIT;
4947 }
4948
4949 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4950 {
4951         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4952                 PIN_BASED_NMI_EXITING;
4953 }
4954
4955 static void enable_irq_window(struct kvm_vcpu *vcpu)
4956 {
4957         u32 cpu_based_vm_exec_control;
4958
4959         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4960         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4961         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4962 }
4963
4964 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4965 {
4966         u32 cpu_based_vm_exec_control;
4967
4968         if (!cpu_has_virtual_nmis() ||
4969             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4970                 enable_irq_window(vcpu);
4971                 return;
4972         }
4973
4974         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4975         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4976         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4977 }
4978
4979 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4980 {
4981         struct vcpu_vmx *vmx = to_vmx(vcpu);
4982         uint32_t intr;
4983         int irq = vcpu->arch.interrupt.nr;
4984
4985         trace_kvm_inj_virq(irq);
4986
4987         ++vcpu->stat.irq_injections;
4988         if (vmx->rmode.vm86_active) {
4989                 int inc_eip = 0;
4990                 if (vcpu->arch.interrupt.soft)
4991                         inc_eip = vcpu->arch.event_exit_inst_len;
4992                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4993                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4994                 return;
4995         }
4996         intr = irq | INTR_INFO_VALID_MASK;
4997         if (vcpu->arch.interrupt.soft) {
4998                 intr |= INTR_TYPE_SOFT_INTR;
4999                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5000                              vmx->vcpu.arch.event_exit_inst_len);
5001         } else
5002                 intr |= INTR_TYPE_EXT_INTR;
5003         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5004 }
5005
5006 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5007 {
5008         struct vcpu_vmx *vmx = to_vmx(vcpu);
5009
5010         if (is_guest_mode(vcpu))
5011                 return;
5012
5013         if (!cpu_has_virtual_nmis()) {
5014                 /*
5015                  * Tracking the NMI-blocked state in software is built upon
5016                  * finding the next open IRQ window. This, in turn, depends on
5017                  * well-behaving guests: They have to keep IRQs disabled at
5018                  * least as long as the NMI handler runs. Otherwise we may
5019                  * cause NMI nesting, maybe breaking the guest. But as this is
5020                  * highly unlikely, we can live with the residual risk.
5021                  */
5022                 vmx->soft_vnmi_blocked = 1;
5023                 vmx->vnmi_blocked_time = 0;
5024         }
5025
5026         ++vcpu->stat.nmi_injections;
5027         vmx->nmi_known_unmasked = false;
5028         if (vmx->rmode.vm86_active) {
5029                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5030                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5031                 return;
5032         }
5033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5034                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5035 }
5036
5037 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5038 {
5039         if (!cpu_has_virtual_nmis())
5040                 return to_vmx(vcpu)->soft_vnmi_blocked;
5041         if (to_vmx(vcpu)->nmi_known_unmasked)
5042                 return false;
5043         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5044 }
5045
5046 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5047 {
5048         struct vcpu_vmx *vmx = to_vmx(vcpu);
5049
5050         if (!cpu_has_virtual_nmis()) {
5051                 if (vmx->soft_vnmi_blocked != masked) {
5052                         vmx->soft_vnmi_blocked = masked;
5053                         vmx->vnmi_blocked_time = 0;
5054                 }
5055         } else {
5056                 vmx->nmi_known_unmasked = !masked;
5057                 if (masked)
5058                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5059                                       GUEST_INTR_STATE_NMI);
5060                 else
5061                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5062                                         GUEST_INTR_STATE_NMI);
5063         }
5064 }
5065
5066 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5067 {
5068         if (to_vmx(vcpu)->nested.nested_run_pending)
5069                 return 0;
5070
5071         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5072                 return 0;
5073
5074         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5075                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5076                    | GUEST_INTR_STATE_NMI));
5077 }
5078
5079 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5080 {
5081         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5082                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5083                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5084                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5085 }
5086
5087 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5088 {
5089         int ret;
5090
5091         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5092                                     PAGE_SIZE * 3);
5093         if (ret)
5094                 return ret;
5095         kvm->arch.tss_addr = addr;
5096         return init_rmode_tss(kvm);
5097 }
5098
5099 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5100 {
5101         switch (vec) {
5102         case BP_VECTOR:
5103                 /*
5104                  * Update instruction length as we may reinject the exception
5105                  * from user space while in guest debugging mode.
5106                  */
5107                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5108                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5109                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5110                         return false;
5111                 /* fall through */
5112         case DB_VECTOR:
5113                 if (vcpu->guest_debug &
5114                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5115                         return false;
5116                 /* fall through */
5117         case DE_VECTOR:
5118         case OF_VECTOR:
5119         case BR_VECTOR:
5120         case UD_VECTOR:
5121         case DF_VECTOR:
5122         case SS_VECTOR:
5123         case GP_VECTOR:
5124         case MF_VECTOR:
5125                 return true;
5126         break;
5127         }
5128         return false;
5129 }
5130
5131 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5132                                   int vec, u32 err_code)
5133 {
5134         /*
5135          * Instruction with address size override prefix opcode 0x67
5136          * Cause the #SS fault with 0 error code in VM86 mode.
5137          */
5138         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5139                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5140                         if (vcpu->arch.halt_request) {
5141                                 vcpu->arch.halt_request = 0;
5142                                 return kvm_vcpu_halt(vcpu);
5143                         }
5144                         return 1;
5145                 }
5146                 return 0;
5147         }
5148
5149         /*
5150          * Forward all other exceptions that are valid in real mode.
5151          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5152          *        the required debugging infrastructure rework.
5153          */
5154         kvm_queue_exception(vcpu, vec);
5155         return 1;
5156 }
5157
5158 /*
5159  * Trigger machine check on the host. We assume all the MSRs are already set up
5160  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5161  * We pass a fake environment to the machine check handler because we want
5162  * the guest to be always treated like user space, no matter what context
5163  * it used internally.
5164  */
5165 static void kvm_machine_check(void)
5166 {
5167 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5168         struct pt_regs regs = {
5169                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5170                 .flags = X86_EFLAGS_IF,
5171         };
5172
5173         do_machine_check(&regs, 0);
5174 #endif
5175 }
5176
5177 static int handle_machine_check(struct kvm_vcpu *vcpu)
5178 {
5179         /* already handled by vcpu_run */
5180         return 1;
5181 }
5182
5183 static int handle_exception(struct kvm_vcpu *vcpu)
5184 {
5185         struct vcpu_vmx *vmx = to_vmx(vcpu);
5186         struct kvm_run *kvm_run = vcpu->run;
5187         u32 intr_info, ex_no, error_code;
5188         unsigned long cr2, rip, dr6;
5189         u32 vect_info;
5190         enum emulation_result er;
5191
5192         vect_info = vmx->idt_vectoring_info;
5193         intr_info = vmx->exit_intr_info;
5194
5195         if (is_machine_check(intr_info))
5196                 return handle_machine_check(vcpu);
5197
5198         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5199                 return 1;  /* already handled by vmx_vcpu_run() */
5200
5201         if (is_no_device(intr_info)) {
5202                 vmx_fpu_activate(vcpu);
5203                 return 1;
5204         }
5205
5206         if (is_invalid_opcode(intr_info)) {
5207                 if (is_guest_mode(vcpu)) {
5208                         kvm_queue_exception(vcpu, UD_VECTOR);
5209                         return 1;
5210                 }
5211                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5212                 if (er != EMULATE_DONE)
5213                         kvm_queue_exception(vcpu, UD_VECTOR);
5214                 return 1;
5215         }
5216
5217         error_code = 0;
5218         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5219                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5220
5221         /*
5222          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5223          * MMIO, it is better to report an internal error.
5224          * See the comments in vmx_handle_exit.
5225          */
5226         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5227             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5228                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5229                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5230                 vcpu->run->internal.ndata = 3;
5231                 vcpu->run->internal.data[0] = vect_info;
5232                 vcpu->run->internal.data[1] = intr_info;
5233                 vcpu->run->internal.data[2] = error_code;
5234                 return 0;
5235         }
5236
5237         if (is_page_fault(intr_info)) {
5238                 /* EPT won't cause page fault directly */
5239                 BUG_ON(enable_ept);
5240                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5241                 trace_kvm_page_fault(cr2, error_code);
5242
5243                 if (kvm_event_needs_reinjection(vcpu))
5244                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5245                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5246         }
5247
5248         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5249
5250         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5251                 return handle_rmode_exception(vcpu, ex_no, error_code);
5252
5253         switch (ex_no) {
5254         case DB_VECTOR:
5255                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5256                 if (!(vcpu->guest_debug &
5257                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5258                         vcpu->arch.dr6 &= ~15;
5259                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5260                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5261                                 skip_emulated_instruction(vcpu);
5262
5263                         kvm_queue_exception(vcpu, DB_VECTOR);
5264                         return 1;
5265                 }
5266                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5267                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5268                 /* fall through */
5269         case BP_VECTOR:
5270                 /*
5271                  * Update instruction length as we may reinject #BP from
5272                  * user space while in guest debugging mode. Reading it for
5273                  * #DB as well causes no harm, it is not used in that case.
5274                  */
5275                 vmx->vcpu.arch.event_exit_inst_len =
5276                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5277                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5278                 rip = kvm_rip_read(vcpu);
5279                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5280                 kvm_run->debug.arch.exception = ex_no;
5281                 break;
5282         default:
5283                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5284                 kvm_run->ex.exception = ex_no;
5285                 kvm_run->ex.error_code = error_code;
5286                 break;
5287         }
5288         return 0;
5289 }
5290
5291 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5292 {
5293         ++vcpu->stat.irq_exits;
5294         return 1;
5295 }
5296
5297 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5298 {
5299         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5300         return 0;
5301 }
5302
5303 static int handle_io(struct kvm_vcpu *vcpu)
5304 {
5305         unsigned long exit_qualification;
5306         int size, in, string;
5307         unsigned port;
5308
5309         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5310         string = (exit_qualification & 16) != 0;
5311         in = (exit_qualification & 8) != 0;
5312
5313         ++vcpu->stat.io_exits;
5314
5315         if (string || in)
5316                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5317
5318         port = exit_qualification >> 16;
5319         size = (exit_qualification & 7) + 1;
5320         skip_emulated_instruction(vcpu);
5321
5322         return kvm_fast_pio_out(vcpu, size, port);
5323 }
5324
5325 static void
5326 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5327 {
5328         /*
5329          * Patch in the VMCALL instruction:
5330          */
5331         hypercall[0] = 0x0f;
5332         hypercall[1] = 0x01;
5333         hypercall[2] = 0xc1;
5334 }
5335
5336 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5337 {
5338         unsigned long always_on = VMXON_CR0_ALWAYSON;
5339         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5340
5341         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5342                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5343             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5344                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5345         return (val & always_on) == always_on;
5346 }
5347
5348 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5349 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5350 {
5351         if (is_guest_mode(vcpu)) {
5352                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5353                 unsigned long orig_val = val;
5354
5355                 /*
5356                  * We get here when L2 changed cr0 in a way that did not change
5357                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5358                  * but did change L0 shadowed bits. So we first calculate the
5359                  * effective cr0 value that L1 would like to write into the
5360                  * hardware. It consists of the L2-owned bits from the new
5361                  * value combined with the L1-owned bits from L1's guest_cr0.
5362                  */
5363                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5364                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5365
5366                 if (!nested_cr0_valid(vcpu, val))
5367                         return 1;
5368
5369                 if (kvm_set_cr0(vcpu, val))
5370                         return 1;
5371                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5372                 return 0;
5373         } else {
5374                 if (to_vmx(vcpu)->nested.vmxon &&
5375                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5376                         return 1;
5377                 return kvm_set_cr0(vcpu, val);
5378         }
5379 }
5380
5381 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5382 {
5383         if (is_guest_mode(vcpu)) {
5384                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5385                 unsigned long orig_val = val;
5386
5387                 /* analogously to handle_set_cr0 */
5388                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5389                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5390                 if (kvm_set_cr4(vcpu, val))
5391                         return 1;
5392                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5393                 return 0;
5394         } else
5395                 return kvm_set_cr4(vcpu, val);
5396 }
5397
5398 /* called to set cr0 as approriate for clts instruction exit. */
5399 static void handle_clts(struct kvm_vcpu *vcpu)
5400 {
5401         if (is_guest_mode(vcpu)) {
5402                 /*
5403                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5404                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5405                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5406                  */
5407                 vmcs_writel(CR0_READ_SHADOW,
5408                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5409                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5410         } else
5411                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5412 }
5413
5414 static int handle_cr(struct kvm_vcpu *vcpu)
5415 {
5416         unsigned long exit_qualification, val;
5417         int cr;
5418         int reg;
5419         int err;
5420
5421         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5422         cr = exit_qualification & 15;
5423         reg = (exit_qualification >> 8) & 15;
5424         switch ((exit_qualification >> 4) & 3) {
5425         case 0: /* mov to cr */
5426                 val = kvm_register_readl(vcpu, reg);
5427                 trace_kvm_cr_write(cr, val);
5428                 switch (cr) {
5429                 case 0:
5430                         err = handle_set_cr0(vcpu, val);
5431                         kvm_complete_insn_gp(vcpu, err);
5432                         return 1;
5433                 case 3:
5434                         err = kvm_set_cr3(vcpu, val);
5435                         kvm_complete_insn_gp(vcpu, err);
5436                         return 1;
5437                 case 4:
5438                         err = handle_set_cr4(vcpu, val);
5439                         kvm_complete_insn_gp(vcpu, err);
5440                         return 1;
5441                 case 8: {
5442                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5443                                 u8 cr8 = (u8)val;
5444                                 err = kvm_set_cr8(vcpu, cr8);
5445                                 kvm_complete_insn_gp(vcpu, err);
5446                                 if (lapic_in_kernel(vcpu))
5447                                         return 1;
5448                                 if (cr8_prev <= cr8)
5449                                         return 1;
5450                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5451                                 return 0;
5452                         }
5453                 }
5454                 break;
5455         case 2: /* clts */
5456                 handle_clts(vcpu);
5457                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5458                 skip_emulated_instruction(vcpu);
5459                 vmx_fpu_activate(vcpu);
5460                 return 1;
5461         case 1: /*mov from cr*/
5462                 switch (cr) {
5463                 case 3:
5464                         val = kvm_read_cr3(vcpu);
5465                         kvm_register_write(vcpu, reg, val);
5466                         trace_kvm_cr_read(cr, val);
5467                         skip_emulated_instruction(vcpu);
5468                         return 1;
5469                 case 8:
5470                         val = kvm_get_cr8(vcpu);
5471                         kvm_register_write(vcpu, reg, val);
5472                         trace_kvm_cr_read(cr, val);
5473                         skip_emulated_instruction(vcpu);
5474                         return 1;
5475                 }
5476                 break;
5477         case 3: /* lmsw */
5478                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5479                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5480                 kvm_lmsw(vcpu, val);
5481
5482                 skip_emulated_instruction(vcpu);
5483                 return 1;
5484         default:
5485                 break;
5486         }
5487         vcpu->run->exit_reason = 0;
5488         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5489                (int)(exit_qualification >> 4) & 3, cr);
5490         return 0;
5491 }
5492
5493 static int handle_dr(struct kvm_vcpu *vcpu)
5494 {
5495         unsigned long exit_qualification;
5496         int dr, dr7, reg;
5497
5498         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5499         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5500
5501         /* First, if DR does not exist, trigger UD */
5502         if (!kvm_require_dr(vcpu, dr))
5503                 return 1;
5504
5505         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5506         if (!kvm_require_cpl(vcpu, 0))
5507                 return 1;
5508         dr7 = vmcs_readl(GUEST_DR7);
5509         if (dr7 & DR7_GD) {
5510                 /*
5511                  * As the vm-exit takes precedence over the debug trap, we
5512                  * need to emulate the latter, either for the host or the
5513                  * guest debugging itself.
5514                  */
5515                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5516                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5517                         vcpu->run->debug.arch.dr7 = dr7;
5518                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5519                         vcpu->run->debug.arch.exception = DB_VECTOR;
5520                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5521                         return 0;
5522                 } else {
5523                         vcpu->arch.dr6 &= ~15;
5524                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5525                         kvm_queue_exception(vcpu, DB_VECTOR);
5526                         return 1;
5527                 }
5528         }
5529
5530         if (vcpu->guest_debug == 0) {
5531                 u32 cpu_based_vm_exec_control;
5532
5533                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5534                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5535                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5536
5537                 /*
5538                  * No more DR vmexits; force a reload of the debug registers
5539                  * and reenter on this instruction.  The next vmexit will
5540                  * retrieve the full state of the debug registers.
5541                  */
5542                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5543                 return 1;
5544         }
5545
5546         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5547         if (exit_qualification & TYPE_MOV_FROM_DR) {
5548                 unsigned long val;
5549
5550                 if (kvm_get_dr(vcpu, dr, &val))
5551                         return 1;
5552                 kvm_register_write(vcpu, reg, val);
5553         } else
5554                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5555                         return 1;
5556
5557         skip_emulated_instruction(vcpu);
5558         return 1;
5559 }
5560
5561 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5562 {
5563         return vcpu->arch.dr6;
5564 }
5565
5566 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5567 {
5568 }
5569
5570 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5571 {
5572         u32 cpu_based_vm_exec_control;
5573
5574         get_debugreg(vcpu->arch.db[0], 0);
5575         get_debugreg(vcpu->arch.db[1], 1);
5576         get_debugreg(vcpu->arch.db[2], 2);
5577         get_debugreg(vcpu->arch.db[3], 3);
5578         get_debugreg(vcpu->arch.dr6, 6);
5579         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5580
5581         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5582
5583         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5584         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5585         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5586 }
5587
5588 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5589 {
5590         vmcs_writel(GUEST_DR7, val);
5591 }
5592
5593 static int handle_cpuid(struct kvm_vcpu *vcpu)
5594 {
5595         kvm_emulate_cpuid(vcpu);
5596         return 1;
5597 }
5598
5599 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5600 {
5601         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5602         struct msr_data msr_info;
5603
5604         msr_info.index = ecx;
5605         msr_info.host_initiated = false;
5606         if (vmx_get_msr(vcpu, &msr_info)) {
5607                 trace_kvm_msr_read_ex(ecx);
5608                 kvm_inject_gp(vcpu, 0);
5609                 return 1;
5610         }
5611
5612         trace_kvm_msr_read(ecx, msr_info.data);
5613
5614         /* FIXME: handling of bits 32:63 of rax, rdx */
5615         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5616         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5617         skip_emulated_instruction(vcpu);
5618         return 1;
5619 }
5620
5621 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5622 {
5623         struct msr_data msr;
5624         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5625         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5626                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5627
5628         msr.data = data;
5629         msr.index = ecx;
5630         msr.host_initiated = false;
5631         if (kvm_set_msr(vcpu, &msr) != 0) {
5632                 trace_kvm_msr_write_ex(ecx, data);
5633                 kvm_inject_gp(vcpu, 0);
5634                 return 1;
5635         }
5636
5637         trace_kvm_msr_write(ecx, data);
5638         skip_emulated_instruction(vcpu);
5639         return 1;
5640 }
5641
5642 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5643 {
5644         kvm_make_request(KVM_REQ_EVENT, vcpu);
5645         return 1;
5646 }
5647
5648 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5649 {
5650         u32 cpu_based_vm_exec_control;
5651
5652         /* clear pending irq */
5653         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5654         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5655         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5656
5657         kvm_make_request(KVM_REQ_EVENT, vcpu);
5658
5659         ++vcpu->stat.irq_window_exits;
5660         return 1;
5661 }
5662
5663 static int handle_halt(struct kvm_vcpu *vcpu)
5664 {
5665         return kvm_emulate_halt(vcpu);
5666 }
5667
5668 static int handle_vmcall(struct kvm_vcpu *vcpu)
5669 {
5670         kvm_emulate_hypercall(vcpu);
5671         return 1;
5672 }
5673
5674 static int handle_invd(struct kvm_vcpu *vcpu)
5675 {
5676         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5677 }
5678
5679 static int handle_invlpg(struct kvm_vcpu *vcpu)
5680 {
5681         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5682
5683         kvm_mmu_invlpg(vcpu, exit_qualification);
5684         skip_emulated_instruction(vcpu);
5685         return 1;
5686 }
5687
5688 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5689 {
5690         int err;
5691
5692         err = kvm_rdpmc(vcpu);
5693         kvm_complete_insn_gp(vcpu, err);
5694
5695         return 1;
5696 }
5697
5698 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5699 {
5700         kvm_emulate_wbinvd(vcpu);
5701         return 1;
5702 }
5703
5704 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5705 {
5706         u64 new_bv = kvm_read_edx_eax(vcpu);
5707         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5708
5709         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5710                 skip_emulated_instruction(vcpu);
5711         return 1;
5712 }
5713
5714 static int handle_xsaves(struct kvm_vcpu *vcpu)
5715 {
5716         skip_emulated_instruction(vcpu);
5717         WARN(1, "this should never happen\n");
5718         return 1;
5719 }
5720
5721 static int handle_xrstors(struct kvm_vcpu *vcpu)
5722 {
5723         skip_emulated_instruction(vcpu);
5724         WARN(1, "this should never happen\n");
5725         return 1;
5726 }
5727
5728 static int handle_apic_access(struct kvm_vcpu *vcpu)
5729 {
5730         if (likely(fasteoi)) {
5731                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5732                 int access_type, offset;
5733
5734                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5735                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5736                 /*
5737                  * Sane guest uses MOV to write EOI, with written value
5738                  * not cared. So make a short-circuit here by avoiding
5739                  * heavy instruction emulation.
5740                  */
5741                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5742                     (offset == APIC_EOI)) {
5743                         kvm_lapic_set_eoi(vcpu);
5744                         skip_emulated_instruction(vcpu);
5745                         return 1;
5746                 }
5747         }
5748         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5749 }
5750
5751 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5752 {
5753         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5754         int vector = exit_qualification & 0xff;
5755
5756         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5757         kvm_apic_set_eoi_accelerated(vcpu, vector);
5758         return 1;
5759 }
5760
5761 static int handle_apic_write(struct kvm_vcpu *vcpu)
5762 {
5763         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5764         u32 offset = exit_qualification & 0xfff;
5765
5766         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5767         kvm_apic_write_nodecode(vcpu, offset);
5768         return 1;
5769 }
5770
5771 static int handle_task_switch(struct kvm_vcpu *vcpu)
5772 {
5773         struct vcpu_vmx *vmx = to_vmx(vcpu);
5774         unsigned long exit_qualification;
5775         bool has_error_code = false;
5776         u32 error_code = 0;
5777         u16 tss_selector;
5778         int reason, type, idt_v, idt_index;
5779
5780         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5781         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5782         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5783
5784         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5785
5786         reason = (u32)exit_qualification >> 30;
5787         if (reason == TASK_SWITCH_GATE && idt_v) {
5788                 switch (type) {
5789                 case INTR_TYPE_NMI_INTR:
5790                         vcpu->arch.nmi_injected = false;
5791                         vmx_set_nmi_mask(vcpu, true);
5792                         break;
5793                 case INTR_TYPE_EXT_INTR:
5794                 case INTR_TYPE_SOFT_INTR:
5795                         kvm_clear_interrupt_queue(vcpu);
5796                         break;
5797                 case INTR_TYPE_HARD_EXCEPTION:
5798                         if (vmx->idt_vectoring_info &
5799                             VECTORING_INFO_DELIVER_CODE_MASK) {
5800                                 has_error_code = true;
5801                                 error_code =
5802                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5803                         }
5804                         /* fall through */
5805                 case INTR_TYPE_SOFT_EXCEPTION:
5806                         kvm_clear_exception_queue(vcpu);
5807                         break;
5808                 default:
5809                         break;
5810                 }
5811         }
5812         tss_selector = exit_qualification;
5813
5814         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5815                        type != INTR_TYPE_EXT_INTR &&
5816                        type != INTR_TYPE_NMI_INTR))
5817                 skip_emulated_instruction(vcpu);
5818
5819         if (kvm_task_switch(vcpu, tss_selector,
5820                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5821                             has_error_code, error_code) == EMULATE_FAIL) {
5822                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5823                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5824                 vcpu->run->internal.ndata = 0;
5825                 return 0;
5826         }
5827
5828         /*
5829          * TODO: What about debug traps on tss switch?
5830          *       Are we supposed to inject them and update dr6?
5831          */
5832
5833         return 1;
5834 }
5835
5836 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5837 {
5838         unsigned long exit_qualification;
5839         gpa_t gpa;
5840         u32 error_code;
5841         int gla_validity;
5842
5843         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5844
5845         gla_validity = (exit_qualification >> 7) & 0x3;
5846         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5847                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5848                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5849                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5850                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5851                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5852                         (long unsigned int)exit_qualification);
5853                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5854                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5855                 return 0;
5856         }
5857
5858         /*
5859          * EPT violation happened while executing iret from NMI,
5860          * "blocked by NMI" bit has to be set before next VM entry.
5861          * There are errata that may cause this bit to not be set:
5862          * AAK134, BY25.
5863          */
5864         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5865                         cpu_has_virtual_nmis() &&
5866                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5867                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5868
5869         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5870         trace_kvm_page_fault(gpa, exit_qualification);
5871
5872         /* It is a write fault? */
5873         error_code = exit_qualification & PFERR_WRITE_MASK;
5874         /* It is a fetch fault? */
5875         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5876         /* ept page table is present? */
5877         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5878
5879         vcpu->arch.exit_qualification = exit_qualification;
5880
5881         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5882 }
5883
5884 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5885 {
5886         int ret;
5887         gpa_t gpa;
5888
5889         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5890         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5891                 skip_emulated_instruction(vcpu);
5892                 trace_kvm_fast_mmio(gpa);
5893                 return 1;
5894         }
5895
5896         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5897         if (likely(ret == RET_MMIO_PF_EMULATE))
5898                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5899                                               EMULATE_DONE;
5900
5901         if (unlikely(ret == RET_MMIO_PF_INVALID))
5902                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5903
5904         if (unlikely(ret == RET_MMIO_PF_RETRY))
5905                 return 1;
5906
5907         /* It is the real ept misconfig */
5908         WARN_ON(1);
5909
5910         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5911         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5912
5913         return 0;
5914 }
5915
5916 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5917 {
5918         u32 cpu_based_vm_exec_control;
5919
5920         /* clear pending NMI */
5921         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5922         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5923         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5924         ++vcpu->stat.nmi_window_exits;
5925         kvm_make_request(KVM_REQ_EVENT, vcpu);
5926
5927         return 1;
5928 }
5929
5930 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5931 {
5932         struct vcpu_vmx *vmx = to_vmx(vcpu);
5933         enum emulation_result err = EMULATE_DONE;
5934         int ret = 1;
5935         u32 cpu_exec_ctrl;
5936         bool intr_window_requested;
5937         unsigned count = 130;
5938
5939         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5940         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5941
5942         while (vmx->emulation_required && count-- != 0) {
5943                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5944                         return handle_interrupt_window(&vmx->vcpu);
5945
5946                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5947                         return 1;
5948
5949                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5950
5951                 if (err == EMULATE_USER_EXIT) {
5952                         ++vcpu->stat.mmio_exits;
5953                         ret = 0;
5954                         goto out;
5955                 }
5956
5957                 if (err != EMULATE_DONE) {
5958                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5959                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5960                         vcpu->run->internal.ndata = 0;
5961                         return 0;
5962                 }
5963
5964                 if (vcpu->arch.halt_request) {
5965                         vcpu->arch.halt_request = 0;
5966                         ret = kvm_vcpu_halt(vcpu);
5967                         goto out;
5968                 }
5969
5970                 if (signal_pending(current))
5971                         goto out;
5972                 if (need_resched())
5973                         schedule();
5974         }
5975
5976 out:
5977         return ret;
5978 }
5979
5980 static int __grow_ple_window(int val)
5981 {
5982         if (ple_window_grow < 1)
5983                 return ple_window;
5984
5985         val = min(val, ple_window_actual_max);
5986
5987         if (ple_window_grow < ple_window)
5988                 val *= ple_window_grow;
5989         else
5990                 val += ple_window_grow;
5991
5992         return val;
5993 }
5994
5995 static int __shrink_ple_window(int val, int modifier, int minimum)
5996 {
5997         if (modifier < 1)
5998                 return ple_window;
5999
6000         if (modifier < ple_window)
6001                 val /= modifier;
6002         else
6003                 val -= modifier;
6004
6005         return max(val, minimum);
6006 }
6007
6008 static void grow_ple_window(struct kvm_vcpu *vcpu)
6009 {
6010         struct vcpu_vmx *vmx = to_vmx(vcpu);
6011         int old = vmx->ple_window;
6012
6013         vmx->ple_window = __grow_ple_window(old);
6014
6015         if (vmx->ple_window != old)
6016                 vmx->ple_window_dirty = true;
6017
6018         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6019 }
6020
6021 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6022 {
6023         struct vcpu_vmx *vmx = to_vmx(vcpu);
6024         int old = vmx->ple_window;
6025
6026         vmx->ple_window = __shrink_ple_window(old,
6027                                               ple_window_shrink, ple_window);
6028
6029         if (vmx->ple_window != old)
6030                 vmx->ple_window_dirty = true;
6031
6032         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6033 }
6034
6035 /*
6036  * ple_window_actual_max is computed to be one grow_ple_window() below
6037  * ple_window_max. (See __grow_ple_window for the reason.)
6038  * This prevents overflows, because ple_window_max is int.
6039  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6040  * this process.
6041  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6042  */
6043 static void update_ple_window_actual_max(void)
6044 {
6045         ple_window_actual_max =
6046                         __shrink_ple_window(max(ple_window_max, ple_window),
6047                                             ple_window_grow, INT_MIN);
6048 }
6049
6050 /*
6051  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6052  */
6053 static void wakeup_handler(void)
6054 {
6055         struct kvm_vcpu *vcpu;
6056         int cpu = smp_processor_id();
6057
6058         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6059         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6060                         blocked_vcpu_list) {
6061                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6062
6063                 if (pi_test_on(pi_desc) == 1)
6064                         kvm_vcpu_kick(vcpu);
6065         }
6066         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6067 }
6068
6069 static __init int hardware_setup(void)
6070 {
6071         int r = -ENOMEM, i, msr;
6072
6073         rdmsrl_safe(MSR_EFER, &host_efer);
6074
6075         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6076                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6077
6078         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6079         if (!vmx_io_bitmap_a)
6080                 return r;
6081
6082         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6083         if (!vmx_io_bitmap_b)
6084                 goto out;
6085
6086         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6087         if (!vmx_msr_bitmap_legacy)
6088                 goto out1;
6089
6090         vmx_msr_bitmap_legacy_x2apic =
6091                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6092         if (!vmx_msr_bitmap_legacy_x2apic)
6093                 goto out2;
6094
6095         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6096         if (!vmx_msr_bitmap_longmode)
6097                 goto out3;
6098
6099         vmx_msr_bitmap_longmode_x2apic =
6100                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6101         if (!vmx_msr_bitmap_longmode_x2apic)
6102                 goto out4;
6103
6104         if (nested) {
6105                 vmx_msr_bitmap_nested =
6106                         (unsigned long *)__get_free_page(GFP_KERNEL);
6107                 if (!vmx_msr_bitmap_nested)
6108                         goto out5;
6109         }
6110
6111         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6112         if (!vmx_vmread_bitmap)
6113                 goto out6;
6114
6115         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6116         if (!vmx_vmwrite_bitmap)
6117                 goto out7;
6118
6119         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6120         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6121
6122         /*
6123          * Allow direct access to the PC debug port (it is often used for I/O
6124          * delays, but the vmexits simply slow things down).
6125          */
6126         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6127         clear_bit(0x80, vmx_io_bitmap_a);
6128
6129         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6130
6131         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6132         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6133         if (nested)
6134                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6135
6136         if (setup_vmcs_config(&vmcs_config) < 0) {
6137                 r = -EIO;
6138                 goto out8;
6139         }
6140
6141         if (boot_cpu_has(X86_FEATURE_NX))
6142                 kvm_enable_efer_bits(EFER_NX);
6143
6144         if (!cpu_has_vmx_vpid())
6145                 enable_vpid = 0;
6146         if (!cpu_has_vmx_shadow_vmcs())
6147                 enable_shadow_vmcs = 0;
6148         if (enable_shadow_vmcs)
6149                 init_vmcs_shadow_fields();
6150
6151         if (!cpu_has_vmx_ept() ||
6152             !cpu_has_vmx_ept_4levels()) {
6153                 enable_ept = 0;
6154                 enable_unrestricted_guest = 0;
6155                 enable_ept_ad_bits = 0;
6156         }
6157
6158         if (!cpu_has_vmx_ept_ad_bits())
6159                 enable_ept_ad_bits = 0;
6160
6161         if (!cpu_has_vmx_unrestricted_guest())
6162                 enable_unrestricted_guest = 0;
6163
6164         if (!cpu_has_vmx_flexpriority())
6165                 flexpriority_enabled = 0;
6166
6167         /*
6168          * set_apic_access_page_addr() is used to reload apic access
6169          * page upon invalidation.  No need to do anything if not
6170          * using the APIC_ACCESS_ADDR VMCS field.
6171          */
6172         if (!flexpriority_enabled)
6173                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6174
6175         if (!cpu_has_vmx_tpr_shadow())
6176                 kvm_x86_ops->update_cr8_intercept = NULL;
6177
6178         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6179                 kvm_disable_largepages();
6180
6181         if (!cpu_has_vmx_ple())
6182                 ple_gap = 0;
6183
6184         if (!cpu_has_vmx_apicv())
6185                 enable_apicv = 0;
6186
6187         if (enable_apicv)
6188                 kvm_x86_ops->update_cr8_intercept = NULL;
6189         else {
6190                 kvm_x86_ops->hwapic_irr_update = NULL;
6191                 kvm_x86_ops->hwapic_isr_update = NULL;
6192                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6193                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6194         }
6195
6196         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6197         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6198         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6199         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6200         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6201         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6202         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6203
6204         memcpy(vmx_msr_bitmap_legacy_x2apic,
6205                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6206         memcpy(vmx_msr_bitmap_longmode_x2apic,
6207                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6208
6209         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6210
6211         if (enable_apicv) {
6212                 for (msr = 0x800; msr <= 0x8ff; msr++)
6213                         vmx_disable_intercept_msr_read_x2apic(msr);
6214
6215                 /* According SDM, in x2apic mode, the whole id reg is used.
6216                  * But in KVM, it only use the highest eight bits. Need to
6217                  * intercept it */
6218                 vmx_enable_intercept_msr_read_x2apic(0x802);
6219                 /* TMCCT */
6220                 vmx_enable_intercept_msr_read_x2apic(0x839);
6221                 /* TPR */
6222                 vmx_disable_intercept_msr_write_x2apic(0x808);
6223                 /* EOI */
6224                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6225                 /* SELF-IPI */
6226                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6227         }
6228
6229         if (enable_ept) {
6230                 kvm_mmu_set_mask_ptes(0ull,
6231                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6232                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6233                         0ull, VMX_EPT_EXECUTABLE_MASK);
6234                 ept_set_mmio_spte_mask();
6235                 kvm_enable_tdp();
6236         } else
6237                 kvm_disable_tdp();
6238
6239         update_ple_window_actual_max();
6240
6241         /*
6242          * Only enable PML when hardware supports PML feature, and both EPT
6243          * and EPT A/D bit features are enabled -- PML depends on them to work.
6244          */
6245         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6246                 enable_pml = 0;
6247
6248         if (!enable_pml) {
6249                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6250                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6251                 kvm_x86_ops->flush_log_dirty = NULL;
6252                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6253         }
6254
6255         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6256
6257         return alloc_kvm_area();
6258
6259 out8:
6260         free_page((unsigned long)vmx_vmwrite_bitmap);
6261 out7:
6262         free_page((unsigned long)vmx_vmread_bitmap);
6263 out6:
6264         if (nested)
6265                 free_page((unsigned long)vmx_msr_bitmap_nested);
6266 out5:
6267         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6268 out4:
6269         free_page((unsigned long)vmx_msr_bitmap_longmode);
6270 out3:
6271         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6272 out2:
6273         free_page((unsigned long)vmx_msr_bitmap_legacy);
6274 out1:
6275         free_page((unsigned long)vmx_io_bitmap_b);
6276 out:
6277         free_page((unsigned long)vmx_io_bitmap_a);
6278
6279     return r;
6280 }
6281
6282 static __exit void hardware_unsetup(void)
6283 {
6284         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6285         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6286         free_page((unsigned long)vmx_msr_bitmap_legacy);
6287         free_page((unsigned long)vmx_msr_bitmap_longmode);
6288         free_page((unsigned long)vmx_io_bitmap_b);
6289         free_page((unsigned long)vmx_io_bitmap_a);
6290         free_page((unsigned long)vmx_vmwrite_bitmap);
6291         free_page((unsigned long)vmx_vmread_bitmap);
6292         if (nested)
6293                 free_page((unsigned long)vmx_msr_bitmap_nested);
6294
6295         free_kvm_area();
6296 }
6297
6298 /*
6299  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6300  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6301  */
6302 static int handle_pause(struct kvm_vcpu *vcpu)
6303 {
6304         if (ple_gap)
6305                 grow_ple_window(vcpu);
6306
6307         skip_emulated_instruction(vcpu);
6308         kvm_vcpu_on_spin(vcpu);
6309
6310         return 1;
6311 }
6312
6313 static int handle_nop(struct kvm_vcpu *vcpu)
6314 {
6315         skip_emulated_instruction(vcpu);
6316         return 1;
6317 }
6318
6319 static int handle_mwait(struct kvm_vcpu *vcpu)
6320 {
6321         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6322         return handle_nop(vcpu);
6323 }
6324
6325 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6326 {
6327         return 1;
6328 }
6329
6330 static int handle_monitor(struct kvm_vcpu *vcpu)
6331 {
6332         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6333         return handle_nop(vcpu);
6334 }
6335
6336 /*
6337  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6338  * We could reuse a single VMCS for all the L2 guests, but we also want the
6339  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6340  * allows keeping them loaded on the processor, and in the future will allow
6341  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6342  * every entry if they never change.
6343  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6344  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6345  *
6346  * The following functions allocate and free a vmcs02 in this pool.
6347  */
6348
6349 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6350 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6351 {
6352         struct vmcs02_list *item;
6353         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6354                 if (item->vmptr == vmx->nested.current_vmptr) {
6355                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6356                         return &item->vmcs02;
6357                 }
6358
6359         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6360                 /* Recycle the least recently used VMCS. */
6361                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6362                         struct vmcs02_list, list);
6363                 item->vmptr = vmx->nested.current_vmptr;
6364                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6365                 return &item->vmcs02;
6366         }
6367
6368         /* Create a new VMCS */
6369         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6370         if (!item)
6371                 return NULL;
6372         item->vmcs02.vmcs = alloc_vmcs();
6373         if (!item->vmcs02.vmcs) {
6374                 kfree(item);
6375                 return NULL;
6376         }
6377         loaded_vmcs_init(&item->vmcs02);
6378         item->vmptr = vmx->nested.current_vmptr;
6379         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6380         vmx->nested.vmcs02_num++;
6381         return &item->vmcs02;
6382 }
6383
6384 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6385 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6386 {
6387         struct vmcs02_list *item;
6388         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6389                 if (item->vmptr == vmptr) {
6390                         free_loaded_vmcs(&item->vmcs02);
6391                         list_del(&item->list);
6392                         kfree(item);
6393                         vmx->nested.vmcs02_num--;
6394                         return;
6395                 }
6396 }
6397
6398 /*
6399  * Free all VMCSs saved for this vcpu, except the one pointed by
6400  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6401  * must be &vmx->vmcs01.
6402  */
6403 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6404 {
6405         struct vmcs02_list *item, *n;
6406
6407         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6408         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6409                 /*
6410                  * Something will leak if the above WARN triggers.  Better than
6411                  * a use-after-free.
6412                  */
6413                 if (vmx->loaded_vmcs == &item->vmcs02)
6414                         continue;
6415
6416                 free_loaded_vmcs(&item->vmcs02);
6417                 list_del(&item->list);
6418                 kfree(item);
6419                 vmx->nested.vmcs02_num--;
6420         }
6421 }
6422
6423 /*
6424  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6425  * set the success or error code of an emulated VMX instruction, as specified
6426  * by Vol 2B, VMX Instruction Reference, "Conventions".
6427  */
6428 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6429 {
6430         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6431                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6432                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6433 }
6434
6435 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6436 {
6437         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6438                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6439                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6440                         | X86_EFLAGS_CF);
6441 }
6442
6443 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6444                                         u32 vm_instruction_error)
6445 {
6446         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6447                 /*
6448                  * failValid writes the error number to the current VMCS, which
6449                  * can't be done there isn't a current VMCS.
6450                  */
6451                 nested_vmx_failInvalid(vcpu);
6452                 return;
6453         }
6454         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6455                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6456                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6457                         | X86_EFLAGS_ZF);
6458         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6459         /*
6460          * We don't need to force a shadow sync because
6461          * VM_INSTRUCTION_ERROR is not shadowed
6462          */
6463 }
6464
6465 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6466 {
6467         /* TODO: not to reset guest simply here. */
6468         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6469         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6470 }
6471
6472 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6473 {
6474         struct vcpu_vmx *vmx =
6475                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6476
6477         vmx->nested.preemption_timer_expired = true;
6478         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6479         kvm_vcpu_kick(&vmx->vcpu);
6480
6481         return HRTIMER_NORESTART;
6482 }
6483
6484 /*
6485  * Decode the memory-address operand of a vmx instruction, as recorded on an
6486  * exit caused by such an instruction (run by a guest hypervisor).
6487  * On success, returns 0. When the operand is invalid, returns 1 and throws
6488  * #UD or #GP.
6489  */
6490 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6491                                  unsigned long exit_qualification,
6492                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6493 {
6494         gva_t off;
6495         bool exn;
6496         struct kvm_segment s;
6497
6498         /*
6499          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6500          * Execution", on an exit, vmx_instruction_info holds most of the
6501          * addressing components of the operand. Only the displacement part
6502          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6503          * For how an actual address is calculated from all these components,
6504          * refer to Vol. 1, "Operand Addressing".
6505          */
6506         int  scaling = vmx_instruction_info & 3;
6507         int  addr_size = (vmx_instruction_info >> 7) & 7;
6508         bool is_reg = vmx_instruction_info & (1u << 10);
6509         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6510         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6511         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6512         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6513         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6514
6515         if (is_reg) {
6516                 kvm_queue_exception(vcpu, UD_VECTOR);
6517                 return 1;
6518         }
6519
6520         /* Addr = segment_base + offset */
6521         /* offset = base + [index * scale] + displacement */
6522         off = exit_qualification; /* holds the displacement */
6523         if (base_is_valid)
6524                 off += kvm_register_read(vcpu, base_reg);
6525         if (index_is_valid)
6526                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6527         vmx_get_segment(vcpu, &s, seg_reg);
6528         *ret = s.base + off;
6529
6530         if (addr_size == 1) /* 32 bit */
6531                 *ret &= 0xffffffff;
6532
6533         /* Checks for #GP/#SS exceptions. */
6534         exn = false;
6535         if (is_protmode(vcpu)) {
6536                 /* Protected mode: apply checks for segment validity in the
6537                  * following order:
6538                  * - segment type check (#GP(0) may be thrown)
6539                  * - usability check (#GP(0)/#SS(0))
6540                  * - limit check (#GP(0)/#SS(0))
6541                  */
6542                 if (wr)
6543                         /* #GP(0) if the destination operand is located in a
6544                          * read-only data segment or any code segment.
6545                          */
6546                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6547                 else
6548                         /* #GP(0) if the source operand is located in an
6549                          * execute-only code segment
6550                          */
6551                         exn = ((s.type & 0xa) == 8);
6552         }
6553         if (exn) {
6554                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6555                 return 1;
6556         }
6557         if (is_long_mode(vcpu)) {
6558                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6559                  * non-canonical form. This is an only check for long mode.
6560                  */
6561                 exn = is_noncanonical_address(*ret);
6562         } else if (is_protmode(vcpu)) {
6563                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6564                  */
6565                 exn = (s.unusable != 0);
6566                 /* Protected mode: #GP(0)/#SS(0) if the memory
6567                  * operand is outside the segment limit.
6568                  */
6569                 exn = exn || (off + sizeof(u64) > s.limit);
6570         }
6571         if (exn) {
6572                 kvm_queue_exception_e(vcpu,
6573                                       seg_reg == VCPU_SREG_SS ?
6574                                                 SS_VECTOR : GP_VECTOR,
6575                                       0);
6576                 return 1;
6577         }
6578
6579         return 0;
6580 }
6581
6582 /*
6583  * This function performs the various checks including
6584  * - if it's 4KB aligned
6585  * - No bits beyond the physical address width are set
6586  * - Returns 0 on success or else 1
6587  * (Intel SDM Section 30.3)
6588  */
6589 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6590                                   gpa_t *vmpointer)
6591 {
6592         gva_t gva;
6593         gpa_t vmptr;
6594         struct x86_exception e;
6595         struct page *page;
6596         struct vcpu_vmx *vmx = to_vmx(vcpu);
6597         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6598
6599         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6600                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6601                 return 1;
6602
6603         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6604                                 sizeof(vmptr), &e)) {
6605                 kvm_inject_page_fault(vcpu, &e);
6606                 return 1;
6607         }
6608
6609         switch (exit_reason) {
6610         case EXIT_REASON_VMON:
6611                 /*
6612                  * SDM 3: 24.11.5
6613                  * The first 4 bytes of VMXON region contain the supported
6614                  * VMCS revision identifier
6615                  *
6616                  * Note - IA32_VMX_BASIC[48] will never be 1
6617                  * for the nested case;
6618                  * which replaces physical address width with 32
6619                  *
6620                  */
6621                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6622                         nested_vmx_failInvalid(vcpu);
6623                         skip_emulated_instruction(vcpu);
6624                         return 1;
6625                 }
6626
6627                 page = nested_get_page(vcpu, vmptr);
6628                 if (page == NULL ||
6629                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6630                         nested_vmx_failInvalid(vcpu);
6631                         kunmap(page);
6632                         skip_emulated_instruction(vcpu);
6633                         return 1;
6634                 }
6635                 kunmap(page);
6636                 vmx->nested.vmxon_ptr = vmptr;
6637                 break;
6638         case EXIT_REASON_VMCLEAR:
6639                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6640                         nested_vmx_failValid(vcpu,
6641                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6642                         skip_emulated_instruction(vcpu);
6643                         return 1;
6644                 }
6645
6646                 if (vmptr == vmx->nested.vmxon_ptr) {
6647                         nested_vmx_failValid(vcpu,
6648                                              VMXERR_VMCLEAR_VMXON_POINTER);
6649                         skip_emulated_instruction(vcpu);
6650                         return 1;
6651                 }
6652                 break;
6653         case EXIT_REASON_VMPTRLD:
6654                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6655                         nested_vmx_failValid(vcpu,
6656                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6657                         skip_emulated_instruction(vcpu);
6658                         return 1;
6659                 }
6660
6661                 if (vmptr == vmx->nested.vmxon_ptr) {
6662                         nested_vmx_failValid(vcpu,
6663                                              VMXERR_VMCLEAR_VMXON_POINTER);
6664                         skip_emulated_instruction(vcpu);
6665                         return 1;
6666                 }
6667                 break;
6668         default:
6669                 return 1; /* shouldn't happen */
6670         }
6671
6672         if (vmpointer)
6673                 *vmpointer = vmptr;
6674         return 0;
6675 }
6676
6677 /*
6678  * Emulate the VMXON instruction.
6679  * Currently, we just remember that VMX is active, and do not save or even
6680  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6681  * do not currently need to store anything in that guest-allocated memory
6682  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6683  * argument is different from the VMXON pointer (which the spec says they do).
6684  */
6685 static int handle_vmon(struct kvm_vcpu *vcpu)
6686 {
6687         struct kvm_segment cs;
6688         struct vcpu_vmx *vmx = to_vmx(vcpu);
6689         struct vmcs *shadow_vmcs;
6690         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6691                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6692
6693         /* The Intel VMX Instruction Reference lists a bunch of bits that
6694          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6695          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6696          * Otherwise, we should fail with #UD. We test these now:
6697          */
6698         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6699             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6700             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6701                 kvm_queue_exception(vcpu, UD_VECTOR);
6702                 return 1;
6703         }
6704
6705         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6706         if (is_long_mode(vcpu) && !cs.l) {
6707                 kvm_queue_exception(vcpu, UD_VECTOR);
6708                 return 1;
6709         }
6710
6711         if (vmx_get_cpl(vcpu)) {
6712                 kvm_inject_gp(vcpu, 0);
6713                 return 1;
6714         }
6715
6716         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6717                 return 1;
6718
6719         if (vmx->nested.vmxon) {
6720                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6721                 skip_emulated_instruction(vcpu);
6722                 return 1;
6723         }
6724
6725         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6726                         != VMXON_NEEDED_FEATURES) {
6727                 kvm_inject_gp(vcpu, 0);
6728                 return 1;
6729         }
6730
6731         if (enable_shadow_vmcs) {
6732                 shadow_vmcs = alloc_vmcs();
6733                 if (!shadow_vmcs)
6734                         return -ENOMEM;
6735                 /* mark vmcs as shadow */
6736                 shadow_vmcs->revision_id |= (1u << 31);
6737                 /* init shadow vmcs */
6738                 vmcs_clear(shadow_vmcs);
6739                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6740         }
6741
6742         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6743         vmx->nested.vmcs02_num = 0;
6744
6745         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6746                      HRTIMER_MODE_REL);
6747         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6748
6749         vmx->nested.vmxon = true;
6750
6751         skip_emulated_instruction(vcpu);
6752         nested_vmx_succeed(vcpu);
6753         return 1;
6754 }
6755
6756 /*
6757  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6758  * for running VMX instructions (except VMXON, whose prerequisites are
6759  * slightly different). It also specifies what exception to inject otherwise.
6760  */
6761 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6762 {
6763         struct kvm_segment cs;
6764         struct vcpu_vmx *vmx = to_vmx(vcpu);
6765
6766         if (!vmx->nested.vmxon) {
6767                 kvm_queue_exception(vcpu, UD_VECTOR);
6768                 return 0;
6769         }
6770
6771         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6772         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6773             (is_long_mode(vcpu) && !cs.l)) {
6774                 kvm_queue_exception(vcpu, UD_VECTOR);
6775                 return 0;
6776         }
6777
6778         if (vmx_get_cpl(vcpu)) {
6779                 kvm_inject_gp(vcpu, 0);
6780                 return 0;
6781         }
6782
6783         return 1;
6784 }
6785
6786 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6787 {
6788         if (vmx->nested.current_vmptr == -1ull)
6789                 return;
6790
6791         /* current_vmptr and current_vmcs12 are always set/reset together */
6792         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6793                 return;
6794
6795         if (enable_shadow_vmcs) {
6796                 /* copy to memory all shadowed fields in case
6797                    they were modified */
6798                 copy_shadow_to_vmcs12(vmx);
6799                 vmx->nested.sync_shadow_vmcs = false;
6800                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6801                                 SECONDARY_EXEC_SHADOW_VMCS);
6802                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6803         }
6804         vmx->nested.posted_intr_nv = -1;
6805         kunmap(vmx->nested.current_vmcs12_page);
6806         nested_release_page(vmx->nested.current_vmcs12_page);
6807         vmx->nested.current_vmptr = -1ull;
6808         vmx->nested.current_vmcs12 = NULL;
6809 }
6810
6811 /*
6812  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6813  * just stops using VMX.
6814  */
6815 static void free_nested(struct vcpu_vmx *vmx)
6816 {
6817         if (!vmx->nested.vmxon)
6818                 return;
6819
6820         vmx->nested.vmxon = false;
6821         nested_release_vmcs12(vmx);
6822         if (enable_shadow_vmcs)
6823                 free_vmcs(vmx->nested.current_shadow_vmcs);
6824         /* Unpin physical memory we referred to in current vmcs02 */
6825         if (vmx->nested.apic_access_page) {
6826                 nested_release_page(vmx->nested.apic_access_page);
6827                 vmx->nested.apic_access_page = NULL;
6828         }
6829         if (vmx->nested.virtual_apic_page) {
6830                 nested_release_page(vmx->nested.virtual_apic_page);
6831                 vmx->nested.virtual_apic_page = NULL;
6832         }
6833         if (vmx->nested.pi_desc_page) {
6834                 kunmap(vmx->nested.pi_desc_page);
6835                 nested_release_page(vmx->nested.pi_desc_page);
6836                 vmx->nested.pi_desc_page = NULL;
6837                 vmx->nested.pi_desc = NULL;
6838         }
6839
6840         nested_free_all_saved_vmcss(vmx);
6841 }
6842
6843 /* Emulate the VMXOFF instruction */
6844 static int handle_vmoff(struct kvm_vcpu *vcpu)
6845 {
6846         if (!nested_vmx_check_permission(vcpu))
6847                 return 1;
6848         free_nested(to_vmx(vcpu));
6849         skip_emulated_instruction(vcpu);
6850         nested_vmx_succeed(vcpu);
6851         return 1;
6852 }
6853
6854 /* Emulate the VMCLEAR instruction */
6855 static int handle_vmclear(struct kvm_vcpu *vcpu)
6856 {
6857         struct vcpu_vmx *vmx = to_vmx(vcpu);
6858         gpa_t vmptr;
6859         struct vmcs12 *vmcs12;
6860         struct page *page;
6861
6862         if (!nested_vmx_check_permission(vcpu))
6863                 return 1;
6864
6865         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6866                 return 1;
6867
6868         if (vmptr == vmx->nested.current_vmptr)
6869                 nested_release_vmcs12(vmx);
6870
6871         page = nested_get_page(vcpu, vmptr);
6872         if (page == NULL) {
6873                 /*
6874                  * For accurate processor emulation, VMCLEAR beyond available
6875                  * physical memory should do nothing at all. However, it is
6876                  * possible that a nested vmx bug, not a guest hypervisor bug,
6877                  * resulted in this case, so let's shut down before doing any
6878                  * more damage:
6879                  */
6880                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6881                 return 1;
6882         }
6883         vmcs12 = kmap(page);
6884         vmcs12->launch_state = 0;
6885         kunmap(page);
6886         nested_release_page(page);
6887
6888         nested_free_vmcs02(vmx, vmptr);
6889
6890         skip_emulated_instruction(vcpu);
6891         nested_vmx_succeed(vcpu);
6892         return 1;
6893 }
6894
6895 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6896
6897 /* Emulate the VMLAUNCH instruction */
6898 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6899 {
6900         return nested_vmx_run(vcpu, true);
6901 }
6902
6903 /* Emulate the VMRESUME instruction */
6904 static int handle_vmresume(struct kvm_vcpu *vcpu)
6905 {
6906
6907         return nested_vmx_run(vcpu, false);
6908 }
6909
6910 enum vmcs_field_type {
6911         VMCS_FIELD_TYPE_U16 = 0,
6912         VMCS_FIELD_TYPE_U64 = 1,
6913         VMCS_FIELD_TYPE_U32 = 2,
6914         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6915 };
6916
6917 static inline int vmcs_field_type(unsigned long field)
6918 {
6919         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6920                 return VMCS_FIELD_TYPE_U32;
6921         return (field >> 13) & 0x3 ;
6922 }
6923
6924 static inline int vmcs_field_readonly(unsigned long field)
6925 {
6926         return (((field >> 10) & 0x3) == 1);
6927 }
6928
6929 /*
6930  * Read a vmcs12 field. Since these can have varying lengths and we return
6931  * one type, we chose the biggest type (u64) and zero-extend the return value
6932  * to that size. Note that the caller, handle_vmread, might need to use only
6933  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6934  * 64-bit fields are to be returned).
6935  */
6936 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6937                                   unsigned long field, u64 *ret)
6938 {
6939         short offset = vmcs_field_to_offset(field);
6940         char *p;
6941
6942         if (offset < 0)
6943                 return offset;
6944
6945         p = ((char *)(get_vmcs12(vcpu))) + offset;
6946
6947         switch (vmcs_field_type(field)) {
6948         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6949                 *ret = *((natural_width *)p);
6950                 return 0;
6951         case VMCS_FIELD_TYPE_U16:
6952                 *ret = *((u16 *)p);
6953                 return 0;
6954         case VMCS_FIELD_TYPE_U32:
6955                 *ret = *((u32 *)p);
6956                 return 0;
6957         case VMCS_FIELD_TYPE_U64:
6958                 *ret = *((u64 *)p);
6959                 return 0;
6960         default:
6961                 WARN_ON(1);
6962                 return -ENOENT;
6963         }
6964 }
6965
6966
6967 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6968                                    unsigned long field, u64 field_value){
6969         short offset = vmcs_field_to_offset(field);
6970         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6971         if (offset < 0)
6972                 return offset;
6973
6974         switch (vmcs_field_type(field)) {
6975         case VMCS_FIELD_TYPE_U16:
6976                 *(u16 *)p = field_value;
6977                 return 0;
6978         case VMCS_FIELD_TYPE_U32:
6979                 *(u32 *)p = field_value;
6980                 return 0;
6981         case VMCS_FIELD_TYPE_U64:
6982                 *(u64 *)p = field_value;
6983                 return 0;
6984         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6985                 *(natural_width *)p = field_value;
6986                 return 0;
6987         default:
6988                 WARN_ON(1);
6989                 return -ENOENT;
6990         }
6991
6992 }
6993
6994 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6995 {
6996         int i;
6997         unsigned long field;
6998         u64 field_value;
6999         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7000         const unsigned long *fields = shadow_read_write_fields;
7001         const int num_fields = max_shadow_read_write_fields;
7002
7003         preempt_disable();
7004
7005         vmcs_load(shadow_vmcs);
7006
7007         for (i = 0; i < num_fields; i++) {
7008                 field = fields[i];
7009                 switch (vmcs_field_type(field)) {
7010                 case VMCS_FIELD_TYPE_U16:
7011                         field_value = vmcs_read16(field);
7012                         break;
7013                 case VMCS_FIELD_TYPE_U32:
7014                         field_value = vmcs_read32(field);
7015                         break;
7016                 case VMCS_FIELD_TYPE_U64:
7017                         field_value = vmcs_read64(field);
7018                         break;
7019                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7020                         field_value = vmcs_readl(field);
7021                         break;
7022                 default:
7023                         WARN_ON(1);
7024                         continue;
7025                 }
7026                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7027         }
7028
7029         vmcs_clear(shadow_vmcs);
7030         vmcs_load(vmx->loaded_vmcs->vmcs);
7031
7032         preempt_enable();
7033 }
7034
7035 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7036 {
7037         const unsigned long *fields[] = {
7038                 shadow_read_write_fields,
7039                 shadow_read_only_fields
7040         };
7041         const int max_fields[] = {
7042                 max_shadow_read_write_fields,
7043                 max_shadow_read_only_fields
7044         };
7045         int i, q;
7046         unsigned long field;
7047         u64 field_value = 0;
7048         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7049
7050         vmcs_load(shadow_vmcs);
7051
7052         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7053                 for (i = 0; i < max_fields[q]; i++) {
7054                         field = fields[q][i];
7055                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7056
7057                         switch (vmcs_field_type(field)) {
7058                         case VMCS_FIELD_TYPE_U16:
7059                                 vmcs_write16(field, (u16)field_value);
7060                                 break;
7061                         case VMCS_FIELD_TYPE_U32:
7062                                 vmcs_write32(field, (u32)field_value);
7063                                 break;
7064                         case VMCS_FIELD_TYPE_U64:
7065                                 vmcs_write64(field, (u64)field_value);
7066                                 break;
7067                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7068                                 vmcs_writel(field, (long)field_value);
7069                                 break;
7070                         default:
7071                                 WARN_ON(1);
7072                                 break;
7073                         }
7074                 }
7075         }
7076
7077         vmcs_clear(shadow_vmcs);
7078         vmcs_load(vmx->loaded_vmcs->vmcs);
7079 }
7080
7081 /*
7082  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7083  * used before) all generate the same failure when it is missing.
7084  */
7085 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7086 {
7087         struct vcpu_vmx *vmx = to_vmx(vcpu);
7088         if (vmx->nested.current_vmptr == -1ull) {
7089                 nested_vmx_failInvalid(vcpu);
7090                 skip_emulated_instruction(vcpu);
7091                 return 0;
7092         }
7093         return 1;
7094 }
7095
7096 static int handle_vmread(struct kvm_vcpu *vcpu)
7097 {
7098         unsigned long field;
7099         u64 field_value;
7100         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7101         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7102         gva_t gva = 0;
7103
7104         if (!nested_vmx_check_permission(vcpu) ||
7105             !nested_vmx_check_vmcs12(vcpu))
7106                 return 1;
7107
7108         /* Decode instruction info and find the field to read */
7109         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7110         /* Read the field, zero-extended to a u64 field_value */
7111         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7112                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7113                 skip_emulated_instruction(vcpu);
7114                 return 1;
7115         }
7116         /*
7117          * Now copy part of this value to register or memory, as requested.
7118          * Note that the number of bits actually copied is 32 or 64 depending
7119          * on the guest's mode (32 or 64 bit), not on the given field's length.
7120          */
7121         if (vmx_instruction_info & (1u << 10)) {
7122                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7123                         field_value);
7124         } else {
7125                 if (get_vmx_mem_address(vcpu, exit_qualification,
7126                                 vmx_instruction_info, true, &gva))
7127                         return 1;
7128                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7129                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7130                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7131         }
7132
7133         nested_vmx_succeed(vcpu);
7134         skip_emulated_instruction(vcpu);
7135         return 1;
7136 }
7137
7138
7139 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7140 {
7141         unsigned long field;
7142         gva_t gva;
7143         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7144         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7145         /* The value to write might be 32 or 64 bits, depending on L1's long
7146          * mode, and eventually we need to write that into a field of several
7147          * possible lengths. The code below first zero-extends the value to 64
7148          * bit (field_value), and then copies only the approriate number of
7149          * bits into the vmcs12 field.
7150          */
7151         u64 field_value = 0;
7152         struct x86_exception e;
7153
7154         if (!nested_vmx_check_permission(vcpu) ||
7155             !nested_vmx_check_vmcs12(vcpu))
7156                 return 1;
7157
7158         if (vmx_instruction_info & (1u << 10))
7159                 field_value = kvm_register_readl(vcpu,
7160                         (((vmx_instruction_info) >> 3) & 0xf));
7161         else {
7162                 if (get_vmx_mem_address(vcpu, exit_qualification,
7163                                 vmx_instruction_info, false, &gva))
7164                         return 1;
7165                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7166                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7167                         kvm_inject_page_fault(vcpu, &e);
7168                         return 1;
7169                 }
7170         }
7171
7172
7173         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7174         if (vmcs_field_readonly(field)) {
7175                 nested_vmx_failValid(vcpu,
7176                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7177                 skip_emulated_instruction(vcpu);
7178                 return 1;
7179         }
7180
7181         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7182                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7183                 skip_emulated_instruction(vcpu);
7184                 return 1;
7185         }
7186
7187         nested_vmx_succeed(vcpu);
7188         skip_emulated_instruction(vcpu);
7189         return 1;
7190 }
7191
7192 /* Emulate the VMPTRLD instruction */
7193 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7194 {
7195         struct vcpu_vmx *vmx = to_vmx(vcpu);
7196         gpa_t vmptr;
7197
7198         if (!nested_vmx_check_permission(vcpu))
7199                 return 1;
7200
7201         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7202                 return 1;
7203
7204         if (vmx->nested.current_vmptr != vmptr) {
7205                 struct vmcs12 *new_vmcs12;
7206                 struct page *page;
7207                 page = nested_get_page(vcpu, vmptr);
7208                 if (page == NULL) {
7209                         nested_vmx_failInvalid(vcpu);
7210                         skip_emulated_instruction(vcpu);
7211                         return 1;
7212                 }
7213                 new_vmcs12 = kmap(page);
7214                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7215                         kunmap(page);
7216                         nested_release_page_clean(page);
7217                         nested_vmx_failValid(vcpu,
7218                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7219                         skip_emulated_instruction(vcpu);
7220                         return 1;
7221                 }
7222
7223                 nested_release_vmcs12(vmx);
7224                 vmx->nested.current_vmptr = vmptr;
7225                 vmx->nested.current_vmcs12 = new_vmcs12;
7226                 vmx->nested.current_vmcs12_page = page;
7227                 if (enable_shadow_vmcs) {
7228                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7229                                       SECONDARY_EXEC_SHADOW_VMCS);
7230                         vmcs_write64(VMCS_LINK_POINTER,
7231                                      __pa(vmx->nested.current_shadow_vmcs));
7232                         vmx->nested.sync_shadow_vmcs = true;
7233                 }
7234         }
7235
7236         nested_vmx_succeed(vcpu);
7237         skip_emulated_instruction(vcpu);
7238         return 1;
7239 }
7240
7241 /* Emulate the VMPTRST instruction */
7242 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7243 {
7244         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7245         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7246         gva_t vmcs_gva;
7247         struct x86_exception e;
7248
7249         if (!nested_vmx_check_permission(vcpu))
7250                 return 1;
7251
7252         if (get_vmx_mem_address(vcpu, exit_qualification,
7253                         vmx_instruction_info, true, &vmcs_gva))
7254                 return 1;
7255         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7256         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7257                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7258                                  sizeof(u64), &e)) {
7259                 kvm_inject_page_fault(vcpu, &e);
7260                 return 1;
7261         }
7262         nested_vmx_succeed(vcpu);
7263         skip_emulated_instruction(vcpu);
7264         return 1;
7265 }
7266
7267 /* Emulate the INVEPT instruction */
7268 static int handle_invept(struct kvm_vcpu *vcpu)
7269 {
7270         struct vcpu_vmx *vmx = to_vmx(vcpu);
7271         u32 vmx_instruction_info, types;
7272         unsigned long type;
7273         gva_t gva;
7274         struct x86_exception e;
7275         struct {
7276                 u64 eptp, gpa;
7277         } operand;
7278
7279         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7280               SECONDARY_EXEC_ENABLE_EPT) ||
7281             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7282                 kvm_queue_exception(vcpu, UD_VECTOR);
7283                 return 1;
7284         }
7285
7286         if (!nested_vmx_check_permission(vcpu))
7287                 return 1;
7288
7289         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7290                 kvm_queue_exception(vcpu, UD_VECTOR);
7291                 return 1;
7292         }
7293
7294         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7295         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7296
7297         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7298
7299         if (!(types & (1UL << type))) {
7300                 nested_vmx_failValid(vcpu,
7301                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7302                 return 1;
7303         }
7304
7305         /* According to the Intel VMX instruction reference, the memory
7306          * operand is read even if it isn't needed (e.g., for type==global)
7307          */
7308         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7309                         vmx_instruction_info, false, &gva))
7310                 return 1;
7311         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7312                                 sizeof(operand), &e)) {
7313                 kvm_inject_page_fault(vcpu, &e);
7314                 return 1;
7315         }
7316
7317         switch (type) {
7318         case VMX_EPT_EXTENT_GLOBAL:
7319                 kvm_mmu_sync_roots(vcpu);
7320                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7321                 nested_vmx_succeed(vcpu);
7322                 break;
7323         default:
7324                 /* Trap single context invalidation invept calls */
7325                 BUG_ON(1);
7326                 break;
7327         }
7328
7329         skip_emulated_instruction(vcpu);
7330         return 1;
7331 }
7332
7333 static int handle_invvpid(struct kvm_vcpu *vcpu)
7334 {
7335         struct vcpu_vmx *vmx = to_vmx(vcpu);
7336         u32 vmx_instruction_info;
7337         unsigned long type, types;
7338         gva_t gva;
7339         struct x86_exception e;
7340         int vpid;
7341
7342         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7343               SECONDARY_EXEC_ENABLE_VPID) ||
7344                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7345                 kvm_queue_exception(vcpu, UD_VECTOR);
7346                 return 1;
7347         }
7348
7349         if (!nested_vmx_check_permission(vcpu))
7350                 return 1;
7351
7352         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7353         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7354
7355         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7356
7357         if (!(types & (1UL << type))) {
7358                 nested_vmx_failValid(vcpu,
7359                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7360                 return 1;
7361         }
7362
7363         /* according to the intel vmx instruction reference, the memory
7364          * operand is read even if it isn't needed (e.g., for type==global)
7365          */
7366         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7367                         vmx_instruction_info, false, &gva))
7368                 return 1;
7369         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7370                                 sizeof(u32), &e)) {
7371                 kvm_inject_page_fault(vcpu, &e);
7372                 return 1;
7373         }
7374
7375         switch (type) {
7376         case VMX_VPID_EXTENT_ALL_CONTEXT:
7377                 if (get_vmcs12(vcpu)->virtual_processor_id == 0) {
7378                         nested_vmx_failValid(vcpu,
7379                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7380                         return 1;
7381                 }
7382                 vmx_flush_tlb(vcpu);
7383                 nested_vmx_succeed(vcpu);
7384                 break;
7385         default:
7386                 /* Trap single context invalidation invvpid calls */
7387                 BUG_ON(1);
7388                 break;
7389         }
7390
7391         skip_emulated_instruction(vcpu);
7392         return 1;
7393 }
7394
7395 static int handle_pml_full(struct kvm_vcpu *vcpu)
7396 {
7397         unsigned long exit_qualification;
7398
7399         trace_kvm_pml_full(vcpu->vcpu_id);
7400
7401         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7402
7403         /*
7404          * PML buffer FULL happened while executing iret from NMI,
7405          * "blocked by NMI" bit has to be set before next VM entry.
7406          */
7407         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7408                         cpu_has_virtual_nmis() &&
7409                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7410                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7411                                 GUEST_INTR_STATE_NMI);
7412
7413         /*
7414          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7415          * here.., and there's no userspace involvement needed for PML.
7416          */
7417         return 1;
7418 }
7419
7420 static int handle_pcommit(struct kvm_vcpu *vcpu)
7421 {
7422         /* we never catch pcommit instruct for L1 guest. */
7423         WARN_ON(1);
7424         return 1;
7425 }
7426
7427 /*
7428  * The exit handlers return 1 if the exit was handled fully and guest execution
7429  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7430  * to be done to userspace and return 0.
7431  */
7432 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7433         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7434         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7435         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7436         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7437         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7438         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7439         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7440         [EXIT_REASON_CPUID]                   = handle_cpuid,
7441         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7442         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7443         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7444         [EXIT_REASON_HLT]                     = handle_halt,
7445         [EXIT_REASON_INVD]                    = handle_invd,
7446         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7447         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7448         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7449         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7450         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7451         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7452         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7453         [EXIT_REASON_VMREAD]                  = handle_vmread,
7454         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7455         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7456         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7457         [EXIT_REASON_VMON]                    = handle_vmon,
7458         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7459         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7460         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7461         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7462         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7463         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7464         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7465         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7466         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7467         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7468         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7469         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7470         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7471         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7472         [EXIT_REASON_INVEPT]                  = handle_invept,
7473         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7474         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7475         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7476         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7477         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7478 };
7479
7480 static const int kvm_vmx_max_exit_handlers =
7481         ARRAY_SIZE(kvm_vmx_exit_handlers);
7482
7483 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7484                                        struct vmcs12 *vmcs12)
7485 {
7486         unsigned long exit_qualification;
7487         gpa_t bitmap, last_bitmap;
7488         unsigned int port;
7489         int size;
7490         u8 b;
7491
7492         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7493                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7494
7495         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7496
7497         port = exit_qualification >> 16;
7498         size = (exit_qualification & 7) + 1;
7499
7500         last_bitmap = (gpa_t)-1;
7501         b = -1;
7502
7503         while (size > 0) {
7504                 if (port < 0x8000)
7505                         bitmap = vmcs12->io_bitmap_a;
7506                 else if (port < 0x10000)
7507                         bitmap = vmcs12->io_bitmap_b;
7508                 else
7509                         return true;
7510                 bitmap += (port & 0x7fff) / 8;
7511
7512                 if (last_bitmap != bitmap)
7513                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7514                                 return true;
7515                 if (b & (1 << (port & 7)))
7516                         return true;
7517
7518                 port++;
7519                 size--;
7520                 last_bitmap = bitmap;
7521         }
7522
7523         return false;
7524 }
7525
7526 /*
7527  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7528  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7529  * disinterest in the current event (read or write a specific MSR) by using an
7530  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7531  */
7532 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7533         struct vmcs12 *vmcs12, u32 exit_reason)
7534 {
7535         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7536         gpa_t bitmap;
7537
7538         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7539                 return true;
7540
7541         /*
7542          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7543          * for the four combinations of read/write and low/high MSR numbers.
7544          * First we need to figure out which of the four to use:
7545          */
7546         bitmap = vmcs12->msr_bitmap;
7547         if (exit_reason == EXIT_REASON_MSR_WRITE)
7548                 bitmap += 2048;
7549         if (msr_index >= 0xc0000000) {
7550                 msr_index -= 0xc0000000;
7551                 bitmap += 1024;
7552         }
7553
7554         /* Then read the msr_index'th bit from this bitmap: */
7555         if (msr_index < 1024*8) {
7556                 unsigned char b;
7557                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7558                         return true;
7559                 return 1 & (b >> (msr_index & 7));
7560         } else
7561                 return true; /* let L1 handle the wrong parameter */
7562 }
7563
7564 /*
7565  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7566  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7567  * intercept (via guest_host_mask etc.) the current event.
7568  */
7569 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7570         struct vmcs12 *vmcs12)
7571 {
7572         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7573         int cr = exit_qualification & 15;
7574         int reg = (exit_qualification >> 8) & 15;
7575         unsigned long val = kvm_register_readl(vcpu, reg);
7576
7577         switch ((exit_qualification >> 4) & 3) {
7578         case 0: /* mov to cr */
7579                 switch (cr) {
7580                 case 0:
7581                         if (vmcs12->cr0_guest_host_mask &
7582                             (val ^ vmcs12->cr0_read_shadow))
7583                                 return true;
7584                         break;
7585                 case 3:
7586                         if ((vmcs12->cr3_target_count >= 1 &&
7587                                         vmcs12->cr3_target_value0 == val) ||
7588                                 (vmcs12->cr3_target_count >= 2 &&
7589                                         vmcs12->cr3_target_value1 == val) ||
7590                                 (vmcs12->cr3_target_count >= 3 &&
7591                                         vmcs12->cr3_target_value2 == val) ||
7592                                 (vmcs12->cr3_target_count >= 4 &&
7593                                         vmcs12->cr3_target_value3 == val))
7594                                 return false;
7595                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7596                                 return true;
7597                         break;
7598                 case 4:
7599                         if (vmcs12->cr4_guest_host_mask &
7600                             (vmcs12->cr4_read_shadow ^ val))
7601                                 return true;
7602                         break;
7603                 case 8:
7604                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7605                                 return true;
7606                         break;
7607                 }
7608                 break;
7609         case 2: /* clts */
7610                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7611                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7612                         return true;
7613                 break;
7614         case 1: /* mov from cr */
7615                 switch (cr) {
7616                 case 3:
7617                         if (vmcs12->cpu_based_vm_exec_control &
7618                             CPU_BASED_CR3_STORE_EXITING)
7619                                 return true;
7620                         break;
7621                 case 8:
7622                         if (vmcs12->cpu_based_vm_exec_control &
7623                             CPU_BASED_CR8_STORE_EXITING)
7624                                 return true;
7625                         break;
7626                 }
7627                 break;
7628         case 3: /* lmsw */
7629                 /*
7630                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7631                  * cr0. Other attempted changes are ignored, with no exit.
7632                  */
7633                 if (vmcs12->cr0_guest_host_mask & 0xe &
7634                     (val ^ vmcs12->cr0_read_shadow))
7635                         return true;
7636                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7637                     !(vmcs12->cr0_read_shadow & 0x1) &&
7638                     (val & 0x1))
7639                         return true;
7640                 break;
7641         }
7642         return false;
7643 }
7644
7645 /*
7646  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7647  * should handle it ourselves in L0 (and then continue L2). Only call this
7648  * when in is_guest_mode (L2).
7649  */
7650 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7651 {
7652         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7653         struct vcpu_vmx *vmx = to_vmx(vcpu);
7654         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7655         u32 exit_reason = vmx->exit_reason;
7656
7657         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7658                                 vmcs_readl(EXIT_QUALIFICATION),
7659                                 vmx->idt_vectoring_info,
7660                                 intr_info,
7661                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7662                                 KVM_ISA_VMX);
7663
7664         if (vmx->nested.nested_run_pending)
7665                 return false;
7666
7667         if (unlikely(vmx->fail)) {
7668                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7669                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7670                 return true;
7671         }
7672
7673         switch (exit_reason) {
7674         case EXIT_REASON_EXCEPTION_NMI:
7675                 if (!is_exception(intr_info))
7676                         return false;
7677                 else if (is_page_fault(intr_info))
7678                         return enable_ept;
7679                 else if (is_no_device(intr_info) &&
7680                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7681                         return false;
7682                 return vmcs12->exception_bitmap &
7683                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7684         case EXIT_REASON_EXTERNAL_INTERRUPT:
7685                 return false;
7686         case EXIT_REASON_TRIPLE_FAULT:
7687                 return true;
7688         case EXIT_REASON_PENDING_INTERRUPT:
7689                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7690         case EXIT_REASON_NMI_WINDOW:
7691                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7692         case EXIT_REASON_TASK_SWITCH:
7693                 return true;
7694         case EXIT_REASON_CPUID:
7695                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7696                         return false;
7697                 return true;
7698         case EXIT_REASON_HLT:
7699                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7700         case EXIT_REASON_INVD:
7701                 return true;
7702         case EXIT_REASON_INVLPG:
7703                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7704         case EXIT_REASON_RDPMC:
7705                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7706         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7707                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7708         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7709         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7710         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7711         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7712         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7713         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7714                 /*
7715                  * VMX instructions trap unconditionally. This allows L1 to
7716                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7717                  */
7718                 return true;
7719         case EXIT_REASON_CR_ACCESS:
7720                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7721         case EXIT_REASON_DR_ACCESS:
7722                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7723         case EXIT_REASON_IO_INSTRUCTION:
7724                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7725         case EXIT_REASON_MSR_READ:
7726         case EXIT_REASON_MSR_WRITE:
7727                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7728         case EXIT_REASON_INVALID_STATE:
7729                 return true;
7730         case EXIT_REASON_MWAIT_INSTRUCTION:
7731                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7732         case EXIT_REASON_MONITOR_TRAP_FLAG:
7733                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7734         case EXIT_REASON_MONITOR_INSTRUCTION:
7735                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7736         case EXIT_REASON_PAUSE_INSTRUCTION:
7737                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7738                         nested_cpu_has2(vmcs12,
7739                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7740         case EXIT_REASON_MCE_DURING_VMENTRY:
7741                 return false;
7742         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7743                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7744         case EXIT_REASON_APIC_ACCESS:
7745                 return nested_cpu_has2(vmcs12,
7746                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7747         case EXIT_REASON_APIC_WRITE:
7748         case EXIT_REASON_EOI_INDUCED:
7749                 /* apic_write and eoi_induced should exit unconditionally. */
7750                 return true;
7751         case EXIT_REASON_EPT_VIOLATION:
7752                 /*
7753                  * L0 always deals with the EPT violation. If nested EPT is
7754                  * used, and the nested mmu code discovers that the address is
7755                  * missing in the guest EPT table (EPT12), the EPT violation
7756                  * will be injected with nested_ept_inject_page_fault()
7757                  */
7758                 return false;
7759         case EXIT_REASON_EPT_MISCONFIG:
7760                 /*
7761                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7762                  * table (shadow on EPT) or a merged EPT table that L0 built
7763                  * (EPT on EPT). So any problems with the structure of the
7764                  * table is L0's fault.
7765                  */
7766                 return false;
7767         case EXIT_REASON_WBINVD:
7768                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7769         case EXIT_REASON_XSETBV:
7770                 return true;
7771         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7772                 /*
7773                  * This should never happen, since it is not possible to
7774                  * set XSS to a non-zero value---neither in L1 nor in L2.
7775                  * If if it were, XSS would have to be checked against
7776                  * the XSS exit bitmap in vmcs12.
7777                  */
7778                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7779         case EXIT_REASON_PCOMMIT:
7780                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7781         default:
7782                 return true;
7783         }
7784 }
7785
7786 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7787 {
7788         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7789         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7790 }
7791
7792 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7793 {
7794         struct page *pml_pg;
7795
7796         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7797         if (!pml_pg)
7798                 return -ENOMEM;
7799
7800         vmx->pml_pg = pml_pg;
7801
7802         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7803         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7804
7805         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
7806
7807         return 0;
7808 }
7809
7810 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7811 {
7812         ASSERT(vmx->pml_pg);
7813         __free_page(vmx->pml_pg);
7814         vmx->pml_pg = NULL;
7815
7816         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_ENABLE_PML);
7817 }
7818
7819 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7820 {
7821         struct vcpu_vmx *vmx = to_vmx(vcpu);
7822         u64 *pml_buf;
7823         u16 pml_idx;
7824
7825         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7826
7827         /* Do nothing if PML buffer is empty */
7828         if (pml_idx == (PML_ENTITY_NUM - 1))
7829                 return;
7830
7831         /* PML index always points to next available PML buffer entity */
7832         if (pml_idx >= PML_ENTITY_NUM)
7833                 pml_idx = 0;
7834         else
7835                 pml_idx++;
7836
7837         pml_buf = page_address(vmx->pml_pg);
7838         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7839                 u64 gpa;
7840
7841                 gpa = pml_buf[pml_idx];
7842                 WARN_ON(gpa & (PAGE_SIZE - 1));
7843                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7844         }
7845
7846         /* reset PML index */
7847         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7848 }
7849
7850 /*
7851  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7852  * Called before reporting dirty_bitmap to userspace.
7853  */
7854 static void kvm_flush_pml_buffers(struct kvm *kvm)
7855 {
7856         int i;
7857         struct kvm_vcpu *vcpu;
7858         /*
7859          * We only need to kick vcpu out of guest mode here, as PML buffer
7860          * is flushed at beginning of all VMEXITs, and it's obvious that only
7861          * vcpus running in guest are possible to have unflushed GPAs in PML
7862          * buffer.
7863          */
7864         kvm_for_each_vcpu(i, vcpu, kvm)
7865                 kvm_vcpu_kick(vcpu);
7866 }
7867
7868 static void vmx_dump_sel(char *name, uint32_t sel)
7869 {
7870         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7871                name, vmcs_read32(sel),
7872                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7873                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7874                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7875 }
7876
7877 static void vmx_dump_dtsel(char *name, uint32_t limit)
7878 {
7879         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7880                name, vmcs_read32(limit),
7881                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7882 }
7883
7884 static void dump_vmcs(void)
7885 {
7886         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7887         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7888         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7889         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7890         u32 secondary_exec_control = 0;
7891         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7892         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7893         int i, n;
7894
7895         if (cpu_has_secondary_exec_ctrls())
7896                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7897
7898         pr_err("*** Guest State ***\n");
7899         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7900                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7901                vmcs_readl(CR0_GUEST_HOST_MASK));
7902         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7903                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7904         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7905         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7906             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7907         {
7908                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7909                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7910                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7911                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7912         }
7913         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7914                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7915         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7916                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7917         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7918                vmcs_readl(GUEST_SYSENTER_ESP),
7919                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7920         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7921         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7922         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7923         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7924         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7925         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7926         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7927         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7928         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7929         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7930         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7931             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7932                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7933                        efer, vmcs_readl(GUEST_IA32_PAT));
7934         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7935                vmcs_readl(GUEST_IA32_DEBUGCTL),
7936                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7937         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7938                 pr_err("PerfGlobCtl = 0x%016lx\n",
7939                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7940         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7941                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7942         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7943                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7944                vmcs_read32(GUEST_ACTIVITY_STATE));
7945         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7946                 pr_err("InterruptStatus = %04x\n",
7947                        vmcs_read16(GUEST_INTR_STATUS));
7948
7949         pr_err("*** Host State ***\n");
7950         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7951                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7952         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7953                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7954                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7955                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7956                vmcs_read16(HOST_TR_SELECTOR));
7957         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7958                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7959                vmcs_readl(HOST_TR_BASE));
7960         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7961                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7962         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7963                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7964                vmcs_readl(HOST_CR4));
7965         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7966                vmcs_readl(HOST_IA32_SYSENTER_ESP),
7967                vmcs_read32(HOST_IA32_SYSENTER_CS),
7968                vmcs_readl(HOST_IA32_SYSENTER_EIP));
7969         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7970                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
7971                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7972         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7973                 pr_err("PerfGlobCtl = 0x%016lx\n",
7974                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7975
7976         pr_err("*** Control State ***\n");
7977         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7978                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7979         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7980         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7981                vmcs_read32(EXCEPTION_BITMAP),
7982                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7983                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7984         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7985                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7986                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7987                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7988         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7989                vmcs_read32(VM_EXIT_INTR_INFO),
7990                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7991                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7992         pr_err("        reason=%08x qualification=%016lx\n",
7993                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7994         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7995                vmcs_read32(IDT_VECTORING_INFO_FIELD),
7996                vmcs_read32(IDT_VECTORING_ERROR_CODE));
7997         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7998         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7999                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8000         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8001                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8002         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8003                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8004         n = vmcs_read32(CR3_TARGET_COUNT);
8005         for (i = 0; i + 1 < n; i += 4)
8006                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8007                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8008                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8009         if (i < n)
8010                 pr_err("CR3 target%u=%016lx\n",
8011                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8012         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8013                 pr_err("PLE Gap=%08x Window=%08x\n",
8014                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8015         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8016                 pr_err("Virtual processor ID = 0x%04x\n",
8017                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8018 }
8019
8020 /*
8021  * The guest has exited.  See if we can fix it or if we need userspace
8022  * assistance.
8023  */
8024 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8025 {
8026         struct vcpu_vmx *vmx = to_vmx(vcpu);
8027         u32 exit_reason = vmx->exit_reason;
8028         u32 vectoring_info = vmx->idt_vectoring_info;
8029
8030         /*
8031          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8032          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8033          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8034          * mode as if vcpus is in root mode, the PML buffer must has been
8035          * flushed already.
8036          */
8037         if (enable_pml)
8038                 vmx_flush_pml_buffer(vcpu);
8039
8040         /* If guest state is invalid, start emulating */
8041         if (vmx->emulation_required)
8042                 return handle_invalid_guest_state(vcpu);
8043
8044         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8045                 nested_vmx_vmexit(vcpu, exit_reason,
8046                                   vmcs_read32(VM_EXIT_INTR_INFO),
8047                                   vmcs_readl(EXIT_QUALIFICATION));
8048                 return 1;
8049         }
8050
8051         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8052                 dump_vmcs();
8053                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8054                 vcpu->run->fail_entry.hardware_entry_failure_reason
8055                         = exit_reason;
8056                 return 0;
8057         }
8058
8059         if (unlikely(vmx->fail)) {
8060                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8061                 vcpu->run->fail_entry.hardware_entry_failure_reason
8062                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8063                 return 0;
8064         }
8065
8066         /*
8067          * Note:
8068          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8069          * delivery event since it indicates guest is accessing MMIO.
8070          * The vm-exit can be triggered again after return to guest that
8071          * will cause infinite loop.
8072          */
8073         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8074                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8075                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8076                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8077                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8078                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8079                 vcpu->run->internal.ndata = 2;
8080                 vcpu->run->internal.data[0] = vectoring_info;
8081                 vcpu->run->internal.data[1] = exit_reason;
8082                 return 0;
8083         }
8084
8085         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8086             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8087                                         get_vmcs12(vcpu))))) {
8088                 if (vmx_interrupt_allowed(vcpu)) {
8089                         vmx->soft_vnmi_blocked = 0;
8090                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8091                            vcpu->arch.nmi_pending) {
8092                         /*
8093                          * This CPU don't support us in finding the end of an
8094                          * NMI-blocked window if the guest runs with IRQs
8095                          * disabled. So we pull the trigger after 1 s of
8096                          * futile waiting, but inform the user about this.
8097                          */
8098                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8099                                "state on VCPU %d after 1 s timeout\n",
8100                                __func__, vcpu->vcpu_id);
8101                         vmx->soft_vnmi_blocked = 0;
8102                 }
8103         }
8104
8105         if (exit_reason < kvm_vmx_max_exit_handlers
8106             && kvm_vmx_exit_handlers[exit_reason])
8107                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8108         else {
8109                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8110                 kvm_queue_exception(vcpu, UD_VECTOR);
8111                 return 1;
8112         }
8113 }
8114
8115 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8116 {
8117         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8118
8119         if (is_guest_mode(vcpu) &&
8120                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8121                 return;
8122
8123         if (irr == -1 || tpr < irr) {
8124                 vmcs_write32(TPR_THRESHOLD, 0);
8125                 return;
8126         }
8127
8128         vmcs_write32(TPR_THRESHOLD, irr);
8129 }
8130
8131 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8132 {
8133         u32 sec_exec_control;
8134
8135         /*
8136          * There is not point to enable virtualize x2apic without enable
8137          * apicv
8138          */
8139         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8140                                 !vmx_cpu_uses_apicv(vcpu))
8141                 return;
8142
8143         if (!cpu_need_tpr_shadow(vcpu))
8144                 return;
8145
8146         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8147
8148         if (set) {
8149                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8150                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8151         } else {
8152                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8153                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8154         }
8155         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8156
8157         vmx_set_msr_bitmap(vcpu);
8158 }
8159
8160 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8161 {
8162         struct vcpu_vmx *vmx = to_vmx(vcpu);
8163
8164         /*
8165          * Currently we do not handle the nested case where L2 has an
8166          * APIC access page of its own; that page is still pinned.
8167          * Hence, we skip the case where the VCPU is in guest mode _and_
8168          * L1 prepared an APIC access page for L2.
8169          *
8170          * For the case where L1 and L2 share the same APIC access page
8171          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8172          * in the vmcs12), this function will only update either the vmcs01
8173          * or the vmcs02.  If the former, the vmcs02 will be updated by
8174          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8175          * the next L2->L1 exit.
8176          */
8177         if (!is_guest_mode(vcpu) ||
8178             !nested_cpu_has2(vmx->nested.current_vmcs12,
8179                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8180                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8181 }
8182
8183 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8184 {
8185         u16 status;
8186         u8 old;
8187
8188         if (isr == -1)
8189                 isr = 0;
8190
8191         status = vmcs_read16(GUEST_INTR_STATUS);
8192         old = status >> 8;
8193         if (isr != old) {
8194                 status &= 0xff;
8195                 status |= isr << 8;
8196                 vmcs_write16(GUEST_INTR_STATUS, status);
8197         }
8198 }
8199
8200 static void vmx_set_rvi(int vector)
8201 {
8202         u16 status;
8203         u8 old;
8204
8205         if (vector == -1)
8206                 vector = 0;
8207
8208         status = vmcs_read16(GUEST_INTR_STATUS);
8209         old = (u8)status & 0xff;
8210         if ((u8)vector != old) {
8211                 status &= ~0xff;
8212                 status |= (u8)vector;
8213                 vmcs_write16(GUEST_INTR_STATUS, status);
8214         }
8215 }
8216
8217 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8218 {
8219         if (!is_guest_mode(vcpu)) {
8220                 vmx_set_rvi(max_irr);
8221                 return;
8222         }
8223
8224         if (max_irr == -1)
8225                 return;
8226
8227         /*
8228          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8229          * handles it.
8230          */
8231         if (nested_exit_on_intr(vcpu))
8232                 return;
8233
8234         /*
8235          * Else, fall back to pre-APICv interrupt injection since L2
8236          * is run without virtual interrupt delivery.
8237          */
8238         if (!kvm_event_needs_reinjection(vcpu) &&
8239             vmx_interrupt_allowed(vcpu)) {
8240                 kvm_queue_interrupt(vcpu, max_irr, false);
8241                 vmx_inject_irq(vcpu);
8242         }
8243 }
8244
8245 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8246 {
8247         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8248         if (!vmx_cpu_uses_apicv(vcpu))
8249                 return;
8250
8251         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8252         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8253         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8254         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8255 }
8256
8257 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8258 {
8259         u32 exit_intr_info;
8260
8261         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8262               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8263                 return;
8264
8265         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8266         exit_intr_info = vmx->exit_intr_info;
8267
8268         /* Handle machine checks before interrupts are enabled */
8269         if (is_machine_check(exit_intr_info))
8270                 kvm_machine_check();
8271
8272         /* We need to handle NMIs before interrupts are enabled */
8273         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8274             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8275                 kvm_before_handle_nmi(&vmx->vcpu);
8276                 asm("int $2");
8277                 kvm_after_handle_nmi(&vmx->vcpu);
8278         }
8279 }
8280
8281 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8282 {
8283         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8284
8285         /*
8286          * If external interrupt exists, IF bit is set in rflags/eflags on the
8287          * interrupt stack frame, and interrupt will be enabled on a return
8288          * from interrupt handler.
8289          */
8290         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8291                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8292                 unsigned int vector;
8293                 unsigned long entry;
8294                 gate_desc *desc;
8295                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8296 #ifdef CONFIG_X86_64
8297                 unsigned long tmp;
8298 #endif
8299
8300                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8301                 desc = (gate_desc *)vmx->host_idt_base + vector;
8302                 entry = gate_offset(*desc);
8303                 asm volatile(
8304 #ifdef CONFIG_X86_64
8305                         "mov %%" _ASM_SP ", %[sp]\n\t"
8306                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8307                         "push $%c[ss]\n\t"
8308                         "push %[sp]\n\t"
8309 #endif
8310                         "pushf\n\t"
8311                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8312                         __ASM_SIZE(push) " $%c[cs]\n\t"
8313                         "call *%[entry]\n\t"
8314                         :
8315 #ifdef CONFIG_X86_64
8316                         [sp]"=&r"(tmp)
8317 #endif
8318                         :
8319                         [entry]"r"(entry),
8320                         [ss]"i"(__KERNEL_DS),
8321                         [cs]"i"(__KERNEL_CS)
8322                         );
8323         } else
8324                 local_irq_enable();
8325 }
8326
8327 static bool vmx_has_high_real_mode_segbase(void)
8328 {
8329         return enable_unrestricted_guest || emulate_invalid_guest_state;
8330 }
8331
8332 static bool vmx_mpx_supported(void)
8333 {
8334         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8335                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8336 }
8337
8338 static bool vmx_xsaves_supported(void)
8339 {
8340         return vmcs_config.cpu_based_2nd_exec_ctrl &
8341                 SECONDARY_EXEC_XSAVES;
8342 }
8343
8344 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8345 {
8346         u32 exit_intr_info;
8347         bool unblock_nmi;
8348         u8 vector;
8349         bool idtv_info_valid;
8350
8351         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8352
8353         if (cpu_has_virtual_nmis()) {
8354                 if (vmx->nmi_known_unmasked)
8355                         return;
8356                 /*
8357                  * Can't use vmx->exit_intr_info since we're not sure what
8358                  * the exit reason is.
8359                  */
8360                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8361                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8362                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8363                 /*
8364                  * SDM 3: 27.7.1.2 (September 2008)
8365                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8366                  * a guest IRET fault.
8367                  * SDM 3: 23.2.2 (September 2008)
8368                  * Bit 12 is undefined in any of the following cases:
8369                  *  If the VM exit sets the valid bit in the IDT-vectoring
8370                  *   information field.
8371                  *  If the VM exit is due to a double fault.
8372                  */
8373                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8374                     vector != DF_VECTOR && !idtv_info_valid)
8375                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8376                                       GUEST_INTR_STATE_NMI);
8377                 else
8378                         vmx->nmi_known_unmasked =
8379                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8380                                   & GUEST_INTR_STATE_NMI);
8381         } else if (unlikely(vmx->soft_vnmi_blocked))
8382                 vmx->vnmi_blocked_time +=
8383                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8384 }
8385
8386 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8387                                       u32 idt_vectoring_info,
8388                                       int instr_len_field,
8389                                       int error_code_field)
8390 {
8391         u8 vector;
8392         int type;
8393         bool idtv_info_valid;
8394
8395         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8396
8397         vcpu->arch.nmi_injected = false;
8398         kvm_clear_exception_queue(vcpu);
8399         kvm_clear_interrupt_queue(vcpu);
8400
8401         if (!idtv_info_valid)
8402                 return;
8403
8404         kvm_make_request(KVM_REQ_EVENT, vcpu);
8405
8406         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8407         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8408
8409         switch (type) {
8410         case INTR_TYPE_NMI_INTR:
8411                 vcpu->arch.nmi_injected = true;
8412                 /*
8413                  * SDM 3: 27.7.1.2 (September 2008)
8414                  * Clear bit "block by NMI" before VM entry if a NMI
8415                  * delivery faulted.
8416                  */
8417                 vmx_set_nmi_mask(vcpu, false);
8418                 break;
8419         case INTR_TYPE_SOFT_EXCEPTION:
8420                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8421                 /* fall through */
8422         case INTR_TYPE_HARD_EXCEPTION:
8423                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8424                         u32 err = vmcs_read32(error_code_field);
8425                         kvm_requeue_exception_e(vcpu, vector, err);
8426                 } else
8427                         kvm_requeue_exception(vcpu, vector);
8428                 break;
8429         case INTR_TYPE_SOFT_INTR:
8430                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8431                 /* fall through */
8432         case INTR_TYPE_EXT_INTR:
8433                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8434                 break;
8435         default:
8436                 break;
8437         }
8438 }
8439
8440 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8441 {
8442         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8443                                   VM_EXIT_INSTRUCTION_LEN,
8444                                   IDT_VECTORING_ERROR_CODE);
8445 }
8446
8447 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8448 {
8449         __vmx_complete_interrupts(vcpu,
8450                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8451                                   VM_ENTRY_INSTRUCTION_LEN,
8452                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8453
8454         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8455 }
8456
8457 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8458 {
8459         int i, nr_msrs;
8460         struct perf_guest_switch_msr *msrs;
8461
8462         msrs = perf_guest_get_msrs(&nr_msrs);
8463
8464         if (!msrs)
8465                 return;
8466
8467         for (i = 0; i < nr_msrs; i++)
8468                 if (msrs[i].host == msrs[i].guest)
8469                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8470                 else
8471                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8472                                         msrs[i].host);
8473 }
8474
8475 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8476 {
8477         struct vcpu_vmx *vmx = to_vmx(vcpu);
8478         unsigned long debugctlmsr, cr4;
8479
8480         /* Record the guest's net vcpu time for enforced NMI injections. */
8481         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8482                 vmx->entry_time = ktime_get();
8483
8484         /* Don't enter VMX if guest state is invalid, let the exit handler
8485            start emulation until we arrive back to a valid state */
8486         if (vmx->emulation_required)
8487                 return;
8488
8489         if (vmx->ple_window_dirty) {
8490                 vmx->ple_window_dirty = false;
8491                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8492         }
8493
8494         if (vmx->nested.sync_shadow_vmcs) {
8495                 copy_vmcs12_to_shadow(vmx);
8496                 vmx->nested.sync_shadow_vmcs = false;
8497         }
8498
8499         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8500                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8501         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8502                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8503
8504         cr4 = cr4_read_shadow();
8505         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8506                 vmcs_writel(HOST_CR4, cr4);
8507                 vmx->host_state.vmcs_host_cr4 = cr4;
8508         }
8509
8510         /* When single-stepping over STI and MOV SS, we must clear the
8511          * corresponding interruptibility bits in the guest state. Otherwise
8512          * vmentry fails as it then expects bit 14 (BS) in pending debug
8513          * exceptions being set, but that's not correct for the guest debugging
8514          * case. */
8515         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8516                 vmx_set_interrupt_shadow(vcpu, 0);
8517
8518         atomic_switch_perf_msrs(vmx);
8519         debugctlmsr = get_debugctlmsr();
8520
8521         vmx->__launched = vmx->loaded_vmcs->launched;
8522         asm(
8523                 /* Store host registers */
8524                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8525                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8526                 "push %%" _ASM_CX " \n\t"
8527                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8528                 "je 1f \n\t"
8529                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8530                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8531                 "1: \n\t"
8532                 /* Reload cr2 if changed */
8533                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8534                 "mov %%cr2, %%" _ASM_DX " \n\t"
8535                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8536                 "je 2f \n\t"
8537                 "mov %%" _ASM_AX", %%cr2 \n\t"
8538                 "2: \n\t"
8539                 /* Check if vmlaunch of vmresume is needed */
8540                 "cmpl $0, %c[launched](%0) \n\t"
8541                 /* Load guest registers.  Don't clobber flags. */
8542                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8543                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8544                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8545                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8546                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8547                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8548 #ifdef CONFIG_X86_64
8549                 "mov %c[r8](%0),  %%r8  \n\t"
8550                 "mov %c[r9](%0),  %%r9  \n\t"
8551                 "mov %c[r10](%0), %%r10 \n\t"
8552                 "mov %c[r11](%0), %%r11 \n\t"
8553                 "mov %c[r12](%0), %%r12 \n\t"
8554                 "mov %c[r13](%0), %%r13 \n\t"
8555                 "mov %c[r14](%0), %%r14 \n\t"
8556                 "mov %c[r15](%0), %%r15 \n\t"
8557 #endif
8558                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8559
8560                 /* Enter guest mode */
8561                 "jne 1f \n\t"
8562                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8563                 "jmp 2f \n\t"
8564                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8565                 "2: "
8566                 /* Save guest registers, load host registers, keep flags */
8567                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8568                 "pop %0 \n\t"
8569                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8570                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8571                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8572                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8573                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8574                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8575                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8576 #ifdef CONFIG_X86_64
8577                 "mov %%r8,  %c[r8](%0) \n\t"
8578                 "mov %%r9,  %c[r9](%0) \n\t"
8579                 "mov %%r10, %c[r10](%0) \n\t"
8580                 "mov %%r11, %c[r11](%0) \n\t"
8581                 "mov %%r12, %c[r12](%0) \n\t"
8582                 "mov %%r13, %c[r13](%0) \n\t"
8583                 "mov %%r14, %c[r14](%0) \n\t"
8584                 "mov %%r15, %c[r15](%0) \n\t"
8585 #endif
8586                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8587                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8588
8589                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8590                 "setbe %c[fail](%0) \n\t"
8591                 ".pushsection .rodata \n\t"
8592                 ".global vmx_return \n\t"
8593                 "vmx_return: " _ASM_PTR " 2b \n\t"
8594                 ".popsection"
8595               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8596                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8597                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8598                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8599                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8600                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8601                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8602                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8603                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8604                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8605                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8606 #ifdef CONFIG_X86_64
8607                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8608                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8609                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8610                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8611                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8612                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8613                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8614                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8615 #endif
8616                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8617                 [wordsize]"i"(sizeof(ulong))
8618               : "cc", "memory"
8619 #ifdef CONFIG_X86_64
8620                 , "rax", "rbx", "rdi", "rsi"
8621                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8622 #else
8623                 , "eax", "ebx", "edi", "esi"
8624 #endif
8625               );
8626
8627         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8628         if (debugctlmsr)
8629                 update_debugctlmsr(debugctlmsr);
8630
8631 #ifndef CONFIG_X86_64
8632         /*
8633          * The sysexit path does not restore ds/es, so we must set them to
8634          * a reasonable value ourselves.
8635          *
8636          * We can't defer this to vmx_load_host_state() since that function
8637          * may be executed in interrupt context, which saves and restore segments
8638          * around it, nullifying its effect.
8639          */
8640         loadsegment(ds, __USER_DS);
8641         loadsegment(es, __USER_DS);
8642 #endif
8643
8644         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8645                                   | (1 << VCPU_EXREG_RFLAGS)
8646                                   | (1 << VCPU_EXREG_PDPTR)
8647                                   | (1 << VCPU_EXREG_SEGMENTS)
8648                                   | (1 << VCPU_EXREG_CR3));
8649         vcpu->arch.regs_dirty = 0;
8650
8651         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8652
8653         vmx->loaded_vmcs->launched = 1;
8654
8655         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8656         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8657
8658         /*
8659          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8660          * we did not inject a still-pending event to L1 now because of
8661          * nested_run_pending, we need to re-enable this bit.
8662          */
8663         if (vmx->nested.nested_run_pending)
8664                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8665
8666         vmx->nested.nested_run_pending = 0;
8667
8668         vmx_complete_atomic_exit(vmx);
8669         vmx_recover_nmi_blocking(vmx);
8670         vmx_complete_interrupts(vmx);
8671 }
8672
8673 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8674 {
8675         struct vcpu_vmx *vmx = to_vmx(vcpu);
8676         int cpu;
8677
8678         if (vmx->loaded_vmcs == &vmx->vmcs01)
8679                 return;
8680
8681         cpu = get_cpu();
8682         vmx->loaded_vmcs = &vmx->vmcs01;
8683         vmx_vcpu_put(vcpu);
8684         vmx_vcpu_load(vcpu, cpu);
8685         vcpu->cpu = cpu;
8686         put_cpu();
8687 }
8688
8689 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8690 {
8691         struct vcpu_vmx *vmx = to_vmx(vcpu);
8692
8693         if (enable_pml)
8694                 vmx_disable_pml(vmx);
8695         free_vpid(vmx->vpid);
8696         leave_guest_mode(vcpu);
8697         vmx_load_vmcs01(vcpu);
8698         free_nested(vmx);
8699         free_loaded_vmcs(vmx->loaded_vmcs);
8700         kfree(vmx->guest_msrs);
8701         kvm_vcpu_uninit(vcpu);
8702         kmem_cache_free(kvm_vcpu_cache, vmx);
8703 }
8704
8705 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8706 {
8707         int err;
8708         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8709         int cpu;
8710
8711         if (!vmx)
8712                 return ERR_PTR(-ENOMEM);
8713
8714         vmx->vpid = allocate_vpid();
8715
8716         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8717         if (err)
8718                 goto free_vcpu;
8719
8720         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8721         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8722                      > PAGE_SIZE);
8723
8724         err = -ENOMEM;
8725         if (!vmx->guest_msrs) {
8726                 goto uninit_vcpu;
8727         }
8728
8729         vmx->loaded_vmcs = &vmx->vmcs01;
8730         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8731         if (!vmx->loaded_vmcs->vmcs)
8732                 goto free_msrs;
8733         if (!vmm_exclusive)
8734                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8735         loaded_vmcs_init(vmx->loaded_vmcs);
8736         if (!vmm_exclusive)
8737                 kvm_cpu_vmxoff();
8738
8739         cpu = get_cpu();
8740         vmx_vcpu_load(&vmx->vcpu, cpu);
8741         vmx->vcpu.cpu = cpu;
8742         err = vmx_vcpu_setup(vmx);
8743         vmx_vcpu_put(&vmx->vcpu);
8744         put_cpu();
8745         if (err)
8746                 goto free_vmcs;
8747         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8748                 err = alloc_apic_access_page(kvm);
8749                 if (err)
8750                         goto free_vmcs;
8751         }
8752
8753         if (enable_ept) {
8754                 if (!kvm->arch.ept_identity_map_addr)
8755                         kvm->arch.ept_identity_map_addr =
8756                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8757                 err = init_rmode_identity_map(kvm);
8758                 if (err)
8759                         goto free_vmcs;
8760         }
8761
8762         if (nested)
8763                 nested_vmx_setup_ctls_msrs(vmx);
8764
8765         vmx->nested.posted_intr_nv = -1;
8766         vmx->nested.current_vmptr = -1ull;
8767         vmx->nested.current_vmcs12 = NULL;
8768
8769         /*
8770          * If PML is turned on, failure on enabling PML just results in failure
8771          * of creating the vcpu, therefore we can simplify PML logic (by
8772          * avoiding dealing with cases, such as enabling PML partially on vcpus
8773          * for the guest, etc.
8774          */
8775         if (enable_pml) {
8776                 err = vmx_enable_pml(vmx);
8777                 if (err)
8778                         goto free_vmcs;
8779         }
8780
8781         return &vmx->vcpu;
8782
8783 free_vmcs:
8784         free_loaded_vmcs(vmx->loaded_vmcs);
8785 free_msrs:
8786         kfree(vmx->guest_msrs);
8787 uninit_vcpu:
8788         kvm_vcpu_uninit(&vmx->vcpu);
8789 free_vcpu:
8790         free_vpid(vmx->vpid);
8791         kmem_cache_free(kvm_vcpu_cache, vmx);
8792         return ERR_PTR(err);
8793 }
8794
8795 static void __init vmx_check_processor_compat(void *rtn)
8796 {
8797         struct vmcs_config vmcs_conf;
8798
8799         *(int *)rtn = 0;
8800         if (setup_vmcs_config(&vmcs_conf) < 0)
8801                 *(int *)rtn = -EIO;
8802         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8803                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8804                                 smp_processor_id());
8805                 *(int *)rtn = -EIO;
8806         }
8807 }
8808
8809 static int get_ept_level(void)
8810 {
8811         return VMX_EPT_DEFAULT_GAW + 1;
8812 }
8813
8814 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8815 {
8816         u8 cache;
8817         u64 ipat = 0;
8818
8819         /* For VT-d and EPT combination
8820          * 1. MMIO: always map as UC
8821          * 2. EPT with VT-d:
8822          *   a. VT-d without snooping control feature: can't guarantee the
8823          *      result, try to trust guest.
8824          *   b. VT-d with snooping control feature: snooping control feature of
8825          *      VT-d engine can guarantee the cache correctness. Just set it
8826          *      to WB to keep consistent with host. So the same as item 3.
8827          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8828          *    consistent with host MTRR
8829          */
8830         if (is_mmio) {
8831                 cache = MTRR_TYPE_UNCACHABLE;
8832                 goto exit;
8833         }
8834
8835         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8836                 ipat = VMX_EPT_IPAT_BIT;
8837                 cache = MTRR_TYPE_WRBACK;
8838                 goto exit;
8839         }
8840
8841         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8842                 ipat = VMX_EPT_IPAT_BIT;
8843                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8844                         cache = MTRR_TYPE_WRBACK;
8845                 else
8846                         cache = MTRR_TYPE_UNCACHABLE;
8847                 goto exit;
8848         }
8849
8850         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8851
8852 exit:
8853         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8854 }
8855
8856 static int vmx_get_lpage_level(void)
8857 {
8858         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8859                 return PT_DIRECTORY_LEVEL;
8860         else
8861                 /* For shadow and EPT supported 1GB page */
8862                 return PT_PDPE_LEVEL;
8863 }
8864
8865 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8866 {
8867         /*
8868          * These bits in the secondary execution controls field
8869          * are dynamic, the others are mostly based on the hypervisor
8870          * architecture and the guest's CPUID.  Do not touch the
8871          * dynamic bits.
8872          */
8873         u32 mask =
8874                 SECONDARY_EXEC_SHADOW_VMCS |
8875                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8876                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8877
8878         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8879
8880         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8881                      (new_ctl & ~mask) | (cur_ctl & mask));
8882 }
8883
8884 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8885 {
8886         struct kvm_cpuid_entry2 *best;
8887         struct vcpu_vmx *vmx = to_vmx(vcpu);
8888         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8889
8890         if (vmx_rdtscp_supported()) {
8891                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8892                 if (!rdtscp_enabled)
8893                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8894
8895                 if (nested) {
8896                         if (rdtscp_enabled)
8897                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8898                                         SECONDARY_EXEC_RDTSCP;
8899                         else
8900                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8901                                         ~SECONDARY_EXEC_RDTSCP;
8902                 }
8903         }
8904
8905         /* Exposing INVPCID only when PCID is exposed */
8906         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8907         if (vmx_invpcid_supported() &&
8908             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8909             !guest_cpuid_has_pcid(vcpu))) {
8910                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8911
8912                 if (best)
8913                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8914         }
8915
8916         vmcs_set_secondary_exec_control(secondary_exec_ctl);
8917
8918         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8919                 if (guest_cpuid_has_pcommit(vcpu))
8920                         vmx->nested.nested_vmx_secondary_ctls_high |=
8921                                 SECONDARY_EXEC_PCOMMIT;
8922                 else
8923                         vmx->nested.nested_vmx_secondary_ctls_high &=
8924                                 ~SECONDARY_EXEC_PCOMMIT;
8925         }
8926 }
8927
8928 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8929 {
8930         if (func == 1 && nested)
8931                 entry->ecx |= bit(X86_FEATURE_VMX);
8932 }
8933
8934 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8935                 struct x86_exception *fault)
8936 {
8937         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8938         u32 exit_reason;
8939
8940         if (fault->error_code & PFERR_RSVD_MASK)
8941                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8942         else
8943                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8944         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8945         vmcs12->guest_physical_address = fault->address;
8946 }
8947
8948 /* Callbacks for nested_ept_init_mmu_context: */
8949
8950 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8951 {
8952         /* return the page table to be shadowed - in our case, EPT12 */
8953         return get_vmcs12(vcpu)->ept_pointer;
8954 }
8955
8956 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8957 {
8958         WARN_ON(mmu_is_nested(vcpu));
8959         kvm_init_shadow_ept_mmu(vcpu,
8960                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8961                         VMX_EPT_EXECUTE_ONLY_BIT);
8962         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8963         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8964         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8965
8966         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8967 }
8968
8969 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8970 {
8971         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8972 }
8973
8974 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8975                                             u16 error_code)
8976 {
8977         bool inequality, bit;
8978
8979         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8980         inequality =
8981                 (error_code & vmcs12->page_fault_error_code_mask) !=
8982                  vmcs12->page_fault_error_code_match;
8983         return inequality ^ bit;
8984 }
8985
8986 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8987                 struct x86_exception *fault)
8988 {
8989         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8990
8991         WARN_ON(!is_guest_mode(vcpu));
8992
8993         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8994                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8995                                   vmcs_read32(VM_EXIT_INTR_INFO),
8996                                   vmcs_readl(EXIT_QUALIFICATION));
8997         else
8998                 kvm_inject_page_fault(vcpu, fault);
8999 }
9000
9001 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9002                                         struct vmcs12 *vmcs12)
9003 {
9004         struct vcpu_vmx *vmx = to_vmx(vcpu);
9005         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9006
9007         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9008                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9009                     vmcs12->apic_access_addr >> maxphyaddr)
9010                         return false;
9011
9012                 /*
9013                  * Translate L1 physical address to host physical
9014                  * address for vmcs02. Keep the page pinned, so this
9015                  * physical address remains valid. We keep a reference
9016                  * to it so we can release it later.
9017                  */
9018                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9019                         nested_release_page(vmx->nested.apic_access_page);
9020                 vmx->nested.apic_access_page =
9021                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9022         }
9023
9024         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9025                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9026                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9027                         return false;
9028
9029                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9030                         nested_release_page(vmx->nested.virtual_apic_page);
9031                 vmx->nested.virtual_apic_page =
9032                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9033
9034                 /*
9035                  * Failing the vm entry is _not_ what the processor does
9036                  * but it's basically the only possibility we have.
9037                  * We could still enter the guest if CR8 load exits are
9038                  * enabled, CR8 store exits are enabled, and virtualize APIC
9039                  * access is disabled; in this case the processor would never
9040                  * use the TPR shadow and we could simply clear the bit from
9041                  * the execution control.  But such a configuration is useless,
9042                  * so let's keep the code simple.
9043                  */
9044                 if (!vmx->nested.virtual_apic_page)
9045                         return false;
9046         }
9047
9048         if (nested_cpu_has_posted_intr(vmcs12)) {
9049                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9050                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9051                         return false;
9052
9053                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9054                         kunmap(vmx->nested.pi_desc_page);
9055                         nested_release_page(vmx->nested.pi_desc_page);
9056                 }
9057                 vmx->nested.pi_desc_page =
9058                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9059                 if (!vmx->nested.pi_desc_page)
9060                         return false;
9061
9062                 vmx->nested.pi_desc =
9063                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9064                 if (!vmx->nested.pi_desc) {
9065                         nested_release_page_clean(vmx->nested.pi_desc_page);
9066                         return false;
9067                 }
9068                 vmx->nested.pi_desc =
9069                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9070                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9071                         (PAGE_SIZE - 1)));
9072         }
9073
9074         return true;
9075 }
9076
9077 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9078 {
9079         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9080         struct vcpu_vmx *vmx = to_vmx(vcpu);
9081
9082         if (vcpu->arch.virtual_tsc_khz == 0)
9083                 return;
9084
9085         /* Make sure short timeouts reliably trigger an immediate vmexit.
9086          * hrtimer_start does not guarantee this. */
9087         if (preemption_timeout <= 1) {
9088                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9089                 return;
9090         }
9091
9092         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9093         preemption_timeout *= 1000000;
9094         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9095         hrtimer_start(&vmx->nested.preemption_timer,
9096                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9097 }
9098
9099 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9100                                                 struct vmcs12 *vmcs12)
9101 {
9102         int maxphyaddr;
9103         u64 addr;
9104
9105         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9106                 return 0;
9107
9108         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9109                 WARN_ON(1);
9110                 return -EINVAL;
9111         }
9112         maxphyaddr = cpuid_maxphyaddr(vcpu);
9113
9114         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9115            ((addr + PAGE_SIZE) >> maxphyaddr))
9116                 return -EINVAL;
9117
9118         return 0;
9119 }
9120
9121 /*
9122  * Merge L0's and L1's MSR bitmap, return false to indicate that
9123  * we do not use the hardware.
9124  */
9125 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9126                                                struct vmcs12 *vmcs12)
9127 {
9128         int msr;
9129         struct page *page;
9130         unsigned long *msr_bitmap;
9131
9132         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9133                 return false;
9134
9135         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9136         if (!page) {
9137                 WARN_ON(1);
9138                 return false;
9139         }
9140         msr_bitmap = (unsigned long *)kmap(page);
9141         if (!msr_bitmap) {
9142                 nested_release_page_clean(page);
9143                 WARN_ON(1);
9144                 return false;
9145         }
9146
9147         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9148                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9149                         for (msr = 0x800; msr <= 0x8ff; msr++)
9150                                 nested_vmx_disable_intercept_for_msr(
9151                                         msr_bitmap,
9152                                         vmx_msr_bitmap_nested,
9153                                         msr, MSR_TYPE_R);
9154                 /* TPR is allowed */
9155                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9156                                 vmx_msr_bitmap_nested,
9157                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9158                                 MSR_TYPE_R | MSR_TYPE_W);
9159                 if (nested_cpu_has_vid(vmcs12)) {
9160                         /* EOI and self-IPI are allowed */
9161                         nested_vmx_disable_intercept_for_msr(
9162                                 msr_bitmap,
9163                                 vmx_msr_bitmap_nested,
9164                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9165                                 MSR_TYPE_W);
9166                         nested_vmx_disable_intercept_for_msr(
9167                                 msr_bitmap,
9168                                 vmx_msr_bitmap_nested,
9169                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9170                                 MSR_TYPE_W);
9171                 }
9172         } else {
9173                 /*
9174                  * Enable reading intercept of all the x2apic
9175                  * MSRs. We should not rely on vmcs12 to do any
9176                  * optimizations here, it may have been modified
9177                  * by L1.
9178                  */
9179                 for (msr = 0x800; msr <= 0x8ff; msr++)
9180                         __vmx_enable_intercept_for_msr(
9181                                 vmx_msr_bitmap_nested,
9182                                 msr,
9183                                 MSR_TYPE_R);
9184
9185                 __vmx_enable_intercept_for_msr(
9186                                 vmx_msr_bitmap_nested,
9187                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9188                                 MSR_TYPE_W);
9189                 __vmx_enable_intercept_for_msr(
9190                                 vmx_msr_bitmap_nested,
9191                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9192                                 MSR_TYPE_W);
9193                 __vmx_enable_intercept_for_msr(
9194                                 vmx_msr_bitmap_nested,
9195                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9196                                 MSR_TYPE_W);
9197         }
9198         kunmap(page);
9199         nested_release_page_clean(page);
9200
9201         return true;
9202 }
9203
9204 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9205                                            struct vmcs12 *vmcs12)
9206 {
9207         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9208             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9209             !nested_cpu_has_vid(vmcs12) &&
9210             !nested_cpu_has_posted_intr(vmcs12))
9211                 return 0;
9212
9213         /*
9214          * If virtualize x2apic mode is enabled,
9215          * virtualize apic access must be disabled.
9216          */
9217         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9218             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9219                 return -EINVAL;
9220
9221         /*
9222          * If virtual interrupt delivery is enabled,
9223          * we must exit on external interrupts.
9224          */
9225         if (nested_cpu_has_vid(vmcs12) &&
9226            !nested_exit_on_intr(vcpu))
9227                 return -EINVAL;
9228
9229         /*
9230          * bits 15:8 should be zero in posted_intr_nv,
9231          * the descriptor address has been already checked
9232          * in nested_get_vmcs12_pages.
9233          */
9234         if (nested_cpu_has_posted_intr(vmcs12) &&
9235            (!nested_cpu_has_vid(vmcs12) ||
9236             !nested_exit_intr_ack_set(vcpu) ||
9237             vmcs12->posted_intr_nv & 0xff00))
9238                 return -EINVAL;
9239
9240         /* tpr shadow is needed by all apicv features. */
9241         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9242                 return -EINVAL;
9243
9244         return 0;
9245 }
9246
9247 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9248                                        unsigned long count_field,
9249                                        unsigned long addr_field)
9250 {
9251         int maxphyaddr;
9252         u64 count, addr;
9253
9254         if (vmcs12_read_any(vcpu, count_field, &count) ||
9255             vmcs12_read_any(vcpu, addr_field, &addr)) {
9256                 WARN_ON(1);
9257                 return -EINVAL;
9258         }
9259         if (count == 0)
9260                 return 0;
9261         maxphyaddr = cpuid_maxphyaddr(vcpu);
9262         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9263             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9264                 pr_warn_ratelimited(
9265                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9266                         addr_field, maxphyaddr, count, addr);
9267                 return -EINVAL;
9268         }
9269         return 0;
9270 }
9271
9272 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9273                                                 struct vmcs12 *vmcs12)
9274 {
9275         if (vmcs12->vm_exit_msr_load_count == 0 &&
9276             vmcs12->vm_exit_msr_store_count == 0 &&
9277             vmcs12->vm_entry_msr_load_count == 0)
9278                 return 0; /* Fast path */
9279         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9280                                         VM_EXIT_MSR_LOAD_ADDR) ||
9281             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9282                                         VM_EXIT_MSR_STORE_ADDR) ||
9283             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9284                                         VM_ENTRY_MSR_LOAD_ADDR))
9285                 return -EINVAL;
9286         return 0;
9287 }
9288
9289 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9290                                        struct vmx_msr_entry *e)
9291 {
9292         /* x2APIC MSR accesses are not allowed */
9293         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9294                 return -EINVAL;
9295         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9296             e->index == MSR_IA32_UCODE_REV)
9297                 return -EINVAL;
9298         if (e->reserved != 0)
9299                 return -EINVAL;
9300         return 0;
9301 }
9302
9303 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9304                                      struct vmx_msr_entry *e)
9305 {
9306         if (e->index == MSR_FS_BASE ||
9307             e->index == MSR_GS_BASE ||
9308             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9309             nested_vmx_msr_check_common(vcpu, e))
9310                 return -EINVAL;
9311         return 0;
9312 }
9313
9314 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9315                                       struct vmx_msr_entry *e)
9316 {
9317         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9318             nested_vmx_msr_check_common(vcpu, e))
9319                 return -EINVAL;
9320         return 0;
9321 }
9322
9323 /*
9324  * Load guest's/host's msr at nested entry/exit.
9325  * return 0 for success, entry index for failure.
9326  */
9327 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9328 {
9329         u32 i;
9330         struct vmx_msr_entry e;
9331         struct msr_data msr;
9332
9333         msr.host_initiated = false;
9334         for (i = 0; i < count; i++) {
9335                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9336                                         &e, sizeof(e))) {
9337                         pr_warn_ratelimited(
9338                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9339                                 __func__, i, gpa + i * sizeof(e));
9340                         goto fail;
9341                 }
9342                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9343                         pr_warn_ratelimited(
9344                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9345                                 __func__, i, e.index, e.reserved);
9346                         goto fail;
9347                 }
9348                 msr.index = e.index;
9349                 msr.data = e.value;
9350                 if (kvm_set_msr(vcpu, &msr)) {
9351                         pr_warn_ratelimited(
9352                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9353                                 __func__, i, e.index, e.value);
9354                         goto fail;
9355                 }
9356         }
9357         return 0;
9358 fail:
9359         return i + 1;
9360 }
9361
9362 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9363 {
9364         u32 i;
9365         struct vmx_msr_entry e;
9366
9367         for (i = 0; i < count; i++) {
9368                 struct msr_data msr_info;
9369                 if (kvm_vcpu_read_guest(vcpu,
9370                                         gpa + i * sizeof(e),
9371                                         &e, 2 * sizeof(u32))) {
9372                         pr_warn_ratelimited(
9373                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9374                                 __func__, i, gpa + i * sizeof(e));
9375                         return -EINVAL;
9376                 }
9377                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9378                         pr_warn_ratelimited(
9379                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9380                                 __func__, i, e.index, e.reserved);
9381                         return -EINVAL;
9382                 }
9383                 msr_info.host_initiated = false;
9384                 msr_info.index = e.index;
9385                 if (kvm_get_msr(vcpu, &msr_info)) {
9386                         pr_warn_ratelimited(
9387                                 "%s cannot read MSR (%u, 0x%x)\n",
9388                                 __func__, i, e.index);
9389                         return -EINVAL;
9390                 }
9391                 if (kvm_vcpu_write_guest(vcpu,
9392                                          gpa + i * sizeof(e) +
9393                                              offsetof(struct vmx_msr_entry, value),
9394                                          &msr_info.data, sizeof(msr_info.data))) {
9395                         pr_warn_ratelimited(
9396                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9397                                 __func__, i, e.index, msr_info.data);
9398                         return -EINVAL;
9399                 }
9400         }
9401         return 0;
9402 }
9403
9404 /*
9405  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9406  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9407  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9408  * guest in a way that will both be appropriate to L1's requests, and our
9409  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9410  * function also has additional necessary side-effects, like setting various
9411  * vcpu->arch fields.
9412  */
9413 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9414 {
9415         struct vcpu_vmx *vmx = to_vmx(vcpu);
9416         u32 exec_control;
9417
9418         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9419         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9420         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9421         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9422         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9423         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9424         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9425         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9426         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9427         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9428         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9429         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9430         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9431         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9432         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9433         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9434         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9435         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9436         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9437         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9438         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9439         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9440         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9441         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9442         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9443         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9444         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9445         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9446         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9447         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9448         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9449         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9450         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9451         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9452         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9453         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9454
9455         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9456                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9457                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9458         } else {
9459                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9460                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9461         }
9462         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9463                 vmcs12->vm_entry_intr_info_field);
9464         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9465                 vmcs12->vm_entry_exception_error_code);
9466         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9467                 vmcs12->vm_entry_instruction_len);
9468         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9469                 vmcs12->guest_interruptibility_info);
9470         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9471         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9472         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9473                 vmcs12->guest_pending_dbg_exceptions);
9474         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9475         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9476
9477         if (nested_cpu_has_xsaves(vmcs12))
9478                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9479         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9480
9481         exec_control = vmcs12->pin_based_vm_exec_control;
9482         exec_control |= vmcs_config.pin_based_exec_ctrl;
9483         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9484
9485         if (nested_cpu_has_posted_intr(vmcs12)) {
9486                 /*
9487                  * Note that we use L0's vector here and in
9488                  * vmx_deliver_nested_posted_interrupt.
9489                  */
9490                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9491                 vmx->nested.pi_pending = false;
9492                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9493                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9494                         page_to_phys(vmx->nested.pi_desc_page) +
9495                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9496                         (PAGE_SIZE - 1)));
9497         } else
9498                 exec_control &= ~PIN_BASED_POSTED_INTR;
9499
9500         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9501
9502         vmx->nested.preemption_timer_expired = false;
9503         if (nested_cpu_has_preemption_timer(vmcs12))
9504                 vmx_start_preemption_timer(vcpu);
9505
9506         /*
9507          * Whether page-faults are trapped is determined by a combination of
9508          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9509          * If enable_ept, L0 doesn't care about page faults and we should
9510          * set all of these to L1's desires. However, if !enable_ept, L0 does
9511          * care about (at least some) page faults, and because it is not easy
9512          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9513          * to exit on each and every L2 page fault. This is done by setting
9514          * MASK=MATCH=0 and (see below) EB.PF=1.
9515          * Note that below we don't need special code to set EB.PF beyond the
9516          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9517          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9518          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9519          *
9520          * A problem with this approach (when !enable_ept) is that L1 may be
9521          * injected with more page faults than it asked for. This could have
9522          * caused problems, but in practice existing hypervisors don't care.
9523          * To fix this, we will need to emulate the PFEC checking (on the L1
9524          * page tables), using walk_addr(), when injecting PFs to L1.
9525          */
9526         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9527                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9528         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9529                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9530
9531         if (cpu_has_secondary_exec_ctrls()) {
9532                 exec_control = vmx_secondary_exec_control(vmx);
9533
9534                 /* Take the following fields only from vmcs12 */
9535                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9536                                   SECONDARY_EXEC_RDTSCP |
9537                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9538                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9539                                   SECONDARY_EXEC_PCOMMIT);
9540                 if (nested_cpu_has(vmcs12,
9541                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9542                         exec_control |= vmcs12->secondary_vm_exec_control;
9543
9544                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9545                         /*
9546                          * If translation failed, no matter: This feature asks
9547                          * to exit when accessing the given address, and if it
9548                          * can never be accessed, this feature won't do
9549                          * anything anyway.
9550                          */
9551                         if (!vmx->nested.apic_access_page)
9552                                 exec_control &=
9553                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9554                         else
9555                                 vmcs_write64(APIC_ACCESS_ADDR,
9556                                   page_to_phys(vmx->nested.apic_access_page));
9557                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9558                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9559                         exec_control |=
9560                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9561                         kvm_vcpu_reload_apic_access_page(vcpu);
9562                 }
9563
9564                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9565                         vmcs_write64(EOI_EXIT_BITMAP0,
9566                                 vmcs12->eoi_exit_bitmap0);
9567                         vmcs_write64(EOI_EXIT_BITMAP1,
9568                                 vmcs12->eoi_exit_bitmap1);
9569                         vmcs_write64(EOI_EXIT_BITMAP2,
9570                                 vmcs12->eoi_exit_bitmap2);
9571                         vmcs_write64(EOI_EXIT_BITMAP3,
9572                                 vmcs12->eoi_exit_bitmap3);
9573                         vmcs_write16(GUEST_INTR_STATUS,
9574                                 vmcs12->guest_intr_status);
9575                 }
9576
9577                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9578         }
9579
9580
9581         /*
9582          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9583          * Some constant fields are set here by vmx_set_constant_host_state().
9584          * Other fields are different per CPU, and will be set later when
9585          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9586          */
9587         vmx_set_constant_host_state(vmx);
9588
9589         /*
9590          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9591          * entry, but only if the current (host) sp changed from the value
9592          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9593          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9594          * here we just force the write to happen on entry.
9595          */
9596         vmx->host_rsp = 0;
9597
9598         exec_control = vmx_exec_control(vmx); /* L0's desires */
9599         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9600         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9601         exec_control &= ~CPU_BASED_TPR_SHADOW;
9602         exec_control |= vmcs12->cpu_based_vm_exec_control;
9603
9604         if (exec_control & CPU_BASED_TPR_SHADOW) {
9605                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9606                                 page_to_phys(vmx->nested.virtual_apic_page));
9607                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9608         }
9609
9610         if (cpu_has_vmx_msr_bitmap() &&
9611             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9612                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9613                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9614         } else
9615                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9616
9617         /*
9618          * Merging of IO bitmap not currently supported.
9619          * Rather, exit every time.
9620          */
9621         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9622         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9623
9624         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9625
9626         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9627          * bitwise-or of what L1 wants to trap for L2, and what we want to
9628          * trap. Note that CR0.TS also needs updating - we do this later.
9629          */
9630         update_exception_bitmap(vcpu);
9631         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9632         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9633
9634         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9635          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9636          * bits are further modified by vmx_set_efer() below.
9637          */
9638         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9639
9640         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9641          * emulated by vmx_set_efer(), below.
9642          */
9643         vm_entry_controls_init(vmx,
9644                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9645                         ~VM_ENTRY_IA32E_MODE) |
9646                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9647
9648         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9649                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9650                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9651         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9652                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9653
9654
9655         set_cr4_guest_host_mask(vmx);
9656
9657         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9658                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9659
9660         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9661                 vmcs_write64(TSC_OFFSET,
9662                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9663         else
9664                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9665
9666         if (enable_vpid) {
9667                 /*
9668                  * Trivially support vpid by letting L2s share their parent
9669                  * L1's vpid. TODO: move to a more elaborate solution, giving
9670                  * each L2 its own vpid and exposing the vpid feature to L1.
9671                  */
9672                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9673                 vmx_flush_tlb(vcpu);
9674         }
9675
9676         if (nested_cpu_has_ept(vmcs12)) {
9677                 kvm_mmu_unload(vcpu);
9678                 nested_ept_init_mmu_context(vcpu);
9679         }
9680
9681         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9682                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9683         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9684                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9685         else
9686                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9687         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9688         vmx_set_efer(vcpu, vcpu->arch.efer);
9689
9690         /*
9691          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9692          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9693          * The CR0_READ_SHADOW is what L2 should have expected to read given
9694          * the specifications by L1; It's not enough to take
9695          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9696          * have more bits than L1 expected.
9697          */
9698         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9699         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9700
9701         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9702         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9703
9704         /* shadow page tables on either EPT or shadow page tables */
9705         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9706         kvm_mmu_reset_context(vcpu);
9707
9708         if (!enable_ept)
9709                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9710
9711         /*
9712          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9713          */
9714         if (enable_ept) {
9715                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9716                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9717                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9718                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9719         }
9720
9721         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9722         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9723 }
9724
9725 /*
9726  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9727  * for running an L2 nested guest.
9728  */
9729 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9730 {
9731         struct vmcs12 *vmcs12;
9732         struct vcpu_vmx *vmx = to_vmx(vcpu);
9733         int cpu;
9734         struct loaded_vmcs *vmcs02;
9735         bool ia32e;
9736         u32 msr_entry_idx;
9737
9738         if (!nested_vmx_check_permission(vcpu) ||
9739             !nested_vmx_check_vmcs12(vcpu))
9740                 return 1;
9741
9742         skip_emulated_instruction(vcpu);
9743         vmcs12 = get_vmcs12(vcpu);
9744
9745         if (enable_shadow_vmcs)
9746                 copy_shadow_to_vmcs12(vmx);
9747
9748         /*
9749          * The nested entry process starts with enforcing various prerequisites
9750          * on vmcs12 as required by the Intel SDM, and act appropriately when
9751          * they fail: As the SDM explains, some conditions should cause the
9752          * instruction to fail, while others will cause the instruction to seem
9753          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9754          * To speed up the normal (success) code path, we should avoid checking
9755          * for misconfigurations which will anyway be caught by the processor
9756          * when using the merged vmcs02.
9757          */
9758         if (vmcs12->launch_state == launch) {
9759                 nested_vmx_failValid(vcpu,
9760                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9761                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9762                 return 1;
9763         }
9764
9765         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9766             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9767                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9768                 return 1;
9769         }
9770
9771         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9772                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9773                 return 1;
9774         }
9775
9776         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9777                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9778                 return 1;
9779         }
9780
9781         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9782                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9783                 return 1;
9784         }
9785
9786         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9787                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9788                 return 1;
9789         }
9790
9791         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9792                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9793                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9794             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9795                                 vmx->nested.nested_vmx_secondary_ctls_low,
9796                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9797             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9798                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9799                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9800             !vmx_control_verify(vmcs12->vm_exit_controls,
9801                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9802                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9803             !vmx_control_verify(vmcs12->vm_entry_controls,
9804                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9805                                 vmx->nested.nested_vmx_entry_ctls_high))
9806         {
9807                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9808                 return 1;
9809         }
9810
9811         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9812             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9813                 nested_vmx_failValid(vcpu,
9814                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9815                 return 1;
9816         }
9817
9818         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9819             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9820                 nested_vmx_entry_failure(vcpu, vmcs12,
9821                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9822                 return 1;
9823         }
9824         if (vmcs12->vmcs_link_pointer != -1ull) {
9825                 nested_vmx_entry_failure(vcpu, vmcs12,
9826                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9827                 return 1;
9828         }
9829
9830         /*
9831          * If the load IA32_EFER VM-entry control is 1, the following checks
9832          * are performed on the field for the IA32_EFER MSR:
9833          * - Bits reserved in the IA32_EFER MSR must be 0.
9834          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9835          *   the IA-32e mode guest VM-exit control. It must also be identical
9836          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9837          *   CR0.PG) is 1.
9838          */
9839         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9840                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9841                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9842                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9843                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9844                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9845                         nested_vmx_entry_failure(vcpu, vmcs12,
9846                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9847                         return 1;
9848                 }
9849         }
9850
9851         /*
9852          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9853          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9854          * the values of the LMA and LME bits in the field must each be that of
9855          * the host address-space size VM-exit control.
9856          */
9857         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9858                 ia32e = (vmcs12->vm_exit_controls &
9859                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9860                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9861                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9862                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9863                         nested_vmx_entry_failure(vcpu, vmcs12,
9864                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9865                         return 1;
9866                 }
9867         }
9868
9869         /*
9870          * We're finally done with prerequisite checking, and can start with
9871          * the nested entry.
9872          */
9873
9874         vmcs02 = nested_get_current_vmcs02(vmx);
9875         if (!vmcs02)
9876                 return -ENOMEM;
9877
9878         enter_guest_mode(vcpu);
9879
9880         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9881
9882         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9883                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9884
9885         cpu = get_cpu();
9886         vmx->loaded_vmcs = vmcs02;
9887         vmx_vcpu_put(vcpu);
9888         vmx_vcpu_load(vcpu, cpu);
9889         vcpu->cpu = cpu;
9890         put_cpu();
9891
9892         vmx_segment_cache_clear(vmx);
9893
9894         prepare_vmcs02(vcpu, vmcs12);
9895
9896         msr_entry_idx = nested_vmx_load_msr(vcpu,
9897                                             vmcs12->vm_entry_msr_load_addr,
9898                                             vmcs12->vm_entry_msr_load_count);
9899         if (msr_entry_idx) {
9900                 leave_guest_mode(vcpu);
9901                 vmx_load_vmcs01(vcpu);
9902                 nested_vmx_entry_failure(vcpu, vmcs12,
9903                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9904                 return 1;
9905         }
9906
9907         vmcs12->launch_state = 1;
9908
9909         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9910                 return kvm_vcpu_halt(vcpu);
9911
9912         vmx->nested.nested_run_pending = 1;
9913
9914         /*
9915          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9916          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9917          * returned as far as L1 is concerned. It will only return (and set
9918          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9919          */
9920         return 1;
9921 }
9922
9923 /*
9924  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9925  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9926  * This function returns the new value we should put in vmcs12.guest_cr0.
9927  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9928  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9929  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9930  *     didn't trap the bit, because if L1 did, so would L0).
9931  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9932  *     been modified by L2, and L1 knows it. So just leave the old value of
9933  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9934  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9935  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9936  *     changed these bits, and therefore they need to be updated, but L0
9937  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9938  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9939  */
9940 static inline unsigned long
9941 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9942 {
9943         return
9944         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9945         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9946         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9947                         vcpu->arch.cr0_guest_owned_bits));
9948 }
9949
9950 static inline unsigned long
9951 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9952 {
9953         return
9954         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9955         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9956         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9957                         vcpu->arch.cr4_guest_owned_bits));
9958 }
9959
9960 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9961                                        struct vmcs12 *vmcs12)
9962 {
9963         u32 idt_vectoring;
9964         unsigned int nr;
9965
9966         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9967                 nr = vcpu->arch.exception.nr;
9968                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9969
9970                 if (kvm_exception_is_soft(nr)) {
9971                         vmcs12->vm_exit_instruction_len =
9972                                 vcpu->arch.event_exit_inst_len;
9973                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9974                 } else
9975                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9976
9977                 if (vcpu->arch.exception.has_error_code) {
9978                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9979                         vmcs12->idt_vectoring_error_code =
9980                                 vcpu->arch.exception.error_code;
9981                 }
9982
9983                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9984         } else if (vcpu->arch.nmi_injected) {
9985                 vmcs12->idt_vectoring_info_field =
9986                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9987         } else if (vcpu->arch.interrupt.pending) {
9988                 nr = vcpu->arch.interrupt.nr;
9989                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9990
9991                 if (vcpu->arch.interrupt.soft) {
9992                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9993                         vmcs12->vm_entry_instruction_len =
9994                                 vcpu->arch.event_exit_inst_len;
9995                 } else
9996                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9997
9998                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9999         }
10000 }
10001
10002 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10003 {
10004         struct vcpu_vmx *vmx = to_vmx(vcpu);
10005
10006         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10007             vmx->nested.preemption_timer_expired) {
10008                 if (vmx->nested.nested_run_pending)
10009                         return -EBUSY;
10010                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10011                 return 0;
10012         }
10013
10014         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10015                 if (vmx->nested.nested_run_pending ||
10016                     vcpu->arch.interrupt.pending)
10017                         return -EBUSY;
10018                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10019                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10020                                   INTR_INFO_VALID_MASK, 0);
10021                 /*
10022                  * The NMI-triggered VM exit counts as injection:
10023                  * clear this one and block further NMIs.
10024                  */
10025                 vcpu->arch.nmi_pending = 0;
10026                 vmx_set_nmi_mask(vcpu, true);
10027                 return 0;
10028         }
10029
10030         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10031             nested_exit_on_intr(vcpu)) {
10032                 if (vmx->nested.nested_run_pending)
10033                         return -EBUSY;
10034                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10035                 return 0;
10036         }
10037
10038         return vmx_complete_nested_posted_interrupt(vcpu);
10039 }
10040
10041 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10042 {
10043         ktime_t remaining =
10044                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10045         u64 value;
10046
10047         if (ktime_to_ns(remaining) <= 0)
10048                 return 0;
10049
10050         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10051         do_div(value, 1000000);
10052         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10053 }
10054
10055 /*
10056  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10057  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10058  * and this function updates it to reflect the changes to the guest state while
10059  * L2 was running (and perhaps made some exits which were handled directly by L0
10060  * without going back to L1), and to reflect the exit reason.
10061  * Note that we do not have to copy here all VMCS fields, just those that
10062  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10063  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10064  * which already writes to vmcs12 directly.
10065  */
10066 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10067                            u32 exit_reason, u32 exit_intr_info,
10068                            unsigned long exit_qualification)
10069 {
10070         /* update guest state fields: */
10071         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10072         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10073
10074         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10075         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10076         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10077
10078         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10079         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10080         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10081         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10082         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10083         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10084         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10085         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10086         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10087         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10088         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10089         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10090         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10091         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10092         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10093         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10094         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10095         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10096         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10097         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10098         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10099         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10100         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10101         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10102         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10103         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10104         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10105         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10106         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10107         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10108         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10109         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10110         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10111         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10112         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10113         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10114
10115         vmcs12->guest_interruptibility_info =
10116                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10117         vmcs12->guest_pending_dbg_exceptions =
10118                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10119         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10120                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10121         else
10122                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10123
10124         if (nested_cpu_has_preemption_timer(vmcs12)) {
10125                 if (vmcs12->vm_exit_controls &
10126                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10127                         vmcs12->vmx_preemption_timer_value =
10128                                 vmx_get_preemption_timer_value(vcpu);
10129                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10130         }
10131
10132         /*
10133          * In some cases (usually, nested EPT), L2 is allowed to change its
10134          * own CR3 without exiting. If it has changed it, we must keep it.
10135          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10136          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10137          *
10138          * Additionally, restore L2's PDPTR to vmcs12.
10139          */
10140         if (enable_ept) {
10141                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10142                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10143                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10144                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10145                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10146         }
10147
10148         if (nested_cpu_has_vid(vmcs12))
10149                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10150
10151         vmcs12->vm_entry_controls =
10152                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10153                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10154
10155         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10156                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10157                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10158         }
10159
10160         /* TODO: These cannot have changed unless we have MSR bitmaps and
10161          * the relevant bit asks not to trap the change */
10162         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10163                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10164         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10165                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10166         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10167         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10168         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10169         if (vmx_mpx_supported())
10170                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10171         if (nested_cpu_has_xsaves(vmcs12))
10172                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10173
10174         /* update exit information fields: */
10175
10176         vmcs12->vm_exit_reason = exit_reason;
10177         vmcs12->exit_qualification = exit_qualification;
10178
10179         vmcs12->vm_exit_intr_info = exit_intr_info;
10180         if ((vmcs12->vm_exit_intr_info &
10181              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10182             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10183                 vmcs12->vm_exit_intr_error_code =
10184                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10185         vmcs12->idt_vectoring_info_field = 0;
10186         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10187         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10188
10189         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10190                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10191                  * instead of reading the real value. */
10192                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10193
10194                 /*
10195                  * Transfer the event that L0 or L1 may wanted to inject into
10196                  * L2 to IDT_VECTORING_INFO_FIELD.
10197                  */
10198                 vmcs12_save_pending_event(vcpu, vmcs12);
10199         }
10200
10201         /*
10202          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10203          * preserved above and would only end up incorrectly in L1.
10204          */
10205         vcpu->arch.nmi_injected = false;
10206         kvm_clear_exception_queue(vcpu);
10207         kvm_clear_interrupt_queue(vcpu);
10208 }
10209
10210 /*
10211  * A part of what we need to when the nested L2 guest exits and we want to
10212  * run its L1 parent, is to reset L1's guest state to the host state specified
10213  * in vmcs12.
10214  * This function is to be called not only on normal nested exit, but also on
10215  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10216  * Failures During or After Loading Guest State").
10217  * This function should be called when the active VMCS is L1's (vmcs01).
10218  */
10219 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10220                                    struct vmcs12 *vmcs12)
10221 {
10222         struct kvm_segment seg;
10223
10224         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10225                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10226         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10227                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10228         else
10229                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10230         vmx_set_efer(vcpu, vcpu->arch.efer);
10231
10232         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10233         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10234         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10235         /*
10236          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10237          * actually changed, because it depends on the current state of
10238          * fpu_active (which may have changed).
10239          * Note that vmx_set_cr0 refers to efer set above.
10240          */
10241         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10242         /*
10243          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10244          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10245          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10246          */
10247         update_exception_bitmap(vcpu);
10248         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10249         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10250
10251         /*
10252          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10253          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10254          */
10255         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10256         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10257
10258         nested_ept_uninit_mmu_context(vcpu);
10259
10260         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10261         kvm_mmu_reset_context(vcpu);
10262
10263         if (!enable_ept)
10264                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10265
10266         if (enable_vpid) {
10267                 /*
10268                  * Trivially support vpid by letting L2s share their parent
10269                  * L1's vpid. TODO: move to a more elaborate solution, giving
10270                  * each L2 its own vpid and exposing the vpid feature to L1.
10271                  */
10272                 vmx_flush_tlb(vcpu);
10273         }
10274
10275
10276         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10277         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10278         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10279         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10280         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10281
10282         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10283         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10284                 vmcs_write64(GUEST_BNDCFGS, 0);
10285
10286         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10287                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10288                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10289         }
10290         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10291                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10292                         vmcs12->host_ia32_perf_global_ctrl);
10293
10294         /* Set L1 segment info according to Intel SDM
10295             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10296         seg = (struct kvm_segment) {
10297                 .base = 0,
10298                 .limit = 0xFFFFFFFF,
10299                 .selector = vmcs12->host_cs_selector,
10300                 .type = 11,
10301                 .present = 1,
10302                 .s = 1,
10303                 .g = 1
10304         };
10305         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10306                 seg.l = 1;
10307         else
10308                 seg.db = 1;
10309         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10310         seg = (struct kvm_segment) {
10311                 .base = 0,
10312                 .limit = 0xFFFFFFFF,
10313                 .type = 3,
10314                 .present = 1,
10315                 .s = 1,
10316                 .db = 1,
10317                 .g = 1
10318         };
10319         seg.selector = vmcs12->host_ds_selector;
10320         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10321         seg.selector = vmcs12->host_es_selector;
10322         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10323         seg.selector = vmcs12->host_ss_selector;
10324         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10325         seg.selector = vmcs12->host_fs_selector;
10326         seg.base = vmcs12->host_fs_base;
10327         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10328         seg.selector = vmcs12->host_gs_selector;
10329         seg.base = vmcs12->host_gs_base;
10330         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10331         seg = (struct kvm_segment) {
10332                 .base = vmcs12->host_tr_base,
10333                 .limit = 0x67,
10334                 .selector = vmcs12->host_tr_selector,
10335                 .type = 11,
10336                 .present = 1
10337         };
10338         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10339
10340         kvm_set_dr(vcpu, 7, 0x400);
10341         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10342
10343         if (cpu_has_vmx_msr_bitmap())
10344                 vmx_set_msr_bitmap(vcpu);
10345
10346         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10347                                 vmcs12->vm_exit_msr_load_count))
10348                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10349 }
10350
10351 /*
10352  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10353  * and modify vmcs12 to make it see what it would expect to see there if
10354  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10355  */
10356 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10357                               u32 exit_intr_info,
10358                               unsigned long exit_qualification)
10359 {
10360         struct vcpu_vmx *vmx = to_vmx(vcpu);
10361         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10362
10363         /* trying to cancel vmlaunch/vmresume is a bug */
10364         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10365
10366         leave_guest_mode(vcpu);
10367         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10368                        exit_qualification);
10369
10370         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10371                                  vmcs12->vm_exit_msr_store_count))
10372                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10373
10374         vmx_load_vmcs01(vcpu);
10375
10376         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10377             && nested_exit_intr_ack_set(vcpu)) {
10378                 int irq = kvm_cpu_get_interrupt(vcpu);
10379                 WARN_ON(irq < 0);
10380                 vmcs12->vm_exit_intr_info = irq |
10381                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10382         }
10383
10384         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10385                                        vmcs12->exit_qualification,
10386                                        vmcs12->idt_vectoring_info_field,
10387                                        vmcs12->vm_exit_intr_info,
10388                                        vmcs12->vm_exit_intr_error_code,
10389                                        KVM_ISA_VMX);
10390
10391         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10392         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10393         vmx_segment_cache_clear(vmx);
10394
10395         /* if no vmcs02 cache requested, remove the one we used */
10396         if (VMCS02_POOL_SIZE == 0)
10397                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10398
10399         load_vmcs12_host_state(vcpu, vmcs12);
10400
10401         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10402         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10403
10404         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10405         vmx->host_rsp = 0;
10406
10407         /* Unpin physical memory we referred to in vmcs02 */
10408         if (vmx->nested.apic_access_page) {
10409                 nested_release_page(vmx->nested.apic_access_page);
10410                 vmx->nested.apic_access_page = NULL;
10411         }
10412         if (vmx->nested.virtual_apic_page) {
10413                 nested_release_page(vmx->nested.virtual_apic_page);
10414                 vmx->nested.virtual_apic_page = NULL;
10415         }
10416         if (vmx->nested.pi_desc_page) {
10417                 kunmap(vmx->nested.pi_desc_page);
10418                 nested_release_page(vmx->nested.pi_desc_page);
10419                 vmx->nested.pi_desc_page = NULL;
10420                 vmx->nested.pi_desc = NULL;
10421         }
10422
10423         /*
10424          * We are now running in L2, mmu_notifier will force to reload the
10425          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10426          */
10427         kvm_vcpu_reload_apic_access_page(vcpu);
10428
10429         /*
10430          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10431          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10432          * success or failure flag accordingly.
10433          */
10434         if (unlikely(vmx->fail)) {
10435                 vmx->fail = 0;
10436                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10437         } else
10438                 nested_vmx_succeed(vcpu);
10439         if (enable_shadow_vmcs)
10440                 vmx->nested.sync_shadow_vmcs = true;
10441
10442         /* in case we halted in L2 */
10443         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10444 }
10445
10446 /*
10447  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10448  */
10449 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10450 {
10451         if (is_guest_mode(vcpu))
10452                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10453         free_nested(to_vmx(vcpu));
10454 }
10455
10456 /*
10457  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10458  * 23.7 "VM-entry failures during or after loading guest state" (this also
10459  * lists the acceptable exit-reason and exit-qualification parameters).
10460  * It should only be called before L2 actually succeeded to run, and when
10461  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10462  */
10463 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10464                         struct vmcs12 *vmcs12,
10465                         u32 reason, unsigned long qualification)
10466 {
10467         load_vmcs12_host_state(vcpu, vmcs12);
10468         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10469         vmcs12->exit_qualification = qualification;
10470         nested_vmx_succeed(vcpu);
10471         if (enable_shadow_vmcs)
10472                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10473 }
10474
10475 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10476                                struct x86_instruction_info *info,
10477                                enum x86_intercept_stage stage)
10478 {
10479         return X86EMUL_CONTINUE;
10480 }
10481
10482 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10483 {
10484         if (ple_gap)
10485                 shrink_ple_window(vcpu);
10486 }
10487
10488 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10489                                      struct kvm_memory_slot *slot)
10490 {
10491         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10492         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10493 }
10494
10495 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10496                                        struct kvm_memory_slot *slot)
10497 {
10498         kvm_mmu_slot_set_dirty(kvm, slot);
10499 }
10500
10501 static void vmx_flush_log_dirty(struct kvm *kvm)
10502 {
10503         kvm_flush_pml_buffers(kvm);
10504 }
10505
10506 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10507                                            struct kvm_memory_slot *memslot,
10508                                            gfn_t offset, unsigned long mask)
10509 {
10510         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10511 }
10512
10513 /*
10514  * This routine does the following things for vCPU which is going
10515  * to be blocked if VT-d PI is enabled.
10516  * - Store the vCPU to the wakeup list, so when interrupts happen
10517  *   we can find the right vCPU to wake up.
10518  * - Change the Posted-interrupt descriptor as below:
10519  *      'NDST' <-- vcpu->pre_pcpu
10520  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10521  * - If 'ON' is set during this process, which means at least one
10522  *   interrupt is posted for this vCPU, we cannot block it, in
10523  *   this case, return 1, otherwise, return 0.
10524  *
10525  */
10526 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10527 {
10528         unsigned long flags;
10529         unsigned int dest;
10530         struct pi_desc old, new;
10531         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10532
10533         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10534                 !irq_remapping_cap(IRQ_POSTING_CAP))
10535                 return 0;
10536
10537         vcpu->pre_pcpu = vcpu->cpu;
10538         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10539                           vcpu->pre_pcpu), flags);
10540         list_add_tail(&vcpu->blocked_vcpu_list,
10541                       &per_cpu(blocked_vcpu_on_cpu,
10542                       vcpu->pre_pcpu));
10543         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10544                                vcpu->pre_pcpu), flags);
10545
10546         do {
10547                 old.control = new.control = pi_desc->control;
10548
10549                 /*
10550                  * We should not block the vCPU if
10551                  * an interrupt is posted for it.
10552                  */
10553                 if (pi_test_on(pi_desc) == 1) {
10554                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10555                                           vcpu->pre_pcpu), flags);
10556                         list_del(&vcpu->blocked_vcpu_list);
10557                         spin_unlock_irqrestore(
10558                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10559                                         vcpu->pre_pcpu), flags);
10560                         vcpu->pre_pcpu = -1;
10561
10562                         return 1;
10563                 }
10564
10565                 WARN((pi_desc->sn == 1),
10566                      "Warning: SN field of posted-interrupts "
10567                      "is set before blocking\n");
10568
10569                 /*
10570                  * Since vCPU can be preempted during this process,
10571                  * vcpu->cpu could be different with pre_pcpu, we
10572                  * need to set pre_pcpu as the destination of wakeup
10573                  * notification event, then we can find the right vCPU
10574                  * to wakeup in wakeup handler if interrupts happen
10575                  * when the vCPU is in blocked state.
10576                  */
10577                 dest = cpu_physical_id(vcpu->pre_pcpu);
10578
10579                 if (x2apic_enabled())
10580                         new.ndst = dest;
10581                 else
10582                         new.ndst = (dest << 8) & 0xFF00;
10583
10584                 /* set 'NV' to 'wakeup vector' */
10585                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10586         } while (cmpxchg(&pi_desc->control, old.control,
10587                         new.control) != old.control);
10588
10589         return 0;
10590 }
10591
10592 static void vmx_post_block(struct kvm_vcpu *vcpu)
10593 {
10594         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10595         struct pi_desc old, new;
10596         unsigned int dest;
10597         unsigned long flags;
10598
10599         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10600                 !irq_remapping_cap(IRQ_POSTING_CAP))
10601                 return;
10602
10603         do {
10604                 old.control = new.control = pi_desc->control;
10605
10606                 dest = cpu_physical_id(vcpu->cpu);
10607
10608                 if (x2apic_enabled())
10609                         new.ndst = dest;
10610                 else
10611                         new.ndst = (dest << 8) & 0xFF00;
10612
10613                 /* Allow posting non-urgent interrupts */
10614                 new.sn = 0;
10615
10616                 /* set 'NV' to 'notification vector' */
10617                 new.nv = POSTED_INTR_VECTOR;
10618         } while (cmpxchg(&pi_desc->control, old.control,
10619                         new.control) != old.control);
10620
10621         if(vcpu->pre_pcpu != -1) {
10622                 spin_lock_irqsave(
10623                         &per_cpu(blocked_vcpu_on_cpu_lock,
10624                         vcpu->pre_pcpu), flags);
10625                 list_del(&vcpu->blocked_vcpu_list);
10626                 spin_unlock_irqrestore(
10627                         &per_cpu(blocked_vcpu_on_cpu_lock,
10628                         vcpu->pre_pcpu), flags);
10629                 vcpu->pre_pcpu = -1;
10630         }
10631 }
10632
10633 /*
10634  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10635  *
10636  * @kvm: kvm
10637  * @host_irq: host irq of the interrupt
10638  * @guest_irq: gsi of the interrupt
10639  * @set: set or unset PI
10640  * returns 0 on success, < 0 on failure
10641  */
10642 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10643                               uint32_t guest_irq, bool set)
10644 {
10645         struct kvm_kernel_irq_routing_entry *e;
10646         struct kvm_irq_routing_table *irq_rt;
10647         struct kvm_lapic_irq irq;
10648         struct kvm_vcpu *vcpu;
10649         struct vcpu_data vcpu_info;
10650         int idx, ret = -EINVAL;
10651
10652         if (!kvm_arch_has_assigned_device(kvm) ||
10653                 !irq_remapping_cap(IRQ_POSTING_CAP))
10654                 return 0;
10655
10656         idx = srcu_read_lock(&kvm->irq_srcu);
10657         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10658         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10659
10660         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10661                 if (e->type != KVM_IRQ_ROUTING_MSI)
10662                         continue;
10663                 /*
10664                  * VT-d PI cannot support posting multicast/broadcast
10665                  * interrupts to a vCPU, we still use interrupt remapping
10666                  * for these kind of interrupts.
10667                  *
10668                  * For lowest-priority interrupts, we only support
10669                  * those with single CPU as the destination, e.g. user
10670                  * configures the interrupts via /proc/irq or uses
10671                  * irqbalance to make the interrupts single-CPU.
10672                  *
10673                  * We will support full lowest-priority interrupt later.
10674                  */
10675
10676                 kvm_set_msi_irq(e, &irq);
10677                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10678                         continue;
10679
10680                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10681                 vcpu_info.vector = irq.vector;
10682
10683                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10684                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10685
10686                 if (set)
10687                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10688                 else {
10689                         /* suppress notification event before unposting */
10690                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10691                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10692                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10693                 }
10694
10695                 if (ret < 0) {
10696                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10697                                         __func__);
10698                         goto out;
10699                 }
10700         }
10701
10702         ret = 0;
10703 out:
10704         srcu_read_unlock(&kvm->irq_srcu, idx);
10705         return ret;
10706 }
10707
10708 static struct kvm_x86_ops vmx_x86_ops = {
10709         .cpu_has_kvm_support = cpu_has_kvm_support,
10710         .disabled_by_bios = vmx_disabled_by_bios,
10711         .hardware_setup = hardware_setup,
10712         .hardware_unsetup = hardware_unsetup,
10713         .check_processor_compatibility = vmx_check_processor_compat,
10714         .hardware_enable = hardware_enable,
10715         .hardware_disable = hardware_disable,
10716         .cpu_has_accelerated_tpr = report_flexpriority,
10717         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10718
10719         .vcpu_create = vmx_create_vcpu,
10720         .vcpu_free = vmx_free_vcpu,
10721         .vcpu_reset = vmx_vcpu_reset,
10722
10723         .prepare_guest_switch = vmx_save_host_state,
10724         .vcpu_load = vmx_vcpu_load,
10725         .vcpu_put = vmx_vcpu_put,
10726
10727         .update_db_bp_intercept = update_exception_bitmap,
10728         .get_msr = vmx_get_msr,
10729         .set_msr = vmx_set_msr,
10730         .get_segment_base = vmx_get_segment_base,
10731         .get_segment = vmx_get_segment,
10732         .set_segment = vmx_set_segment,
10733         .get_cpl = vmx_get_cpl,
10734         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10735         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10736         .decache_cr3 = vmx_decache_cr3,
10737         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10738         .set_cr0 = vmx_set_cr0,
10739         .set_cr3 = vmx_set_cr3,
10740         .set_cr4 = vmx_set_cr4,
10741         .set_efer = vmx_set_efer,
10742         .get_idt = vmx_get_idt,
10743         .set_idt = vmx_set_idt,
10744         .get_gdt = vmx_get_gdt,
10745         .set_gdt = vmx_set_gdt,
10746         .get_dr6 = vmx_get_dr6,
10747         .set_dr6 = vmx_set_dr6,
10748         .set_dr7 = vmx_set_dr7,
10749         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10750         .cache_reg = vmx_cache_reg,
10751         .get_rflags = vmx_get_rflags,
10752         .set_rflags = vmx_set_rflags,
10753         .fpu_activate = vmx_fpu_activate,
10754         .fpu_deactivate = vmx_fpu_deactivate,
10755
10756         .tlb_flush = vmx_flush_tlb,
10757
10758         .run = vmx_vcpu_run,
10759         .handle_exit = vmx_handle_exit,
10760         .skip_emulated_instruction = skip_emulated_instruction,
10761         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10762         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10763         .patch_hypercall = vmx_patch_hypercall,
10764         .set_irq = vmx_inject_irq,
10765         .set_nmi = vmx_inject_nmi,
10766         .queue_exception = vmx_queue_exception,
10767         .cancel_injection = vmx_cancel_injection,
10768         .interrupt_allowed = vmx_interrupt_allowed,
10769         .nmi_allowed = vmx_nmi_allowed,
10770         .get_nmi_mask = vmx_get_nmi_mask,
10771         .set_nmi_mask = vmx_set_nmi_mask,
10772         .enable_nmi_window = enable_nmi_window,
10773         .enable_irq_window = enable_irq_window,
10774         .update_cr8_intercept = update_cr8_intercept,
10775         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10776         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10777         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10778         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10779         .hwapic_irr_update = vmx_hwapic_irr_update,
10780         .hwapic_isr_update = vmx_hwapic_isr_update,
10781         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10782         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10783
10784         .set_tss_addr = vmx_set_tss_addr,
10785         .get_tdp_level = get_ept_level,
10786         .get_mt_mask = vmx_get_mt_mask,
10787
10788         .get_exit_info = vmx_get_exit_info,
10789
10790         .get_lpage_level = vmx_get_lpage_level,
10791
10792         .cpuid_update = vmx_cpuid_update,
10793
10794         .rdtscp_supported = vmx_rdtscp_supported,
10795         .invpcid_supported = vmx_invpcid_supported,
10796
10797         .set_supported_cpuid = vmx_set_supported_cpuid,
10798
10799         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10800
10801         .set_tsc_khz = vmx_set_tsc_khz,
10802         .read_tsc_offset = vmx_read_tsc_offset,
10803         .write_tsc_offset = vmx_write_tsc_offset,
10804         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10805         .compute_tsc_offset = vmx_compute_tsc_offset,
10806         .read_l1_tsc = vmx_read_l1_tsc,
10807
10808         .set_tdp_cr3 = vmx_set_cr3,
10809
10810         .check_intercept = vmx_check_intercept,
10811         .handle_external_intr = vmx_handle_external_intr,
10812         .mpx_supported = vmx_mpx_supported,
10813         .xsaves_supported = vmx_xsaves_supported,
10814
10815         .check_nested_events = vmx_check_nested_events,
10816
10817         .sched_in = vmx_sched_in,
10818
10819         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10820         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10821         .flush_log_dirty = vmx_flush_log_dirty,
10822         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10823
10824         .pre_block = vmx_pre_block,
10825         .post_block = vmx_post_block,
10826
10827         .pmu_ops = &intel_pmu_ops,
10828
10829         .update_pi_irte = vmx_update_pi_irte,
10830 };
10831
10832 static int __init vmx_init(void)
10833 {
10834         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10835                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10836         if (r)
10837                 return r;
10838
10839 #ifdef CONFIG_KEXEC_CORE
10840         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10841                            crash_vmclear_local_loaded_vmcss);
10842 #endif
10843
10844         return 0;
10845 }
10846
10847 static void __exit vmx_exit(void)
10848 {
10849 #ifdef CONFIG_KEXEC_CORE
10850         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10851         synchronize_rcu();
10852 #endif
10853
10854         kvm_exit();
10855 }
10856
10857 module_init(vmx_init)
10858 module_exit(vmx_exit)