arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 static u64 __read_mostly host_xss;
 103
 104 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 105 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 106 #define KVM_VM_CR0_ALWAYS_ON                                            \
 107         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 108 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 109         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 110          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 111
 112 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 113 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 114
 115 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 116
 117 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 118
 119 /*
 120  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 121  * ple_gap:    upper bound on the amount of time between two successive
 122  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 123  *             According to test, this time is usually smaller than 128 cycles.
 124  * ple_window: upper bound on the amount of time a guest is allowed to execute
 125  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 126  *             less than 2^12 cycles
 127  * Time is measured based on a counter that runs at the same rate as the TSC,
 128  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 129  */
 130 #define KVM_VMX_DEFAULT_PLE_GAP           128
 131 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 132 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 133 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 134 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 135                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 136
 137 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 138 module_param(ple_gap, int, S_IRUGO);
 139
 140 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 141 module_param(ple_window, int, S_IRUGO);
 142
 143 /* Default doubles per-vcpu window every exit. */
 144 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 145 module_param(ple_window_grow, int, S_IRUGO);
 146
 147 /* Default resets per-vcpu window every exit to ple_window. */
 148 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 149 module_param(ple_window_shrink, int, S_IRUGO);
 150
 151 /* Default is to compute the maximum so we can never overflow. */
 152 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 153 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 154 module_param(ple_window_max, int, S_IRUGO);
 155
 156 extern const ulong vmx_return;
 157
 158 #define NR_AUTOLOAD_MSRS 8
 159 #define VMCS02_POOL_SIZE 1
 160
 161 struct vmcs {
 162         u32 revision_id;
 163         u32 abort;
 164         char data[0];
 165 };
 166
 167 /*
 168  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 169  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 170  * loaded on this CPU (so we can clear them if the CPU goes down).
 171  */
 172 struct loaded_vmcs {
 173         struct vmcs *vmcs;
 174         int cpu;
 175         int launched;
 176         struct list_head loaded_vmcss_on_cpu_link;
 177 };
 178
 179 struct shared_msr_entry {
 180         unsigned index;
 181         u64 data;
 182         u64 mask;
 183 };
 184
 185 /*
 186  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 187  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 188  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 189  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 190  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 191  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 192  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 193  * underlying hardware which will be used to run L2.
 194  * This structure is packed to ensure that its layout is identical across
 195  * machines (necessary for live migration).
 196  * If there are changes in this struct, VMCS12_REVISION must be changed.
 197  */
 198 typedef u64 natural_width;
 199 struct __packed vmcs12 {
 200         /* According to the Intel spec, a VMCS region must start with the
 201          * following two fields. Then follow implementation-specific data.
 202          */
 203         u32 revision_id;
 204         u32 abort;
 205
 206         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 207         u32 padding[7]; /* room for future expansion */
 208
 209         u64 io_bitmap_a;
 210         u64 io_bitmap_b;
 211         u64 msr_bitmap;
 212         u64 vm_exit_msr_store_addr;
 213         u64 vm_exit_msr_load_addr;
 214         u64 vm_entry_msr_load_addr;
 215         u64 tsc_offset;
 216         u64 virtual_apic_page_addr;
 217         u64 apic_access_addr;
 218         u64 ept_pointer;
 219         u64 guest_physical_address;
 220         u64 vmcs_link_pointer;
 221         u64 guest_ia32_debugctl;
 222         u64 guest_ia32_pat;
 223         u64 guest_ia32_efer;
 224         u64 guest_ia32_perf_global_ctrl;
 225         u64 guest_pdptr0;
 226         u64 guest_pdptr1;
 227         u64 guest_pdptr2;
 228         u64 guest_pdptr3;
 229         u64 guest_bndcfgs;
 230         u64 host_ia32_pat;
 231         u64 host_ia32_efer;
 232         u64 host_ia32_perf_global_ctrl;
 233         u64 padding64[8]; /* room for future expansion */
 234         /*
 235          * To allow migration of L1 (complete with its L2 guests) between
 236          * machines of different natural widths (32 or 64 bit), we cannot have
 237          * unsigned long fields with no explict size. We use u64 (aliased
 238          * natural_width) instead. Luckily, x86 is little-endian.
 239          */
 240         natural_width cr0_guest_host_mask;
 241         natural_width cr4_guest_host_mask;
 242         natural_width cr0_read_shadow;
 243         natural_width cr4_read_shadow;
 244         natural_width cr3_target_value0;
 245         natural_width cr3_target_value1;
 246         natural_width cr3_target_value2;
 247         natural_width cr3_target_value3;
 248         natural_width exit_qualification;
 249         natural_width guest_linear_address;
 250         natural_width guest_cr0;
 251         natural_width guest_cr3;
 252         natural_width guest_cr4;
 253         natural_width guest_es_base;
 254         natural_width guest_cs_base;
 255         natural_width guest_ss_base;
 256         natural_width guest_ds_base;
 257         natural_width guest_fs_base;
 258         natural_width guest_gs_base;
 259         natural_width guest_ldtr_base;
 260         natural_width guest_tr_base;
 261         natural_width guest_gdtr_base;
 262         natural_width guest_idtr_base;
 263         natural_width guest_dr7;
 264         natural_width guest_rsp;
 265         natural_width guest_rip;
 266         natural_width guest_rflags;
 267         natural_width guest_pending_dbg_exceptions;
 268         natural_width guest_sysenter_esp;
 269         natural_width guest_sysenter_eip;
 270         natural_width host_cr0;
 271         natural_width host_cr3;
 272         natural_width host_cr4;
 273         natural_width host_fs_base;
 274         natural_width host_gs_base;
 275         natural_width host_tr_base;
 276         natural_width host_gdtr_base;
 277         natural_width host_idtr_base;
 278         natural_width host_ia32_sysenter_esp;
 279         natural_width host_ia32_sysenter_eip;
 280         natural_width host_rsp;
 281         natural_width host_rip;
 282         natural_width paddingl[8]; /* room for future expansion */
 283         u32 pin_based_vm_exec_control;
 284         u32 cpu_based_vm_exec_control;
 285         u32 exception_bitmap;
 286         u32 page_fault_error_code_mask;
 287         u32 page_fault_error_code_match;
 288         u32 cr3_target_count;
 289         u32 vm_exit_controls;
 290         u32 vm_exit_msr_store_count;
 291         u32 vm_exit_msr_load_count;
 292         u32 vm_entry_controls;
 293         u32 vm_entry_msr_load_count;
 294         u32 vm_entry_intr_info_field;
 295         u32 vm_entry_exception_error_code;
 296         u32 vm_entry_instruction_len;
 297         u32 tpr_threshold;
 298         u32 secondary_vm_exec_control;
 299         u32 vm_instruction_error;
 300         u32 vm_exit_reason;
 301         u32 vm_exit_intr_info;
 302         u32 vm_exit_intr_error_code;
 303         u32 idt_vectoring_info_field;
 304         u32 idt_vectoring_error_code;
 305         u32 vm_exit_instruction_len;
 306         u32 vmx_instruction_info;
 307         u32 guest_es_limit;
 308         u32 guest_cs_limit;
 309         u32 guest_ss_limit;
 310         u32 guest_ds_limit;
 311         u32 guest_fs_limit;
 312         u32 guest_gs_limit;
 313         u32 guest_ldtr_limit;
 314         u32 guest_tr_limit;
 315         u32 guest_gdtr_limit;
 316         u32 guest_idtr_limit;
 317         u32 guest_es_ar_bytes;
 318         u32 guest_cs_ar_bytes;
 319         u32 guest_ss_ar_bytes;
 320         u32 guest_ds_ar_bytes;
 321         u32 guest_fs_ar_bytes;
 322         u32 guest_gs_ar_bytes;
 323         u32 guest_ldtr_ar_bytes;
 324         u32 guest_tr_ar_bytes;
 325         u32 guest_interruptibility_info;
 326         u32 guest_activity_state;
 327         u32 guest_sysenter_cs;
 328         u32 host_ia32_sysenter_cs;
 329         u32 vmx_preemption_timer_value;
 330         u32 padding32[7]; /* room for future expansion */
 331         u16 virtual_processor_id;
 332         u16 guest_es_selector;
 333         u16 guest_cs_selector;
 334         u16 guest_ss_selector;
 335         u16 guest_ds_selector;
 336         u16 guest_fs_selector;
 337         u16 guest_gs_selector;
 338         u16 guest_ldtr_selector;
 339         u16 guest_tr_selector;
 340         u16 host_es_selector;
 341         u16 host_cs_selector;
 342         u16 host_ss_selector;
 343         u16 host_ds_selector;
 344         u16 host_fs_selector;
 345         u16 host_gs_selector;
 346         u16 host_tr_selector;
 347 };
 348
 349 /*
 350  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 351  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 352  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 353  */
 354 #define VMCS12_REVISION 0x11e57ed0
 355
 356 /*
 357  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 358  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 359  * current implementation, 4K are reserved to avoid future complications.
 360  */
 361 #define VMCS12_SIZE 0x1000
 362
 363 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 364 struct vmcs02_list {
 365         struct list_head list;
 366         gpa_t vmptr;
 367         struct loaded_vmcs vmcs02;
 368 };
 369
 370 /*
 371  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 372  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 373  */
 374 struct nested_vmx {
 375         /* Has the level1 guest done vmxon? */
 376         bool vmxon;
 377         gpa_t vmxon_ptr;
 378
 379         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 380         gpa_t current_vmptr;
 381         /* The host-usable pointer to the above */
 382         struct page *current_vmcs12_page;
 383         struct vmcs12 *current_vmcs12;
 384         struct vmcs *current_shadow_vmcs;
 385         /*
 386          * Indicates if the shadow vmcs must be updated with the
 387          * data hold by vmcs12
 388          */
 389         bool sync_shadow_vmcs;
 390
 391         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 392         struct list_head vmcs02_pool;
 393         int vmcs02_num;
 394         u64 vmcs01_tsc_offset;
 395         /* L2 must run next, and mustn't decide to exit to L1. */
 396         bool nested_run_pending;
 397         /*
 398          * Guest pages referred to in vmcs02 with host-physical pointers, so
 399          * we must keep them pinned while L2 runs.
 400          */
 401         struct page *apic_access_page;
 402         struct page *virtual_apic_page;
 403         u64 msr_ia32_feature_control;
 404
 405         struct hrtimer preemption_timer;
 406         bool preemption_timer_expired;
 407
 408         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 409         u64 vmcs01_debugctl;
 410 };
 411
 412 #define POSTED_INTR_ON  0
 413 /* Posted-Interrupt Descriptor */
 414 struct pi_desc {
 415         u32 pir[8];     /* Posted interrupt requested */
 416         u32 control;    /* bit 0 of control is outstanding notification bit */
 417         u32 rsvd[7];
 418 } __aligned(64);
 419
 420 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 421 {
 422         return test_and_set_bit(POSTED_INTR_ON,
 423                         (unsigned long *)&pi_desc->control);
 424 }
 425
 426 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 427 {
 428         return test_and_clear_bit(POSTED_INTR_ON,
 429                         (unsigned long *)&pi_desc->control);
 430 }
 431
 432 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 433 {
 434         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 435 }
 436
 437 struct vcpu_vmx {
 438         struct kvm_vcpu       vcpu;
 439         unsigned long         host_rsp;
 440         u8                    fail;
 441         bool                  nmi_known_unmasked;
 442         u32                   exit_intr_info;
 443         u32                   idt_vectoring_info;
 444         ulong                 rflags;
 445         struct shared_msr_entry *guest_msrs;
 446         int                   nmsrs;
 447         int                   save_nmsrs;
 448         unsigned long         host_idt_base;
 449 #ifdef CONFIG_X86_64
 450         u64                   msr_host_kernel_gs_base;
 451         u64                   msr_guest_kernel_gs_base;
 452 #endif
 453         u32 vm_entry_controls_shadow;
 454         u32 vm_exit_controls_shadow;
 455         /*
 456          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 457          * non-nested (L1) guest, it always points to vmcs01. For a nested
 458          * guest (L2), it points to a different VMCS.
 459          */
 460         struct loaded_vmcs    vmcs01;
 461         struct loaded_vmcs   *loaded_vmcs;
 462         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 463         struct msr_autoload {
 464                 unsigned nr;
 465                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 466                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 467         } msr_autoload;
 468         struct {
 469                 int           loaded;
 470                 u16           fs_sel, gs_sel, ldt_sel;
 471 #ifdef CONFIG_X86_64
 472                 u16           ds_sel, es_sel;
 473 #endif
 474                 int           gs_ldt_reload_needed;
 475                 int           fs_reload_needed;
 476                 u64           msr_host_bndcfgs;
 477                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 478         } host_state;
 479         struct {
 480                 int vm86_active;
 481                 ulong save_rflags;
 482                 struct kvm_segment segs[8];
 483         } rmode;
 484         struct {
 485                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 486                 struct kvm_save_segment {
 487                         u16 selector;
 488                         unsigned long base;
 489                         u32 limit;
 490                         u32 ar;
 491                 } seg[8];
 492         } segment_cache;
 493         int vpid;
 494         bool emulation_required;
 495
 496         /* Support for vnmi-less CPUs */
 497         int soft_vnmi_blocked;
 498         ktime_t entry_time;
 499         s64 vnmi_blocked_time;
 500         u32 exit_reason;
 501
 502         bool rdtscp_enabled;
 503
 504         /* Posted interrupt descriptor */
 505         struct pi_desc pi_desc;
 506
 507         /* Support for a guest hypervisor (nested VMX) */
 508         struct nested_vmx nested;
 509
 510         /* Dynamic PLE window. */
 511         int ple_window;
 512         bool ple_window_dirty;
 513 };
 514
 515 enum segment_cache_field {
 516         SEG_FIELD_SEL = 0,
 517         SEG_FIELD_BASE = 1,
 518         SEG_FIELD_LIMIT = 2,
 519         SEG_FIELD_AR = 3,
 520
 521         SEG_FIELD_NR = 4
 522 };
 523
 524 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 525 {
 526         return container_of(vcpu, struct vcpu_vmx, vcpu);
 527 }
 528
 529 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 530 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 531 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 532                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 533
 534
 535 static unsigned long shadow_read_only_fields[] = {
 536         /*
 537          * We do NOT shadow fields that are modified when L0
 538          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 539          * VMXON...) executed by L1.
 540          * For example, VM_INSTRUCTION_ERROR is read
 541          * by L1 if a vmx instruction fails (part of the error path).
 542          * Note the code assumes this logic. If for some reason
 543          * we start shadowing these fields then we need to
 544          * force a shadow sync when L0 emulates vmx instructions
 545          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 546          * by nested_vmx_failValid)
 547          */
 548         VM_EXIT_REASON,
 549         VM_EXIT_INTR_INFO,
 550         VM_EXIT_INSTRUCTION_LEN,
 551         IDT_VECTORING_INFO_FIELD,
 552         IDT_VECTORING_ERROR_CODE,
 553         VM_EXIT_INTR_ERROR_CODE,
 554         EXIT_QUALIFICATION,
 555         GUEST_LINEAR_ADDRESS,
 556         GUEST_PHYSICAL_ADDRESS
 557 };
 558 static int max_shadow_read_only_fields =
 559         ARRAY_SIZE(shadow_read_only_fields);
 560
 561 static unsigned long shadow_read_write_fields[] = {
 562         TPR_THRESHOLD,
 563         GUEST_RIP,
 564         GUEST_RSP,
 565         GUEST_CR0,
 566         GUEST_CR3,
 567         GUEST_CR4,
 568         GUEST_INTERRUPTIBILITY_INFO,
 569         GUEST_RFLAGS,
 570         GUEST_CS_SELECTOR,
 571         GUEST_CS_AR_BYTES,
 572         GUEST_CS_LIMIT,
 573         GUEST_CS_BASE,
 574         GUEST_ES_BASE,
 575         GUEST_BNDCFGS,
 576         CR0_GUEST_HOST_MASK,
 577         CR0_READ_SHADOW,
 578         CR4_READ_SHADOW,
 579         TSC_OFFSET,
 580         EXCEPTION_BITMAP,
 581         CPU_BASED_VM_EXEC_CONTROL,
 582         VM_ENTRY_EXCEPTION_ERROR_CODE,
 583         VM_ENTRY_INTR_INFO_FIELD,
 584         VM_ENTRY_INSTRUCTION_LEN,
 585         VM_ENTRY_EXCEPTION_ERROR_CODE,
 586         HOST_FS_BASE,
 587         HOST_GS_BASE,
 588         HOST_FS_SELECTOR,
 589         HOST_GS_SELECTOR
 590 };
 591 static int max_shadow_read_write_fields =
 592         ARRAY_SIZE(shadow_read_write_fields);
 593
 594 static const unsigned short vmcs_field_to_offset_table[] = {
 595         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 596         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 597         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 598         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 599         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 600         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 601         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 602         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 603         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 604         FIELD(HOST_ES_SELECTOR, host_es_selector),
 605         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 606         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 607         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 608         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 609         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 610         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 611         FIELD64(IO_BITMAP_A, io_bitmap_a),
 612         FIELD64(IO_BITMAP_B, io_bitmap_b),
 613         FIELD64(MSR_BITMAP, msr_bitmap),
 614         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 615         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 616         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 617         FIELD64(TSC_OFFSET, tsc_offset),
 618         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 619         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 620         FIELD64(EPT_POINTER, ept_pointer),
 621         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 622         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 623         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 624         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 625         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 626         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 627         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 628         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 629         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 630         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 631         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 632         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 633         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 634         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 635         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 636         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 637         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 638         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 639         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 640         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 641         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 642         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 643         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 644         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 645         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 646         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 647         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 648         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 649         FIELD(TPR_THRESHOLD, tpr_threshold),
 650         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 651         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 652         FIELD(VM_EXIT_REASON, vm_exit_reason),
 653         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 654         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 655         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 656         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 657         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 658         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 659         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 660         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 661         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 662         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 663         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 664         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 665         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 666         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 667         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 668         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 669         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 670         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 671         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 672         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 673         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 674         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 675         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 676         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 677         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 678         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 679         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 680         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 681         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 682         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 683         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 684         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 685         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 686         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 687         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 688         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 689         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 690         FIELD(EXIT_QUALIFICATION, exit_qualification),
 691         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 692         FIELD(GUEST_CR0, guest_cr0),
 693         FIELD(GUEST_CR3, guest_cr3),
 694         FIELD(GUEST_CR4, guest_cr4),
 695         FIELD(GUEST_ES_BASE, guest_es_base),
 696         FIELD(GUEST_CS_BASE, guest_cs_base),
 697         FIELD(GUEST_SS_BASE, guest_ss_base),
 698         FIELD(GUEST_DS_BASE, guest_ds_base),
 699         FIELD(GUEST_FS_BASE, guest_fs_base),
 700         FIELD(GUEST_GS_BASE, guest_gs_base),
 701         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 702         FIELD(GUEST_TR_BASE, guest_tr_base),
 703         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 704         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 705         FIELD(GUEST_DR7, guest_dr7),
 706         FIELD(GUEST_RSP, guest_rsp),
 707         FIELD(GUEST_RIP, guest_rip),
 708         FIELD(GUEST_RFLAGS, guest_rflags),
 709         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 710         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 711         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 712         FIELD(HOST_CR0, host_cr0),
 713         FIELD(HOST_CR3, host_cr3),
 714         FIELD(HOST_CR4, host_cr4),
 715         FIELD(HOST_FS_BASE, host_fs_base),
 716         FIELD(HOST_GS_BASE, host_gs_base),
 717         FIELD(HOST_TR_BASE, host_tr_base),
 718         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 719         FIELD(HOST_IDTR_BASE, host_idtr_base),
 720         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 721         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 722         FIELD(HOST_RSP, host_rsp),
 723         FIELD(HOST_RIP, host_rip),
 724 };
 725
 726 static inline short vmcs_field_to_offset(unsigned long field)
 727 {
 728         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 729
 730         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 731             vmcs_field_to_offset_table[field] == 0)
 732                 return -ENOENT;
 733
 734         return vmcs_field_to_offset_table[field];
 735 }
 736
 737 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 738 {
 739         return to_vmx(vcpu)->nested.current_vmcs12;
 740 }
 741
 742 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 743 {
 744         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 745         if (is_error_page(page))
 746                 return NULL;
 747
 748         return page;
 749 }
 750
 751 static void nested_release_page(struct page *page)
 752 {
 753         kvm_release_page_dirty(page);
 754 }
 755
 756 static void nested_release_page_clean(struct page *page)
 757 {
 758         kvm_release_page_clean(page);
 759 }
 760
 761 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 762 static u64 construct_eptp(unsigned long root_hpa);
 763 static void kvm_cpu_vmxon(u64 addr);
 764 static void kvm_cpu_vmxoff(void);
 765 static bool vmx_mpx_supported(void);
 766 static bool vmx_xsaves_supported(void);
 767 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 768 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 769                             struct kvm_segment *var, int seg);
 770 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 771                             struct kvm_segment *var, int seg);
 772 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 773 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 774 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 775 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 776 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 777 static int alloc_identity_pagetable(struct kvm *kvm);
 778
 779 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 780 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 781 /*
 782  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 783  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 784  */
 785 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 786 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 787
 788 static unsigned long *vmx_io_bitmap_a;
 789 static unsigned long *vmx_io_bitmap_b;
 790 static unsigned long *vmx_msr_bitmap_legacy;
 791 static unsigned long *vmx_msr_bitmap_longmode;
 792 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 793 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 794 static unsigned long *vmx_vmread_bitmap;
 795 static unsigned long *vmx_vmwrite_bitmap;
 796
 797 static bool cpu_has_load_ia32_efer;
 798 static bool cpu_has_load_perf_global_ctrl;
 799
 800 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 801 static DEFINE_SPINLOCK(vmx_vpid_lock);
 802
 803 static struct vmcs_config {
 804         int size;
 805         int order;
 806         u32 revision_id;
 807         u32 pin_based_exec_ctrl;
 808         u32 cpu_based_exec_ctrl;
 809         u32 cpu_based_2nd_exec_ctrl;
 810         u32 vmexit_ctrl;
 811         u32 vmentry_ctrl;
 812 } vmcs_config;
 813
 814 static struct vmx_capability {
 815         u32 ept;
 816         u32 vpid;
 817 } vmx_capability;
 818
 819 #define VMX_SEGMENT_FIELD(seg)                                  \
 820         [VCPU_SREG_##seg] = {                                   \
 821                 .selector = GUEST_##seg##_SELECTOR,             \
 822                 .base = GUEST_##seg##_BASE,                     \
 823                 .limit = GUEST_##seg##_LIMIT,                   \
 824                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 825         }
 826
 827 static const struct kvm_vmx_segment_field {
 828         unsigned selector;
 829         unsigned base;
 830         unsigned limit;
 831         unsigned ar_bytes;
 832 } kvm_vmx_segment_fields[] = {
 833         VMX_SEGMENT_FIELD(CS),
 834         VMX_SEGMENT_FIELD(DS),
 835         VMX_SEGMENT_FIELD(ES),
 836         VMX_SEGMENT_FIELD(FS),
 837         VMX_SEGMENT_FIELD(GS),
 838         VMX_SEGMENT_FIELD(SS),
 839         VMX_SEGMENT_FIELD(TR),
 840         VMX_SEGMENT_FIELD(LDTR),
 841 };
 842
 843 static u64 host_efer;
 844
 845 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 846
 847 /*
 848  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 849  * away by decrementing the array size.
 850  */
 851 static const u32 vmx_msr_index[] = {
 852 #ifdef CONFIG_X86_64
 853         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 854 #endif
 855         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 856 };
 857
 858 static inline bool is_page_fault(u32 intr_info)
 859 {
 860         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 861                              INTR_INFO_VALID_MASK)) ==
 862                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 863 }
 864
 865 static inline bool is_no_device(u32 intr_info)
 866 {
 867         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 868                              INTR_INFO_VALID_MASK)) ==
 869                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 870 }
 871
 872 static inline bool is_invalid_opcode(u32 intr_info)
 873 {
 874         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 875                              INTR_INFO_VALID_MASK)) ==
 876                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 877 }
 878
 879 static inline bool is_external_interrupt(u32 intr_info)
 880 {
 881         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 882                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 883 }
 884
 885 static inline bool is_machine_check(u32 intr_info)
 886 {
 887         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 888                              INTR_INFO_VALID_MASK)) ==
 889                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 890 }
 891
 892 static inline bool cpu_has_vmx_msr_bitmap(void)
 893 {
 894         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 895 }
 896
 897 static inline bool cpu_has_vmx_tpr_shadow(void)
 898 {
 899         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 900 }
 901
 902 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 903 {
 904         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 905 }
 906
 907 static inline bool cpu_has_secondary_exec_ctrls(void)
 908 {
 909         return vmcs_config.cpu_based_exec_ctrl &
 910                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 911 }
 912
 913 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 914 {
 915         return vmcs_config.cpu_based_2nd_exec_ctrl &
 916                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 917 }
 918
 919 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 920 {
 921         return vmcs_config.cpu_based_2nd_exec_ctrl &
 922                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 923 }
 924
 925 static inline bool cpu_has_vmx_apic_register_virt(void)
 926 {
 927         return vmcs_config.cpu_based_2nd_exec_ctrl &
 928                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 929 }
 930
 931 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 932 {
 933         return vmcs_config.cpu_based_2nd_exec_ctrl &
 934                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 935 }
 936
 937 static inline bool cpu_has_vmx_posted_intr(void)
 938 {
 939         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 940 }
 941
 942 static inline bool cpu_has_vmx_apicv(void)
 943 {
 944         return cpu_has_vmx_apic_register_virt() &&
 945                 cpu_has_vmx_virtual_intr_delivery() &&
 946                 cpu_has_vmx_posted_intr();
 947 }
 948
 949 static inline bool cpu_has_vmx_flexpriority(void)
 950 {
 951         return cpu_has_vmx_tpr_shadow() &&
 952                 cpu_has_vmx_virtualize_apic_accesses();
 953 }
 954
 955 static inline bool cpu_has_vmx_ept_execute_only(void)
 956 {
 957         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 958 }
 959
 960 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 961 {
 962         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 963 }
 964
 965 static inline bool cpu_has_vmx_eptp_writeback(void)
 966 {
 967         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 968 }
 969
 970 static inline bool cpu_has_vmx_ept_2m_page(void)
 971 {
 972         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 973 }
 974
 975 static inline bool cpu_has_vmx_ept_1g_page(void)
 976 {
 977         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 978 }
 979
 980 static inline bool cpu_has_vmx_ept_4levels(void)
 981 {
 982         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 983 }
 984
 985 static inline bool cpu_has_vmx_ept_ad_bits(void)
 986 {
 987         return vmx_capability.ept & VMX_EPT_AD_BIT;
 988 }
 989
 990 static inline bool cpu_has_vmx_invept_context(void)
 991 {
 992         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 993 }
 994
 995 static inline bool cpu_has_vmx_invept_global(void)
 996 {
 997         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 998 }
 999
1000 static inline bool cpu_has_vmx_invvpid_single(void)
1001 {
1002         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1003 }
1004
1005 static inline bool cpu_has_vmx_invvpid_global(void)
1006 {
1007         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1008 }
1009
1010 static inline bool cpu_has_vmx_ept(void)
1011 {
1012         return vmcs_config.cpu_based_2nd_exec_ctrl &
1013                 SECONDARY_EXEC_ENABLE_EPT;
1014 }
1015
1016 static inline bool cpu_has_vmx_unrestricted_guest(void)
1017 {
1018         return vmcs_config.cpu_based_2nd_exec_ctrl &
1019                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1020 }
1021
1022 static inline bool cpu_has_vmx_ple(void)
1023 {
1024         return vmcs_config.cpu_based_2nd_exec_ctrl &
1025                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1026 }
1027
1028 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1029 {
1030         return flexpriority_enabled && irqchip_in_kernel(kvm);
1031 }
1032
1033 static inline bool cpu_has_vmx_vpid(void)
1034 {
1035         return vmcs_config.cpu_based_2nd_exec_ctrl &
1036                 SECONDARY_EXEC_ENABLE_VPID;
1037 }
1038
1039 static inline bool cpu_has_vmx_rdtscp(void)
1040 {
1041         return vmcs_config.cpu_based_2nd_exec_ctrl &
1042                 SECONDARY_EXEC_RDTSCP;
1043 }
1044
1045 static inline bool cpu_has_vmx_invpcid(void)
1046 {
1047         return vmcs_config.cpu_based_2nd_exec_ctrl &
1048                 SECONDARY_EXEC_ENABLE_INVPCID;
1049 }
1050
1051 static inline bool cpu_has_virtual_nmis(void)
1052 {
1053         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1054 }
1055
1056 static inline bool cpu_has_vmx_wbinvd_exit(void)
1057 {
1058         return vmcs_config.cpu_based_2nd_exec_ctrl &
1059                 SECONDARY_EXEC_WBINVD_EXITING;
1060 }
1061
1062 static inline bool cpu_has_vmx_shadow_vmcs(void)
1063 {
1064         u64 vmx_msr;
1065         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1066         /* check if the cpu supports writing r/o exit information fields */
1067         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1068                 return false;
1069
1070         return vmcs_config.cpu_based_2nd_exec_ctrl &
1071                 SECONDARY_EXEC_SHADOW_VMCS;
1072 }
1073
1074 static inline bool report_flexpriority(void)
1075 {
1076         return flexpriority_enabled;
1077 }
1078
1079 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1080 {
1081         return vmcs12->cpu_based_vm_exec_control & bit;
1082 }
1083
1084 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1085 {
1086         return (vmcs12->cpu_based_vm_exec_control &
1087                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1088                 (vmcs12->secondary_vm_exec_control & bit);
1089 }
1090
1091 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1092 {
1093         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1094 }
1095
1096 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1097 {
1098         return vmcs12->pin_based_vm_exec_control &
1099                 PIN_BASED_VMX_PREEMPTION_TIMER;
1100 }
1101
1102 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1103 {
1104         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1105 }
1106
1107 static inline bool is_exception(u32 intr_info)
1108 {
1109         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1110                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1111 }
1112
1113 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1114                               u32 exit_intr_info,
1115                               unsigned long exit_qualification);
1116 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1117                         struct vmcs12 *vmcs12,
1118                         u32 reason, unsigned long qualification);
1119
1120 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1121 {
1122         int i;
1123
1124         for (i = 0; i < vmx->nmsrs; ++i)
1125                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1126                         return i;
1127         return -1;
1128 }
1129
1130 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1131 {
1132     struct {
1133         u64 vpid : 16;
1134         u64 rsvd : 48;
1135         u64 gva;
1136     } operand = { vpid, 0, gva };
1137
1138     asm volatile (__ex(ASM_VMX_INVVPID)
1139                   /* CF==1 or ZF==1 --> rc = -1 */
1140                   "; ja 1f ; ud2 ; 1:"
1141                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1142 }
1143
1144 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1145 {
1146         struct {
1147                 u64 eptp, gpa;
1148         } operand = {eptp, gpa};
1149
1150         asm volatile (__ex(ASM_VMX_INVEPT)
1151                         /* CF==1 or ZF==1 --> rc = -1 */
1152                         "; ja 1f ; ud2 ; 1:\n"
1153                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1154 }
1155
1156 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1157 {
1158         int i;
1159
1160         i = __find_msr_index(vmx, msr);
1161         if (i >= 0)
1162                 return &vmx->guest_msrs[i];
1163         return NULL;
1164 }
1165
1166 static void vmcs_clear(struct vmcs *vmcs)
1167 {
1168         u64 phys_addr = __pa(vmcs);
1169         u8 error;
1170
1171         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1172                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1173                       : "cc", "memory");
1174         if (error)
1175                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1176                        vmcs, phys_addr);
1177 }
1178
1179 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1180 {
1181         vmcs_clear(loaded_vmcs->vmcs);
1182         loaded_vmcs->cpu = -1;
1183         loaded_vmcs->launched = 0;
1184 }
1185
1186 static void vmcs_load(struct vmcs *vmcs)
1187 {
1188         u64 phys_addr = __pa(vmcs);
1189         u8 error;
1190
1191         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1192                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1193                         : "cc", "memory");
1194         if (error)
1195                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1196                        vmcs, phys_addr);
1197 }
1198
1199 #ifdef CONFIG_KEXEC
1200 /*
1201  * This bitmap is used to indicate whether the vmclear
1202  * operation is enabled on all cpus. All disabled by
1203  * default.
1204  */
1205 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1206
1207 static inline void crash_enable_local_vmclear(int cpu)
1208 {
1209         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1210 }
1211
1212 static inline void crash_disable_local_vmclear(int cpu)
1213 {
1214         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1215 }
1216
1217 static inline int crash_local_vmclear_enabled(int cpu)
1218 {
1219         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1220 }
1221
1222 static void crash_vmclear_local_loaded_vmcss(void)
1223 {
1224         int cpu = raw_smp_processor_id();
1225         struct loaded_vmcs *v;
1226
1227         if (!crash_local_vmclear_enabled(cpu))
1228                 return;
1229
1230         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1231                             loaded_vmcss_on_cpu_link)
1232                 vmcs_clear(v->vmcs);
1233 }
1234 #else
1235 static inline void crash_enable_local_vmclear(int cpu) { }
1236 static inline void crash_disable_local_vmclear(int cpu) { }
1237 #endif /* CONFIG_KEXEC */
1238
1239 static void __loaded_vmcs_clear(void *arg)
1240 {
1241         struct loaded_vmcs *loaded_vmcs = arg;
1242         int cpu = raw_smp_processor_id();
1243
1244         if (loaded_vmcs->cpu != cpu)
1245                 return; /* vcpu migration can race with cpu offline */
1246         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1247                 per_cpu(current_vmcs, cpu) = NULL;
1248         crash_disable_local_vmclear(cpu);
1249         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1250
1251         /*
1252          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1253          * is before setting loaded_vmcs->vcpu to -1 which is done in
1254          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1255          * then adds the vmcs into percpu list before it is deleted.
1256          */
1257         smp_wmb();
1258
1259         loaded_vmcs_init(loaded_vmcs);
1260         crash_enable_local_vmclear(cpu);
1261 }
1262
1263 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1264 {
1265         int cpu = loaded_vmcs->cpu;
1266
1267         if (cpu != -1)
1268                 smp_call_function_single(cpu,
1269                          __loaded_vmcs_clear, loaded_vmcs, 1);
1270 }
1271
1272 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1273 {
1274         if (vmx->vpid == 0)
1275                 return;
1276
1277         if (cpu_has_vmx_invvpid_single())
1278                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1279 }
1280
1281 static inline void vpid_sync_vcpu_global(void)
1282 {
1283         if (cpu_has_vmx_invvpid_global())
1284                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1285 }
1286
1287 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1288 {
1289         if (cpu_has_vmx_invvpid_single())
1290                 vpid_sync_vcpu_single(vmx);
1291         else
1292                 vpid_sync_vcpu_global();
1293 }
1294
1295 static inline void ept_sync_global(void)
1296 {
1297         if (cpu_has_vmx_invept_global())
1298                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1299 }
1300
1301 static inline void ept_sync_context(u64 eptp)
1302 {
1303         if (enable_ept) {
1304                 if (cpu_has_vmx_invept_context())
1305                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1306                 else
1307                         ept_sync_global();
1308         }
1309 }
1310
1311 static __always_inline unsigned long vmcs_readl(unsigned long field)
1312 {
1313         unsigned long value;
1314
1315         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1316                       : "=a"(value) : "d"(field) : "cc");
1317         return value;
1318 }
1319
1320 static __always_inline u16 vmcs_read16(unsigned long field)
1321 {
1322         return vmcs_readl(field);
1323 }
1324
1325 static __always_inline u32 vmcs_read32(unsigned long field)
1326 {
1327         return vmcs_readl(field);
1328 }
1329
1330 static __always_inline u64 vmcs_read64(unsigned long field)
1331 {
1332 #ifdef CONFIG_X86_64
1333         return vmcs_readl(field);
1334 #else
1335         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1336 #endif
1337 }
1338
1339 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1340 {
1341         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1342                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1343         dump_stack();
1344 }
1345
1346 static void vmcs_writel(unsigned long field, unsigned long value)
1347 {
1348         u8 error;
1349
1350         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1351                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1352         if (unlikely(error))
1353                 vmwrite_error(field, value);
1354 }
1355
1356 static void vmcs_write16(unsigned long field, u16 value)
1357 {
1358         vmcs_writel(field, value);
1359 }
1360
1361 static void vmcs_write32(unsigned long field, u32 value)
1362 {
1363         vmcs_writel(field, value);
1364 }
1365
1366 static void vmcs_write64(unsigned long field, u64 value)
1367 {
1368         vmcs_writel(field, value);
1369 #ifndef CONFIG_X86_64
1370         asm volatile ("");
1371         vmcs_writel(field+1, value >> 32);
1372 #endif
1373 }
1374
1375 static void vmcs_clear_bits(unsigned long field, u32 mask)
1376 {
1377         vmcs_writel(field, vmcs_readl(field) & ~mask);
1378 }
1379
1380 static void vmcs_set_bits(unsigned long field, u32 mask)
1381 {
1382         vmcs_writel(field, vmcs_readl(field) | mask);
1383 }
1384
1385 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1386 {
1387         vmcs_write32(VM_ENTRY_CONTROLS, val);
1388         vmx->vm_entry_controls_shadow = val;
1389 }
1390
1391 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1392 {
1393         if (vmx->vm_entry_controls_shadow != val)
1394                 vm_entry_controls_init(vmx, val);
1395 }
1396
1397 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1398 {
1399         return vmx->vm_entry_controls_shadow;
1400 }
1401
1402
1403 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1406 }
1407
1408 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1409 {
1410         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1411 }
1412
1413 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1414 {
1415         vmcs_write32(VM_EXIT_CONTROLS, val);
1416         vmx->vm_exit_controls_shadow = val;
1417 }
1418
1419 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1420 {
1421         if (vmx->vm_exit_controls_shadow != val)
1422                 vm_exit_controls_init(vmx, val);
1423 }
1424
1425 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1426 {
1427         return vmx->vm_exit_controls_shadow;
1428 }
1429
1430
1431 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1432 {
1433         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1434 }
1435
1436 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1437 {
1438         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1439 }
1440
1441 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1442 {
1443         vmx->segment_cache.bitmask = 0;
1444 }
1445
1446 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1447                                        unsigned field)
1448 {
1449         bool ret;
1450         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1451
1452         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1453                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1454                 vmx->segment_cache.bitmask = 0;
1455         }
1456         ret = vmx->segment_cache.bitmask & mask;
1457         vmx->segment_cache.bitmask |= mask;
1458         return ret;
1459 }
1460
1461 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1462 {
1463         u16 *p = &vmx->segment_cache.seg[seg].selector;
1464
1465         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1466                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1467         return *p;
1468 }
1469
1470 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1471 {
1472         ulong *p = &vmx->segment_cache.seg[seg].base;
1473
1474         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1475                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1476         return *p;
1477 }
1478
1479 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1480 {
1481         u32 *p = &vmx->segment_cache.seg[seg].limit;
1482
1483         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1484                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1485         return *p;
1486 }
1487
1488 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1489 {
1490         u32 *p = &vmx->segment_cache.seg[seg].ar;
1491
1492         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1493                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1494         return *p;
1495 }
1496
1497 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1498 {
1499         u32 eb;
1500
1501         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1502              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1503         if ((vcpu->guest_debug &
1504              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1505             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1506                 eb |= 1u << BP_VECTOR;
1507         if (to_vmx(vcpu)->rmode.vm86_active)
1508                 eb = ~0;
1509         if (enable_ept)
1510                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1511         if (vcpu->fpu_active)
1512                 eb &= ~(1u << NM_VECTOR);
1513
1514         /* When we are running a nested L2 guest and L1 specified for it a
1515          * certain exception bitmap, we must trap the same exceptions and pass
1516          * them to L1. When running L2, we will only handle the exceptions
1517          * specified above if L1 did not want them.
1518          */
1519         if (is_guest_mode(vcpu))
1520                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1521
1522         vmcs_write32(EXCEPTION_BITMAP, eb);
1523 }
1524
1525 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1526                 unsigned long entry, unsigned long exit)
1527 {
1528         vm_entry_controls_clearbit(vmx, entry);
1529         vm_exit_controls_clearbit(vmx, exit);
1530 }
1531
1532 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1533 {
1534         unsigned i;
1535         struct msr_autoload *m = &vmx->msr_autoload;
1536
1537         switch (msr) {
1538         case MSR_EFER:
1539                 if (cpu_has_load_ia32_efer) {
1540                         clear_atomic_switch_msr_special(vmx,
1541                                         VM_ENTRY_LOAD_IA32_EFER,
1542                                         VM_EXIT_LOAD_IA32_EFER);
1543                         return;
1544                 }
1545                 break;
1546         case MSR_CORE_PERF_GLOBAL_CTRL:
1547                 if (cpu_has_load_perf_global_ctrl) {
1548                         clear_atomic_switch_msr_special(vmx,
1549                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1550                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1551                         return;
1552                 }
1553                 break;
1554         }
1555
1556         for (i = 0; i < m->nr; ++i)
1557                 if (m->guest[i].index == msr)
1558                         break;
1559
1560         if (i == m->nr)
1561                 return;
1562         --m->nr;
1563         m->guest[i] = m->guest[m->nr];
1564         m->host[i] = m->host[m->nr];
1565         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1566         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1567 }
1568
1569 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1570                 unsigned long entry, unsigned long exit,
1571                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1572                 u64 guest_val, u64 host_val)
1573 {
1574         vmcs_write64(guest_val_vmcs, guest_val);
1575         vmcs_write64(host_val_vmcs, host_val);
1576         vm_entry_controls_setbit(vmx, entry);
1577         vm_exit_controls_setbit(vmx, exit);
1578 }
1579
1580 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1581                                   u64 guest_val, u64 host_val)
1582 {
1583         unsigned i;
1584         struct msr_autoload *m = &vmx->msr_autoload;
1585
1586         switch (msr) {
1587         case MSR_EFER:
1588                 if (cpu_has_load_ia32_efer) {
1589                         add_atomic_switch_msr_special(vmx,
1590                                         VM_ENTRY_LOAD_IA32_EFER,
1591                                         VM_EXIT_LOAD_IA32_EFER,
1592                                         GUEST_IA32_EFER,
1593                                         HOST_IA32_EFER,
1594                                         guest_val, host_val);
1595                         return;
1596                 }
1597                 break;
1598         case MSR_CORE_PERF_GLOBAL_CTRL:
1599                 if (cpu_has_load_perf_global_ctrl) {
1600                         add_atomic_switch_msr_special(vmx,
1601                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1602                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1603                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1604                                         HOST_IA32_PERF_GLOBAL_CTRL,
1605                                         guest_val, host_val);
1606                         return;
1607                 }
1608                 break;
1609         }
1610
1611         for (i = 0; i < m->nr; ++i)
1612                 if (m->guest[i].index == msr)
1613                         break;
1614
1615         if (i == NR_AUTOLOAD_MSRS) {
1616                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1617                                 "Can't add msr %x\n", msr);
1618                 return;
1619         } else if (i == m->nr) {
1620                 ++m->nr;
1621                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1622                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1623         }
1624
1625         m->guest[i].index = msr;
1626         m->guest[i].value = guest_val;
1627         m->host[i].index = msr;
1628         m->host[i].value = host_val;
1629 }
1630
1631 static void reload_tss(void)
1632 {
1633         /*
1634          * VT restores TR but not its size.  Useless.
1635          */
1636         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1637         struct desc_struct *descs;
1638
1639         descs = (void *)gdt->address;
1640         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1641         load_TR_desc();
1642 }
1643
1644 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1645 {
1646         u64 guest_efer;
1647         u64 ignore_bits;
1648
1649         guest_efer = vmx->vcpu.arch.efer;
1650
1651         /*
1652          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1653          * outside long mode
1654          */
1655         ignore_bits = EFER_NX | EFER_SCE;
1656 #ifdef CONFIG_X86_64
1657         ignore_bits |= EFER_LMA | EFER_LME;
1658         /* SCE is meaningful only in long mode on Intel */
1659         if (guest_efer & EFER_LMA)
1660                 ignore_bits &= ~(u64)EFER_SCE;
1661 #endif
1662         guest_efer &= ~ignore_bits;
1663         guest_efer |= host_efer & ignore_bits;
1664         vmx->guest_msrs[efer_offset].data = guest_efer;
1665         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1666
1667         clear_atomic_switch_msr(vmx, MSR_EFER);
1668
1669         /*
1670          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1671          * On CPUs that support "load IA32_EFER", always switch EFER
1672          * atomically, since it's faster than switching it manually.
1673          */
1674         if (cpu_has_load_ia32_efer ||
1675             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1676                 guest_efer = vmx->vcpu.arch.efer;
1677                 if (!(guest_efer & EFER_LMA))
1678                         guest_efer &= ~EFER_LME;
1679                 if (guest_efer != host_efer)
1680                         add_atomic_switch_msr(vmx, MSR_EFER,
1681                                               guest_efer, host_efer);
1682                 return false;
1683         }
1684
1685         return true;
1686 }
1687
1688 static unsigned long segment_base(u16 selector)
1689 {
1690         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1691         struct desc_struct *d;
1692         unsigned long table_base;
1693         unsigned long v;
1694
1695         if (!(selector & ~3))
1696                 return 0;
1697
1698         table_base = gdt->address;
1699
1700         if (selector & 4) {           /* from ldt */
1701                 u16 ldt_selector = kvm_read_ldt();
1702
1703                 if (!(ldt_selector & ~3))
1704                         return 0;
1705
1706                 table_base = segment_base(ldt_selector);
1707         }
1708         d = (struct desc_struct *)(table_base + (selector & ~7));
1709         v = get_desc_base(d);
1710 #ifdef CONFIG_X86_64
1711        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1712                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1713 #endif
1714         return v;
1715 }
1716
1717 static inline unsigned long kvm_read_tr_base(void)
1718 {
1719         u16 tr;
1720         asm("str %0" : "=g"(tr));
1721         return segment_base(tr);
1722 }
1723
1724 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1725 {
1726         struct vcpu_vmx *vmx = to_vmx(vcpu);
1727         int i;
1728
1729         if (vmx->host_state.loaded)
1730                 return;
1731
1732         vmx->host_state.loaded = 1;
1733         /*
1734          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1735          * allow segment selectors with cpl > 0 or ti == 1.
1736          */
1737         vmx->host_state.ldt_sel = kvm_read_ldt();
1738         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1739         savesegment(fs, vmx->host_state.fs_sel);
1740         if (!(vmx->host_state.fs_sel & 7)) {
1741                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1742                 vmx->host_state.fs_reload_needed = 0;
1743         } else {
1744                 vmcs_write16(HOST_FS_SELECTOR, 0);
1745                 vmx->host_state.fs_reload_needed = 1;
1746         }
1747         savesegment(gs, vmx->host_state.gs_sel);
1748         if (!(vmx->host_state.gs_sel & 7))
1749                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1750         else {
1751                 vmcs_write16(HOST_GS_SELECTOR, 0);
1752                 vmx->host_state.gs_ldt_reload_needed = 1;
1753         }
1754
1755 #ifdef CONFIG_X86_64
1756         savesegment(ds, vmx->host_state.ds_sel);
1757         savesegment(es, vmx->host_state.es_sel);
1758 #endif
1759
1760 #ifdef CONFIG_X86_64
1761         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1762         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1763 #else
1764         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1765         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1766 #endif
1767
1768 #ifdef CONFIG_X86_64
1769         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770         if (is_long_mode(&vmx->vcpu))
1771                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1772 #endif
1773         if (boot_cpu_has(X86_FEATURE_MPX))
1774                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1775         for (i = 0; i < vmx->save_nmsrs; ++i)
1776                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1777                                    vmx->guest_msrs[i].data,
1778                                    vmx->guest_msrs[i].mask);
1779 }
1780
1781 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1782 {
1783         if (!vmx->host_state.loaded)
1784                 return;
1785
1786         ++vmx->vcpu.stat.host_state_reload;
1787         vmx->host_state.loaded = 0;
1788 #ifdef CONFIG_X86_64
1789         if (is_long_mode(&vmx->vcpu))
1790                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1791 #endif
1792         if (vmx->host_state.gs_ldt_reload_needed) {
1793                 kvm_load_ldt(vmx->host_state.ldt_sel);
1794 #ifdef CONFIG_X86_64
1795                 load_gs_index(vmx->host_state.gs_sel);
1796 #else
1797                 loadsegment(gs, vmx->host_state.gs_sel);
1798 #endif
1799         }
1800         if (vmx->host_state.fs_reload_needed)
1801                 loadsegment(fs, vmx->host_state.fs_sel);
1802 #ifdef CONFIG_X86_64
1803         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1804                 loadsegment(ds, vmx->host_state.ds_sel);
1805                 loadsegment(es, vmx->host_state.es_sel);
1806         }
1807 #endif
1808         reload_tss();
1809 #ifdef CONFIG_X86_64
1810         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1811 #endif
1812         if (vmx->host_state.msr_host_bndcfgs)
1813                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1814         /*
1815          * If the FPU is not active (through the host task or
1816          * the guest vcpu), then restore the cr0.TS bit.
1817          */
1818         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1819                 stts();
1820         load_gdt(this_cpu_ptr(&host_gdt));
1821 }
1822
1823 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1824 {
1825         preempt_disable();
1826         __vmx_load_host_state(vmx);
1827         preempt_enable();
1828 }
1829
1830 /*
1831  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1832  * vcpu mutex is already taken.
1833  */
1834 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1835 {
1836         struct vcpu_vmx *vmx = to_vmx(vcpu);
1837         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1838
1839         if (!vmm_exclusive)
1840                 kvm_cpu_vmxon(phys_addr);
1841         else if (vmx->loaded_vmcs->cpu != cpu)
1842                 loaded_vmcs_clear(vmx->loaded_vmcs);
1843
1844         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1845                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1846                 vmcs_load(vmx->loaded_vmcs->vmcs);
1847         }
1848
1849         if (vmx->loaded_vmcs->cpu != cpu) {
1850                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1851                 unsigned long sysenter_esp;
1852
1853                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1854                 local_irq_disable();
1855                 crash_disable_local_vmclear(cpu);
1856
1857                 /*
1858                  * Read loaded_vmcs->cpu should be before fetching
1859                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1860                  * See the comments in __loaded_vmcs_clear().
1861                  */
1862                 smp_rmb();
1863
1864                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1865                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1866                 crash_enable_local_vmclear(cpu);
1867                 local_irq_enable();
1868
1869                 /*
1870                  * Linux uses per-cpu TSS and GDT, so set these when switching
1871                  * processors.
1872                  */
1873                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1874                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1875
1876                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1877                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1878                 vmx->loaded_vmcs->cpu = cpu;
1879         }
1880 }
1881
1882 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1883 {
1884         __vmx_load_host_state(to_vmx(vcpu));
1885         if (!vmm_exclusive) {
1886                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1887                 vcpu->cpu = -1;
1888                 kvm_cpu_vmxoff();
1889         }
1890 }
1891
1892 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1893 {
1894         ulong cr0;
1895
1896         if (vcpu->fpu_active)
1897                 return;
1898         vcpu->fpu_active = 1;
1899         cr0 = vmcs_readl(GUEST_CR0);
1900         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1901         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1902         vmcs_writel(GUEST_CR0, cr0);
1903         update_exception_bitmap(vcpu);
1904         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1905         if (is_guest_mode(vcpu))
1906                 vcpu->arch.cr0_guest_owned_bits &=
1907                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1908         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1909 }
1910
1911 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1912
1913 /*
1914  * Return the cr0 value that a nested guest would read. This is a combination
1915  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1916  * its hypervisor (cr0_read_shadow).
1917  */
1918 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1919 {
1920         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1921                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1922 }
1923 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1924 {
1925         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1926                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1927 }
1928
1929 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1930 {
1931         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1932          * set this *before* calling this function.
1933          */
1934         vmx_decache_cr0_guest_bits(vcpu);
1935         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1936         update_exception_bitmap(vcpu);
1937         vcpu->arch.cr0_guest_owned_bits = 0;
1938         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1939         if (is_guest_mode(vcpu)) {
1940                 /*
1941                  * L1's specified read shadow might not contain the TS bit,
1942                  * so now that we turned on shadowing of this bit, we need to
1943                  * set this bit of the shadow. Like in nested_vmx_run we need
1944                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1945                  * up-to-date here because we just decached cr0.TS (and we'll
1946                  * only update vmcs12->guest_cr0 on nested exit).
1947                  */
1948                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1949                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1950                         (vcpu->arch.cr0 & X86_CR0_TS);
1951                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1952         } else
1953                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1954 }
1955
1956 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1957 {
1958         unsigned long rflags, save_rflags;
1959
1960         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1961                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1962                 rflags = vmcs_readl(GUEST_RFLAGS);
1963                 if (to_vmx(vcpu)->rmode.vm86_active) {
1964                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1965                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1966                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1967                 }
1968                 to_vmx(vcpu)->rflags = rflags;
1969         }
1970         return to_vmx(vcpu)->rflags;
1971 }
1972
1973 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1974 {
1975         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1976         to_vmx(vcpu)->rflags = rflags;
1977         if (to_vmx(vcpu)->rmode.vm86_active) {
1978                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1979                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1980         }
1981         vmcs_writel(GUEST_RFLAGS, rflags);
1982 }
1983
1984 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1985 {
1986         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1987         int ret = 0;
1988
1989         if (interruptibility & GUEST_INTR_STATE_STI)
1990                 ret |= KVM_X86_SHADOW_INT_STI;
1991         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1992                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1993
1994         return ret;
1995 }
1996
1997 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1998 {
1999         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2000         u32 interruptibility = interruptibility_old;
2001
2002         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2003
2004         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2005                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2006         else if (mask & KVM_X86_SHADOW_INT_STI)
2007                 interruptibility |= GUEST_INTR_STATE_STI;
2008
2009         if ((interruptibility != interruptibility_old))
2010                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2011 }
2012
2013 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2014 {
2015         unsigned long rip;
2016
2017         rip = kvm_rip_read(vcpu);
2018         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2019         kvm_rip_write(vcpu, rip);
2020
2021         /* skipping an emulated instruction also counts */
2022         vmx_set_interrupt_shadow(vcpu, 0);
2023 }
2024
2025 /*
2026  * KVM wants to inject page-faults which it got to the guest. This function
2027  * checks whether in a nested guest, we need to inject them to L1 or L2.
2028  */
2029 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2030 {
2031         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2032
2033         if (!(vmcs12->exception_bitmap & (1u << nr)))
2034                 return 0;
2035
2036         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2037                           vmcs_read32(VM_EXIT_INTR_INFO),
2038                           vmcs_readl(EXIT_QUALIFICATION));
2039         return 1;
2040 }
2041
2042 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2043                                 bool has_error_code, u32 error_code,
2044                                 bool reinject)
2045 {
2046         struct vcpu_vmx *vmx = to_vmx(vcpu);
2047         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2048
2049         if (!reinject && is_guest_mode(vcpu) &&
2050             nested_vmx_check_exception(vcpu, nr))
2051                 return;
2052
2053         if (has_error_code) {
2054                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2055                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2056         }
2057
2058         if (vmx->rmode.vm86_active) {
2059                 int inc_eip = 0;
2060                 if (kvm_exception_is_soft(nr))
2061                         inc_eip = vcpu->arch.event_exit_inst_len;
2062                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2063                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2064                 return;
2065         }
2066
2067         if (kvm_exception_is_soft(nr)) {
2068                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2069                              vmx->vcpu.arch.event_exit_inst_len);
2070                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2071         } else
2072                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2073
2074         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2075 }
2076
2077 static bool vmx_rdtscp_supported(void)
2078 {
2079         return cpu_has_vmx_rdtscp();
2080 }
2081
2082 static bool vmx_invpcid_supported(void)
2083 {
2084         return cpu_has_vmx_invpcid() && enable_ept;
2085 }
2086
2087 /*
2088  * Swap MSR entry in host/guest MSR entry array.
2089  */
2090 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2091 {
2092         struct shared_msr_entry tmp;
2093
2094         tmp = vmx->guest_msrs[to];
2095         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2096         vmx->guest_msrs[from] = tmp;
2097 }
2098
2099 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2100 {
2101         unsigned long *msr_bitmap;
2102
2103         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2104                 if (is_long_mode(vcpu))
2105                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2106                 else
2107                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2108         } else {
2109                 if (is_long_mode(vcpu))
2110                         msr_bitmap = vmx_msr_bitmap_longmode;
2111                 else
2112                         msr_bitmap = vmx_msr_bitmap_legacy;
2113         }
2114
2115         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2116 }
2117
2118 /*
2119  * Set up the vmcs to automatically save and restore system
2120  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2121  * mode, as fiddling with msrs is very expensive.
2122  */
2123 static void setup_msrs(struct vcpu_vmx *vmx)
2124 {
2125         int save_nmsrs, index;
2126
2127         save_nmsrs = 0;
2128 #ifdef CONFIG_X86_64
2129         if (is_long_mode(&vmx->vcpu)) {
2130                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2131                 if (index >= 0)
2132                         move_msr_up(vmx, index, save_nmsrs++);
2133                 index = __find_msr_index(vmx, MSR_LSTAR);
2134                 if (index >= 0)
2135                         move_msr_up(vmx, index, save_nmsrs++);
2136                 index = __find_msr_index(vmx, MSR_CSTAR);
2137                 if (index >= 0)
2138                         move_msr_up(vmx, index, save_nmsrs++);
2139                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2140                 if (index >= 0 && vmx->rdtscp_enabled)
2141                         move_msr_up(vmx, index, save_nmsrs++);
2142                 /*
2143                  * MSR_STAR is only needed on long mode guests, and only
2144                  * if efer.sce is enabled.
2145                  */
2146                 index = __find_msr_index(vmx, MSR_STAR);
2147                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2148                         move_msr_up(vmx, index, save_nmsrs++);
2149         }
2150 #endif
2151         index = __find_msr_index(vmx, MSR_EFER);
2152         if (index >= 0 && update_transition_efer(vmx, index))
2153                 move_msr_up(vmx, index, save_nmsrs++);
2154
2155         vmx->save_nmsrs = save_nmsrs;
2156
2157         if (cpu_has_vmx_msr_bitmap())
2158                 vmx_set_msr_bitmap(&vmx->vcpu);
2159 }
2160
2161 /*
2162  * reads and returns guest's timestamp counter "register"
2163  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2164  */
2165 static u64 guest_read_tsc(void)
2166 {
2167         u64 host_tsc, tsc_offset;
2168
2169         rdtscll(host_tsc);
2170         tsc_offset = vmcs_read64(TSC_OFFSET);
2171         return host_tsc + tsc_offset;
2172 }
2173
2174 /*
2175  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2176  * counter, even if a nested guest (L2) is currently running.
2177  */
2178 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2179 {
2180         u64 tsc_offset;
2181
2182         tsc_offset = is_guest_mode(vcpu) ?
2183                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2184                 vmcs_read64(TSC_OFFSET);
2185         return host_tsc + tsc_offset;
2186 }
2187
2188 /*
2189  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2190  * software catchup for faster rates on slower CPUs.
2191  */
2192 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2193 {
2194         if (!scale)
2195                 return;
2196
2197         if (user_tsc_khz > tsc_khz) {
2198                 vcpu->arch.tsc_catchup = 1;
2199                 vcpu->arch.tsc_always_catchup = 1;
2200         } else
2201                 WARN(1, "user requested TSC rate below hardware speed\n");
2202 }
2203
2204 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2205 {
2206         return vmcs_read64(TSC_OFFSET);
2207 }
2208
2209 /*
2210  * writes 'offset' into guest's timestamp counter offset register
2211  */
2212 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2213 {
2214         if (is_guest_mode(vcpu)) {
2215                 /*
2216                  * We're here if L1 chose not to trap WRMSR to TSC. According
2217                  * to the spec, this should set L1's TSC; The offset that L1
2218                  * set for L2 remains unchanged, and still needs to be added
2219                  * to the newly set TSC to get L2's TSC.
2220                  */
2221                 struct vmcs12 *vmcs12;
2222                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2223                 /* recalculate vmcs02.TSC_OFFSET: */
2224                 vmcs12 = get_vmcs12(vcpu);
2225                 vmcs_write64(TSC_OFFSET, offset +
2226                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2227                          vmcs12->tsc_offset : 0));
2228         } else {
2229                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2230                                            vmcs_read64(TSC_OFFSET), offset);
2231                 vmcs_write64(TSC_OFFSET, offset);
2232         }
2233 }
2234
2235 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2236 {
2237         u64 offset = vmcs_read64(TSC_OFFSET);
2238
2239         vmcs_write64(TSC_OFFSET, offset + adjustment);
2240         if (is_guest_mode(vcpu)) {
2241                 /* Even when running L2, the adjustment needs to apply to L1 */
2242                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2243         } else
2244                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2245                                            offset + adjustment);
2246 }
2247
2248 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2249 {
2250         return target_tsc - native_read_tsc();
2251 }
2252
2253 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2254 {
2255         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2256         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2257 }
2258
2259 /*
2260  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2261  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2262  * all guests if the "nested" module option is off, and can also be disabled
2263  * for a single guest by disabling its VMX cpuid bit.
2264  */
2265 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2266 {
2267         return nested && guest_cpuid_has_vmx(vcpu);
2268 }
2269
2270 /*
2271  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2272  * returned for the various VMX controls MSRs when nested VMX is enabled.
2273  * The same values should also be used to verify that vmcs12 control fields are
2274  * valid during nested entry from L1 to L2.
2275  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2276  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2277  * bit in the high half is on if the corresponding bit in the control field
2278  * may be on. See also vmx_control_verify().
2279  * TODO: allow these variables to be modified (downgraded) by module options
2280  * or other means.
2281  */
2282 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2283 static u32 nested_vmx_true_procbased_ctls_low;
2284 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2285 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2286 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2287 static u32 nested_vmx_true_exit_ctls_low;
2288 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2289 static u32 nested_vmx_true_entry_ctls_low;
2290 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2291 static u32 nested_vmx_ept_caps;
2292 static __init void nested_vmx_setup_ctls_msrs(void)
2293 {
2294         /*
2295          * Note that as a general rule, the high half of the MSRs (bits in
2296          * the control fields which may be 1) should be initialized by the
2297          * intersection of the underlying hardware's MSR (i.e., features which
2298          * can be supported) and the list of features we want to expose -
2299          * because they are known to be properly supported in our code.
2300          * Also, usually, the low half of the MSRs (bits which must be 1) can
2301          * be set to 0, meaning that L1 may turn off any of these bits. The
2302          * reason is that if one of these bits is necessary, it will appear
2303          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2304          * fields of vmcs01 and vmcs02, will turn these bits off - and
2305          * nested_vmx_exit_handled() will not pass related exits to L1.
2306          * These rules have exceptions below.
2307          */
2308
2309         /* pin-based controls */
2310         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2311               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2312         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2313         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2314                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2315         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2316                 PIN_BASED_VMX_PREEMPTION_TIMER;
2317
2318         /* exit controls */
2319         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2320                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2321         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2322
2323         nested_vmx_exit_ctls_high &=
2324 #ifdef CONFIG_X86_64
2325                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2326 #endif
2327                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2328         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2329                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2330                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2331
2332         if (vmx_mpx_supported())
2333                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2334
2335         /* We support free control of debug control saving. */
2336         nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2337                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2338
2339         /* entry controls */
2340         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2341                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2342         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2343         nested_vmx_entry_ctls_high &=
2344 #ifdef CONFIG_X86_64
2345                 VM_ENTRY_IA32E_MODE |
2346 #endif
2347                 VM_ENTRY_LOAD_IA32_PAT;
2348         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2349                                        VM_ENTRY_LOAD_IA32_EFER);
2350         if (vmx_mpx_supported())
2351                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2352
2353         /* We support free control of debug control loading. */
2354         nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2355                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2356
2357         /* cpu-based controls */
2358         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2359                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2360         nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2361         nested_vmx_procbased_ctls_high &=
2362                 CPU_BASED_VIRTUAL_INTR_PENDING |
2363                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2364                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2365                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2366                 CPU_BASED_CR3_STORE_EXITING |
2367 #ifdef CONFIG_X86_64
2368                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2369 #endif
2370                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2371                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2372                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2373                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2374                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2375         /*
2376          * We can allow some features even when not supported by the
2377          * hardware. For example, L1 can specify an MSR bitmap - and we
2378          * can use it to avoid exits to L1 - even when L0 runs L2
2379          * without MSR bitmaps.
2380          */
2381         nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2382                 CPU_BASED_USE_MSR_BITMAPS;
2383
2384         /* We support free control of CR3 access interception. */
2385         nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2386                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2387
2388         /* secondary cpu-based controls */
2389         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2390                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2391         nested_vmx_secondary_ctls_low = 0;
2392         nested_vmx_secondary_ctls_high &=
2393                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2394                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2395                 SECONDARY_EXEC_WBINVD_EXITING;
2396
2397         if (enable_ept) {
2398                 /* nested EPT: emulate EPT also to L1 */
2399                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2400                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2401                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2402                          VMX_EPT_INVEPT_BIT;
2403                 nested_vmx_ept_caps &= vmx_capability.ept;
2404                 /*
2405                  * For nested guests, we don't do anything specific
2406                  * for single context invalidation. Hence, only advertise
2407                  * support for global context invalidation.
2408                  */
2409                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2410         } else
2411                 nested_vmx_ept_caps = 0;
2412
2413         /* miscellaneous data */
2414         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2415         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2416         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2417                 VMX_MISC_ACTIVITY_HLT;
2418         nested_vmx_misc_high = 0;
2419 }
2420
2421 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2422 {
2423         /*
2424          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2425          */
2426         return ((control & high) | low) == control;
2427 }
2428
2429 static inline u64 vmx_control_msr(u32 low, u32 high)
2430 {
2431         return low | ((u64)high << 32);
2432 }
2433
2434 /* Returns 0 on success, non-0 otherwise. */
2435 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2436 {
2437         switch (msr_index) {
2438         case MSR_IA32_VMX_BASIC:
2439                 /*
2440                  * This MSR reports some information about VMX support. We
2441                  * should return information about the VMX we emulate for the
2442                  * guest, and the VMCS structure we give it - not about the
2443                  * VMX support of the underlying hardware.
2444                  */
2445                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2446                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2447                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2448                 break;
2449         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2450         case MSR_IA32_VMX_PINBASED_CTLS:
2451                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2452                                         nested_vmx_pinbased_ctls_high);
2453                 break;
2454         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2455                 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2456                                         nested_vmx_procbased_ctls_high);
2457                 break;
2458         case MSR_IA32_VMX_PROCBASED_CTLS:
2459                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2460                                         nested_vmx_procbased_ctls_high);
2461                 break;
2462         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2463                 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2464                                         nested_vmx_exit_ctls_high);
2465                 break;
2466         case MSR_IA32_VMX_EXIT_CTLS:
2467                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2468                                         nested_vmx_exit_ctls_high);
2469                 break;
2470         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2471                 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2472                                         nested_vmx_entry_ctls_high);
2473                 break;
2474         case MSR_IA32_VMX_ENTRY_CTLS:
2475                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2476                                         nested_vmx_entry_ctls_high);
2477                 break;
2478         case MSR_IA32_VMX_MISC:
2479                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2480                                          nested_vmx_misc_high);
2481                 break;
2482         /*
2483          * These MSRs specify bits which the guest must keep fixed (on or off)
2484          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2485          * We picked the standard core2 setting.
2486          */
2487 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2488 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2489         case MSR_IA32_VMX_CR0_FIXED0:
2490                 *pdata = VMXON_CR0_ALWAYSON;
2491                 break;
2492         case MSR_IA32_VMX_CR0_FIXED1:
2493                 *pdata = -1ULL;
2494                 break;
2495         case MSR_IA32_VMX_CR4_FIXED0:
2496                 *pdata = VMXON_CR4_ALWAYSON;
2497                 break;
2498         case MSR_IA32_VMX_CR4_FIXED1:
2499                 *pdata = -1ULL;
2500                 break;
2501         case MSR_IA32_VMX_VMCS_ENUM:
2502                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2503                 break;
2504         case MSR_IA32_VMX_PROCBASED_CTLS2:
2505                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2506                                         nested_vmx_secondary_ctls_high);
2507                 break;
2508         case MSR_IA32_VMX_EPT_VPID_CAP:
2509                 /* Currently, no nested vpid support */
2510                 *pdata = nested_vmx_ept_caps;
2511                 break;
2512         default:
2513                 return 1;
2514         }
2515
2516         return 0;
2517 }
2518
2519 /*
2520  * Reads an msr value (of 'msr_index') into 'pdata'.
2521  * Returns 0 on success, non-0 otherwise.
2522  * Assumes vcpu_load() was already called.
2523  */
2524 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2525 {
2526         u64 data;
2527         struct shared_msr_entry *msr;
2528
2529         if (!pdata) {
2530                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2531                 return -EINVAL;
2532         }
2533
2534         switch (msr_index) {
2535 #ifdef CONFIG_X86_64
2536         case MSR_FS_BASE:
2537                 data = vmcs_readl(GUEST_FS_BASE);
2538                 break;
2539         case MSR_GS_BASE:
2540                 data = vmcs_readl(GUEST_GS_BASE);
2541                 break;
2542         case MSR_KERNEL_GS_BASE:
2543                 vmx_load_host_state(to_vmx(vcpu));
2544                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2545                 break;
2546 #endif
2547         case MSR_EFER:
2548                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2549         case MSR_IA32_TSC:
2550                 data = guest_read_tsc();
2551                 break;
2552         case MSR_IA32_SYSENTER_CS:
2553                 data = vmcs_read32(GUEST_SYSENTER_CS);
2554                 break;
2555         case MSR_IA32_SYSENTER_EIP:
2556                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2557                 break;
2558         case MSR_IA32_SYSENTER_ESP:
2559                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2560                 break;
2561         case MSR_IA32_BNDCFGS:
2562                 if (!vmx_mpx_supported())
2563                         return 1;
2564                 data = vmcs_read64(GUEST_BNDCFGS);
2565                 break;
2566         case MSR_IA32_FEATURE_CONTROL:
2567                 if (!nested_vmx_allowed(vcpu))
2568                         return 1;
2569                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2570                 break;
2571         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2572                 if (!nested_vmx_allowed(vcpu))
2573                         return 1;
2574                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2575         case MSR_IA32_XSS:
2576                 if (!vmx_xsaves_supported())
2577                         return 1;
2578                 data = vcpu->arch.ia32_xss;
2579                 break;
2580         case MSR_TSC_AUX:
2581                 if (!to_vmx(vcpu)->rdtscp_enabled)
2582                         return 1;
2583                 /* Otherwise falls through */
2584         default:
2585                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2586                 if (msr) {
2587                         data = msr->data;
2588                         break;
2589                 }
2590                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2591         }
2592
2593         *pdata = data;
2594         return 0;
2595 }
2596
2597 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2598
2599 /*
2600  * Writes msr value into into the appropriate "register".
2601  * Returns 0 on success, non-0 otherwise.
2602  * Assumes vcpu_load() was already called.
2603  */
2604 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2605 {
2606         struct vcpu_vmx *vmx = to_vmx(vcpu);
2607         struct shared_msr_entry *msr;
2608         int ret = 0;
2609         u32 msr_index = msr_info->index;
2610         u64 data = msr_info->data;
2611
2612         switch (msr_index) {
2613         case MSR_EFER:
2614                 ret = kvm_set_msr_common(vcpu, msr_info);
2615                 break;
2616 #ifdef CONFIG_X86_64
2617         case MSR_FS_BASE:
2618                 vmx_segment_cache_clear(vmx);
2619                 vmcs_writel(GUEST_FS_BASE, data);
2620                 break;
2621         case MSR_GS_BASE:
2622                 vmx_segment_cache_clear(vmx);
2623                 vmcs_writel(GUEST_GS_BASE, data);
2624                 break;
2625         case MSR_KERNEL_GS_BASE:
2626                 vmx_load_host_state(vmx);
2627                 vmx->msr_guest_kernel_gs_base = data;
2628                 break;
2629 #endif
2630         case MSR_IA32_SYSENTER_CS:
2631                 vmcs_write32(GUEST_SYSENTER_CS, data);
2632                 break;
2633         case MSR_IA32_SYSENTER_EIP:
2634                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2635                 break;
2636         case MSR_IA32_SYSENTER_ESP:
2637                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2638                 break;
2639         case MSR_IA32_BNDCFGS:
2640                 if (!vmx_mpx_supported())
2641                         return 1;
2642                 vmcs_write64(GUEST_BNDCFGS, data);
2643                 break;
2644         case MSR_IA32_TSC:
2645                 kvm_write_tsc(vcpu, msr_info);
2646                 break;
2647         case MSR_IA32_CR_PAT:
2648                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2649                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2650                                 return 1;
2651                         vmcs_write64(GUEST_IA32_PAT, data);
2652                         vcpu->arch.pat = data;
2653                         break;
2654                 }
2655                 ret = kvm_set_msr_common(vcpu, msr_info);
2656                 break;
2657         case MSR_IA32_TSC_ADJUST:
2658                 ret = kvm_set_msr_common(vcpu, msr_info);
2659                 break;
2660         case MSR_IA32_FEATURE_CONTROL:
2661                 if (!nested_vmx_allowed(vcpu) ||
2662                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2663                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2664                         return 1;
2665                 vmx->nested.msr_ia32_feature_control = data;
2666                 if (msr_info->host_initiated && data == 0)
2667                         vmx_leave_nested(vcpu);
2668                 break;
2669         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2670                 return 1; /* they are read-only */
2671         case MSR_IA32_XSS:
2672                 if (!vmx_xsaves_supported())
2673                         return 1;
2674                 /*
2675                  * The only supported bit as of Skylake is bit 8, but
2676                  * it is not supported on KVM.
2677                  */
2678                 if (data != 0)
2679                         return 1;
2680                 vcpu->arch.ia32_xss = data;
2681                 if (vcpu->arch.ia32_xss != host_xss)
2682                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2683                                 vcpu->arch.ia32_xss, host_xss);
2684                 else
2685                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2686                 break;
2687         case MSR_TSC_AUX:
2688                 if (!vmx->rdtscp_enabled)
2689                         return 1;
2690                 /* Check reserved bit, higher 32 bits should be zero */
2691                 if ((data >> 32) != 0)
2692                         return 1;
2693                 /* Otherwise falls through */
2694         default:
2695                 msr = find_msr_entry(vmx, msr_index);
2696                 if (msr) {
2697                         u64 old_msr_data = msr->data;
2698                         msr->data = data;
2699                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2700                                 preempt_disable();
2701                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2702                                                          msr->mask);
2703                                 preempt_enable();
2704                                 if (ret)
2705                                         msr->data = old_msr_data;
2706                         }
2707                         break;
2708                 }
2709                 ret = kvm_set_msr_common(vcpu, msr_info);
2710         }
2711
2712         return ret;
2713 }
2714
2715 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2716 {
2717         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2718         switch (reg) {
2719         case VCPU_REGS_RSP:
2720                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2721                 break;
2722         case VCPU_REGS_RIP:
2723                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2724                 break;
2725         case VCPU_EXREG_PDPTR:
2726                 if (enable_ept)
2727                         ept_save_pdptrs(vcpu);
2728                 break;
2729         default:
2730                 break;
2731         }
2732 }
2733
2734 static __init int cpu_has_kvm_support(void)
2735 {
2736         return cpu_has_vmx();
2737 }
2738
2739 static __init int vmx_disabled_by_bios(void)
2740 {
2741         u64 msr;
2742
2743         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2744         if (msr & FEATURE_CONTROL_LOCKED) {
2745                 /* launched w/ TXT and VMX disabled */
2746                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2747                         && tboot_enabled())
2748                         return 1;
2749                 /* launched w/o TXT and VMX only enabled w/ TXT */
2750                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2751                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2752                         && !tboot_enabled()) {
2753                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2754                                 "activate TXT before enabling KVM\n");
2755                         return 1;
2756                 }
2757                 /* launched w/o TXT and VMX disabled */
2758                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2759                         && !tboot_enabled())
2760                         return 1;
2761         }
2762
2763         return 0;
2764 }
2765
2766 static void kvm_cpu_vmxon(u64 addr)
2767 {
2768         asm volatile (ASM_VMX_VMXON_RAX
2769                         : : "a"(&addr), "m"(addr)
2770                         : "memory", "cc");
2771 }
2772
2773 static int hardware_enable(void)
2774 {
2775         int cpu = raw_smp_processor_id();
2776         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2777         u64 old, test_bits;
2778
2779         if (read_cr4() & X86_CR4_VMXE)
2780                 return -EBUSY;
2781
2782         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2783
2784         /*
2785          * Now we can enable the vmclear operation in kdump
2786          * since the loaded_vmcss_on_cpu list on this cpu
2787          * has been initialized.
2788          *
2789          * Though the cpu is not in VMX operation now, there
2790          * is no problem to enable the vmclear operation
2791          * for the loaded_vmcss_on_cpu list is empty!
2792          */
2793         crash_enable_local_vmclear(cpu);
2794
2795         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2796
2797         test_bits = FEATURE_CONTROL_LOCKED;
2798         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2799         if (tboot_enabled())
2800                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2801
2802         if ((old & test_bits) != test_bits) {
2803                 /* enable and lock */
2804                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2805         }
2806         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2807
2808         if (vmm_exclusive) {
2809                 kvm_cpu_vmxon(phys_addr);
2810                 ept_sync_global();
2811         }
2812
2813         native_store_gdt(this_cpu_ptr(&host_gdt));
2814
2815         return 0;
2816 }
2817
2818 static void vmclear_local_loaded_vmcss(void)
2819 {
2820         int cpu = raw_smp_processor_id();
2821         struct loaded_vmcs *v, *n;
2822
2823         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2824                                  loaded_vmcss_on_cpu_link)
2825                 __loaded_vmcs_clear(v);
2826 }
2827
2828
2829 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2830  * tricks.
2831  */
2832 static void kvm_cpu_vmxoff(void)
2833 {
2834         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2835 }
2836
2837 static void hardware_disable(void)
2838 {
2839         if (vmm_exclusive) {
2840                 vmclear_local_loaded_vmcss();
2841                 kvm_cpu_vmxoff();
2842         }
2843         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2844 }
2845
2846 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2847                                       u32 msr, u32 *result)
2848 {
2849         u32 vmx_msr_low, vmx_msr_high;
2850         u32 ctl = ctl_min | ctl_opt;
2851
2852         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2853
2854         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2855         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2856
2857         /* Ensure minimum (required) set of control bits are supported. */
2858         if (ctl_min & ~ctl)
2859                 return -EIO;
2860
2861         *result = ctl;
2862         return 0;
2863 }
2864
2865 static __init bool allow_1_setting(u32 msr, u32 ctl)
2866 {
2867         u32 vmx_msr_low, vmx_msr_high;
2868
2869         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2870         return vmx_msr_high & ctl;
2871 }
2872
2873 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2874 {
2875         u32 vmx_msr_low, vmx_msr_high;
2876         u32 min, opt, min2, opt2;
2877         u32 _pin_based_exec_control = 0;
2878         u32 _cpu_based_exec_control = 0;
2879         u32 _cpu_based_2nd_exec_control = 0;
2880         u32 _vmexit_control = 0;
2881         u32 _vmentry_control = 0;
2882
2883         min = CPU_BASED_HLT_EXITING |
2884 #ifdef CONFIG_X86_64
2885               CPU_BASED_CR8_LOAD_EXITING |
2886               CPU_BASED_CR8_STORE_EXITING |
2887 #endif
2888               CPU_BASED_CR3_LOAD_EXITING |
2889               CPU_BASED_CR3_STORE_EXITING |
2890               CPU_BASED_USE_IO_BITMAPS |
2891               CPU_BASED_MOV_DR_EXITING |
2892               CPU_BASED_USE_TSC_OFFSETING |
2893               CPU_BASED_MWAIT_EXITING |
2894               CPU_BASED_MONITOR_EXITING |
2895               CPU_BASED_INVLPG_EXITING |
2896               CPU_BASED_RDPMC_EXITING;
2897
2898         opt = CPU_BASED_TPR_SHADOW |
2899               CPU_BASED_USE_MSR_BITMAPS |
2900               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2901         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2902                                 &_cpu_based_exec_control) < 0)
2903                 return -EIO;
2904 #ifdef CONFIG_X86_64
2905         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2906                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2907                                            ~CPU_BASED_CR8_STORE_EXITING;
2908 #endif
2909         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2910                 min2 = 0;
2911                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2912                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2913                         SECONDARY_EXEC_WBINVD_EXITING |
2914                         SECONDARY_EXEC_ENABLE_VPID |
2915                         SECONDARY_EXEC_ENABLE_EPT |
2916                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2917                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2918                         SECONDARY_EXEC_RDTSCP |
2919                         SECONDARY_EXEC_ENABLE_INVPCID |
2920                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2921                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2922                         SECONDARY_EXEC_SHADOW_VMCS |
2923                         SECONDARY_EXEC_XSAVES;
2924                 if (adjust_vmx_controls(min2, opt2,
2925                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2926                                         &_cpu_based_2nd_exec_control) < 0)
2927                         return -EIO;
2928         }
2929 #ifndef CONFIG_X86_64
2930         if (!(_cpu_based_2nd_exec_control &
2931                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2932                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2933 #endif
2934
2935         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2936                 _cpu_based_2nd_exec_control &= ~(
2937                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2938                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2939                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2940
2941         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2942                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2943                    enabled */
2944                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2945                                              CPU_BASED_CR3_STORE_EXITING |
2946                                              CPU_BASED_INVLPG_EXITING);
2947                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2948                       vmx_capability.ept, vmx_capability.vpid);
2949         }
2950
2951         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2952 #ifdef CONFIG_X86_64
2953         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2954 #endif
2955         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2956                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2957         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2958                                 &_vmexit_control) < 0)
2959                 return -EIO;
2960
2961         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2962         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2963         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2964                                 &_pin_based_exec_control) < 0)
2965                 return -EIO;
2966
2967         if (!(_cpu_based_2nd_exec_control &
2968                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2969                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2970                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2971
2972         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2973         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2974         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2975                                 &_vmentry_control) < 0)
2976                 return -EIO;
2977
2978         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2979
2980         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2981         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2982                 return -EIO;
2983
2984 #ifdef CONFIG_X86_64
2985         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2986         if (vmx_msr_high & (1u<<16))
2987                 return -EIO;
2988 #endif
2989
2990         /* Require Write-Back (WB) memory type for VMCS accesses. */
2991         if (((vmx_msr_high >> 18) & 15) != 6)
2992                 return -EIO;
2993
2994         vmcs_conf->size = vmx_msr_high & 0x1fff;
2995         vmcs_conf->order = get_order(vmcs_config.size);
2996         vmcs_conf->revision_id = vmx_msr_low;
2997
2998         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2999         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3000         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3001         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3002         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3003
3004         cpu_has_load_ia32_efer =
3005                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3006                                 VM_ENTRY_LOAD_IA32_EFER)
3007                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3008                                    VM_EXIT_LOAD_IA32_EFER);
3009
3010         cpu_has_load_perf_global_ctrl =
3011                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3012                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3013                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3014                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3015
3016         /*
3017          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3018          * but due to arrata below it can't be used. Workaround is to use
3019          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3020          *
3021          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3022          *
3023          * AAK155             (model 26)
3024          * AAP115             (model 30)
3025          * AAT100             (model 37)
3026          * BC86,AAY89,BD102   (model 44)
3027          * BA97               (model 46)
3028          *
3029          */
3030         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3031                 switch (boot_cpu_data.x86_model) {
3032                 case 26:
3033                 case 30:
3034                 case 37:
3035                 case 44:
3036                 case 46:
3037                         cpu_has_load_perf_global_ctrl = false;
3038                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3039                                         "does not work properly. Using workaround\n");
3040                         break;
3041                 default:
3042                         break;
3043                 }
3044         }
3045
3046         if (cpu_has_xsaves)
3047                 rdmsrl(MSR_IA32_XSS, host_xss);
3048
3049         return 0;
3050 }
3051
3052 static struct vmcs *alloc_vmcs_cpu(int cpu)
3053 {
3054         int node = cpu_to_node(cpu);
3055         struct page *pages;
3056         struct vmcs *vmcs;
3057
3058         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3059         if (!pages)
3060                 return NULL;
3061         vmcs = page_address(pages);
3062         memset(vmcs, 0, vmcs_config.size);
3063         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3064         return vmcs;
3065 }
3066
3067 static struct vmcs *alloc_vmcs(void)
3068 {
3069         return alloc_vmcs_cpu(raw_smp_processor_id());
3070 }
3071
3072 static void free_vmcs(struct vmcs *vmcs)
3073 {
3074         free_pages((unsigned long)vmcs, vmcs_config.order);
3075 }
3076
3077 /*
3078  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3079  */
3080 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3081 {
3082         if (!loaded_vmcs->vmcs)
3083                 return;
3084         loaded_vmcs_clear(loaded_vmcs);
3085         free_vmcs(loaded_vmcs->vmcs);
3086         loaded_vmcs->vmcs = NULL;
3087 }
3088
3089 static void free_kvm_area(void)
3090 {
3091         int cpu;
3092
3093         for_each_possible_cpu(cpu) {
3094                 free_vmcs(per_cpu(vmxarea, cpu));
3095                 per_cpu(vmxarea, cpu) = NULL;
3096         }
3097 }
3098
3099 static void init_vmcs_shadow_fields(void)
3100 {
3101         int i, j;
3102
3103         /* No checks for read only fields yet */
3104
3105         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3106                 switch (shadow_read_write_fields[i]) {
3107                 case GUEST_BNDCFGS:
3108                         if (!vmx_mpx_supported())
3109                                 continue;
3110                         break;
3111                 default:
3112                         break;
3113                 }
3114
3115                 if (j < i)
3116                         shadow_read_write_fields[j] =
3117                                 shadow_read_write_fields[i];
3118                 j++;
3119         }
3120         max_shadow_read_write_fields = j;
3121
3122         /* shadowed fields guest access without vmexit */
3123         for (i = 0; i < max_shadow_read_write_fields; i++) {
3124                 clear_bit(shadow_read_write_fields[i],
3125                           vmx_vmwrite_bitmap);
3126                 clear_bit(shadow_read_write_fields[i],
3127                           vmx_vmread_bitmap);
3128         }
3129         for (i = 0; i < max_shadow_read_only_fields; i++)
3130                 clear_bit(shadow_read_only_fields[i],
3131                           vmx_vmread_bitmap);
3132 }
3133
3134 static __init int alloc_kvm_area(void)
3135 {
3136         int cpu;
3137
3138         for_each_possible_cpu(cpu) {
3139                 struct vmcs *vmcs;
3140
3141                 vmcs = alloc_vmcs_cpu(cpu);
3142                 if (!vmcs) {
3143                         free_kvm_area();
3144                         return -ENOMEM;
3145                 }
3146
3147                 per_cpu(vmxarea, cpu) = vmcs;
3148         }
3149         return 0;
3150 }
3151
3152 static bool emulation_required(struct kvm_vcpu *vcpu)
3153 {
3154         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3155 }
3156
3157 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3158                 struct kvm_segment *save)
3159 {
3160         if (!emulate_invalid_guest_state) {
3161                 /*
3162                  * CS and SS RPL should be equal during guest entry according
3163                  * to VMX spec, but in reality it is not always so. Since vcpu
3164                  * is in the middle of the transition from real mode to
3165                  * protected mode it is safe to assume that RPL 0 is a good
3166                  * default value.
3167                  */
3168                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3169                         save->selector &= ~SELECTOR_RPL_MASK;
3170                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3171                 save->s = 1;
3172         }
3173         vmx_set_segment(vcpu, save, seg);
3174 }
3175
3176 static void enter_pmode(struct kvm_vcpu *vcpu)
3177 {
3178         unsigned long flags;
3179         struct vcpu_vmx *vmx = to_vmx(vcpu);
3180
3181         /*
3182          * Update real mode segment cache. It may be not up-to-date if sement
3183          * register was written while vcpu was in a guest mode.
3184          */
3185         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3186         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3187         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3188         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3189         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3190         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3191
3192         vmx->rmode.vm86_active = 0;
3193
3194         vmx_segment_cache_clear(vmx);
3195
3196         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3197
3198         flags = vmcs_readl(GUEST_RFLAGS);
3199         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3200         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3201         vmcs_writel(GUEST_RFLAGS, flags);
3202
3203         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3204                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3205
3206         update_exception_bitmap(vcpu);
3207
3208         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3209         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3210         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3211         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3212         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3213         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3214 }
3215
3216 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3217 {
3218         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3219         struct kvm_segment var = *save;
3220
3221         var.dpl = 0x3;
3222         if (seg == VCPU_SREG_CS)
3223                 var.type = 0x3;
3224
3225         if (!emulate_invalid_guest_state) {
3226                 var.selector = var.base >> 4;
3227                 var.base = var.base & 0xffff0;
3228                 var.limit = 0xffff;
3229                 var.g = 0;
3230                 var.db = 0;
3231                 var.present = 1;
3232                 var.s = 1;
3233                 var.l = 0;
3234                 var.unusable = 0;
3235                 var.type = 0x3;
3236                 var.avl = 0;
3237                 if (save->base & 0xf)
3238                         printk_once(KERN_WARNING "kvm: segment base is not "
3239                                         "paragraph aligned when entering "
3240                                         "protected mode (seg=%d)", seg);
3241         }
3242
3243         vmcs_write16(sf->selector, var.selector);
3244         vmcs_write32(sf->base, var.base);
3245         vmcs_write32(sf->limit, var.limit);
3246         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3247 }
3248
3249 static void enter_rmode(struct kvm_vcpu *vcpu)
3250 {
3251         unsigned long flags;
3252         struct vcpu_vmx *vmx = to_vmx(vcpu);
3253
3254         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3255         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3256         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3257         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3258         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3259         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3260         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3261
3262         vmx->rmode.vm86_active = 1;
3263
3264         /*
3265          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3266          * vcpu. Warn the user that an update is overdue.
3267          */
3268         if (!vcpu->kvm->arch.tss_addr)
3269                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3270                              "called before entering vcpu\n");
3271
3272         vmx_segment_cache_clear(vmx);
3273
3274         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3275         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3276         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3277
3278         flags = vmcs_readl(GUEST_RFLAGS);
3279         vmx->rmode.save_rflags = flags;
3280
3281         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3282
3283         vmcs_writel(GUEST_RFLAGS, flags);
3284         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3285         update_exception_bitmap(vcpu);
3286
3287         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3288         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3289         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3290         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3291         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3292         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3293
3294         kvm_mmu_reset_context(vcpu);
3295 }
3296
3297 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3298 {
3299         struct vcpu_vmx *vmx = to_vmx(vcpu);
3300         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3301
3302         if (!msr)
3303                 return;
3304
3305         /*
3306          * Force kernel_gs_base reloading before EFER changes, as control
3307          * of this msr depends on is_long_mode().
3308          */
3309         vmx_load_host_state(to_vmx(vcpu));
3310         vcpu->arch.efer = efer;
3311         if (efer & EFER_LMA) {
3312                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3313                 msr->data = efer;
3314         } else {
3315                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3316
3317                 msr->data = efer & ~EFER_LME;
3318         }
3319         setup_msrs(vmx);
3320 }
3321
3322 #ifdef CONFIG_X86_64
3323
3324 static void enter_lmode(struct kvm_vcpu *vcpu)
3325 {
3326         u32 guest_tr_ar;
3327
3328         vmx_segment_cache_clear(to_vmx(vcpu));
3329
3330         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3331         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3332                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3333                                      __func__);
3334                 vmcs_write32(GUEST_TR_AR_BYTES,
3335                              (guest_tr_ar & ~AR_TYPE_MASK)
3336                              | AR_TYPE_BUSY_64_TSS);
3337         }
3338         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3339 }
3340
3341 static void exit_lmode(struct kvm_vcpu *vcpu)
3342 {
3343         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3344         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3345 }
3346
3347 #endif
3348
3349 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3350 {
3351         vpid_sync_context(to_vmx(vcpu));
3352         if (enable_ept) {
3353                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3354                         return;
3355                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3356         }
3357 }
3358
3359 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3360 {
3361         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3362
3363         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3364         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3365 }
3366
3367 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3368 {
3369         if (enable_ept && is_paging(vcpu))
3370                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3371         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3372 }
3373
3374 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3375 {
3376         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3377
3378         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3379         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3380 }
3381
3382 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3383 {
3384         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3385
3386         if (!test_bit(VCPU_EXREG_PDPTR,
3387                       (unsigned long *)&vcpu->arch.regs_dirty))
3388                 return;
3389
3390         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3391                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3392                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3393                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3394                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3395         }
3396 }
3397
3398 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3399 {
3400         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3401
3402         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3403                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3404                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3405                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3406                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3407         }
3408
3409         __set_bit(VCPU_EXREG_PDPTR,
3410                   (unsigned long *)&vcpu->arch.regs_avail);
3411         __set_bit(VCPU_EXREG_PDPTR,
3412                   (unsigned long *)&vcpu->arch.regs_dirty);
3413 }
3414
3415 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3416
3417 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3418                                         unsigned long cr0,
3419                                         struct kvm_vcpu *vcpu)
3420 {
3421         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3422                 vmx_decache_cr3(vcpu);
3423         if (!(cr0 & X86_CR0_PG)) {
3424                 /* From paging/starting to nonpaging */
3425                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3426                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3427                              (CPU_BASED_CR3_LOAD_EXITING |
3428                               CPU_BASED_CR3_STORE_EXITING));
3429                 vcpu->arch.cr0 = cr0;
3430                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3431         } else if (!is_paging(vcpu)) {
3432                 /* From nonpaging to paging */
3433                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3434                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3435                              ~(CPU_BASED_CR3_LOAD_EXITING |
3436                                CPU_BASED_CR3_STORE_EXITING));
3437                 vcpu->arch.cr0 = cr0;
3438                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3439         }
3440
3441         if (!(cr0 & X86_CR0_WP))
3442                 *hw_cr0 &= ~X86_CR0_WP;
3443 }
3444
3445 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3446 {
3447         struct vcpu_vmx *vmx = to_vmx(vcpu);
3448         unsigned long hw_cr0;
3449
3450         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3451         if (enable_unrestricted_guest)
3452                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3453         else {
3454                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3455
3456                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3457                         enter_pmode(vcpu);
3458
3459                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3460                         enter_rmode(vcpu);
3461         }
3462
3463 #ifdef CONFIG_X86_64
3464         if (vcpu->arch.efer & EFER_LME) {
3465                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3466                         enter_lmode(vcpu);
3467                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3468                         exit_lmode(vcpu);
3469         }
3470 #endif
3471
3472         if (enable_ept)
3473                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3474
3475         if (!vcpu->fpu_active)
3476                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3477
3478         vmcs_writel(CR0_READ_SHADOW, cr0);
3479         vmcs_writel(GUEST_CR0, hw_cr0);
3480         vcpu->arch.cr0 = cr0;
3481
3482         /* depends on vcpu->arch.cr0 to be set to a new value */
3483         vmx->emulation_required = emulation_required(vcpu);
3484 }
3485
3486 static u64 construct_eptp(unsigned long root_hpa)
3487 {
3488         u64 eptp;
3489
3490         /* TODO write the value reading from MSR */
3491         eptp = VMX_EPT_DEFAULT_MT |
3492                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3493         if (enable_ept_ad_bits)
3494                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3495         eptp |= (root_hpa & PAGE_MASK);
3496
3497         return eptp;
3498 }
3499
3500 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3501 {
3502         unsigned long guest_cr3;
3503         u64 eptp;
3504
3505         guest_cr3 = cr3;
3506         if (enable_ept) {
3507                 eptp = construct_eptp(cr3);
3508                 vmcs_write64(EPT_POINTER, eptp);
3509                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3510                         guest_cr3 = kvm_read_cr3(vcpu);
3511                 else
3512                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3513                 ept_load_pdptrs(vcpu);
3514         }
3515
3516         vmx_flush_tlb(vcpu);
3517         vmcs_writel(GUEST_CR3, guest_cr3);
3518 }
3519
3520 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3521 {
3522         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3523                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3524
3525         if (cr4 & X86_CR4_VMXE) {
3526                 /*
3527                  * To use VMXON (and later other VMX instructions), a guest
3528                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3529                  * So basically the check on whether to allow nested VMX
3530                  * is here.
3531                  */
3532                 if (!nested_vmx_allowed(vcpu))
3533                         return 1;
3534         }
3535         if (to_vmx(vcpu)->nested.vmxon &&
3536             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3537                 return 1;
3538
3539         vcpu->arch.cr4 = cr4;
3540         if (enable_ept) {
3541                 if (!is_paging(vcpu)) {
3542                         hw_cr4 &= ~X86_CR4_PAE;
3543                         hw_cr4 |= X86_CR4_PSE;
3544                         /*
3545                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3546                          * in hardware. However KVM always uses paging mode to
3547                          * emulate guest non-paging mode with TDP.
3548                          * To emulate this behavior, SMEP/SMAP needs to be
3549                          * manually disabled when guest switches to non-paging
3550                          * mode.
3551                          */
3552                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3553                 } else if (!(cr4 & X86_CR4_PAE)) {
3554                         hw_cr4 &= ~X86_CR4_PAE;
3555                 }
3556         }
3557
3558         vmcs_writel(CR4_READ_SHADOW, cr4);
3559         vmcs_writel(GUEST_CR4, hw_cr4);
3560         return 0;
3561 }
3562
3563 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3564                             struct kvm_segment *var, int seg)
3565 {
3566         struct vcpu_vmx *vmx = to_vmx(vcpu);
3567         u32 ar;
3568
3569         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3570                 *var = vmx->rmode.segs[seg];
3571                 if (seg == VCPU_SREG_TR
3572                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3573                         return;
3574                 var->base = vmx_read_guest_seg_base(vmx, seg);
3575                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3576                 return;
3577         }
3578         var->base = vmx_read_guest_seg_base(vmx, seg);
3579         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3580         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3581         ar = vmx_read_guest_seg_ar(vmx, seg);
3582         var->unusable = (ar >> 16) & 1;
3583         var->type = ar & 15;
3584         var->s = (ar >> 4) & 1;
3585         var->dpl = (ar >> 5) & 3;
3586         /*
3587          * Some userspaces do not preserve unusable property. Since usable
3588          * segment has to be present according to VMX spec we can use present
3589          * property to amend userspace bug by making unusable segment always
3590          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3591          * segment as unusable.
3592          */
3593         var->present = !var->unusable;
3594         var->avl = (ar >> 12) & 1;
3595         var->l = (ar >> 13) & 1;
3596         var->db = (ar >> 14) & 1;
3597         var->g = (ar >> 15) & 1;
3598 }
3599
3600 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3601 {
3602         struct kvm_segment s;
3603
3604         if (to_vmx(vcpu)->rmode.vm86_active) {
3605                 vmx_get_segment(vcpu, &s, seg);
3606                 return s.base;
3607         }
3608         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3609 }
3610
3611 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3612 {
3613         struct vcpu_vmx *vmx = to_vmx(vcpu);
3614
3615         if (unlikely(vmx->rmode.vm86_active))
3616                 return 0;
3617         else {
3618                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3619                 return AR_DPL(ar);
3620         }
3621 }
3622
3623 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3624 {
3625         u32 ar;
3626
3627         if (var->unusable || !var->present)
3628                 ar = 1 << 16;
3629         else {
3630                 ar = var->type & 15;
3631                 ar |= (var->s & 1) << 4;
3632                 ar |= (var->dpl & 3) << 5;
3633                 ar |= (var->present & 1) << 7;
3634                 ar |= (var->avl & 1) << 12;
3635                 ar |= (var->l & 1) << 13;
3636                 ar |= (var->db & 1) << 14;
3637                 ar |= (var->g & 1) << 15;
3638         }
3639
3640         return ar;
3641 }
3642
3643 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3644                             struct kvm_segment *var, int seg)
3645 {
3646         struct vcpu_vmx *vmx = to_vmx(vcpu);
3647         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3648
3649         vmx_segment_cache_clear(vmx);
3650
3651         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3652                 vmx->rmode.segs[seg] = *var;
3653                 if (seg == VCPU_SREG_TR)
3654                         vmcs_write16(sf->selector, var->selector);
3655                 else if (var->s)
3656                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3657                 goto out;
3658         }
3659
3660         vmcs_writel(sf->base, var->base);
3661         vmcs_write32(sf->limit, var->limit);
3662         vmcs_write16(sf->selector, var->selector);
3663
3664         /*
3665          *   Fix the "Accessed" bit in AR field of segment registers for older
3666          * qemu binaries.
3667          *   IA32 arch specifies that at the time of processor reset the
3668          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3669          * is setting it to 0 in the userland code. This causes invalid guest
3670          * state vmexit when "unrestricted guest" mode is turned on.
3671          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3672          * tree. Newer qemu binaries with that qemu fix would not need this
3673          * kvm hack.
3674          */
3675         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3676                 var->type |= 0x1; /* Accessed */
3677
3678         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3679
3680 out:
3681         vmx->emulation_required = emulation_required(vcpu);
3682 }
3683
3684 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3685 {
3686         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3687
3688         *db = (ar >> 14) & 1;
3689         *l = (ar >> 13) & 1;
3690 }
3691
3692 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3693 {
3694         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3695         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3696 }
3697
3698 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3699 {
3700         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3701         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3702 }
3703
3704 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3705 {
3706         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3707         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3708 }
3709
3710 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3711 {
3712         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3713         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3714 }
3715
3716 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3717 {
3718         struct kvm_segment var;
3719         u32 ar;
3720
3721         vmx_get_segment(vcpu, &var, seg);
3722         var.dpl = 0x3;
3723         if (seg == VCPU_SREG_CS)
3724                 var.type = 0x3;
3725         ar = vmx_segment_access_rights(&var);
3726
3727         if (var.base != (var.selector << 4))
3728                 return false;
3729         if (var.limit != 0xffff)
3730                 return false;
3731         if (ar != 0xf3)
3732                 return false;
3733
3734         return true;
3735 }
3736
3737 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3738 {
3739         struct kvm_segment cs;
3740         unsigned int cs_rpl;
3741
3742         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3743         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3744
3745         if (cs.unusable)
3746                 return false;
3747         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3748                 return false;
3749         if (!cs.s)
3750                 return false;
3751         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3752                 if (cs.dpl > cs_rpl)
3753                         return false;
3754         } else {
3755                 if (cs.dpl != cs_rpl)
3756                         return false;
3757         }
3758         if (!cs.present)
3759                 return false;
3760
3761         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3762         return true;
3763 }
3764
3765 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3766 {
3767         struct kvm_segment ss;
3768         unsigned int ss_rpl;
3769
3770         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3771         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3772
3773         if (ss.unusable)
3774                 return true;
3775         if (ss.type != 3 && ss.type != 7)
3776                 return false;
3777         if (!ss.s)
3778                 return false;
3779         if (ss.dpl != ss_rpl) /* DPL != RPL */
3780                 return false;
3781         if (!ss.present)
3782                 return false;
3783
3784         return true;
3785 }
3786
3787 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3788 {
3789         struct kvm_segment var;
3790         unsigned int rpl;
3791
3792         vmx_get_segment(vcpu, &var, seg);
3793         rpl = var.selector & SELECTOR_RPL_MASK;
3794
3795         if (var.unusable)
3796                 return true;
3797         if (!var.s)
3798                 return false;
3799         if (!var.present)
3800                 return false;
3801         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3802                 if (var.dpl < rpl) /* DPL < RPL */
3803                         return false;
3804         }
3805
3806         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3807          * rights flags
3808          */
3809         return true;
3810 }
3811
3812 static bool tr_valid(struct kvm_vcpu *vcpu)
3813 {
3814         struct kvm_segment tr;
3815
3816         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3817
3818         if (tr.unusable)
3819                 return false;
3820         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3821                 return false;
3822         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3823                 return false;
3824         if (!tr.present)
3825                 return false;
3826
3827         return true;
3828 }
3829
3830 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3831 {
3832         struct kvm_segment ldtr;
3833
3834         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3835
3836         if (ldtr.unusable)
3837                 return true;
3838         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3839                 return false;
3840         if (ldtr.type != 2)
3841                 return false;
3842         if (!ldtr.present)
3843                 return false;
3844
3845         return true;
3846 }
3847
3848 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3849 {
3850         struct kvm_segment cs, ss;
3851
3852         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3853         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3854
3855         return ((cs.selector & SELECTOR_RPL_MASK) ==
3856                  (ss.selector & SELECTOR_RPL_MASK));
3857 }
3858
3859 /*
3860  * Check if guest state is valid. Returns true if valid, false if
3861  * not.
3862  * We assume that registers are always usable
3863  */
3864 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3865 {
3866         if (enable_unrestricted_guest)
3867                 return true;
3868
3869         /* real mode guest state checks */
3870         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3871                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3872                         return false;
3873                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3874                         return false;
3875                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3876                         return false;
3877                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3878                         return false;
3879                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3880                         return false;
3881                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3882                         return false;
3883         } else {
3884         /* protected mode guest state checks */
3885                 if (!cs_ss_rpl_check(vcpu))
3886                         return false;
3887                 if (!code_segment_valid(vcpu))
3888                         return false;
3889                 if (!stack_segment_valid(vcpu))
3890                         return false;
3891                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3892                         return false;
3893                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3894                         return false;
3895                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3896                         return false;
3897                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3898                         return false;
3899                 if (!tr_valid(vcpu))
3900                         return false;
3901                 if (!ldtr_valid(vcpu))
3902                         return false;
3903         }
3904         /* TODO:
3905          * - Add checks on RIP
3906          * - Add checks on RFLAGS
3907          */
3908
3909         return true;
3910 }
3911
3912 static int init_rmode_tss(struct kvm *kvm)
3913 {
3914         gfn_t fn;
3915         u16 data = 0;
3916         int idx, r;
3917
3918         idx = srcu_read_lock(&kvm->srcu);
3919         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3920         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3921         if (r < 0)
3922                 goto out;
3923         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3924         r = kvm_write_guest_page(kvm, fn++, &data,
3925                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3926         if (r < 0)
3927                 goto out;
3928         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3929         if (r < 0)
3930                 goto out;
3931         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3932         if (r < 0)
3933                 goto out;
3934         data = ~0;
3935         r = kvm_write_guest_page(kvm, fn, &data,
3936                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3937                                  sizeof(u8));
3938 out:
3939         srcu_read_unlock(&kvm->srcu, idx);
3940         return r;
3941 }
3942
3943 static int init_rmode_identity_map(struct kvm *kvm)
3944 {
3945         int i, idx, r = 0;
3946         pfn_t identity_map_pfn;
3947         u32 tmp;
3948
3949         if (!enable_ept)
3950                 return 0;
3951
3952         /* Protect kvm->arch.ept_identity_pagetable_done. */
3953         mutex_lock(&kvm->slots_lock);
3954
3955         if (likely(kvm->arch.ept_identity_pagetable_done))
3956                 goto out2;
3957
3958         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3959
3960         r = alloc_identity_pagetable(kvm);
3961         if (r < 0)
3962                 goto out2;
3963
3964         idx = srcu_read_lock(&kvm->srcu);
3965         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3966         if (r < 0)
3967                 goto out;
3968         /* Set up identity-mapping pagetable for EPT in real mode */
3969         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3970                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3971                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3972                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3973                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3974                 if (r < 0)
3975                         goto out;
3976         }
3977         kvm->arch.ept_identity_pagetable_done = true;
3978
3979 out:
3980         srcu_read_unlock(&kvm->srcu, idx);
3981
3982 out2:
3983         mutex_unlock(&kvm->slots_lock);
3984         return r;
3985 }
3986
3987 static void seg_setup(int seg)
3988 {
3989         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3990         unsigned int ar;
3991
3992         vmcs_write16(sf->selector, 0);
3993         vmcs_writel(sf->base, 0);
3994         vmcs_write32(sf->limit, 0xffff);
3995         ar = 0x93;
3996         if (seg == VCPU_SREG_CS)
3997                 ar |= 0x08; /* code segment */
3998
3999         vmcs_write32(sf->ar_bytes, ar);
4000 }
4001
4002 static int alloc_apic_access_page(struct kvm *kvm)
4003 {
4004         struct page *page;
4005         struct kvm_userspace_memory_region kvm_userspace_mem;
4006         int r = 0;
4007
4008         mutex_lock(&kvm->slots_lock);
4009         if (kvm->arch.apic_access_page_done)
4010                 goto out;
4011         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4012         kvm_userspace_mem.flags = 0;
4013         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4014         kvm_userspace_mem.memory_size = PAGE_SIZE;
4015         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4016         if (r)
4017                 goto out;
4018
4019         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4020         if (is_error_page(page)) {
4021                 r = -EFAULT;
4022                 goto out;
4023         }
4024
4025         /*
4026          * Do not pin the page in memory, so that memory hot-unplug
4027          * is able to migrate it.
4028          */
4029         put_page(page);
4030         kvm->arch.apic_access_page_done = true;
4031 out:
4032         mutex_unlock(&kvm->slots_lock);
4033         return r;
4034 }
4035
4036 static int alloc_identity_pagetable(struct kvm *kvm)
4037 {
4038         /* Called with kvm->slots_lock held. */
4039
4040         struct kvm_userspace_memory_region kvm_userspace_mem;
4041         int r = 0;
4042
4043         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4044
4045         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4046         kvm_userspace_mem.flags = 0;
4047         kvm_userspace_mem.guest_phys_addr =
4048                 kvm->arch.ept_identity_map_addr;
4049         kvm_userspace_mem.memory_size = PAGE_SIZE;
4050         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4051
4052         return r;
4053 }
4054
4055 static void allocate_vpid(struct vcpu_vmx *vmx)
4056 {
4057         int vpid;
4058
4059         vmx->vpid = 0;
4060         if (!enable_vpid)
4061                 return;
4062         spin_lock(&vmx_vpid_lock);
4063         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4064         if (vpid < VMX_NR_VPIDS) {
4065                 vmx->vpid = vpid;
4066                 __set_bit(vpid, vmx_vpid_bitmap);
4067         }
4068         spin_unlock(&vmx_vpid_lock);
4069 }
4070
4071 static void free_vpid(struct vcpu_vmx *vmx)
4072 {
4073         if (!enable_vpid)
4074                 return;
4075         spin_lock(&vmx_vpid_lock);
4076         if (vmx->vpid != 0)
4077                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4078         spin_unlock(&vmx_vpid_lock);
4079 }
4080
4081 #define MSR_TYPE_R      1
4082 #define MSR_TYPE_W      2
4083 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4084                                                 u32 msr, int type)
4085 {
4086         int f = sizeof(unsigned long);
4087
4088         if (!cpu_has_vmx_msr_bitmap())
4089                 return;
4090
4091         /*
4092          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4093          * have the write-low and read-high bitmap offsets the wrong way round.
4094          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4095          */
4096         if (msr <= 0x1fff) {
4097                 if (type & MSR_TYPE_R)
4098                         /* read-low */
4099                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4100
4101                 if (type & MSR_TYPE_W)
4102                         /* write-low */
4103                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4104
4105         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4106                 msr &= 0x1fff;
4107                 if (type & MSR_TYPE_R)
4108                         /* read-high */
4109                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4110
4111                 if (type & MSR_TYPE_W)
4112                         /* write-high */
4113                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4114
4115         }
4116 }
4117
4118 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4119                                                 u32 msr, int type)
4120 {
4121         int f = sizeof(unsigned long);
4122
4123         if (!cpu_has_vmx_msr_bitmap())
4124                 return;
4125
4126         /*
4127          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4128          * have the write-low and read-high bitmap offsets the wrong way round.
4129          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4130          */
4131         if (msr <= 0x1fff) {
4132                 if (type & MSR_TYPE_R)
4133                         /* read-low */
4134                         __set_bit(msr, msr_bitmap + 0x000 / f);
4135
4136                 if (type & MSR_TYPE_W)
4137                         /* write-low */
4138                         __set_bit(msr, msr_bitmap + 0x800 / f);
4139
4140         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4141                 msr &= 0x1fff;
4142                 if (type & MSR_TYPE_R)
4143                         /* read-high */
4144                         __set_bit(msr, msr_bitmap + 0x400 / f);
4145
4146                 if (type & MSR_TYPE_W)
4147                         /* write-high */
4148                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4149
4150         }
4151 }
4152
4153 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4154 {
4155         if (!longmode_only)
4156                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4157                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4158         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4159                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4160 }
4161
4162 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4163 {
4164         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4165                         msr, MSR_TYPE_R);
4166         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4167                         msr, MSR_TYPE_R);
4168 }
4169
4170 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4171 {
4172         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4173                         msr, MSR_TYPE_R);
4174         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4175                         msr, MSR_TYPE_R);
4176 }
4177
4178 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4179 {
4180         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4181                         msr, MSR_TYPE_W);
4182         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4183                         msr, MSR_TYPE_W);
4184 }
4185
4186 static int vmx_vm_has_apicv(struct kvm *kvm)
4187 {
4188         return enable_apicv && irqchip_in_kernel(kvm);
4189 }
4190
4191 /*
4192  * Send interrupt to vcpu via posted interrupt way.
4193  * 1. If target vcpu is running(non-root mode), send posted interrupt
4194  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4195  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4196  * interrupt from PIR in next vmentry.
4197  */
4198 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4199 {
4200         struct vcpu_vmx *vmx = to_vmx(vcpu);
4201         int r;
4202
4203         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4204                 return;
4205
4206         r = pi_test_and_set_on(&vmx->pi_desc);
4207         kvm_make_request(KVM_REQ_EVENT, vcpu);
4208 #ifdef CONFIG_SMP
4209         if (!r && (vcpu->mode == IN_GUEST_MODE))
4210                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4211                                 POSTED_INTR_VECTOR);
4212         else
4213 #endif
4214                 kvm_vcpu_kick(vcpu);
4215 }
4216
4217 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4218 {
4219         struct vcpu_vmx *vmx = to_vmx(vcpu);
4220
4221         if (!pi_test_and_clear_on(&vmx->pi_desc))
4222                 return;
4223
4224         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4225 }
4226
4227 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4228 {
4229         return;
4230 }
4231
4232 /*
4233  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4234  * will not change in the lifetime of the guest.
4235  * Note that host-state that does change is set elsewhere. E.g., host-state
4236  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4237  */
4238 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4239 {
4240         u32 low32, high32;
4241         unsigned long tmpl;
4242         struct desc_ptr dt;
4243         unsigned long cr4;
4244
4245         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4246         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4247
4248         /* Save the most likely value for this task's CR4 in the VMCS. */
4249         cr4 = read_cr4();
4250         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4251         vmx->host_state.vmcs_host_cr4 = cr4;
4252
4253         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4254 #ifdef CONFIG_X86_64
4255         /*
4256          * Load null selectors, so we can avoid reloading them in
4257          * __vmx_load_host_state(), in case userspace uses the null selectors
4258          * too (the expected case).
4259          */
4260         vmcs_write16(HOST_DS_SELECTOR, 0);
4261         vmcs_write16(HOST_ES_SELECTOR, 0);
4262 #else
4263         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4264         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4265 #endif
4266         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4267         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4268
4269         native_store_idt(&dt);
4270         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4271         vmx->host_idt_base = dt.address;
4272
4273         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4274
4275         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4276         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4277         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4278         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4279
4280         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4281                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4282                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4283         }
4284 }
4285
4286 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4287 {
4288         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4289         if (enable_ept)
4290                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4291         if (is_guest_mode(&vmx->vcpu))
4292                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4293                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4294         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4295 }
4296
4297 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4298 {
4299         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4300
4301         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4302                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4303         return pin_based_exec_ctrl;
4304 }
4305
4306 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4307 {
4308         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4309
4310         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4311                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4312
4313         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4314                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4315 #ifdef CONFIG_X86_64
4316                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4317                                 CPU_BASED_CR8_LOAD_EXITING;
4318 #endif
4319         }
4320         if (!enable_ept)
4321                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4322                                 CPU_BASED_CR3_LOAD_EXITING  |
4323                                 CPU_BASED_INVLPG_EXITING;
4324         return exec_control;
4325 }
4326
4327 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4328 {
4329         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4330         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4331                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4332         if (vmx->vpid == 0)
4333                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4334         if (!enable_ept) {
4335                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4336                 enable_unrestricted_guest = 0;
4337                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4338                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4339         }
4340         if (!enable_unrestricted_guest)
4341                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4342         if (!ple_gap)
4343                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4344         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4345                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4346                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4347         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4348         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4349            (handle_vmptrld).
4350            We can NOT enable shadow_vmcs here because we don't have yet
4351            a current VMCS12
4352         */
4353         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4354         return exec_control;
4355 }
4356
4357 static void ept_set_mmio_spte_mask(void)
4358 {
4359         /*
4360          * EPT Misconfigurations can be generated if the value of bits 2:0
4361          * of an EPT paging-structure entry is 110b (write/execute).
4362          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4363          * spte.
4364          */
4365         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4366 }
4367
4368 #define VMX_XSS_EXIT_BITMAP 0
4369 /*
4370  * Sets up the vmcs for emulated real mode.
4371  */
4372 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4373 {
4374 #ifdef CONFIG_X86_64
4375         unsigned long a;
4376 #endif
4377         int i;
4378
4379         /* I/O */
4380         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4381         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4382
4383         if (enable_shadow_vmcs) {
4384                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4385                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4386         }
4387         if (cpu_has_vmx_msr_bitmap())
4388                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4389
4390         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4391
4392         /* Control */
4393         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4394
4395         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4396
4397         if (cpu_has_secondary_exec_ctrls()) {
4398                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4399                                 vmx_secondary_exec_control(vmx));
4400         }
4401
4402         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4403                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4404                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4405                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4406                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4407
4408                 vmcs_write16(GUEST_INTR_STATUS, 0);
4409
4410                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4411                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4412         }
4413
4414         if (ple_gap) {
4415                 vmcs_write32(PLE_GAP, ple_gap);
4416                 vmx->ple_window = ple_window;
4417                 vmx->ple_window_dirty = true;
4418         }
4419
4420         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4421         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4422         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4423
4424         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4425         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4426         vmx_set_constant_host_state(vmx);
4427 #ifdef CONFIG_X86_64
4428         rdmsrl(MSR_FS_BASE, a);
4429         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4430         rdmsrl(MSR_GS_BASE, a);
4431         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4432 #else
4433         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4434         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4435 #endif
4436
4437         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4438         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4439         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4440         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4441         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4442
4443         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4444                 u32 msr_low, msr_high;
4445                 u64 host_pat;
4446                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4447                 host_pat = msr_low | ((u64) msr_high << 32);
4448                 /* Write the default value follow host pat */
4449                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4450                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4451                 vmx->vcpu.arch.pat = host_pat;
4452         }
4453
4454         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4455                 u32 index = vmx_msr_index[i];
4456                 u32 data_low, data_high;
4457                 int j = vmx->nmsrs;
4458
4459                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4460                         continue;
4461                 if (wrmsr_safe(index, data_low, data_high) < 0)
4462                         continue;
4463                 vmx->guest_msrs[j].index = i;
4464                 vmx->guest_msrs[j].data = 0;
4465                 vmx->guest_msrs[j].mask = -1ull;
4466                 ++vmx->nmsrs;
4467         }
4468
4469
4470         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4471
4472         /* 22.2.1, 20.8.1 */
4473         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4474
4475         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4476         set_cr4_guest_host_mask(vmx);
4477
4478         if (vmx_xsaves_supported())
4479                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4480
4481         return 0;
4482 }
4483
4484 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4485 {
4486         struct vcpu_vmx *vmx = to_vmx(vcpu);
4487         struct msr_data apic_base_msr;
4488
4489         vmx->rmode.vm86_active = 0;
4490
4491         vmx->soft_vnmi_blocked = 0;
4492
4493         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4494         kvm_set_cr8(&vmx->vcpu, 0);
4495         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4496         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4497                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4498         apic_base_msr.host_initiated = true;
4499         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4500
4501         vmx_segment_cache_clear(vmx);
4502
4503         seg_setup(VCPU_SREG_CS);
4504         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4505         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4506
4507         seg_setup(VCPU_SREG_DS);
4508         seg_setup(VCPU_SREG_ES);
4509         seg_setup(VCPU_SREG_FS);
4510         seg_setup(VCPU_SREG_GS);
4511         seg_setup(VCPU_SREG_SS);
4512
4513         vmcs_write16(GUEST_TR_SELECTOR, 0);
4514         vmcs_writel(GUEST_TR_BASE, 0);
4515         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4516         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4517
4518         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4519         vmcs_writel(GUEST_LDTR_BASE, 0);
4520         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4521         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4522
4523         vmcs_write32(GUEST_SYSENTER_CS, 0);
4524         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4525         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4526
4527         vmcs_writel(GUEST_RFLAGS, 0x02);
4528         kvm_rip_write(vcpu, 0xfff0);
4529
4530         vmcs_writel(GUEST_GDTR_BASE, 0);
4531         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4532
4533         vmcs_writel(GUEST_IDTR_BASE, 0);
4534         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4535
4536         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4537         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4538         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4539
4540         /* Special registers */
4541         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4542
4543         setup_msrs(vmx);
4544
4545         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4546
4547         if (cpu_has_vmx_tpr_shadow()) {
4548                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4549                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4550                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4551                                      __pa(vmx->vcpu.arch.apic->regs));
4552                 vmcs_write32(TPR_THRESHOLD, 0);
4553         }
4554
4555         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4556
4557         if (vmx_vm_has_apicv(vcpu->kvm))
4558                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4559
4560         if (vmx->vpid != 0)
4561                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4562
4563         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4564         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4565         vmx_set_cr4(&vmx->vcpu, 0);
4566         vmx_set_efer(&vmx->vcpu, 0);
4567         vmx_fpu_activate(&vmx->vcpu);
4568         update_exception_bitmap(&vmx->vcpu);
4569
4570         vpid_sync_context(vmx);
4571 }
4572
4573 /*
4574  * In nested virtualization, check if L1 asked to exit on external interrupts.
4575  * For most existing hypervisors, this will always return true.
4576  */
4577 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4578 {
4579         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4580                 PIN_BASED_EXT_INTR_MASK;
4581 }
4582
4583 /*
4584  * In nested virtualization, check if L1 has set
4585  * VM_EXIT_ACK_INTR_ON_EXIT
4586  */
4587 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4588 {
4589         return get_vmcs12(vcpu)->vm_exit_controls &
4590                 VM_EXIT_ACK_INTR_ON_EXIT;
4591 }
4592
4593 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4594 {
4595         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4596                 PIN_BASED_NMI_EXITING;
4597 }
4598
4599 static void enable_irq_window(struct kvm_vcpu *vcpu)
4600 {
4601         u32 cpu_based_vm_exec_control;
4602
4603         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4604         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4605         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4606 }
4607
4608 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4609 {
4610         u32 cpu_based_vm_exec_control;
4611
4612         if (!cpu_has_virtual_nmis() ||
4613             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4614                 enable_irq_window(vcpu);
4615                 return;
4616         }
4617
4618         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4619         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4620         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4621 }
4622
4623 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4624 {
4625         struct vcpu_vmx *vmx = to_vmx(vcpu);
4626         uint32_t intr;
4627         int irq = vcpu->arch.interrupt.nr;
4628
4629         trace_kvm_inj_virq(irq);
4630
4631         ++vcpu->stat.irq_injections;
4632         if (vmx->rmode.vm86_active) {
4633                 int inc_eip = 0;
4634                 if (vcpu->arch.interrupt.soft)
4635                         inc_eip = vcpu->arch.event_exit_inst_len;
4636                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4637                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4638                 return;
4639         }
4640         intr = irq | INTR_INFO_VALID_MASK;
4641         if (vcpu->arch.interrupt.soft) {
4642                 intr |= INTR_TYPE_SOFT_INTR;
4643                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4644                              vmx->vcpu.arch.event_exit_inst_len);
4645         } else
4646                 intr |= INTR_TYPE_EXT_INTR;
4647         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4648 }
4649
4650 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4651 {
4652         struct vcpu_vmx *vmx = to_vmx(vcpu);
4653
4654         if (is_guest_mode(vcpu))
4655                 return;
4656
4657         if (!cpu_has_virtual_nmis()) {
4658                 /*
4659                  * Tracking the NMI-blocked state in software is built upon
4660                  * finding the next open IRQ window. This, in turn, depends on
4661                  * well-behaving guests: They have to keep IRQs disabled at
4662                  * least as long as the NMI handler runs. Otherwise we may
4663                  * cause NMI nesting, maybe breaking the guest. But as this is
4664                  * highly unlikely, we can live with the residual risk.
4665                  */
4666                 vmx->soft_vnmi_blocked = 1;
4667                 vmx->vnmi_blocked_time = 0;
4668         }
4669
4670         ++vcpu->stat.nmi_injections;
4671         vmx->nmi_known_unmasked = false;
4672         if (vmx->rmode.vm86_active) {
4673                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4674                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4675                 return;
4676         }
4677         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4678                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4679 }
4680
4681 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4682 {
4683         if (!cpu_has_virtual_nmis())
4684                 return to_vmx(vcpu)->soft_vnmi_blocked;
4685         if (to_vmx(vcpu)->nmi_known_unmasked)
4686                 return false;
4687         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4688 }
4689
4690 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4691 {
4692         struct vcpu_vmx *vmx = to_vmx(vcpu);
4693
4694         if (!cpu_has_virtual_nmis()) {
4695                 if (vmx->soft_vnmi_blocked != masked) {
4696                         vmx->soft_vnmi_blocked = masked;
4697                         vmx->vnmi_blocked_time = 0;
4698                 }
4699         } else {
4700                 vmx->nmi_known_unmasked = !masked;
4701                 if (masked)
4702                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4703                                       GUEST_INTR_STATE_NMI);
4704                 else
4705                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4706                                         GUEST_INTR_STATE_NMI);
4707         }
4708 }
4709
4710 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4711 {
4712         if (to_vmx(vcpu)->nested.nested_run_pending)
4713                 return 0;
4714
4715         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4716                 return 0;
4717
4718         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4719                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4720                    | GUEST_INTR_STATE_NMI));
4721 }
4722
4723 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4724 {
4725         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4726                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4727                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4728                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4729 }
4730
4731 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4732 {
4733         int ret;
4734         struct kvm_userspace_memory_region tss_mem = {
4735                 .slot = TSS_PRIVATE_MEMSLOT,
4736                 .guest_phys_addr = addr,
4737                 .memory_size = PAGE_SIZE * 3,
4738                 .flags = 0,
4739         };
4740
4741         ret = kvm_set_memory_region(kvm, &tss_mem);
4742         if (ret)
4743                 return ret;
4744         kvm->arch.tss_addr = addr;
4745         return init_rmode_tss(kvm);
4746 }
4747
4748 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4749 {
4750         switch (vec) {
4751         case BP_VECTOR:
4752                 /*
4753                  * Update instruction length as we may reinject the exception
4754                  * from user space while in guest debugging mode.
4755                  */
4756                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4757                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4758                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4759                         return false;
4760                 /* fall through */
4761         case DB_VECTOR:
4762                 if (vcpu->guest_debug &
4763                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4764                         return false;
4765                 /* fall through */
4766         case DE_VECTOR:
4767         case OF_VECTOR:
4768         case BR_VECTOR:
4769         case UD_VECTOR:
4770         case DF_VECTOR:
4771         case SS_VECTOR:
4772         case GP_VECTOR:
4773         case MF_VECTOR:
4774                 return true;
4775         break;
4776         }
4777         return false;
4778 }
4779
4780 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4781                                   int vec, u32 err_code)
4782 {
4783         /*
4784          * Instruction with address size override prefix opcode 0x67
4785          * Cause the #SS fault with 0 error code in VM86 mode.
4786          */
4787         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4788                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4789                         if (vcpu->arch.halt_request) {
4790                                 vcpu->arch.halt_request = 0;
4791                                 return kvm_emulate_halt(vcpu);
4792                         }
4793                         return 1;
4794                 }
4795                 return 0;
4796         }
4797
4798         /*
4799          * Forward all other exceptions that are valid in real mode.
4800          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4801          *        the required debugging infrastructure rework.
4802          */
4803         kvm_queue_exception(vcpu, vec);
4804         return 1;
4805 }
4806
4807 /*
4808  * Trigger machine check on the host. We assume all the MSRs are already set up
4809  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4810  * We pass a fake environment to the machine check handler because we want
4811  * the guest to be always treated like user space, no matter what context
4812  * it used internally.
4813  */
4814 static void kvm_machine_check(void)
4815 {
4816 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4817         struct pt_regs regs = {
4818                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4819                 .flags = X86_EFLAGS_IF,
4820         };
4821
4822         do_machine_check(&regs, 0);
4823 #endif
4824 }
4825
4826 static int handle_machine_check(struct kvm_vcpu *vcpu)
4827 {
4828         /* already handled by vcpu_run */
4829         return 1;
4830 }
4831
4832 static int handle_exception(struct kvm_vcpu *vcpu)
4833 {
4834         struct vcpu_vmx *vmx = to_vmx(vcpu);
4835         struct kvm_run *kvm_run = vcpu->run;
4836         u32 intr_info, ex_no, error_code;
4837         unsigned long cr2, rip, dr6;
4838         u32 vect_info;
4839         enum emulation_result er;
4840
4841         vect_info = vmx->idt_vectoring_info;
4842         intr_info = vmx->exit_intr_info;
4843
4844         if (is_machine_check(intr_info))
4845                 return handle_machine_check(vcpu);
4846
4847         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4848                 return 1;  /* already handled by vmx_vcpu_run() */
4849
4850         if (is_no_device(intr_info)) {
4851                 vmx_fpu_activate(vcpu);
4852                 return 1;
4853         }
4854
4855         if (is_invalid_opcode(intr_info)) {
4856                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4857                 if (er != EMULATE_DONE)
4858                         kvm_queue_exception(vcpu, UD_VECTOR);
4859                 return 1;
4860         }
4861
4862         error_code = 0;
4863         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4864                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4865
4866         /*
4867          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4868          * MMIO, it is better to report an internal error.
4869          * See the comments in vmx_handle_exit.
4870          */
4871         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4872             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4873                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4874                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4875                 vcpu->run->internal.ndata = 2;
4876                 vcpu->run->internal.data[0] = vect_info;
4877                 vcpu->run->internal.data[1] = intr_info;
4878                 return 0;
4879         }
4880
4881         if (is_page_fault(intr_info)) {
4882                 /* EPT won't cause page fault directly */
4883                 BUG_ON(enable_ept);
4884                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4885                 trace_kvm_page_fault(cr2, error_code);
4886
4887                 if (kvm_event_needs_reinjection(vcpu))
4888                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4889                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4890         }
4891
4892         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4893
4894         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4895                 return handle_rmode_exception(vcpu, ex_no, error_code);
4896
4897         switch (ex_no) {
4898         case DB_VECTOR:
4899                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4900                 if (!(vcpu->guest_debug &
4901                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4902                         vcpu->arch.dr6 &= ~15;
4903                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4904                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4905                                 skip_emulated_instruction(vcpu);
4906
4907                         kvm_queue_exception(vcpu, DB_VECTOR);
4908                         return 1;
4909                 }
4910                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4911                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4912                 /* fall through */
4913         case BP_VECTOR:
4914                 /*
4915                  * Update instruction length as we may reinject #BP from
4916                  * user space while in guest debugging mode. Reading it for
4917                  * #DB as well causes no harm, it is not used in that case.
4918                  */
4919                 vmx->vcpu.arch.event_exit_inst_len =
4920                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4921                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4922                 rip = kvm_rip_read(vcpu);
4923                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4924                 kvm_run->debug.arch.exception = ex_no;
4925                 break;
4926         default:
4927                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4928                 kvm_run->ex.exception = ex_no;
4929                 kvm_run->ex.error_code = error_code;
4930                 break;
4931         }
4932         return 0;
4933 }
4934
4935 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4936 {
4937         ++vcpu->stat.irq_exits;
4938         return 1;
4939 }
4940
4941 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4942 {
4943         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4944         return 0;
4945 }
4946
4947 static int handle_io(struct kvm_vcpu *vcpu)
4948 {
4949         unsigned long exit_qualification;
4950         int size, in, string;
4951         unsigned port;
4952
4953         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4954         string = (exit_qualification & 16) != 0;
4955         in = (exit_qualification & 8) != 0;
4956
4957         ++vcpu->stat.io_exits;
4958
4959         if (string || in)
4960                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4961
4962         port = exit_qualification >> 16;
4963         size = (exit_qualification & 7) + 1;
4964         skip_emulated_instruction(vcpu);
4965
4966         return kvm_fast_pio_out(vcpu, size, port);
4967 }
4968
4969 static void
4970 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4971 {
4972         /*
4973          * Patch in the VMCALL instruction:
4974          */
4975         hypercall[0] = 0x0f;
4976         hypercall[1] = 0x01;
4977         hypercall[2] = 0xc1;
4978 }
4979
4980 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4981 {
4982         unsigned long always_on = VMXON_CR0_ALWAYSON;
4983
4984         if (nested_vmx_secondary_ctls_high &
4985                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4986             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4987                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4988         return (val & always_on) == always_on;
4989 }
4990
4991 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4992 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4993 {
4994         if (is_guest_mode(vcpu)) {
4995                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4996                 unsigned long orig_val = val;
4997
4998                 /*
4999                  * We get here when L2 changed cr0 in a way that did not change
5000                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5001                  * but did change L0 shadowed bits. So we first calculate the
5002                  * effective cr0 value that L1 would like to write into the
5003                  * hardware. It consists of the L2-owned bits from the new
5004                  * value combined with the L1-owned bits from L1's guest_cr0.
5005                  */
5006                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5007                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5008
5009                 if (!nested_cr0_valid(vmcs12, val))
5010                         return 1;
5011
5012                 if (kvm_set_cr0(vcpu, val))
5013                         return 1;
5014                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5015                 return 0;
5016         } else {
5017                 if (to_vmx(vcpu)->nested.vmxon &&
5018                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5019                         return 1;
5020                 return kvm_set_cr0(vcpu, val);
5021         }
5022 }
5023
5024 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5025 {
5026         if (is_guest_mode(vcpu)) {
5027                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5028                 unsigned long orig_val = val;
5029
5030                 /* analogously to handle_set_cr0 */
5031                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5032                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5033                 if (kvm_set_cr4(vcpu, val))
5034                         return 1;
5035                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5036                 return 0;
5037         } else
5038                 return kvm_set_cr4(vcpu, val);
5039 }
5040
5041 /* called to set cr0 as approriate for clts instruction exit. */
5042 static void handle_clts(struct kvm_vcpu *vcpu)
5043 {
5044         if (is_guest_mode(vcpu)) {
5045                 /*
5046                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5047                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5048                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5049                  */
5050                 vmcs_writel(CR0_READ_SHADOW,
5051                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5052                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5053         } else
5054                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5055 }
5056
5057 static int handle_cr(struct kvm_vcpu *vcpu)
5058 {
5059         unsigned long exit_qualification, val;
5060         int cr;
5061         int reg;
5062         int err;
5063
5064         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5065         cr = exit_qualification & 15;
5066         reg = (exit_qualification >> 8) & 15;
5067         switch ((exit_qualification >> 4) & 3) {
5068         case 0: /* mov to cr */
5069                 val = kvm_register_readl(vcpu, reg);
5070                 trace_kvm_cr_write(cr, val);
5071                 switch (cr) {
5072                 case 0:
5073                         err = handle_set_cr0(vcpu, val);
5074                         kvm_complete_insn_gp(vcpu, err);
5075                         return 1;
5076                 case 3:
5077                         err = kvm_set_cr3(vcpu, val);
5078                         kvm_complete_insn_gp(vcpu, err);
5079                         return 1;
5080                 case 4:
5081                         err = handle_set_cr4(vcpu, val);
5082                         kvm_complete_insn_gp(vcpu, err);
5083                         return 1;
5084                 case 8: {
5085                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5086                                 u8 cr8 = (u8)val;
5087                                 err = kvm_set_cr8(vcpu, cr8);
5088                                 kvm_complete_insn_gp(vcpu, err);
5089                                 if (irqchip_in_kernel(vcpu->kvm))
5090                                         return 1;
5091                                 if (cr8_prev <= cr8)
5092                                         return 1;
5093                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5094                                 return 0;
5095                         }
5096                 }
5097                 break;
5098         case 2: /* clts */
5099                 handle_clts(vcpu);
5100                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5101                 skip_emulated_instruction(vcpu);
5102                 vmx_fpu_activate(vcpu);
5103                 return 1;
5104         case 1: /*mov from cr*/
5105                 switch (cr) {
5106                 case 3:
5107                         val = kvm_read_cr3(vcpu);
5108                         kvm_register_write(vcpu, reg, val);
5109                         trace_kvm_cr_read(cr, val);
5110                         skip_emulated_instruction(vcpu);
5111                         return 1;
5112                 case 8:
5113                         val = kvm_get_cr8(vcpu);
5114                         kvm_register_write(vcpu, reg, val);
5115                         trace_kvm_cr_read(cr, val);
5116                         skip_emulated_instruction(vcpu);
5117                         return 1;
5118                 }
5119                 break;
5120         case 3: /* lmsw */
5121                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5122                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5123                 kvm_lmsw(vcpu, val);
5124
5125                 skip_emulated_instruction(vcpu);
5126                 return 1;
5127         default:
5128                 break;
5129         }
5130         vcpu->run->exit_reason = 0;
5131         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5132                (int)(exit_qualification >> 4) & 3, cr);
5133         return 0;
5134 }
5135
5136 static int handle_dr(struct kvm_vcpu *vcpu)
5137 {
5138         unsigned long exit_qualification;
5139         int dr, dr7, reg;
5140
5141         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5142         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5143
5144         /* First, if DR does not exist, trigger UD */
5145         if (!kvm_require_dr(vcpu, dr))
5146                 return 1;
5147
5148         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5149         if (!kvm_require_cpl(vcpu, 0))
5150                 return 1;
5151         dr7 = vmcs_readl(GUEST_DR7);
5152         if (dr7 & DR7_GD) {
5153                 /*
5154                  * As the vm-exit takes precedence over the debug trap, we
5155                  * need to emulate the latter, either for the host or the
5156                  * guest debugging itself.
5157                  */
5158                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5159                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5160                         vcpu->run->debug.arch.dr7 = dr7;
5161                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5162                         vcpu->run->debug.arch.exception = DB_VECTOR;
5163                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5164                         return 0;
5165                 } else {
5166                         vcpu->arch.dr6 &= ~15;
5167                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5168                         kvm_queue_exception(vcpu, DB_VECTOR);
5169                         return 1;
5170                 }
5171         }
5172
5173         if (vcpu->guest_debug == 0) {
5174                 u32 cpu_based_vm_exec_control;
5175
5176                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5177                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5178                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5179
5180                 /*
5181                  * No more DR vmexits; force a reload of the debug registers
5182                  * and reenter on this instruction.  The next vmexit will
5183                  * retrieve the full state of the debug registers.
5184                  */
5185                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5186                 return 1;
5187         }
5188
5189         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5190         if (exit_qualification & TYPE_MOV_FROM_DR) {
5191                 unsigned long val;
5192
5193                 if (kvm_get_dr(vcpu, dr, &val))
5194                         return 1;
5195                 kvm_register_write(vcpu, reg, val);
5196         } else
5197                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5198                         return 1;
5199
5200         skip_emulated_instruction(vcpu);
5201         return 1;
5202 }
5203
5204 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5205 {
5206         return vcpu->arch.dr6;
5207 }
5208
5209 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5210 {
5211 }
5212
5213 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5214 {
5215         u32 cpu_based_vm_exec_control;
5216
5217         get_debugreg(vcpu->arch.db[0], 0);
5218         get_debugreg(vcpu->arch.db[1], 1);
5219         get_debugreg(vcpu->arch.db[2], 2);
5220         get_debugreg(vcpu->arch.db[3], 3);
5221         get_debugreg(vcpu->arch.dr6, 6);
5222         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5223
5224         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5225
5226         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5227         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5228         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5229 }
5230
5231 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5232 {
5233         vmcs_writel(GUEST_DR7, val);
5234 }
5235
5236 static int handle_cpuid(struct kvm_vcpu *vcpu)
5237 {
5238         kvm_emulate_cpuid(vcpu);
5239         return 1;
5240 }
5241
5242 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5243 {
5244         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5245         u64 data;
5246
5247         if (vmx_get_msr(vcpu, ecx, &data)) {
5248                 trace_kvm_msr_read_ex(ecx);
5249                 kvm_inject_gp(vcpu, 0);
5250                 return 1;
5251         }
5252
5253         trace_kvm_msr_read(ecx, data);
5254
5255         /* FIXME: handling of bits 32:63 of rax, rdx */
5256         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5257         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5258         skip_emulated_instruction(vcpu);
5259         return 1;
5260 }
5261
5262 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5263 {
5264         struct msr_data msr;
5265         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5266         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5267                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5268
5269         msr.data = data;
5270         msr.index = ecx;
5271         msr.host_initiated = false;
5272         if (kvm_set_msr(vcpu, &msr) != 0) {
5273                 trace_kvm_msr_write_ex(ecx, data);
5274                 kvm_inject_gp(vcpu, 0);
5275                 return 1;
5276         }
5277
5278         trace_kvm_msr_write(ecx, data);
5279         skip_emulated_instruction(vcpu);
5280         return 1;
5281 }
5282
5283 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5284 {
5285         kvm_make_request(KVM_REQ_EVENT, vcpu);
5286         return 1;
5287 }
5288
5289 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5290 {
5291         u32 cpu_based_vm_exec_control;
5292
5293         /* clear pending irq */
5294         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5295         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5296         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5297
5298         kvm_make_request(KVM_REQ_EVENT, vcpu);
5299
5300         ++vcpu->stat.irq_window_exits;
5301
5302         /*
5303          * If the user space waits to inject interrupts, exit as soon as
5304          * possible
5305          */
5306         if (!irqchip_in_kernel(vcpu->kvm) &&
5307             vcpu->run->request_interrupt_window &&
5308             !kvm_cpu_has_interrupt(vcpu)) {
5309                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5310                 return 0;
5311         }
5312         return 1;
5313 }
5314
5315 static int handle_halt(struct kvm_vcpu *vcpu)
5316 {
5317         skip_emulated_instruction(vcpu);
5318         return kvm_emulate_halt(vcpu);
5319 }
5320
5321 static int handle_vmcall(struct kvm_vcpu *vcpu)
5322 {
5323         skip_emulated_instruction(vcpu);
5324         kvm_emulate_hypercall(vcpu);
5325         return 1;
5326 }
5327
5328 static int handle_invd(struct kvm_vcpu *vcpu)
5329 {
5330         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5331 }
5332
5333 static int handle_invlpg(struct kvm_vcpu *vcpu)
5334 {
5335         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5336
5337         kvm_mmu_invlpg(vcpu, exit_qualification);
5338         skip_emulated_instruction(vcpu);
5339         return 1;
5340 }
5341
5342 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5343 {
5344         int err;
5345
5346         err = kvm_rdpmc(vcpu);
5347         kvm_complete_insn_gp(vcpu, err);
5348
5349         return 1;
5350 }
5351
5352 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5353 {
5354         skip_emulated_instruction(vcpu);
5355         kvm_emulate_wbinvd(vcpu);
5356         return 1;
5357 }
5358
5359 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5360 {
5361         u64 new_bv = kvm_read_edx_eax(vcpu);
5362         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5363
5364         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5365                 skip_emulated_instruction(vcpu);
5366         return 1;
5367 }
5368
5369 static int handle_xsaves(struct kvm_vcpu *vcpu)
5370 {
5371         skip_emulated_instruction(vcpu);
5372         WARN(1, "this should never happen\n");
5373         return 1;
5374 }
5375
5376 static int handle_xrstors(struct kvm_vcpu *vcpu)
5377 {
5378         skip_emulated_instruction(vcpu);
5379         WARN(1, "this should never happen\n");
5380         return 1;
5381 }
5382
5383 static int handle_apic_access(struct kvm_vcpu *vcpu)
5384 {
5385         if (likely(fasteoi)) {
5386                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5387                 int access_type, offset;
5388
5389                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5390                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5391                 /*
5392                  * Sane guest uses MOV to write EOI, with written value
5393                  * not cared. So make a short-circuit here by avoiding
5394                  * heavy instruction emulation.
5395                  */
5396                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5397                     (offset == APIC_EOI)) {
5398                         kvm_lapic_set_eoi(vcpu);
5399                         skip_emulated_instruction(vcpu);
5400                         return 1;
5401                 }
5402         }
5403         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5404 }
5405
5406 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5407 {
5408         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5409         int vector = exit_qualification & 0xff;
5410
5411         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5412         kvm_apic_set_eoi_accelerated(vcpu, vector);
5413         return 1;
5414 }
5415
5416 static int handle_apic_write(struct kvm_vcpu *vcpu)
5417 {
5418         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5419         u32 offset = exit_qualification & 0xfff;
5420
5421         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5422         kvm_apic_write_nodecode(vcpu, offset);
5423         return 1;
5424 }
5425
5426 static int handle_task_switch(struct kvm_vcpu *vcpu)
5427 {
5428         struct vcpu_vmx *vmx = to_vmx(vcpu);
5429         unsigned long exit_qualification;
5430         bool has_error_code = false;
5431         u32 error_code = 0;
5432         u16 tss_selector;
5433         int reason, type, idt_v, idt_index;
5434
5435         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5436         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5437         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5438
5439         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5440
5441         reason = (u32)exit_qualification >> 30;
5442         if (reason == TASK_SWITCH_GATE && idt_v) {
5443                 switch (type) {
5444                 case INTR_TYPE_NMI_INTR:
5445                         vcpu->arch.nmi_injected = false;
5446                         vmx_set_nmi_mask(vcpu, true);
5447                         break;
5448                 case INTR_TYPE_EXT_INTR:
5449                 case INTR_TYPE_SOFT_INTR:
5450                         kvm_clear_interrupt_queue(vcpu);
5451                         break;
5452                 case INTR_TYPE_HARD_EXCEPTION:
5453                         if (vmx->idt_vectoring_info &
5454                             VECTORING_INFO_DELIVER_CODE_MASK) {
5455                                 has_error_code = true;
5456                                 error_code =
5457                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5458                         }
5459                         /* fall through */
5460                 case INTR_TYPE_SOFT_EXCEPTION:
5461                         kvm_clear_exception_queue(vcpu);
5462                         break;
5463                 default:
5464                         break;
5465                 }
5466         }
5467         tss_selector = exit_qualification;
5468
5469         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5470                        type != INTR_TYPE_EXT_INTR &&
5471                        type != INTR_TYPE_NMI_INTR))
5472                 skip_emulated_instruction(vcpu);
5473
5474         if (kvm_task_switch(vcpu, tss_selector,
5475                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5476                             has_error_code, error_code) == EMULATE_FAIL) {
5477                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5478                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5479                 vcpu->run->internal.ndata = 0;
5480                 return 0;
5481         }
5482
5483         /* clear all local breakpoint enable flags */
5484         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5485
5486         /*
5487          * TODO: What about debug traps on tss switch?
5488          *       Are we supposed to inject them and update dr6?
5489          */
5490
5491         return 1;
5492 }
5493
5494 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5495 {
5496         unsigned long exit_qualification;
5497         gpa_t gpa;
5498         u32 error_code;
5499         int gla_validity;
5500
5501         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5502
5503         gla_validity = (exit_qualification >> 7) & 0x3;
5504         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5505                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5506                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5507                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5508                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5509                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5510                         (long unsigned int)exit_qualification);
5511                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5512                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5513                 return 0;
5514         }
5515
5516         /*
5517          * EPT violation happened while executing iret from NMI,
5518          * "blocked by NMI" bit has to be set before next VM entry.
5519          * There are errata that may cause this bit to not be set:
5520          * AAK134, BY25.
5521          */
5522         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5523                         cpu_has_virtual_nmis() &&
5524                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5525                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5526
5527         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5528         trace_kvm_page_fault(gpa, exit_qualification);
5529
5530         /* It is a write fault? */
5531         error_code = exit_qualification & PFERR_WRITE_MASK;
5532         /* It is a fetch fault? */
5533         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5534         /* ept page table is present? */
5535         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5536
5537         vcpu->arch.exit_qualification = exit_qualification;
5538
5539         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5540 }
5541
5542 static u64 ept_rsvd_mask(u64 spte, int level)
5543 {
5544         int i;
5545         u64 mask = 0;
5546
5547         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5548                 mask |= (1ULL << i);
5549
5550         if (level == 4)
5551                 /* bits 7:3 reserved */
5552                 mask |= 0xf8;
5553         else if (spte & (1ULL << 7))
5554                 /*
5555                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5556                  * level == 1 if the hypervisor is using the ignored bit 7.
5557                  */
5558                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5559         else if (level > 1)
5560                 /* bits 6:3 reserved */
5561                 mask |= 0x78;
5562
5563         return mask;
5564 }
5565
5566 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5567                                        int level)
5568 {
5569         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5570
5571         /* 010b (write-only) */
5572         WARN_ON((spte & 0x7) == 0x2);
5573
5574         /* 110b (write/execute) */
5575         WARN_ON((spte & 0x7) == 0x6);
5576
5577         /* 100b (execute-only) and value not supported by logical processor */
5578         if (!cpu_has_vmx_ept_execute_only())
5579                 WARN_ON((spte & 0x7) == 0x4);
5580
5581         /* not 000b */
5582         if ((spte & 0x7)) {
5583                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5584
5585                 if (rsvd_bits != 0) {
5586                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5587                                          __func__, rsvd_bits);
5588                         WARN_ON(1);
5589                 }
5590
5591                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5592                 if ((rsvd_bits & 0x38) == 0) {
5593                         u64 ept_mem_type = (spte & 0x38) >> 3;
5594
5595                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5596                             ept_mem_type == 7) {
5597                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5598                                                 __func__, ept_mem_type);
5599                                 WARN_ON(1);
5600                         }
5601                 }
5602         }
5603 }
5604
5605 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5606 {
5607         u64 sptes[4];
5608         int nr_sptes, i, ret;
5609         gpa_t gpa;
5610
5611         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5612         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5613                 skip_emulated_instruction(vcpu);
5614                 return 1;
5615         }
5616
5617         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5618         if (likely(ret == RET_MMIO_PF_EMULATE))
5619                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5620                                               EMULATE_DONE;
5621
5622         if (unlikely(ret == RET_MMIO_PF_INVALID))
5623                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5624
5625         if (unlikely(ret == RET_MMIO_PF_RETRY))
5626                 return 1;
5627
5628         /* It is the real ept misconfig */
5629         printk(KERN_ERR "EPT: Misconfiguration.\n");
5630         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5631
5632         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5633
5634         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5635                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5636
5637         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5638         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5639
5640         return 0;
5641 }
5642
5643 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5644 {
5645         u32 cpu_based_vm_exec_control;
5646
5647         /* clear pending NMI */
5648         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5649         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5650         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5651         ++vcpu->stat.nmi_window_exits;
5652         kvm_make_request(KVM_REQ_EVENT, vcpu);
5653
5654         return 1;
5655 }
5656
5657 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5658 {
5659         struct vcpu_vmx *vmx = to_vmx(vcpu);
5660         enum emulation_result err = EMULATE_DONE;
5661         int ret = 1;
5662         u32 cpu_exec_ctrl;
5663         bool intr_window_requested;
5664         unsigned count = 130;
5665
5666         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5667         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5668
5669         while (vmx->emulation_required && count-- != 0) {
5670                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5671                         return handle_interrupt_window(&vmx->vcpu);
5672
5673                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5674                         return 1;
5675
5676                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5677
5678                 if (err == EMULATE_USER_EXIT) {
5679                         ++vcpu->stat.mmio_exits;
5680                         ret = 0;
5681                         goto out;
5682                 }
5683
5684                 if (err != EMULATE_DONE) {
5685                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5686                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5687                         vcpu->run->internal.ndata = 0;
5688                         return 0;
5689                 }
5690
5691                 if (vcpu->arch.halt_request) {
5692                         vcpu->arch.halt_request = 0;
5693                         ret = kvm_emulate_halt(vcpu);
5694                         goto out;
5695                 }
5696
5697                 if (signal_pending(current))
5698                         goto out;
5699                 if (need_resched())
5700                         schedule();
5701         }
5702
5703 out:
5704         return ret;
5705 }
5706
5707 static int __grow_ple_window(int val)
5708 {
5709         if (ple_window_grow < 1)
5710                 return ple_window;
5711
5712         val = min(val, ple_window_actual_max);
5713
5714         if (ple_window_grow < ple_window)
5715                 val *= ple_window_grow;
5716         else
5717                 val += ple_window_grow;
5718
5719         return val;
5720 }
5721
5722 static int __shrink_ple_window(int val, int modifier, int minimum)
5723 {
5724         if (modifier < 1)
5725                 return ple_window;
5726
5727         if (modifier < ple_window)
5728                 val /= modifier;
5729         else
5730                 val -= modifier;
5731
5732         return max(val, minimum);
5733 }
5734
5735 static void grow_ple_window(struct kvm_vcpu *vcpu)
5736 {
5737         struct vcpu_vmx *vmx = to_vmx(vcpu);
5738         int old = vmx->ple_window;
5739
5740         vmx->ple_window = __grow_ple_window(old);
5741
5742         if (vmx->ple_window != old)
5743                 vmx->ple_window_dirty = true;
5744
5745         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5746 }
5747
5748 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5749 {
5750         struct vcpu_vmx *vmx = to_vmx(vcpu);
5751         int old = vmx->ple_window;
5752
5753         vmx->ple_window = __shrink_ple_window(old,
5754                                               ple_window_shrink, ple_window);
5755
5756         if (vmx->ple_window != old)
5757                 vmx->ple_window_dirty = true;
5758
5759         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5760 }
5761
5762 /*
5763  * ple_window_actual_max is computed to be one grow_ple_window() below
5764  * ple_window_max. (See __grow_ple_window for the reason.)
5765  * This prevents overflows, because ple_window_max is int.
5766  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5767  * this process.
5768  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5769  */
5770 static void update_ple_window_actual_max(void)
5771 {
5772         ple_window_actual_max =
5773                         __shrink_ple_window(max(ple_window_max, ple_window),
5774                                             ple_window_grow, INT_MIN);
5775 }
5776
5777 static __init int hardware_setup(void)
5778 {
5779         int r = -ENOMEM, i, msr;
5780
5781         rdmsrl_safe(MSR_EFER, &host_efer);
5782
5783         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5784                 kvm_define_shared_msr(i, vmx_msr_index[i]);
5785
5786         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5787         if (!vmx_io_bitmap_a)
5788                 return r;
5789
5790         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5791         if (!vmx_io_bitmap_b)
5792                 goto out;
5793
5794         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5795         if (!vmx_msr_bitmap_legacy)
5796                 goto out1;
5797
5798         vmx_msr_bitmap_legacy_x2apic =
5799                                 (unsigned long *)__get_free_page(GFP_KERNEL);
5800         if (!vmx_msr_bitmap_legacy_x2apic)
5801                 goto out2;
5802
5803         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5804         if (!vmx_msr_bitmap_longmode)
5805                 goto out3;
5806
5807         vmx_msr_bitmap_longmode_x2apic =
5808                                 (unsigned long *)__get_free_page(GFP_KERNEL);
5809         if (!vmx_msr_bitmap_longmode_x2apic)
5810                 goto out4;
5811         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5812         if (!vmx_vmread_bitmap)
5813                 goto out5;
5814
5815         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5816         if (!vmx_vmwrite_bitmap)
5817                 goto out6;
5818
5819         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5820         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5821
5822         /*
5823          * Allow direct access to the PC debug port (it is often used for I/O
5824          * delays, but the vmexits simply slow things down).
5825          */
5826         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5827         clear_bit(0x80, vmx_io_bitmap_a);
5828
5829         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5830
5831         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5832         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5833
5834         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5835         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5836         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5837         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5838         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5839         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5840         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5841
5842         memcpy(vmx_msr_bitmap_legacy_x2apic,
5843                         vmx_msr_bitmap_legacy, PAGE_SIZE);
5844         memcpy(vmx_msr_bitmap_longmode_x2apic,
5845                         vmx_msr_bitmap_longmode, PAGE_SIZE);
5846
5847         if (enable_apicv) {
5848                 for (msr = 0x800; msr <= 0x8ff; msr++)
5849                         vmx_disable_intercept_msr_read_x2apic(msr);
5850
5851                 /* According SDM, in x2apic mode, the whole id reg is used.
5852                  * But in KVM, it only use the highest eight bits. Need to
5853                  * intercept it */
5854                 vmx_enable_intercept_msr_read_x2apic(0x802);
5855                 /* TMCCT */
5856                 vmx_enable_intercept_msr_read_x2apic(0x839);
5857                 /* TPR */
5858                 vmx_disable_intercept_msr_write_x2apic(0x808);
5859                 /* EOI */
5860                 vmx_disable_intercept_msr_write_x2apic(0x80b);
5861                 /* SELF-IPI */
5862                 vmx_disable_intercept_msr_write_x2apic(0x83f);
5863         }
5864
5865         if (enable_ept) {
5866                 kvm_mmu_set_mask_ptes(0ull,
5867                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5868                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5869                         0ull, VMX_EPT_EXECUTABLE_MASK);
5870                 ept_set_mmio_spte_mask();
5871                 kvm_enable_tdp();
5872         } else
5873                 kvm_disable_tdp();
5874
5875         update_ple_window_actual_max();
5876
5877         if (setup_vmcs_config(&vmcs_config) < 0) {
5878                 r = -EIO;
5879                 goto out7;
5880     }
5881
5882         if (boot_cpu_has(X86_FEATURE_NX))
5883                 kvm_enable_efer_bits(EFER_NX);
5884
5885         if (!cpu_has_vmx_vpid())
5886                 enable_vpid = 0;
5887         if (!cpu_has_vmx_shadow_vmcs())
5888                 enable_shadow_vmcs = 0;
5889         if (enable_shadow_vmcs)
5890                 init_vmcs_shadow_fields();
5891
5892         if (!cpu_has_vmx_ept() ||
5893             !cpu_has_vmx_ept_4levels()) {
5894                 enable_ept = 0;
5895                 enable_unrestricted_guest = 0;
5896                 enable_ept_ad_bits = 0;
5897         }
5898
5899         if (!cpu_has_vmx_ept_ad_bits())
5900                 enable_ept_ad_bits = 0;
5901
5902         if (!cpu_has_vmx_unrestricted_guest())
5903                 enable_unrestricted_guest = 0;
5904
5905         if (!cpu_has_vmx_flexpriority()) {
5906                 flexpriority_enabled = 0;
5907
5908                 /*
5909                  * set_apic_access_page_addr() is used to reload apic access
5910                  * page upon invalidation.  No need to do anything if the
5911                  * processor does not have the APIC_ACCESS_ADDR VMCS field.
5912                  */
5913                 kvm_x86_ops->set_apic_access_page_addr = NULL;
5914         }
5915
5916         if (!cpu_has_vmx_tpr_shadow())
5917                 kvm_x86_ops->update_cr8_intercept = NULL;
5918
5919         if (enable_ept && !cpu_has_vmx_ept_2m_page())
5920                 kvm_disable_largepages();
5921
5922         if (!cpu_has_vmx_ple())
5923                 ple_gap = 0;
5924
5925         if (!cpu_has_vmx_apicv())
5926                 enable_apicv = 0;
5927
5928         if (enable_apicv)
5929                 kvm_x86_ops->update_cr8_intercept = NULL;
5930         else {
5931                 kvm_x86_ops->hwapic_irr_update = NULL;
5932                 kvm_x86_ops->deliver_posted_interrupt = NULL;
5933                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5934         }
5935
5936         if (nested)
5937                 nested_vmx_setup_ctls_msrs();
5938
5939         return alloc_kvm_area();
5940
5941 out7:
5942         free_page((unsigned long)vmx_vmwrite_bitmap);
5943 out6:
5944         free_page((unsigned long)vmx_vmread_bitmap);
5945 out5:
5946         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5947 out4:
5948         free_page((unsigned long)vmx_msr_bitmap_longmode);
5949 out3:
5950         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5951 out2:
5952         free_page((unsigned long)vmx_msr_bitmap_legacy);
5953 out1:
5954         free_page((unsigned long)vmx_io_bitmap_b);
5955 out:
5956         free_page((unsigned long)vmx_io_bitmap_a);
5957
5958     return r;
5959 }
5960
5961 static __exit void hardware_unsetup(void)
5962 {
5963         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5964         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5965         free_page((unsigned long)vmx_msr_bitmap_legacy);
5966         free_page((unsigned long)vmx_msr_bitmap_longmode);
5967         free_page((unsigned long)vmx_io_bitmap_b);
5968         free_page((unsigned long)vmx_io_bitmap_a);
5969         free_page((unsigned long)vmx_vmwrite_bitmap);
5970         free_page((unsigned long)vmx_vmread_bitmap);
5971
5972         free_kvm_area();
5973 }
5974
5975 /*
5976  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5977  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5978  */
5979 static int handle_pause(struct kvm_vcpu *vcpu)
5980 {
5981         if (ple_gap)
5982                 grow_ple_window(vcpu);
5983
5984         skip_emulated_instruction(vcpu);
5985         kvm_vcpu_on_spin(vcpu);
5986
5987         return 1;
5988 }
5989
5990 static int handle_nop(struct kvm_vcpu *vcpu)
5991 {
5992         skip_emulated_instruction(vcpu);
5993         return 1;
5994 }
5995
5996 static int handle_mwait(struct kvm_vcpu *vcpu)
5997 {
5998         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5999         return handle_nop(vcpu);
6000 }
6001
6002 static int handle_monitor(struct kvm_vcpu *vcpu)
6003 {
6004         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6005         return handle_nop(vcpu);
6006 }
6007
6008 /*
6009  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6010  * We could reuse a single VMCS for all the L2 guests, but we also want the
6011  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6012  * allows keeping them loaded on the processor, and in the future will allow
6013  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6014  * every entry if they never change.
6015  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6016  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6017  *
6018  * The following functions allocate and free a vmcs02 in this pool.
6019  */
6020
6021 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6022 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6023 {
6024         struct vmcs02_list *item;
6025         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6026                 if (item->vmptr == vmx->nested.current_vmptr) {
6027                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6028                         return &item->vmcs02;
6029                 }
6030
6031         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6032                 /* Recycle the least recently used VMCS. */
6033                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6034                         struct vmcs02_list, list);
6035                 item->vmptr = vmx->nested.current_vmptr;
6036                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6037                 return &item->vmcs02;
6038         }
6039
6040         /* Create a new VMCS */
6041         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6042         if (!item)
6043                 return NULL;
6044         item->vmcs02.vmcs = alloc_vmcs();
6045         if (!item->vmcs02.vmcs) {
6046                 kfree(item);
6047                 return NULL;
6048         }
6049         loaded_vmcs_init(&item->vmcs02);
6050         item->vmptr = vmx->nested.current_vmptr;
6051         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6052         vmx->nested.vmcs02_num++;
6053         return &item->vmcs02;
6054 }
6055
6056 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6057 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6058 {
6059         struct vmcs02_list *item;
6060         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6061                 if (item->vmptr == vmptr) {
6062                         free_loaded_vmcs(&item->vmcs02);
6063                         list_del(&item->list);
6064                         kfree(item);
6065                         vmx->nested.vmcs02_num--;
6066                         return;
6067                 }
6068 }
6069
6070 /*
6071  * Free all VMCSs saved for this vcpu, except the one pointed by
6072  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6073  * must be &vmx->vmcs01.
6074  */
6075 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6076 {
6077         struct vmcs02_list *item, *n;
6078
6079         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6080         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6081                 /*
6082                  * Something will leak if the above WARN triggers.  Better than
6083                  * a use-after-free.
6084                  */
6085                 if (vmx->loaded_vmcs == &item->vmcs02)
6086                         continue;
6087
6088                 free_loaded_vmcs(&item->vmcs02);
6089                 list_del(&item->list);
6090                 kfree(item);
6091                 vmx->nested.vmcs02_num--;
6092         }
6093 }
6094
6095 /*
6096  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6097  * set the success or error code of an emulated VMX instruction, as specified
6098  * by Vol 2B, VMX Instruction Reference, "Conventions".
6099  */
6100 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6101 {
6102         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6103                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6104                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6105 }
6106
6107 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6108 {
6109         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6110                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6111                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6112                         | X86_EFLAGS_CF);
6113 }
6114
6115 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6116                                         u32 vm_instruction_error)
6117 {
6118         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6119                 /*
6120                  * failValid writes the error number to the current VMCS, which
6121                  * can't be done there isn't a current VMCS.
6122                  */
6123                 nested_vmx_failInvalid(vcpu);
6124                 return;
6125         }
6126         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6127                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6128                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6129                         | X86_EFLAGS_ZF);
6130         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6131         /*
6132          * We don't need to force a shadow sync because
6133          * VM_INSTRUCTION_ERROR is not shadowed
6134          */
6135 }
6136
6137 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6138 {
6139         struct vcpu_vmx *vmx =
6140                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6141
6142         vmx->nested.preemption_timer_expired = true;
6143         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6144         kvm_vcpu_kick(&vmx->vcpu);
6145
6146         return HRTIMER_NORESTART;
6147 }
6148
6149 /*
6150  * Decode the memory-address operand of a vmx instruction, as recorded on an
6151  * exit caused by such an instruction (run by a guest hypervisor).
6152  * On success, returns 0. When the operand is invalid, returns 1 and throws
6153  * #UD or #GP.
6154  */
6155 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6156                                  unsigned long exit_qualification,
6157                                  u32 vmx_instruction_info, gva_t *ret)
6158 {
6159         /*
6160          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6161          * Execution", on an exit, vmx_instruction_info holds most of the
6162          * addressing components of the operand. Only the displacement part
6163          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6164          * For how an actual address is calculated from all these components,
6165          * refer to Vol. 1, "Operand Addressing".
6166          */
6167         int  scaling = vmx_instruction_info & 3;
6168         int  addr_size = (vmx_instruction_info >> 7) & 7;
6169         bool is_reg = vmx_instruction_info & (1u << 10);
6170         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6171         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6172         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6173         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6174         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6175
6176         if (is_reg) {
6177                 kvm_queue_exception(vcpu, UD_VECTOR);
6178                 return 1;
6179         }
6180
6181         /* Addr = segment_base + offset */
6182         /* offset = base + [index * scale] + displacement */
6183         *ret = vmx_get_segment_base(vcpu, seg_reg);
6184         if (base_is_valid)
6185                 *ret += kvm_register_read(vcpu, base_reg);
6186         if (index_is_valid)
6187                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6188         *ret += exit_qualification; /* holds the displacement */
6189
6190         if (addr_size == 1) /* 32 bit */
6191                 *ret &= 0xffffffff;
6192
6193         /*
6194          * TODO: throw #GP (and return 1) in various cases that the VM*
6195          * instructions require it - e.g., offset beyond segment limit,
6196          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6197          * address, and so on. Currently these are not checked.
6198          */
6199         return 0;
6200 }
6201
6202 /*
6203  * This function performs the various checks including
6204  * - if it's 4KB aligned
6205  * - No bits beyond the physical address width are set
6206  * - Returns 0 on success or else 1
6207  * (Intel SDM Section 30.3)
6208  */
6209 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6210                                   gpa_t *vmpointer)
6211 {
6212         gva_t gva;
6213         gpa_t vmptr;
6214         struct x86_exception e;
6215         struct page *page;
6216         struct vcpu_vmx *vmx = to_vmx(vcpu);
6217         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6218
6219         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6220                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6221                 return 1;
6222
6223         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6224                                 sizeof(vmptr), &e)) {
6225                 kvm_inject_page_fault(vcpu, &e);
6226                 return 1;
6227         }
6228
6229         switch (exit_reason) {
6230         case EXIT_REASON_VMON:
6231                 /*
6232                  * SDM 3: 24.11.5
6233                  * The first 4 bytes of VMXON region contain the supported
6234                  * VMCS revision identifier
6235                  *
6236                  * Note - IA32_VMX_BASIC[48] will never be 1
6237                  * for the nested case;
6238                  * which replaces physical address width with 32
6239                  *
6240                  */
6241                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6242                         nested_vmx_failInvalid(vcpu);
6243                         skip_emulated_instruction(vcpu);
6244                         return 1;
6245                 }
6246
6247                 page = nested_get_page(vcpu, vmptr);
6248                 if (page == NULL ||
6249                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6250                         nested_vmx_failInvalid(vcpu);
6251                         kunmap(page);
6252                         skip_emulated_instruction(vcpu);
6253                         return 1;
6254                 }
6255                 kunmap(page);
6256                 vmx->nested.vmxon_ptr = vmptr;
6257                 break;
6258         case EXIT_REASON_VMCLEAR:
6259                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6260                         nested_vmx_failValid(vcpu,
6261                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6262                         skip_emulated_instruction(vcpu);
6263                         return 1;
6264                 }
6265
6266                 if (vmptr == vmx->nested.vmxon_ptr) {
6267                         nested_vmx_failValid(vcpu,
6268                                              VMXERR_VMCLEAR_VMXON_POINTER);
6269                         skip_emulated_instruction(vcpu);
6270                         return 1;
6271                 }
6272                 break;
6273         case EXIT_REASON_VMPTRLD:
6274                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6275                         nested_vmx_failValid(vcpu,
6276                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6277                         skip_emulated_instruction(vcpu);
6278                         return 1;
6279                 }
6280
6281                 if (vmptr == vmx->nested.vmxon_ptr) {
6282                         nested_vmx_failValid(vcpu,
6283                                              VMXERR_VMCLEAR_VMXON_POINTER);
6284                         skip_emulated_instruction(vcpu);
6285                         return 1;
6286                 }
6287                 break;
6288         default:
6289                 return 1; /* shouldn't happen */
6290         }
6291
6292         if (vmpointer)
6293                 *vmpointer = vmptr;
6294         return 0;
6295 }
6296
6297 /*
6298  * Emulate the VMXON instruction.
6299  * Currently, we just remember that VMX is active, and do not save or even
6300  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6301  * do not currently need to store anything in that guest-allocated memory
6302  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6303  * argument is different from the VMXON pointer (which the spec says they do).
6304  */
6305 static int handle_vmon(struct kvm_vcpu *vcpu)
6306 {
6307         struct kvm_segment cs;
6308         struct vcpu_vmx *vmx = to_vmx(vcpu);
6309         struct vmcs *shadow_vmcs;
6310         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6311                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6312
6313         /* The Intel VMX Instruction Reference lists a bunch of bits that
6314          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6315          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6316          * Otherwise, we should fail with #UD. We test these now:
6317          */
6318         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6319             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6320             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6321                 kvm_queue_exception(vcpu, UD_VECTOR);
6322                 return 1;
6323         }
6324
6325         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6326         if (is_long_mode(vcpu) && !cs.l) {
6327                 kvm_queue_exception(vcpu, UD_VECTOR);
6328                 return 1;
6329         }
6330
6331         if (vmx_get_cpl(vcpu)) {
6332                 kvm_inject_gp(vcpu, 0);
6333                 return 1;
6334         }
6335
6336         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6337                 return 1;
6338
6339         if (vmx->nested.vmxon) {
6340                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6341                 skip_emulated_instruction(vcpu);
6342                 return 1;
6343         }
6344
6345         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6346                         != VMXON_NEEDED_FEATURES) {
6347                 kvm_inject_gp(vcpu, 0);
6348                 return 1;
6349         }
6350
6351         if (enable_shadow_vmcs) {
6352                 shadow_vmcs = alloc_vmcs();
6353                 if (!shadow_vmcs)
6354                         return -ENOMEM;
6355                 /* mark vmcs as shadow */
6356                 shadow_vmcs->revision_id |= (1u << 31);
6357                 /* init shadow vmcs */
6358                 vmcs_clear(shadow_vmcs);
6359                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6360         }
6361
6362         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6363         vmx->nested.vmcs02_num = 0;
6364
6365         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6366                      HRTIMER_MODE_REL);
6367         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6368
6369         vmx->nested.vmxon = true;
6370
6371         skip_emulated_instruction(vcpu);
6372         nested_vmx_succeed(vcpu);
6373         return 1;
6374 }
6375
6376 /*
6377  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6378  * for running VMX instructions (except VMXON, whose prerequisites are
6379  * slightly different). It also specifies what exception to inject otherwise.
6380  */
6381 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6382 {
6383         struct kvm_segment cs;
6384         struct vcpu_vmx *vmx = to_vmx(vcpu);
6385
6386         if (!vmx->nested.vmxon) {
6387                 kvm_queue_exception(vcpu, UD_VECTOR);
6388                 return 0;
6389         }
6390
6391         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6392         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6393             (is_long_mode(vcpu) && !cs.l)) {
6394                 kvm_queue_exception(vcpu, UD_VECTOR);
6395                 return 0;
6396         }
6397
6398         if (vmx_get_cpl(vcpu)) {
6399                 kvm_inject_gp(vcpu, 0);
6400                 return 0;
6401         }
6402
6403         return 1;
6404 }
6405
6406 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6407 {
6408         u32 exec_control;
6409         if (vmx->nested.current_vmptr == -1ull)
6410                 return;
6411
6412         /* current_vmptr and current_vmcs12 are always set/reset together */
6413         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6414                 return;
6415
6416         if (enable_shadow_vmcs) {
6417                 /* copy to memory all shadowed fields in case
6418                    they were modified */
6419                 copy_shadow_to_vmcs12(vmx);
6420                 vmx->nested.sync_shadow_vmcs = false;
6421                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6422                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6423                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6424                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6425         }
6426         kunmap(vmx->nested.current_vmcs12_page);
6427         nested_release_page(vmx->nested.current_vmcs12_page);
6428         vmx->nested.current_vmptr = -1ull;
6429         vmx->nested.current_vmcs12 = NULL;
6430 }
6431
6432 /*
6433  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6434  * just stops using VMX.
6435  */
6436 static void free_nested(struct vcpu_vmx *vmx)
6437 {
6438         if (!vmx->nested.vmxon)
6439                 return;
6440
6441         vmx->nested.vmxon = false;
6442         nested_release_vmcs12(vmx);
6443         if (enable_shadow_vmcs)
6444                 free_vmcs(vmx->nested.current_shadow_vmcs);
6445         /* Unpin physical memory we referred to in current vmcs02 */
6446         if (vmx->nested.apic_access_page) {
6447                 nested_release_page(vmx->nested.apic_access_page);
6448                 vmx->nested.apic_access_page = NULL;
6449         }
6450         if (vmx->nested.virtual_apic_page) {
6451                 nested_release_page(vmx->nested.virtual_apic_page);
6452                 vmx->nested.virtual_apic_page = NULL;
6453         }
6454
6455         nested_free_all_saved_vmcss(vmx);
6456 }
6457
6458 /* Emulate the VMXOFF instruction */
6459 static int handle_vmoff(struct kvm_vcpu *vcpu)
6460 {
6461         if (!nested_vmx_check_permission(vcpu))
6462                 return 1;
6463         free_nested(to_vmx(vcpu));
6464         skip_emulated_instruction(vcpu);
6465         nested_vmx_succeed(vcpu);
6466         return 1;
6467 }
6468
6469 /* Emulate the VMCLEAR instruction */
6470 static int handle_vmclear(struct kvm_vcpu *vcpu)
6471 {
6472         struct vcpu_vmx *vmx = to_vmx(vcpu);
6473         gpa_t vmptr;
6474         struct vmcs12 *vmcs12;
6475         struct page *page;
6476
6477         if (!nested_vmx_check_permission(vcpu))
6478                 return 1;
6479
6480         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6481                 return 1;
6482
6483         if (vmptr == vmx->nested.current_vmptr)
6484                 nested_release_vmcs12(vmx);
6485
6486         page = nested_get_page(vcpu, vmptr);
6487         if (page == NULL) {
6488                 /*
6489                  * For accurate processor emulation, VMCLEAR beyond available
6490                  * physical memory should do nothing at all. However, it is
6491                  * possible that a nested vmx bug, not a guest hypervisor bug,
6492                  * resulted in this case, so let's shut down before doing any
6493                  * more damage:
6494                  */
6495                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6496                 return 1;
6497         }
6498         vmcs12 = kmap(page);
6499         vmcs12->launch_state = 0;
6500         kunmap(page);
6501         nested_release_page(page);
6502
6503         nested_free_vmcs02(vmx, vmptr);
6504
6505         skip_emulated_instruction(vcpu);
6506         nested_vmx_succeed(vcpu);
6507         return 1;
6508 }
6509
6510 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6511
6512 /* Emulate the VMLAUNCH instruction */
6513 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6514 {
6515         return nested_vmx_run(vcpu, true);
6516 }
6517
6518 /* Emulate the VMRESUME instruction */
6519 static int handle_vmresume(struct kvm_vcpu *vcpu)
6520 {
6521
6522         return nested_vmx_run(vcpu, false);
6523 }
6524
6525 enum vmcs_field_type {
6526         VMCS_FIELD_TYPE_U16 = 0,
6527         VMCS_FIELD_TYPE_U64 = 1,
6528         VMCS_FIELD_TYPE_U32 = 2,
6529         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6530 };
6531
6532 static inline int vmcs_field_type(unsigned long field)
6533 {
6534         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6535                 return VMCS_FIELD_TYPE_U32;
6536         return (field >> 13) & 0x3 ;
6537 }
6538
6539 static inline int vmcs_field_readonly(unsigned long field)
6540 {
6541         return (((field >> 10) & 0x3) == 1);
6542 }
6543
6544 /*
6545  * Read a vmcs12 field. Since these can have varying lengths and we return
6546  * one type, we chose the biggest type (u64) and zero-extend the return value
6547  * to that size. Note that the caller, handle_vmread, might need to use only
6548  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6549  * 64-bit fields are to be returned).
6550  */
6551 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6552                                   unsigned long field, u64 *ret)
6553 {
6554         short offset = vmcs_field_to_offset(field);
6555         char *p;
6556
6557         if (offset < 0)
6558                 return offset;
6559
6560         p = ((char *)(get_vmcs12(vcpu))) + offset;
6561
6562         switch (vmcs_field_type(field)) {
6563         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6564                 *ret = *((natural_width *)p);
6565                 return 0;
6566         case VMCS_FIELD_TYPE_U16:
6567                 *ret = *((u16 *)p);
6568                 return 0;
6569         case VMCS_FIELD_TYPE_U32:
6570                 *ret = *((u32 *)p);
6571                 return 0;
6572         case VMCS_FIELD_TYPE_U64:
6573                 *ret = *((u64 *)p);
6574                 return 0;
6575         default:
6576                 WARN_ON(1);
6577                 return -ENOENT;
6578         }
6579 }
6580
6581
6582 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6583                                    unsigned long field, u64 field_value){
6584         short offset = vmcs_field_to_offset(field);
6585         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6586         if (offset < 0)
6587                 return offset;
6588
6589         switch (vmcs_field_type(field)) {
6590         case VMCS_FIELD_TYPE_U16:
6591                 *(u16 *)p = field_value;
6592                 return 0;
6593         case VMCS_FIELD_TYPE_U32:
6594                 *(u32 *)p = field_value;
6595                 return 0;
6596         case VMCS_FIELD_TYPE_U64:
6597                 *(u64 *)p = field_value;
6598                 return 0;
6599         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6600                 *(natural_width *)p = field_value;
6601                 return 0;
6602         default:
6603                 WARN_ON(1);
6604                 return -ENOENT;
6605         }
6606
6607 }
6608
6609 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6610 {
6611         int i;
6612         unsigned long field;
6613         u64 field_value;
6614         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6615         const unsigned long *fields = shadow_read_write_fields;
6616         const int num_fields = max_shadow_read_write_fields;
6617
6618         preempt_disable();
6619
6620         vmcs_load(shadow_vmcs);
6621
6622         for (i = 0; i < num_fields; i++) {
6623                 field = fields[i];
6624                 switch (vmcs_field_type(field)) {
6625                 case VMCS_FIELD_TYPE_U16:
6626                         field_value = vmcs_read16(field);
6627                         break;
6628                 case VMCS_FIELD_TYPE_U32:
6629                         field_value = vmcs_read32(field);
6630                         break;
6631                 case VMCS_FIELD_TYPE_U64:
6632                         field_value = vmcs_read64(field);
6633                         break;
6634                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6635                         field_value = vmcs_readl(field);
6636                         break;
6637                 default:
6638                         WARN_ON(1);
6639                         continue;
6640                 }
6641                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6642         }
6643
6644         vmcs_clear(shadow_vmcs);
6645         vmcs_load(vmx->loaded_vmcs->vmcs);
6646
6647         preempt_enable();
6648 }
6649
6650 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6651 {
6652         const unsigned long *fields[] = {
6653                 shadow_read_write_fields,
6654                 shadow_read_only_fields
6655         };
6656         const int max_fields[] = {
6657                 max_shadow_read_write_fields,
6658                 max_shadow_read_only_fields
6659         };
6660         int i, q;
6661         unsigned long field;
6662         u64 field_value = 0;
6663         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6664
6665         vmcs_load(shadow_vmcs);
6666
6667         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6668                 for (i = 0; i < max_fields[q]; i++) {
6669                         field = fields[q][i];
6670                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6671
6672                         switch (vmcs_field_type(field)) {
6673                         case VMCS_FIELD_TYPE_U16:
6674                                 vmcs_write16(field, (u16)field_value);
6675                                 break;
6676                         case VMCS_FIELD_TYPE_U32:
6677                                 vmcs_write32(field, (u32)field_value);
6678                                 break;
6679                         case VMCS_FIELD_TYPE_U64:
6680                                 vmcs_write64(field, (u64)field_value);
6681                                 break;
6682                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6683                                 vmcs_writel(field, (long)field_value);
6684                                 break;
6685                         default:
6686                                 WARN_ON(1);
6687                                 break;
6688                         }
6689                 }
6690         }
6691
6692         vmcs_clear(shadow_vmcs);
6693         vmcs_load(vmx->loaded_vmcs->vmcs);
6694 }
6695
6696 /*
6697  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6698  * used before) all generate the same failure when it is missing.
6699  */
6700 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6701 {
6702         struct vcpu_vmx *vmx = to_vmx(vcpu);
6703         if (vmx->nested.current_vmptr == -1ull) {
6704                 nested_vmx_failInvalid(vcpu);
6705                 skip_emulated_instruction(vcpu);
6706                 return 0;
6707         }
6708         return 1;
6709 }
6710
6711 static int handle_vmread(struct kvm_vcpu *vcpu)
6712 {
6713         unsigned long field;
6714         u64 field_value;
6715         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6716         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6717         gva_t gva = 0;
6718
6719         if (!nested_vmx_check_permission(vcpu) ||
6720             !nested_vmx_check_vmcs12(vcpu))
6721                 return 1;
6722
6723         /* Decode instruction info and find the field to read */
6724         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6725         /* Read the field, zero-extended to a u64 field_value */
6726         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6727                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6728                 skip_emulated_instruction(vcpu);
6729                 return 1;
6730         }
6731         /*
6732          * Now copy part of this value to register or memory, as requested.
6733          * Note that the number of bits actually copied is 32 or 64 depending
6734          * on the guest's mode (32 or 64 bit), not on the given field's length.
6735          */
6736         if (vmx_instruction_info & (1u << 10)) {
6737                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6738                         field_value);
6739         } else {
6740                 if (get_vmx_mem_address(vcpu, exit_qualification,
6741                                 vmx_instruction_info, &gva))
6742                         return 1;
6743                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6744                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6745                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6746         }
6747
6748         nested_vmx_succeed(vcpu);
6749         skip_emulated_instruction(vcpu);
6750         return 1;
6751 }
6752
6753
6754 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6755 {
6756         unsigned long field;
6757         gva_t gva;
6758         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6759         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6760         /* The value to write might be 32 or 64 bits, depending on L1's long
6761          * mode, and eventually we need to write that into a field of several
6762          * possible lengths. The code below first zero-extends the value to 64
6763          * bit (field_value), and then copies only the approriate number of
6764          * bits into the vmcs12 field.
6765          */
6766         u64 field_value = 0;
6767         struct x86_exception e;
6768
6769         if (!nested_vmx_check_permission(vcpu) ||
6770             !nested_vmx_check_vmcs12(vcpu))
6771                 return 1;
6772
6773         if (vmx_instruction_info & (1u << 10))
6774                 field_value = kvm_register_readl(vcpu,
6775                         (((vmx_instruction_info) >> 3) & 0xf));
6776         else {
6777                 if (get_vmx_mem_address(vcpu, exit_qualification,
6778                                 vmx_instruction_info, &gva))
6779                         return 1;
6780                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6781                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
6782                         kvm_inject_page_fault(vcpu, &e);
6783                         return 1;
6784                 }
6785         }
6786
6787
6788         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6789         if (vmcs_field_readonly(field)) {
6790                 nested_vmx_failValid(vcpu,
6791                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6792                 skip_emulated_instruction(vcpu);
6793                 return 1;
6794         }
6795
6796         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
6797                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6798                 skip_emulated_instruction(vcpu);
6799                 return 1;
6800         }
6801
6802         nested_vmx_succeed(vcpu);
6803         skip_emulated_instruction(vcpu);
6804         return 1;
6805 }
6806
6807 /* Emulate the VMPTRLD instruction */
6808 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6809 {
6810         struct vcpu_vmx *vmx = to_vmx(vcpu);
6811         gpa_t vmptr;
6812         u32 exec_control;
6813
6814         if (!nested_vmx_check_permission(vcpu))
6815                 return 1;
6816
6817         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
6818                 return 1;
6819
6820         if (vmx->nested.current_vmptr != vmptr) {
6821                 struct vmcs12 *new_vmcs12;
6822                 struct page *page;
6823                 page = nested_get_page(vcpu, vmptr);
6824                 if (page == NULL) {
6825                         nested_vmx_failInvalid(vcpu);
6826                         skip_emulated_instruction(vcpu);
6827                         return 1;
6828                 }
6829                 new_vmcs12 = kmap(page);
6830                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6831                         kunmap(page);
6832                         nested_release_page_clean(page);
6833                         nested_vmx_failValid(vcpu,
6834                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6835                         skip_emulated_instruction(vcpu);
6836                         return 1;
6837                 }
6838
6839                 nested_release_vmcs12(vmx);
6840                 vmx->nested.current_vmptr = vmptr;
6841                 vmx->nested.current_vmcs12 = new_vmcs12;
6842                 vmx->nested.current_vmcs12_page = page;
6843                 if (enable_shadow_vmcs) {
6844                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6845                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6846                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6847                         vmcs_write64(VMCS_LINK_POINTER,
6848                                      __pa(vmx->nested.current_shadow_vmcs));
6849                         vmx->nested.sync_shadow_vmcs = true;
6850                 }
6851         }
6852
6853         nested_vmx_succeed(vcpu);
6854         skip_emulated_instruction(vcpu);
6855         return 1;
6856 }
6857
6858 /* Emulate the VMPTRST instruction */
6859 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6860 {
6861         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6862         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6863         gva_t vmcs_gva;
6864         struct x86_exception e;
6865
6866         if (!nested_vmx_check_permission(vcpu))
6867                 return 1;
6868
6869         if (get_vmx_mem_address(vcpu, exit_qualification,
6870                         vmx_instruction_info, &vmcs_gva))
6871                 return 1;
6872         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6873         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6874                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6875                                  sizeof(u64), &e)) {
6876                 kvm_inject_page_fault(vcpu, &e);
6877                 return 1;
6878         }
6879         nested_vmx_succeed(vcpu);
6880         skip_emulated_instruction(vcpu);
6881         return 1;
6882 }
6883
6884 /* Emulate the INVEPT instruction */
6885 static int handle_invept(struct kvm_vcpu *vcpu)
6886 {
6887         u32 vmx_instruction_info, types;
6888         unsigned long type;
6889         gva_t gva;
6890         struct x86_exception e;
6891         struct {
6892                 u64 eptp, gpa;
6893         } operand;
6894
6895         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6896             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6897                 kvm_queue_exception(vcpu, UD_VECTOR);
6898                 return 1;
6899         }
6900
6901         if (!nested_vmx_check_permission(vcpu))
6902                 return 1;
6903
6904         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6905                 kvm_queue_exception(vcpu, UD_VECTOR);
6906                 return 1;
6907         }
6908
6909         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6910         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
6911
6912         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6913
6914         if (!(types & (1UL << type))) {
6915                 nested_vmx_failValid(vcpu,
6916                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6917                 return 1;
6918         }
6919
6920         /* According to the Intel VMX instruction reference, the memory
6921          * operand is read even if it isn't needed (e.g., for type==global)
6922          */
6923         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6924                         vmx_instruction_info, &gva))
6925                 return 1;
6926         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6927                                 sizeof(operand), &e)) {
6928                 kvm_inject_page_fault(vcpu, &e);
6929                 return 1;
6930         }
6931
6932         switch (type) {
6933         case VMX_EPT_EXTENT_GLOBAL:
6934                 kvm_mmu_sync_roots(vcpu);
6935                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6936                 nested_vmx_succeed(vcpu);
6937                 break;
6938         default:
6939                 /* Trap single context invalidation invept calls */
6940                 BUG_ON(1);
6941                 break;
6942         }
6943
6944         skip_emulated_instruction(vcpu);
6945         return 1;
6946 }
6947
6948 static int handle_invvpid(struct kvm_vcpu *vcpu)
6949 {
6950         kvm_queue_exception(vcpu, UD_VECTOR);
6951         return 1;
6952 }
6953
6954 /*
6955  * The exit handlers return 1 if the exit was handled fully and guest execution
6956  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6957  * to be done to userspace and return 0.
6958  */
6959 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6960         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6961         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6962         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6963         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6964         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6965         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6966         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6967         [EXIT_REASON_CPUID]                   = handle_cpuid,
6968         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6969         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6970         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6971         [EXIT_REASON_HLT]                     = handle_halt,
6972         [EXIT_REASON_INVD]                    = handle_invd,
6973         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6974         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6975         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6976         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6977         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6978         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6979         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6980         [EXIT_REASON_VMREAD]                  = handle_vmread,
6981         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6982         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6983         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6984         [EXIT_REASON_VMON]                    = handle_vmon,
6985         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6986         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6987         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6988         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6989         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6990         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6991         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6992         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6993         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6994         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6995         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6996         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
6997         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
6998         [EXIT_REASON_INVEPT]                  = handle_invept,
6999         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7000         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7001         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7002 };
7003
7004 static const int kvm_vmx_max_exit_handlers =
7005         ARRAY_SIZE(kvm_vmx_exit_handlers);
7006
7007 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7008                                        struct vmcs12 *vmcs12)
7009 {
7010         unsigned long exit_qualification;
7011         gpa_t bitmap, last_bitmap;
7012         unsigned int port;
7013         int size;
7014         u8 b;
7015
7016         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7017                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7018
7019         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7020
7021         port = exit_qualification >> 16;
7022         size = (exit_qualification & 7) + 1;
7023
7024         last_bitmap = (gpa_t)-1;
7025         b = -1;
7026
7027         while (size > 0) {
7028                 if (port < 0x8000)
7029                         bitmap = vmcs12->io_bitmap_a;
7030                 else if (port < 0x10000)
7031                         bitmap = vmcs12->io_bitmap_b;
7032                 else
7033                         return 1;
7034                 bitmap += (port & 0x7fff) / 8;
7035
7036                 if (last_bitmap != bitmap)
7037                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7038                                 return 1;
7039                 if (b & (1 << (port & 7)))
7040                         return 1;
7041
7042                 port++;
7043                 size--;
7044                 last_bitmap = bitmap;
7045         }
7046
7047         return 0;
7048 }
7049
7050 /*
7051  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7052  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7053  * disinterest in the current event (read or write a specific MSR) by using an
7054  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7055  */
7056 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7057         struct vmcs12 *vmcs12, u32 exit_reason)
7058 {
7059         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7060         gpa_t bitmap;
7061
7062         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7063                 return 1;
7064
7065         /*
7066          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7067          * for the four combinations of read/write and low/high MSR numbers.
7068          * First we need to figure out which of the four to use:
7069          */
7070         bitmap = vmcs12->msr_bitmap;
7071         if (exit_reason == EXIT_REASON_MSR_WRITE)
7072                 bitmap += 2048;
7073         if (msr_index >= 0xc0000000) {
7074                 msr_index -= 0xc0000000;
7075                 bitmap += 1024;
7076         }
7077
7078         /* Then read the msr_index'th bit from this bitmap: */
7079         if (msr_index < 1024*8) {
7080                 unsigned char b;
7081                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7082                         return 1;
7083                 return 1 & (b >> (msr_index & 7));
7084         } else
7085                 return 1; /* let L1 handle the wrong parameter */
7086 }
7087
7088 /*
7089  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7090  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7091  * intercept (via guest_host_mask etc.) the current event.
7092  */
7093 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7094         struct vmcs12 *vmcs12)
7095 {
7096         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7097         int cr = exit_qualification & 15;
7098         int reg = (exit_qualification >> 8) & 15;
7099         unsigned long val = kvm_register_readl(vcpu, reg);
7100
7101         switch ((exit_qualification >> 4) & 3) {
7102         case 0: /* mov to cr */
7103                 switch (cr) {
7104                 case 0:
7105                         if (vmcs12->cr0_guest_host_mask &
7106                             (val ^ vmcs12->cr0_read_shadow))
7107                                 return 1;
7108                         break;
7109                 case 3:
7110                         if ((vmcs12->cr3_target_count >= 1 &&
7111                                         vmcs12->cr3_target_value0 == val) ||
7112                                 (vmcs12->cr3_target_count >= 2 &&
7113                                         vmcs12->cr3_target_value1 == val) ||
7114                                 (vmcs12->cr3_target_count >= 3 &&
7115                                         vmcs12->cr3_target_value2 == val) ||
7116                                 (vmcs12->cr3_target_count >= 4 &&
7117                                         vmcs12->cr3_target_value3 == val))
7118                                 return 0;
7119                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7120                                 return 1;
7121                         break;
7122                 case 4:
7123                         if (vmcs12->cr4_guest_host_mask &
7124                             (vmcs12->cr4_read_shadow ^ val))
7125                                 return 1;
7126                         break;
7127                 case 8:
7128                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7129                                 return 1;
7130                         break;
7131                 }
7132                 break;
7133         case 2: /* clts */
7134                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7135                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7136                         return 1;
7137                 break;
7138         case 1: /* mov from cr */
7139                 switch (cr) {
7140                 case 3:
7141                         if (vmcs12->cpu_based_vm_exec_control &
7142                             CPU_BASED_CR3_STORE_EXITING)
7143                                 return 1;
7144                         break;
7145                 case 8:
7146                         if (vmcs12->cpu_based_vm_exec_control &
7147                             CPU_BASED_CR8_STORE_EXITING)
7148                                 return 1;
7149                         break;
7150                 }
7151                 break;
7152         case 3: /* lmsw */
7153                 /*
7154                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7155                  * cr0. Other attempted changes are ignored, with no exit.
7156                  */
7157                 if (vmcs12->cr0_guest_host_mask & 0xe &
7158                     (val ^ vmcs12->cr0_read_shadow))
7159                         return 1;
7160                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7161                     !(vmcs12->cr0_read_shadow & 0x1) &&
7162                     (val & 0x1))
7163                         return 1;
7164                 break;
7165         }
7166         return 0;
7167 }
7168
7169 /*
7170  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7171  * should handle it ourselves in L0 (and then continue L2). Only call this
7172  * when in is_guest_mode (L2).
7173  */
7174 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7175 {
7176         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7177         struct vcpu_vmx *vmx = to_vmx(vcpu);
7178         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7179         u32 exit_reason = vmx->exit_reason;
7180
7181         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7182                                 vmcs_readl(EXIT_QUALIFICATION),
7183                                 vmx->idt_vectoring_info,
7184                                 intr_info,
7185                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7186                                 KVM_ISA_VMX);
7187
7188         if (vmx->nested.nested_run_pending)
7189                 return 0;
7190
7191         if (unlikely(vmx->fail)) {
7192                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7193                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7194                 return 1;
7195         }
7196
7197         switch (exit_reason) {
7198         case EXIT_REASON_EXCEPTION_NMI:
7199                 if (!is_exception(intr_info))
7200                         return 0;
7201                 else if (is_page_fault(intr_info))
7202                         return enable_ept;
7203                 else if (is_no_device(intr_info) &&
7204                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7205                         return 0;
7206                 return vmcs12->exception_bitmap &
7207                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7208         case EXIT_REASON_EXTERNAL_INTERRUPT:
7209                 return 0;
7210         case EXIT_REASON_TRIPLE_FAULT:
7211                 return 1;
7212         case EXIT_REASON_PENDING_INTERRUPT:
7213                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7214         case EXIT_REASON_NMI_WINDOW:
7215                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7216         case EXIT_REASON_TASK_SWITCH:
7217                 return 1;
7218         case EXIT_REASON_CPUID:
7219                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7220                         return 0;
7221                 return 1;
7222         case EXIT_REASON_HLT:
7223                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7224         case EXIT_REASON_INVD:
7225                 return 1;
7226         case EXIT_REASON_INVLPG:
7227                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7228         case EXIT_REASON_RDPMC:
7229                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7230         case EXIT_REASON_RDTSC:
7231                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7232         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7233         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7234         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7235         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7236         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7237         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7238                 /*
7239                  * VMX instructions trap unconditionally. This allows L1 to
7240                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7241                  */
7242                 return 1;
7243         case EXIT_REASON_CR_ACCESS:
7244                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7245         case EXIT_REASON_DR_ACCESS:
7246                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7247         case EXIT_REASON_IO_INSTRUCTION:
7248                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7249         case EXIT_REASON_MSR_READ:
7250         case EXIT_REASON_MSR_WRITE:
7251                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7252         case EXIT_REASON_INVALID_STATE:
7253                 return 1;
7254         case EXIT_REASON_MWAIT_INSTRUCTION:
7255                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7256         case EXIT_REASON_MONITOR_INSTRUCTION:
7257                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7258         case EXIT_REASON_PAUSE_INSTRUCTION:
7259                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7260                         nested_cpu_has2(vmcs12,
7261                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7262         case EXIT_REASON_MCE_DURING_VMENTRY:
7263                 return 0;
7264         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7265                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7266         case EXIT_REASON_APIC_ACCESS:
7267                 return nested_cpu_has2(vmcs12,
7268                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7269         case EXIT_REASON_EPT_VIOLATION:
7270                 /*
7271                  * L0 always deals with the EPT violation. If nested EPT is
7272                  * used, and the nested mmu code discovers that the address is
7273                  * missing in the guest EPT table (EPT12), the EPT violation
7274                  * will be injected with nested_ept_inject_page_fault()
7275                  */
7276                 return 0;
7277         case EXIT_REASON_EPT_MISCONFIG:
7278                 /*
7279                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7280                  * table (shadow on EPT) or a merged EPT table that L0 built
7281                  * (EPT on EPT). So any problems with the structure of the
7282                  * table is L0's fault.
7283                  */
7284                 return 0;
7285         case EXIT_REASON_WBINVD:
7286                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7287         case EXIT_REASON_XSETBV:
7288                 return 1;
7289         default:
7290                 return 1;
7291         }
7292 }
7293
7294 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7295 {
7296         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7297         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7298 }
7299
7300 /*
7301  * The guest has exited.  See if we can fix it or if we need userspace
7302  * assistance.
7303  */
7304 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7305 {
7306         struct vcpu_vmx *vmx = to_vmx(vcpu);
7307         u32 exit_reason = vmx->exit_reason;
7308         u32 vectoring_info = vmx->idt_vectoring_info;
7309
7310         /* If guest state is invalid, start emulating */
7311         if (vmx->emulation_required)
7312                 return handle_invalid_guest_state(vcpu);
7313
7314         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7315                 nested_vmx_vmexit(vcpu, exit_reason,
7316                                   vmcs_read32(VM_EXIT_INTR_INFO),
7317                                   vmcs_readl(EXIT_QUALIFICATION));
7318                 return 1;
7319         }
7320
7321         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7322                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7323                 vcpu->run->fail_entry.hardware_entry_failure_reason
7324                         = exit_reason;
7325                 return 0;
7326         }
7327
7328         if (unlikely(vmx->fail)) {
7329                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7330                 vcpu->run->fail_entry.hardware_entry_failure_reason
7331                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7332                 return 0;
7333         }
7334
7335         /*
7336          * Note:
7337          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7338          * delivery event since it indicates guest is accessing MMIO.
7339          * The vm-exit can be triggered again after return to guest that
7340          * will cause infinite loop.
7341          */
7342         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7343                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7344                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7345                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7346                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7347                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7348                 vcpu->run->internal.ndata = 2;
7349                 vcpu->run->internal.data[0] = vectoring_info;
7350                 vcpu->run->internal.data[1] = exit_reason;
7351                 return 0;
7352         }
7353
7354         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7355             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7356                                         get_vmcs12(vcpu))))) {
7357                 if (vmx_interrupt_allowed(vcpu)) {
7358                         vmx->soft_vnmi_blocked = 0;
7359                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7360                            vcpu->arch.nmi_pending) {
7361                         /*
7362                          * This CPU don't support us in finding the end of an
7363                          * NMI-blocked window if the guest runs with IRQs
7364                          * disabled. So we pull the trigger after 1 s of
7365                          * futile waiting, but inform the user about this.
7366                          */
7367                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7368                                "state on VCPU %d after 1 s timeout\n",
7369                                __func__, vcpu->vcpu_id);
7370                         vmx->soft_vnmi_blocked = 0;
7371                 }
7372         }
7373
7374         if (exit_reason < kvm_vmx_max_exit_handlers
7375             && kvm_vmx_exit_handlers[exit_reason])
7376                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7377         else {
7378                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7379                 kvm_queue_exception(vcpu, UD_VECTOR);
7380                 return 1;
7381         }
7382 }
7383
7384 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7385 {
7386         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7387
7388         if (is_guest_mode(vcpu) &&
7389                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7390                 return;
7391
7392         if (irr == -1 || tpr < irr) {
7393                 vmcs_write32(TPR_THRESHOLD, 0);
7394                 return;
7395         }
7396
7397         vmcs_write32(TPR_THRESHOLD, irr);
7398 }
7399
7400 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7401 {
7402         u32 sec_exec_control;
7403
7404         /*
7405          * There is not point to enable virtualize x2apic without enable
7406          * apicv
7407          */
7408         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7409                                 !vmx_vm_has_apicv(vcpu->kvm))
7410                 return;
7411
7412         if (!vm_need_tpr_shadow(vcpu->kvm))
7413                 return;
7414
7415         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7416
7417         if (set) {
7418                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7419                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7420         } else {
7421                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7422                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7423         }
7424         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7425
7426         vmx_set_msr_bitmap(vcpu);
7427 }
7428
7429 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7430 {
7431         struct vcpu_vmx *vmx = to_vmx(vcpu);
7432
7433         /*
7434          * Currently we do not handle the nested case where L2 has an
7435          * APIC access page of its own; that page is still pinned.
7436          * Hence, we skip the case where the VCPU is in guest mode _and_
7437          * L1 prepared an APIC access page for L2.
7438          *
7439          * For the case where L1 and L2 share the same APIC access page
7440          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7441          * in the vmcs12), this function will only update either the vmcs01
7442          * or the vmcs02.  If the former, the vmcs02 will be updated by
7443          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7444          * the next L2->L1 exit.
7445          */
7446         if (!is_guest_mode(vcpu) ||
7447             !nested_cpu_has2(vmx->nested.current_vmcs12,
7448                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7449                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7450 }
7451
7452 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7453 {
7454         u16 status;
7455         u8 old;
7456
7457         if (!vmx_vm_has_apicv(kvm))
7458                 return;
7459
7460         if (isr == -1)
7461                 isr = 0;
7462
7463         status = vmcs_read16(GUEST_INTR_STATUS);
7464         old = status >> 8;
7465         if (isr != old) {
7466                 status &= 0xff;
7467                 status |= isr << 8;
7468                 vmcs_write16(GUEST_INTR_STATUS, status);
7469         }
7470 }
7471
7472 static void vmx_set_rvi(int vector)
7473 {
7474         u16 status;
7475         u8 old;
7476
7477         if (vector == -1)
7478                 vector = 0;
7479
7480         status = vmcs_read16(GUEST_INTR_STATUS);
7481         old = (u8)status & 0xff;
7482         if ((u8)vector != old) {
7483                 status &= ~0xff;
7484                 status |= (u8)vector;
7485                 vmcs_write16(GUEST_INTR_STATUS, status);
7486         }
7487 }
7488
7489 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7490 {
7491         if (!is_guest_mode(vcpu)) {
7492                 vmx_set_rvi(max_irr);
7493                 return;
7494         }
7495
7496         if (max_irr == -1)
7497                 return;
7498
7499         /*
7500          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7501          * handles it.
7502          */
7503         if (nested_exit_on_intr(vcpu))
7504                 return;
7505
7506         /*
7507          * Else, fall back to pre-APICv interrupt injection since L2
7508          * is run without virtual interrupt delivery.
7509          */
7510         if (!kvm_event_needs_reinjection(vcpu) &&
7511             vmx_interrupt_allowed(vcpu)) {
7512                 kvm_queue_interrupt(vcpu, max_irr, false);
7513                 vmx_inject_irq(vcpu);
7514         }
7515 }
7516
7517 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7518 {
7519         if (!vmx_vm_has_apicv(vcpu->kvm))
7520                 return;
7521
7522         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7523         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7524         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7525         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7526 }
7527
7528 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7529 {
7530         u32 exit_intr_info;
7531
7532         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7533               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7534                 return;
7535
7536         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7537         exit_intr_info = vmx->exit_intr_info;
7538
7539         /* Handle machine checks before interrupts are enabled */
7540         if (is_machine_check(exit_intr_info))
7541                 kvm_machine_check();
7542
7543         /* We need to handle NMIs before interrupts are enabled */
7544         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7545             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7546                 kvm_before_handle_nmi(&vmx->vcpu);
7547                 asm("int $2");
7548                 kvm_after_handle_nmi(&vmx->vcpu);
7549         }
7550 }
7551
7552 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7553 {
7554         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7555
7556         /*
7557          * If external interrupt exists, IF bit is set in rflags/eflags on the
7558          * interrupt stack frame, and interrupt will be enabled on a return
7559          * from interrupt handler.
7560          */
7561         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7562                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7563                 unsigned int vector;
7564                 unsigned long entry;
7565                 gate_desc *desc;
7566                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7567 #ifdef CONFIG_X86_64
7568                 unsigned long tmp;
7569 #endif
7570
7571                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7572                 desc = (gate_desc *)vmx->host_idt_base + vector;
7573                 entry = gate_offset(*desc);
7574                 asm volatile(
7575 #ifdef CONFIG_X86_64
7576                         "mov %%" _ASM_SP ", %[sp]\n\t"
7577                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7578                         "push $%c[ss]\n\t"
7579                         "push %[sp]\n\t"
7580 #endif
7581                         "pushf\n\t"
7582                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7583                         __ASM_SIZE(push) " $%c[cs]\n\t"
7584                         "call *%[entry]\n\t"
7585                         :
7586 #ifdef CONFIG_X86_64
7587                         [sp]"=&r"(tmp)
7588 #endif
7589                         :
7590                         [entry]"r"(entry),
7591                         [ss]"i"(__KERNEL_DS),
7592                         [cs]"i"(__KERNEL_CS)
7593                         );
7594         } else
7595                 local_irq_enable();
7596 }
7597
7598 static bool vmx_mpx_supported(void)
7599 {
7600         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7601                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7602 }
7603
7604 static bool vmx_xsaves_supported(void)
7605 {
7606         return vmcs_config.cpu_based_2nd_exec_ctrl &
7607                 SECONDARY_EXEC_XSAVES;
7608 }
7609
7610 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7611 {
7612         u32 exit_intr_info;
7613         bool unblock_nmi;
7614         u8 vector;
7615         bool idtv_info_valid;
7616
7617         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7618
7619         if (cpu_has_virtual_nmis()) {
7620                 if (vmx->nmi_known_unmasked)
7621                         return;
7622                 /*
7623                  * Can't use vmx->exit_intr_info since we're not sure what
7624                  * the exit reason is.
7625                  */
7626                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7627                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7628                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7629                 /*
7630                  * SDM 3: 27.7.1.2 (September 2008)
7631                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7632                  * a guest IRET fault.
7633                  * SDM 3: 23.2.2 (September 2008)
7634                  * Bit 12 is undefined in any of the following cases:
7635                  *  If the VM exit sets the valid bit in the IDT-vectoring
7636                  *   information field.
7637                  *  If the VM exit is due to a double fault.
7638                  */
7639                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7640                     vector != DF_VECTOR && !idtv_info_valid)
7641                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7642                                       GUEST_INTR_STATE_NMI);
7643                 else
7644                         vmx->nmi_known_unmasked =
7645                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7646                                   & GUEST_INTR_STATE_NMI);
7647         } else if (unlikely(vmx->soft_vnmi_blocked))
7648                 vmx->vnmi_blocked_time +=
7649                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7650 }
7651
7652 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7653                                       u32 idt_vectoring_info,
7654                                       int instr_len_field,
7655                                       int error_code_field)
7656 {
7657         u8 vector;
7658         int type;
7659         bool idtv_info_valid;
7660
7661         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7662
7663         vcpu->arch.nmi_injected = false;
7664         kvm_clear_exception_queue(vcpu);
7665         kvm_clear_interrupt_queue(vcpu);
7666
7667         if (!idtv_info_valid)
7668                 return;
7669
7670         kvm_make_request(KVM_REQ_EVENT, vcpu);
7671
7672         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7673         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7674
7675         switch (type) {
7676         case INTR_TYPE_NMI_INTR:
7677                 vcpu->arch.nmi_injected = true;
7678                 /*
7679                  * SDM 3: 27.7.1.2 (September 2008)
7680                  * Clear bit "block by NMI" before VM entry if a NMI
7681                  * delivery faulted.
7682                  */
7683                 vmx_set_nmi_mask(vcpu, false);
7684                 break;
7685         case INTR_TYPE_SOFT_EXCEPTION:
7686                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7687                 /* fall through */
7688         case INTR_TYPE_HARD_EXCEPTION:
7689                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7690                         u32 err = vmcs_read32(error_code_field);
7691                         kvm_requeue_exception_e(vcpu, vector, err);
7692                 } else
7693                         kvm_requeue_exception(vcpu, vector);
7694                 break;
7695         case INTR_TYPE_SOFT_INTR:
7696                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7697                 /* fall through */
7698         case INTR_TYPE_EXT_INTR:
7699                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7700                 break;
7701         default:
7702                 break;
7703         }
7704 }
7705
7706 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7707 {
7708         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7709                                   VM_EXIT_INSTRUCTION_LEN,
7710                                   IDT_VECTORING_ERROR_CODE);
7711 }
7712
7713 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7714 {
7715         __vmx_complete_interrupts(vcpu,
7716                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7717                                   VM_ENTRY_INSTRUCTION_LEN,
7718                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7719
7720         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7721 }
7722
7723 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7724 {
7725         int i, nr_msrs;
7726         struct perf_guest_switch_msr *msrs;
7727
7728         msrs = perf_guest_get_msrs(&nr_msrs);
7729
7730         if (!msrs)
7731                 return;
7732
7733         for (i = 0; i < nr_msrs; i++)
7734                 if (msrs[i].host == msrs[i].guest)
7735                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7736                 else
7737                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7738                                         msrs[i].host);
7739 }
7740
7741 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7742 {
7743         struct vcpu_vmx *vmx = to_vmx(vcpu);
7744         unsigned long debugctlmsr, cr4;
7745
7746         /* Record the guest's net vcpu time for enforced NMI injections. */
7747         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7748                 vmx->entry_time = ktime_get();
7749
7750         /* Don't enter VMX if guest state is invalid, let the exit handler
7751            start emulation until we arrive back to a valid state */
7752         if (vmx->emulation_required)
7753                 return;
7754
7755         if (vmx->ple_window_dirty) {
7756                 vmx->ple_window_dirty = false;
7757                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7758         }
7759
7760         if (vmx->nested.sync_shadow_vmcs) {
7761                 copy_vmcs12_to_shadow(vmx);
7762                 vmx->nested.sync_shadow_vmcs = false;
7763         }
7764
7765         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7766                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7767         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7768                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7769
7770         cr4 = read_cr4();
7771         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7772                 vmcs_writel(HOST_CR4, cr4);
7773                 vmx->host_state.vmcs_host_cr4 = cr4;
7774         }
7775
7776         /* When single-stepping over STI and MOV SS, we must clear the
7777          * corresponding interruptibility bits in the guest state. Otherwise
7778          * vmentry fails as it then expects bit 14 (BS) in pending debug
7779          * exceptions being set, but that's not correct for the guest debugging
7780          * case. */
7781         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7782                 vmx_set_interrupt_shadow(vcpu, 0);
7783
7784         atomic_switch_perf_msrs(vmx);
7785         debugctlmsr = get_debugctlmsr();
7786
7787         vmx->__launched = vmx->loaded_vmcs->launched;
7788         asm(
7789                 /* Store host registers */
7790                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7791                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7792                 "push %%" _ASM_CX " \n\t"
7793                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7794                 "je 1f \n\t"
7795                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7796                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7797                 "1: \n\t"
7798                 /* Reload cr2 if changed */
7799                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7800                 "mov %%cr2, %%" _ASM_DX " \n\t"
7801                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7802                 "je 2f \n\t"
7803                 "mov %%" _ASM_AX", %%cr2 \n\t"
7804                 "2: \n\t"
7805                 /* Check if vmlaunch of vmresume is needed */
7806                 "cmpl $0, %c[launched](%0) \n\t"
7807                 /* Load guest registers.  Don't clobber flags. */
7808                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7809                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7810                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7811                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7812                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7813                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7814 #ifdef CONFIG_X86_64
7815                 "mov %c[r8](%0),  %%r8  \n\t"
7816                 "mov %c[r9](%0),  %%r9  \n\t"
7817                 "mov %c[r10](%0), %%r10 \n\t"
7818                 "mov %c[r11](%0), %%r11 \n\t"
7819                 "mov %c[r12](%0), %%r12 \n\t"
7820                 "mov %c[r13](%0), %%r13 \n\t"
7821                 "mov %c[r14](%0), %%r14 \n\t"
7822                 "mov %c[r15](%0), %%r15 \n\t"
7823 #endif
7824                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7825
7826                 /* Enter guest mode */
7827                 "jne 1f \n\t"
7828                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7829                 "jmp 2f \n\t"
7830                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7831                 "2: "
7832                 /* Save guest registers, load host registers, keep flags */
7833                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7834                 "pop %0 \n\t"
7835                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7836                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7837                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7838                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7839                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7840                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7841                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7842 #ifdef CONFIG_X86_64
7843                 "mov %%r8,  %c[r8](%0) \n\t"
7844                 "mov %%r9,  %c[r9](%0) \n\t"
7845                 "mov %%r10, %c[r10](%0) \n\t"
7846                 "mov %%r11, %c[r11](%0) \n\t"
7847                 "mov %%r12, %c[r12](%0) \n\t"
7848                 "mov %%r13, %c[r13](%0) \n\t"
7849                 "mov %%r14, %c[r14](%0) \n\t"
7850                 "mov %%r15, %c[r15](%0) \n\t"
7851 #endif
7852                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7853                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7854
7855                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7856                 "setbe %c[fail](%0) \n\t"
7857                 ".pushsection .rodata \n\t"
7858                 ".global vmx_return \n\t"
7859                 "vmx_return: " _ASM_PTR " 2b \n\t"
7860                 ".popsection"
7861               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7862                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7863                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7864                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7865                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7866                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7867                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7868                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7869                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7870                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7871                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7872 #ifdef CONFIG_X86_64
7873                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7874                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7875                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7876                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7877                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7878                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7879                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7880                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7881 #endif
7882                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7883                 [wordsize]"i"(sizeof(ulong))
7884               : "cc", "memory"
7885 #ifdef CONFIG_X86_64
7886                 , "rax", "rbx", "rdi", "rsi"
7887                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7888 #else
7889                 , "eax", "ebx", "edi", "esi"
7890 #endif
7891               );
7892
7893         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7894         if (debugctlmsr)
7895                 update_debugctlmsr(debugctlmsr);
7896
7897 #ifndef CONFIG_X86_64
7898         /*
7899          * The sysexit path does not restore ds/es, so we must set them to
7900          * a reasonable value ourselves.
7901          *
7902          * We can't defer this to vmx_load_host_state() since that function
7903          * may be executed in interrupt context, which saves and restore segments
7904          * around it, nullifying its effect.
7905          */
7906         loadsegment(ds, __USER_DS);
7907         loadsegment(es, __USER_DS);
7908 #endif
7909
7910         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7911                                   | (1 << VCPU_EXREG_RFLAGS)
7912                                   | (1 << VCPU_EXREG_PDPTR)
7913                                   | (1 << VCPU_EXREG_SEGMENTS)
7914                                   | (1 << VCPU_EXREG_CR3));
7915         vcpu->arch.regs_dirty = 0;
7916
7917         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7918
7919         vmx->loaded_vmcs->launched = 1;
7920
7921         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7922         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7923
7924         /*
7925          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7926          * we did not inject a still-pending event to L1 now because of
7927          * nested_run_pending, we need to re-enable this bit.
7928          */
7929         if (vmx->nested.nested_run_pending)
7930                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7931
7932         vmx->nested.nested_run_pending = 0;
7933
7934         vmx_complete_atomic_exit(vmx);
7935         vmx_recover_nmi_blocking(vmx);
7936         vmx_complete_interrupts(vmx);
7937 }
7938
7939 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7940 {
7941         struct vcpu_vmx *vmx = to_vmx(vcpu);
7942         int cpu;
7943
7944         if (vmx->loaded_vmcs == &vmx->vmcs01)
7945                 return;
7946
7947         cpu = get_cpu();
7948         vmx->loaded_vmcs = &vmx->vmcs01;
7949         vmx_vcpu_put(vcpu);
7950         vmx_vcpu_load(vcpu, cpu);
7951         vcpu->cpu = cpu;
7952         put_cpu();
7953 }
7954
7955 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7956 {
7957         struct vcpu_vmx *vmx = to_vmx(vcpu);
7958
7959         free_vpid(vmx);
7960         leave_guest_mode(vcpu);
7961         vmx_load_vmcs01(vcpu);
7962         free_nested(vmx);
7963         free_loaded_vmcs(vmx->loaded_vmcs);
7964         kfree(vmx->guest_msrs);
7965         kvm_vcpu_uninit(vcpu);
7966         kmem_cache_free(kvm_vcpu_cache, vmx);
7967 }
7968
7969 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7970 {
7971         int err;
7972         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7973         int cpu;
7974
7975         if (!vmx)
7976                 return ERR_PTR(-ENOMEM);
7977
7978         allocate_vpid(vmx);
7979
7980         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7981         if (err)
7982                 goto free_vcpu;
7983
7984         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7985         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7986                      > PAGE_SIZE);
7987
7988         err = -ENOMEM;
7989         if (!vmx->guest_msrs) {
7990                 goto uninit_vcpu;
7991         }
7992
7993         vmx->loaded_vmcs = &vmx->vmcs01;
7994         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7995         if (!vmx->loaded_vmcs->vmcs)
7996                 goto free_msrs;
7997         if (!vmm_exclusive)
7998                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7999         loaded_vmcs_init(vmx->loaded_vmcs);
8000         if (!vmm_exclusive)
8001                 kvm_cpu_vmxoff();
8002
8003         cpu = get_cpu();
8004         vmx_vcpu_load(&vmx->vcpu, cpu);
8005         vmx->vcpu.cpu = cpu;
8006         err = vmx_vcpu_setup(vmx);
8007         vmx_vcpu_put(&vmx->vcpu);
8008         put_cpu();
8009         if (err)
8010                 goto free_vmcs;
8011         if (vm_need_virtualize_apic_accesses(kvm)) {
8012                 err = alloc_apic_access_page(kvm);
8013                 if (err)
8014                         goto free_vmcs;
8015         }
8016
8017         if (enable_ept) {
8018                 if (!kvm->arch.ept_identity_map_addr)
8019                         kvm->arch.ept_identity_map_addr =
8020                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8021                 err = init_rmode_identity_map(kvm);
8022                 if (err)
8023                         goto free_vmcs;
8024         }
8025
8026         vmx->nested.current_vmptr = -1ull;
8027         vmx->nested.current_vmcs12 = NULL;
8028
8029         return &vmx->vcpu;
8030
8031 free_vmcs:
8032         free_loaded_vmcs(vmx->loaded_vmcs);
8033 free_msrs:
8034         kfree(vmx->guest_msrs);
8035 uninit_vcpu:
8036         kvm_vcpu_uninit(&vmx->vcpu);
8037 free_vcpu:
8038         free_vpid(vmx);
8039         kmem_cache_free(kvm_vcpu_cache, vmx);
8040         return ERR_PTR(err);
8041 }
8042
8043 static void __init vmx_check_processor_compat(void *rtn)
8044 {
8045         struct vmcs_config vmcs_conf;
8046
8047         *(int *)rtn = 0;
8048         if (setup_vmcs_config(&vmcs_conf) < 0)
8049                 *(int *)rtn = -EIO;
8050         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8051                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8052                                 smp_processor_id());
8053                 *(int *)rtn = -EIO;
8054         }
8055 }
8056
8057 static int get_ept_level(void)
8058 {
8059         return VMX_EPT_DEFAULT_GAW + 1;
8060 }
8061
8062 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8063 {
8064         u64 ret;
8065
8066         /* For VT-d and EPT combination
8067          * 1. MMIO: always map as UC
8068          * 2. EPT with VT-d:
8069          *   a. VT-d without snooping control feature: can't guarantee the
8070          *      result, try to trust guest.
8071          *   b. VT-d with snooping control feature: snooping control feature of
8072          *      VT-d engine can guarantee the cache correctness. Just set it
8073          *      to WB to keep consistent with host. So the same as item 3.
8074          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8075          *    consistent with host MTRR
8076          */
8077         if (is_mmio)
8078                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8079         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8080                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8081                       VMX_EPT_MT_EPTE_SHIFT;
8082         else
8083                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8084                         | VMX_EPT_IPAT_BIT;
8085
8086         return ret;
8087 }
8088
8089 static int vmx_get_lpage_level(void)
8090 {
8091         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8092                 return PT_DIRECTORY_LEVEL;
8093         else
8094                 /* For shadow and EPT supported 1GB page */
8095                 return PT_PDPE_LEVEL;
8096 }
8097
8098 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8099 {
8100         struct kvm_cpuid_entry2 *best;
8101         struct vcpu_vmx *vmx = to_vmx(vcpu);
8102         u32 exec_control;
8103
8104         vmx->rdtscp_enabled = false;
8105         if (vmx_rdtscp_supported()) {
8106                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8107                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8108                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8109                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8110                                 vmx->rdtscp_enabled = true;
8111                         else {
8112                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8113                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8114                                                 exec_control);
8115                         }
8116                 }
8117         }
8118
8119         /* Exposing INVPCID only when PCID is exposed */
8120         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8121         if (vmx_invpcid_supported() &&
8122             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8123             guest_cpuid_has_pcid(vcpu)) {
8124                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8125                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8126                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8127                              exec_control);
8128         } else {
8129                 if (cpu_has_secondary_exec_ctrls()) {
8130                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8131                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8132                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8133                                      exec_control);
8134                 }
8135                 if (best)
8136                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8137         }
8138 }
8139
8140 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8141 {
8142         if (func == 1 && nested)
8143                 entry->ecx |= bit(X86_FEATURE_VMX);
8144 }
8145
8146 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8147                 struct x86_exception *fault)
8148 {
8149         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8150         u32 exit_reason;
8151
8152         if (fault->error_code & PFERR_RSVD_MASK)
8153                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8154         else
8155                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8156         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8157         vmcs12->guest_physical_address = fault->address;
8158 }
8159
8160 /* Callbacks for nested_ept_init_mmu_context: */
8161
8162 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8163 {
8164         /* return the page table to be shadowed - in our case, EPT12 */
8165         return get_vmcs12(vcpu)->ept_pointer;
8166 }
8167
8168 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8169 {
8170         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
8171                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8172
8173         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8174         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8175         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8176
8177         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8178 }
8179
8180 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8181 {
8182         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8183 }
8184
8185 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8186                 struct x86_exception *fault)
8187 {
8188         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8189
8190         WARN_ON(!is_guest_mode(vcpu));
8191
8192         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8193         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
8194                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8195                                   vmcs_read32(VM_EXIT_INTR_INFO),
8196                                   vmcs_readl(EXIT_QUALIFICATION));
8197         else
8198                 kvm_inject_page_fault(vcpu, fault);
8199 }
8200
8201 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8202                                         struct vmcs12 *vmcs12)
8203 {
8204         struct vcpu_vmx *vmx = to_vmx(vcpu);
8205
8206         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8207                 /* TODO: Also verify bits beyond physical address width are 0 */
8208                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
8209                         return false;
8210
8211                 /*
8212                  * Translate L1 physical address to host physical
8213                  * address for vmcs02. Keep the page pinned, so this
8214                  * physical address remains valid. We keep a reference
8215                  * to it so we can release it later.
8216                  */
8217                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8218                         nested_release_page(vmx->nested.apic_access_page);
8219                 vmx->nested.apic_access_page =
8220                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8221         }
8222
8223         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8224                 /* TODO: Also verify bits beyond physical address width are 0 */
8225                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8226                         return false;
8227
8228                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8229                         nested_release_page(vmx->nested.virtual_apic_page);
8230                 vmx->nested.virtual_apic_page =
8231                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8232
8233                 /*
8234                  * Failing the vm entry is _not_ what the processor does
8235                  * but it's basically the only possibility we have.
8236                  * We could still enter the guest if CR8 load exits are
8237                  * enabled, CR8 store exits are enabled, and virtualize APIC
8238                  * access is disabled; in this case the processor would never
8239                  * use the TPR shadow and we could simply clear the bit from
8240                  * the execution control.  But such a configuration is useless,
8241                  * so let's keep the code simple.
8242                  */
8243                 if (!vmx->nested.virtual_apic_page)
8244                         return false;
8245         }
8246
8247         return true;
8248 }
8249
8250 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8251 {
8252         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8253         struct vcpu_vmx *vmx = to_vmx(vcpu);
8254
8255         if (vcpu->arch.virtual_tsc_khz == 0)
8256                 return;
8257
8258         /* Make sure short timeouts reliably trigger an immediate vmexit.
8259          * hrtimer_start does not guarantee this. */
8260         if (preemption_timeout <= 1) {
8261                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8262                 return;
8263         }
8264
8265         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8266         preemption_timeout *= 1000000;
8267         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8268         hrtimer_start(&vmx->nested.preemption_timer,
8269                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8270 }
8271
8272 /*
8273  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8274  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8275  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8276  * guest in a way that will both be appropriate to L1's requests, and our
8277  * needs. In addition to modifying the active vmcs (which is vmcs02), this
8278  * function also has additional necessary side-effects, like setting various
8279  * vcpu->arch fields.
8280  */
8281 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8282 {
8283         struct vcpu_vmx *vmx = to_vmx(vcpu);
8284         u32 exec_control;
8285
8286         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8287         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8288         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8289         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8290         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8291         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8292         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8293         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8294         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8295         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8296         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8297         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8298         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8299         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8300         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8301         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8302         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8303         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8304         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8305         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8306         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8307         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8308         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8309         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8310         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8311         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8312         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8313         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8314         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8315         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8316         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8317         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8318         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8319         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8320         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8321         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8322
8323         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8324                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8325                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8326         } else {
8327                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8328                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8329         }
8330         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8331                 vmcs12->vm_entry_intr_info_field);
8332         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8333                 vmcs12->vm_entry_exception_error_code);
8334         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8335                 vmcs12->vm_entry_instruction_len);
8336         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8337                 vmcs12->guest_interruptibility_info);
8338         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
8339         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
8340         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8341                 vmcs12->guest_pending_dbg_exceptions);
8342         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8343         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8344
8345         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8346
8347         exec_control = vmcs12->pin_based_vm_exec_control;
8348         exec_control |= vmcs_config.pin_based_exec_ctrl;
8349         exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8350                           PIN_BASED_POSTED_INTR);
8351         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
8352
8353         vmx->nested.preemption_timer_expired = false;
8354         if (nested_cpu_has_preemption_timer(vmcs12))
8355                 vmx_start_preemption_timer(vcpu);
8356
8357         /*
8358          * Whether page-faults are trapped is determined by a combination of
8359          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8360          * If enable_ept, L0 doesn't care about page faults and we should
8361          * set all of these to L1's desires. However, if !enable_ept, L0 does
8362          * care about (at least some) page faults, and because it is not easy
8363          * (if at all possible?) to merge L0 and L1's desires, we simply ask
8364          * to exit on each and every L2 page fault. This is done by setting
8365          * MASK=MATCH=0 and (see below) EB.PF=1.
8366          * Note that below we don't need special code to set EB.PF beyond the
8367          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8368          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8369          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8370          *
8371          * A problem with this approach (when !enable_ept) is that L1 may be
8372          * injected with more page faults than it asked for. This could have
8373          * caused problems, but in practice existing hypervisors don't care.
8374          * To fix this, we will need to emulate the PFEC checking (on the L1
8375          * page tables), using walk_addr(), when injecting PFs to L1.
8376          */
8377         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8378                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8379         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8380                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8381
8382         if (cpu_has_secondary_exec_ctrls()) {
8383                 exec_control = vmx_secondary_exec_control(vmx);
8384                 if (!vmx->rdtscp_enabled)
8385                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
8386                 /* Take the following fields only from vmcs12 */
8387                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8388                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8389                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
8390                 if (nested_cpu_has(vmcs12,
8391                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8392                         exec_control |= vmcs12->secondary_vm_exec_control;
8393
8394                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
8395                         /*
8396                          * If translation failed, no matter: This feature asks
8397                          * to exit when accessing the given address, and if it
8398                          * can never be accessed, this feature won't do
8399                          * anything anyway.
8400                          */
8401                         if (!vmx->nested.apic_access_page)
8402                                 exec_control &=
8403                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8404                         else
8405                                 vmcs_write64(APIC_ACCESS_ADDR,
8406                                   page_to_phys(vmx->nested.apic_access_page));
8407                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8408                         exec_control |=
8409                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8410                         kvm_vcpu_reload_apic_access_page(vcpu);
8411                 }
8412
8413                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8414         }
8415
8416
8417         /*
8418          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8419          * Some constant fields are set here by vmx_set_constant_host_state().
8420          * Other fields are different per CPU, and will be set later when
8421          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8422          */
8423         vmx_set_constant_host_state(vmx);
8424
8425         /*
8426          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8427          * entry, but only if the current (host) sp changed from the value
8428          * we wrote last (vmx->host_rsp). This cache is no longer relevant
8429          * if we switch vmcs, and rather than hold a separate cache per vmcs,
8430          * here we just force the write to happen on entry.
8431          */
8432         vmx->host_rsp = 0;
8433
8434         exec_control = vmx_exec_control(vmx); /* L0's desires */
8435         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8436         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8437         exec_control &= ~CPU_BASED_TPR_SHADOW;
8438         exec_control |= vmcs12->cpu_based_vm_exec_control;
8439
8440         if (exec_control & CPU_BASED_TPR_SHADOW) {
8441                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8442                                 page_to_phys(vmx->nested.virtual_apic_page));
8443                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8444         }
8445
8446         /*
8447          * Merging of IO and MSR bitmaps not currently supported.
8448          * Rather, exit every time.
8449          */
8450         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8451         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8452         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8453
8454         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8455
8456         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8457          * bitwise-or of what L1 wants to trap for L2, and what we want to
8458          * trap. Note that CR0.TS also needs updating - we do this later.
8459          */
8460         update_exception_bitmap(vcpu);
8461         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8462         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8463
8464         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8465          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8466          * bits are further modified by vmx_set_efer() below.
8467          */
8468         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8469
8470         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8471          * emulated by vmx_set_efer(), below.
8472          */
8473         vm_entry_controls_init(vmx,
8474                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8475                         ~VM_ENTRY_IA32E_MODE) |
8476                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8477
8478         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
8479                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
8480                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8481         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
8482                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8483
8484
8485         set_cr4_guest_host_mask(vmx);
8486
8487         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8488                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8489
8490         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8491                 vmcs_write64(TSC_OFFSET,
8492                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8493         else
8494                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8495
8496         if (enable_vpid) {
8497                 /*
8498                  * Trivially support vpid by letting L2s share their parent
8499                  * L1's vpid. TODO: move to a more elaborate solution, giving
8500                  * each L2 its own vpid and exposing the vpid feature to L1.
8501                  */
8502                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8503                 vmx_flush_tlb(vcpu);
8504         }
8505
8506         if (nested_cpu_has_ept(vmcs12)) {
8507                 kvm_mmu_unload(vcpu);
8508                 nested_ept_init_mmu_context(vcpu);
8509         }
8510
8511         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8512                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
8513         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
8514                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8515         else
8516                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8517         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8518         vmx_set_efer(vcpu, vcpu->arch.efer);
8519
8520         /*
8521          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8522          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8523          * The CR0_READ_SHADOW is what L2 should have expected to read given
8524          * the specifications by L1; It's not enough to take
8525          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8526          * have more bits than L1 expected.
8527          */
8528         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8529         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8530
8531         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8532         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8533
8534         /* shadow page tables on either EPT or shadow page tables */
8535         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8536         kvm_mmu_reset_context(vcpu);
8537
8538         if (!enable_ept)
8539                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8540
8541         /*
8542          * L1 may access the L2's PDPTR, so save them to construct vmcs12
8543          */
8544         if (enable_ept) {
8545                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8546                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8547                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8548                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8549         }
8550
8551         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8552         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8553 }
8554
8555 /*
8556  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8557  * for running an L2 nested guest.
8558  */
8559 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8560 {
8561         struct vmcs12 *vmcs12;
8562         struct vcpu_vmx *vmx = to_vmx(vcpu);
8563         int cpu;
8564         struct loaded_vmcs *vmcs02;
8565         bool ia32e;
8566
8567         if (!nested_vmx_check_permission(vcpu) ||
8568             !nested_vmx_check_vmcs12(vcpu))
8569                 return 1;
8570
8571         skip_emulated_instruction(vcpu);
8572         vmcs12 = get_vmcs12(vcpu);
8573
8574         if (enable_shadow_vmcs)
8575                 copy_shadow_to_vmcs12(vmx);
8576
8577         /*
8578          * The nested entry process starts with enforcing various prerequisites
8579          * on vmcs12 as required by the Intel SDM, and act appropriately when
8580          * they fail: As the SDM explains, some conditions should cause the
8581          * instruction to fail, while others will cause the instruction to seem
8582          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8583          * To speed up the normal (success) code path, we should avoid checking
8584          * for misconfigurations which will anyway be caught by the processor
8585          * when using the merged vmcs02.
8586          */
8587         if (vmcs12->launch_state == launch) {
8588                 nested_vmx_failValid(vcpu,
8589                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8590                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8591                 return 1;
8592         }
8593
8594         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8595             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8596                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8597                 return 1;
8598         }
8599
8600         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8601                         !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
8602                 /*TODO: Also verify bits beyond physical address width are 0*/
8603                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8604                 return 1;
8605         }
8606
8607         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
8608                 /*TODO: Also verify bits beyond physical address width are 0*/
8609                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8610                 return 1;
8611         }
8612
8613         if (vmcs12->vm_entry_msr_load_count > 0 ||
8614             vmcs12->vm_exit_msr_load_count > 0 ||
8615             vmcs12->vm_exit_msr_store_count > 0) {
8616                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8617                                     __func__);
8618                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8619                 return 1;
8620         }
8621
8622         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8623                                 nested_vmx_true_procbased_ctls_low,
8624                                 nested_vmx_procbased_ctls_high) ||
8625             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8626               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8627             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8628               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8629             !vmx_control_verify(vmcs12->vm_exit_controls,
8630                                 nested_vmx_true_exit_ctls_low,
8631                                 nested_vmx_exit_ctls_high) ||
8632             !vmx_control_verify(vmcs12->vm_entry_controls,
8633                                 nested_vmx_true_entry_ctls_low,
8634                                 nested_vmx_entry_ctls_high))
8635         {
8636                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8637                 return 1;
8638         }
8639
8640         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8641             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8642                 nested_vmx_failValid(vcpu,
8643                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8644                 return 1;
8645         }
8646
8647         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8648             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8649                 nested_vmx_entry_failure(vcpu, vmcs12,
8650                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8651                 return 1;
8652         }
8653         if (vmcs12->vmcs_link_pointer != -1ull) {
8654                 nested_vmx_entry_failure(vcpu, vmcs12,
8655                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8656                 return 1;
8657         }
8658
8659         /*
8660          * If the load IA32_EFER VM-entry control is 1, the following checks
8661          * are performed on the field for the IA32_EFER MSR:
8662          * - Bits reserved in the IA32_EFER MSR must be 0.
8663          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8664          *   the IA-32e mode guest VM-exit control. It must also be identical
8665          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8666          *   CR0.PG) is 1.
8667          */
8668         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8669                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8670                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8671                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8672                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8673                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8674                         nested_vmx_entry_failure(vcpu, vmcs12,
8675                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8676                         return 1;
8677                 }
8678         }
8679
8680         /*
8681          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8682          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8683          * the values of the LMA and LME bits in the field must each be that of
8684          * the host address-space size VM-exit control.
8685          */
8686         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8687                 ia32e = (vmcs12->vm_exit_controls &
8688                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8689                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8690                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8691                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8692                         nested_vmx_entry_failure(vcpu, vmcs12,
8693                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8694                         return 1;
8695                 }
8696         }
8697
8698         /*
8699          * We're finally done with prerequisite checking, and can start with
8700          * the nested entry.
8701          */
8702
8703         vmcs02 = nested_get_current_vmcs02(vmx);
8704         if (!vmcs02)
8705                 return -ENOMEM;
8706
8707         enter_guest_mode(vcpu);
8708
8709         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8710
8711         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8712                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8713
8714         cpu = get_cpu();
8715         vmx->loaded_vmcs = vmcs02;
8716         vmx_vcpu_put(vcpu);
8717         vmx_vcpu_load(vcpu, cpu);
8718         vcpu->cpu = cpu;
8719         put_cpu();
8720
8721         vmx_segment_cache_clear(vmx);
8722
8723         vmcs12->launch_state = 1;
8724
8725         prepare_vmcs02(vcpu, vmcs12);
8726
8727         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8728                 return kvm_emulate_halt(vcpu);
8729
8730         vmx->nested.nested_run_pending = 1;
8731
8732         /*
8733          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8734          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8735          * returned as far as L1 is concerned. It will only return (and set
8736          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8737          */
8738         return 1;
8739 }
8740
8741 /*
8742  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8743  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8744  * This function returns the new value we should put in vmcs12.guest_cr0.
8745  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8746  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8747  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8748  *     didn't trap the bit, because if L1 did, so would L0).
8749  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8750  *     been modified by L2, and L1 knows it. So just leave the old value of
8751  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8752  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8753  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8754  *     changed these bits, and therefore they need to be updated, but L0
8755  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8756  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8757  */
8758 static inline unsigned long
8759 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8760 {
8761         return
8762         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8763         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8764         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8765                         vcpu->arch.cr0_guest_owned_bits));
8766 }
8767
8768 static inline unsigned long
8769 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8770 {
8771         return
8772         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8773         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8774         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8775                         vcpu->arch.cr4_guest_owned_bits));
8776 }
8777
8778 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8779                                        struct vmcs12 *vmcs12)
8780 {
8781         u32 idt_vectoring;
8782         unsigned int nr;
8783
8784         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8785                 nr = vcpu->arch.exception.nr;
8786                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8787
8788                 if (kvm_exception_is_soft(nr)) {
8789                         vmcs12->vm_exit_instruction_len =
8790                                 vcpu->arch.event_exit_inst_len;
8791                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8792                 } else
8793                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8794
8795                 if (vcpu->arch.exception.has_error_code) {
8796                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8797                         vmcs12->idt_vectoring_error_code =
8798                                 vcpu->arch.exception.error_code;
8799                 }
8800
8801                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8802         } else if (vcpu->arch.nmi_injected) {
8803                 vmcs12->idt_vectoring_info_field =
8804                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8805         } else if (vcpu->arch.interrupt.pending) {
8806                 nr = vcpu->arch.interrupt.nr;
8807                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8808
8809                 if (vcpu->arch.interrupt.soft) {
8810                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8811                         vmcs12->vm_entry_instruction_len =
8812                                 vcpu->arch.event_exit_inst_len;
8813                 } else
8814                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8815
8816                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8817         }
8818 }
8819
8820 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8821 {
8822         struct vcpu_vmx *vmx = to_vmx(vcpu);
8823
8824         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8825             vmx->nested.preemption_timer_expired) {
8826                 if (vmx->nested.nested_run_pending)
8827                         return -EBUSY;
8828                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8829                 return 0;
8830         }
8831
8832         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8833                 if (vmx->nested.nested_run_pending ||
8834                     vcpu->arch.interrupt.pending)
8835                         return -EBUSY;
8836                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8837                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8838                                   INTR_INFO_VALID_MASK, 0);
8839                 /*
8840                  * The NMI-triggered VM exit counts as injection:
8841                  * clear this one and block further NMIs.
8842                  */
8843                 vcpu->arch.nmi_pending = 0;
8844                 vmx_set_nmi_mask(vcpu, true);
8845                 return 0;
8846         }
8847
8848         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8849             nested_exit_on_intr(vcpu)) {
8850                 if (vmx->nested.nested_run_pending)
8851                         return -EBUSY;
8852                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8853         }
8854
8855         return 0;
8856 }
8857
8858 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8859 {
8860         ktime_t remaining =
8861                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8862         u64 value;
8863
8864         if (ktime_to_ns(remaining) <= 0)
8865                 return 0;
8866
8867         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8868         do_div(value, 1000000);
8869         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8870 }
8871
8872 /*
8873  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8874  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8875  * and this function updates it to reflect the changes to the guest state while
8876  * L2 was running (and perhaps made some exits which were handled directly by L0
8877  * without going back to L1), and to reflect the exit reason.
8878  * Note that we do not have to copy here all VMCS fields, just those that
8879  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8880  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8881  * which already writes to vmcs12 directly.
8882  */
8883 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8884                            u32 exit_reason, u32 exit_intr_info,
8885                            unsigned long exit_qualification)
8886 {
8887         /* update guest state fields: */
8888         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8889         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8890
8891         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8892         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8893         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8894
8895         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8896         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8897         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8898         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8899         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8900         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8901         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8902         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8903         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8904         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8905         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8906         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8907         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8908         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8909         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8910         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8911         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8912         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8913         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8914         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8915         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8916         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8917         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8918         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8919         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8920         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8921         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8922         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8923         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8924         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8925         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8926         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8927         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8928         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8929         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8930         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8931
8932         vmcs12->guest_interruptibility_info =
8933                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8934         vmcs12->guest_pending_dbg_exceptions =
8935                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8936         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8937                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8938         else
8939                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8940
8941         if (nested_cpu_has_preemption_timer(vmcs12)) {
8942                 if (vmcs12->vm_exit_controls &
8943                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8944                         vmcs12->vmx_preemption_timer_value =
8945                                 vmx_get_preemption_timer_value(vcpu);
8946                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8947         }
8948
8949         /*
8950          * In some cases (usually, nested EPT), L2 is allowed to change its
8951          * own CR3 without exiting. If it has changed it, we must keep it.
8952          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8953          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8954          *
8955          * Additionally, restore L2's PDPTR to vmcs12.
8956          */
8957         if (enable_ept) {
8958                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8959                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8960                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8961                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8962                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8963         }
8964
8965         vmcs12->vm_entry_controls =
8966                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8967                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8968
8969         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8970                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8971                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8972         }
8973
8974         /* TODO: These cannot have changed unless we have MSR bitmaps and
8975          * the relevant bit asks not to trap the change */
8976         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8977                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8978         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8979                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8980         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8981         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8982         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8983         if (vmx_mpx_supported())
8984                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8985
8986         /* update exit information fields: */
8987
8988         vmcs12->vm_exit_reason = exit_reason;
8989         vmcs12->exit_qualification = exit_qualification;
8990
8991         vmcs12->vm_exit_intr_info = exit_intr_info;
8992         if ((vmcs12->vm_exit_intr_info &
8993              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8994             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8995                 vmcs12->vm_exit_intr_error_code =
8996                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8997         vmcs12->idt_vectoring_info_field = 0;
8998         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8999         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9000
9001         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9002                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9003                  * instead of reading the real value. */
9004                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9005
9006                 /*
9007                  * Transfer the event that L0 or L1 may wanted to inject into
9008                  * L2 to IDT_VECTORING_INFO_FIELD.
9009                  */
9010                 vmcs12_save_pending_event(vcpu, vmcs12);
9011         }
9012
9013         /*
9014          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9015          * preserved above and would only end up incorrectly in L1.
9016          */
9017         vcpu->arch.nmi_injected = false;
9018         kvm_clear_exception_queue(vcpu);
9019         kvm_clear_interrupt_queue(vcpu);
9020 }
9021
9022 /*
9023  * A part of what we need to when the nested L2 guest exits and we want to
9024  * run its L1 parent, is to reset L1's guest state to the host state specified
9025  * in vmcs12.
9026  * This function is to be called not only on normal nested exit, but also on
9027  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9028  * Failures During or After Loading Guest State").
9029  * This function should be called when the active VMCS is L1's (vmcs01).
9030  */
9031 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9032                                    struct vmcs12 *vmcs12)
9033 {
9034         struct kvm_segment seg;
9035
9036         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9037                 vcpu->arch.efer = vmcs12->host_ia32_efer;
9038         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9039                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9040         else
9041                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9042         vmx_set_efer(vcpu, vcpu->arch.efer);
9043
9044         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9045         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9046         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9047         /*
9048          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9049          * actually changed, because it depends on the current state of
9050          * fpu_active (which may have changed).
9051          * Note that vmx_set_cr0 refers to efer set above.
9052          */
9053         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9054         /*
9055          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9056          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9057          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9058          */
9059         update_exception_bitmap(vcpu);
9060         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9061         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9062
9063         /*
9064          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9065          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9066          */
9067         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9068         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9069
9070         nested_ept_uninit_mmu_context(vcpu);
9071
9072         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9073         kvm_mmu_reset_context(vcpu);
9074
9075         if (!enable_ept)
9076                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9077
9078         if (enable_vpid) {
9079                 /*
9080                  * Trivially support vpid by letting L2s share their parent
9081                  * L1's vpid. TODO: move to a more elaborate solution, giving
9082                  * each L2 its own vpid and exposing the vpid feature to L1.
9083                  */
9084                 vmx_flush_tlb(vcpu);
9085         }
9086
9087
9088         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9089         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9090         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9091         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9092         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9093
9094         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9095         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9096                 vmcs_write64(GUEST_BNDCFGS, 0);
9097
9098         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9099                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9100                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9101         }
9102         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9103                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9104                         vmcs12->host_ia32_perf_global_ctrl);
9105
9106         /* Set L1 segment info according to Intel SDM
9107             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9108         seg = (struct kvm_segment) {
9109                 .base = 0,
9110                 .limit = 0xFFFFFFFF,
9111                 .selector = vmcs12->host_cs_selector,
9112                 .type = 11,
9113                 .present = 1,
9114                 .s = 1,
9115                 .g = 1
9116         };
9117         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9118                 seg.l = 1;
9119         else
9120                 seg.db = 1;
9121         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9122         seg = (struct kvm_segment) {
9123                 .base = 0,
9124                 .limit = 0xFFFFFFFF,
9125                 .type = 3,
9126                 .present = 1,
9127                 .s = 1,
9128                 .db = 1,
9129                 .g = 1
9130         };
9131         seg.selector = vmcs12->host_ds_selector;
9132         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9133         seg.selector = vmcs12->host_es_selector;
9134         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9135         seg.selector = vmcs12->host_ss_selector;
9136         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9137         seg.selector = vmcs12->host_fs_selector;
9138         seg.base = vmcs12->host_fs_base;
9139         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9140         seg.selector = vmcs12->host_gs_selector;
9141         seg.base = vmcs12->host_gs_base;
9142         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9143         seg = (struct kvm_segment) {
9144                 .base = vmcs12->host_tr_base,
9145                 .limit = 0x67,
9146                 .selector = vmcs12->host_tr_selector,
9147                 .type = 11,
9148                 .present = 1
9149         };
9150         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9151
9152         kvm_set_dr(vcpu, 7, 0x400);
9153         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9154 }
9155
9156 /*
9157  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9158  * and modify vmcs12 to make it see what it would expect to see there if
9159  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9160  */
9161 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9162                               u32 exit_intr_info,
9163                               unsigned long exit_qualification)
9164 {
9165         struct vcpu_vmx *vmx = to_vmx(vcpu);
9166         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9167
9168         /* trying to cancel vmlaunch/vmresume is a bug */
9169         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9170
9171         leave_guest_mode(vcpu);
9172         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9173                        exit_qualification);
9174
9175         vmx_load_vmcs01(vcpu);
9176
9177         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9178             && nested_exit_intr_ack_set(vcpu)) {
9179                 int irq = kvm_cpu_get_interrupt(vcpu);
9180                 WARN_ON(irq < 0);
9181                 vmcs12->vm_exit_intr_info = irq |
9182                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9183         }
9184
9185         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9186                                        vmcs12->exit_qualification,
9187                                        vmcs12->idt_vectoring_info_field,
9188                                        vmcs12->vm_exit_intr_info,
9189                                        vmcs12->vm_exit_intr_error_code,
9190                                        KVM_ISA_VMX);
9191
9192         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9193         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
9194         vmx_segment_cache_clear(vmx);
9195
9196         /* if no vmcs02 cache requested, remove the one we used */
9197         if (VMCS02_POOL_SIZE == 0)
9198                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9199
9200         load_vmcs12_host_state(vcpu, vmcs12);
9201
9202         /* Update TSC_OFFSET if TSC was changed while L2 ran */
9203         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9204
9205         /* This is needed for same reason as it was needed in prepare_vmcs02 */
9206         vmx->host_rsp = 0;
9207
9208         /* Unpin physical memory we referred to in vmcs02 */
9209         if (vmx->nested.apic_access_page) {
9210                 nested_release_page(vmx->nested.apic_access_page);
9211                 vmx->nested.apic_access_page = NULL;
9212         }
9213         if (vmx->nested.virtual_apic_page) {
9214                 nested_release_page(vmx->nested.virtual_apic_page);
9215                 vmx->nested.virtual_apic_page = NULL;
9216         }
9217
9218         /*
9219          * We are now running in L2, mmu_notifier will force to reload the
9220          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9221          */
9222         kvm_vcpu_reload_apic_access_page(vcpu);
9223
9224         /*
9225          * Exiting from L2 to L1, we're now back to L1 which thinks it just
9226          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9227          * success or failure flag accordingly.
9228          */
9229         if (unlikely(vmx->fail)) {
9230                 vmx->fail = 0;
9231                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9232         } else
9233                 nested_vmx_succeed(vcpu);
9234         if (enable_shadow_vmcs)
9235                 vmx->nested.sync_shadow_vmcs = true;
9236
9237         /* in case we halted in L2 */
9238         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9239 }
9240
9241 /*
9242  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9243  */
9244 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9245 {
9246         if (is_guest_mode(vcpu))
9247                 nested_vmx_vmexit(vcpu, -1, 0, 0);
9248         free_nested(to_vmx(vcpu));
9249 }
9250
9251 /*
9252  * L1's failure to enter L2 is a subset of a normal exit, as explained in
9253  * 23.7 "VM-entry failures during or after loading guest state" (this also
9254  * lists the acceptable exit-reason and exit-qualification parameters).
9255  * It should only be called before L2 actually succeeded to run, and when
9256  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9257  */
9258 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9259                         struct vmcs12 *vmcs12,
9260                         u32 reason, unsigned long qualification)
9261 {
9262         load_vmcs12_host_state(vcpu, vmcs12);
9263         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9264         vmcs12->exit_qualification = qualification;
9265         nested_vmx_succeed(vcpu);
9266         if (enable_shadow_vmcs)
9267                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
9268 }
9269
9270 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9271                                struct x86_instruction_info *info,
9272                                enum x86_intercept_stage stage)
9273 {
9274         return X86EMUL_CONTINUE;
9275 }
9276
9277 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
9278 {
9279         if (ple_gap)
9280                 shrink_ple_window(vcpu);
9281 }
9282
9283 static struct kvm_x86_ops vmx_x86_ops = {
9284         .cpu_has_kvm_support = cpu_has_kvm_support,
9285         .disabled_by_bios = vmx_disabled_by_bios,
9286         .hardware_setup = hardware_setup,
9287         .hardware_unsetup = hardware_unsetup,
9288         .check_processor_compatibility = vmx_check_processor_compat,
9289         .hardware_enable = hardware_enable,
9290         .hardware_disable = hardware_disable,
9291         .cpu_has_accelerated_tpr = report_flexpriority,
9292
9293         .vcpu_create = vmx_create_vcpu,
9294         .vcpu_free = vmx_free_vcpu,
9295         .vcpu_reset = vmx_vcpu_reset,
9296
9297         .prepare_guest_switch = vmx_save_host_state,
9298         .vcpu_load = vmx_vcpu_load,
9299         .vcpu_put = vmx_vcpu_put,
9300
9301         .update_db_bp_intercept = update_exception_bitmap,
9302         .get_msr = vmx_get_msr,
9303         .set_msr = vmx_set_msr,
9304         .get_segment_base = vmx_get_segment_base,
9305         .get_segment = vmx_get_segment,
9306         .set_segment = vmx_set_segment,
9307         .get_cpl = vmx_get_cpl,
9308         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
9309         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
9310         .decache_cr3 = vmx_decache_cr3,
9311         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
9312         .set_cr0 = vmx_set_cr0,
9313         .set_cr3 = vmx_set_cr3,
9314         .set_cr4 = vmx_set_cr4,
9315         .set_efer = vmx_set_efer,
9316         .get_idt = vmx_get_idt,
9317         .set_idt = vmx_set_idt,
9318         .get_gdt = vmx_get_gdt,
9319         .set_gdt = vmx_set_gdt,
9320         .get_dr6 = vmx_get_dr6,
9321         .set_dr6 = vmx_set_dr6,
9322         .set_dr7 = vmx_set_dr7,
9323         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
9324         .cache_reg = vmx_cache_reg,
9325         .get_rflags = vmx_get_rflags,
9326         .set_rflags = vmx_set_rflags,
9327         .fpu_deactivate = vmx_fpu_deactivate,
9328
9329         .tlb_flush = vmx_flush_tlb,
9330
9331         .run = vmx_vcpu_run,
9332         .handle_exit = vmx_handle_exit,
9333         .skip_emulated_instruction = skip_emulated_instruction,
9334         .set_interrupt_shadow = vmx_set_interrupt_shadow,
9335         .get_interrupt_shadow = vmx_get_interrupt_shadow,
9336         .patch_hypercall = vmx_patch_hypercall,
9337         .set_irq = vmx_inject_irq,
9338         .set_nmi = vmx_inject_nmi,
9339         .queue_exception = vmx_queue_exception,
9340         .cancel_injection = vmx_cancel_injection,
9341         .interrupt_allowed = vmx_interrupt_allowed,
9342         .nmi_allowed = vmx_nmi_allowed,
9343         .get_nmi_mask = vmx_get_nmi_mask,
9344         .set_nmi_mask = vmx_set_nmi_mask,
9345         .enable_nmi_window = enable_nmi_window,
9346         .enable_irq_window = enable_irq_window,
9347         .update_cr8_intercept = update_cr8_intercept,
9348         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
9349         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
9350         .vm_has_apicv = vmx_vm_has_apicv,
9351         .load_eoi_exitmap = vmx_load_eoi_exitmap,
9352         .hwapic_irr_update = vmx_hwapic_irr_update,
9353         .hwapic_isr_update = vmx_hwapic_isr_update,
9354         .sync_pir_to_irr = vmx_sync_pir_to_irr,
9355         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
9356
9357         .set_tss_addr = vmx_set_tss_addr,
9358         .get_tdp_level = get_ept_level,
9359         .get_mt_mask = vmx_get_mt_mask,
9360
9361         .get_exit_info = vmx_get_exit_info,
9362
9363         .get_lpage_level = vmx_get_lpage_level,
9364
9365         .cpuid_update = vmx_cpuid_update,
9366
9367         .rdtscp_supported = vmx_rdtscp_supported,
9368         .invpcid_supported = vmx_invpcid_supported,
9369
9370         .set_supported_cpuid = vmx_set_supported_cpuid,
9371
9372         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
9373
9374         .set_tsc_khz = vmx_set_tsc_khz,
9375         .read_tsc_offset = vmx_read_tsc_offset,
9376         .write_tsc_offset = vmx_write_tsc_offset,
9377         .adjust_tsc_offset = vmx_adjust_tsc_offset,
9378         .compute_tsc_offset = vmx_compute_tsc_offset,
9379         .read_l1_tsc = vmx_read_l1_tsc,
9380
9381         .set_tdp_cr3 = vmx_set_cr3,
9382
9383         .check_intercept = vmx_check_intercept,
9384         .handle_external_intr = vmx_handle_external_intr,
9385         .mpx_supported = vmx_mpx_supported,
9386         .xsaves_supported = vmx_xsaves_supported,
9387
9388         .check_nested_events = vmx_check_nested_events,
9389
9390         .sched_in = vmx_sched_in,
9391 };
9392
9393 static int __init vmx_init(void)
9394 {
9395         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9396                      __alignof__(struct vcpu_vmx), THIS_MODULE);
9397         if (r)
9398                 return r;
9399
9400 #ifdef CONFIG_KEXEC
9401         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9402                            crash_vmclear_local_loaded_vmcss);
9403 #endif
9404
9405         return 0;
9406 }
9407
9408 static void __exit vmx_exit(void)
9409 {
9410 #ifdef CONFIG_KEXEC
9411         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
9412         synchronize_rcu();
9413 #endif
9414
9415         kvm_exit();
9416 }
9417
9418 module_init(vmx_init)
9419 module_exit(vmx_exit)