arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept_ad_bits = 1;
  75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  76
  77 static bool __read_mostly emulate_invalid_guest_state = true;
  78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  79
  80 static bool __read_mostly vmm_exclusive = 1;
  81 module_param(vmm_exclusive, bool, S_IRUGO);
  82
  83 static bool __read_mostly fasteoi = 1;
  84 module_param(fasteoi, bool, S_IRUGO);
  85
  86 /*
  87  * If nested=1, nested virtualization is supported, i.e., guests may use
  88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  89  * use VMX instructions.
  90  */
  91 static bool __read_mostly nested = 0;
  92 module_param(nested, bool, S_IRUGO);
  93
  94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  96 #define KVM_GUEST_CR0_MASK                                              \
  97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  99         (X86_CR0_WP | X86_CR0_NE)
 100 #define KVM_VM_CR0_ALWAYS_ON                                            \
 101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 104          | X86_CR4_OSXMMEXCPT)
 105
 106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 108
 109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 110
 111 /*
 112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 113  * ple_gap:    upper bound on the amount of time between two successive
 114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 115  *             According to test, this time is usually smaller than 128 cycles.
 116  * ple_window: upper bound on the amount of time a guest is allowed to execute
 117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 118  *             less than 2^12 cycles
 119  * Time is measured based on a counter that runs at the same rate as the TSC,
 120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 121  */
 122 #define KVM_VMX_DEFAULT_PLE_GAP    128
 123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 125 module_param(ple_gap, int, S_IRUGO);
 126
 127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 128 module_param(ple_window, int, S_IRUGO);
 129
 130 #define NR_AUTOLOAD_MSRS 8
 131 #define VMCS02_POOL_SIZE 1
 132
 133 struct vmcs {
 134         u32 revision_id;
 135         u32 abort;
 136         char data[0];
 137 };
 138
 139 /*
 140  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 141  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 142  * loaded on this CPU (so we can clear them if the CPU goes down).
 143  */
 144 struct loaded_vmcs {
 145         struct vmcs *vmcs;
 146         int cpu;
 147         int launched;
 148         struct list_head loaded_vmcss_on_cpu_link;
 149 };
 150
 151 struct shared_msr_entry {
 152         unsigned index;
 153         u64 data;
 154         u64 mask;
 155 };
 156
 157 /*
 158  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 159  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 160  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 161  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 162  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 163  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 164  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 165  * underlying hardware which will be used to run L2.
 166  * This structure is packed to ensure that its layout is identical across
 167  * machines (necessary for live migration).
 168  * If there are changes in this struct, VMCS12_REVISION must be changed.
 169  */
 170 typedef u64 natural_width;
 171 struct __packed vmcs12 {
 172         /* According to the Intel spec, a VMCS region must start with the
 173          * following two fields. Then follow implementation-specific data.
 174          */
 175         u32 revision_id;
 176         u32 abort;
 177
 178         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 179         u32 padding[7]; /* room for future expansion */
 180
 181         u64 io_bitmap_a;
 182         u64 io_bitmap_b;
 183         u64 msr_bitmap;
 184         u64 vm_exit_msr_store_addr;
 185         u64 vm_exit_msr_load_addr;
 186         u64 vm_entry_msr_load_addr;
 187         u64 tsc_offset;
 188         u64 virtual_apic_page_addr;
 189         u64 apic_access_addr;
 190         u64 ept_pointer;
 191         u64 guest_physical_address;
 192         u64 vmcs_link_pointer;
 193         u64 guest_ia32_debugctl;
 194         u64 guest_ia32_pat;
 195         u64 guest_ia32_efer;
 196         u64 guest_ia32_perf_global_ctrl;
 197         u64 guest_pdptr0;
 198         u64 guest_pdptr1;
 199         u64 guest_pdptr2;
 200         u64 guest_pdptr3;
 201         u64 host_ia32_pat;
 202         u64 host_ia32_efer;
 203         u64 host_ia32_perf_global_ctrl;
 204         u64 padding64[8]; /* room for future expansion */
 205         /*
 206          * To allow migration of L1 (complete with its L2 guests) between
 207          * machines of different natural widths (32 or 64 bit), we cannot have
 208          * unsigned long fields with no explict size. We use u64 (aliased
 209          * natural_width) instead. Luckily, x86 is little-endian.
 210          */
 211         natural_width cr0_guest_host_mask;
 212         natural_width cr4_guest_host_mask;
 213         natural_width cr0_read_shadow;
 214         natural_width cr4_read_shadow;
 215         natural_width cr3_target_value0;
 216         natural_width cr3_target_value1;
 217         natural_width cr3_target_value2;
 218         natural_width cr3_target_value3;
 219         natural_width exit_qualification;
 220         natural_width guest_linear_address;
 221         natural_width guest_cr0;
 222         natural_width guest_cr3;
 223         natural_width guest_cr4;
 224         natural_width guest_es_base;
 225         natural_width guest_cs_base;
 226         natural_width guest_ss_base;
 227         natural_width guest_ds_base;
 228         natural_width guest_fs_base;
 229         natural_width guest_gs_base;
 230         natural_width guest_ldtr_base;
 231         natural_width guest_tr_base;
 232         natural_width guest_gdtr_base;
 233         natural_width guest_idtr_base;
 234         natural_width guest_dr7;
 235         natural_width guest_rsp;
 236         natural_width guest_rip;
 237         natural_width guest_rflags;
 238         natural_width guest_pending_dbg_exceptions;
 239         natural_width guest_sysenter_esp;
 240         natural_width guest_sysenter_eip;
 241         natural_width host_cr0;
 242         natural_width host_cr3;
 243         natural_width host_cr4;
 244         natural_width host_fs_base;
 245         natural_width host_gs_base;
 246         natural_width host_tr_base;
 247         natural_width host_gdtr_base;
 248         natural_width host_idtr_base;
 249         natural_width host_ia32_sysenter_esp;
 250         natural_width host_ia32_sysenter_eip;
 251         natural_width host_rsp;
 252         natural_width host_rip;
 253         natural_width paddingl[8]; /* room for future expansion */
 254         u32 pin_based_vm_exec_control;
 255         u32 cpu_based_vm_exec_control;
 256         u32 exception_bitmap;
 257         u32 page_fault_error_code_mask;
 258         u32 page_fault_error_code_match;
 259         u32 cr3_target_count;
 260         u32 vm_exit_controls;
 261         u32 vm_exit_msr_store_count;
 262         u32 vm_exit_msr_load_count;
 263         u32 vm_entry_controls;
 264         u32 vm_entry_msr_load_count;
 265         u32 vm_entry_intr_info_field;
 266         u32 vm_entry_exception_error_code;
 267         u32 vm_entry_instruction_len;
 268         u32 tpr_threshold;
 269         u32 secondary_vm_exec_control;
 270         u32 vm_instruction_error;
 271         u32 vm_exit_reason;
 272         u32 vm_exit_intr_info;
 273         u32 vm_exit_intr_error_code;
 274         u32 idt_vectoring_info_field;
 275         u32 idt_vectoring_error_code;
 276         u32 vm_exit_instruction_len;
 277         u32 vmx_instruction_info;
 278         u32 guest_es_limit;
 279         u32 guest_cs_limit;
 280         u32 guest_ss_limit;
 281         u32 guest_ds_limit;
 282         u32 guest_fs_limit;
 283         u32 guest_gs_limit;
 284         u32 guest_ldtr_limit;
 285         u32 guest_tr_limit;
 286         u32 guest_gdtr_limit;
 287         u32 guest_idtr_limit;
 288         u32 guest_es_ar_bytes;
 289         u32 guest_cs_ar_bytes;
 290         u32 guest_ss_ar_bytes;
 291         u32 guest_ds_ar_bytes;
 292         u32 guest_fs_ar_bytes;
 293         u32 guest_gs_ar_bytes;
 294         u32 guest_ldtr_ar_bytes;
 295         u32 guest_tr_ar_bytes;
 296         u32 guest_interruptibility_info;
 297         u32 guest_activity_state;
 298         u32 guest_sysenter_cs;
 299         u32 host_ia32_sysenter_cs;
 300         u32 padding32[8]; /* room for future expansion */
 301         u16 virtual_processor_id;
 302         u16 guest_es_selector;
 303         u16 guest_cs_selector;
 304         u16 guest_ss_selector;
 305         u16 guest_ds_selector;
 306         u16 guest_fs_selector;
 307         u16 guest_gs_selector;
 308         u16 guest_ldtr_selector;
 309         u16 guest_tr_selector;
 310         u16 host_es_selector;
 311         u16 host_cs_selector;
 312         u16 host_ss_selector;
 313         u16 host_ds_selector;
 314         u16 host_fs_selector;
 315         u16 host_gs_selector;
 316         u16 host_tr_selector;
 317 };
 318
 319 /*
 320  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 321  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 322  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 323  */
 324 #define VMCS12_REVISION 0x11e57ed0
 325
 326 /*
 327  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 328  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 329  * current implementation, 4K are reserved to avoid future complications.
 330  */
 331 #define VMCS12_SIZE 0x1000
 332
 333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 334 struct vmcs02_list {
 335         struct list_head list;
 336         gpa_t vmptr;
 337         struct loaded_vmcs vmcs02;
 338 };
 339
 340 /*
 341  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 342  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 343  */
 344 struct nested_vmx {
 345         /* Has the level1 guest done vmxon? */
 346         bool vmxon;
 347
 348         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 349         gpa_t current_vmptr;
 350         /* The host-usable pointer to the above */
 351         struct page *current_vmcs12_page;
 352         struct vmcs12 *current_vmcs12;
 353
 354         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 355         struct list_head vmcs02_pool;
 356         int vmcs02_num;
 357         u64 vmcs01_tsc_offset;
 358         /* L2 must run next, and mustn't decide to exit to L1. */
 359         bool nested_run_pending;
 360         /*
 361          * Guest pages referred to in vmcs02 with host-physical pointers, so
 362          * we must keep them pinned while L2 runs.
 363          */
 364         struct page *apic_access_page;
 365 };
 366
 367 struct vcpu_vmx {
 368         struct kvm_vcpu       vcpu;
 369         unsigned long         host_rsp;
 370         u8                    fail;
 371         u8                    cpl;
 372         bool                  nmi_known_unmasked;
 373         u32                   exit_intr_info;
 374         u32                   idt_vectoring_info;
 375         ulong                 rflags;
 376         struct shared_msr_entry *guest_msrs;
 377         int                   nmsrs;
 378         int                   save_nmsrs;
 379 #ifdef CONFIG_X86_64
 380         u64                   msr_host_kernel_gs_base;
 381         u64                   msr_guest_kernel_gs_base;
 382 #endif
 383         /*
 384          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 385          * non-nested (L1) guest, it always points to vmcs01. For a nested
 386          * guest (L2), it points to a different VMCS.
 387          */
 388         struct loaded_vmcs    vmcs01;
 389         struct loaded_vmcs   *loaded_vmcs;
 390         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 391         struct msr_autoload {
 392                 unsigned nr;
 393                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 394                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 395         } msr_autoload;
 396         struct {
 397                 int           loaded;
 398                 u16           fs_sel, gs_sel, ldt_sel;
 399 #ifdef CONFIG_X86_64
 400                 u16           ds_sel, es_sel;
 401 #endif
 402                 int           gs_ldt_reload_needed;
 403                 int           fs_reload_needed;
 404         } host_state;
 405         struct {
 406                 int vm86_active;
 407                 ulong save_rflags;
 408                 struct kvm_save_segment {
 409                         u16 selector;
 410                         unsigned long base;
 411                         u32 limit;
 412                         u32 ar;
 413                 } tr, es, ds, fs, gs;
 414         } rmode;
 415         struct {
 416                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 417                 struct kvm_save_segment seg[8];
 418         } segment_cache;
 419         int vpid;
 420         bool emulation_required;
 421
 422         /* Support for vnmi-less CPUs */
 423         int soft_vnmi_blocked;
 424         ktime_t entry_time;
 425         s64 vnmi_blocked_time;
 426         u32 exit_reason;
 427
 428         bool rdtscp_enabled;
 429
 430         /* Support for a guest hypervisor (nested VMX) */
 431         struct nested_vmx nested;
 432 };
 433
 434 enum segment_cache_field {
 435         SEG_FIELD_SEL = 0,
 436         SEG_FIELD_BASE = 1,
 437         SEG_FIELD_LIMIT = 2,
 438         SEG_FIELD_AR = 3,
 439
 440         SEG_FIELD_NR = 4
 441 };
 442
 443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 444 {
 445         return container_of(vcpu, struct vcpu_vmx, vcpu);
 446 }
 447
 448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 449 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 450 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 451                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 452
 453 static unsigned short vmcs_field_to_offset_table[] = {
 454         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 455         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 456         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 457         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 458         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 459         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 460         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 461         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 462         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 463         FIELD(HOST_ES_SELECTOR, host_es_selector),
 464         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 465         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 466         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 467         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 468         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 469         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 470         FIELD64(IO_BITMAP_A, io_bitmap_a),
 471         FIELD64(IO_BITMAP_B, io_bitmap_b),
 472         FIELD64(MSR_BITMAP, msr_bitmap),
 473         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 474         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 475         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 476         FIELD64(TSC_OFFSET, tsc_offset),
 477         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 478         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 479         FIELD64(EPT_POINTER, ept_pointer),
 480         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 481         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 482         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 483         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 484         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 485         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 486         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 487         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 488         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 489         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 490         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 491         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 492         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 493         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 494         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 495         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 496         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 497         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 498         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 499         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 500         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 501         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 502         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 503         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 504         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 505         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 506         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 507         FIELD(TPR_THRESHOLD, tpr_threshold),
 508         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 509         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 510         FIELD(VM_EXIT_REASON, vm_exit_reason),
 511         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 512         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 513         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 514         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 515         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 516         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 517         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 518         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 519         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 520         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 521         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 522         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 523         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 524         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 525         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 526         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 527         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 528         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 529         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 530         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 531         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 532         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 533         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 534         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 535         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 536         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 537         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 538         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 539         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 540         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 541         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 542         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 543         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 544         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 545         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 546         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 547         FIELD(EXIT_QUALIFICATION, exit_qualification),
 548         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 549         FIELD(GUEST_CR0, guest_cr0),
 550         FIELD(GUEST_CR3, guest_cr3),
 551         FIELD(GUEST_CR4, guest_cr4),
 552         FIELD(GUEST_ES_BASE, guest_es_base),
 553         FIELD(GUEST_CS_BASE, guest_cs_base),
 554         FIELD(GUEST_SS_BASE, guest_ss_base),
 555         FIELD(GUEST_DS_BASE, guest_ds_base),
 556         FIELD(GUEST_FS_BASE, guest_fs_base),
 557         FIELD(GUEST_GS_BASE, guest_gs_base),
 558         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 559         FIELD(GUEST_TR_BASE, guest_tr_base),
 560         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 561         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 562         FIELD(GUEST_DR7, guest_dr7),
 563         FIELD(GUEST_RSP, guest_rsp),
 564         FIELD(GUEST_RIP, guest_rip),
 565         FIELD(GUEST_RFLAGS, guest_rflags),
 566         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 567         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 568         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 569         FIELD(HOST_CR0, host_cr0),
 570         FIELD(HOST_CR3, host_cr3),
 571         FIELD(HOST_CR4, host_cr4),
 572         FIELD(HOST_FS_BASE, host_fs_base),
 573         FIELD(HOST_GS_BASE, host_gs_base),
 574         FIELD(HOST_TR_BASE, host_tr_base),
 575         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 576         FIELD(HOST_IDTR_BASE, host_idtr_base),
 577         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 578         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 579         FIELD(HOST_RSP, host_rsp),
 580         FIELD(HOST_RIP, host_rip),
 581 };
 582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 583
 584 static inline short vmcs_field_to_offset(unsigned long field)
 585 {
 586         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 587                 return -1;
 588         return vmcs_field_to_offset_table[field];
 589 }
 590
 591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 592 {
 593         return to_vmx(vcpu)->nested.current_vmcs12;
 594 }
 595
 596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 597 {
 598         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 599         if (is_error_page(page)) {
 600                 kvm_release_page_clean(page);
 601                 return NULL;
 602         }
 603         return page;
 604 }
 605
 606 static void nested_release_page(struct page *page)
 607 {
 608         kvm_release_page_dirty(page);
 609 }
 610
 611 static void nested_release_page_clean(struct page *page)
 612 {
 613         kvm_release_page_clean(page);
 614 }
 615
 616 static u64 construct_eptp(unsigned long root_hpa);
 617 static void kvm_cpu_vmxon(u64 addr);
 618 static void kvm_cpu_vmxoff(void);
 619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 622                             struct kvm_segment *var, int seg);
 623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 624                             struct kvm_segment *var, int seg);
 625
 626 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 627 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 628 /*
 629  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 630  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 631  */
 632 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 633 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 634
 635 static unsigned long *vmx_io_bitmap_a;
 636 static unsigned long *vmx_io_bitmap_b;
 637 static unsigned long *vmx_msr_bitmap_legacy;
 638 static unsigned long *vmx_msr_bitmap_longmode;
 639
 640 static bool cpu_has_load_ia32_efer;
 641 static bool cpu_has_load_perf_global_ctrl;
 642
 643 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 644 static DEFINE_SPINLOCK(vmx_vpid_lock);
 645
 646 static struct vmcs_config {
 647         int size;
 648         int order;
 649         u32 revision_id;
 650         u32 pin_based_exec_ctrl;
 651         u32 cpu_based_exec_ctrl;
 652         u32 cpu_based_2nd_exec_ctrl;
 653         u32 vmexit_ctrl;
 654         u32 vmentry_ctrl;
 655 } vmcs_config;
 656
 657 static struct vmx_capability {
 658         u32 ept;
 659         u32 vpid;
 660 } vmx_capability;
 661
 662 #define VMX_SEGMENT_FIELD(seg)                                  \
 663         [VCPU_SREG_##seg] = {                                   \
 664                 .selector = GUEST_##seg##_SELECTOR,             \
 665                 .base = GUEST_##seg##_BASE,                     \
 666                 .limit = GUEST_##seg##_LIMIT,                   \
 667                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 668         }
 669
 670 static struct kvm_vmx_segment_field {
 671         unsigned selector;
 672         unsigned base;
 673         unsigned limit;
 674         unsigned ar_bytes;
 675 } kvm_vmx_segment_fields[] = {
 676         VMX_SEGMENT_FIELD(CS),
 677         VMX_SEGMENT_FIELD(DS),
 678         VMX_SEGMENT_FIELD(ES),
 679         VMX_SEGMENT_FIELD(FS),
 680         VMX_SEGMENT_FIELD(GS),
 681         VMX_SEGMENT_FIELD(SS),
 682         VMX_SEGMENT_FIELD(TR),
 683         VMX_SEGMENT_FIELD(LDTR),
 684 };
 685
 686 static u64 host_efer;
 687
 688 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 689
 690 /*
 691  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 692  * away by decrementing the array size.
 693  */
 694 static const u32 vmx_msr_index[] = {
 695 #ifdef CONFIG_X86_64
 696         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 697 #endif
 698         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 699 };
 700 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 701
 702 static inline bool is_page_fault(u32 intr_info)
 703 {
 704         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 705                              INTR_INFO_VALID_MASK)) ==
 706                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 707 }
 708
 709 static inline bool is_no_device(u32 intr_info)
 710 {
 711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 712                              INTR_INFO_VALID_MASK)) ==
 713                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 714 }
 715
 716 static inline bool is_invalid_opcode(u32 intr_info)
 717 {
 718         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 719                              INTR_INFO_VALID_MASK)) ==
 720                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 721 }
 722
 723 static inline bool is_external_interrupt(u32 intr_info)
 724 {
 725         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 726                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 727 }
 728
 729 static inline bool is_machine_check(u32 intr_info)
 730 {
 731         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 732                              INTR_INFO_VALID_MASK)) ==
 733                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 734 }
 735
 736 static inline bool cpu_has_vmx_msr_bitmap(void)
 737 {
 738         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 739 }
 740
 741 static inline bool cpu_has_vmx_tpr_shadow(void)
 742 {
 743         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 744 }
 745
 746 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 747 {
 748         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 749 }
 750
 751 static inline bool cpu_has_secondary_exec_ctrls(void)
 752 {
 753         return vmcs_config.cpu_based_exec_ctrl &
 754                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 755 }
 756
 757 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 758 {
 759         return vmcs_config.cpu_based_2nd_exec_ctrl &
 760                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 761 }
 762
 763 static inline bool cpu_has_vmx_flexpriority(void)
 764 {
 765         return cpu_has_vmx_tpr_shadow() &&
 766                 cpu_has_vmx_virtualize_apic_accesses();
 767 }
 768
 769 static inline bool cpu_has_vmx_ept_execute_only(void)
 770 {
 771         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 775 {
 776         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_eptp_writeback(void)
 780 {
 781         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_ept_2m_page(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_ept_1g_page(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_ept_4levels(void)
 795 {
 796         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_ept_ad_bits(void)
 800 {
 801         return vmx_capability.ept & VMX_EPT_AD_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_invept_individual_addr(void)
 805 {
 806         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 807 }
 808
 809 static inline bool cpu_has_vmx_invept_context(void)
 810 {
 811         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 812 }
 813
 814 static inline bool cpu_has_vmx_invept_global(void)
 815 {
 816         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 817 }
 818
 819 static inline bool cpu_has_vmx_invvpid_single(void)
 820 {
 821         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 822 }
 823
 824 static inline bool cpu_has_vmx_invvpid_global(void)
 825 {
 826         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 827 }
 828
 829 static inline bool cpu_has_vmx_ept(void)
 830 {
 831         return vmcs_config.cpu_based_2nd_exec_ctrl &
 832                 SECONDARY_EXEC_ENABLE_EPT;
 833 }
 834
 835 static inline bool cpu_has_vmx_unrestricted_guest(void)
 836 {
 837         return vmcs_config.cpu_based_2nd_exec_ctrl &
 838                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 839 }
 840
 841 static inline bool cpu_has_vmx_ple(void)
 842 {
 843         return vmcs_config.cpu_based_2nd_exec_ctrl &
 844                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 845 }
 846
 847 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 848 {
 849         return flexpriority_enabled && irqchip_in_kernel(kvm);
 850 }
 851
 852 static inline bool cpu_has_vmx_vpid(void)
 853 {
 854         return vmcs_config.cpu_based_2nd_exec_ctrl &
 855                 SECONDARY_EXEC_ENABLE_VPID;
 856 }
 857
 858 static inline bool cpu_has_vmx_rdtscp(void)
 859 {
 860         return vmcs_config.cpu_based_2nd_exec_ctrl &
 861                 SECONDARY_EXEC_RDTSCP;
 862 }
 863
 864 static inline bool cpu_has_vmx_invpcid(void)
 865 {
 866         return vmcs_config.cpu_based_2nd_exec_ctrl &
 867                 SECONDARY_EXEC_ENABLE_INVPCID;
 868 }
 869
 870 static inline bool cpu_has_virtual_nmis(void)
 871 {
 872         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 873 }
 874
 875 static inline bool cpu_has_vmx_wbinvd_exit(void)
 876 {
 877         return vmcs_config.cpu_based_2nd_exec_ctrl &
 878                 SECONDARY_EXEC_WBINVD_EXITING;
 879 }
 880
 881 static inline bool report_flexpriority(void)
 882 {
 883         return flexpriority_enabled;
 884 }
 885
 886 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 887 {
 888         return vmcs12->cpu_based_vm_exec_control & bit;
 889 }
 890
 891 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 892 {
 893         return (vmcs12->cpu_based_vm_exec_control &
 894                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 895                 (vmcs12->secondary_vm_exec_control & bit);
 896 }
 897
 898 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 899         struct kvm_vcpu *vcpu)
 900 {
 901         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 902 }
 903
 904 static inline bool is_exception(u32 intr_info)
 905 {
 906         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 907                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 908 }
 909
 910 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 911 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 912                         struct vmcs12 *vmcs12,
 913                         u32 reason, unsigned long qualification);
 914
 915 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 916 {
 917         int i;
 918
 919         for (i = 0; i < vmx->nmsrs; ++i)
 920                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 921                         return i;
 922         return -1;
 923 }
 924
 925 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 926 {
 927     struct {
 928         u64 vpid : 16;
 929         u64 rsvd : 48;
 930         u64 gva;
 931     } operand = { vpid, 0, gva };
 932
 933     asm volatile (__ex(ASM_VMX_INVVPID)
 934                   /* CF==1 or ZF==1 --> rc = -1 */
 935                   "; ja 1f ; ud2 ; 1:"
 936                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 937 }
 938
 939 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 940 {
 941         struct {
 942                 u64 eptp, gpa;
 943         } operand = {eptp, gpa};
 944
 945         asm volatile (__ex(ASM_VMX_INVEPT)
 946                         /* CF==1 or ZF==1 --> rc = -1 */
 947                         "; ja 1f ; ud2 ; 1:\n"
 948                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 949 }
 950
 951 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 952 {
 953         int i;
 954
 955         i = __find_msr_index(vmx, msr);
 956         if (i >= 0)
 957                 return &vmx->guest_msrs[i];
 958         return NULL;
 959 }
 960
 961 static void vmcs_clear(struct vmcs *vmcs)
 962 {
 963         u64 phys_addr = __pa(vmcs);
 964         u8 error;
 965
 966         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 967                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 968                       : "cc", "memory");
 969         if (error)
 970                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 971                        vmcs, phys_addr);
 972 }
 973
 974 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 975 {
 976         vmcs_clear(loaded_vmcs->vmcs);
 977         loaded_vmcs->cpu = -1;
 978         loaded_vmcs->launched = 0;
 979 }
 980
 981 static void vmcs_load(struct vmcs *vmcs)
 982 {
 983         u64 phys_addr = __pa(vmcs);
 984         u8 error;
 985
 986         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 987                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 988                         : "cc", "memory");
 989         if (error)
 990                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 991                        vmcs, phys_addr);
 992 }
 993
 994 static void __loaded_vmcs_clear(void *arg)
 995 {
 996         struct loaded_vmcs *loaded_vmcs = arg;
 997         int cpu = raw_smp_processor_id();
 998
 999         if (loaded_vmcs->cpu != cpu)
1000                 return; /* vcpu migration can race with cpu offline */
1001         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1002                 per_cpu(current_vmcs, cpu) = NULL;
1003         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1004         loaded_vmcs_init(loaded_vmcs);
1005 }
1006
1007 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1008 {
1009         if (loaded_vmcs->cpu != -1)
1010                 smp_call_function_single(
1011                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1012 }
1013
1014 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1015 {
1016         if (vmx->vpid == 0)
1017                 return;
1018
1019         if (cpu_has_vmx_invvpid_single())
1020                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1021 }
1022
1023 static inline void vpid_sync_vcpu_global(void)
1024 {
1025         if (cpu_has_vmx_invvpid_global())
1026                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1027 }
1028
1029 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1030 {
1031         if (cpu_has_vmx_invvpid_single())
1032                 vpid_sync_vcpu_single(vmx);
1033         else
1034                 vpid_sync_vcpu_global();
1035 }
1036
1037 static inline void ept_sync_global(void)
1038 {
1039         if (cpu_has_vmx_invept_global())
1040                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1041 }
1042
1043 static inline void ept_sync_context(u64 eptp)
1044 {
1045         if (enable_ept) {
1046                 if (cpu_has_vmx_invept_context())
1047                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1048                 else
1049                         ept_sync_global();
1050         }
1051 }
1052
1053 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1054 {
1055         if (enable_ept) {
1056                 if (cpu_has_vmx_invept_individual_addr())
1057                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1058                                         eptp, gpa);
1059                 else
1060                         ept_sync_context(eptp);
1061         }
1062 }
1063
1064 static __always_inline unsigned long vmcs_readl(unsigned long field)
1065 {
1066         unsigned long value;
1067
1068         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1069                       : "=a"(value) : "d"(field) : "cc");
1070         return value;
1071 }
1072
1073 static __always_inline u16 vmcs_read16(unsigned long field)
1074 {
1075         return vmcs_readl(field);
1076 }
1077
1078 static __always_inline u32 vmcs_read32(unsigned long field)
1079 {
1080         return vmcs_readl(field);
1081 }
1082
1083 static __always_inline u64 vmcs_read64(unsigned long field)
1084 {
1085 #ifdef CONFIG_X86_64
1086         return vmcs_readl(field);
1087 #else
1088         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1089 #endif
1090 }
1091
1092 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1093 {
1094         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1095                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1096         dump_stack();
1097 }
1098
1099 static void vmcs_writel(unsigned long field, unsigned long value)
1100 {
1101         u8 error;
1102
1103         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1104                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1105         if (unlikely(error))
1106                 vmwrite_error(field, value);
1107 }
1108
1109 static void vmcs_write16(unsigned long field, u16 value)
1110 {
1111         vmcs_writel(field, value);
1112 }
1113
1114 static void vmcs_write32(unsigned long field, u32 value)
1115 {
1116         vmcs_writel(field, value);
1117 }
1118
1119 static void vmcs_write64(unsigned long field, u64 value)
1120 {
1121         vmcs_writel(field, value);
1122 #ifndef CONFIG_X86_64
1123         asm volatile ("");
1124         vmcs_writel(field+1, value >> 32);
1125 #endif
1126 }
1127
1128 static void vmcs_clear_bits(unsigned long field, u32 mask)
1129 {
1130         vmcs_writel(field, vmcs_readl(field) & ~mask);
1131 }
1132
1133 static void vmcs_set_bits(unsigned long field, u32 mask)
1134 {
1135         vmcs_writel(field, vmcs_readl(field) | mask);
1136 }
1137
1138 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1139 {
1140         vmx->segment_cache.bitmask = 0;
1141 }
1142
1143 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1144                                        unsigned field)
1145 {
1146         bool ret;
1147         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1148
1149         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1150                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1151                 vmx->segment_cache.bitmask = 0;
1152         }
1153         ret = vmx->segment_cache.bitmask & mask;
1154         vmx->segment_cache.bitmask |= mask;
1155         return ret;
1156 }
1157
1158 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1159 {
1160         u16 *p = &vmx->segment_cache.seg[seg].selector;
1161
1162         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1163                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1164         return *p;
1165 }
1166
1167 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1168 {
1169         ulong *p = &vmx->segment_cache.seg[seg].base;
1170
1171         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1172                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1173         return *p;
1174 }
1175
1176 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1177 {
1178         u32 *p = &vmx->segment_cache.seg[seg].limit;
1179
1180         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1181                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1182         return *p;
1183 }
1184
1185 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1186 {
1187         u32 *p = &vmx->segment_cache.seg[seg].ar;
1188
1189         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1190                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1191         return *p;
1192 }
1193
1194 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1195 {
1196         u32 eb;
1197
1198         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1199              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1200         if ((vcpu->guest_debug &
1201              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1202             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1203                 eb |= 1u << BP_VECTOR;
1204         if (to_vmx(vcpu)->rmode.vm86_active)
1205                 eb = ~0;
1206         if (enable_ept)
1207                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1208         if (vcpu->fpu_active)
1209                 eb &= ~(1u << NM_VECTOR);
1210
1211         /* When we are running a nested L2 guest and L1 specified for it a
1212          * certain exception bitmap, we must trap the same exceptions and pass
1213          * them to L1. When running L2, we will only handle the exceptions
1214          * specified above if L1 did not want them.
1215          */
1216         if (is_guest_mode(vcpu))
1217                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1218
1219         vmcs_write32(EXCEPTION_BITMAP, eb);
1220 }
1221
1222 static void clear_atomic_switch_msr_special(unsigned long entry,
1223                 unsigned long exit)
1224 {
1225         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1226         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1227 }
1228
1229 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1230 {
1231         unsigned i;
1232         struct msr_autoload *m = &vmx->msr_autoload;
1233
1234         switch (msr) {
1235         case MSR_EFER:
1236                 if (cpu_has_load_ia32_efer) {
1237                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1238                                         VM_EXIT_LOAD_IA32_EFER);
1239                         return;
1240                 }
1241                 break;
1242         case MSR_CORE_PERF_GLOBAL_CTRL:
1243                 if (cpu_has_load_perf_global_ctrl) {
1244                         clear_atomic_switch_msr_special(
1245                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1246                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1247                         return;
1248                 }
1249                 break;
1250         }
1251
1252         for (i = 0; i < m->nr; ++i)
1253                 if (m->guest[i].index == msr)
1254                         break;
1255
1256         if (i == m->nr)
1257                 return;
1258         --m->nr;
1259         m->guest[i] = m->guest[m->nr];
1260         m->host[i] = m->host[m->nr];
1261         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1262         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1263 }
1264
1265 static void add_atomic_switch_msr_special(unsigned long entry,
1266                 unsigned long exit, unsigned long guest_val_vmcs,
1267                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1268 {
1269         vmcs_write64(guest_val_vmcs, guest_val);
1270         vmcs_write64(host_val_vmcs, host_val);
1271         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1272         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1273 }
1274
1275 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1276                                   u64 guest_val, u64 host_val)
1277 {
1278         unsigned i;
1279         struct msr_autoload *m = &vmx->msr_autoload;
1280
1281         switch (msr) {
1282         case MSR_EFER:
1283                 if (cpu_has_load_ia32_efer) {
1284                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1285                                         VM_EXIT_LOAD_IA32_EFER,
1286                                         GUEST_IA32_EFER,
1287                                         HOST_IA32_EFER,
1288                                         guest_val, host_val);
1289                         return;
1290                 }
1291                 break;
1292         case MSR_CORE_PERF_GLOBAL_CTRL:
1293                 if (cpu_has_load_perf_global_ctrl) {
1294                         add_atomic_switch_msr_special(
1295                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1296                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1297                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1298                                         HOST_IA32_PERF_GLOBAL_CTRL,
1299                                         guest_val, host_val);
1300                         return;
1301                 }
1302                 break;
1303         }
1304
1305         for (i = 0; i < m->nr; ++i)
1306                 if (m->guest[i].index == msr)
1307                         break;
1308
1309         if (i == NR_AUTOLOAD_MSRS) {
1310                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1311                                 "Can't add msr %x\n", msr);
1312                 return;
1313         } else if (i == m->nr) {
1314                 ++m->nr;
1315                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1316                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1317         }
1318
1319         m->guest[i].index = msr;
1320         m->guest[i].value = guest_val;
1321         m->host[i].index = msr;
1322         m->host[i].value = host_val;
1323 }
1324
1325 static void reload_tss(void)
1326 {
1327         /*
1328          * VT restores TR but not its size.  Useless.
1329          */
1330         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1331         struct desc_struct *descs;
1332
1333         descs = (void *)gdt->address;
1334         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1335         load_TR_desc();
1336 }
1337
1338 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1339 {
1340         u64 guest_efer;
1341         u64 ignore_bits;
1342
1343         guest_efer = vmx->vcpu.arch.efer;
1344
1345         /*
1346          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1347          * outside long mode
1348          */
1349         ignore_bits = EFER_NX | EFER_SCE;
1350 #ifdef CONFIG_X86_64
1351         ignore_bits |= EFER_LMA | EFER_LME;
1352         /* SCE is meaningful only in long mode on Intel */
1353         if (guest_efer & EFER_LMA)
1354                 ignore_bits &= ~(u64)EFER_SCE;
1355 #endif
1356         guest_efer &= ~ignore_bits;
1357         guest_efer |= host_efer & ignore_bits;
1358         vmx->guest_msrs[efer_offset].data = guest_efer;
1359         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1360
1361         clear_atomic_switch_msr(vmx, MSR_EFER);
1362         /* On ept, can't emulate nx, and must switch nx atomically */
1363         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1364                 guest_efer = vmx->vcpu.arch.efer;
1365                 if (!(guest_efer & EFER_LMA))
1366                         guest_efer &= ~EFER_LME;
1367                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1368                 return false;
1369         }
1370
1371         return true;
1372 }
1373
1374 static unsigned long segment_base(u16 selector)
1375 {
1376         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1377         struct desc_struct *d;
1378         unsigned long table_base;
1379         unsigned long v;
1380
1381         if (!(selector & ~3))
1382                 return 0;
1383
1384         table_base = gdt->address;
1385
1386         if (selector & 4) {           /* from ldt */
1387                 u16 ldt_selector = kvm_read_ldt();
1388
1389                 if (!(ldt_selector & ~3))
1390                         return 0;
1391
1392                 table_base = segment_base(ldt_selector);
1393         }
1394         d = (struct desc_struct *)(table_base + (selector & ~7));
1395         v = get_desc_base(d);
1396 #ifdef CONFIG_X86_64
1397        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1398                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1399 #endif
1400         return v;
1401 }
1402
1403 static inline unsigned long kvm_read_tr_base(void)
1404 {
1405         u16 tr;
1406         asm("str %0" : "=g"(tr));
1407         return segment_base(tr);
1408 }
1409
1410 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1411 {
1412         struct vcpu_vmx *vmx = to_vmx(vcpu);
1413         int i;
1414
1415         if (vmx->host_state.loaded)
1416                 return;
1417
1418         vmx->host_state.loaded = 1;
1419         /*
1420          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1421          * allow segment selectors with cpl > 0 or ti == 1.
1422          */
1423         vmx->host_state.ldt_sel = kvm_read_ldt();
1424         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1425         savesegment(fs, vmx->host_state.fs_sel);
1426         if (!(vmx->host_state.fs_sel & 7)) {
1427                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1428                 vmx->host_state.fs_reload_needed = 0;
1429         } else {
1430                 vmcs_write16(HOST_FS_SELECTOR, 0);
1431                 vmx->host_state.fs_reload_needed = 1;
1432         }
1433         savesegment(gs, vmx->host_state.gs_sel);
1434         if (!(vmx->host_state.gs_sel & 7))
1435                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1436         else {
1437                 vmcs_write16(HOST_GS_SELECTOR, 0);
1438                 vmx->host_state.gs_ldt_reload_needed = 1;
1439         }
1440
1441 #ifdef CONFIG_X86_64
1442         savesegment(ds, vmx->host_state.ds_sel);
1443         savesegment(es, vmx->host_state.es_sel);
1444 #endif
1445
1446 #ifdef CONFIG_X86_64
1447         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1448         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1449 #else
1450         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1451         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1452 #endif
1453
1454 #ifdef CONFIG_X86_64
1455         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1456         if (is_long_mode(&vmx->vcpu))
1457                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1458 #endif
1459         for (i = 0; i < vmx->save_nmsrs; ++i)
1460                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1461                                    vmx->guest_msrs[i].data,
1462                                    vmx->guest_msrs[i].mask);
1463 }
1464
1465 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1466 {
1467         if (!vmx->host_state.loaded)
1468                 return;
1469
1470         ++vmx->vcpu.stat.host_state_reload;
1471         vmx->host_state.loaded = 0;
1472 #ifdef CONFIG_X86_64
1473         if (is_long_mode(&vmx->vcpu))
1474                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1475 #endif
1476         if (vmx->host_state.gs_ldt_reload_needed) {
1477                 kvm_load_ldt(vmx->host_state.ldt_sel);
1478 #ifdef CONFIG_X86_64
1479                 load_gs_index(vmx->host_state.gs_sel);
1480 #else
1481                 loadsegment(gs, vmx->host_state.gs_sel);
1482 #endif
1483         }
1484         if (vmx->host_state.fs_reload_needed)
1485                 loadsegment(fs, vmx->host_state.fs_sel);
1486 #ifdef CONFIG_X86_64
1487         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1488                 loadsegment(ds, vmx->host_state.ds_sel);
1489                 loadsegment(es, vmx->host_state.es_sel);
1490         }
1491 #endif
1492         reload_tss();
1493 #ifdef CONFIG_X86_64
1494         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1495 #endif
1496         if (user_has_fpu())
1497                 clts();
1498         load_gdt(&__get_cpu_var(host_gdt));
1499 }
1500
1501 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1502 {
1503         preempt_disable();
1504         __vmx_load_host_state(vmx);
1505         preempt_enable();
1506 }
1507
1508 /*
1509  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1510  * vcpu mutex is already taken.
1511  */
1512 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1513 {
1514         struct vcpu_vmx *vmx = to_vmx(vcpu);
1515         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1516
1517         if (!vmm_exclusive)
1518                 kvm_cpu_vmxon(phys_addr);
1519         else if (vmx->loaded_vmcs->cpu != cpu)
1520                 loaded_vmcs_clear(vmx->loaded_vmcs);
1521
1522         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1523                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1524                 vmcs_load(vmx->loaded_vmcs->vmcs);
1525         }
1526
1527         if (vmx->loaded_vmcs->cpu != cpu) {
1528                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1529                 unsigned long sysenter_esp;
1530
1531                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1532                 local_irq_disable();
1533                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1534                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1535                 local_irq_enable();
1536
1537                 /*
1538                  * Linux uses per-cpu TSS and GDT, so set these when switching
1539                  * processors.
1540                  */
1541                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1542                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1543
1544                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1545                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1546                 vmx->loaded_vmcs->cpu = cpu;
1547         }
1548 }
1549
1550 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1551 {
1552         __vmx_load_host_state(to_vmx(vcpu));
1553         if (!vmm_exclusive) {
1554                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1555                 vcpu->cpu = -1;
1556                 kvm_cpu_vmxoff();
1557         }
1558 }
1559
1560 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1561 {
1562         ulong cr0;
1563
1564         if (vcpu->fpu_active)
1565                 return;
1566         vcpu->fpu_active = 1;
1567         cr0 = vmcs_readl(GUEST_CR0);
1568         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1569         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1570         vmcs_writel(GUEST_CR0, cr0);
1571         update_exception_bitmap(vcpu);
1572         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1573         if (is_guest_mode(vcpu))
1574                 vcpu->arch.cr0_guest_owned_bits &=
1575                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1576         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1577 }
1578
1579 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1580
1581 /*
1582  * Return the cr0 value that a nested guest would read. This is a combination
1583  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1584  * its hypervisor (cr0_read_shadow).
1585  */
1586 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1587 {
1588         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1589                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1590 }
1591 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1592 {
1593         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1594                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1595 }
1596
1597 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1598 {
1599         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1600          * set this *before* calling this function.
1601          */
1602         vmx_decache_cr0_guest_bits(vcpu);
1603         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1604         update_exception_bitmap(vcpu);
1605         vcpu->arch.cr0_guest_owned_bits = 0;
1606         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1607         if (is_guest_mode(vcpu)) {
1608                 /*
1609                  * L1's specified read shadow might not contain the TS bit,
1610                  * so now that we turned on shadowing of this bit, we need to
1611                  * set this bit of the shadow. Like in nested_vmx_run we need
1612                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1613                  * up-to-date here because we just decached cr0.TS (and we'll
1614                  * only update vmcs12->guest_cr0 on nested exit).
1615                  */
1616                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1617                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1618                         (vcpu->arch.cr0 & X86_CR0_TS);
1619                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1620         } else
1621                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1622 }
1623
1624 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1625 {
1626         unsigned long rflags, save_rflags;
1627
1628         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1629                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1630                 rflags = vmcs_readl(GUEST_RFLAGS);
1631                 if (to_vmx(vcpu)->rmode.vm86_active) {
1632                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1633                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1634                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1635                 }
1636                 to_vmx(vcpu)->rflags = rflags;
1637         }
1638         return to_vmx(vcpu)->rflags;
1639 }
1640
1641 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1642 {
1643         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1644         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1645         to_vmx(vcpu)->rflags = rflags;
1646         if (to_vmx(vcpu)->rmode.vm86_active) {
1647                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1648                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1649         }
1650         vmcs_writel(GUEST_RFLAGS, rflags);
1651 }
1652
1653 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1654 {
1655         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1656         int ret = 0;
1657
1658         if (interruptibility & GUEST_INTR_STATE_STI)
1659                 ret |= KVM_X86_SHADOW_INT_STI;
1660         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1661                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1662
1663         return ret & mask;
1664 }
1665
1666 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1667 {
1668         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1669         u32 interruptibility = interruptibility_old;
1670
1671         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1672
1673         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1674                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1675         else if (mask & KVM_X86_SHADOW_INT_STI)
1676                 interruptibility |= GUEST_INTR_STATE_STI;
1677
1678         if ((interruptibility != interruptibility_old))
1679                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1680 }
1681
1682 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1683 {
1684         unsigned long rip;
1685
1686         rip = kvm_rip_read(vcpu);
1687         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1688         kvm_rip_write(vcpu, rip);
1689
1690         /* skipping an emulated instruction also counts */
1691         vmx_set_interrupt_shadow(vcpu, 0);
1692 }
1693
1694 /*
1695  * KVM wants to inject page-faults which it got to the guest. This function
1696  * checks whether in a nested guest, we need to inject them to L1 or L2.
1697  * This function assumes it is called with the exit reason in vmcs02 being
1698  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1699  * is running).
1700  */
1701 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1702 {
1703         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1704
1705         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1706         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1707                 return 0;
1708
1709         nested_vmx_vmexit(vcpu);
1710         return 1;
1711 }
1712
1713 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1714                                 bool has_error_code, u32 error_code,
1715                                 bool reinject)
1716 {
1717         struct vcpu_vmx *vmx = to_vmx(vcpu);
1718         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1719
1720         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1721                 nested_pf_handled(vcpu))
1722                 return;
1723
1724         if (has_error_code) {
1725                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1726                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1727         }
1728
1729         if (vmx->rmode.vm86_active) {
1730                 int inc_eip = 0;
1731                 if (kvm_exception_is_soft(nr))
1732                         inc_eip = vcpu->arch.event_exit_inst_len;
1733                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1734                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1735                 return;
1736         }
1737
1738         if (kvm_exception_is_soft(nr)) {
1739                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1740                              vmx->vcpu.arch.event_exit_inst_len);
1741                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1742         } else
1743                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1744
1745         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1746 }
1747
1748 static bool vmx_rdtscp_supported(void)
1749 {
1750         return cpu_has_vmx_rdtscp();
1751 }
1752
1753 static bool vmx_invpcid_supported(void)
1754 {
1755         return cpu_has_vmx_invpcid() && enable_ept;
1756 }
1757
1758 /*
1759  * Swap MSR entry in host/guest MSR entry array.
1760  */
1761 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1762 {
1763         struct shared_msr_entry tmp;
1764
1765         tmp = vmx->guest_msrs[to];
1766         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1767         vmx->guest_msrs[from] = tmp;
1768 }
1769
1770 /*
1771  * Set up the vmcs to automatically save and restore system
1772  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1773  * mode, as fiddling with msrs is very expensive.
1774  */
1775 static void setup_msrs(struct vcpu_vmx *vmx)
1776 {
1777         int save_nmsrs, index;
1778         unsigned long *msr_bitmap;
1779
1780         save_nmsrs = 0;
1781 #ifdef CONFIG_X86_64
1782         if (is_long_mode(&vmx->vcpu)) {
1783                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1784                 if (index >= 0)
1785                         move_msr_up(vmx, index, save_nmsrs++);
1786                 index = __find_msr_index(vmx, MSR_LSTAR);
1787                 if (index >= 0)
1788                         move_msr_up(vmx, index, save_nmsrs++);
1789                 index = __find_msr_index(vmx, MSR_CSTAR);
1790                 if (index >= 0)
1791                         move_msr_up(vmx, index, save_nmsrs++);
1792                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1793                 if (index >= 0 && vmx->rdtscp_enabled)
1794                         move_msr_up(vmx, index, save_nmsrs++);
1795                 /*
1796                  * MSR_STAR is only needed on long mode guests, and only
1797                  * if efer.sce is enabled.
1798                  */
1799                 index = __find_msr_index(vmx, MSR_STAR);
1800                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1801                         move_msr_up(vmx, index, save_nmsrs++);
1802         }
1803 #endif
1804         index = __find_msr_index(vmx, MSR_EFER);
1805         if (index >= 0 && update_transition_efer(vmx, index))
1806                 move_msr_up(vmx, index, save_nmsrs++);
1807
1808         vmx->save_nmsrs = save_nmsrs;
1809
1810         if (cpu_has_vmx_msr_bitmap()) {
1811                 if (is_long_mode(&vmx->vcpu))
1812                         msr_bitmap = vmx_msr_bitmap_longmode;
1813                 else
1814                         msr_bitmap = vmx_msr_bitmap_legacy;
1815
1816                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1817         }
1818 }
1819
1820 /*
1821  * reads and returns guest's timestamp counter "register"
1822  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1823  */
1824 static u64 guest_read_tsc(void)
1825 {
1826         u64 host_tsc, tsc_offset;
1827
1828         rdtscll(host_tsc);
1829         tsc_offset = vmcs_read64(TSC_OFFSET);
1830         return host_tsc + tsc_offset;
1831 }
1832
1833 /*
1834  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1835  * counter, even if a nested guest (L2) is currently running.
1836  */
1837 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1838 {
1839         u64 host_tsc, tsc_offset;
1840
1841         rdtscll(host_tsc);
1842         tsc_offset = is_guest_mode(vcpu) ?
1843                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1844                 vmcs_read64(TSC_OFFSET);
1845         return host_tsc + tsc_offset;
1846 }
1847
1848 /*
1849  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1850  * software catchup for faster rates on slower CPUs.
1851  */
1852 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1853 {
1854         if (!scale)
1855                 return;
1856
1857         if (user_tsc_khz > tsc_khz) {
1858                 vcpu->arch.tsc_catchup = 1;
1859                 vcpu->arch.tsc_always_catchup = 1;
1860         } else
1861                 WARN(1, "user requested TSC rate below hardware speed\n");
1862 }
1863
1864 /*
1865  * writes 'offset' into guest's timestamp counter offset register
1866  */
1867 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1868 {
1869         if (is_guest_mode(vcpu)) {
1870                 /*
1871                  * We're here if L1 chose not to trap WRMSR to TSC. According
1872                  * to the spec, this should set L1's TSC; The offset that L1
1873                  * set for L2 remains unchanged, and still needs to be added
1874                  * to the newly set TSC to get L2's TSC.
1875                  */
1876                 struct vmcs12 *vmcs12;
1877                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1878                 /* recalculate vmcs02.TSC_OFFSET: */
1879                 vmcs12 = get_vmcs12(vcpu);
1880                 vmcs_write64(TSC_OFFSET, offset +
1881                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1882                          vmcs12->tsc_offset : 0));
1883         } else {
1884                 vmcs_write64(TSC_OFFSET, offset);
1885         }
1886 }
1887
1888 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1889 {
1890         u64 offset = vmcs_read64(TSC_OFFSET);
1891         vmcs_write64(TSC_OFFSET, offset + adjustment);
1892         if (is_guest_mode(vcpu)) {
1893                 /* Even when running L2, the adjustment needs to apply to L1 */
1894                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1895         }
1896 }
1897
1898 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1899 {
1900         return target_tsc - native_read_tsc();
1901 }
1902
1903 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1904 {
1905         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1906         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1907 }
1908
1909 /*
1910  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1911  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1912  * all guests if the "nested" module option is off, and can also be disabled
1913  * for a single guest by disabling its VMX cpuid bit.
1914  */
1915 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1916 {
1917         return nested && guest_cpuid_has_vmx(vcpu);
1918 }
1919
1920 /*
1921  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1922  * returned for the various VMX controls MSRs when nested VMX is enabled.
1923  * The same values should also be used to verify that vmcs12 control fields are
1924  * valid during nested entry from L1 to L2.
1925  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1926  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1927  * bit in the high half is on if the corresponding bit in the control field
1928  * may be on. See also vmx_control_verify().
1929  * TODO: allow these variables to be modified (downgraded) by module options
1930  * or other means.
1931  */
1932 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1933 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1934 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1935 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1936 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1937 static __init void nested_vmx_setup_ctls_msrs(void)
1938 {
1939         /*
1940          * Note that as a general rule, the high half of the MSRs (bits in
1941          * the control fields which may be 1) should be initialized by the
1942          * intersection of the underlying hardware's MSR (i.e., features which
1943          * can be supported) and the list of features we want to expose -
1944          * because they are known to be properly supported in our code.
1945          * Also, usually, the low half of the MSRs (bits which must be 1) can
1946          * be set to 0, meaning that L1 may turn off any of these bits. The
1947          * reason is that if one of these bits is necessary, it will appear
1948          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1949          * fields of vmcs01 and vmcs02, will turn these bits off - and
1950          * nested_vmx_exit_handled() will not pass related exits to L1.
1951          * These rules have exceptions below.
1952          */
1953
1954         /* pin-based controls */
1955         /*
1956          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1957          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1958          */
1959         nested_vmx_pinbased_ctls_low = 0x16 ;
1960         nested_vmx_pinbased_ctls_high = 0x16 |
1961                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1962                 PIN_BASED_VIRTUAL_NMIS;
1963
1964         /* exit controls */
1965         nested_vmx_exit_ctls_low = 0;
1966         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1967 #ifdef CONFIG_X86_64
1968         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1969 #else
1970         nested_vmx_exit_ctls_high = 0;
1971 #endif
1972
1973         /* entry controls */
1974         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1975                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1976         nested_vmx_entry_ctls_low = 0;
1977         nested_vmx_entry_ctls_high &=
1978                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1979
1980         /* cpu-based controls */
1981         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1982                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1983         nested_vmx_procbased_ctls_low = 0;
1984         nested_vmx_procbased_ctls_high &=
1985                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1986                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1987                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1988                 CPU_BASED_CR3_STORE_EXITING |
1989 #ifdef CONFIG_X86_64
1990                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1991 #endif
1992                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1993                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1994                 CPU_BASED_RDPMC_EXITING |
1995                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1996         /*
1997          * We can allow some features even when not supported by the
1998          * hardware. For example, L1 can specify an MSR bitmap - and we
1999          * can use it to avoid exits to L1 - even when L0 runs L2
2000          * without MSR bitmaps.
2001          */
2002         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2003
2004         /* secondary cpu-based controls */
2005         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2006                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2007         nested_vmx_secondary_ctls_low = 0;
2008         nested_vmx_secondary_ctls_high &=
2009                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2010 }
2011
2012 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2013 {
2014         /*
2015          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2016          */
2017         return ((control & high) | low) == control;
2018 }
2019
2020 static inline u64 vmx_control_msr(u32 low, u32 high)
2021 {
2022         return low | ((u64)high << 32);
2023 }
2024
2025 /*
2026  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2027  * also let it use VMX-specific MSRs.
2028  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2029  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2030  * like all other MSRs).
2031  */
2032 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2033 {
2034         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2035                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2036                 /*
2037                  * According to the spec, processors which do not support VMX
2038                  * should throw a #GP(0) when VMX capability MSRs are read.
2039                  */
2040                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2041                 return 1;
2042         }
2043
2044         switch (msr_index) {
2045         case MSR_IA32_FEATURE_CONTROL:
2046                 *pdata = 0;
2047                 break;
2048         case MSR_IA32_VMX_BASIC:
2049                 /*
2050                  * This MSR reports some information about VMX support. We
2051                  * should return information about the VMX we emulate for the
2052                  * guest, and the VMCS structure we give it - not about the
2053                  * VMX support of the underlying hardware.
2054                  */
2055                 *pdata = VMCS12_REVISION |
2056                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2057                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2058                 break;
2059         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2060         case MSR_IA32_VMX_PINBASED_CTLS:
2061                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2062                                         nested_vmx_pinbased_ctls_high);
2063                 break;
2064         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2065         case MSR_IA32_VMX_PROCBASED_CTLS:
2066                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2067                                         nested_vmx_procbased_ctls_high);
2068                 break;
2069         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2070         case MSR_IA32_VMX_EXIT_CTLS:
2071                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2072                                         nested_vmx_exit_ctls_high);
2073                 break;
2074         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2075         case MSR_IA32_VMX_ENTRY_CTLS:
2076                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2077                                         nested_vmx_entry_ctls_high);
2078                 break;
2079         case MSR_IA32_VMX_MISC:
2080                 *pdata = 0;
2081                 break;
2082         /*
2083          * These MSRs specify bits which the guest must keep fixed (on or off)
2084          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2085          * We picked the standard core2 setting.
2086          */
2087 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2088 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2089         case MSR_IA32_VMX_CR0_FIXED0:
2090                 *pdata = VMXON_CR0_ALWAYSON;
2091                 break;
2092         case MSR_IA32_VMX_CR0_FIXED1:
2093                 *pdata = -1ULL;
2094                 break;
2095         case MSR_IA32_VMX_CR4_FIXED0:
2096                 *pdata = VMXON_CR4_ALWAYSON;
2097                 break;
2098         case MSR_IA32_VMX_CR4_FIXED1:
2099                 *pdata = -1ULL;
2100                 break;
2101         case MSR_IA32_VMX_VMCS_ENUM:
2102                 *pdata = 0x1f;
2103                 break;
2104         case MSR_IA32_VMX_PROCBASED_CTLS2:
2105                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2106                                         nested_vmx_secondary_ctls_high);
2107                 break;
2108         case MSR_IA32_VMX_EPT_VPID_CAP:
2109                 /* Currently, no nested ept or nested vpid */
2110                 *pdata = 0;
2111                 break;
2112         default:
2113                 return 0;
2114         }
2115
2116         return 1;
2117 }
2118
2119 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2120 {
2121         if (!nested_vmx_allowed(vcpu))
2122                 return 0;
2123
2124         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2125                 /* TODO: the right thing. */
2126                 return 1;
2127         /*
2128          * No need to treat VMX capability MSRs specially: If we don't handle
2129          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2130          */
2131         return 0;
2132 }
2133
2134 /*
2135  * Reads an msr value (of 'msr_index') into 'pdata'.
2136  * Returns 0 on success, non-0 otherwise.
2137  * Assumes vcpu_load() was already called.
2138  */
2139 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2140 {
2141         u64 data;
2142         struct shared_msr_entry *msr;
2143
2144         if (!pdata) {
2145                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2146                 return -EINVAL;
2147         }
2148
2149         switch (msr_index) {
2150 #ifdef CONFIG_X86_64
2151         case MSR_FS_BASE:
2152                 data = vmcs_readl(GUEST_FS_BASE);
2153                 break;
2154         case MSR_GS_BASE:
2155                 data = vmcs_readl(GUEST_GS_BASE);
2156                 break;
2157         case MSR_KERNEL_GS_BASE:
2158                 vmx_load_host_state(to_vmx(vcpu));
2159                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2160                 break;
2161 #endif
2162         case MSR_EFER:
2163                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2164         case MSR_IA32_TSC:
2165                 data = guest_read_tsc();
2166                 break;
2167         case MSR_IA32_SYSENTER_CS:
2168                 data = vmcs_read32(GUEST_SYSENTER_CS);
2169                 break;
2170         case MSR_IA32_SYSENTER_EIP:
2171                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2172                 break;
2173         case MSR_IA32_SYSENTER_ESP:
2174                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2175                 break;
2176         case MSR_TSC_AUX:
2177                 if (!to_vmx(vcpu)->rdtscp_enabled)
2178                         return 1;
2179                 /* Otherwise falls through */
2180         default:
2181                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2182                         return 0;
2183                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2184                 if (msr) {
2185                         data = msr->data;
2186                         break;
2187                 }
2188                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2189         }
2190
2191         *pdata = data;
2192         return 0;
2193 }
2194
2195 /*
2196  * Writes msr value into into the appropriate "register".
2197  * Returns 0 on success, non-0 otherwise.
2198  * Assumes vcpu_load() was already called.
2199  */
2200 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2201 {
2202         struct vcpu_vmx *vmx = to_vmx(vcpu);
2203         struct shared_msr_entry *msr;
2204         int ret = 0;
2205
2206         switch (msr_index) {
2207         case MSR_EFER:
2208                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2209                 break;
2210 #ifdef CONFIG_X86_64
2211         case MSR_FS_BASE:
2212                 vmx_segment_cache_clear(vmx);
2213                 vmcs_writel(GUEST_FS_BASE, data);
2214                 break;
2215         case MSR_GS_BASE:
2216                 vmx_segment_cache_clear(vmx);
2217                 vmcs_writel(GUEST_GS_BASE, data);
2218                 break;
2219         case MSR_KERNEL_GS_BASE:
2220                 vmx_load_host_state(vmx);
2221                 vmx->msr_guest_kernel_gs_base = data;
2222                 break;
2223 #endif
2224         case MSR_IA32_SYSENTER_CS:
2225                 vmcs_write32(GUEST_SYSENTER_CS, data);
2226                 break;
2227         case MSR_IA32_SYSENTER_EIP:
2228                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2229                 break;
2230         case MSR_IA32_SYSENTER_ESP:
2231                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2232                 break;
2233         case MSR_IA32_TSC:
2234                 kvm_write_tsc(vcpu, data);
2235                 break;
2236         case MSR_IA32_CR_PAT:
2237                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2238                         vmcs_write64(GUEST_IA32_PAT, data);
2239                         vcpu->arch.pat = data;
2240                         break;
2241                 }
2242                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2243                 break;
2244         case MSR_TSC_AUX:
2245                 if (!vmx->rdtscp_enabled)
2246                         return 1;
2247                 /* Check reserved bit, higher 32 bits should be zero */
2248                 if ((data >> 32) != 0)
2249                         return 1;
2250                 /* Otherwise falls through */
2251         default:
2252                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2253                         break;
2254                 msr = find_msr_entry(vmx, msr_index);
2255                 if (msr) {
2256                         msr->data = data;
2257                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2258                                 preempt_disable();
2259                                 kvm_set_shared_msr(msr->index, msr->data,
2260                                                    msr->mask);
2261                                 preempt_enable();
2262                         }
2263                         break;
2264                 }
2265                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2266         }
2267
2268         return ret;
2269 }
2270
2271 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2272 {
2273         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2274         switch (reg) {
2275         case VCPU_REGS_RSP:
2276                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2277                 break;
2278         case VCPU_REGS_RIP:
2279                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2280                 break;
2281         case VCPU_EXREG_PDPTR:
2282                 if (enable_ept)
2283                         ept_save_pdptrs(vcpu);
2284                 break;
2285         default:
2286                 break;
2287         }
2288 }
2289
2290 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2291 {
2292         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2293                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2294         else
2295                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2296
2297         update_exception_bitmap(vcpu);
2298 }
2299
2300 static __init int cpu_has_kvm_support(void)
2301 {
2302         return cpu_has_vmx();
2303 }
2304
2305 static __init int vmx_disabled_by_bios(void)
2306 {
2307         u64 msr;
2308
2309         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2310         if (msr & FEATURE_CONTROL_LOCKED) {
2311                 /* launched w/ TXT and VMX disabled */
2312                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2313                         && tboot_enabled())
2314                         return 1;
2315                 /* launched w/o TXT and VMX only enabled w/ TXT */
2316                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2317                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2318                         && !tboot_enabled()) {
2319                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2320                                 "activate TXT before enabling KVM\n");
2321                         return 1;
2322                 }
2323                 /* launched w/o TXT and VMX disabled */
2324                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2325                         && !tboot_enabled())
2326                         return 1;
2327         }
2328
2329         return 0;
2330 }
2331
2332 static void kvm_cpu_vmxon(u64 addr)
2333 {
2334         asm volatile (ASM_VMX_VMXON_RAX
2335                         : : "a"(&addr), "m"(addr)
2336                         : "memory", "cc");
2337 }
2338
2339 static int hardware_enable(void *garbage)
2340 {
2341         int cpu = raw_smp_processor_id();
2342         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2343         u64 old, test_bits;
2344
2345         if (read_cr4() & X86_CR4_VMXE)
2346                 return -EBUSY;
2347
2348         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2349         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2350
2351         test_bits = FEATURE_CONTROL_LOCKED;
2352         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2353         if (tboot_enabled())
2354                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2355
2356         if ((old & test_bits) != test_bits) {
2357                 /* enable and lock */
2358                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2359         }
2360         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2361
2362         if (vmm_exclusive) {
2363                 kvm_cpu_vmxon(phys_addr);
2364                 ept_sync_global();
2365         }
2366
2367         store_gdt(&__get_cpu_var(host_gdt));
2368
2369         return 0;
2370 }
2371
2372 static void vmclear_local_loaded_vmcss(void)
2373 {
2374         int cpu = raw_smp_processor_id();
2375         struct loaded_vmcs *v, *n;
2376
2377         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2378                                  loaded_vmcss_on_cpu_link)
2379                 __loaded_vmcs_clear(v);
2380 }
2381
2382
2383 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2384  * tricks.
2385  */
2386 static void kvm_cpu_vmxoff(void)
2387 {
2388         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2389 }
2390
2391 static void hardware_disable(void *garbage)
2392 {
2393         if (vmm_exclusive) {
2394                 vmclear_local_loaded_vmcss();
2395                 kvm_cpu_vmxoff();
2396         }
2397         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2398 }
2399
2400 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2401                                       u32 msr, u32 *result)
2402 {
2403         u32 vmx_msr_low, vmx_msr_high;
2404         u32 ctl = ctl_min | ctl_opt;
2405
2406         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2407
2408         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2409         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2410
2411         /* Ensure minimum (required) set of control bits are supported. */
2412         if (ctl_min & ~ctl)
2413                 return -EIO;
2414
2415         *result = ctl;
2416         return 0;
2417 }
2418
2419 static __init bool allow_1_setting(u32 msr, u32 ctl)
2420 {
2421         u32 vmx_msr_low, vmx_msr_high;
2422
2423         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2424         return vmx_msr_high & ctl;
2425 }
2426
2427 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2428 {
2429         u32 vmx_msr_low, vmx_msr_high;
2430         u32 min, opt, min2, opt2;
2431         u32 _pin_based_exec_control = 0;
2432         u32 _cpu_based_exec_control = 0;
2433         u32 _cpu_based_2nd_exec_control = 0;
2434         u32 _vmexit_control = 0;
2435         u32 _vmentry_control = 0;
2436
2437         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2438         opt = PIN_BASED_VIRTUAL_NMIS;
2439         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2440                                 &_pin_based_exec_control) < 0)
2441                 return -EIO;
2442
2443         min = CPU_BASED_HLT_EXITING |
2444 #ifdef CONFIG_X86_64
2445               CPU_BASED_CR8_LOAD_EXITING |
2446               CPU_BASED_CR8_STORE_EXITING |
2447 #endif
2448               CPU_BASED_CR3_LOAD_EXITING |
2449               CPU_BASED_CR3_STORE_EXITING |
2450               CPU_BASED_USE_IO_BITMAPS |
2451               CPU_BASED_MOV_DR_EXITING |
2452               CPU_BASED_USE_TSC_OFFSETING |
2453               CPU_BASED_MWAIT_EXITING |
2454               CPU_BASED_MONITOR_EXITING |
2455               CPU_BASED_INVLPG_EXITING |
2456               CPU_BASED_RDPMC_EXITING;
2457
2458         opt = CPU_BASED_TPR_SHADOW |
2459               CPU_BASED_USE_MSR_BITMAPS |
2460               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2461         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2462                                 &_cpu_based_exec_control) < 0)
2463                 return -EIO;
2464 #ifdef CONFIG_X86_64
2465         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2466                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2467                                            ~CPU_BASED_CR8_STORE_EXITING;
2468 #endif
2469         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2470                 min2 = 0;
2471                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2472                         SECONDARY_EXEC_WBINVD_EXITING |
2473                         SECONDARY_EXEC_ENABLE_VPID |
2474                         SECONDARY_EXEC_ENABLE_EPT |
2475                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2476                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2477                         SECONDARY_EXEC_RDTSCP |
2478                         SECONDARY_EXEC_ENABLE_INVPCID;
2479                 if (adjust_vmx_controls(min2, opt2,
2480                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2481                                         &_cpu_based_2nd_exec_control) < 0)
2482                         return -EIO;
2483         }
2484 #ifndef CONFIG_X86_64
2485         if (!(_cpu_based_2nd_exec_control &
2486                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2487                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2488 #endif
2489         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2490                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2491                    enabled */
2492                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2493                                              CPU_BASED_CR3_STORE_EXITING |
2494                                              CPU_BASED_INVLPG_EXITING);
2495                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2496                       vmx_capability.ept, vmx_capability.vpid);
2497         }
2498
2499         min = 0;
2500 #ifdef CONFIG_X86_64
2501         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2502 #endif
2503         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2504         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2505                                 &_vmexit_control) < 0)
2506                 return -EIO;
2507
2508         min = 0;
2509         opt = VM_ENTRY_LOAD_IA32_PAT;
2510         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2511                                 &_vmentry_control) < 0)
2512                 return -EIO;
2513
2514         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2515
2516         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2517         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2518                 return -EIO;
2519
2520 #ifdef CONFIG_X86_64
2521         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2522         if (vmx_msr_high & (1u<<16))
2523                 return -EIO;
2524 #endif
2525
2526         /* Require Write-Back (WB) memory type for VMCS accesses. */
2527         if (((vmx_msr_high >> 18) & 15) != 6)
2528                 return -EIO;
2529
2530         vmcs_conf->size = vmx_msr_high & 0x1fff;
2531         vmcs_conf->order = get_order(vmcs_config.size);
2532         vmcs_conf->revision_id = vmx_msr_low;
2533
2534         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2535         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2536         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2537         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2538         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2539
2540         cpu_has_load_ia32_efer =
2541                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2542                                 VM_ENTRY_LOAD_IA32_EFER)
2543                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2544                                    VM_EXIT_LOAD_IA32_EFER);
2545
2546         cpu_has_load_perf_global_ctrl =
2547                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2548                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2549                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2550                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2551
2552         /*
2553          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2554          * but due to arrata below it can't be used. Workaround is to use
2555          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2556          *
2557          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2558          *
2559          * AAK155             (model 26)
2560          * AAP115             (model 30)
2561          * AAT100             (model 37)
2562          * BC86,AAY89,BD102   (model 44)
2563          * BA97               (model 46)
2564          *
2565          */
2566         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2567                 switch (boot_cpu_data.x86_model) {
2568                 case 26:
2569                 case 30:
2570                 case 37:
2571                 case 44:
2572                 case 46:
2573                         cpu_has_load_perf_global_ctrl = false;
2574                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2575                                         "does not work properly. Using workaround\n");
2576                         break;
2577                 default:
2578                         break;
2579                 }
2580         }
2581
2582         return 0;
2583 }
2584
2585 static struct vmcs *alloc_vmcs_cpu(int cpu)
2586 {
2587         int node = cpu_to_node(cpu);
2588         struct page *pages;
2589         struct vmcs *vmcs;
2590
2591         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2592         if (!pages)
2593                 return NULL;
2594         vmcs = page_address(pages);
2595         memset(vmcs, 0, vmcs_config.size);
2596         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2597         return vmcs;
2598 }
2599
2600 static struct vmcs *alloc_vmcs(void)
2601 {
2602         return alloc_vmcs_cpu(raw_smp_processor_id());
2603 }
2604
2605 static void free_vmcs(struct vmcs *vmcs)
2606 {
2607         free_pages((unsigned long)vmcs, vmcs_config.order);
2608 }
2609
2610 /*
2611  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2612  */
2613 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2614 {
2615         if (!loaded_vmcs->vmcs)
2616                 return;
2617         loaded_vmcs_clear(loaded_vmcs);
2618         free_vmcs(loaded_vmcs->vmcs);
2619         loaded_vmcs->vmcs = NULL;
2620 }
2621
2622 static void free_kvm_area(void)
2623 {
2624         int cpu;
2625
2626         for_each_possible_cpu(cpu) {
2627                 free_vmcs(per_cpu(vmxarea, cpu));
2628                 per_cpu(vmxarea, cpu) = NULL;
2629         }
2630 }
2631
2632 static __init int alloc_kvm_area(void)
2633 {
2634         int cpu;
2635
2636         for_each_possible_cpu(cpu) {
2637                 struct vmcs *vmcs;
2638
2639                 vmcs = alloc_vmcs_cpu(cpu);
2640                 if (!vmcs) {
2641                         free_kvm_area();
2642                         return -ENOMEM;
2643                 }
2644
2645                 per_cpu(vmxarea, cpu) = vmcs;
2646         }
2647         return 0;
2648 }
2649
2650 static __init int hardware_setup(void)
2651 {
2652         if (setup_vmcs_config(&vmcs_config) < 0)
2653                 return -EIO;
2654
2655         if (boot_cpu_has(X86_FEATURE_NX))
2656                 kvm_enable_efer_bits(EFER_NX);
2657
2658         if (!cpu_has_vmx_vpid())
2659                 enable_vpid = 0;
2660
2661         if (!cpu_has_vmx_ept() ||
2662             !cpu_has_vmx_ept_4levels()) {
2663                 enable_ept = 0;
2664                 enable_unrestricted_guest = 0;
2665                 enable_ept_ad_bits = 0;
2666         }
2667
2668         if (!cpu_has_vmx_ept_ad_bits())
2669                 enable_ept_ad_bits = 0;
2670
2671         if (!cpu_has_vmx_unrestricted_guest())
2672                 enable_unrestricted_guest = 0;
2673
2674         if (!cpu_has_vmx_flexpriority())
2675                 flexpriority_enabled = 0;
2676
2677         if (!cpu_has_vmx_tpr_shadow())
2678                 kvm_x86_ops->update_cr8_intercept = NULL;
2679
2680         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2681                 kvm_disable_largepages();
2682
2683         if (!cpu_has_vmx_ple())
2684                 ple_gap = 0;
2685
2686         if (nested)
2687                 nested_vmx_setup_ctls_msrs();
2688
2689         return alloc_kvm_area();
2690 }
2691
2692 static __exit void hardware_unsetup(void)
2693 {
2694         free_kvm_area();
2695 }
2696
2697 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2698 {
2699         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2700
2701         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2702                 vmcs_write16(sf->selector, save->selector);
2703                 vmcs_writel(sf->base, save->base);
2704                 vmcs_write32(sf->limit, save->limit);
2705                 vmcs_write32(sf->ar_bytes, save->ar);
2706         } else {
2707                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2708                         << AR_DPL_SHIFT;
2709                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2710         }
2711 }
2712
2713 static void enter_pmode(struct kvm_vcpu *vcpu)
2714 {
2715         unsigned long flags;
2716         struct vcpu_vmx *vmx = to_vmx(vcpu);
2717
2718         vmx->emulation_required = 1;
2719         vmx->rmode.vm86_active = 0;
2720
2721         vmx_segment_cache_clear(vmx);
2722
2723         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2724         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2725         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2726         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2727
2728         flags = vmcs_readl(GUEST_RFLAGS);
2729         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2730         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2731         vmcs_writel(GUEST_RFLAGS, flags);
2732
2733         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2734                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2735
2736         update_exception_bitmap(vcpu);
2737
2738         if (emulate_invalid_guest_state)
2739                 return;
2740
2741         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2742         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2743         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2744         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2745
2746         vmx_segment_cache_clear(vmx);
2747
2748         vmcs_write16(GUEST_SS_SELECTOR, 0);
2749         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2750
2751         vmcs_write16(GUEST_CS_SELECTOR,
2752                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2753         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2754 }
2755
2756 static gva_t rmode_tss_base(struct kvm *kvm)
2757 {
2758         if (!kvm->arch.tss_addr) {
2759                 struct kvm_memslots *slots;
2760                 struct kvm_memory_slot *slot;
2761                 gfn_t base_gfn;
2762
2763                 slots = kvm_memslots(kvm);
2764                 slot = id_to_memslot(slots, 0);
2765                 base_gfn = slot->base_gfn + slot->npages - 3;
2766
2767                 return base_gfn << PAGE_SHIFT;
2768         }
2769         return kvm->arch.tss_addr;
2770 }
2771
2772 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2773 {
2774         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2775
2776         save->selector = vmcs_read16(sf->selector);
2777         save->base = vmcs_readl(sf->base);
2778         save->limit = vmcs_read32(sf->limit);
2779         save->ar = vmcs_read32(sf->ar_bytes);
2780         vmcs_write16(sf->selector, save->base >> 4);
2781         vmcs_write32(sf->base, save->base & 0xffff0);
2782         vmcs_write32(sf->limit, 0xffff);
2783         vmcs_write32(sf->ar_bytes, 0xf3);
2784         if (save->base & 0xf)
2785                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2786                             " aligned when entering protected mode (seg=%d)",
2787                             seg);
2788 }
2789
2790 static void enter_rmode(struct kvm_vcpu *vcpu)
2791 {
2792         unsigned long flags;
2793         struct vcpu_vmx *vmx = to_vmx(vcpu);
2794         struct kvm_segment var;
2795
2796         if (enable_unrestricted_guest)
2797                 return;
2798
2799         vmx->emulation_required = 1;
2800         vmx->rmode.vm86_active = 1;
2801
2802         /*
2803          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2804          * vcpu. Call it here with phys address pointing 16M below 4G.
2805          */
2806         if (!vcpu->kvm->arch.tss_addr) {
2807                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2808                              "called before entering vcpu\n");
2809                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2810                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2811                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2812         }
2813
2814         vmx_segment_cache_clear(vmx);
2815
2816         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2817         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2818         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2819
2820         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2821         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2822
2823         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2824         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2825
2826         flags = vmcs_readl(GUEST_RFLAGS);
2827         vmx->rmode.save_rflags = flags;
2828
2829         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2830
2831         vmcs_writel(GUEST_RFLAGS, flags);
2832         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2833         update_exception_bitmap(vcpu);
2834
2835         if (emulate_invalid_guest_state)
2836                 goto continue_rmode;
2837
2838         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2839         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2840
2841         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2842         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2843
2844         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2845         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2846
2847         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2848         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2849
2850         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2851         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2852
2853         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2854         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2855
2856 continue_rmode:
2857         kvm_mmu_reset_context(vcpu);
2858 }
2859
2860 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2861 {
2862         struct vcpu_vmx *vmx = to_vmx(vcpu);
2863         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2864
2865         if (!msr)
2866                 return;
2867
2868         /*
2869          * Force kernel_gs_base reloading before EFER changes, as control
2870          * of this msr depends on is_long_mode().
2871          */
2872         vmx_load_host_state(to_vmx(vcpu));
2873         vcpu->arch.efer = efer;
2874         if (efer & EFER_LMA) {
2875                 vmcs_write32(VM_ENTRY_CONTROLS,
2876                              vmcs_read32(VM_ENTRY_CONTROLS) |
2877                              VM_ENTRY_IA32E_MODE);
2878                 msr->data = efer;
2879         } else {
2880                 vmcs_write32(VM_ENTRY_CONTROLS,
2881                              vmcs_read32(VM_ENTRY_CONTROLS) &
2882                              ~VM_ENTRY_IA32E_MODE);
2883
2884                 msr->data = efer & ~EFER_LME;
2885         }
2886         setup_msrs(vmx);
2887 }
2888
2889 #ifdef CONFIG_X86_64
2890
2891 static void enter_lmode(struct kvm_vcpu *vcpu)
2892 {
2893         u32 guest_tr_ar;
2894
2895         vmx_segment_cache_clear(to_vmx(vcpu));
2896
2897         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2898         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2899                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2900                                      __func__);
2901                 vmcs_write32(GUEST_TR_AR_BYTES,
2902                              (guest_tr_ar & ~AR_TYPE_MASK)
2903                              | AR_TYPE_BUSY_64_TSS);
2904         }
2905         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2906 }
2907
2908 static void exit_lmode(struct kvm_vcpu *vcpu)
2909 {
2910         vmcs_write32(VM_ENTRY_CONTROLS,
2911                      vmcs_read32(VM_ENTRY_CONTROLS)
2912                      & ~VM_ENTRY_IA32E_MODE);
2913         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2914 }
2915
2916 #endif
2917
2918 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2919 {
2920         vpid_sync_context(to_vmx(vcpu));
2921         if (enable_ept) {
2922                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2923                         return;
2924                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2925         }
2926 }
2927
2928 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2929 {
2930         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2931
2932         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2933         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2934 }
2935
2936 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2937 {
2938         if (enable_ept && is_paging(vcpu))
2939                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2940         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2941 }
2942
2943 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2944 {
2945         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2946
2947         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2948         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2949 }
2950
2951 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2952 {
2953         if (!test_bit(VCPU_EXREG_PDPTR,
2954                       (unsigned long *)&vcpu->arch.regs_dirty))
2955                 return;
2956
2957         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2958                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2959                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2960                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2961                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2962         }
2963 }
2964
2965 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2966 {
2967         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2968                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2969                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2970                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2971                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2972         }
2973
2974         __set_bit(VCPU_EXREG_PDPTR,
2975                   (unsigned long *)&vcpu->arch.regs_avail);
2976         __set_bit(VCPU_EXREG_PDPTR,
2977                   (unsigned long *)&vcpu->arch.regs_dirty);
2978 }
2979
2980 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2981
2982 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2983                                         unsigned long cr0,
2984                                         struct kvm_vcpu *vcpu)
2985 {
2986         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2987                 vmx_decache_cr3(vcpu);
2988         if (!(cr0 & X86_CR0_PG)) {
2989                 /* From paging/starting to nonpaging */
2990                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2991                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2992                              (CPU_BASED_CR3_LOAD_EXITING |
2993                               CPU_BASED_CR3_STORE_EXITING));
2994                 vcpu->arch.cr0 = cr0;
2995                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2996         } else if (!is_paging(vcpu)) {
2997                 /* From nonpaging to paging */
2998                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2999                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3000                              ~(CPU_BASED_CR3_LOAD_EXITING |
3001                                CPU_BASED_CR3_STORE_EXITING));
3002                 vcpu->arch.cr0 = cr0;
3003                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3004         }
3005
3006         if (!(cr0 & X86_CR0_WP))
3007                 *hw_cr0 &= ~X86_CR0_WP;
3008 }
3009
3010 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3011 {
3012         struct vcpu_vmx *vmx = to_vmx(vcpu);
3013         unsigned long hw_cr0;
3014
3015         if (enable_unrestricted_guest)
3016                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3017                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3018         else
3019                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3020
3021         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3022                 enter_pmode(vcpu);
3023
3024         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3025                 enter_rmode(vcpu);
3026
3027 #ifdef CONFIG_X86_64
3028         if (vcpu->arch.efer & EFER_LME) {
3029                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3030                         enter_lmode(vcpu);
3031                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3032                         exit_lmode(vcpu);
3033         }
3034 #endif
3035
3036         if (enable_ept)
3037                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3038
3039         if (!vcpu->fpu_active)
3040                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3041
3042         vmcs_writel(CR0_READ_SHADOW, cr0);
3043         vmcs_writel(GUEST_CR0, hw_cr0);
3044         vcpu->arch.cr0 = cr0;
3045         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3046 }
3047
3048 static u64 construct_eptp(unsigned long root_hpa)
3049 {
3050         u64 eptp;
3051
3052         /* TODO write the value reading from MSR */
3053         eptp = VMX_EPT_DEFAULT_MT |
3054                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3055         if (enable_ept_ad_bits)
3056                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3057         eptp |= (root_hpa & PAGE_MASK);
3058
3059         return eptp;
3060 }
3061
3062 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3063 {
3064         unsigned long guest_cr3;
3065         u64 eptp;
3066
3067         guest_cr3 = cr3;
3068         if (enable_ept) {
3069                 eptp = construct_eptp(cr3);
3070                 vmcs_write64(EPT_POINTER, eptp);
3071                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3072                         vcpu->kvm->arch.ept_identity_map_addr;
3073                 ept_load_pdptrs(vcpu);
3074         }
3075
3076         vmx_flush_tlb(vcpu);
3077         vmcs_writel(GUEST_CR3, guest_cr3);
3078 }
3079
3080 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3081 {
3082         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3083                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3084
3085         if (cr4 & X86_CR4_VMXE) {
3086                 /*
3087                  * To use VMXON (and later other VMX instructions), a guest
3088                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3089                  * So basically the check on whether to allow nested VMX
3090                  * is here.
3091                  */
3092                 if (!nested_vmx_allowed(vcpu))
3093                         return 1;
3094         } else if (to_vmx(vcpu)->nested.vmxon)
3095                 return 1;
3096
3097         vcpu->arch.cr4 = cr4;
3098         if (enable_ept) {
3099                 if (!is_paging(vcpu)) {
3100                         hw_cr4 &= ~X86_CR4_PAE;
3101                         hw_cr4 |= X86_CR4_PSE;
3102                 } else if (!(cr4 & X86_CR4_PAE)) {
3103                         hw_cr4 &= ~X86_CR4_PAE;
3104                 }
3105         }
3106
3107         vmcs_writel(CR4_READ_SHADOW, cr4);
3108         vmcs_writel(GUEST_CR4, hw_cr4);
3109         return 0;
3110 }
3111
3112 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3113                             struct kvm_segment *var, int seg)
3114 {
3115         struct vcpu_vmx *vmx = to_vmx(vcpu);
3116         struct kvm_save_segment *save;
3117         u32 ar;
3118
3119         if (vmx->rmode.vm86_active
3120             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3121                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3122                 || seg == VCPU_SREG_GS)
3123             && !emulate_invalid_guest_state) {
3124                 switch (seg) {
3125                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3126                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3127                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3128                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3129                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3130                 default: BUG();
3131                 }
3132                 var->selector = save->selector;
3133                 var->base = save->base;
3134                 var->limit = save->limit;
3135                 ar = save->ar;
3136                 if (seg == VCPU_SREG_TR
3137                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3138                         goto use_saved_rmode_seg;
3139         }
3140         var->base = vmx_read_guest_seg_base(vmx, seg);
3141         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3142         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3143         ar = vmx_read_guest_seg_ar(vmx, seg);
3144 use_saved_rmode_seg:
3145         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3146                 ar = 0;
3147         var->type = ar & 15;
3148         var->s = (ar >> 4) & 1;
3149         var->dpl = (ar >> 5) & 3;
3150         var->present = (ar >> 7) & 1;
3151         var->avl = (ar >> 12) & 1;
3152         var->l = (ar >> 13) & 1;
3153         var->db = (ar >> 14) & 1;
3154         var->g = (ar >> 15) & 1;
3155         var->unusable = (ar >> 16) & 1;
3156 }
3157
3158 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3159 {
3160         struct kvm_segment s;
3161
3162         if (to_vmx(vcpu)->rmode.vm86_active) {
3163                 vmx_get_segment(vcpu, &s, seg);
3164                 return s.base;
3165         }
3166         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3167 }
3168
3169 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3170 {
3171         if (!is_protmode(vcpu))
3172                 return 0;
3173
3174         if (!is_long_mode(vcpu)
3175             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3176                 return 3;
3177
3178         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3179 }
3180
3181 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3182 {
3183         struct vcpu_vmx *vmx = to_vmx(vcpu);
3184
3185         /*
3186          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3187          * fail; use the cache instead.
3188          */
3189         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3190                 return vmx->cpl;
3191         }
3192
3193         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3194                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3195                 vmx->cpl = __vmx_get_cpl(vcpu);
3196         }
3197
3198         return vmx->cpl;
3199 }
3200
3201
3202 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3203 {
3204         u32 ar;
3205
3206         if (var->unusable || !var->present)
3207                 ar = 1 << 16;
3208         else {
3209                 ar = var->type & 15;
3210                 ar |= (var->s & 1) << 4;
3211                 ar |= (var->dpl & 3) << 5;
3212                 ar |= (var->present & 1) << 7;
3213                 ar |= (var->avl & 1) << 12;
3214                 ar |= (var->l & 1) << 13;
3215                 ar |= (var->db & 1) << 14;
3216                 ar |= (var->g & 1) << 15;
3217         }
3218
3219         return ar;
3220 }
3221
3222 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3223                             struct kvm_segment *var, int seg)
3224 {
3225         struct vcpu_vmx *vmx = to_vmx(vcpu);
3226         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3227         u32 ar;
3228
3229         vmx_segment_cache_clear(vmx);
3230
3231         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3232                 vmcs_write16(sf->selector, var->selector);
3233                 vmx->rmode.tr.selector = var->selector;
3234                 vmx->rmode.tr.base = var->base;
3235                 vmx->rmode.tr.limit = var->limit;
3236                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3237                 return;
3238         }
3239         vmcs_writel(sf->base, var->base);
3240         vmcs_write32(sf->limit, var->limit);
3241         vmcs_write16(sf->selector, var->selector);
3242         if (vmx->rmode.vm86_active && var->s) {
3243                 /*
3244                  * Hack real-mode segments into vm86 compatibility.
3245                  */
3246                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3247                         vmcs_writel(sf->base, 0xf0000);
3248                 ar = 0xf3;
3249         } else
3250                 ar = vmx_segment_access_rights(var);
3251
3252         /*
3253          *   Fix the "Accessed" bit in AR field of segment registers for older
3254          * qemu binaries.
3255          *   IA32 arch specifies that at the time of processor reset the
3256          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3257          * is setting it to 0 in the userland code. This causes invalid guest
3258          * state vmexit when "unrestricted guest" mode is turned on.
3259          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3260          * tree. Newer qemu binaries with that qemu fix would not need this
3261          * kvm hack.
3262          */
3263         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3264                 ar |= 0x1; /* Accessed */
3265
3266         vmcs_write32(sf->ar_bytes, ar);
3267         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3268
3269         /*
3270          * Fix segments for real mode guest in hosts that don't have
3271          * "unrestricted_mode" or it was disabled.
3272          * This is done to allow migration of the guests from hosts with
3273          * unrestricted guest like Westmere to older host that don't have
3274          * unrestricted guest like Nehelem.
3275          */
3276         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3277                 switch (seg) {
3278                 case VCPU_SREG_CS:
3279                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3280                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3281                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3282                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3283                         vmcs_write16(GUEST_CS_SELECTOR,
3284                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3285                         break;
3286                 case VCPU_SREG_ES:
3287                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3288                         break;
3289                 case VCPU_SREG_DS:
3290                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3291                         break;
3292                 case VCPU_SREG_GS:
3293                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3294                         break;
3295                 case VCPU_SREG_FS:
3296                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3297                         break;
3298                 case VCPU_SREG_SS:
3299                         vmcs_write16(GUEST_SS_SELECTOR,
3300                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3301                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3302                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3303                         break;
3304                 }
3305         }
3306 }
3307
3308 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3309 {
3310         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3311
3312         *db = (ar >> 14) & 1;
3313         *l = (ar >> 13) & 1;
3314 }
3315
3316 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3317 {
3318         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3319         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3320 }
3321
3322 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3323 {
3324         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3325         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3326 }
3327
3328 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3329 {
3330         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3331         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3332 }
3333
3334 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3335 {
3336         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3337         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3338 }
3339
3340 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3341 {
3342         struct kvm_segment var;
3343         u32 ar;
3344
3345         vmx_get_segment(vcpu, &var, seg);
3346         ar = vmx_segment_access_rights(&var);
3347
3348         if (var.base != (var.selector << 4))
3349                 return false;
3350         if (var.limit != 0xffff)
3351                 return false;
3352         if (ar != 0xf3)
3353                 return false;
3354
3355         return true;
3356 }
3357
3358 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3359 {
3360         struct kvm_segment cs;
3361         unsigned int cs_rpl;
3362
3363         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3364         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3365
3366         if (cs.unusable)
3367                 return false;
3368         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3369                 return false;
3370         if (!cs.s)
3371                 return false;
3372         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3373                 if (cs.dpl > cs_rpl)
3374                         return false;
3375         } else {
3376                 if (cs.dpl != cs_rpl)
3377                         return false;
3378         }
3379         if (!cs.present)
3380                 return false;
3381
3382         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3383         return true;
3384 }
3385
3386 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3387 {
3388         struct kvm_segment ss;
3389         unsigned int ss_rpl;
3390
3391         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3392         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3393
3394         if (ss.unusable)
3395                 return true;
3396         if (ss.type != 3 && ss.type != 7)
3397                 return false;
3398         if (!ss.s)
3399                 return false;
3400         if (ss.dpl != ss_rpl) /* DPL != RPL */
3401                 return false;
3402         if (!ss.present)
3403                 return false;
3404
3405         return true;
3406 }
3407
3408 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3409 {
3410         struct kvm_segment var;
3411         unsigned int rpl;
3412
3413         vmx_get_segment(vcpu, &var, seg);
3414         rpl = var.selector & SELECTOR_RPL_MASK;
3415
3416         if (var.unusable)
3417                 return true;
3418         if (!var.s)
3419                 return false;
3420         if (!var.present)
3421                 return false;
3422         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3423                 if (var.dpl < rpl) /* DPL < RPL */
3424                         return false;
3425         }
3426
3427         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3428          * rights flags
3429          */
3430         return true;
3431 }
3432
3433 static bool tr_valid(struct kvm_vcpu *vcpu)
3434 {
3435         struct kvm_segment tr;
3436
3437         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3438
3439         if (tr.unusable)
3440                 return false;
3441         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3442                 return false;
3443         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3444                 return false;
3445         if (!tr.present)
3446                 return false;
3447
3448         return true;
3449 }
3450
3451 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3452 {
3453         struct kvm_segment ldtr;
3454
3455         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3456
3457         if (ldtr.unusable)
3458                 return true;
3459         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3460                 return false;
3461         if (ldtr.type != 2)
3462                 return false;
3463         if (!ldtr.present)
3464                 return false;
3465
3466         return true;
3467 }
3468
3469 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3470 {
3471         struct kvm_segment cs, ss;
3472
3473         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3474         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3475
3476         return ((cs.selector & SELECTOR_RPL_MASK) ==
3477                  (ss.selector & SELECTOR_RPL_MASK));
3478 }
3479
3480 /*
3481  * Check if guest state is valid. Returns true if valid, false if
3482  * not.
3483  * We assume that registers are always usable
3484  */
3485 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3486 {
3487         /* real mode guest state checks */
3488         if (!is_protmode(vcpu)) {
3489                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3490                         return false;
3491                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3492                         return false;
3493                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3494                         return false;
3495                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3496                         return false;
3497                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3498                         return false;
3499                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3500                         return false;
3501         } else {
3502         /* protected mode guest state checks */
3503                 if (!cs_ss_rpl_check(vcpu))
3504                         return false;
3505                 if (!code_segment_valid(vcpu))
3506                         return false;
3507                 if (!stack_segment_valid(vcpu))
3508                         return false;
3509                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3510                         return false;
3511                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3512                         return false;
3513                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3514                         return false;
3515                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3516                         return false;
3517                 if (!tr_valid(vcpu))
3518                         return false;
3519                 if (!ldtr_valid(vcpu))
3520                         return false;
3521         }
3522         /* TODO:
3523          * - Add checks on RIP
3524          * - Add checks on RFLAGS
3525          */
3526
3527         return true;
3528 }
3529
3530 static int init_rmode_tss(struct kvm *kvm)
3531 {
3532         gfn_t fn;
3533         u16 data = 0;
3534         int r, idx, ret = 0;
3535
3536         idx = srcu_read_lock(&kvm->srcu);
3537         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3538         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3539         if (r < 0)
3540                 goto out;
3541         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3542         r = kvm_write_guest_page(kvm, fn++, &data,
3543                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3544         if (r < 0)
3545                 goto out;
3546         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3547         if (r < 0)
3548                 goto out;
3549         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3550         if (r < 0)
3551                 goto out;
3552         data = ~0;
3553         r = kvm_write_guest_page(kvm, fn, &data,
3554                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3555                                  sizeof(u8));
3556         if (r < 0)
3557                 goto out;
3558
3559         ret = 1;
3560 out:
3561         srcu_read_unlock(&kvm->srcu, idx);
3562         return ret;
3563 }
3564
3565 static int init_rmode_identity_map(struct kvm *kvm)
3566 {
3567         int i, idx, r, ret;
3568         pfn_t identity_map_pfn;
3569         u32 tmp;
3570
3571         if (!enable_ept)
3572                 return 1;
3573         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3574                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3575                         "haven't been allocated!\n");
3576                 return 0;
3577         }
3578         if (likely(kvm->arch.ept_identity_pagetable_done))
3579                 return 1;
3580         ret = 0;
3581         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3582         idx = srcu_read_lock(&kvm->srcu);
3583         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3584         if (r < 0)
3585                 goto out;
3586         /* Set up identity-mapping pagetable for EPT in real mode */
3587         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3588                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3589                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3590                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3591                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3592                 if (r < 0)
3593                         goto out;
3594         }
3595         kvm->arch.ept_identity_pagetable_done = true;
3596         ret = 1;
3597 out:
3598         srcu_read_unlock(&kvm->srcu, idx);
3599         return ret;
3600 }
3601
3602 static void seg_setup(int seg)
3603 {
3604         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3605         unsigned int ar;
3606
3607         vmcs_write16(sf->selector, 0);
3608         vmcs_writel(sf->base, 0);
3609         vmcs_write32(sf->limit, 0xffff);
3610         if (enable_unrestricted_guest) {
3611                 ar = 0x93;
3612                 if (seg == VCPU_SREG_CS)
3613                         ar |= 0x08; /* code segment */
3614         } else
3615                 ar = 0xf3;
3616
3617         vmcs_write32(sf->ar_bytes, ar);
3618 }
3619
3620 static int alloc_apic_access_page(struct kvm *kvm)
3621 {
3622         struct kvm_userspace_memory_region kvm_userspace_mem;
3623         int r = 0;
3624
3625         mutex_lock(&kvm->slots_lock);
3626         if (kvm->arch.apic_access_page)
3627                 goto out;
3628         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3629         kvm_userspace_mem.flags = 0;
3630         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3631         kvm_userspace_mem.memory_size = PAGE_SIZE;
3632         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3633         if (r)
3634                 goto out;
3635
3636         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3637 out:
3638         mutex_unlock(&kvm->slots_lock);
3639         return r;
3640 }
3641
3642 static int alloc_identity_pagetable(struct kvm *kvm)
3643 {
3644         struct kvm_userspace_memory_region kvm_userspace_mem;
3645         int r = 0;
3646
3647         mutex_lock(&kvm->slots_lock);
3648         if (kvm->arch.ept_identity_pagetable)
3649                 goto out;
3650         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3651         kvm_userspace_mem.flags = 0;
3652         kvm_userspace_mem.guest_phys_addr =
3653                 kvm->arch.ept_identity_map_addr;
3654         kvm_userspace_mem.memory_size = PAGE_SIZE;
3655         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3656         if (r)
3657                 goto out;
3658
3659         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3660                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3661 out:
3662         mutex_unlock(&kvm->slots_lock);
3663         return r;
3664 }
3665
3666 static void allocate_vpid(struct vcpu_vmx *vmx)
3667 {
3668         int vpid;
3669
3670         vmx->vpid = 0;
3671         if (!enable_vpid)
3672                 return;
3673         spin_lock(&vmx_vpid_lock);
3674         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3675         if (vpid < VMX_NR_VPIDS) {
3676                 vmx->vpid = vpid;
3677                 __set_bit(vpid, vmx_vpid_bitmap);
3678         }
3679         spin_unlock(&vmx_vpid_lock);
3680 }
3681
3682 static void free_vpid(struct vcpu_vmx *vmx)
3683 {
3684         if (!enable_vpid)
3685                 return;
3686         spin_lock(&vmx_vpid_lock);
3687         if (vmx->vpid != 0)
3688                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3689         spin_unlock(&vmx_vpid_lock);
3690 }
3691
3692 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3693 {
3694         int f = sizeof(unsigned long);
3695
3696         if (!cpu_has_vmx_msr_bitmap())
3697                 return;
3698
3699         /*
3700          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3701          * have the write-low and read-high bitmap offsets the wrong way round.
3702          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3703          */
3704         if (msr <= 0x1fff) {
3705                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3706                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3707         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3708                 msr &= 0x1fff;
3709                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3710                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3711         }
3712 }
3713
3714 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3715 {
3716         if (!longmode_only)
3717                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3718         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3719 }
3720
3721 /*
3722  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3723  * will not change in the lifetime of the guest.
3724  * Note that host-state that does change is set elsewhere. E.g., host-state
3725  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3726  */
3727 static void vmx_set_constant_host_state(void)
3728 {
3729         u32 low32, high32;
3730         unsigned long tmpl;
3731         struct desc_ptr dt;
3732
3733         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3734         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3735         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3736
3737         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3738 #ifdef CONFIG_X86_64
3739         /*
3740          * Load null selectors, so we can avoid reloading them in
3741          * __vmx_load_host_state(), in case userspace uses the null selectors
3742          * too (the expected case).
3743          */
3744         vmcs_write16(HOST_DS_SELECTOR, 0);
3745         vmcs_write16(HOST_ES_SELECTOR, 0);
3746 #else
3747         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3748         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3749 #endif
3750         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3751         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3752
3753         native_store_idt(&dt);
3754         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3755
3756         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3757         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3758
3759         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3760         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3761         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3762         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3763
3764         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3765                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3766                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3767         }
3768 }
3769
3770 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3771 {
3772         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3773         if (enable_ept)
3774                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3775         if (is_guest_mode(&vmx->vcpu))
3776                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3777                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3778         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3779 }
3780
3781 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3782 {
3783         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3784         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3785                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3786 #ifdef CONFIG_X86_64
3787                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3788                                 CPU_BASED_CR8_LOAD_EXITING;
3789 #endif
3790         }
3791         if (!enable_ept)
3792                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3793                                 CPU_BASED_CR3_LOAD_EXITING  |
3794                                 CPU_BASED_INVLPG_EXITING;
3795         return exec_control;
3796 }
3797
3798 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3799 {
3800         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3801         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3802                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3803         if (vmx->vpid == 0)
3804                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3805         if (!enable_ept) {
3806                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3807                 enable_unrestricted_guest = 0;
3808                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3809                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3810         }
3811         if (!enable_unrestricted_guest)
3812                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3813         if (!ple_gap)
3814                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3815         return exec_control;
3816 }
3817
3818 static void ept_set_mmio_spte_mask(void)
3819 {
3820         /*
3821          * EPT Misconfigurations can be generated if the value of bits 2:0
3822          * of an EPT paging-structure entry is 110b (write/execute).
3823          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3824          * spte.
3825          */
3826         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3827 }
3828
3829 /*
3830  * Sets up the vmcs for emulated real mode.
3831  */
3832 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3833 {
3834 #ifdef CONFIG_X86_64
3835         unsigned long a;
3836 #endif
3837         int i;
3838
3839         /* I/O */
3840         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3841         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3842
3843         if (cpu_has_vmx_msr_bitmap())
3844                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3845
3846         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3847
3848         /* Control */
3849         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3850                 vmcs_config.pin_based_exec_ctrl);
3851
3852         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3853
3854         if (cpu_has_secondary_exec_ctrls()) {
3855                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3856                                 vmx_secondary_exec_control(vmx));
3857         }
3858
3859         if (ple_gap) {
3860                 vmcs_write32(PLE_GAP, ple_gap);
3861                 vmcs_write32(PLE_WINDOW, ple_window);
3862         }
3863
3864         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3865         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3866         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3867
3868         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3869         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3870         vmx_set_constant_host_state();
3871 #ifdef CONFIG_X86_64
3872         rdmsrl(MSR_FS_BASE, a);
3873         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3874         rdmsrl(MSR_GS_BASE, a);
3875         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3876 #else
3877         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3878         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3879 #endif
3880
3881         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3882         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3883         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3884         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3885         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3886
3887         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3888                 u32 msr_low, msr_high;
3889                 u64 host_pat;
3890                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3891                 host_pat = msr_low | ((u64) msr_high << 32);
3892                 /* Write the default value follow host pat */
3893                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3894                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3895                 vmx->vcpu.arch.pat = host_pat;
3896         }
3897
3898         for (i = 0; i < NR_VMX_MSR; ++i) {
3899                 u32 index = vmx_msr_index[i];
3900                 u32 data_low, data_high;
3901                 int j = vmx->nmsrs;
3902
3903                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3904                         continue;
3905                 if (wrmsr_safe(index, data_low, data_high) < 0)
3906                         continue;
3907                 vmx->guest_msrs[j].index = i;
3908                 vmx->guest_msrs[j].data = 0;
3909                 vmx->guest_msrs[j].mask = -1ull;
3910                 ++vmx->nmsrs;
3911         }
3912
3913         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3914
3915         /* 22.2.1, 20.8.1 */
3916         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3917
3918         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3919         set_cr4_guest_host_mask(vmx);
3920
3921         kvm_write_tsc(&vmx->vcpu, 0);
3922
3923         return 0;
3924 }
3925
3926 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3927 {
3928         struct vcpu_vmx *vmx = to_vmx(vcpu);
3929         u64 msr;
3930         int ret;
3931
3932         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3933
3934         vmx->rmode.vm86_active = 0;
3935
3936         vmx->soft_vnmi_blocked = 0;
3937
3938         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3939         kvm_set_cr8(&vmx->vcpu, 0);
3940         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3941         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3942                 msr |= MSR_IA32_APICBASE_BSP;
3943         kvm_set_apic_base(&vmx->vcpu, msr);
3944
3945         ret = fx_init(&vmx->vcpu);
3946         if (ret != 0)
3947                 goto out;
3948
3949         vmx_segment_cache_clear(vmx);
3950
3951         seg_setup(VCPU_SREG_CS);
3952         /*
3953          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3954          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3955          */
3956         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3957                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3958                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3959         } else {
3960                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3961                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3962         }
3963
3964         seg_setup(VCPU_SREG_DS);
3965         seg_setup(VCPU_SREG_ES);
3966         seg_setup(VCPU_SREG_FS);
3967         seg_setup(VCPU_SREG_GS);
3968         seg_setup(VCPU_SREG_SS);
3969
3970         vmcs_write16(GUEST_TR_SELECTOR, 0);
3971         vmcs_writel(GUEST_TR_BASE, 0);
3972         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3973         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3974
3975         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3976         vmcs_writel(GUEST_LDTR_BASE, 0);
3977         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3978         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3979
3980         vmcs_write32(GUEST_SYSENTER_CS, 0);
3981         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3982         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3983
3984         vmcs_writel(GUEST_RFLAGS, 0x02);
3985         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3986                 kvm_rip_write(vcpu, 0xfff0);
3987         else
3988                 kvm_rip_write(vcpu, 0);
3989         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3990
3991         vmcs_writel(GUEST_DR7, 0x400);
3992
3993         vmcs_writel(GUEST_GDTR_BASE, 0);
3994         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3995
3996         vmcs_writel(GUEST_IDTR_BASE, 0);
3997         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3998
3999         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4000         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4001         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4002
4003         /* Special registers */
4004         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4005
4006         setup_msrs(vmx);
4007
4008         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4009
4010         if (cpu_has_vmx_tpr_shadow()) {
4011                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4012                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4013                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4014                                      __pa(vmx->vcpu.arch.apic->regs));
4015                 vmcs_write32(TPR_THRESHOLD, 0);
4016         }
4017
4018         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4019                 vmcs_write64(APIC_ACCESS_ADDR,
4020                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4021
4022         if (vmx->vpid != 0)
4023                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4024
4025         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4026         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4027         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4028         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4029         vmx_set_cr4(&vmx->vcpu, 0);
4030         vmx_set_efer(&vmx->vcpu, 0);
4031         vmx_fpu_activate(&vmx->vcpu);
4032         update_exception_bitmap(&vmx->vcpu);
4033
4034         vpid_sync_context(vmx);
4035
4036         ret = 0;
4037
4038         /* HACK: Don't enable emulation on guest boot/reset */
4039         vmx->emulation_required = 0;
4040
4041 out:
4042         return ret;
4043 }
4044
4045 /*
4046  * In nested virtualization, check if L1 asked to exit on external interrupts.
4047  * For most existing hypervisors, this will always return true.
4048  */
4049 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4050 {
4051         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4052                 PIN_BASED_EXT_INTR_MASK;
4053 }
4054
4055 static void enable_irq_window(struct kvm_vcpu *vcpu)
4056 {
4057         u32 cpu_based_vm_exec_control;
4058         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4059                 /*
4060                  * We get here if vmx_interrupt_allowed() said we can't
4061                  * inject to L1 now because L2 must run. Ask L2 to exit
4062                  * right after entry, so we can inject to L1 more promptly.
4063                  */
4064                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4065                 return;
4066         }
4067
4068         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4069         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4070         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4071 }
4072
4073 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4074 {
4075         u32 cpu_based_vm_exec_control;
4076
4077         if (!cpu_has_virtual_nmis()) {
4078                 enable_irq_window(vcpu);
4079                 return;
4080         }
4081
4082         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4083                 enable_irq_window(vcpu);
4084                 return;
4085         }
4086         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4087         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4088         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4089 }
4090
4091 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4092 {
4093         struct vcpu_vmx *vmx = to_vmx(vcpu);
4094         uint32_t intr;
4095         int irq = vcpu->arch.interrupt.nr;
4096
4097         trace_kvm_inj_virq(irq);
4098
4099         ++vcpu->stat.irq_injections;
4100         if (vmx->rmode.vm86_active) {
4101                 int inc_eip = 0;
4102                 if (vcpu->arch.interrupt.soft)
4103                         inc_eip = vcpu->arch.event_exit_inst_len;
4104                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4105                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4106                 return;
4107         }
4108         intr = irq | INTR_INFO_VALID_MASK;
4109         if (vcpu->arch.interrupt.soft) {
4110                 intr |= INTR_TYPE_SOFT_INTR;
4111                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4112                              vmx->vcpu.arch.event_exit_inst_len);
4113         } else
4114                 intr |= INTR_TYPE_EXT_INTR;
4115         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4116 }
4117
4118 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4119 {
4120         struct vcpu_vmx *vmx = to_vmx(vcpu);
4121
4122         if (is_guest_mode(vcpu))
4123                 return;
4124
4125         if (!cpu_has_virtual_nmis()) {
4126                 /*
4127                  * Tracking the NMI-blocked state in software is built upon
4128                  * finding the next open IRQ window. This, in turn, depends on
4129                  * well-behaving guests: They have to keep IRQs disabled at
4130                  * least as long as the NMI handler runs. Otherwise we may
4131                  * cause NMI nesting, maybe breaking the guest. But as this is
4132                  * highly unlikely, we can live with the residual risk.
4133                  */
4134                 vmx->soft_vnmi_blocked = 1;
4135                 vmx->vnmi_blocked_time = 0;
4136         }
4137
4138         ++vcpu->stat.nmi_injections;
4139         vmx->nmi_known_unmasked = false;
4140         if (vmx->rmode.vm86_active) {
4141                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4142                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4143                 return;
4144         }
4145         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4146                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4147 }
4148
4149 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4150 {
4151         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4152                 return 0;
4153
4154         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4155                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4156                    | GUEST_INTR_STATE_NMI));
4157 }
4158
4159 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4160 {
4161         if (!cpu_has_virtual_nmis())
4162                 return to_vmx(vcpu)->soft_vnmi_blocked;
4163         if (to_vmx(vcpu)->nmi_known_unmasked)
4164                 return false;
4165         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4166 }
4167
4168 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4169 {
4170         struct vcpu_vmx *vmx = to_vmx(vcpu);
4171
4172         if (!cpu_has_virtual_nmis()) {
4173                 if (vmx->soft_vnmi_blocked != masked) {
4174                         vmx->soft_vnmi_blocked = masked;
4175                         vmx->vnmi_blocked_time = 0;
4176                 }
4177         } else {
4178                 vmx->nmi_known_unmasked = !masked;
4179                 if (masked)
4180                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4181                                       GUEST_INTR_STATE_NMI);
4182                 else
4183                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4184                                         GUEST_INTR_STATE_NMI);
4185         }
4186 }
4187
4188 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4189 {
4190         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4191                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4192                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4193                     (vmcs12->idt_vectoring_info_field &
4194                      VECTORING_INFO_VALID_MASK))
4195                         return 0;
4196                 nested_vmx_vmexit(vcpu);
4197                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4198                 vmcs12->vm_exit_intr_info = 0;
4199                 /* fall through to normal code, but now in L1, not L2 */
4200         }
4201
4202         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4203                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4204                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4205 }
4206
4207 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4208 {
4209         int ret;
4210         struct kvm_userspace_memory_region tss_mem = {
4211                 .slot = TSS_PRIVATE_MEMSLOT,
4212                 .guest_phys_addr = addr,
4213                 .memory_size = PAGE_SIZE * 3,
4214                 .flags = 0,
4215         };
4216
4217         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4218         if (ret)
4219                 return ret;
4220         kvm->arch.tss_addr = addr;
4221         if (!init_rmode_tss(kvm))
4222                 return  -ENOMEM;
4223
4224         return 0;
4225 }
4226
4227 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4228                                   int vec, u32 err_code)
4229 {
4230         /*
4231          * Instruction with address size override prefix opcode 0x67
4232          * Cause the #SS fault with 0 error code in VM86 mode.
4233          */
4234         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4235                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4236                         return 1;
4237         /*
4238          * Forward all other exceptions that are valid in real mode.
4239          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4240          *        the required debugging infrastructure rework.
4241          */
4242         switch (vec) {
4243         case DB_VECTOR:
4244                 if (vcpu->guest_debug &
4245                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4246                         return 0;
4247                 kvm_queue_exception(vcpu, vec);
4248                 return 1;
4249         case BP_VECTOR:
4250                 /*
4251                  * Update instruction length as we may reinject the exception
4252                  * from user space while in guest debugging mode.
4253                  */
4254                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4255                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4256                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4257                         return 0;
4258                 /* fall through */
4259         case DE_VECTOR:
4260         case OF_VECTOR:
4261         case BR_VECTOR:
4262         case UD_VECTOR:
4263         case DF_VECTOR:
4264         case SS_VECTOR:
4265         case GP_VECTOR:
4266         case MF_VECTOR:
4267                 kvm_queue_exception(vcpu, vec);
4268                 return 1;
4269         }
4270         return 0;
4271 }
4272
4273 /*
4274  * Trigger machine check on the host. We assume all the MSRs are already set up
4275  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4276  * We pass a fake environment to the machine check handler because we want
4277  * the guest to be always treated like user space, no matter what context
4278  * it used internally.
4279  */
4280 static void kvm_machine_check(void)
4281 {
4282 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4283         struct pt_regs regs = {
4284                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4285                 .flags = X86_EFLAGS_IF,
4286         };
4287
4288         do_machine_check(&regs, 0);
4289 #endif
4290 }
4291
4292 static int handle_machine_check(struct kvm_vcpu *vcpu)
4293 {
4294         /* already handled by vcpu_run */
4295         return 1;
4296 }
4297
4298 static int handle_exception(struct kvm_vcpu *vcpu)
4299 {
4300         struct vcpu_vmx *vmx = to_vmx(vcpu);
4301         struct kvm_run *kvm_run = vcpu->run;
4302         u32 intr_info, ex_no, error_code;
4303         unsigned long cr2, rip, dr6;
4304         u32 vect_info;
4305         enum emulation_result er;
4306
4307         vect_info = vmx->idt_vectoring_info;
4308         intr_info = vmx->exit_intr_info;
4309
4310         if (is_machine_check(intr_info))
4311                 return handle_machine_check(vcpu);
4312
4313         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4314             !is_page_fault(intr_info)) {
4315                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4316                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4317                 vcpu->run->internal.ndata = 2;
4318                 vcpu->run->internal.data[0] = vect_info;
4319                 vcpu->run->internal.data[1] = intr_info;
4320                 return 0;
4321         }
4322
4323         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4324                 return 1;  /* already handled by vmx_vcpu_run() */
4325
4326         if (is_no_device(intr_info)) {
4327                 vmx_fpu_activate(vcpu);
4328                 return 1;
4329         }
4330
4331         if (is_invalid_opcode(intr_info)) {
4332                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4333                 if (er != EMULATE_DONE)
4334                         kvm_queue_exception(vcpu, UD_VECTOR);
4335                 return 1;
4336         }
4337
4338         error_code = 0;
4339         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4340                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4341         if (is_page_fault(intr_info)) {
4342                 /* EPT won't cause page fault directly */
4343                 BUG_ON(enable_ept);
4344                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4345                 trace_kvm_page_fault(cr2, error_code);
4346
4347                 if (kvm_event_needs_reinjection(vcpu))
4348                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4349                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4350         }
4351
4352         if (vmx->rmode.vm86_active &&
4353             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4354                                                                 error_code)) {
4355                 if (vcpu->arch.halt_request) {
4356                         vcpu->arch.halt_request = 0;
4357                         return kvm_emulate_halt(vcpu);
4358                 }
4359                 return 1;
4360         }
4361
4362         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4363         switch (ex_no) {
4364         case DB_VECTOR:
4365                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4366                 if (!(vcpu->guest_debug &
4367                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4368                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4369                         kvm_queue_exception(vcpu, DB_VECTOR);
4370                         return 1;
4371                 }
4372                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4373                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4374                 /* fall through */
4375         case BP_VECTOR:
4376                 /*
4377                  * Update instruction length as we may reinject #BP from
4378                  * user space while in guest debugging mode. Reading it for
4379                  * #DB as well causes no harm, it is not used in that case.
4380                  */
4381                 vmx->vcpu.arch.event_exit_inst_len =
4382                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4383                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4384                 rip = kvm_rip_read(vcpu);
4385                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4386                 kvm_run->debug.arch.exception = ex_no;
4387                 break;
4388         default:
4389                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4390                 kvm_run->ex.exception = ex_no;
4391                 kvm_run->ex.error_code = error_code;
4392                 break;
4393         }
4394         return 0;
4395 }
4396
4397 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4398 {
4399         ++vcpu->stat.irq_exits;
4400         return 1;
4401 }
4402
4403 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4404 {
4405         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4406         return 0;
4407 }
4408
4409 static int handle_io(struct kvm_vcpu *vcpu)
4410 {
4411         unsigned long exit_qualification;
4412         int size, in, string;
4413         unsigned port;
4414
4415         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4416         string = (exit_qualification & 16) != 0;
4417         in = (exit_qualification & 8) != 0;
4418
4419         ++vcpu->stat.io_exits;
4420
4421         if (string || in)
4422                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4423
4424         port = exit_qualification >> 16;
4425         size = (exit_qualification & 7) + 1;
4426         skip_emulated_instruction(vcpu);
4427
4428         return kvm_fast_pio_out(vcpu, size, port);
4429 }
4430
4431 static void
4432 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4433 {
4434         /*
4435          * Patch in the VMCALL instruction:
4436          */
4437         hypercall[0] = 0x0f;
4438         hypercall[1] = 0x01;
4439         hypercall[2] = 0xc1;
4440 }
4441
4442 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4443 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4444 {
4445         if (to_vmx(vcpu)->nested.vmxon &&
4446             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4447                 return 1;
4448
4449         if (is_guest_mode(vcpu)) {
4450                 /*
4451                  * We get here when L2 changed cr0 in a way that did not change
4452                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4453                  * but did change L0 shadowed bits. This can currently happen
4454                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4455                  * loading) while pretending to allow the guest to change it.
4456                  */
4457                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4458                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4459                         return 1;
4460                 vmcs_writel(CR0_READ_SHADOW, val);
4461                 return 0;
4462         } else
4463                 return kvm_set_cr0(vcpu, val);
4464 }
4465
4466 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4467 {
4468         if (is_guest_mode(vcpu)) {
4469                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4470                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4471                         return 1;
4472                 vmcs_writel(CR4_READ_SHADOW, val);
4473                 return 0;
4474         } else
4475                 return kvm_set_cr4(vcpu, val);
4476 }
4477
4478 /* called to set cr0 as approriate for clts instruction exit. */
4479 static void handle_clts(struct kvm_vcpu *vcpu)
4480 {
4481         if (is_guest_mode(vcpu)) {
4482                 /*
4483                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4484                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4485                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4486                  */
4487                 vmcs_writel(CR0_READ_SHADOW,
4488                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4489                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4490         } else
4491                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4492 }
4493
4494 static int handle_cr(struct kvm_vcpu *vcpu)
4495 {
4496         unsigned long exit_qualification, val;
4497         int cr;
4498         int reg;
4499         int err;
4500
4501         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4502         cr = exit_qualification & 15;
4503         reg = (exit_qualification >> 8) & 15;
4504         switch ((exit_qualification >> 4) & 3) {
4505         case 0: /* mov to cr */
4506                 val = kvm_register_read(vcpu, reg);
4507                 trace_kvm_cr_write(cr, val);
4508                 switch (cr) {
4509                 case 0:
4510                         err = handle_set_cr0(vcpu, val);
4511                         kvm_complete_insn_gp(vcpu, err);
4512                         return 1;
4513                 case 3:
4514                         err = kvm_set_cr3(vcpu, val);
4515                         kvm_complete_insn_gp(vcpu, err);
4516                         return 1;
4517                 case 4:
4518                         err = handle_set_cr4(vcpu, val);
4519                         kvm_complete_insn_gp(vcpu, err);
4520                         return 1;
4521                 case 8: {
4522                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4523                                 u8 cr8 = kvm_register_read(vcpu, reg);
4524                                 err = kvm_set_cr8(vcpu, cr8);
4525                                 kvm_complete_insn_gp(vcpu, err);
4526                                 if (irqchip_in_kernel(vcpu->kvm))
4527                                         return 1;
4528                                 if (cr8_prev <= cr8)
4529                                         return 1;
4530                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4531                                 return 0;
4532                         }
4533                 };
4534                 break;
4535         case 2: /* clts */
4536                 handle_clts(vcpu);
4537                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4538                 skip_emulated_instruction(vcpu);
4539                 vmx_fpu_activate(vcpu);
4540                 return 1;
4541         case 1: /*mov from cr*/
4542                 switch (cr) {
4543                 case 3:
4544                         val = kvm_read_cr3(vcpu);
4545                         kvm_register_write(vcpu, reg, val);
4546                         trace_kvm_cr_read(cr, val);
4547                         skip_emulated_instruction(vcpu);
4548                         return 1;
4549                 case 8:
4550                         val = kvm_get_cr8(vcpu);
4551                         kvm_register_write(vcpu, reg, val);
4552                         trace_kvm_cr_read(cr, val);
4553                         skip_emulated_instruction(vcpu);
4554                         return 1;
4555                 }
4556                 break;
4557         case 3: /* lmsw */
4558                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4559                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4560                 kvm_lmsw(vcpu, val);
4561
4562                 skip_emulated_instruction(vcpu);
4563                 return 1;
4564         default:
4565                 break;
4566         }
4567         vcpu->run->exit_reason = 0;
4568         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4569                (int)(exit_qualification >> 4) & 3, cr);
4570         return 0;
4571 }
4572
4573 static int handle_dr(struct kvm_vcpu *vcpu)
4574 {
4575         unsigned long exit_qualification;
4576         int dr, reg;
4577
4578         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4579         if (!kvm_require_cpl(vcpu, 0))
4580                 return 1;
4581         dr = vmcs_readl(GUEST_DR7);
4582         if (dr & DR7_GD) {
4583                 /*
4584                  * As the vm-exit takes precedence over the debug trap, we
4585                  * need to emulate the latter, either for the host or the
4586                  * guest debugging itself.
4587                  */
4588                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4589                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4590                         vcpu->run->debug.arch.dr7 = dr;
4591                         vcpu->run->debug.arch.pc =
4592                                 vmcs_readl(GUEST_CS_BASE) +
4593                                 vmcs_readl(GUEST_RIP);
4594                         vcpu->run->debug.arch.exception = DB_VECTOR;
4595                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4596                         return 0;
4597                 } else {
4598                         vcpu->arch.dr7 &= ~DR7_GD;
4599                         vcpu->arch.dr6 |= DR6_BD;
4600                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4601                         kvm_queue_exception(vcpu, DB_VECTOR);
4602                         return 1;
4603                 }
4604         }
4605
4606         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4607         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4608         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4609         if (exit_qualification & TYPE_MOV_FROM_DR) {
4610                 unsigned long val;
4611                 if (!kvm_get_dr(vcpu, dr, &val))
4612                         kvm_register_write(vcpu, reg, val);
4613         } else
4614                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4615         skip_emulated_instruction(vcpu);
4616         return 1;
4617 }
4618
4619 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4620 {
4621         vmcs_writel(GUEST_DR7, val);
4622 }
4623
4624 static int handle_cpuid(struct kvm_vcpu *vcpu)
4625 {
4626         kvm_emulate_cpuid(vcpu);
4627         return 1;
4628 }
4629
4630 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4631 {
4632         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4633         u64 data;
4634
4635         if (vmx_get_msr(vcpu, ecx, &data)) {
4636                 trace_kvm_msr_read_ex(ecx);
4637                 kvm_inject_gp(vcpu, 0);
4638                 return 1;
4639         }
4640
4641         trace_kvm_msr_read(ecx, data);
4642
4643         /* FIXME: handling of bits 32:63 of rax, rdx */
4644         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4645         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4646         skip_emulated_instruction(vcpu);
4647         return 1;
4648 }
4649
4650 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4651 {
4652         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4653         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4654                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4655
4656         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4657                 trace_kvm_msr_write_ex(ecx, data);
4658                 kvm_inject_gp(vcpu, 0);
4659                 return 1;
4660         }
4661
4662         trace_kvm_msr_write(ecx, data);
4663         skip_emulated_instruction(vcpu);
4664         return 1;
4665 }
4666
4667 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4668 {
4669         kvm_make_request(KVM_REQ_EVENT, vcpu);
4670         return 1;
4671 }
4672
4673 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4674 {
4675         u32 cpu_based_vm_exec_control;
4676
4677         /* clear pending irq */
4678         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4679         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4680         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4681
4682         kvm_make_request(KVM_REQ_EVENT, vcpu);
4683
4684         ++vcpu->stat.irq_window_exits;
4685
4686         /*
4687          * If the user space waits to inject interrupts, exit as soon as
4688          * possible
4689          */
4690         if (!irqchip_in_kernel(vcpu->kvm) &&
4691             vcpu->run->request_interrupt_window &&
4692             !kvm_cpu_has_interrupt(vcpu)) {
4693                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4694                 return 0;
4695         }
4696         return 1;
4697 }
4698
4699 static int handle_halt(struct kvm_vcpu *vcpu)
4700 {
4701         skip_emulated_instruction(vcpu);
4702         return kvm_emulate_halt(vcpu);
4703 }
4704
4705 static int handle_vmcall(struct kvm_vcpu *vcpu)
4706 {
4707         skip_emulated_instruction(vcpu);
4708         kvm_emulate_hypercall(vcpu);
4709         return 1;
4710 }
4711
4712 static int handle_invd(struct kvm_vcpu *vcpu)
4713 {
4714         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4715 }
4716
4717 static int handle_invlpg(struct kvm_vcpu *vcpu)
4718 {
4719         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4720
4721         kvm_mmu_invlpg(vcpu, exit_qualification);
4722         skip_emulated_instruction(vcpu);
4723         return 1;
4724 }
4725
4726 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4727 {
4728         int err;
4729
4730         err = kvm_rdpmc(vcpu);
4731         kvm_complete_insn_gp(vcpu, err);
4732
4733         return 1;
4734 }
4735
4736 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4737 {
4738         skip_emulated_instruction(vcpu);
4739         kvm_emulate_wbinvd(vcpu);
4740         return 1;
4741 }
4742
4743 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4744 {
4745         u64 new_bv = kvm_read_edx_eax(vcpu);
4746         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4747
4748         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4749                 skip_emulated_instruction(vcpu);
4750         return 1;
4751 }
4752
4753 static int handle_apic_access(struct kvm_vcpu *vcpu)
4754 {
4755         if (likely(fasteoi)) {
4756                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4757                 int access_type, offset;
4758
4759                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4760                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4761                 /*
4762                  * Sane guest uses MOV to write EOI, with written value
4763                  * not cared. So make a short-circuit here by avoiding
4764                  * heavy instruction emulation.
4765                  */
4766                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4767                     (offset == APIC_EOI)) {
4768                         kvm_lapic_set_eoi(vcpu);
4769                         skip_emulated_instruction(vcpu);
4770                         return 1;
4771                 }
4772         }
4773         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4774 }
4775
4776 static int handle_task_switch(struct kvm_vcpu *vcpu)
4777 {
4778         struct vcpu_vmx *vmx = to_vmx(vcpu);
4779         unsigned long exit_qualification;
4780         bool has_error_code = false;
4781         u32 error_code = 0;
4782         u16 tss_selector;
4783         int reason, type, idt_v, idt_index;
4784
4785         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4786         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4787         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4788
4789         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4790
4791         reason = (u32)exit_qualification >> 30;
4792         if (reason == TASK_SWITCH_GATE && idt_v) {
4793                 switch (type) {
4794                 case INTR_TYPE_NMI_INTR:
4795                         vcpu->arch.nmi_injected = false;
4796                         vmx_set_nmi_mask(vcpu, true);
4797                         break;
4798                 case INTR_TYPE_EXT_INTR:
4799                 case INTR_TYPE_SOFT_INTR:
4800                         kvm_clear_interrupt_queue(vcpu);
4801                         break;
4802                 case INTR_TYPE_HARD_EXCEPTION:
4803                         if (vmx->idt_vectoring_info &
4804                             VECTORING_INFO_DELIVER_CODE_MASK) {
4805                                 has_error_code = true;
4806                                 error_code =
4807                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4808                         }
4809                         /* fall through */
4810                 case INTR_TYPE_SOFT_EXCEPTION:
4811                         kvm_clear_exception_queue(vcpu);
4812                         break;
4813                 default:
4814                         break;
4815                 }
4816         }
4817         tss_selector = exit_qualification;
4818
4819         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4820                        type != INTR_TYPE_EXT_INTR &&
4821                        type != INTR_TYPE_NMI_INTR))
4822                 skip_emulated_instruction(vcpu);
4823
4824         if (kvm_task_switch(vcpu, tss_selector,
4825                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4826                             has_error_code, error_code) == EMULATE_FAIL) {
4827                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4828                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4829                 vcpu->run->internal.ndata = 0;
4830                 return 0;
4831         }
4832
4833         /* clear all local breakpoint enable flags */
4834         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4835
4836         /*
4837          * TODO: What about debug traps on tss switch?
4838          *       Are we supposed to inject them and update dr6?
4839          */
4840
4841         return 1;
4842 }
4843
4844 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4845 {
4846         unsigned long exit_qualification;
4847         gpa_t gpa;
4848         u32 error_code;
4849         int gla_validity;
4850
4851         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4852
4853         if (exit_qualification & (1 << 6)) {
4854                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4855                 return -EINVAL;
4856         }
4857
4858         gla_validity = (exit_qualification >> 7) & 0x3;
4859         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4860                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4861                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4862                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4863                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4864                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4865                         (long unsigned int)exit_qualification);
4866                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4867                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4868                 return 0;
4869         }
4870
4871         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4872         trace_kvm_page_fault(gpa, exit_qualification);
4873
4874         /* It is a write fault? */
4875         error_code = exit_qualification & (1U << 1);
4876         /* ept page table is present? */
4877         error_code |= (exit_qualification >> 3) & 0x1;
4878
4879         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4880 }
4881
4882 static u64 ept_rsvd_mask(u64 spte, int level)
4883 {
4884         int i;
4885         u64 mask = 0;
4886
4887         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4888                 mask |= (1ULL << i);
4889
4890         if (level > 2)
4891                 /* bits 7:3 reserved */
4892                 mask |= 0xf8;
4893         else if (level == 2) {
4894                 if (spte & (1ULL << 7))
4895                         /* 2MB ref, bits 20:12 reserved */
4896                         mask |= 0x1ff000;
4897                 else
4898                         /* bits 6:3 reserved */
4899                         mask |= 0x78;
4900         }
4901
4902         return mask;
4903 }
4904
4905 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4906                                        int level)
4907 {
4908         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4909
4910         /* 010b (write-only) */
4911         WARN_ON((spte & 0x7) == 0x2);
4912
4913         /* 110b (write/execute) */
4914         WARN_ON((spte & 0x7) == 0x6);
4915
4916         /* 100b (execute-only) and value not supported by logical processor */
4917         if (!cpu_has_vmx_ept_execute_only())
4918                 WARN_ON((spte & 0x7) == 0x4);
4919
4920         /* not 000b */
4921         if ((spte & 0x7)) {
4922                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4923
4924                 if (rsvd_bits != 0) {
4925                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4926                                          __func__, rsvd_bits);
4927                         WARN_ON(1);
4928                 }
4929
4930                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4931                         u64 ept_mem_type = (spte & 0x38) >> 3;
4932
4933                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4934                             ept_mem_type == 7) {
4935                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4936                                                 __func__, ept_mem_type);
4937                                 WARN_ON(1);
4938                         }
4939                 }
4940         }
4941 }
4942
4943 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4944 {
4945         u64 sptes[4];
4946         int nr_sptes, i, ret;
4947         gpa_t gpa;
4948
4949         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4950
4951         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4952         if (likely(ret == 1))
4953                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4954                                               EMULATE_DONE;
4955         if (unlikely(!ret))
4956                 return 1;
4957
4958         /* It is the real ept misconfig */
4959         printk(KERN_ERR "EPT: Misconfiguration.\n");
4960         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4961
4962         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4963
4964         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4965                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4966
4967         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4968         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4969
4970         return 0;
4971 }
4972
4973 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4974 {
4975         u32 cpu_based_vm_exec_control;
4976
4977         /* clear pending NMI */
4978         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4979         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4980         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4981         ++vcpu->stat.nmi_window_exits;
4982         kvm_make_request(KVM_REQ_EVENT, vcpu);
4983
4984         return 1;
4985 }
4986
4987 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4988 {
4989         struct vcpu_vmx *vmx = to_vmx(vcpu);
4990         enum emulation_result err = EMULATE_DONE;
4991         int ret = 1;
4992         u32 cpu_exec_ctrl;
4993         bool intr_window_requested;
4994         unsigned count = 130;
4995
4996         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4997         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4998
4999         while (!guest_state_valid(vcpu) && count-- != 0) {
5000                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5001                         return handle_interrupt_window(&vmx->vcpu);
5002
5003                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5004                         return 1;
5005
5006                 err = emulate_instruction(vcpu, 0);
5007
5008                 if (err == EMULATE_DO_MMIO) {
5009                         ret = 0;
5010                         goto out;
5011                 }
5012
5013                 if (err != EMULATE_DONE) {
5014                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5015                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5016                         vcpu->run->internal.ndata = 0;
5017                         return 0;
5018                 }
5019
5020                 if (signal_pending(current))
5021                         goto out;
5022                 if (need_resched())
5023                         schedule();
5024         }
5025
5026         vmx->emulation_required = !guest_state_valid(vcpu);
5027 out:
5028         return ret;
5029 }
5030
5031 /*
5032  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5033  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5034  */
5035 static int handle_pause(struct kvm_vcpu *vcpu)
5036 {
5037         skip_emulated_instruction(vcpu);
5038         kvm_vcpu_on_spin(vcpu);
5039
5040         return 1;
5041 }
5042
5043 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5044 {
5045         kvm_queue_exception(vcpu, UD_VECTOR);
5046         return 1;
5047 }
5048
5049 /*
5050  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5051  * We could reuse a single VMCS for all the L2 guests, but we also want the
5052  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5053  * allows keeping them loaded on the processor, and in the future will allow
5054  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5055  * every entry if they never change.
5056  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5057  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5058  *
5059  * The following functions allocate and free a vmcs02 in this pool.
5060  */
5061
5062 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5063 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5064 {
5065         struct vmcs02_list *item;
5066         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5067                 if (item->vmptr == vmx->nested.current_vmptr) {
5068                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5069                         return &item->vmcs02;
5070                 }
5071
5072         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5073                 /* Recycle the least recently used VMCS. */
5074                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5075                         struct vmcs02_list, list);
5076                 item->vmptr = vmx->nested.current_vmptr;
5077                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5078                 return &item->vmcs02;
5079         }
5080
5081         /* Create a new VMCS */
5082         item = (struct vmcs02_list *)
5083                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5084         if (!item)
5085                 return NULL;
5086         item->vmcs02.vmcs = alloc_vmcs();
5087         if (!item->vmcs02.vmcs) {
5088                 kfree(item);
5089                 return NULL;
5090         }
5091         loaded_vmcs_init(&item->vmcs02);
5092         item->vmptr = vmx->nested.current_vmptr;
5093         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5094         vmx->nested.vmcs02_num++;
5095         return &item->vmcs02;
5096 }
5097
5098 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5099 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5100 {
5101         struct vmcs02_list *item;
5102         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5103                 if (item->vmptr == vmptr) {
5104                         free_loaded_vmcs(&item->vmcs02);
5105                         list_del(&item->list);
5106                         kfree(item);
5107                         vmx->nested.vmcs02_num--;
5108                         return;
5109                 }
5110 }
5111
5112 /*
5113  * Free all VMCSs saved for this vcpu, except the one pointed by
5114  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5115  * currently used, if running L2), and vmcs01 when running L2.
5116  */
5117 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5118 {
5119         struct vmcs02_list *item, *n;
5120         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5121                 if (vmx->loaded_vmcs != &item->vmcs02)
5122                         free_loaded_vmcs(&item->vmcs02);
5123                 list_del(&item->list);
5124                 kfree(item);
5125         }
5126         vmx->nested.vmcs02_num = 0;
5127
5128         if (vmx->loaded_vmcs != &vmx->vmcs01)
5129                 free_loaded_vmcs(&vmx->vmcs01);
5130 }
5131
5132 /*
5133  * Emulate the VMXON instruction.
5134  * Currently, we just remember that VMX is active, and do not save or even
5135  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5136  * do not currently need to store anything in that guest-allocated memory
5137  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5138  * argument is different from the VMXON pointer (which the spec says they do).
5139  */
5140 static int handle_vmon(struct kvm_vcpu *vcpu)
5141 {
5142         struct kvm_segment cs;
5143         struct vcpu_vmx *vmx = to_vmx(vcpu);
5144
5145         /* The Intel VMX Instruction Reference lists a bunch of bits that
5146          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5147          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5148          * Otherwise, we should fail with #UD. We test these now:
5149          */
5150         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5151             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5152             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5153                 kvm_queue_exception(vcpu, UD_VECTOR);
5154                 return 1;
5155         }
5156
5157         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5158         if (is_long_mode(vcpu) && !cs.l) {
5159                 kvm_queue_exception(vcpu, UD_VECTOR);
5160                 return 1;
5161         }
5162
5163         if (vmx_get_cpl(vcpu)) {
5164                 kvm_inject_gp(vcpu, 0);
5165                 return 1;
5166         }
5167
5168         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5169         vmx->nested.vmcs02_num = 0;
5170
5171         vmx->nested.vmxon = true;
5172
5173         skip_emulated_instruction(vcpu);
5174         return 1;
5175 }
5176
5177 /*
5178  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5179  * for running VMX instructions (except VMXON, whose prerequisites are
5180  * slightly different). It also specifies what exception to inject otherwise.
5181  */
5182 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5183 {
5184         struct kvm_segment cs;
5185         struct vcpu_vmx *vmx = to_vmx(vcpu);
5186
5187         if (!vmx->nested.vmxon) {
5188                 kvm_queue_exception(vcpu, UD_VECTOR);
5189                 return 0;
5190         }
5191
5192         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5193         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5194             (is_long_mode(vcpu) && !cs.l)) {
5195                 kvm_queue_exception(vcpu, UD_VECTOR);
5196                 return 0;
5197         }
5198
5199         if (vmx_get_cpl(vcpu)) {
5200                 kvm_inject_gp(vcpu, 0);
5201                 return 0;
5202         }
5203
5204         return 1;
5205 }
5206
5207 /*
5208  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5209  * just stops using VMX.
5210  */
5211 static void free_nested(struct vcpu_vmx *vmx)
5212 {
5213         if (!vmx->nested.vmxon)
5214                 return;
5215         vmx->nested.vmxon = false;
5216         if (vmx->nested.current_vmptr != -1ull) {
5217                 kunmap(vmx->nested.current_vmcs12_page);
5218                 nested_release_page(vmx->nested.current_vmcs12_page);
5219                 vmx->nested.current_vmptr = -1ull;
5220                 vmx->nested.current_vmcs12 = NULL;
5221         }
5222         /* Unpin physical memory we referred to in current vmcs02 */
5223         if (vmx->nested.apic_access_page) {
5224                 nested_release_page(vmx->nested.apic_access_page);
5225                 vmx->nested.apic_access_page = 0;
5226         }
5227
5228         nested_free_all_saved_vmcss(vmx);
5229 }
5230
5231 /* Emulate the VMXOFF instruction */
5232 static int handle_vmoff(struct kvm_vcpu *vcpu)
5233 {
5234         if (!nested_vmx_check_permission(vcpu))
5235                 return 1;
5236         free_nested(to_vmx(vcpu));
5237         skip_emulated_instruction(vcpu);
5238         return 1;
5239 }
5240
5241 /*
5242  * Decode the memory-address operand of a vmx instruction, as recorded on an
5243  * exit caused by such an instruction (run by a guest hypervisor).
5244  * On success, returns 0. When the operand is invalid, returns 1 and throws
5245  * #UD or #GP.
5246  */
5247 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5248                                  unsigned long exit_qualification,
5249                                  u32 vmx_instruction_info, gva_t *ret)
5250 {
5251         /*
5252          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5253          * Execution", on an exit, vmx_instruction_info holds most of the
5254          * addressing components of the operand. Only the displacement part
5255          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5256          * For how an actual address is calculated from all these components,
5257          * refer to Vol. 1, "Operand Addressing".
5258          */
5259         int  scaling = vmx_instruction_info & 3;
5260         int  addr_size = (vmx_instruction_info >> 7) & 7;
5261         bool is_reg = vmx_instruction_info & (1u << 10);
5262         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5263         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5264         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5265         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5266         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5267
5268         if (is_reg) {
5269                 kvm_queue_exception(vcpu, UD_VECTOR);
5270                 return 1;
5271         }
5272
5273         /* Addr = segment_base + offset */
5274         /* offset = base + [index * scale] + displacement */
5275         *ret = vmx_get_segment_base(vcpu, seg_reg);
5276         if (base_is_valid)
5277                 *ret += kvm_register_read(vcpu, base_reg);
5278         if (index_is_valid)
5279                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5280         *ret += exit_qualification; /* holds the displacement */
5281
5282         if (addr_size == 1) /* 32 bit */
5283                 *ret &= 0xffffffff;
5284
5285         /*
5286          * TODO: throw #GP (and return 1) in various cases that the VM*
5287          * instructions require it - e.g., offset beyond segment limit,
5288          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5289          * address, and so on. Currently these are not checked.
5290          */
5291         return 0;
5292 }
5293
5294 /*
5295  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5296  * set the success or error code of an emulated VMX instruction, as specified
5297  * by Vol 2B, VMX Instruction Reference, "Conventions".
5298  */
5299 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5300 {
5301         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5302                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5303                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5304 }
5305
5306 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5307 {
5308         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5309                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5310                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5311                         | X86_EFLAGS_CF);
5312 }
5313
5314 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5315                                         u32 vm_instruction_error)
5316 {
5317         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5318                 /*
5319                  * failValid writes the error number to the current VMCS, which
5320                  * can't be done there isn't a current VMCS.
5321                  */
5322                 nested_vmx_failInvalid(vcpu);
5323                 return;
5324         }
5325         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5326                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5327                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5328                         | X86_EFLAGS_ZF);
5329         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5330 }
5331
5332 /* Emulate the VMCLEAR instruction */
5333 static int handle_vmclear(struct kvm_vcpu *vcpu)
5334 {
5335         struct vcpu_vmx *vmx = to_vmx(vcpu);
5336         gva_t gva;
5337         gpa_t vmptr;
5338         struct vmcs12 *vmcs12;
5339         struct page *page;
5340         struct x86_exception e;
5341
5342         if (!nested_vmx_check_permission(vcpu))
5343                 return 1;
5344
5345         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5346                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5347                 return 1;
5348
5349         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5350                                 sizeof(vmptr), &e)) {
5351                 kvm_inject_page_fault(vcpu, &e);
5352                 return 1;
5353         }
5354
5355         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5356                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5357                 skip_emulated_instruction(vcpu);
5358                 return 1;
5359         }
5360
5361         if (vmptr == vmx->nested.current_vmptr) {
5362                 kunmap(vmx->nested.current_vmcs12_page);
5363                 nested_release_page(vmx->nested.current_vmcs12_page);
5364                 vmx->nested.current_vmptr = -1ull;
5365                 vmx->nested.current_vmcs12 = NULL;
5366         }
5367
5368         page = nested_get_page(vcpu, vmptr);
5369         if (page == NULL) {
5370                 /*
5371                  * For accurate processor emulation, VMCLEAR beyond available
5372                  * physical memory should do nothing at all. However, it is
5373                  * possible that a nested vmx bug, not a guest hypervisor bug,
5374                  * resulted in this case, so let's shut down before doing any
5375                  * more damage:
5376                  */
5377                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5378                 return 1;
5379         }
5380         vmcs12 = kmap(page);
5381         vmcs12->launch_state = 0;
5382         kunmap(page);
5383         nested_release_page(page);
5384
5385         nested_free_vmcs02(vmx, vmptr);
5386
5387         skip_emulated_instruction(vcpu);
5388         nested_vmx_succeed(vcpu);
5389         return 1;
5390 }
5391
5392 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5393
5394 /* Emulate the VMLAUNCH instruction */
5395 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5396 {
5397         return nested_vmx_run(vcpu, true);
5398 }
5399
5400 /* Emulate the VMRESUME instruction */
5401 static int handle_vmresume(struct kvm_vcpu *vcpu)
5402 {
5403
5404         return nested_vmx_run(vcpu, false);
5405 }
5406
5407 enum vmcs_field_type {
5408         VMCS_FIELD_TYPE_U16 = 0,
5409         VMCS_FIELD_TYPE_U64 = 1,
5410         VMCS_FIELD_TYPE_U32 = 2,
5411         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5412 };
5413
5414 static inline int vmcs_field_type(unsigned long field)
5415 {
5416         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5417                 return VMCS_FIELD_TYPE_U32;
5418         return (field >> 13) & 0x3 ;
5419 }
5420
5421 static inline int vmcs_field_readonly(unsigned long field)
5422 {
5423         return (((field >> 10) & 0x3) == 1);
5424 }
5425
5426 /*
5427  * Read a vmcs12 field. Since these can have varying lengths and we return
5428  * one type, we chose the biggest type (u64) and zero-extend the return value
5429  * to that size. Note that the caller, handle_vmread, might need to use only
5430  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5431  * 64-bit fields are to be returned).
5432  */
5433 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5434                                         unsigned long field, u64 *ret)
5435 {
5436         short offset = vmcs_field_to_offset(field);
5437         char *p;
5438
5439         if (offset < 0)
5440                 return 0;
5441
5442         p = ((char *)(get_vmcs12(vcpu))) + offset;
5443
5444         switch (vmcs_field_type(field)) {
5445         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5446                 *ret = *((natural_width *)p);
5447                 return 1;
5448         case VMCS_FIELD_TYPE_U16:
5449                 *ret = *((u16 *)p);
5450                 return 1;
5451         case VMCS_FIELD_TYPE_U32:
5452                 *ret = *((u32 *)p);
5453                 return 1;
5454         case VMCS_FIELD_TYPE_U64:
5455                 *ret = *((u64 *)p);
5456                 return 1;
5457         default:
5458                 return 0; /* can never happen. */
5459         }
5460 }
5461
5462 /*
5463  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5464  * used before) all generate the same failure when it is missing.
5465  */
5466 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5467 {
5468         struct vcpu_vmx *vmx = to_vmx(vcpu);
5469         if (vmx->nested.current_vmptr == -1ull) {
5470                 nested_vmx_failInvalid(vcpu);
5471                 skip_emulated_instruction(vcpu);
5472                 return 0;
5473         }
5474         return 1;
5475 }
5476
5477 static int handle_vmread(struct kvm_vcpu *vcpu)
5478 {
5479         unsigned long field;
5480         u64 field_value;
5481         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5482         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5483         gva_t gva = 0;
5484
5485         if (!nested_vmx_check_permission(vcpu) ||
5486             !nested_vmx_check_vmcs12(vcpu))
5487                 return 1;
5488
5489         /* Decode instruction info and find the field to read */
5490         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5491         /* Read the field, zero-extended to a u64 field_value */
5492         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5493                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5494                 skip_emulated_instruction(vcpu);
5495                 return 1;
5496         }
5497         /*
5498          * Now copy part of this value to register or memory, as requested.
5499          * Note that the number of bits actually copied is 32 or 64 depending
5500          * on the guest's mode (32 or 64 bit), not on the given field's length.
5501          */
5502         if (vmx_instruction_info & (1u << 10)) {
5503                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5504                         field_value);
5505         } else {
5506                 if (get_vmx_mem_address(vcpu, exit_qualification,
5507                                 vmx_instruction_info, &gva))
5508                         return 1;
5509                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5510                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5511                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5512         }
5513
5514         nested_vmx_succeed(vcpu);
5515         skip_emulated_instruction(vcpu);
5516         return 1;
5517 }
5518
5519
5520 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5521 {
5522         unsigned long field;
5523         gva_t gva;
5524         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5525         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5526         char *p;
5527         short offset;
5528         /* The value to write might be 32 or 64 bits, depending on L1's long
5529          * mode, and eventually we need to write that into a field of several
5530          * possible lengths. The code below first zero-extends the value to 64
5531          * bit (field_value), and then copies only the approriate number of
5532          * bits into the vmcs12 field.
5533          */
5534         u64 field_value = 0;
5535         struct x86_exception e;
5536
5537         if (!nested_vmx_check_permission(vcpu) ||
5538             !nested_vmx_check_vmcs12(vcpu))
5539                 return 1;
5540
5541         if (vmx_instruction_info & (1u << 10))
5542                 field_value = kvm_register_read(vcpu,
5543                         (((vmx_instruction_info) >> 3) & 0xf));
5544         else {
5545                 if (get_vmx_mem_address(vcpu, exit_qualification,
5546                                 vmx_instruction_info, &gva))
5547                         return 1;
5548                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5549                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5550                         kvm_inject_page_fault(vcpu, &e);
5551                         return 1;
5552                 }
5553         }
5554
5555
5556         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5557         if (vmcs_field_readonly(field)) {
5558                 nested_vmx_failValid(vcpu,
5559                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5560                 skip_emulated_instruction(vcpu);
5561                 return 1;
5562         }
5563
5564         offset = vmcs_field_to_offset(field);
5565         if (offset < 0) {
5566                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5567                 skip_emulated_instruction(vcpu);
5568                 return 1;
5569         }
5570         p = ((char *) get_vmcs12(vcpu)) + offset;
5571
5572         switch (vmcs_field_type(field)) {
5573         case VMCS_FIELD_TYPE_U16:
5574                 *(u16 *)p = field_value;
5575                 break;
5576         case VMCS_FIELD_TYPE_U32:
5577                 *(u32 *)p = field_value;
5578                 break;
5579         case VMCS_FIELD_TYPE_U64:
5580                 *(u64 *)p = field_value;
5581                 break;
5582         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5583                 *(natural_width *)p = field_value;
5584                 break;
5585         default:
5586                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5587                 skip_emulated_instruction(vcpu);
5588                 return 1;
5589         }
5590
5591         nested_vmx_succeed(vcpu);
5592         skip_emulated_instruction(vcpu);
5593         return 1;
5594 }
5595
5596 /* Emulate the VMPTRLD instruction */
5597 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5598 {
5599         struct vcpu_vmx *vmx = to_vmx(vcpu);
5600         gva_t gva;
5601         gpa_t vmptr;
5602         struct x86_exception e;
5603
5604         if (!nested_vmx_check_permission(vcpu))
5605                 return 1;
5606
5607         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5608                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5609                 return 1;
5610
5611         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5612                                 sizeof(vmptr), &e)) {
5613                 kvm_inject_page_fault(vcpu, &e);
5614                 return 1;
5615         }
5616
5617         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5618                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5619                 skip_emulated_instruction(vcpu);
5620                 return 1;
5621         }
5622
5623         if (vmx->nested.current_vmptr != vmptr) {
5624                 struct vmcs12 *new_vmcs12;
5625                 struct page *page;
5626                 page = nested_get_page(vcpu, vmptr);
5627                 if (page == NULL) {
5628                         nested_vmx_failInvalid(vcpu);
5629                         skip_emulated_instruction(vcpu);
5630                         return 1;
5631                 }
5632                 new_vmcs12 = kmap(page);
5633                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5634                         kunmap(page);
5635                         nested_release_page_clean(page);
5636                         nested_vmx_failValid(vcpu,
5637                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5638                         skip_emulated_instruction(vcpu);
5639                         return 1;
5640                 }
5641                 if (vmx->nested.current_vmptr != -1ull) {
5642                         kunmap(vmx->nested.current_vmcs12_page);
5643                         nested_release_page(vmx->nested.current_vmcs12_page);
5644                 }
5645
5646                 vmx->nested.current_vmptr = vmptr;
5647                 vmx->nested.current_vmcs12 = new_vmcs12;
5648                 vmx->nested.current_vmcs12_page = page;
5649         }
5650
5651         nested_vmx_succeed(vcpu);
5652         skip_emulated_instruction(vcpu);
5653         return 1;
5654 }
5655
5656 /* Emulate the VMPTRST instruction */
5657 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5658 {
5659         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5660         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5661         gva_t vmcs_gva;
5662         struct x86_exception e;
5663
5664         if (!nested_vmx_check_permission(vcpu))
5665                 return 1;
5666
5667         if (get_vmx_mem_address(vcpu, exit_qualification,
5668                         vmx_instruction_info, &vmcs_gva))
5669                 return 1;
5670         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5671         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5672                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5673                                  sizeof(u64), &e)) {
5674                 kvm_inject_page_fault(vcpu, &e);
5675                 return 1;
5676         }
5677         nested_vmx_succeed(vcpu);
5678         skip_emulated_instruction(vcpu);
5679         return 1;
5680 }
5681
5682 /*
5683  * The exit handlers return 1 if the exit was handled fully and guest execution
5684  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5685  * to be done to userspace and return 0.
5686  */
5687 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5688         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5689         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5690         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5691         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5692         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5693         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5694         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5695         [EXIT_REASON_CPUID]                   = handle_cpuid,
5696         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5697         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5698         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5699         [EXIT_REASON_HLT]                     = handle_halt,
5700         [EXIT_REASON_INVD]                    = handle_invd,
5701         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5702         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5703         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5704         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5705         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5706         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5707         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5708         [EXIT_REASON_VMREAD]                  = handle_vmread,
5709         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5710         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5711         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5712         [EXIT_REASON_VMON]                    = handle_vmon,
5713         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5714         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5715         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5716         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5717         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5718         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5719         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5720         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5721         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5722         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5723         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5724 };
5725
5726 static const int kvm_vmx_max_exit_handlers =
5727         ARRAY_SIZE(kvm_vmx_exit_handlers);
5728
5729 /*
5730  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5731  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5732  * disinterest in the current event (read or write a specific MSR) by using an
5733  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5734  */
5735 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5736         struct vmcs12 *vmcs12, u32 exit_reason)
5737 {
5738         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5739         gpa_t bitmap;
5740
5741         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5742                 return 1;
5743
5744         /*
5745          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5746          * for the four combinations of read/write and low/high MSR numbers.
5747          * First we need to figure out which of the four to use:
5748          */
5749         bitmap = vmcs12->msr_bitmap;
5750         if (exit_reason == EXIT_REASON_MSR_WRITE)
5751                 bitmap += 2048;
5752         if (msr_index >= 0xc0000000) {
5753                 msr_index -= 0xc0000000;
5754                 bitmap += 1024;
5755         }
5756
5757         /* Then read the msr_index'th bit from this bitmap: */
5758         if (msr_index < 1024*8) {
5759                 unsigned char b;
5760                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5761                 return 1 & (b >> (msr_index & 7));
5762         } else
5763                 return 1; /* let L1 handle the wrong parameter */
5764 }
5765
5766 /*
5767  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5768  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5769  * intercept (via guest_host_mask etc.) the current event.
5770  */
5771 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5772         struct vmcs12 *vmcs12)
5773 {
5774         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5775         int cr = exit_qualification & 15;
5776         int reg = (exit_qualification >> 8) & 15;
5777         unsigned long val = kvm_register_read(vcpu, reg);
5778
5779         switch ((exit_qualification >> 4) & 3) {
5780         case 0: /* mov to cr */
5781                 switch (cr) {
5782                 case 0:
5783                         if (vmcs12->cr0_guest_host_mask &
5784                             (val ^ vmcs12->cr0_read_shadow))
5785                                 return 1;
5786                         break;
5787                 case 3:
5788                         if ((vmcs12->cr3_target_count >= 1 &&
5789                                         vmcs12->cr3_target_value0 == val) ||
5790                                 (vmcs12->cr3_target_count >= 2 &&
5791                                         vmcs12->cr3_target_value1 == val) ||
5792                                 (vmcs12->cr3_target_count >= 3 &&
5793                                         vmcs12->cr3_target_value2 == val) ||
5794                                 (vmcs12->cr3_target_count >= 4 &&
5795                                         vmcs12->cr3_target_value3 == val))
5796                                 return 0;
5797                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5798                                 return 1;
5799                         break;
5800                 case 4:
5801                         if (vmcs12->cr4_guest_host_mask &
5802                             (vmcs12->cr4_read_shadow ^ val))
5803                                 return 1;
5804                         break;
5805                 case 8:
5806                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5807                                 return 1;
5808                         break;
5809                 }
5810                 break;
5811         case 2: /* clts */
5812                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5813                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5814                         return 1;
5815                 break;
5816         case 1: /* mov from cr */
5817                 switch (cr) {
5818                 case 3:
5819                         if (vmcs12->cpu_based_vm_exec_control &
5820                             CPU_BASED_CR3_STORE_EXITING)
5821                                 return 1;
5822                         break;
5823                 case 8:
5824                         if (vmcs12->cpu_based_vm_exec_control &
5825                             CPU_BASED_CR8_STORE_EXITING)
5826                                 return 1;
5827                         break;
5828                 }
5829                 break;
5830         case 3: /* lmsw */
5831                 /*
5832                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5833                  * cr0. Other attempted changes are ignored, with no exit.
5834                  */
5835                 if (vmcs12->cr0_guest_host_mask & 0xe &
5836                     (val ^ vmcs12->cr0_read_shadow))
5837                         return 1;
5838                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5839                     !(vmcs12->cr0_read_shadow & 0x1) &&
5840                     (val & 0x1))
5841                         return 1;
5842                 break;
5843         }
5844         return 0;
5845 }
5846
5847 /*
5848  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5849  * should handle it ourselves in L0 (and then continue L2). Only call this
5850  * when in is_guest_mode (L2).
5851  */
5852 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5853 {
5854         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5855         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5856         struct vcpu_vmx *vmx = to_vmx(vcpu);
5857         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5858
5859         if (vmx->nested.nested_run_pending)
5860                 return 0;
5861
5862         if (unlikely(vmx->fail)) {
5863                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5864                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5865                 return 1;
5866         }
5867
5868         switch (exit_reason) {
5869         case EXIT_REASON_EXCEPTION_NMI:
5870                 if (!is_exception(intr_info))
5871                         return 0;
5872                 else if (is_page_fault(intr_info))
5873                         return enable_ept;
5874                 return vmcs12->exception_bitmap &
5875                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5876         case EXIT_REASON_EXTERNAL_INTERRUPT:
5877                 return 0;
5878         case EXIT_REASON_TRIPLE_FAULT:
5879                 return 1;
5880         case EXIT_REASON_PENDING_INTERRUPT:
5881         case EXIT_REASON_NMI_WINDOW:
5882                 /*
5883                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5884                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5885                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5886                  * Same for NMI Window Exiting.
5887                  */
5888                 return 1;
5889         case EXIT_REASON_TASK_SWITCH:
5890                 return 1;
5891         case EXIT_REASON_CPUID:
5892                 return 1;
5893         case EXIT_REASON_HLT:
5894                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5895         case EXIT_REASON_INVD:
5896                 return 1;
5897         case EXIT_REASON_INVLPG:
5898                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5899         case EXIT_REASON_RDPMC:
5900                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5901         case EXIT_REASON_RDTSC:
5902                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5903         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5904         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5905         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5906         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5907         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5908                 /*
5909                  * VMX instructions trap unconditionally. This allows L1 to
5910                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5911                  */
5912                 return 1;
5913         case EXIT_REASON_CR_ACCESS:
5914                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5915         case EXIT_REASON_DR_ACCESS:
5916                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5917         case EXIT_REASON_IO_INSTRUCTION:
5918                 /* TODO: support IO bitmaps */
5919                 return 1;
5920         case EXIT_REASON_MSR_READ:
5921         case EXIT_REASON_MSR_WRITE:
5922                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5923         case EXIT_REASON_INVALID_STATE:
5924                 return 1;
5925         case EXIT_REASON_MWAIT_INSTRUCTION:
5926                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5927         case EXIT_REASON_MONITOR_INSTRUCTION:
5928                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5929         case EXIT_REASON_PAUSE_INSTRUCTION:
5930                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5931                         nested_cpu_has2(vmcs12,
5932                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5933         case EXIT_REASON_MCE_DURING_VMENTRY:
5934                 return 0;
5935         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5936                 return 1;
5937         case EXIT_REASON_APIC_ACCESS:
5938                 return nested_cpu_has2(vmcs12,
5939                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5940         case EXIT_REASON_EPT_VIOLATION:
5941         case EXIT_REASON_EPT_MISCONFIG:
5942                 return 0;
5943         case EXIT_REASON_WBINVD:
5944                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5945         case EXIT_REASON_XSETBV:
5946                 return 1;
5947         default:
5948                 return 1;
5949         }
5950 }
5951
5952 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5953 {
5954         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5955         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5956 }
5957
5958 /*
5959  * The guest has exited.  See if we can fix it or if we need userspace
5960  * assistance.
5961  */
5962 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5963 {
5964         struct vcpu_vmx *vmx = to_vmx(vcpu);
5965         u32 exit_reason = vmx->exit_reason;
5966         u32 vectoring_info = vmx->idt_vectoring_info;
5967
5968         /* If guest state is invalid, start emulating */
5969         if (vmx->emulation_required && emulate_invalid_guest_state)
5970                 return handle_invalid_guest_state(vcpu);
5971
5972         /*
5973          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5974          * we did not inject a still-pending event to L1 now because of
5975          * nested_run_pending, we need to re-enable this bit.
5976          */
5977         if (vmx->nested.nested_run_pending)
5978                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5979
5980         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5981             exit_reason == EXIT_REASON_VMRESUME))
5982                 vmx->nested.nested_run_pending = 1;
5983         else
5984                 vmx->nested.nested_run_pending = 0;
5985
5986         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5987                 nested_vmx_vmexit(vcpu);
5988                 return 1;
5989         }
5990
5991         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5992                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5993                 vcpu->run->fail_entry.hardware_entry_failure_reason
5994                         = exit_reason;
5995                 return 0;
5996         }
5997
5998         if (unlikely(vmx->fail)) {
5999                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6000                 vcpu->run->fail_entry.hardware_entry_failure_reason
6001                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6002                 return 0;
6003         }
6004
6005         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6006                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6007                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6008                         exit_reason != EXIT_REASON_TASK_SWITCH))
6009                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
6010                        "(0x%x) and exit reason is 0x%x\n",
6011                        __func__, vectoring_info, exit_reason);
6012
6013         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6014             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6015                                         get_vmcs12(vcpu), vcpu)))) {
6016                 if (vmx_interrupt_allowed(vcpu)) {
6017                         vmx->soft_vnmi_blocked = 0;
6018                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6019                            vcpu->arch.nmi_pending) {
6020                         /*
6021                          * This CPU don't support us in finding the end of an
6022                          * NMI-blocked window if the guest runs with IRQs
6023                          * disabled. So we pull the trigger after 1 s of
6024                          * futile waiting, but inform the user about this.
6025                          */
6026                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6027                                "state on VCPU %d after 1 s timeout\n",
6028                                __func__, vcpu->vcpu_id);
6029                         vmx->soft_vnmi_blocked = 0;
6030                 }
6031         }
6032
6033         if (exit_reason < kvm_vmx_max_exit_handlers
6034             && kvm_vmx_exit_handlers[exit_reason])
6035                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6036         else {
6037                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6038                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6039         }
6040         return 0;
6041 }
6042
6043 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6044 {
6045         if (irr == -1 || tpr < irr) {
6046                 vmcs_write32(TPR_THRESHOLD, 0);
6047                 return;
6048         }
6049
6050         vmcs_write32(TPR_THRESHOLD, irr);
6051 }
6052
6053 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6054 {
6055         u32 exit_intr_info;
6056
6057         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6058               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6059                 return;
6060
6061         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6062         exit_intr_info = vmx->exit_intr_info;
6063
6064         /* Handle machine checks before interrupts are enabled */
6065         if (is_machine_check(exit_intr_info))
6066                 kvm_machine_check();
6067
6068         /* We need to handle NMIs before interrupts are enabled */
6069         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6070             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6071                 kvm_before_handle_nmi(&vmx->vcpu);
6072                 asm("int $2");
6073                 kvm_after_handle_nmi(&vmx->vcpu);
6074         }
6075 }
6076
6077 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6078 {
6079         u32 exit_intr_info;
6080         bool unblock_nmi;
6081         u8 vector;
6082         bool idtv_info_valid;
6083
6084         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6085
6086         if (cpu_has_virtual_nmis()) {
6087                 if (vmx->nmi_known_unmasked)
6088                         return;
6089                 /*
6090                  * Can't use vmx->exit_intr_info since we're not sure what
6091                  * the exit reason is.
6092                  */
6093                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6094                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6095                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6096                 /*
6097                  * SDM 3: 27.7.1.2 (September 2008)
6098                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6099                  * a guest IRET fault.
6100                  * SDM 3: 23.2.2 (September 2008)
6101                  * Bit 12 is undefined in any of the following cases:
6102                  *  If the VM exit sets the valid bit in the IDT-vectoring
6103                  *   information field.
6104                  *  If the VM exit is due to a double fault.
6105                  */
6106                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6107                     vector != DF_VECTOR && !idtv_info_valid)
6108                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6109                                       GUEST_INTR_STATE_NMI);
6110                 else
6111                         vmx->nmi_known_unmasked =
6112                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6113                                   & GUEST_INTR_STATE_NMI);
6114         } else if (unlikely(vmx->soft_vnmi_blocked))
6115                 vmx->vnmi_blocked_time +=
6116                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6117 }
6118
6119 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6120                                       u32 idt_vectoring_info,
6121                                       int instr_len_field,
6122                                       int error_code_field)
6123 {
6124         u8 vector;
6125         int type;
6126         bool idtv_info_valid;
6127
6128         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6129
6130         vmx->vcpu.arch.nmi_injected = false;
6131         kvm_clear_exception_queue(&vmx->vcpu);
6132         kvm_clear_interrupt_queue(&vmx->vcpu);
6133
6134         if (!idtv_info_valid)
6135                 return;
6136
6137         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6138
6139         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6140         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6141
6142         switch (type) {
6143         case INTR_TYPE_NMI_INTR:
6144                 vmx->vcpu.arch.nmi_injected = true;
6145                 /*
6146                  * SDM 3: 27.7.1.2 (September 2008)
6147                  * Clear bit "block by NMI" before VM entry if a NMI
6148                  * delivery faulted.
6149                  */
6150                 vmx_set_nmi_mask(&vmx->vcpu, false);
6151                 break;
6152         case INTR_TYPE_SOFT_EXCEPTION:
6153                 vmx->vcpu.arch.event_exit_inst_len =
6154                         vmcs_read32(instr_len_field);
6155                 /* fall through */
6156         case INTR_TYPE_HARD_EXCEPTION:
6157                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6158                         u32 err = vmcs_read32(error_code_field);
6159                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6160                 } else
6161                         kvm_queue_exception(&vmx->vcpu, vector);
6162                 break;
6163         case INTR_TYPE_SOFT_INTR:
6164                 vmx->vcpu.arch.event_exit_inst_len =
6165                         vmcs_read32(instr_len_field);
6166                 /* fall through */
6167         case INTR_TYPE_EXT_INTR:
6168                 kvm_queue_interrupt(&vmx->vcpu, vector,
6169                         type == INTR_TYPE_SOFT_INTR);
6170                 break;
6171         default:
6172                 break;
6173         }
6174 }
6175
6176 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6177 {
6178         if (is_guest_mode(&vmx->vcpu))
6179                 return;
6180         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6181                                   VM_EXIT_INSTRUCTION_LEN,
6182                                   IDT_VECTORING_ERROR_CODE);
6183 }
6184
6185 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6186 {
6187         if (is_guest_mode(vcpu))
6188                 return;
6189         __vmx_complete_interrupts(to_vmx(vcpu),
6190                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6191                                   VM_ENTRY_INSTRUCTION_LEN,
6192                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6193
6194         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6195 }
6196
6197 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6198 {
6199         int i, nr_msrs;
6200         struct perf_guest_switch_msr *msrs;
6201
6202         msrs = perf_guest_get_msrs(&nr_msrs);
6203
6204         if (!msrs)
6205                 return;
6206
6207         for (i = 0; i < nr_msrs; i++)
6208                 if (msrs[i].host == msrs[i].guest)
6209                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6210                 else
6211                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6212                                         msrs[i].host);
6213 }
6214
6215 #ifdef CONFIG_X86_64
6216 #define R "r"
6217 #define Q "q"
6218 #else
6219 #define R "e"
6220 #define Q "l"
6221 #endif
6222
6223 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6224 {
6225         struct vcpu_vmx *vmx = to_vmx(vcpu);
6226
6227         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6228                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6229                 if (vmcs12->idt_vectoring_info_field &
6230                                 VECTORING_INFO_VALID_MASK) {
6231                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6232                                 vmcs12->idt_vectoring_info_field);
6233                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6234                                 vmcs12->vm_exit_instruction_len);
6235                         if (vmcs12->idt_vectoring_info_field &
6236                                         VECTORING_INFO_DELIVER_CODE_MASK)
6237                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6238                                         vmcs12->idt_vectoring_error_code);
6239                 }
6240         }
6241
6242         /* Record the guest's net vcpu time for enforced NMI injections. */
6243         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6244                 vmx->entry_time = ktime_get();
6245
6246         /* Don't enter VMX if guest state is invalid, let the exit handler
6247            start emulation until we arrive back to a valid state */
6248         if (vmx->emulation_required && emulate_invalid_guest_state)
6249                 return;
6250
6251         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6252                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6253         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6254                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6255
6256         /* When single-stepping over STI and MOV SS, we must clear the
6257          * corresponding interruptibility bits in the guest state. Otherwise
6258          * vmentry fails as it then expects bit 14 (BS) in pending debug
6259          * exceptions being set, but that's not correct for the guest debugging
6260          * case. */
6261         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6262                 vmx_set_interrupt_shadow(vcpu, 0);
6263
6264         atomic_switch_perf_msrs(vmx);
6265
6266         vmx->__launched = vmx->loaded_vmcs->launched;
6267         asm(
6268                 /* Store host registers */
6269                 "push %%"R"dx; push %%"R"bp;"
6270                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6271                 "push %%"R"cx \n\t"
6272                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6273                 "je 1f \n\t"
6274                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6275                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6276                 "1: \n\t"
6277                 /* Reload cr2 if changed */
6278                 "mov %c[cr2](%0), %%"R"ax \n\t"
6279                 "mov %%cr2, %%"R"dx \n\t"
6280                 "cmp %%"R"ax, %%"R"dx \n\t"
6281                 "je 2f \n\t"
6282                 "mov %%"R"ax, %%cr2 \n\t"
6283                 "2: \n\t"
6284                 /* Check if vmlaunch of vmresume is needed */
6285                 "cmpl $0, %c[launched](%0) \n\t"
6286                 /* Load guest registers.  Don't clobber flags. */
6287                 "mov %c[rax](%0), %%"R"ax \n\t"
6288                 "mov %c[rbx](%0), %%"R"bx \n\t"
6289                 "mov %c[rdx](%0), %%"R"dx \n\t"
6290                 "mov %c[rsi](%0), %%"R"si \n\t"
6291                 "mov %c[rdi](%0), %%"R"di \n\t"
6292                 "mov %c[rbp](%0), %%"R"bp \n\t"
6293 #ifdef CONFIG_X86_64
6294                 "mov %c[r8](%0),  %%r8  \n\t"
6295                 "mov %c[r9](%0),  %%r9  \n\t"
6296                 "mov %c[r10](%0), %%r10 \n\t"
6297                 "mov %c[r11](%0), %%r11 \n\t"
6298                 "mov %c[r12](%0), %%r12 \n\t"
6299                 "mov %c[r13](%0), %%r13 \n\t"
6300                 "mov %c[r14](%0), %%r14 \n\t"
6301                 "mov %c[r15](%0), %%r15 \n\t"
6302 #endif
6303                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6304
6305                 /* Enter guest mode */
6306                 "jne .Llaunched \n\t"
6307                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6308                 "jmp .Lkvm_vmx_return \n\t"
6309                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6310                 ".Lkvm_vmx_return: "
6311                 /* Save guest registers, load host registers, keep flags */
6312                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6313                 "pop %0 \n\t"
6314                 "mov %%"R"ax, %c[rax](%0) \n\t"
6315                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6316                 "pop"Q" %c[rcx](%0) \n\t"
6317                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6318                 "mov %%"R"si, %c[rsi](%0) \n\t"
6319                 "mov %%"R"di, %c[rdi](%0) \n\t"
6320                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6321 #ifdef CONFIG_X86_64
6322                 "mov %%r8,  %c[r8](%0) \n\t"
6323                 "mov %%r9,  %c[r9](%0) \n\t"
6324                 "mov %%r10, %c[r10](%0) \n\t"
6325                 "mov %%r11, %c[r11](%0) \n\t"
6326                 "mov %%r12, %c[r12](%0) \n\t"
6327                 "mov %%r13, %c[r13](%0) \n\t"
6328                 "mov %%r14, %c[r14](%0) \n\t"
6329                 "mov %%r15, %c[r15](%0) \n\t"
6330 #endif
6331                 "mov %%cr2, %%"R"ax   \n\t"
6332                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6333
6334                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6335                 "setbe %c[fail](%0) \n\t"
6336               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6337                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6338                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6339                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6340                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6341                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6342                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6343                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6344                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6345                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6346                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6347 #ifdef CONFIG_X86_64
6348                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6349                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6350                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6351                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6352                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6353                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6354                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6355                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6356 #endif
6357                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6358                 [wordsize]"i"(sizeof(ulong))
6359               : "cc", "memory"
6360                 , R"ax", R"bx", R"di", R"si"
6361 #ifdef CONFIG_X86_64
6362                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6363 #endif
6364               );
6365
6366 #ifndef CONFIG_X86_64
6367         /*
6368          * The sysexit path does not restore ds/es, so we must set them to
6369          * a reasonable value ourselves.
6370          *
6371          * We can't defer this to vmx_load_host_state() since that function
6372          * may be executed in interrupt context, which saves and restore segments
6373          * around it, nullifying its effect.
6374          */
6375         loadsegment(ds, __USER_DS);
6376         loadsegment(es, __USER_DS);
6377 #endif
6378
6379         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6380                                   | (1 << VCPU_EXREG_RFLAGS)
6381                                   | (1 << VCPU_EXREG_CPL)
6382                                   | (1 << VCPU_EXREG_PDPTR)
6383                                   | (1 << VCPU_EXREG_SEGMENTS)
6384                                   | (1 << VCPU_EXREG_CR3));
6385         vcpu->arch.regs_dirty = 0;
6386
6387         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6388
6389         if (is_guest_mode(vcpu)) {
6390                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6391                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6392                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6393                         vmcs12->idt_vectoring_error_code =
6394                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6395                         vmcs12->vm_exit_instruction_len =
6396                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6397                 }
6398         }
6399
6400         vmx->loaded_vmcs->launched = 1;
6401
6402         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6403         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6404
6405         vmx_complete_atomic_exit(vmx);
6406         vmx_recover_nmi_blocking(vmx);
6407         vmx_complete_interrupts(vmx);
6408 }
6409
6410 #undef R
6411 #undef Q
6412
6413 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6414 {
6415         struct vcpu_vmx *vmx = to_vmx(vcpu);
6416
6417         free_vpid(vmx);
6418         free_nested(vmx);
6419         free_loaded_vmcs(vmx->loaded_vmcs);
6420         kfree(vmx->guest_msrs);
6421         kvm_vcpu_uninit(vcpu);
6422         kmem_cache_free(kvm_vcpu_cache, vmx);
6423 }
6424
6425 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6426 {
6427         int err;
6428         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6429         int cpu;
6430
6431         if (!vmx)
6432                 return ERR_PTR(-ENOMEM);
6433
6434         allocate_vpid(vmx);
6435
6436         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6437         if (err)
6438                 goto free_vcpu;
6439
6440         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6441         err = -ENOMEM;
6442         if (!vmx->guest_msrs) {
6443                 goto uninit_vcpu;
6444         }
6445
6446         vmx->loaded_vmcs = &vmx->vmcs01;
6447         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6448         if (!vmx->loaded_vmcs->vmcs)
6449                 goto free_msrs;
6450         if (!vmm_exclusive)
6451                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6452         loaded_vmcs_init(vmx->loaded_vmcs);
6453         if (!vmm_exclusive)
6454                 kvm_cpu_vmxoff();
6455
6456         cpu = get_cpu();
6457         vmx_vcpu_load(&vmx->vcpu, cpu);
6458         vmx->vcpu.cpu = cpu;
6459         err = vmx_vcpu_setup(vmx);
6460         vmx_vcpu_put(&vmx->vcpu);
6461         put_cpu();
6462         if (err)
6463                 goto free_vmcs;
6464         if (vm_need_virtualize_apic_accesses(kvm))
6465                 err = alloc_apic_access_page(kvm);
6466                 if (err)
6467                         goto free_vmcs;
6468
6469         if (enable_ept) {
6470                 if (!kvm->arch.ept_identity_map_addr)
6471                         kvm->arch.ept_identity_map_addr =
6472                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6473                 err = -ENOMEM;
6474                 if (alloc_identity_pagetable(kvm) != 0)
6475                         goto free_vmcs;
6476                 if (!init_rmode_identity_map(kvm))
6477                         goto free_vmcs;
6478         }
6479
6480         vmx->nested.current_vmptr = -1ull;
6481         vmx->nested.current_vmcs12 = NULL;
6482
6483         return &vmx->vcpu;
6484
6485 free_vmcs:
6486         free_loaded_vmcs(vmx->loaded_vmcs);
6487 free_msrs:
6488         kfree(vmx->guest_msrs);
6489 uninit_vcpu:
6490         kvm_vcpu_uninit(&vmx->vcpu);
6491 free_vcpu:
6492         free_vpid(vmx);
6493         kmem_cache_free(kvm_vcpu_cache, vmx);
6494         return ERR_PTR(err);
6495 }
6496
6497 static void __init vmx_check_processor_compat(void *rtn)
6498 {
6499         struct vmcs_config vmcs_conf;
6500
6501         *(int *)rtn = 0;
6502         if (setup_vmcs_config(&vmcs_conf) < 0)
6503                 *(int *)rtn = -EIO;
6504         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6505                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6506                                 smp_processor_id());
6507                 *(int *)rtn = -EIO;
6508         }
6509 }
6510
6511 static int get_ept_level(void)
6512 {
6513         return VMX_EPT_DEFAULT_GAW + 1;
6514 }
6515
6516 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6517 {
6518         u64 ret;
6519
6520         /* For VT-d and EPT combination
6521          * 1. MMIO: always map as UC
6522          * 2. EPT with VT-d:
6523          *   a. VT-d without snooping control feature: can't guarantee the
6524          *      result, try to trust guest.
6525          *   b. VT-d with snooping control feature: snooping control feature of
6526          *      VT-d engine can guarantee the cache correctness. Just set it
6527          *      to WB to keep consistent with host. So the same as item 3.
6528          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6529          *    consistent with host MTRR
6530          */
6531         if (is_mmio)
6532                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6533         else if (vcpu->kvm->arch.iommu_domain &&
6534                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6535                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6536                       VMX_EPT_MT_EPTE_SHIFT;
6537         else
6538                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6539                         | VMX_EPT_IPAT_BIT;
6540
6541         return ret;
6542 }
6543
6544 static int vmx_get_lpage_level(void)
6545 {
6546         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6547                 return PT_DIRECTORY_LEVEL;
6548         else
6549                 /* For shadow and EPT supported 1GB page */
6550                 return PT_PDPE_LEVEL;
6551 }
6552
6553 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6554 {
6555         struct kvm_cpuid_entry2 *best;
6556         struct vcpu_vmx *vmx = to_vmx(vcpu);
6557         u32 exec_control;
6558
6559         vmx->rdtscp_enabled = false;
6560         if (vmx_rdtscp_supported()) {
6561                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6562                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6563                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6564                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6565                                 vmx->rdtscp_enabled = true;
6566                         else {
6567                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6568                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6569                                                 exec_control);
6570                         }
6571                 }
6572         }
6573
6574         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6575         /* Exposing INVPCID only when PCID is exposed */
6576         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6577         if (vmx_invpcid_supported() &&
6578             best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
6579             guest_cpuid_has_pcid(vcpu)) {
6580                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6581                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6582                              exec_control);
6583         } else {
6584                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6585                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6586                              exec_control);
6587                 if (best)
6588                         best->ecx &= ~bit(X86_FEATURE_INVPCID);
6589         }
6590 }
6591
6592 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6593 {
6594         if (func == 1 && nested)
6595                 entry->ecx |= bit(X86_FEATURE_VMX);
6596 }
6597
6598 /*
6599  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6600  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6601  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6602  * guest in a way that will both be appropriate to L1's requests, and our
6603  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6604  * function also has additional necessary side-effects, like setting various
6605  * vcpu->arch fields.
6606  */
6607 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6608 {
6609         struct vcpu_vmx *vmx = to_vmx(vcpu);
6610         u32 exec_control;
6611
6612         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6613         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6614         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6615         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6616         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6617         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6618         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6619         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6620         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6621         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6622         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6623         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6624         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6625         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6626         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6627         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6628         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6629         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6630         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6631         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6632         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6633         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6634         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6635         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6636         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6637         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6638         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6639         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6640         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6641         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6642         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6643         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6644         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6645         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6646         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6647         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6648
6649         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6650         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6651                 vmcs12->vm_entry_intr_info_field);
6652         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6653                 vmcs12->vm_entry_exception_error_code);
6654         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6655                 vmcs12->vm_entry_instruction_len);
6656         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6657                 vmcs12->guest_interruptibility_info);
6658         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6659         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6660         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6661         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6662         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6663                 vmcs12->guest_pending_dbg_exceptions);
6664         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6665         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6666
6667         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6668
6669         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6670                 (vmcs_config.pin_based_exec_ctrl |
6671                  vmcs12->pin_based_vm_exec_control));
6672
6673         /*
6674          * Whether page-faults are trapped is determined by a combination of
6675          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6676          * If enable_ept, L0 doesn't care about page faults and we should
6677          * set all of these to L1's desires. However, if !enable_ept, L0 does
6678          * care about (at least some) page faults, and because it is not easy
6679          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6680          * to exit on each and every L2 page fault. This is done by setting
6681          * MASK=MATCH=0 and (see below) EB.PF=1.
6682          * Note that below we don't need special code to set EB.PF beyond the
6683          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6684          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6685          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6686          *
6687          * A problem with this approach (when !enable_ept) is that L1 may be
6688          * injected with more page faults than it asked for. This could have
6689          * caused problems, but in practice existing hypervisors don't care.
6690          * To fix this, we will need to emulate the PFEC checking (on the L1
6691          * page tables), using walk_addr(), when injecting PFs to L1.
6692          */
6693         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6694                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6695         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6696                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6697
6698         if (cpu_has_secondary_exec_ctrls()) {
6699                 u32 exec_control = vmx_secondary_exec_control(vmx);
6700                 if (!vmx->rdtscp_enabled)
6701                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6702                 /* Take the following fields only from vmcs12 */
6703                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6704                 if (nested_cpu_has(vmcs12,
6705                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6706                         exec_control |= vmcs12->secondary_vm_exec_control;
6707
6708                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6709                         /*
6710                          * Translate L1 physical address to host physical
6711                          * address for vmcs02. Keep the page pinned, so this
6712                          * physical address remains valid. We keep a reference
6713                          * to it so we can release it later.
6714                          */
6715                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6716                                 nested_release_page(vmx->nested.apic_access_page);
6717                         vmx->nested.apic_access_page =
6718                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6719                         /*
6720                          * If translation failed, no matter: This feature asks
6721                          * to exit when accessing the given address, and if it
6722                          * can never be accessed, this feature won't do
6723                          * anything anyway.
6724                          */
6725                         if (!vmx->nested.apic_access_page)
6726                                 exec_control &=
6727                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6728                         else
6729                                 vmcs_write64(APIC_ACCESS_ADDR,
6730                                   page_to_phys(vmx->nested.apic_access_page));
6731                 }
6732
6733                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6734         }
6735
6736
6737         /*
6738          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6739          * Some constant fields are set here by vmx_set_constant_host_state().
6740          * Other fields are different per CPU, and will be set later when
6741          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6742          */
6743         vmx_set_constant_host_state();
6744
6745         /*
6746          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6747          * entry, but only if the current (host) sp changed from the value
6748          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6749          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6750          * here we just force the write to happen on entry.
6751          */
6752         vmx->host_rsp = 0;
6753
6754         exec_control = vmx_exec_control(vmx); /* L0's desires */
6755         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6756         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6757         exec_control &= ~CPU_BASED_TPR_SHADOW;
6758         exec_control |= vmcs12->cpu_based_vm_exec_control;
6759         /*
6760          * Merging of IO and MSR bitmaps not currently supported.
6761          * Rather, exit every time.
6762          */
6763         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6764         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6765         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6766
6767         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6768
6769         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6770          * bitwise-or of what L1 wants to trap for L2, and what we want to
6771          * trap. Note that CR0.TS also needs updating - we do this later.
6772          */
6773         update_exception_bitmap(vcpu);
6774         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6775         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6776
6777         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6778         vmcs_write32(VM_EXIT_CONTROLS,
6779                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6780         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6781                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6782
6783         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6784                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6785         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6786                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6787
6788
6789         set_cr4_guest_host_mask(vmx);
6790
6791         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6792                 vmcs_write64(TSC_OFFSET,
6793                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6794         else
6795                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6796
6797         if (enable_vpid) {
6798                 /*
6799                  * Trivially support vpid by letting L2s share their parent
6800                  * L1's vpid. TODO: move to a more elaborate solution, giving
6801                  * each L2 its own vpid and exposing the vpid feature to L1.
6802                  */
6803                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6804                 vmx_flush_tlb(vcpu);
6805         }
6806
6807         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6808                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6809         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6810                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6811         else
6812                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6813         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6814         vmx_set_efer(vcpu, vcpu->arch.efer);
6815
6816         /*
6817          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6818          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6819          * The CR0_READ_SHADOW is what L2 should have expected to read given
6820          * the specifications by L1; It's not enough to take
6821          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6822          * have more bits than L1 expected.
6823          */
6824         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6825         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6826
6827         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6828         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6829
6830         /* shadow page tables on either EPT or shadow page tables */
6831         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6832         kvm_mmu_reset_context(vcpu);
6833
6834         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6835         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6836 }
6837
6838 /*
6839  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6840  * for running an L2 nested guest.
6841  */
6842 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6843 {
6844         struct vmcs12 *vmcs12;
6845         struct vcpu_vmx *vmx = to_vmx(vcpu);
6846         int cpu;
6847         struct loaded_vmcs *vmcs02;
6848
6849         if (!nested_vmx_check_permission(vcpu) ||
6850             !nested_vmx_check_vmcs12(vcpu))
6851                 return 1;
6852
6853         skip_emulated_instruction(vcpu);
6854         vmcs12 = get_vmcs12(vcpu);
6855
6856         /*
6857          * The nested entry process starts with enforcing various prerequisites
6858          * on vmcs12 as required by the Intel SDM, and act appropriately when
6859          * they fail: As the SDM explains, some conditions should cause the
6860          * instruction to fail, while others will cause the instruction to seem
6861          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6862          * To speed up the normal (success) code path, we should avoid checking
6863          * for misconfigurations which will anyway be caught by the processor
6864          * when using the merged vmcs02.
6865          */
6866         if (vmcs12->launch_state == launch) {
6867                 nested_vmx_failValid(vcpu,
6868                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6869                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6870                 return 1;
6871         }
6872
6873         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6874                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6875                 /*TODO: Also verify bits beyond physical address width are 0*/
6876                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6877                 return 1;
6878         }
6879
6880         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6881                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6882                 /*TODO: Also verify bits beyond physical address width are 0*/
6883                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6884                 return 1;
6885         }
6886
6887         if (vmcs12->vm_entry_msr_load_count > 0 ||
6888             vmcs12->vm_exit_msr_load_count > 0 ||
6889             vmcs12->vm_exit_msr_store_count > 0) {
6890                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6891                                     __func__);
6892                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6893                 return 1;
6894         }
6895
6896         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6897               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6898             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6899               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6900             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6901               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6902             !vmx_control_verify(vmcs12->vm_exit_controls,
6903               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6904             !vmx_control_verify(vmcs12->vm_entry_controls,
6905               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6906         {
6907                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6908                 return 1;
6909         }
6910
6911         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6912             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6913                 nested_vmx_failValid(vcpu,
6914                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6915                 return 1;
6916         }
6917
6918         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6919             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6920                 nested_vmx_entry_failure(vcpu, vmcs12,
6921                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6922                 return 1;
6923         }
6924         if (vmcs12->vmcs_link_pointer != -1ull) {
6925                 nested_vmx_entry_failure(vcpu, vmcs12,
6926                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6927                 return 1;
6928         }
6929
6930         /*
6931          * We're finally done with prerequisite checking, and can start with
6932          * the nested entry.
6933          */
6934
6935         vmcs02 = nested_get_current_vmcs02(vmx);
6936         if (!vmcs02)
6937                 return -ENOMEM;
6938
6939         enter_guest_mode(vcpu);
6940
6941         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6942
6943         cpu = get_cpu();
6944         vmx->loaded_vmcs = vmcs02;
6945         vmx_vcpu_put(vcpu);
6946         vmx_vcpu_load(vcpu, cpu);
6947         vcpu->cpu = cpu;
6948         put_cpu();
6949
6950         vmcs12->launch_state = 1;
6951
6952         prepare_vmcs02(vcpu, vmcs12);
6953
6954         /*
6955          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6956          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6957          * returned as far as L1 is concerned. It will only return (and set
6958          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6959          */
6960         return 1;
6961 }
6962
6963 /*
6964  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6965  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6966  * This function returns the new value we should put in vmcs12.guest_cr0.
6967  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6968  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6969  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6970  *     didn't trap the bit, because if L1 did, so would L0).
6971  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6972  *     been modified by L2, and L1 knows it. So just leave the old value of
6973  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6974  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6975  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6976  *     changed these bits, and therefore they need to be updated, but L0
6977  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6978  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6979  */
6980 static inline unsigned long
6981 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6982 {
6983         return
6984         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6985         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6986         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6987                         vcpu->arch.cr0_guest_owned_bits));
6988 }
6989
6990 static inline unsigned long
6991 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6992 {
6993         return
6994         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6995         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6996         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6997                         vcpu->arch.cr4_guest_owned_bits));
6998 }
6999
7000 /*
7001  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7002  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7003  * and this function updates it to reflect the changes to the guest state while
7004  * L2 was running (and perhaps made some exits which were handled directly by L0
7005  * without going back to L1), and to reflect the exit reason.
7006  * Note that we do not have to copy here all VMCS fields, just those that
7007  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7008  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7009  * which already writes to vmcs12 directly.
7010  */
7011 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7012 {
7013         /* update guest state fields: */
7014         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7015         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7016
7017         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7018         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7019         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7020         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7021
7022         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7023         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7024         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7025         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7026         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7027         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7028         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7029         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7030         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7031         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7032         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7033         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7034         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7035         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7036         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7037         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7038         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7039         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7040         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7041         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7042         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7043         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7044         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7045         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7046         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7047         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7048         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7049         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7050         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7051         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7052         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7053         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7054         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7055         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7056         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7057         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7058
7059         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7060         vmcs12->guest_interruptibility_info =
7061                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7062         vmcs12->guest_pending_dbg_exceptions =
7063                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7064
7065         /* TODO: These cannot have changed unless we have MSR bitmaps and
7066          * the relevant bit asks not to trap the change */
7067         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7068         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7069                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7070         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7071         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7072         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7073
7074         /* update exit information fields: */
7075
7076         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7077         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7078
7079         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7080         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7081         vmcs12->idt_vectoring_info_field =
7082                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7083         vmcs12->idt_vectoring_error_code =
7084                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7085         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7086         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7087
7088         /* clear vm-entry fields which are to be cleared on exit */
7089         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7090                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7091 }
7092
7093 /*
7094  * A part of what we need to when the nested L2 guest exits and we want to
7095  * run its L1 parent, is to reset L1's guest state to the host state specified
7096  * in vmcs12.
7097  * This function is to be called not only on normal nested exit, but also on
7098  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7099  * Failures During or After Loading Guest State").
7100  * This function should be called when the active VMCS is L1's (vmcs01).
7101  */
7102 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7103 {
7104         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7105                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7106         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7107                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7108         else
7109                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7110         vmx_set_efer(vcpu, vcpu->arch.efer);
7111
7112         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7113         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7114         /*
7115          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7116          * actually changed, because it depends on the current state of
7117          * fpu_active (which may have changed).
7118          * Note that vmx_set_cr0 refers to efer set above.
7119          */
7120         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7121         /*
7122          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7123          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7124          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7125          */
7126         update_exception_bitmap(vcpu);
7127         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7128         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7129
7130         /*
7131          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7132          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7133          */
7134         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7135         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7136
7137         /* shadow page tables on either EPT or shadow page tables */
7138         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7139         kvm_mmu_reset_context(vcpu);
7140
7141         if (enable_vpid) {
7142                 /*
7143                  * Trivially support vpid by letting L2s share their parent
7144                  * L1's vpid. TODO: move to a more elaborate solution, giving
7145                  * each L2 its own vpid and exposing the vpid feature to L1.
7146                  */
7147                 vmx_flush_tlb(vcpu);
7148         }
7149
7150
7151         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7152         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7153         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7154         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7155         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7156         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7157         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7158         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7159         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7160         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7161         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7162         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7163         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7164         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7165         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7166
7167         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7168                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7169         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7170                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7171                         vmcs12->host_ia32_perf_global_ctrl);
7172 }
7173
7174 /*
7175  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7176  * and modify vmcs12 to make it see what it would expect to see there if
7177  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7178  */
7179 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7180 {
7181         struct vcpu_vmx *vmx = to_vmx(vcpu);
7182         int cpu;
7183         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7184
7185         leave_guest_mode(vcpu);
7186         prepare_vmcs12(vcpu, vmcs12);
7187
7188         cpu = get_cpu();
7189         vmx->loaded_vmcs = &vmx->vmcs01;
7190         vmx_vcpu_put(vcpu);
7191         vmx_vcpu_load(vcpu, cpu);
7192         vcpu->cpu = cpu;
7193         put_cpu();
7194
7195         /* if no vmcs02 cache requested, remove the one we used */
7196         if (VMCS02_POOL_SIZE == 0)
7197                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7198
7199         load_vmcs12_host_state(vcpu, vmcs12);
7200
7201         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7202         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7203
7204         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7205         vmx->host_rsp = 0;
7206
7207         /* Unpin physical memory we referred to in vmcs02 */
7208         if (vmx->nested.apic_access_page) {
7209                 nested_release_page(vmx->nested.apic_access_page);
7210                 vmx->nested.apic_access_page = 0;
7211         }
7212
7213         /*
7214          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7215          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7216          * success or failure flag accordingly.
7217          */
7218         if (unlikely(vmx->fail)) {
7219                 vmx->fail = 0;
7220                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7221         } else
7222                 nested_vmx_succeed(vcpu);
7223 }
7224
7225 /*
7226  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7227  * 23.7 "VM-entry failures during or after loading guest state" (this also
7228  * lists the acceptable exit-reason and exit-qualification parameters).
7229  * It should only be called before L2 actually succeeded to run, and when
7230  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7231  */
7232 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7233                         struct vmcs12 *vmcs12,
7234                         u32 reason, unsigned long qualification)
7235 {
7236         load_vmcs12_host_state(vcpu, vmcs12);
7237         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7238         vmcs12->exit_qualification = qualification;
7239         nested_vmx_succeed(vcpu);
7240 }
7241
7242 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7243                                struct x86_instruction_info *info,
7244                                enum x86_intercept_stage stage)
7245 {
7246         return X86EMUL_CONTINUE;
7247 }
7248
7249 static struct kvm_x86_ops vmx_x86_ops = {
7250         .cpu_has_kvm_support = cpu_has_kvm_support,
7251         .disabled_by_bios = vmx_disabled_by_bios,
7252         .hardware_setup = hardware_setup,
7253         .hardware_unsetup = hardware_unsetup,
7254         .check_processor_compatibility = vmx_check_processor_compat,
7255         .hardware_enable = hardware_enable,
7256         .hardware_disable = hardware_disable,
7257         .cpu_has_accelerated_tpr = report_flexpriority,
7258
7259         .vcpu_create = vmx_create_vcpu,
7260         .vcpu_free = vmx_free_vcpu,
7261         .vcpu_reset = vmx_vcpu_reset,
7262
7263         .prepare_guest_switch = vmx_save_host_state,
7264         .vcpu_load = vmx_vcpu_load,
7265         .vcpu_put = vmx_vcpu_put,
7266
7267         .set_guest_debug = set_guest_debug,
7268         .get_msr = vmx_get_msr,
7269         .set_msr = vmx_set_msr,
7270         .get_segment_base = vmx_get_segment_base,
7271         .get_segment = vmx_get_segment,
7272         .set_segment = vmx_set_segment,
7273         .get_cpl = vmx_get_cpl,
7274         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7275         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7276         .decache_cr3 = vmx_decache_cr3,
7277         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7278         .set_cr0 = vmx_set_cr0,
7279         .set_cr3 = vmx_set_cr3,
7280         .set_cr4 = vmx_set_cr4,
7281         .set_efer = vmx_set_efer,
7282         .get_idt = vmx_get_idt,
7283         .set_idt = vmx_set_idt,
7284         .get_gdt = vmx_get_gdt,
7285         .set_gdt = vmx_set_gdt,
7286         .set_dr7 = vmx_set_dr7,
7287         .cache_reg = vmx_cache_reg,
7288         .get_rflags = vmx_get_rflags,
7289         .set_rflags = vmx_set_rflags,
7290         .fpu_activate = vmx_fpu_activate,
7291         .fpu_deactivate = vmx_fpu_deactivate,
7292
7293         .tlb_flush = vmx_flush_tlb,
7294
7295         .run = vmx_vcpu_run,
7296         .handle_exit = vmx_handle_exit,
7297         .skip_emulated_instruction = skip_emulated_instruction,
7298         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7299         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7300         .patch_hypercall = vmx_patch_hypercall,
7301         .set_irq = vmx_inject_irq,
7302         .set_nmi = vmx_inject_nmi,
7303         .queue_exception = vmx_queue_exception,
7304         .cancel_injection = vmx_cancel_injection,
7305         .interrupt_allowed = vmx_interrupt_allowed,
7306         .nmi_allowed = vmx_nmi_allowed,
7307         .get_nmi_mask = vmx_get_nmi_mask,
7308         .set_nmi_mask = vmx_set_nmi_mask,
7309         .enable_nmi_window = enable_nmi_window,
7310         .enable_irq_window = enable_irq_window,
7311         .update_cr8_intercept = update_cr8_intercept,
7312
7313         .set_tss_addr = vmx_set_tss_addr,
7314         .get_tdp_level = get_ept_level,
7315         .get_mt_mask = vmx_get_mt_mask,
7316
7317         .get_exit_info = vmx_get_exit_info,
7318
7319         .get_lpage_level = vmx_get_lpage_level,
7320
7321         .cpuid_update = vmx_cpuid_update,
7322
7323         .rdtscp_supported = vmx_rdtscp_supported,
7324         .invpcid_supported = vmx_invpcid_supported,
7325
7326         .set_supported_cpuid = vmx_set_supported_cpuid,
7327
7328         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7329
7330         .set_tsc_khz = vmx_set_tsc_khz,
7331         .write_tsc_offset = vmx_write_tsc_offset,
7332         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7333         .compute_tsc_offset = vmx_compute_tsc_offset,
7334         .read_l1_tsc = vmx_read_l1_tsc,
7335
7336         .set_tdp_cr3 = vmx_set_cr3,
7337
7338         .check_intercept = vmx_check_intercept,
7339 };
7340
7341 static int __init vmx_init(void)
7342 {
7343         int r, i;
7344
7345         rdmsrl_safe(MSR_EFER, &host_efer);
7346
7347         for (i = 0; i < NR_VMX_MSR; ++i)
7348                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7349
7350         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7351         if (!vmx_io_bitmap_a)
7352                 return -ENOMEM;
7353
7354         r = -ENOMEM;
7355
7356         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7357         if (!vmx_io_bitmap_b)
7358                 goto out;
7359
7360         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7361         if (!vmx_msr_bitmap_legacy)
7362                 goto out1;
7363
7364
7365         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7366         if (!vmx_msr_bitmap_longmode)
7367                 goto out2;
7368
7369
7370         /*
7371          * Allow direct access to the PC debug port (it is often used for I/O
7372          * delays, but the vmexits simply slow things down).
7373          */
7374         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7375         clear_bit(0x80, vmx_io_bitmap_a);
7376
7377         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7378
7379         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7380         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7381
7382         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7383
7384         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7385                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7386         if (r)
7387                 goto out3;
7388
7389         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7390         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7391         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7392         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7393         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7394         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7395
7396         if (enable_ept) {
7397                 kvm_mmu_set_mask_ptes(0ull,
7398                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7399                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7400                         0ull, VMX_EPT_EXECUTABLE_MASK);
7401                 ept_set_mmio_spte_mask();
7402                 kvm_enable_tdp();
7403         } else
7404                 kvm_disable_tdp();
7405
7406         return 0;
7407
7408 out3:
7409         free_page((unsigned long)vmx_msr_bitmap_longmode);
7410 out2:
7411         free_page((unsigned long)vmx_msr_bitmap_legacy);
7412 out1:
7413         free_page((unsigned long)vmx_io_bitmap_b);
7414 out:
7415         free_page((unsigned long)vmx_io_bitmap_a);
7416         return r;
7417 }
7418
7419 static void __exit vmx_exit(void)
7420 {
7421         free_page((unsigned long)vmx_msr_bitmap_legacy);
7422         free_page((unsigned long)vmx_msr_bitmap_longmode);
7423         free_page((unsigned long)vmx_io_bitmap_b);
7424         free_page((unsigned long)vmx_io_bitmap_a);
7425
7426         kvm_exit();
7427 }
7428
7429 module_init(vmx_init)
7430 module_exit(vmx_exit)