arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49
  50 #include "trace.h"
  51
  52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  53 #define __ex_clear(x, reg) \
  54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  55
  56 MODULE_AUTHOR("Qumranet");
  57 MODULE_LICENSE("GPL");
  58
  59 static const struct x86_cpu_id vmx_cpu_id[] = {
  60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  61         {}
  62 };
  63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  64
  65 static bool __read_mostly enable_vpid = 1;
  66 module_param_named(vpid, enable_vpid, bool, 0444);
  67
  68 static bool __read_mostly flexpriority_enabled = 1;
  69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_ept = 1;
  72 module_param_named(ept, enable_ept, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_unrestricted_guest = 1;
  75 module_param_named(unrestricted_guest,
  76                         enable_unrestricted_guest, bool, S_IRUGO);
  77
  78 static bool __read_mostly enable_ept_ad_bits = 1;
  79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  80
  81 static bool __read_mostly emulate_invalid_guest_state = true;
  82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  83
  84 static bool __read_mostly vmm_exclusive = 1;
  85 module_param(vmm_exclusive, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 110 #define KVM_VM_CR0_ALWAYS_ON                                            \
 111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 115
 116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 118
 119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 120
 121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 122
 123 /*
 124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 125  * ple_gap:    upper bound on the amount of time between two successive
 126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 127  *             According to test, this time is usually smaller than 128 cycles.
 128  * ple_window: upper bound on the amount of time a guest is allowed to execute
 129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 130  *             less than 2^12 cycles
 131  * Time is measured based on a counter that runs at the same rate as the TSC,
 132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 133  */
 134 #define KVM_VMX_DEFAULT_PLE_GAP           128
 135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 140
 141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 142 module_param(ple_gap, int, S_IRUGO);
 143
 144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 145 module_param(ple_window, int, S_IRUGO);
 146
 147 /* Default doubles per-vcpu window every exit. */
 148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 149 module_param(ple_window_grow, int, S_IRUGO);
 150
 151 /* Default resets per-vcpu window every exit to ple_window. */
 152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 153 module_param(ple_window_shrink, int, S_IRUGO);
 154
 155 /* Default is to compute the maximum so we can never overflow. */
 156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 158 module_param(ple_window_max, int, S_IRUGO);
 159
 160 extern const ulong vmx_return;
 161
 162 #define NR_AUTOLOAD_MSRS 8
 163 #define VMCS02_POOL_SIZE 1
 164
 165 struct vmcs {
 166         u32 revision_id;
 167         u32 abort;
 168         char data[0];
 169 };
 170
 171 /*
 172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 174  * loaded on this CPU (so we can clear them if the CPU goes down).
 175  */
 176 struct loaded_vmcs {
 177         struct vmcs *vmcs;
 178         int cpu;
 179         int launched;
 180         struct list_head loaded_vmcss_on_cpu_link;
 181 };
 182
 183 struct shared_msr_entry {
 184         unsigned index;
 185         u64 data;
 186         u64 mask;
 187 };
 188
 189 /*
 190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 197  * underlying hardware which will be used to run L2.
 198  * This structure is packed to ensure that its layout is identical across
 199  * machines (necessary for live migration).
 200  * If there are changes in this struct, VMCS12_REVISION must be changed.
 201  */
 202 typedef u64 natural_width;
 203 struct __packed vmcs12 {
 204         /* According to the Intel spec, a VMCS region must start with the
 205          * following two fields. Then follow implementation-specific data.
 206          */
 207         u32 revision_id;
 208         u32 abort;
 209
 210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 211         u32 padding[7]; /* room for future expansion */
 212
 213         u64 io_bitmap_a;
 214         u64 io_bitmap_b;
 215         u64 msr_bitmap;
 216         u64 vm_exit_msr_store_addr;
 217         u64 vm_exit_msr_load_addr;
 218         u64 vm_entry_msr_load_addr;
 219         u64 tsc_offset;
 220         u64 virtual_apic_page_addr;
 221         u64 apic_access_addr;
 222         u64 posted_intr_desc_addr;
 223         u64 ept_pointer;
 224         u64 eoi_exit_bitmap0;
 225         u64 eoi_exit_bitmap1;
 226         u64 eoi_exit_bitmap2;
 227         u64 eoi_exit_bitmap3;
 228         u64 xss_exit_bitmap;
 229         u64 guest_physical_address;
 230         u64 vmcs_link_pointer;
 231         u64 guest_ia32_debugctl;
 232         u64 guest_ia32_pat;
 233         u64 guest_ia32_efer;
 234         u64 guest_ia32_perf_global_ctrl;
 235         u64 guest_pdptr0;
 236         u64 guest_pdptr1;
 237         u64 guest_pdptr2;
 238         u64 guest_pdptr3;
 239         u64 guest_bndcfgs;
 240         u64 host_ia32_pat;
 241         u64 host_ia32_efer;
 242         u64 host_ia32_perf_global_ctrl;
 243         u64 padding64[8]; /* room for future expansion */
 244         /*
 245          * To allow migration of L1 (complete with its L2 guests) between
 246          * machines of different natural widths (32 or 64 bit), we cannot have
 247          * unsigned long fields with no explict size. We use u64 (aliased
 248          * natural_width) instead. Luckily, x86 is little-endian.
 249          */
 250         natural_width cr0_guest_host_mask;
 251         natural_width cr4_guest_host_mask;
 252         natural_width cr0_read_shadow;
 253         natural_width cr4_read_shadow;
 254         natural_width cr3_target_value0;
 255         natural_width cr3_target_value1;
 256         natural_width cr3_target_value2;
 257         natural_width cr3_target_value3;
 258         natural_width exit_qualification;
 259         natural_width guest_linear_address;
 260         natural_width guest_cr0;
 261         natural_width guest_cr3;
 262         natural_width guest_cr4;
 263         natural_width guest_es_base;
 264         natural_width guest_cs_base;
 265         natural_width guest_ss_base;
 266         natural_width guest_ds_base;
 267         natural_width guest_fs_base;
 268         natural_width guest_gs_base;
 269         natural_width guest_ldtr_base;
 270         natural_width guest_tr_base;
 271         natural_width guest_gdtr_base;
 272         natural_width guest_idtr_base;
 273         natural_width guest_dr7;
 274         natural_width guest_rsp;
 275         natural_width guest_rip;
 276         natural_width guest_rflags;
 277         natural_width guest_pending_dbg_exceptions;
 278         natural_width guest_sysenter_esp;
 279         natural_width guest_sysenter_eip;
 280         natural_width host_cr0;
 281         natural_width host_cr3;
 282         natural_width host_cr4;
 283         natural_width host_fs_base;
 284         natural_width host_gs_base;
 285         natural_width host_tr_base;
 286         natural_width host_gdtr_base;
 287         natural_width host_idtr_base;
 288         natural_width host_ia32_sysenter_esp;
 289         natural_width host_ia32_sysenter_eip;
 290         natural_width host_rsp;
 291         natural_width host_rip;
 292         natural_width paddingl[8]; /* room for future expansion */
 293         u32 pin_based_vm_exec_control;
 294         u32 cpu_based_vm_exec_control;
 295         u32 exception_bitmap;
 296         u32 page_fault_error_code_mask;
 297         u32 page_fault_error_code_match;
 298         u32 cr3_target_count;
 299         u32 vm_exit_controls;
 300         u32 vm_exit_msr_store_count;
 301         u32 vm_exit_msr_load_count;
 302         u32 vm_entry_controls;
 303         u32 vm_entry_msr_load_count;
 304         u32 vm_entry_intr_info_field;
 305         u32 vm_entry_exception_error_code;
 306         u32 vm_entry_instruction_len;
 307         u32 tpr_threshold;
 308         u32 secondary_vm_exec_control;
 309         u32 vm_instruction_error;
 310         u32 vm_exit_reason;
 311         u32 vm_exit_intr_info;
 312         u32 vm_exit_intr_error_code;
 313         u32 idt_vectoring_info_field;
 314         u32 idt_vectoring_error_code;
 315         u32 vm_exit_instruction_len;
 316         u32 vmx_instruction_info;
 317         u32 guest_es_limit;
 318         u32 guest_cs_limit;
 319         u32 guest_ss_limit;
 320         u32 guest_ds_limit;
 321         u32 guest_fs_limit;
 322         u32 guest_gs_limit;
 323         u32 guest_ldtr_limit;
 324         u32 guest_tr_limit;
 325         u32 guest_gdtr_limit;
 326         u32 guest_idtr_limit;
 327         u32 guest_es_ar_bytes;
 328         u32 guest_cs_ar_bytes;
 329         u32 guest_ss_ar_bytes;
 330         u32 guest_ds_ar_bytes;
 331         u32 guest_fs_ar_bytes;
 332         u32 guest_gs_ar_bytes;
 333         u32 guest_ldtr_ar_bytes;
 334         u32 guest_tr_ar_bytes;
 335         u32 guest_interruptibility_info;
 336         u32 guest_activity_state;
 337         u32 guest_sysenter_cs;
 338         u32 host_ia32_sysenter_cs;
 339         u32 vmx_preemption_timer_value;
 340         u32 padding32[7]; /* room for future expansion */
 341         u16 virtual_processor_id;
 342         u16 posted_intr_nv;
 343         u16 guest_es_selector;
 344         u16 guest_cs_selector;
 345         u16 guest_ss_selector;
 346         u16 guest_ds_selector;
 347         u16 guest_fs_selector;
 348         u16 guest_gs_selector;
 349         u16 guest_ldtr_selector;
 350         u16 guest_tr_selector;
 351         u16 guest_intr_status;
 352         u16 host_es_selector;
 353         u16 host_cs_selector;
 354         u16 host_ss_selector;
 355         u16 host_ds_selector;
 356         u16 host_fs_selector;
 357         u16 host_gs_selector;
 358         u16 host_tr_selector;
 359 };
 360
 361 /*
 362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 365  */
 366 #define VMCS12_REVISION 0x11e57ed0
 367
 368 /*
 369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 371  * current implementation, 4K are reserved to avoid future complications.
 372  */
 373 #define VMCS12_SIZE 0x1000
 374
 375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 376 struct vmcs02_list {
 377         struct list_head list;
 378         gpa_t vmptr;
 379         struct loaded_vmcs vmcs02;
 380 };
 381
 382 /*
 383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 385  */
 386 struct nested_vmx {
 387         /* Has the level1 guest done vmxon? */
 388         bool vmxon;
 389         gpa_t vmxon_ptr;
 390
 391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 392         gpa_t current_vmptr;
 393         /* The host-usable pointer to the above */
 394         struct page *current_vmcs12_page;
 395         struct vmcs12 *current_vmcs12;
 396         struct vmcs *current_shadow_vmcs;
 397         /*
 398          * Indicates if the shadow vmcs must be updated with the
 399          * data hold by vmcs12
 400          */
 401         bool sync_shadow_vmcs;
 402
 403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 404         struct list_head vmcs02_pool;
 405         int vmcs02_num;
 406         u64 vmcs01_tsc_offset;
 407         /* L2 must run next, and mustn't decide to exit to L1. */
 408         bool nested_run_pending;
 409         /*
 410          * Guest pages referred to in vmcs02 with host-physical pointers, so
 411          * we must keep them pinned while L2 runs.
 412          */
 413         struct page *apic_access_page;
 414         struct page *virtual_apic_page;
 415         struct page *pi_desc_page;
 416         struct pi_desc *pi_desc;
 417         bool pi_pending;
 418         u16 posted_intr_nv;
 419         u64 msr_ia32_feature_control;
 420
 421         struct hrtimer preemption_timer;
 422         bool preemption_timer_expired;
 423
 424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 425         u64 vmcs01_debugctl;
 426
 427         u32 nested_vmx_procbased_ctls_low;
 428         u32 nested_vmx_procbased_ctls_high;
 429         u32 nested_vmx_true_procbased_ctls_low;
 430         u32 nested_vmx_secondary_ctls_low;
 431         u32 nested_vmx_secondary_ctls_high;
 432         u32 nested_vmx_pinbased_ctls_low;
 433         u32 nested_vmx_pinbased_ctls_high;
 434         u32 nested_vmx_exit_ctls_low;
 435         u32 nested_vmx_exit_ctls_high;
 436         u32 nested_vmx_true_exit_ctls_low;
 437         u32 nested_vmx_entry_ctls_low;
 438         u32 nested_vmx_entry_ctls_high;
 439         u32 nested_vmx_true_entry_ctls_low;
 440         u32 nested_vmx_misc_low;
 441         u32 nested_vmx_misc_high;
 442         u32 nested_vmx_ept_caps;
 443 };
 444
 445 #define POSTED_INTR_ON  0
 446 /* Posted-Interrupt Descriptor */
 447 struct pi_desc {
 448         u32 pir[8];     /* Posted interrupt requested */
 449         u32 control;    /* bit 0 of control is outstanding notification bit */
 450         u32 rsvd[7];
 451 } __aligned(64);
 452
 453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 454 {
 455         return test_and_set_bit(POSTED_INTR_ON,
 456                         (unsigned long *)&pi_desc->control);
 457 }
 458
 459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 460 {
 461         return test_and_clear_bit(POSTED_INTR_ON,
 462                         (unsigned long *)&pi_desc->control);
 463 }
 464
 465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 466 {
 467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 468 }
 469
 470 struct vcpu_vmx {
 471         struct kvm_vcpu       vcpu;
 472         unsigned long         host_rsp;
 473         u8                    fail;
 474         bool                  nmi_known_unmasked;
 475         u32                   exit_intr_info;
 476         u32                   idt_vectoring_info;
 477         ulong                 rflags;
 478         struct shared_msr_entry *guest_msrs;
 479         int                   nmsrs;
 480         int                   save_nmsrs;
 481         unsigned long         host_idt_base;
 482 #ifdef CONFIG_X86_64
 483         u64                   msr_host_kernel_gs_base;
 484         u64                   msr_guest_kernel_gs_base;
 485 #endif
 486         u32 vm_entry_controls_shadow;
 487         u32 vm_exit_controls_shadow;
 488         /*
 489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 490          * non-nested (L1) guest, it always points to vmcs01. For a nested
 491          * guest (L2), it points to a different VMCS.
 492          */
 493         struct loaded_vmcs    vmcs01;
 494         struct loaded_vmcs   *loaded_vmcs;
 495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 496         struct msr_autoload {
 497                 unsigned nr;
 498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 500         } msr_autoload;
 501         struct {
 502                 int           loaded;
 503                 u16           fs_sel, gs_sel, ldt_sel;
 504 #ifdef CONFIG_X86_64
 505                 u16           ds_sel, es_sel;
 506 #endif
 507                 int           gs_ldt_reload_needed;
 508                 int           fs_reload_needed;
 509                 u64           msr_host_bndcfgs;
 510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 511         } host_state;
 512         struct {
 513                 int vm86_active;
 514                 ulong save_rflags;
 515                 struct kvm_segment segs[8];
 516         } rmode;
 517         struct {
 518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 519                 struct kvm_save_segment {
 520                         u16 selector;
 521                         unsigned long base;
 522                         u32 limit;
 523                         u32 ar;
 524                 } seg[8];
 525         } segment_cache;
 526         int vpid;
 527         bool emulation_required;
 528
 529         /* Support for vnmi-less CPUs */
 530         int soft_vnmi_blocked;
 531         ktime_t entry_time;
 532         s64 vnmi_blocked_time;
 533         u32 exit_reason;
 534
 535         bool rdtscp_enabled;
 536
 537         /* Posted interrupt descriptor */
 538         struct pi_desc pi_desc;
 539
 540         /* Support for a guest hypervisor (nested VMX) */
 541         struct nested_vmx nested;
 542
 543         /* Dynamic PLE window. */
 544         int ple_window;
 545         bool ple_window_dirty;
 546
 547         /* Support for PML */
 548 #define PML_ENTITY_NUM          512
 549         struct page *pml_pg;
 550 };
 551
 552 enum segment_cache_field {
 553         SEG_FIELD_SEL = 0,
 554         SEG_FIELD_BASE = 1,
 555         SEG_FIELD_LIMIT = 2,
 556         SEG_FIELD_AR = 3,
 557
 558         SEG_FIELD_NR = 4
 559 };
 560
 561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 562 {
 563         return container_of(vcpu, struct vcpu_vmx, vcpu);
 564 }
 565
 566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 570
 571
 572 static unsigned long shadow_read_only_fields[] = {
 573         /*
 574          * We do NOT shadow fields that are modified when L0
 575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 576          * VMXON...) executed by L1.
 577          * For example, VM_INSTRUCTION_ERROR is read
 578          * by L1 if a vmx instruction fails (part of the error path).
 579          * Note the code assumes this logic. If for some reason
 580          * we start shadowing these fields then we need to
 581          * force a shadow sync when L0 emulates vmx instructions
 582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 583          * by nested_vmx_failValid)
 584          */
 585         VM_EXIT_REASON,
 586         VM_EXIT_INTR_INFO,
 587         VM_EXIT_INSTRUCTION_LEN,
 588         IDT_VECTORING_INFO_FIELD,
 589         IDT_VECTORING_ERROR_CODE,
 590         VM_EXIT_INTR_ERROR_CODE,
 591         EXIT_QUALIFICATION,
 592         GUEST_LINEAR_ADDRESS,
 593         GUEST_PHYSICAL_ADDRESS
 594 };
 595 static int max_shadow_read_only_fields =
 596         ARRAY_SIZE(shadow_read_only_fields);
 597
 598 static unsigned long shadow_read_write_fields[] = {
 599         TPR_THRESHOLD,
 600         GUEST_RIP,
 601         GUEST_RSP,
 602         GUEST_CR0,
 603         GUEST_CR3,
 604         GUEST_CR4,
 605         GUEST_INTERRUPTIBILITY_INFO,
 606         GUEST_RFLAGS,
 607         GUEST_CS_SELECTOR,
 608         GUEST_CS_AR_BYTES,
 609         GUEST_CS_LIMIT,
 610         GUEST_CS_BASE,
 611         GUEST_ES_BASE,
 612         GUEST_BNDCFGS,
 613         CR0_GUEST_HOST_MASK,
 614         CR0_READ_SHADOW,
 615         CR4_READ_SHADOW,
 616         TSC_OFFSET,
 617         EXCEPTION_BITMAP,
 618         CPU_BASED_VM_EXEC_CONTROL,
 619         VM_ENTRY_EXCEPTION_ERROR_CODE,
 620         VM_ENTRY_INTR_INFO_FIELD,
 621         VM_ENTRY_INSTRUCTION_LEN,
 622         VM_ENTRY_EXCEPTION_ERROR_CODE,
 623         HOST_FS_BASE,
 624         HOST_GS_BASE,
 625         HOST_FS_SELECTOR,
 626         HOST_GS_SELECTOR
 627 };
 628 static int max_shadow_read_write_fields =
 629         ARRAY_SIZE(shadow_read_write_fields);
 630
 631 static const unsigned short vmcs_field_to_offset_table[] = {
 632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 633         FIELD(POSTED_INTR_NV, posted_intr_nv),
 634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 643         FIELD(HOST_ES_SELECTOR, host_es_selector),
 644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 650         FIELD64(IO_BITMAP_A, io_bitmap_a),
 651         FIELD64(IO_BITMAP_B, io_bitmap_b),
 652         FIELD64(MSR_BITMAP, msr_bitmap),
 653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 656         FIELD64(TSC_OFFSET, tsc_offset),
 657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 660         FIELD64(EPT_POINTER, ept_pointer),
 661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 694         FIELD(TPR_THRESHOLD, tpr_threshold),
 695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 697         FIELD(VM_EXIT_REASON, vm_exit_reason),
 698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 735         FIELD(EXIT_QUALIFICATION, exit_qualification),
 736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 737         FIELD(GUEST_CR0, guest_cr0),
 738         FIELD(GUEST_CR3, guest_cr3),
 739         FIELD(GUEST_CR4, guest_cr4),
 740         FIELD(GUEST_ES_BASE, guest_es_base),
 741         FIELD(GUEST_CS_BASE, guest_cs_base),
 742         FIELD(GUEST_SS_BASE, guest_ss_base),
 743         FIELD(GUEST_DS_BASE, guest_ds_base),
 744         FIELD(GUEST_FS_BASE, guest_fs_base),
 745         FIELD(GUEST_GS_BASE, guest_gs_base),
 746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 747         FIELD(GUEST_TR_BASE, guest_tr_base),
 748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 750         FIELD(GUEST_DR7, guest_dr7),
 751         FIELD(GUEST_RSP, guest_rsp),
 752         FIELD(GUEST_RIP, guest_rip),
 753         FIELD(GUEST_RFLAGS, guest_rflags),
 754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 757         FIELD(HOST_CR0, host_cr0),
 758         FIELD(HOST_CR3, host_cr3),
 759         FIELD(HOST_CR4, host_cr4),
 760         FIELD(HOST_FS_BASE, host_fs_base),
 761         FIELD(HOST_GS_BASE, host_gs_base),
 762         FIELD(HOST_TR_BASE, host_tr_base),
 763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 764         FIELD(HOST_IDTR_BASE, host_idtr_base),
 765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 767         FIELD(HOST_RSP, host_rsp),
 768         FIELD(HOST_RIP, host_rip),
 769 };
 770
 771 static inline short vmcs_field_to_offset(unsigned long field)
 772 {
 773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 774
 775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 776             vmcs_field_to_offset_table[field] == 0)
 777                 return -ENOENT;
 778
 779         return vmcs_field_to_offset_table[field];
 780 }
 781
 782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 783 {
 784         return to_vmx(vcpu)->nested.current_vmcs12;
 785 }
 786
 787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 788 {
 789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 790         if (is_error_page(page))
 791                 return NULL;
 792
 793         return page;
 794 }
 795
 796 static void nested_release_page(struct page *page)
 797 {
 798         kvm_release_page_dirty(page);
 799 }
 800
 801 static void nested_release_page_clean(struct page *page)
 802 {
 803         kvm_release_page_clean(page);
 804 }
 805
 806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 807 static u64 construct_eptp(unsigned long root_hpa);
 808 static void kvm_cpu_vmxon(u64 addr);
 809 static void kvm_cpu_vmxoff(void);
 810 static bool vmx_mpx_supported(void);
 811 static bool vmx_xsaves_supported(void);
 812 static int vmx_vm_has_apicv(struct kvm *kvm);
 813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 815                             struct kvm_segment *var, int seg);
 816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 817                             struct kvm_segment *var, int seg);
 818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 823 static int alloc_identity_pagetable(struct kvm *kvm);
 824
 825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 827 /*
 828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 830  */
 831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 833
 834 static unsigned long *vmx_io_bitmap_a;
 835 static unsigned long *vmx_io_bitmap_b;
 836 static unsigned long *vmx_msr_bitmap_legacy;
 837 static unsigned long *vmx_msr_bitmap_longmode;
 838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 840 static unsigned long *vmx_msr_bitmap_nested;
 841 static unsigned long *vmx_vmread_bitmap;
 842 static unsigned long *vmx_vmwrite_bitmap;
 843
 844 static bool cpu_has_load_ia32_efer;
 845 static bool cpu_has_load_perf_global_ctrl;
 846
 847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 848 static DEFINE_SPINLOCK(vmx_vpid_lock);
 849
 850 static struct vmcs_config {
 851         int size;
 852         int order;
 853         u32 revision_id;
 854         u32 pin_based_exec_ctrl;
 855         u32 cpu_based_exec_ctrl;
 856         u32 cpu_based_2nd_exec_ctrl;
 857         u32 vmexit_ctrl;
 858         u32 vmentry_ctrl;
 859 } vmcs_config;
 860
 861 static struct vmx_capability {
 862         u32 ept;
 863         u32 vpid;
 864 } vmx_capability;
 865
 866 #define VMX_SEGMENT_FIELD(seg)                                  \
 867         [VCPU_SREG_##seg] = {                                   \
 868                 .selector = GUEST_##seg##_SELECTOR,             \
 869                 .base = GUEST_##seg##_BASE,                     \
 870                 .limit = GUEST_##seg##_LIMIT,                   \
 871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 872         }
 873
 874 static const struct kvm_vmx_segment_field {
 875         unsigned selector;
 876         unsigned base;
 877         unsigned limit;
 878         unsigned ar_bytes;
 879 } kvm_vmx_segment_fields[] = {
 880         VMX_SEGMENT_FIELD(CS),
 881         VMX_SEGMENT_FIELD(DS),
 882         VMX_SEGMENT_FIELD(ES),
 883         VMX_SEGMENT_FIELD(FS),
 884         VMX_SEGMENT_FIELD(GS),
 885         VMX_SEGMENT_FIELD(SS),
 886         VMX_SEGMENT_FIELD(TR),
 887         VMX_SEGMENT_FIELD(LDTR),
 888 };
 889
 890 static u64 host_efer;
 891
 892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 893
 894 /*
 895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 896  * away by decrementing the array size.
 897  */
 898 static const u32 vmx_msr_index[] = {
 899 #ifdef CONFIG_X86_64
 900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 901 #endif
 902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 903 };
 904
 905 static inline bool is_page_fault(u32 intr_info)
 906 {
 907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 908                              INTR_INFO_VALID_MASK)) ==
 909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 910 }
 911
 912 static inline bool is_no_device(u32 intr_info)
 913 {
 914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 915                              INTR_INFO_VALID_MASK)) ==
 916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 917 }
 918
 919 static inline bool is_invalid_opcode(u32 intr_info)
 920 {
 921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 922                              INTR_INFO_VALID_MASK)) ==
 923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 924 }
 925
 926 static inline bool is_external_interrupt(u32 intr_info)
 927 {
 928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 930 }
 931
 932 static inline bool is_machine_check(u32 intr_info)
 933 {
 934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 935                              INTR_INFO_VALID_MASK)) ==
 936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 937 }
 938
 939 static inline bool cpu_has_vmx_msr_bitmap(void)
 940 {
 941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 942 }
 943
 944 static inline bool cpu_has_vmx_tpr_shadow(void)
 945 {
 946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 947 }
 948
 949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 950 {
 951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 952 }
 953
 954 static inline bool cpu_has_secondary_exec_ctrls(void)
 955 {
 956         return vmcs_config.cpu_based_exec_ctrl &
 957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 958 }
 959
 960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 961 {
 962         return vmcs_config.cpu_based_2nd_exec_ctrl &
 963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 964 }
 965
 966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 967 {
 968         return vmcs_config.cpu_based_2nd_exec_ctrl &
 969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 970 }
 971
 972 static inline bool cpu_has_vmx_apic_register_virt(void)
 973 {
 974         return vmcs_config.cpu_based_2nd_exec_ctrl &
 975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 976 }
 977
 978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 979 {
 980         return vmcs_config.cpu_based_2nd_exec_ctrl &
 981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 982 }
 983
 984 static inline bool cpu_has_vmx_posted_intr(void)
 985 {
 986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 987 }
 988
 989 static inline bool cpu_has_vmx_apicv(void)
 990 {
 991         return cpu_has_vmx_apic_register_virt() &&
 992                 cpu_has_vmx_virtual_intr_delivery() &&
 993                 cpu_has_vmx_posted_intr();
 994 }
 995
 996 static inline bool cpu_has_vmx_flexpriority(void)
 997 {
 998         return cpu_has_vmx_tpr_shadow() &&
 999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469
1470
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497
1498
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716
1717         guest_efer = vmx->vcpu.arch.efer;
1718
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762
1763         if (!(selector & ~3))
1764                 return 0;
1765
1766         table_base = gdt->address;
1767
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796
1797         if (vmx->host_state.loaded)
1798                 return;
1799
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061
2062         return ret;
2063 }
2064
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170
2171         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2172                 if (is_long_mode(vcpu))
2173                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2174                 else
2175                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2176         } else {
2177                 if (is_long_mode(vcpu))
2178                         msr_bitmap = vmx_msr_bitmap_longmode;
2179                 else
2180                         msr_bitmap = vmx_msr_bitmap_legacy;
2181         }
2182
2183         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2184 }
2185
2186 /*
2187  * Set up the vmcs to automatically save and restore system
2188  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2189  * mode, as fiddling with msrs is very expensive.
2190  */
2191 static void setup_msrs(struct vcpu_vmx *vmx)
2192 {
2193         int save_nmsrs, index;
2194
2195         save_nmsrs = 0;
2196 #ifdef CONFIG_X86_64
2197         if (is_long_mode(&vmx->vcpu)) {
2198                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2199                 if (index >= 0)
2200                         move_msr_up(vmx, index, save_nmsrs++);
2201                 index = __find_msr_index(vmx, MSR_LSTAR);
2202                 if (index >= 0)
2203                         move_msr_up(vmx, index, save_nmsrs++);
2204                 index = __find_msr_index(vmx, MSR_CSTAR);
2205                 if (index >= 0)
2206                         move_msr_up(vmx, index, save_nmsrs++);
2207                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2208                 if (index >= 0 && vmx->rdtscp_enabled)
2209                         move_msr_up(vmx, index, save_nmsrs++);
2210                 /*
2211                  * MSR_STAR is only needed on long mode guests, and only
2212                  * if efer.sce is enabled.
2213                  */
2214                 index = __find_msr_index(vmx, MSR_STAR);
2215                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2216                         move_msr_up(vmx, index, save_nmsrs++);
2217         }
2218 #endif
2219         index = __find_msr_index(vmx, MSR_EFER);
2220         if (index >= 0 && update_transition_efer(vmx, index))
2221                 move_msr_up(vmx, index, save_nmsrs++);
2222
2223         vmx->save_nmsrs = save_nmsrs;
2224
2225         if (cpu_has_vmx_msr_bitmap())
2226                 vmx_set_msr_bitmap(&vmx->vcpu);
2227 }
2228
2229 /*
2230  * reads and returns guest's timestamp counter "register"
2231  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2232  */
2233 static u64 guest_read_tsc(void)
2234 {
2235         u64 host_tsc, tsc_offset;
2236
2237         rdtscll(host_tsc);
2238         tsc_offset = vmcs_read64(TSC_OFFSET);
2239         return host_tsc + tsc_offset;
2240 }
2241
2242 /*
2243  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2244  * counter, even if a nested guest (L2) is currently running.
2245  */
2246 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2247 {
2248         u64 tsc_offset;
2249
2250         tsc_offset = is_guest_mode(vcpu) ?
2251                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2252                 vmcs_read64(TSC_OFFSET);
2253         return host_tsc + tsc_offset;
2254 }
2255
2256 /*
2257  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2258  * software catchup for faster rates on slower CPUs.
2259  */
2260 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2261 {
2262         if (!scale)
2263                 return;
2264
2265         if (user_tsc_khz > tsc_khz) {
2266                 vcpu->arch.tsc_catchup = 1;
2267                 vcpu->arch.tsc_always_catchup = 1;
2268         } else
2269                 WARN(1, "user requested TSC rate below hardware speed\n");
2270 }
2271
2272 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2273 {
2274         return vmcs_read64(TSC_OFFSET);
2275 }
2276
2277 /*
2278  * writes 'offset' into guest's timestamp counter offset register
2279  */
2280 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2281 {
2282         if (is_guest_mode(vcpu)) {
2283                 /*
2284                  * We're here if L1 chose not to trap WRMSR to TSC. According
2285                  * to the spec, this should set L1's TSC; The offset that L1
2286                  * set for L2 remains unchanged, and still needs to be added
2287                  * to the newly set TSC to get L2's TSC.
2288                  */
2289                 struct vmcs12 *vmcs12;
2290                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2291                 /* recalculate vmcs02.TSC_OFFSET: */
2292                 vmcs12 = get_vmcs12(vcpu);
2293                 vmcs_write64(TSC_OFFSET, offset +
2294                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2295                          vmcs12->tsc_offset : 0));
2296         } else {
2297                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2298                                            vmcs_read64(TSC_OFFSET), offset);
2299                 vmcs_write64(TSC_OFFSET, offset);
2300         }
2301 }
2302
2303 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2304 {
2305         u64 offset = vmcs_read64(TSC_OFFSET);
2306
2307         vmcs_write64(TSC_OFFSET, offset + adjustment);
2308         if (is_guest_mode(vcpu)) {
2309                 /* Even when running L2, the adjustment needs to apply to L1 */
2310                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2311         } else
2312                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2313                                            offset + adjustment);
2314 }
2315
2316 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2317 {
2318         return target_tsc - native_read_tsc();
2319 }
2320
2321 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2322 {
2323         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2324         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2325 }
2326
2327 /*
2328  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2329  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2330  * all guests if the "nested" module option is off, and can also be disabled
2331  * for a single guest by disabling its VMX cpuid bit.
2332  */
2333 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2334 {
2335         return nested && guest_cpuid_has_vmx(vcpu);
2336 }
2337
2338 /*
2339  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2340  * returned for the various VMX controls MSRs when nested VMX is enabled.
2341  * The same values should also be used to verify that vmcs12 control fields are
2342  * valid during nested entry from L1 to L2.
2343  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2344  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2345  * bit in the high half is on if the corresponding bit in the control field
2346  * may be on. See also vmx_control_verify().
2347  */
2348 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2349 {
2350         /*
2351          * Note that as a general rule, the high half of the MSRs (bits in
2352          * the control fields which may be 1) should be initialized by the
2353          * intersection of the underlying hardware's MSR (i.e., features which
2354          * can be supported) and the list of features we want to expose -
2355          * because they are known to be properly supported in our code.
2356          * Also, usually, the low half of the MSRs (bits which must be 1) can
2357          * be set to 0, meaning that L1 may turn off any of these bits. The
2358          * reason is that if one of these bits is necessary, it will appear
2359          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2360          * fields of vmcs01 and vmcs02, will turn these bits off - and
2361          * nested_vmx_exit_handled() will not pass related exits to L1.
2362          * These rules have exceptions below.
2363          */
2364
2365         /* pin-based controls */
2366         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2367                 vmx->nested.nested_vmx_pinbased_ctls_low,
2368                 vmx->nested.nested_vmx_pinbased_ctls_high);
2369         vmx->nested.nested_vmx_pinbased_ctls_low |=
2370                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2371         vmx->nested.nested_vmx_pinbased_ctls_high &=
2372                 PIN_BASED_EXT_INTR_MASK |
2373                 PIN_BASED_NMI_EXITING |
2374                 PIN_BASED_VIRTUAL_NMIS;
2375         vmx->nested.nested_vmx_pinbased_ctls_high |=
2376                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2377                 PIN_BASED_VMX_PREEMPTION_TIMER;
2378         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2379                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2380                         PIN_BASED_POSTED_INTR;
2381
2382         /* exit controls */
2383         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2384                 vmx->nested.nested_vmx_exit_ctls_low,
2385                 vmx->nested.nested_vmx_exit_ctls_high);
2386         vmx->nested.nested_vmx_exit_ctls_low =
2387                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2388
2389         vmx->nested.nested_vmx_exit_ctls_high &=
2390 #ifdef CONFIG_X86_64
2391                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2392 #endif
2393                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2394         vmx->nested.nested_vmx_exit_ctls_high |=
2395                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2396                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2397                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2398
2399         if (vmx_mpx_supported())
2400                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2401
2402         /* We support free control of debug control saving. */
2403         vmx->nested.nested_vmx_true_exit_ctls_low =
2404                 vmx->nested.nested_vmx_exit_ctls_low &
2405                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2406
2407         /* entry controls */
2408         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2409                 vmx->nested.nested_vmx_entry_ctls_low,
2410                 vmx->nested.nested_vmx_entry_ctls_high);
2411         vmx->nested.nested_vmx_entry_ctls_low =
2412                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2413         vmx->nested.nested_vmx_entry_ctls_high &=
2414 #ifdef CONFIG_X86_64
2415                 VM_ENTRY_IA32E_MODE |
2416 #endif
2417                 VM_ENTRY_LOAD_IA32_PAT;
2418         vmx->nested.nested_vmx_entry_ctls_high |=
2419                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2420         if (vmx_mpx_supported())
2421                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2422
2423         /* We support free control of debug control loading. */
2424         vmx->nested.nested_vmx_true_entry_ctls_low =
2425                 vmx->nested.nested_vmx_entry_ctls_low &
2426                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2427
2428         /* cpu-based controls */
2429         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2430                 vmx->nested.nested_vmx_procbased_ctls_low,
2431                 vmx->nested.nested_vmx_procbased_ctls_high);
2432         vmx->nested.nested_vmx_procbased_ctls_low =
2433                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2434         vmx->nested.nested_vmx_procbased_ctls_high &=
2435                 CPU_BASED_VIRTUAL_INTR_PENDING |
2436                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2437                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2438                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2439                 CPU_BASED_CR3_STORE_EXITING |
2440 #ifdef CONFIG_X86_64
2441                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2442 #endif
2443                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2444                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2445                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2446                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2447                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2448         /*
2449          * We can allow some features even when not supported by the
2450          * hardware. For example, L1 can specify an MSR bitmap - and we
2451          * can use it to avoid exits to L1 - even when L0 runs L2
2452          * without MSR bitmaps.
2453          */
2454         vmx->nested.nested_vmx_procbased_ctls_high |=
2455                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2456                 CPU_BASED_USE_MSR_BITMAPS;
2457
2458         /* We support free control of CR3 access interception. */
2459         vmx->nested.nested_vmx_true_procbased_ctls_low =
2460                 vmx->nested.nested_vmx_procbased_ctls_low &
2461                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2462
2463         /* secondary cpu-based controls */
2464         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2465                 vmx->nested.nested_vmx_secondary_ctls_low,
2466                 vmx->nested.nested_vmx_secondary_ctls_high);
2467         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2468         vmx->nested.nested_vmx_secondary_ctls_high &=
2469                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2470                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2471                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2472                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2473                 SECONDARY_EXEC_WBINVD_EXITING |
2474                 SECONDARY_EXEC_XSAVES;
2475
2476         if (enable_ept) {
2477                 /* nested EPT: emulate EPT also to L1 */
2478                 vmx->nested.nested_vmx_secondary_ctls_high |=
2479                         SECONDARY_EXEC_ENABLE_EPT |
2480                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2481                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2482                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2483                          VMX_EPT_INVEPT_BIT;
2484                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2485                 /*
2486                  * For nested guests, we don't do anything specific
2487                  * for single context invalidation. Hence, only advertise
2488                  * support for global context invalidation.
2489                  */
2490                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2491         } else
2492                 vmx->nested.nested_vmx_ept_caps = 0;
2493
2494         /* miscellaneous data */
2495         rdmsr(MSR_IA32_VMX_MISC,
2496                 vmx->nested.nested_vmx_misc_low,
2497                 vmx->nested.nested_vmx_misc_high);
2498         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2499         vmx->nested.nested_vmx_misc_low |=
2500                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2501                 VMX_MISC_ACTIVITY_HLT;
2502         vmx->nested.nested_vmx_misc_high = 0;
2503 }
2504
2505 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2506 {
2507         /*
2508          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2509          */
2510         return ((control & high) | low) == control;
2511 }
2512
2513 static inline u64 vmx_control_msr(u32 low, u32 high)
2514 {
2515         return low | ((u64)high << 32);
2516 }
2517
2518 /* Returns 0 on success, non-0 otherwise. */
2519 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2520 {
2521         struct vcpu_vmx *vmx = to_vmx(vcpu);
2522
2523         switch (msr_index) {
2524         case MSR_IA32_VMX_BASIC:
2525                 /*
2526                  * This MSR reports some information about VMX support. We
2527                  * should return information about the VMX we emulate for the
2528                  * guest, and the VMCS structure we give it - not about the
2529                  * VMX support of the underlying hardware.
2530                  */
2531                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2532                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2533                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2534                 break;
2535         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2536         case MSR_IA32_VMX_PINBASED_CTLS:
2537                 *pdata = vmx_control_msr(
2538                         vmx->nested.nested_vmx_pinbased_ctls_low,
2539                         vmx->nested.nested_vmx_pinbased_ctls_high);
2540                 break;
2541         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2542                 *pdata = vmx_control_msr(
2543                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2544                         vmx->nested.nested_vmx_procbased_ctls_high);
2545                 break;
2546         case MSR_IA32_VMX_PROCBASED_CTLS:
2547                 *pdata = vmx_control_msr(
2548                         vmx->nested.nested_vmx_procbased_ctls_low,
2549                         vmx->nested.nested_vmx_procbased_ctls_high);
2550                 break;
2551         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2552                 *pdata = vmx_control_msr(
2553                         vmx->nested.nested_vmx_true_exit_ctls_low,
2554                         vmx->nested.nested_vmx_exit_ctls_high);
2555                 break;
2556         case MSR_IA32_VMX_EXIT_CTLS:
2557                 *pdata = vmx_control_msr(
2558                         vmx->nested.nested_vmx_exit_ctls_low,
2559                         vmx->nested.nested_vmx_exit_ctls_high);
2560                 break;
2561         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2562                 *pdata = vmx_control_msr(
2563                         vmx->nested.nested_vmx_true_entry_ctls_low,
2564                         vmx->nested.nested_vmx_entry_ctls_high);
2565                 break;
2566         case MSR_IA32_VMX_ENTRY_CTLS:
2567                 *pdata = vmx_control_msr(
2568                         vmx->nested.nested_vmx_entry_ctls_low,
2569                         vmx->nested.nested_vmx_entry_ctls_high);
2570                 break;
2571         case MSR_IA32_VMX_MISC:
2572                 *pdata = vmx_control_msr(
2573                         vmx->nested.nested_vmx_misc_low,
2574                         vmx->nested.nested_vmx_misc_high);
2575                 break;
2576         /*
2577          * These MSRs specify bits which the guest must keep fixed (on or off)
2578          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2579          * We picked the standard core2 setting.
2580          */
2581 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2582 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2583         case MSR_IA32_VMX_CR0_FIXED0:
2584                 *pdata = VMXON_CR0_ALWAYSON;
2585                 break;
2586         case MSR_IA32_VMX_CR0_FIXED1:
2587                 *pdata = -1ULL;
2588                 break;
2589         case MSR_IA32_VMX_CR4_FIXED0:
2590                 *pdata = VMXON_CR4_ALWAYSON;
2591                 break;
2592         case MSR_IA32_VMX_CR4_FIXED1:
2593                 *pdata = -1ULL;
2594                 break;
2595         case MSR_IA32_VMX_VMCS_ENUM:
2596                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2597                 break;
2598         case MSR_IA32_VMX_PROCBASED_CTLS2:
2599                 *pdata = vmx_control_msr(
2600                         vmx->nested.nested_vmx_secondary_ctls_low,
2601                         vmx->nested.nested_vmx_secondary_ctls_high);
2602                 break;
2603         case MSR_IA32_VMX_EPT_VPID_CAP:
2604                 /* Currently, no nested vpid support */
2605                 *pdata = vmx->nested.nested_vmx_ept_caps;
2606                 break;
2607         default:
2608                 return 1;
2609         }
2610
2611         return 0;
2612 }
2613
2614 /*
2615  * Reads an msr value (of 'msr_index') into 'pdata'.
2616  * Returns 0 on success, non-0 otherwise.
2617  * Assumes vcpu_load() was already called.
2618  */
2619 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2620 {
2621         u64 data;
2622         struct shared_msr_entry *msr;
2623
2624         if (!pdata) {
2625                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2626                 return -EINVAL;
2627         }
2628
2629         switch (msr_index) {
2630 #ifdef CONFIG_X86_64
2631         case MSR_FS_BASE:
2632                 data = vmcs_readl(GUEST_FS_BASE);
2633                 break;
2634         case MSR_GS_BASE:
2635                 data = vmcs_readl(GUEST_GS_BASE);
2636                 break;
2637         case MSR_KERNEL_GS_BASE:
2638                 vmx_load_host_state(to_vmx(vcpu));
2639                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2640                 break;
2641 #endif
2642         case MSR_EFER:
2643                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2644         case MSR_IA32_TSC:
2645                 data = guest_read_tsc();
2646                 break;
2647         case MSR_IA32_SYSENTER_CS:
2648                 data = vmcs_read32(GUEST_SYSENTER_CS);
2649                 break;
2650         case MSR_IA32_SYSENTER_EIP:
2651                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2652                 break;
2653         case MSR_IA32_SYSENTER_ESP:
2654                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2655                 break;
2656         case MSR_IA32_BNDCFGS:
2657                 if (!vmx_mpx_supported())
2658                         return 1;
2659                 data = vmcs_read64(GUEST_BNDCFGS);
2660                 break;
2661         case MSR_IA32_FEATURE_CONTROL:
2662                 if (!nested_vmx_allowed(vcpu))
2663                         return 1;
2664                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2665                 break;
2666         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2667                 if (!nested_vmx_allowed(vcpu))
2668                         return 1;
2669                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2670         case MSR_IA32_XSS:
2671                 if (!vmx_xsaves_supported())
2672                         return 1;
2673                 data = vcpu->arch.ia32_xss;
2674                 break;
2675         case MSR_TSC_AUX:
2676                 if (!to_vmx(vcpu)->rdtscp_enabled)
2677                         return 1;
2678                 /* Otherwise falls through */
2679         default:
2680                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2681                 if (msr) {
2682                         data = msr->data;
2683                         break;
2684                 }
2685                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2686         }
2687
2688         *pdata = data;
2689         return 0;
2690 }
2691
2692 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2693
2694 /*
2695  * Writes msr value into into the appropriate "register".
2696  * Returns 0 on success, non-0 otherwise.
2697  * Assumes vcpu_load() was already called.
2698  */
2699 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2700 {
2701         struct vcpu_vmx *vmx = to_vmx(vcpu);
2702         struct shared_msr_entry *msr;
2703         int ret = 0;
2704         u32 msr_index = msr_info->index;
2705         u64 data = msr_info->data;
2706
2707         switch (msr_index) {
2708         case MSR_EFER:
2709                 ret = kvm_set_msr_common(vcpu, msr_info);
2710                 break;
2711 #ifdef CONFIG_X86_64
2712         case MSR_FS_BASE:
2713                 vmx_segment_cache_clear(vmx);
2714                 vmcs_writel(GUEST_FS_BASE, data);
2715                 break;
2716         case MSR_GS_BASE:
2717                 vmx_segment_cache_clear(vmx);
2718                 vmcs_writel(GUEST_GS_BASE, data);
2719                 break;
2720         case MSR_KERNEL_GS_BASE:
2721                 vmx_load_host_state(vmx);
2722                 vmx->msr_guest_kernel_gs_base = data;
2723                 break;
2724 #endif
2725         case MSR_IA32_SYSENTER_CS:
2726                 vmcs_write32(GUEST_SYSENTER_CS, data);
2727                 break;
2728         case MSR_IA32_SYSENTER_EIP:
2729                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2730                 break;
2731         case MSR_IA32_SYSENTER_ESP:
2732                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2733                 break;
2734         case MSR_IA32_BNDCFGS:
2735                 if (!vmx_mpx_supported())
2736                         return 1;
2737                 vmcs_write64(GUEST_BNDCFGS, data);
2738                 break;
2739         case MSR_IA32_TSC:
2740                 kvm_write_tsc(vcpu, msr_info);
2741                 break;
2742         case MSR_IA32_CR_PAT:
2743                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2744                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2745                                 return 1;
2746                         vmcs_write64(GUEST_IA32_PAT, data);
2747                         vcpu->arch.pat = data;
2748                         break;
2749                 }
2750                 ret = kvm_set_msr_common(vcpu, msr_info);
2751                 break;
2752         case MSR_IA32_TSC_ADJUST:
2753                 ret = kvm_set_msr_common(vcpu, msr_info);
2754                 break;
2755         case MSR_IA32_FEATURE_CONTROL:
2756                 if (!nested_vmx_allowed(vcpu) ||
2757                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2758                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2759                         return 1;
2760                 vmx->nested.msr_ia32_feature_control = data;
2761                 if (msr_info->host_initiated && data == 0)
2762                         vmx_leave_nested(vcpu);
2763                 break;
2764         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2765                 return 1; /* they are read-only */
2766         case MSR_IA32_XSS:
2767                 if (!vmx_xsaves_supported())
2768                         return 1;
2769                 /*
2770                  * The only supported bit as of Skylake is bit 8, but
2771                  * it is not supported on KVM.
2772                  */
2773                 if (data != 0)
2774                         return 1;
2775                 vcpu->arch.ia32_xss = data;
2776                 if (vcpu->arch.ia32_xss != host_xss)
2777                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2778                                 vcpu->arch.ia32_xss, host_xss);
2779                 else
2780                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2781                 break;
2782         case MSR_TSC_AUX:
2783                 if (!vmx->rdtscp_enabled)
2784                         return 1;
2785                 /* Check reserved bit, higher 32 bits should be zero */
2786                 if ((data >> 32) != 0)
2787                         return 1;
2788                 /* Otherwise falls through */
2789         default:
2790                 msr = find_msr_entry(vmx, msr_index);
2791                 if (msr) {
2792                         u64 old_msr_data = msr->data;
2793                         msr->data = data;
2794                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2795                                 preempt_disable();
2796                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2797                                                          msr->mask);
2798                                 preempt_enable();
2799                                 if (ret)
2800                                         msr->data = old_msr_data;
2801                         }
2802                         break;
2803                 }
2804                 ret = kvm_set_msr_common(vcpu, msr_info);
2805         }
2806
2807         return ret;
2808 }
2809
2810 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2811 {
2812         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2813         switch (reg) {
2814         case VCPU_REGS_RSP:
2815                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2816                 break;
2817         case VCPU_REGS_RIP:
2818                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2819                 break;
2820         case VCPU_EXREG_PDPTR:
2821                 if (enable_ept)
2822                         ept_save_pdptrs(vcpu);
2823                 break;
2824         default:
2825                 break;
2826         }
2827 }
2828
2829 static __init int cpu_has_kvm_support(void)
2830 {
2831         return cpu_has_vmx();
2832 }
2833
2834 static __init int vmx_disabled_by_bios(void)
2835 {
2836         u64 msr;
2837
2838         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2839         if (msr & FEATURE_CONTROL_LOCKED) {
2840                 /* launched w/ TXT and VMX disabled */
2841                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2842                         && tboot_enabled())
2843                         return 1;
2844                 /* launched w/o TXT and VMX only enabled w/ TXT */
2845                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2846                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2847                         && !tboot_enabled()) {
2848                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2849                                 "activate TXT before enabling KVM\n");
2850                         return 1;
2851                 }
2852                 /* launched w/o TXT and VMX disabled */
2853                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2854                         && !tboot_enabled())
2855                         return 1;
2856         }
2857
2858         return 0;
2859 }
2860
2861 static void kvm_cpu_vmxon(u64 addr)
2862 {
2863         asm volatile (ASM_VMX_VMXON_RAX
2864                         : : "a"(&addr), "m"(addr)
2865                         : "memory", "cc");
2866 }
2867
2868 static int hardware_enable(void)
2869 {
2870         int cpu = raw_smp_processor_id();
2871         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2872         u64 old, test_bits;
2873
2874         if (cr4_read_shadow() & X86_CR4_VMXE)
2875                 return -EBUSY;
2876
2877         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2878
2879         /*
2880          * Now we can enable the vmclear operation in kdump
2881          * since the loaded_vmcss_on_cpu list on this cpu
2882          * has been initialized.
2883          *
2884          * Though the cpu is not in VMX operation now, there
2885          * is no problem to enable the vmclear operation
2886          * for the loaded_vmcss_on_cpu list is empty!
2887          */
2888         crash_enable_local_vmclear(cpu);
2889
2890         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2891
2892         test_bits = FEATURE_CONTROL_LOCKED;
2893         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2894         if (tboot_enabled())
2895                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2896
2897         if ((old & test_bits) != test_bits) {
2898                 /* enable and lock */
2899                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2900         }
2901         cr4_set_bits(X86_CR4_VMXE);
2902
2903         if (vmm_exclusive) {
2904                 kvm_cpu_vmxon(phys_addr);
2905                 ept_sync_global();
2906         }
2907
2908         native_store_gdt(this_cpu_ptr(&host_gdt));
2909
2910         return 0;
2911 }
2912
2913 static void vmclear_local_loaded_vmcss(void)
2914 {
2915         int cpu = raw_smp_processor_id();
2916         struct loaded_vmcs *v, *n;
2917
2918         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2919                                  loaded_vmcss_on_cpu_link)
2920                 __loaded_vmcs_clear(v);
2921 }
2922
2923
2924 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2925  * tricks.
2926  */
2927 static void kvm_cpu_vmxoff(void)
2928 {
2929         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2930 }
2931
2932 static void hardware_disable(void)
2933 {
2934         if (vmm_exclusive) {
2935                 vmclear_local_loaded_vmcss();
2936                 kvm_cpu_vmxoff();
2937         }
2938         cr4_clear_bits(X86_CR4_VMXE);
2939 }
2940
2941 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2942                                       u32 msr, u32 *result)
2943 {
2944         u32 vmx_msr_low, vmx_msr_high;
2945         u32 ctl = ctl_min | ctl_opt;
2946
2947         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2948
2949         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2950         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2951
2952         /* Ensure minimum (required) set of control bits are supported. */
2953         if (ctl_min & ~ctl)
2954                 return -EIO;
2955
2956         *result = ctl;
2957         return 0;
2958 }
2959
2960 static __init bool allow_1_setting(u32 msr, u32 ctl)
2961 {
2962         u32 vmx_msr_low, vmx_msr_high;
2963
2964         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2965         return vmx_msr_high & ctl;
2966 }
2967
2968 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2969 {
2970         u32 vmx_msr_low, vmx_msr_high;
2971         u32 min, opt, min2, opt2;
2972         u32 _pin_based_exec_control = 0;
2973         u32 _cpu_based_exec_control = 0;
2974         u32 _cpu_based_2nd_exec_control = 0;
2975         u32 _vmexit_control = 0;
2976         u32 _vmentry_control = 0;
2977
2978         min = CPU_BASED_HLT_EXITING |
2979 #ifdef CONFIG_X86_64
2980               CPU_BASED_CR8_LOAD_EXITING |
2981               CPU_BASED_CR8_STORE_EXITING |
2982 #endif
2983               CPU_BASED_CR3_LOAD_EXITING |
2984               CPU_BASED_CR3_STORE_EXITING |
2985               CPU_BASED_USE_IO_BITMAPS |
2986               CPU_BASED_MOV_DR_EXITING |
2987               CPU_BASED_USE_TSC_OFFSETING |
2988               CPU_BASED_MWAIT_EXITING |
2989               CPU_BASED_MONITOR_EXITING |
2990               CPU_BASED_INVLPG_EXITING |
2991               CPU_BASED_RDPMC_EXITING;
2992
2993         opt = CPU_BASED_TPR_SHADOW |
2994               CPU_BASED_USE_MSR_BITMAPS |
2995               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2996         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2997                                 &_cpu_based_exec_control) < 0)
2998                 return -EIO;
2999 #ifdef CONFIG_X86_64
3000         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3001                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3002                                            ~CPU_BASED_CR8_STORE_EXITING;
3003 #endif
3004         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3005                 min2 = 0;
3006                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3007                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3008                         SECONDARY_EXEC_WBINVD_EXITING |
3009                         SECONDARY_EXEC_ENABLE_VPID |
3010                         SECONDARY_EXEC_ENABLE_EPT |
3011                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3012                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3013                         SECONDARY_EXEC_RDTSCP |
3014                         SECONDARY_EXEC_ENABLE_INVPCID |
3015                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3016                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3017                         SECONDARY_EXEC_SHADOW_VMCS |
3018                         SECONDARY_EXEC_XSAVES |
3019                         SECONDARY_EXEC_ENABLE_PML;
3020                 if (adjust_vmx_controls(min2, opt2,
3021                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3022                                         &_cpu_based_2nd_exec_control) < 0)
3023                         return -EIO;
3024         }
3025 #ifndef CONFIG_X86_64
3026         if (!(_cpu_based_2nd_exec_control &
3027                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3028                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3029 #endif
3030
3031         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3032                 _cpu_based_2nd_exec_control &= ~(
3033                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3034                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3035                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3036
3037         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3038                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3039                    enabled */
3040                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3041                                              CPU_BASED_CR3_STORE_EXITING |
3042                                              CPU_BASED_INVLPG_EXITING);
3043                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3044                       vmx_capability.ept, vmx_capability.vpid);
3045         }
3046
3047         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3048 #ifdef CONFIG_X86_64
3049         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3050 #endif
3051         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3052                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3053         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3054                                 &_vmexit_control) < 0)
3055                 return -EIO;
3056
3057         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3058         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3059         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3060                                 &_pin_based_exec_control) < 0)
3061                 return -EIO;
3062
3063         if (!(_cpu_based_2nd_exec_control &
3064                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3065                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3066                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3067
3068         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3069         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3070         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3071                                 &_vmentry_control) < 0)
3072                 return -EIO;
3073
3074         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3075
3076         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3077         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3078                 return -EIO;
3079
3080 #ifdef CONFIG_X86_64
3081         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3082         if (vmx_msr_high & (1u<<16))
3083                 return -EIO;
3084 #endif
3085
3086         /* Require Write-Back (WB) memory type for VMCS accesses. */
3087         if (((vmx_msr_high >> 18) & 15) != 6)
3088                 return -EIO;
3089
3090         vmcs_conf->size = vmx_msr_high & 0x1fff;
3091         vmcs_conf->order = get_order(vmcs_config.size);
3092         vmcs_conf->revision_id = vmx_msr_low;
3093
3094         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3095         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3096         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3097         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3098         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3099
3100         cpu_has_load_ia32_efer =
3101                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3102                                 VM_ENTRY_LOAD_IA32_EFER)
3103                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3104                                    VM_EXIT_LOAD_IA32_EFER);
3105
3106         cpu_has_load_perf_global_ctrl =
3107                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3109                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3111
3112         /*
3113          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3114          * but due to arrata below it can't be used. Workaround is to use
3115          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3116          *
3117          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3118          *
3119          * AAK155             (model 26)
3120          * AAP115             (model 30)
3121          * AAT100             (model 37)
3122          * BC86,AAY89,BD102   (model 44)
3123          * BA97               (model 46)
3124          *
3125          */
3126         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3127                 switch (boot_cpu_data.x86_model) {
3128                 case 26:
3129                 case 30:
3130                 case 37:
3131                 case 44:
3132                 case 46:
3133                         cpu_has_load_perf_global_ctrl = false;
3134                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3135                                         "does not work properly. Using workaround\n");
3136                         break;
3137                 default:
3138                         break;
3139                 }
3140         }
3141
3142         if (cpu_has_xsaves)
3143                 rdmsrl(MSR_IA32_XSS, host_xss);
3144
3145         return 0;
3146 }
3147
3148 static struct vmcs *alloc_vmcs_cpu(int cpu)
3149 {
3150         int node = cpu_to_node(cpu);
3151         struct page *pages;
3152         struct vmcs *vmcs;
3153
3154         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3155         if (!pages)
3156                 return NULL;
3157         vmcs = page_address(pages);
3158         memset(vmcs, 0, vmcs_config.size);
3159         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3160         return vmcs;
3161 }
3162
3163 static struct vmcs *alloc_vmcs(void)
3164 {
3165         return alloc_vmcs_cpu(raw_smp_processor_id());
3166 }
3167
3168 static void free_vmcs(struct vmcs *vmcs)
3169 {
3170         free_pages((unsigned long)vmcs, vmcs_config.order);
3171 }
3172
3173 /*
3174  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3175  */
3176 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3177 {
3178         if (!loaded_vmcs->vmcs)
3179                 return;
3180         loaded_vmcs_clear(loaded_vmcs);
3181         free_vmcs(loaded_vmcs->vmcs);
3182         loaded_vmcs->vmcs = NULL;
3183 }
3184
3185 static void free_kvm_area(void)
3186 {
3187         int cpu;
3188
3189         for_each_possible_cpu(cpu) {
3190                 free_vmcs(per_cpu(vmxarea, cpu));
3191                 per_cpu(vmxarea, cpu) = NULL;
3192         }
3193 }
3194
3195 static void init_vmcs_shadow_fields(void)
3196 {
3197         int i, j;
3198
3199         /* No checks for read only fields yet */
3200
3201         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3202                 switch (shadow_read_write_fields[i]) {
3203                 case GUEST_BNDCFGS:
3204                         if (!vmx_mpx_supported())
3205                                 continue;
3206                         break;
3207                 default:
3208                         break;
3209                 }
3210
3211                 if (j < i)
3212                         shadow_read_write_fields[j] =
3213                                 shadow_read_write_fields[i];
3214                 j++;
3215         }
3216         max_shadow_read_write_fields = j;
3217
3218         /* shadowed fields guest access without vmexit */
3219         for (i = 0; i < max_shadow_read_write_fields; i++) {
3220                 clear_bit(shadow_read_write_fields[i],
3221                           vmx_vmwrite_bitmap);
3222                 clear_bit(shadow_read_write_fields[i],
3223                           vmx_vmread_bitmap);
3224         }
3225         for (i = 0; i < max_shadow_read_only_fields; i++)
3226                 clear_bit(shadow_read_only_fields[i],
3227                           vmx_vmread_bitmap);
3228 }
3229
3230 static __init int alloc_kvm_area(void)
3231 {
3232         int cpu;
3233
3234         for_each_possible_cpu(cpu) {
3235                 struct vmcs *vmcs;
3236
3237                 vmcs = alloc_vmcs_cpu(cpu);
3238                 if (!vmcs) {
3239                         free_kvm_area();
3240                         return -ENOMEM;
3241                 }
3242
3243                 per_cpu(vmxarea, cpu) = vmcs;
3244         }
3245         return 0;
3246 }
3247
3248 static bool emulation_required(struct kvm_vcpu *vcpu)
3249 {
3250         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3251 }
3252
3253 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3254                 struct kvm_segment *save)
3255 {
3256         if (!emulate_invalid_guest_state) {
3257                 /*
3258                  * CS and SS RPL should be equal during guest entry according
3259                  * to VMX spec, but in reality it is not always so. Since vcpu
3260                  * is in the middle of the transition from real mode to
3261                  * protected mode it is safe to assume that RPL 0 is a good
3262                  * default value.
3263                  */
3264                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3265                         save->selector &= ~SELECTOR_RPL_MASK;
3266                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3267                 save->s = 1;
3268         }
3269         vmx_set_segment(vcpu, save, seg);
3270 }
3271
3272 static void enter_pmode(struct kvm_vcpu *vcpu)
3273 {
3274         unsigned long flags;
3275         struct vcpu_vmx *vmx = to_vmx(vcpu);
3276
3277         /*
3278          * Update real mode segment cache. It may be not up-to-date if sement
3279          * register was written while vcpu was in a guest mode.
3280          */
3281         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3282         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3283         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3284         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3285         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3286         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3287
3288         vmx->rmode.vm86_active = 0;
3289
3290         vmx_segment_cache_clear(vmx);
3291
3292         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3293
3294         flags = vmcs_readl(GUEST_RFLAGS);
3295         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3296         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3297         vmcs_writel(GUEST_RFLAGS, flags);
3298
3299         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3300                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3301
3302         update_exception_bitmap(vcpu);
3303
3304         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3305         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3306         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3307         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3308         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3309         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3310 }
3311
3312 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3313 {
3314         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3315         struct kvm_segment var = *save;
3316
3317         var.dpl = 0x3;
3318         if (seg == VCPU_SREG_CS)
3319                 var.type = 0x3;
3320
3321         if (!emulate_invalid_guest_state) {
3322                 var.selector = var.base >> 4;
3323                 var.base = var.base & 0xffff0;
3324                 var.limit = 0xffff;
3325                 var.g = 0;
3326                 var.db = 0;
3327                 var.present = 1;
3328                 var.s = 1;
3329                 var.l = 0;
3330                 var.unusable = 0;
3331                 var.type = 0x3;
3332                 var.avl = 0;
3333                 if (save->base & 0xf)
3334                         printk_once(KERN_WARNING "kvm: segment base is not "
3335                                         "paragraph aligned when entering "
3336                                         "protected mode (seg=%d)", seg);
3337         }
3338
3339         vmcs_write16(sf->selector, var.selector);
3340         vmcs_write32(sf->base, var.base);
3341         vmcs_write32(sf->limit, var.limit);
3342         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3343 }
3344
3345 static void enter_rmode(struct kvm_vcpu *vcpu)
3346 {
3347         unsigned long flags;
3348         struct vcpu_vmx *vmx = to_vmx(vcpu);
3349
3350         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3351         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3352         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3353         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3354         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3355         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3356         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3357
3358         vmx->rmode.vm86_active = 1;
3359
3360         /*
3361          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3362          * vcpu. Warn the user that an update is overdue.
3363          */
3364         if (!vcpu->kvm->arch.tss_addr)
3365                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3366                              "called before entering vcpu\n");
3367
3368         vmx_segment_cache_clear(vmx);
3369
3370         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3371         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3372         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3373
3374         flags = vmcs_readl(GUEST_RFLAGS);
3375         vmx->rmode.save_rflags = flags;
3376
3377         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3378
3379         vmcs_writel(GUEST_RFLAGS, flags);
3380         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3381         update_exception_bitmap(vcpu);
3382
3383         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3384         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3385         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3386         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3387         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3388         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3389
3390         kvm_mmu_reset_context(vcpu);
3391 }
3392
3393 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3394 {
3395         struct vcpu_vmx *vmx = to_vmx(vcpu);
3396         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3397
3398         if (!msr)
3399                 return;
3400
3401         /*
3402          * Force kernel_gs_base reloading before EFER changes, as control
3403          * of this msr depends on is_long_mode().
3404          */
3405         vmx_load_host_state(to_vmx(vcpu));
3406         vcpu->arch.efer = efer;
3407         if (efer & EFER_LMA) {
3408                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3409                 msr->data = efer;
3410         } else {
3411                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3412
3413                 msr->data = efer & ~EFER_LME;
3414         }
3415         setup_msrs(vmx);
3416 }
3417
3418 #ifdef CONFIG_X86_64
3419
3420 static void enter_lmode(struct kvm_vcpu *vcpu)
3421 {
3422         u32 guest_tr_ar;
3423
3424         vmx_segment_cache_clear(to_vmx(vcpu));
3425
3426         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3427         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3428                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3429                                      __func__);
3430                 vmcs_write32(GUEST_TR_AR_BYTES,
3431                              (guest_tr_ar & ~AR_TYPE_MASK)
3432                              | AR_TYPE_BUSY_64_TSS);
3433         }
3434         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3435 }
3436
3437 static void exit_lmode(struct kvm_vcpu *vcpu)
3438 {
3439         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3440         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3441 }
3442
3443 #endif
3444
3445 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3446 {
3447         vpid_sync_context(to_vmx(vcpu));
3448         if (enable_ept) {
3449                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3450                         return;
3451                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3452         }
3453 }
3454
3455 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3456 {
3457         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3458
3459         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3460         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3461 }
3462
3463 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3464 {
3465         if (enable_ept && is_paging(vcpu))
3466                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3467         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3468 }
3469
3470 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3471 {
3472         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3473
3474         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3475         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3476 }
3477
3478 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3479 {
3480         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3481
3482         if (!test_bit(VCPU_EXREG_PDPTR,
3483                       (unsigned long *)&vcpu->arch.regs_dirty))
3484                 return;
3485
3486         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3487                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3488                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3489                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3490                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3491         }
3492 }
3493
3494 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3495 {
3496         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3497
3498         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3499                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3500                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3501                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3502                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3503         }
3504
3505         __set_bit(VCPU_EXREG_PDPTR,
3506                   (unsigned long *)&vcpu->arch.regs_avail);
3507         __set_bit(VCPU_EXREG_PDPTR,
3508                   (unsigned long *)&vcpu->arch.regs_dirty);
3509 }
3510
3511 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3512
3513 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3514                                         unsigned long cr0,
3515                                         struct kvm_vcpu *vcpu)
3516 {
3517         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3518                 vmx_decache_cr3(vcpu);
3519         if (!(cr0 & X86_CR0_PG)) {
3520                 /* From paging/starting to nonpaging */
3521                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3522                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3523                              (CPU_BASED_CR3_LOAD_EXITING |
3524                               CPU_BASED_CR3_STORE_EXITING));
3525                 vcpu->arch.cr0 = cr0;
3526                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3527         } else if (!is_paging(vcpu)) {
3528                 /* From nonpaging to paging */
3529                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3530                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3531                              ~(CPU_BASED_CR3_LOAD_EXITING |
3532                                CPU_BASED_CR3_STORE_EXITING));
3533                 vcpu->arch.cr0 = cr0;
3534                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3535         }
3536
3537         if (!(cr0 & X86_CR0_WP))
3538                 *hw_cr0 &= ~X86_CR0_WP;
3539 }
3540
3541 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3542 {
3543         struct vcpu_vmx *vmx = to_vmx(vcpu);
3544         unsigned long hw_cr0;
3545
3546         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3547         if (enable_unrestricted_guest)
3548                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3549         else {
3550                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3551
3552                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3553                         enter_pmode(vcpu);
3554
3555                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3556                         enter_rmode(vcpu);
3557         }
3558
3559 #ifdef CONFIG_X86_64
3560         if (vcpu->arch.efer & EFER_LME) {
3561                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3562                         enter_lmode(vcpu);
3563                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3564                         exit_lmode(vcpu);
3565         }
3566 #endif
3567
3568         if (enable_ept)
3569                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3570
3571         if (!vcpu->fpu_active)
3572                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3573
3574         vmcs_writel(CR0_READ_SHADOW, cr0);
3575         vmcs_writel(GUEST_CR0, hw_cr0);
3576         vcpu->arch.cr0 = cr0;
3577
3578         /* depends on vcpu->arch.cr0 to be set to a new value */
3579         vmx->emulation_required = emulation_required(vcpu);
3580 }
3581
3582 static u64 construct_eptp(unsigned long root_hpa)
3583 {
3584         u64 eptp;
3585
3586         /* TODO write the value reading from MSR */
3587         eptp = VMX_EPT_DEFAULT_MT |
3588                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3589         if (enable_ept_ad_bits)
3590                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3591         eptp |= (root_hpa & PAGE_MASK);
3592
3593         return eptp;
3594 }
3595
3596 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3597 {
3598         unsigned long guest_cr3;
3599         u64 eptp;
3600
3601         guest_cr3 = cr3;
3602         if (enable_ept) {
3603                 eptp = construct_eptp(cr3);
3604                 vmcs_write64(EPT_POINTER, eptp);
3605                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3606                         guest_cr3 = kvm_read_cr3(vcpu);
3607                 else
3608                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3609                 ept_load_pdptrs(vcpu);
3610         }
3611
3612         vmx_flush_tlb(vcpu);
3613         vmcs_writel(GUEST_CR3, guest_cr3);
3614 }
3615
3616 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3617 {
3618         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3619                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3620
3621         if (cr4 & X86_CR4_VMXE) {
3622                 /*
3623                  * To use VMXON (and later other VMX instructions), a guest
3624                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3625                  * So basically the check on whether to allow nested VMX
3626                  * is here.
3627                  */
3628                 if (!nested_vmx_allowed(vcpu))
3629                         return 1;
3630         }
3631         if (to_vmx(vcpu)->nested.vmxon &&
3632             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3633                 return 1;
3634
3635         vcpu->arch.cr4 = cr4;
3636         if (enable_ept) {
3637                 if (!is_paging(vcpu)) {
3638                         hw_cr4 &= ~X86_CR4_PAE;
3639                         hw_cr4 |= X86_CR4_PSE;
3640                         /*
3641                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3642                          * in hardware. However KVM always uses paging mode to
3643                          * emulate guest non-paging mode with TDP.
3644                          * To emulate this behavior, SMEP/SMAP needs to be
3645                          * manually disabled when guest switches to non-paging
3646                          * mode.
3647                          */
3648                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3649                 } else if (!(cr4 & X86_CR4_PAE)) {
3650                         hw_cr4 &= ~X86_CR4_PAE;
3651                 }
3652         }
3653
3654         vmcs_writel(CR4_READ_SHADOW, cr4);
3655         vmcs_writel(GUEST_CR4, hw_cr4);
3656         return 0;
3657 }
3658
3659 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3660                             struct kvm_segment *var, int seg)
3661 {
3662         struct vcpu_vmx *vmx = to_vmx(vcpu);
3663         u32 ar;
3664
3665         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3666                 *var = vmx->rmode.segs[seg];
3667                 if (seg == VCPU_SREG_TR
3668                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3669                         return;
3670                 var->base = vmx_read_guest_seg_base(vmx, seg);
3671                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3672                 return;
3673         }
3674         var->base = vmx_read_guest_seg_base(vmx, seg);
3675         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3676         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3677         ar = vmx_read_guest_seg_ar(vmx, seg);
3678         var->unusable = (ar >> 16) & 1;
3679         var->type = ar & 15;
3680         var->s = (ar >> 4) & 1;
3681         var->dpl = (ar >> 5) & 3;
3682         /*
3683          * Some userspaces do not preserve unusable property. Since usable
3684          * segment has to be present according to VMX spec we can use present
3685          * property to amend userspace bug by making unusable segment always
3686          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3687          * segment as unusable.
3688          */
3689         var->present = !var->unusable;
3690         var->avl = (ar >> 12) & 1;
3691         var->l = (ar >> 13) & 1;
3692         var->db = (ar >> 14) & 1;
3693         var->g = (ar >> 15) & 1;
3694 }
3695
3696 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3697 {
3698         struct kvm_segment s;
3699
3700         if (to_vmx(vcpu)->rmode.vm86_active) {
3701                 vmx_get_segment(vcpu, &s, seg);
3702                 return s.base;
3703         }
3704         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3705 }
3706
3707 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3708 {
3709         struct vcpu_vmx *vmx = to_vmx(vcpu);
3710
3711         if (unlikely(vmx->rmode.vm86_active))
3712                 return 0;
3713         else {
3714                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3715                 return AR_DPL(ar);
3716         }
3717 }
3718
3719 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3720 {
3721         u32 ar;
3722
3723         if (var->unusable || !var->present)
3724                 ar = 1 << 16;
3725         else {
3726                 ar = var->type & 15;
3727                 ar |= (var->s & 1) << 4;
3728                 ar |= (var->dpl & 3) << 5;
3729                 ar |= (var->present & 1) << 7;
3730                 ar |= (var->avl & 1) << 12;
3731                 ar |= (var->l & 1) << 13;
3732                 ar |= (var->db & 1) << 14;
3733                 ar |= (var->g & 1) << 15;
3734         }
3735
3736         return ar;
3737 }
3738
3739 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3740                             struct kvm_segment *var, int seg)
3741 {
3742         struct vcpu_vmx *vmx = to_vmx(vcpu);
3743         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3744
3745         vmx_segment_cache_clear(vmx);
3746
3747         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3748                 vmx->rmode.segs[seg] = *var;
3749                 if (seg == VCPU_SREG_TR)
3750                         vmcs_write16(sf->selector, var->selector);
3751                 else if (var->s)
3752                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3753                 goto out;
3754         }
3755
3756         vmcs_writel(sf->base, var->base);
3757         vmcs_write32(sf->limit, var->limit);
3758         vmcs_write16(sf->selector, var->selector);
3759
3760         /*
3761          *   Fix the "Accessed" bit in AR field of segment registers for older
3762          * qemu binaries.
3763          *   IA32 arch specifies that at the time of processor reset the
3764          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3765          * is setting it to 0 in the userland code. This causes invalid guest
3766          * state vmexit when "unrestricted guest" mode is turned on.
3767          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3768          * tree. Newer qemu binaries with that qemu fix would not need this
3769          * kvm hack.
3770          */
3771         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3772                 var->type |= 0x1; /* Accessed */
3773
3774         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3775
3776 out:
3777         vmx->emulation_required = emulation_required(vcpu);
3778 }
3779
3780 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3781 {
3782         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3783
3784         *db = (ar >> 14) & 1;
3785         *l = (ar >> 13) & 1;
3786 }
3787
3788 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3789 {
3790         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3791         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3792 }
3793
3794 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3795 {
3796         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3797         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3798 }
3799
3800 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3801 {
3802         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3803         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3804 }
3805
3806 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3807 {
3808         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3809         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3810 }
3811
3812 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3813 {
3814         struct kvm_segment var;
3815         u32 ar;
3816
3817         vmx_get_segment(vcpu, &var, seg);
3818         var.dpl = 0x3;
3819         if (seg == VCPU_SREG_CS)
3820                 var.type = 0x3;
3821         ar = vmx_segment_access_rights(&var);
3822
3823         if (var.base != (var.selector << 4))
3824                 return false;
3825         if (var.limit != 0xffff)
3826                 return false;
3827         if (ar != 0xf3)
3828                 return false;
3829
3830         return true;
3831 }
3832
3833 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3834 {
3835         struct kvm_segment cs;
3836         unsigned int cs_rpl;
3837
3838         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3839         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3840
3841         if (cs.unusable)
3842                 return false;
3843         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3844                 return false;
3845         if (!cs.s)
3846                 return false;
3847         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3848                 if (cs.dpl > cs_rpl)
3849                         return false;
3850         } else {
3851                 if (cs.dpl != cs_rpl)
3852                         return false;
3853         }
3854         if (!cs.present)
3855                 return false;
3856
3857         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3858         return true;
3859 }
3860
3861 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3862 {
3863         struct kvm_segment ss;
3864         unsigned int ss_rpl;
3865
3866         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3867         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3868
3869         if (ss.unusable)
3870                 return true;
3871         if (ss.type != 3 && ss.type != 7)
3872                 return false;
3873         if (!ss.s)
3874                 return false;
3875         if (ss.dpl != ss_rpl) /* DPL != RPL */
3876                 return false;
3877         if (!ss.present)
3878                 return false;
3879
3880         return true;
3881 }
3882
3883 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3884 {
3885         struct kvm_segment var;
3886         unsigned int rpl;
3887
3888         vmx_get_segment(vcpu, &var, seg);
3889         rpl = var.selector & SELECTOR_RPL_MASK;
3890
3891         if (var.unusable)
3892                 return true;
3893         if (!var.s)
3894                 return false;
3895         if (!var.present)
3896                 return false;
3897         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3898                 if (var.dpl < rpl) /* DPL < RPL */
3899                         return false;
3900         }
3901
3902         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3903          * rights flags
3904          */
3905         return true;
3906 }
3907
3908 static bool tr_valid(struct kvm_vcpu *vcpu)
3909 {
3910         struct kvm_segment tr;
3911
3912         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3913
3914         if (tr.unusable)
3915                 return false;
3916         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3917                 return false;
3918         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3919                 return false;
3920         if (!tr.present)
3921                 return false;
3922
3923         return true;
3924 }
3925
3926 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3927 {
3928         struct kvm_segment ldtr;
3929
3930         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3931
3932         if (ldtr.unusable)
3933                 return true;
3934         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3935                 return false;
3936         if (ldtr.type != 2)
3937                 return false;
3938         if (!ldtr.present)
3939                 return false;
3940
3941         return true;
3942 }
3943
3944 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3945 {
3946         struct kvm_segment cs, ss;
3947
3948         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3949         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3950
3951         return ((cs.selector & SELECTOR_RPL_MASK) ==
3952                  (ss.selector & SELECTOR_RPL_MASK));
3953 }
3954
3955 /*
3956  * Check if guest state is valid. Returns true if valid, false if
3957  * not.
3958  * We assume that registers are always usable
3959  */
3960 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3961 {
3962         if (enable_unrestricted_guest)
3963                 return true;
3964
3965         /* real mode guest state checks */
3966         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3967                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3968                         return false;
3969                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3970                         return false;
3971                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3972                         return false;
3973                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3974                         return false;
3975                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3976                         return false;
3977                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3978                         return false;
3979         } else {
3980         /* protected mode guest state checks */
3981                 if (!cs_ss_rpl_check(vcpu))
3982                         return false;
3983                 if (!code_segment_valid(vcpu))
3984                         return false;
3985                 if (!stack_segment_valid(vcpu))
3986                         return false;
3987                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3988                         return false;
3989                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3990                         return false;
3991                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3992                         return false;
3993                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3994                         return false;
3995                 if (!tr_valid(vcpu))
3996                         return false;
3997                 if (!ldtr_valid(vcpu))
3998                         return false;
3999         }
4000         /* TODO:
4001          * - Add checks on RIP
4002          * - Add checks on RFLAGS
4003          */
4004
4005         return true;
4006 }
4007
4008 static int init_rmode_tss(struct kvm *kvm)
4009 {
4010         gfn_t fn;
4011         u16 data = 0;
4012         int idx, r;
4013
4014         idx = srcu_read_lock(&kvm->srcu);
4015         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4016         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4017         if (r < 0)
4018                 goto out;
4019         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4020         r = kvm_write_guest_page(kvm, fn++, &data,
4021                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4022         if (r < 0)
4023                 goto out;
4024         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4025         if (r < 0)
4026                 goto out;
4027         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4028         if (r < 0)
4029                 goto out;
4030         data = ~0;
4031         r = kvm_write_guest_page(kvm, fn, &data,
4032                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4033                                  sizeof(u8));
4034 out:
4035         srcu_read_unlock(&kvm->srcu, idx);
4036         return r;
4037 }
4038
4039 static int init_rmode_identity_map(struct kvm *kvm)
4040 {
4041         int i, idx, r = 0;
4042         pfn_t identity_map_pfn;
4043         u32 tmp;
4044
4045         if (!enable_ept)
4046                 return 0;
4047
4048         /* Protect kvm->arch.ept_identity_pagetable_done. */
4049         mutex_lock(&kvm->slots_lock);
4050
4051         if (likely(kvm->arch.ept_identity_pagetable_done))
4052                 goto out2;
4053
4054         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4055
4056         r = alloc_identity_pagetable(kvm);
4057         if (r < 0)
4058                 goto out2;
4059
4060         idx = srcu_read_lock(&kvm->srcu);
4061         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4062         if (r < 0)
4063                 goto out;
4064         /* Set up identity-mapping pagetable for EPT in real mode */
4065         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4066                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4067                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4068                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4069                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4070                 if (r < 0)
4071                         goto out;
4072         }
4073         kvm->arch.ept_identity_pagetable_done = true;
4074
4075 out:
4076         srcu_read_unlock(&kvm->srcu, idx);
4077
4078 out2:
4079         mutex_unlock(&kvm->slots_lock);
4080         return r;
4081 }
4082
4083 static void seg_setup(int seg)
4084 {
4085         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4086         unsigned int ar;
4087
4088         vmcs_write16(sf->selector, 0);
4089         vmcs_writel(sf->base, 0);
4090         vmcs_write32(sf->limit, 0xffff);
4091         ar = 0x93;
4092         if (seg == VCPU_SREG_CS)
4093                 ar |= 0x08; /* code segment */
4094
4095         vmcs_write32(sf->ar_bytes, ar);
4096 }
4097
4098 static int alloc_apic_access_page(struct kvm *kvm)
4099 {
4100         struct page *page;
4101         struct kvm_userspace_memory_region kvm_userspace_mem;
4102         int r = 0;
4103
4104         mutex_lock(&kvm->slots_lock);
4105         if (kvm->arch.apic_access_page_done)
4106                 goto out;
4107         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4108         kvm_userspace_mem.flags = 0;
4109         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4110         kvm_userspace_mem.memory_size = PAGE_SIZE;
4111         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4112         if (r)
4113                 goto out;
4114
4115         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4116         if (is_error_page(page)) {
4117                 r = -EFAULT;
4118                 goto out;
4119         }
4120
4121         /*
4122          * Do not pin the page in memory, so that memory hot-unplug
4123          * is able to migrate it.
4124          */
4125         put_page(page);
4126         kvm->arch.apic_access_page_done = true;
4127 out:
4128         mutex_unlock(&kvm->slots_lock);
4129         return r;
4130 }
4131
4132 static int alloc_identity_pagetable(struct kvm *kvm)
4133 {
4134         /* Called with kvm->slots_lock held. */
4135
4136         struct kvm_userspace_memory_region kvm_userspace_mem;
4137         int r = 0;
4138
4139         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4140
4141         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4142         kvm_userspace_mem.flags = 0;
4143         kvm_userspace_mem.guest_phys_addr =
4144                 kvm->arch.ept_identity_map_addr;
4145         kvm_userspace_mem.memory_size = PAGE_SIZE;
4146         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4147
4148         return r;
4149 }
4150
4151 static void allocate_vpid(struct vcpu_vmx *vmx)
4152 {
4153         int vpid;
4154
4155         vmx->vpid = 0;
4156         if (!enable_vpid)
4157                 return;
4158         spin_lock(&vmx_vpid_lock);
4159         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4160         if (vpid < VMX_NR_VPIDS) {
4161                 vmx->vpid = vpid;
4162                 __set_bit(vpid, vmx_vpid_bitmap);
4163         }
4164         spin_unlock(&vmx_vpid_lock);
4165 }
4166
4167 static void free_vpid(struct vcpu_vmx *vmx)
4168 {
4169         if (!enable_vpid)
4170                 return;
4171         spin_lock(&vmx_vpid_lock);
4172         if (vmx->vpid != 0)
4173                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4174         spin_unlock(&vmx_vpid_lock);
4175 }
4176
4177 #define MSR_TYPE_R      1
4178 #define MSR_TYPE_W      2
4179 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4180                                                 u32 msr, int type)
4181 {
4182         int f = sizeof(unsigned long);
4183
4184         if (!cpu_has_vmx_msr_bitmap())
4185                 return;
4186
4187         /*
4188          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4189          * have the write-low and read-high bitmap offsets the wrong way round.
4190          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4191          */
4192         if (msr <= 0x1fff) {
4193                 if (type & MSR_TYPE_R)
4194                         /* read-low */
4195                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4196
4197                 if (type & MSR_TYPE_W)
4198                         /* write-low */
4199                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4200
4201         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4202                 msr &= 0x1fff;
4203                 if (type & MSR_TYPE_R)
4204                         /* read-high */
4205                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4206
4207                 if (type & MSR_TYPE_W)
4208                         /* write-high */
4209                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4210
4211         }
4212 }
4213
4214 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4215                                                 u32 msr, int type)
4216 {
4217         int f = sizeof(unsigned long);
4218
4219         if (!cpu_has_vmx_msr_bitmap())
4220                 return;
4221
4222         /*
4223          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4224          * have the write-low and read-high bitmap offsets the wrong way round.
4225          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4226          */
4227         if (msr <= 0x1fff) {
4228                 if (type & MSR_TYPE_R)
4229                         /* read-low */
4230                         __set_bit(msr, msr_bitmap + 0x000 / f);
4231
4232                 if (type & MSR_TYPE_W)
4233                         /* write-low */
4234                         __set_bit(msr, msr_bitmap + 0x800 / f);
4235
4236         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4237                 msr &= 0x1fff;
4238                 if (type & MSR_TYPE_R)
4239                         /* read-high */
4240                         __set_bit(msr, msr_bitmap + 0x400 / f);
4241
4242                 if (type & MSR_TYPE_W)
4243                         /* write-high */
4244                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4245
4246         }
4247 }
4248
4249 /*
4250  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4251  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4252  */
4253 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4254                                                unsigned long *msr_bitmap_nested,
4255                                                u32 msr, int type)
4256 {
4257         int f = sizeof(unsigned long);
4258
4259         if (!cpu_has_vmx_msr_bitmap()) {
4260                 WARN_ON(1);
4261                 return;
4262         }
4263
4264         /*
4265          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4266          * have the write-low and read-high bitmap offsets the wrong way round.
4267          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4268          */
4269         if (msr <= 0x1fff) {
4270                 if (type & MSR_TYPE_R &&
4271                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4272                         /* read-low */
4273                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4274
4275                 if (type & MSR_TYPE_W &&
4276                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4277                         /* write-low */
4278                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4279
4280         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4281                 msr &= 0x1fff;
4282                 if (type & MSR_TYPE_R &&
4283                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4284                         /* read-high */
4285                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4286
4287                 if (type & MSR_TYPE_W &&
4288                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4289                         /* write-high */
4290                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4291
4292         }
4293 }
4294
4295 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4296 {
4297         if (!longmode_only)
4298                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4299                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4300         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4301                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4302 }
4303
4304 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4305 {
4306         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4307                         msr, MSR_TYPE_R);
4308         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4309                         msr, MSR_TYPE_R);
4310 }
4311
4312 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4313 {
4314         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4315                         msr, MSR_TYPE_R);
4316         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4317                         msr, MSR_TYPE_R);
4318 }
4319
4320 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4321 {
4322         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4323                         msr, MSR_TYPE_W);
4324         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4325                         msr, MSR_TYPE_W);
4326 }
4327
4328 static int vmx_vm_has_apicv(struct kvm *kvm)
4329 {
4330         return enable_apicv && irqchip_in_kernel(kvm);
4331 }
4332
4333 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4334 {
4335         struct vcpu_vmx *vmx = to_vmx(vcpu);
4336         int max_irr;
4337         void *vapic_page;
4338         u16 status;
4339
4340         if (vmx->nested.pi_desc &&
4341             vmx->nested.pi_pending) {
4342                 vmx->nested.pi_pending = false;
4343                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4344                         return 0;
4345
4346                 max_irr = find_last_bit(
4347                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4348
4349                 if (max_irr == 256)
4350                         return 0;
4351
4352                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4353                 if (!vapic_page) {
4354                         WARN_ON(1);
4355                         return -ENOMEM;
4356                 }
4357                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4358                 kunmap(vmx->nested.virtual_apic_page);
4359
4360                 status = vmcs_read16(GUEST_INTR_STATUS);
4361                 if ((u8)max_irr > ((u8)status & 0xff)) {
4362                         status &= ~0xff;
4363                         status |= (u8)max_irr;
4364                         vmcs_write16(GUEST_INTR_STATUS, status);
4365                 }
4366         }
4367         return 0;
4368 }
4369
4370 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4371 {
4372 #ifdef CONFIG_SMP
4373         if (vcpu->mode == IN_GUEST_MODE) {
4374                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4375                                 POSTED_INTR_VECTOR);
4376                 return true;
4377         }
4378 #endif
4379         return false;
4380 }
4381
4382 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4383                                                 int vector)
4384 {
4385         struct vcpu_vmx *vmx = to_vmx(vcpu);
4386
4387         if (is_guest_mode(vcpu) &&
4388             vector == vmx->nested.posted_intr_nv) {
4389                 /* the PIR and ON have been set by L1. */
4390                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4391                 /*
4392                  * If a posted intr is not recognized by hardware,
4393                  * we will accomplish it in the next vmentry.
4394                  */
4395                 vmx->nested.pi_pending = true;
4396                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4397                 return 0;
4398         }
4399         return -1;
4400 }
4401 /*
4402  * Send interrupt to vcpu via posted interrupt way.
4403  * 1. If target vcpu is running(non-root mode), send posted interrupt
4404  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4405  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4406  * interrupt from PIR in next vmentry.
4407  */
4408 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4409 {
4410         struct vcpu_vmx *vmx = to_vmx(vcpu);
4411         int r;
4412
4413         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4414         if (!r)
4415                 return;
4416
4417         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4418                 return;
4419
4420         r = pi_test_and_set_on(&vmx->pi_desc);
4421         kvm_make_request(KVM_REQ_EVENT, vcpu);
4422         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4423                 kvm_vcpu_kick(vcpu);
4424 }
4425
4426 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4427 {
4428         struct vcpu_vmx *vmx = to_vmx(vcpu);
4429
4430         if (!pi_test_and_clear_on(&vmx->pi_desc))
4431                 return;
4432
4433         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4434 }
4435
4436 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4437 {
4438         return;
4439 }
4440
4441 /*
4442  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4443  * will not change in the lifetime of the guest.
4444  * Note that host-state that does change is set elsewhere. E.g., host-state
4445  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4446  */
4447 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4448 {
4449         u32 low32, high32;
4450         unsigned long tmpl;
4451         struct desc_ptr dt;
4452         unsigned long cr4;
4453
4454         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4455         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4456
4457         /* Save the most likely value for this task's CR4 in the VMCS. */
4458         cr4 = cr4_read_shadow();
4459         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4460         vmx->host_state.vmcs_host_cr4 = cr4;
4461
4462         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4463 #ifdef CONFIG_X86_64
4464         /*
4465          * Load null selectors, so we can avoid reloading them in
4466          * __vmx_load_host_state(), in case userspace uses the null selectors
4467          * too (the expected case).
4468          */
4469         vmcs_write16(HOST_DS_SELECTOR, 0);
4470         vmcs_write16(HOST_ES_SELECTOR, 0);
4471 #else
4472         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4473         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4474 #endif
4475         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4476         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4477
4478         native_store_idt(&dt);
4479         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4480         vmx->host_idt_base = dt.address;
4481
4482         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4483
4484         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4485         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4486         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4487         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4488
4489         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4490                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4491                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4492         }
4493 }
4494
4495 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4496 {
4497         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4498         if (enable_ept)
4499                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4500         if (is_guest_mode(&vmx->vcpu))
4501                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4502                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4503         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4504 }
4505
4506 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4507 {
4508         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4509
4510         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4511                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4512         return pin_based_exec_ctrl;
4513 }
4514
4515 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4516 {
4517         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4518
4519         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4520                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4521
4522         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4523                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4524 #ifdef CONFIG_X86_64
4525                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4526                                 CPU_BASED_CR8_LOAD_EXITING;
4527 #endif
4528         }
4529         if (!enable_ept)
4530                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4531                                 CPU_BASED_CR3_LOAD_EXITING  |
4532                                 CPU_BASED_INVLPG_EXITING;
4533         return exec_control;
4534 }
4535
4536 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4537 {
4538         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4539         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4540                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4541         if (vmx->vpid == 0)
4542                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4543         if (!enable_ept) {
4544                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4545                 enable_unrestricted_guest = 0;
4546                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4547                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4548         }
4549         if (!enable_unrestricted_guest)
4550                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4551         if (!ple_gap)
4552                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4553         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4554                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4555                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4556         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4557         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4558            (handle_vmptrld).
4559            We can NOT enable shadow_vmcs here because we don't have yet
4560            a current VMCS12
4561         */
4562         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4563         /* PML is enabled/disabled in creating/destorying vcpu */
4564         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4565
4566         return exec_control;
4567 }
4568
4569 static void ept_set_mmio_spte_mask(void)
4570 {
4571         /*
4572          * EPT Misconfigurations can be generated if the value of bits 2:0
4573          * of an EPT paging-structure entry is 110b (write/execute).
4574          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4575          * spte.
4576          */
4577         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4578 }
4579
4580 #define VMX_XSS_EXIT_BITMAP 0
4581 /*
4582  * Sets up the vmcs for emulated real mode.
4583  */
4584 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4585 {
4586 #ifdef CONFIG_X86_64
4587         unsigned long a;
4588 #endif
4589         int i;
4590
4591         /* I/O */
4592         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4593         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4594
4595         if (enable_shadow_vmcs) {
4596                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4597                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4598         }
4599         if (cpu_has_vmx_msr_bitmap())
4600                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4601
4602         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4603
4604         /* Control */
4605         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4606
4607         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4608
4609         if (cpu_has_secondary_exec_ctrls()) {
4610                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4611                                 vmx_secondary_exec_control(vmx));
4612         }
4613
4614         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4615                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4616                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4617                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4618                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4619
4620                 vmcs_write16(GUEST_INTR_STATUS, 0);
4621
4622                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4623                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4624         }
4625
4626         if (ple_gap) {
4627                 vmcs_write32(PLE_GAP, ple_gap);
4628                 vmx->ple_window = ple_window;
4629                 vmx->ple_window_dirty = true;
4630         }
4631
4632         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4633         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4634         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4635
4636         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4637         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4638         vmx_set_constant_host_state(vmx);
4639 #ifdef CONFIG_X86_64
4640         rdmsrl(MSR_FS_BASE, a);
4641         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4642         rdmsrl(MSR_GS_BASE, a);
4643         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4644 #else
4645         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4646         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4647 #endif
4648
4649         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4650         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4651         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4652         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4653         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4654
4655         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4656                 u32 msr_low, msr_high;
4657                 u64 host_pat;
4658                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4659                 host_pat = msr_low | ((u64) msr_high << 32);
4660                 /* Write the default value follow host pat */
4661                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4662                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4663                 vmx->vcpu.arch.pat = host_pat;
4664         }
4665
4666         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4667                 u32 index = vmx_msr_index[i];
4668                 u32 data_low, data_high;
4669                 int j = vmx->nmsrs;
4670
4671                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4672                         continue;
4673                 if (wrmsr_safe(index, data_low, data_high) < 0)
4674                         continue;
4675                 vmx->guest_msrs[j].index = i;
4676                 vmx->guest_msrs[j].data = 0;
4677                 vmx->guest_msrs[j].mask = -1ull;
4678                 ++vmx->nmsrs;
4679         }
4680
4681
4682         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4683
4684         /* 22.2.1, 20.8.1 */
4685         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4686
4687         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4688         set_cr4_guest_host_mask(vmx);
4689
4690         if (vmx_xsaves_supported())
4691                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4692
4693         return 0;
4694 }
4695
4696 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4697 {
4698         struct vcpu_vmx *vmx = to_vmx(vcpu);
4699         struct msr_data apic_base_msr;
4700
4701         vmx->rmode.vm86_active = 0;
4702
4703         vmx->soft_vnmi_blocked = 0;
4704
4705         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4706         kvm_set_cr8(&vmx->vcpu, 0);
4707         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4708         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4709                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4710         apic_base_msr.host_initiated = true;
4711         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4712
4713         vmx_segment_cache_clear(vmx);
4714
4715         seg_setup(VCPU_SREG_CS);
4716         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4717         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4718
4719         seg_setup(VCPU_SREG_DS);
4720         seg_setup(VCPU_SREG_ES);
4721         seg_setup(VCPU_SREG_FS);
4722         seg_setup(VCPU_SREG_GS);
4723         seg_setup(VCPU_SREG_SS);
4724
4725         vmcs_write16(GUEST_TR_SELECTOR, 0);
4726         vmcs_writel(GUEST_TR_BASE, 0);
4727         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4728         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4729
4730         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4731         vmcs_writel(GUEST_LDTR_BASE, 0);
4732         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4733         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4734
4735         vmcs_write32(GUEST_SYSENTER_CS, 0);
4736         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4737         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4738
4739         vmcs_writel(GUEST_RFLAGS, 0x02);
4740         kvm_rip_write(vcpu, 0xfff0);
4741
4742         vmcs_writel(GUEST_GDTR_BASE, 0);
4743         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4744
4745         vmcs_writel(GUEST_IDTR_BASE, 0);
4746         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4747
4748         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4749         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4750         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4751
4752         /* Special registers */
4753         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4754
4755         setup_msrs(vmx);
4756
4757         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4758
4759         if (cpu_has_vmx_tpr_shadow()) {
4760                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4761                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4762                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4763                                      __pa(vmx->vcpu.arch.apic->regs));
4764                 vmcs_write32(TPR_THRESHOLD, 0);
4765         }
4766
4767         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4768
4769         if (vmx_vm_has_apicv(vcpu->kvm))
4770                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4771
4772         if (vmx->vpid != 0)
4773                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4774
4775         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4776         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4777         vmx_set_cr4(&vmx->vcpu, 0);
4778         vmx_set_efer(&vmx->vcpu, 0);
4779         vmx_fpu_activate(&vmx->vcpu);
4780         update_exception_bitmap(&vmx->vcpu);
4781
4782         vpid_sync_context(vmx);
4783 }
4784
4785 /*
4786  * In nested virtualization, check if L1 asked to exit on external interrupts.
4787  * For most existing hypervisors, this will always return true.
4788  */
4789 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4790 {
4791         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4792                 PIN_BASED_EXT_INTR_MASK;
4793 }
4794
4795 /*
4796  * In nested virtualization, check if L1 has set
4797  * VM_EXIT_ACK_INTR_ON_EXIT
4798  */
4799 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4800 {
4801         return get_vmcs12(vcpu)->vm_exit_controls &
4802                 VM_EXIT_ACK_INTR_ON_EXIT;
4803 }
4804
4805 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4806 {
4807         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4808                 PIN_BASED_NMI_EXITING;
4809 }
4810
4811 static void enable_irq_window(struct kvm_vcpu *vcpu)
4812 {
4813         u32 cpu_based_vm_exec_control;
4814
4815         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4816         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4817         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4818 }
4819
4820 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4821 {
4822         u32 cpu_based_vm_exec_control;
4823
4824         if (!cpu_has_virtual_nmis() ||
4825             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4826                 enable_irq_window(vcpu);
4827                 return;
4828         }
4829
4830         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4831         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4832         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4833 }
4834
4835 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4836 {
4837         struct vcpu_vmx *vmx = to_vmx(vcpu);
4838         uint32_t intr;
4839         int irq = vcpu->arch.interrupt.nr;
4840
4841         trace_kvm_inj_virq(irq);
4842
4843         ++vcpu->stat.irq_injections;
4844         if (vmx->rmode.vm86_active) {
4845                 int inc_eip = 0;
4846                 if (vcpu->arch.interrupt.soft)
4847                         inc_eip = vcpu->arch.event_exit_inst_len;
4848                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4849                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4850                 return;
4851         }
4852         intr = irq | INTR_INFO_VALID_MASK;
4853         if (vcpu->arch.interrupt.soft) {
4854                 intr |= INTR_TYPE_SOFT_INTR;
4855                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4856                              vmx->vcpu.arch.event_exit_inst_len);
4857         } else
4858                 intr |= INTR_TYPE_EXT_INTR;
4859         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4860 }
4861
4862 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4863 {
4864         struct vcpu_vmx *vmx = to_vmx(vcpu);
4865
4866         if (is_guest_mode(vcpu))
4867                 return;
4868
4869         if (!cpu_has_virtual_nmis()) {
4870                 /*
4871                  * Tracking the NMI-blocked state in software is built upon
4872                  * finding the next open IRQ window. This, in turn, depends on
4873                  * well-behaving guests: They have to keep IRQs disabled at
4874                  * least as long as the NMI handler runs. Otherwise we may
4875                  * cause NMI nesting, maybe breaking the guest. But as this is
4876                  * highly unlikely, we can live with the residual risk.
4877                  */
4878                 vmx->soft_vnmi_blocked = 1;
4879                 vmx->vnmi_blocked_time = 0;
4880         }
4881
4882         ++vcpu->stat.nmi_injections;
4883         vmx->nmi_known_unmasked = false;
4884         if (vmx->rmode.vm86_active) {
4885                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4886                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4887                 return;
4888         }
4889         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4890                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4891 }
4892
4893 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4894 {
4895         if (!cpu_has_virtual_nmis())
4896                 return to_vmx(vcpu)->soft_vnmi_blocked;
4897         if (to_vmx(vcpu)->nmi_known_unmasked)
4898                 return false;
4899         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4900 }
4901
4902 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4903 {
4904         struct vcpu_vmx *vmx = to_vmx(vcpu);
4905
4906         if (!cpu_has_virtual_nmis()) {
4907                 if (vmx->soft_vnmi_blocked != masked) {
4908                         vmx->soft_vnmi_blocked = masked;
4909                         vmx->vnmi_blocked_time = 0;
4910                 }
4911         } else {
4912                 vmx->nmi_known_unmasked = !masked;
4913                 if (masked)
4914                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4915                                       GUEST_INTR_STATE_NMI);
4916                 else
4917                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4918                                         GUEST_INTR_STATE_NMI);
4919         }
4920 }
4921
4922 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4923 {
4924         if (to_vmx(vcpu)->nested.nested_run_pending)
4925                 return 0;
4926
4927         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4928                 return 0;
4929
4930         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4931                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4932                    | GUEST_INTR_STATE_NMI));
4933 }
4934
4935 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4936 {
4937         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4938                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4939                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4940                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4941 }
4942
4943 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4944 {
4945         int ret;
4946         struct kvm_userspace_memory_region tss_mem = {
4947                 .slot = TSS_PRIVATE_MEMSLOT,
4948                 .guest_phys_addr = addr,
4949                 .memory_size = PAGE_SIZE * 3,
4950                 .flags = 0,
4951         };
4952
4953         ret = kvm_set_memory_region(kvm, &tss_mem);
4954         if (ret)
4955                 return ret;
4956         kvm->arch.tss_addr = addr;
4957         return init_rmode_tss(kvm);
4958 }
4959
4960 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4961 {
4962         switch (vec) {
4963         case BP_VECTOR:
4964                 /*
4965                  * Update instruction length as we may reinject the exception
4966                  * from user space while in guest debugging mode.
4967                  */
4968                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4969                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4970                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4971                         return false;
4972                 /* fall through */
4973         case DB_VECTOR:
4974                 if (vcpu->guest_debug &
4975                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4976                         return false;
4977                 /* fall through */
4978         case DE_VECTOR:
4979         case OF_VECTOR:
4980         case BR_VECTOR:
4981         case UD_VECTOR:
4982         case DF_VECTOR:
4983         case SS_VECTOR:
4984         case GP_VECTOR:
4985         case MF_VECTOR:
4986                 return true;
4987         break;
4988         }
4989         return false;
4990 }
4991
4992 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4993                                   int vec, u32 err_code)
4994 {
4995         /*
4996          * Instruction with address size override prefix opcode 0x67
4997          * Cause the #SS fault with 0 error code in VM86 mode.
4998          */
4999         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5000                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5001                         if (vcpu->arch.halt_request) {
5002                                 vcpu->arch.halt_request = 0;
5003                                 return kvm_vcpu_halt(vcpu);
5004                         }
5005                         return 1;
5006                 }
5007                 return 0;
5008         }
5009
5010         /*
5011          * Forward all other exceptions that are valid in real mode.
5012          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5013          *        the required debugging infrastructure rework.
5014          */
5015         kvm_queue_exception(vcpu, vec);
5016         return 1;
5017 }
5018
5019 /*
5020  * Trigger machine check on the host. We assume all the MSRs are already set up
5021  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5022  * We pass a fake environment to the machine check handler because we want
5023  * the guest to be always treated like user space, no matter what context
5024  * it used internally.
5025  */
5026 static void kvm_machine_check(void)
5027 {
5028 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5029         struct pt_regs regs = {
5030                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5031                 .flags = X86_EFLAGS_IF,
5032         };
5033
5034         do_machine_check(&regs, 0);
5035 #endif
5036 }
5037
5038 static int handle_machine_check(struct kvm_vcpu *vcpu)
5039 {
5040         /* already handled by vcpu_run */
5041         return 1;
5042 }
5043
5044 static int handle_exception(struct kvm_vcpu *vcpu)
5045 {
5046         struct vcpu_vmx *vmx = to_vmx(vcpu);
5047         struct kvm_run *kvm_run = vcpu->run;
5048         u32 intr_info, ex_no, error_code;
5049         unsigned long cr2, rip, dr6;
5050         u32 vect_info;
5051         enum emulation_result er;
5052
5053         vect_info = vmx->idt_vectoring_info;
5054         intr_info = vmx->exit_intr_info;
5055
5056         if (is_machine_check(intr_info))
5057                 return handle_machine_check(vcpu);
5058
5059         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5060                 return 1;  /* already handled by vmx_vcpu_run() */
5061
5062         if (is_no_device(intr_info)) {
5063                 vmx_fpu_activate(vcpu);
5064                 return 1;
5065         }
5066
5067         if (is_invalid_opcode(intr_info)) {
5068                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5069                 if (er != EMULATE_DONE)
5070                         kvm_queue_exception(vcpu, UD_VECTOR);
5071                 return 1;
5072         }
5073
5074         error_code = 0;
5075         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5076                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5077
5078         /*
5079          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5080          * MMIO, it is better to report an internal error.
5081          * See the comments in vmx_handle_exit.
5082          */
5083         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5084             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5085                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5086                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5087                 vcpu->run->internal.ndata = 2;
5088                 vcpu->run->internal.data[0] = vect_info;
5089                 vcpu->run->internal.data[1] = intr_info;
5090                 return 0;
5091         }
5092
5093         if (is_page_fault(intr_info)) {
5094                 /* EPT won't cause page fault directly */
5095                 BUG_ON(enable_ept);
5096                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5097                 trace_kvm_page_fault(cr2, error_code);
5098
5099                 if (kvm_event_needs_reinjection(vcpu))
5100                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5101                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5102         }
5103
5104         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5105
5106         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5107                 return handle_rmode_exception(vcpu, ex_no, error_code);
5108
5109         switch (ex_no) {
5110         case DB_VECTOR:
5111                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5112                 if (!(vcpu->guest_debug &
5113                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5114                         vcpu->arch.dr6 &= ~15;
5115                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5116                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5117                                 skip_emulated_instruction(vcpu);
5118
5119                         kvm_queue_exception(vcpu, DB_VECTOR);
5120                         return 1;
5121                 }
5122                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5123                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5124                 /* fall through */
5125         case BP_VECTOR:
5126                 /*
5127                  * Update instruction length as we may reinject #BP from
5128                  * user space while in guest debugging mode. Reading it for
5129                  * #DB as well causes no harm, it is not used in that case.
5130                  */
5131                 vmx->vcpu.arch.event_exit_inst_len =
5132                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5133                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5134                 rip = kvm_rip_read(vcpu);
5135                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5136                 kvm_run->debug.arch.exception = ex_no;
5137                 break;
5138         default:
5139                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5140                 kvm_run->ex.exception = ex_no;
5141                 kvm_run->ex.error_code = error_code;
5142                 break;
5143         }
5144         return 0;
5145 }
5146
5147 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5148 {
5149         ++vcpu->stat.irq_exits;
5150         return 1;
5151 }
5152
5153 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5154 {
5155         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5156         return 0;
5157 }
5158
5159 static int handle_io(struct kvm_vcpu *vcpu)
5160 {
5161         unsigned long exit_qualification;
5162         int size, in, string;
5163         unsigned port;
5164
5165         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5166         string = (exit_qualification & 16) != 0;
5167         in = (exit_qualification & 8) != 0;
5168
5169         ++vcpu->stat.io_exits;
5170
5171         if (string || in)
5172                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5173
5174         port = exit_qualification >> 16;
5175         size = (exit_qualification & 7) + 1;
5176         skip_emulated_instruction(vcpu);
5177
5178         return kvm_fast_pio_out(vcpu, size, port);
5179 }
5180
5181 static void
5182 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5183 {
5184         /*
5185          * Patch in the VMCALL instruction:
5186          */
5187         hypercall[0] = 0x0f;
5188         hypercall[1] = 0x01;
5189         hypercall[2] = 0xc1;
5190 }
5191
5192 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5193 {
5194         unsigned long always_on = VMXON_CR0_ALWAYSON;
5195         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5196
5197         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5198                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5199             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5200                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5201         return (val & always_on) == always_on;
5202 }
5203
5204 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5205 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5206 {
5207         if (is_guest_mode(vcpu)) {
5208                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5209                 unsigned long orig_val = val;
5210
5211                 /*
5212                  * We get here when L2 changed cr0 in a way that did not change
5213                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5214                  * but did change L0 shadowed bits. So we first calculate the
5215                  * effective cr0 value that L1 would like to write into the
5216                  * hardware. It consists of the L2-owned bits from the new
5217                  * value combined with the L1-owned bits from L1's guest_cr0.
5218                  */
5219                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5220                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5221
5222                 if (!nested_cr0_valid(vcpu, val))
5223                         return 1;
5224
5225                 if (kvm_set_cr0(vcpu, val))
5226                         return 1;
5227                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5228                 return 0;
5229         } else {
5230                 if (to_vmx(vcpu)->nested.vmxon &&
5231                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5232                         return 1;
5233                 return kvm_set_cr0(vcpu, val);
5234         }
5235 }
5236
5237 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5238 {
5239         if (is_guest_mode(vcpu)) {
5240                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5241                 unsigned long orig_val = val;
5242
5243                 /* analogously to handle_set_cr0 */
5244                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5245                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5246                 if (kvm_set_cr4(vcpu, val))
5247                         return 1;
5248                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5249                 return 0;
5250         } else
5251                 return kvm_set_cr4(vcpu, val);
5252 }
5253
5254 /* called to set cr0 as approriate for clts instruction exit. */
5255 static void handle_clts(struct kvm_vcpu *vcpu)
5256 {
5257         if (is_guest_mode(vcpu)) {
5258                 /*
5259                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5260                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5261                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5262                  */
5263                 vmcs_writel(CR0_READ_SHADOW,
5264                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5265                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5266         } else
5267                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5268 }
5269
5270 static int handle_cr(struct kvm_vcpu *vcpu)
5271 {
5272         unsigned long exit_qualification, val;
5273         int cr;
5274         int reg;
5275         int err;
5276
5277         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5278         cr = exit_qualification & 15;
5279         reg = (exit_qualification >> 8) & 15;
5280         switch ((exit_qualification >> 4) & 3) {
5281         case 0: /* mov to cr */
5282                 val = kvm_register_readl(vcpu, reg);
5283                 trace_kvm_cr_write(cr, val);
5284                 switch (cr) {
5285                 case 0:
5286                         err = handle_set_cr0(vcpu, val);
5287                         kvm_complete_insn_gp(vcpu, err);
5288                         return 1;
5289                 case 3:
5290                         err = kvm_set_cr3(vcpu, val);
5291                         kvm_complete_insn_gp(vcpu, err);
5292                         return 1;
5293                 case 4:
5294                         err = handle_set_cr4(vcpu, val);
5295                         kvm_complete_insn_gp(vcpu, err);
5296                         return 1;
5297                 case 8: {
5298                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5299                                 u8 cr8 = (u8)val;
5300                                 err = kvm_set_cr8(vcpu, cr8);
5301                                 kvm_complete_insn_gp(vcpu, err);
5302                                 if (irqchip_in_kernel(vcpu->kvm))
5303                                         return 1;
5304                                 if (cr8_prev <= cr8)
5305                                         return 1;
5306                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5307                                 return 0;
5308                         }
5309                 }
5310                 break;
5311         case 2: /* clts */
5312                 handle_clts(vcpu);
5313                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5314                 skip_emulated_instruction(vcpu);
5315                 vmx_fpu_activate(vcpu);
5316                 return 1;
5317         case 1: /*mov from cr*/
5318                 switch (cr) {
5319                 case 3:
5320                         val = kvm_read_cr3(vcpu);
5321                         kvm_register_write(vcpu, reg, val);
5322                         trace_kvm_cr_read(cr, val);
5323                         skip_emulated_instruction(vcpu);
5324                         return 1;
5325                 case 8:
5326                         val = kvm_get_cr8(vcpu);
5327                         kvm_register_write(vcpu, reg, val);
5328                         trace_kvm_cr_read(cr, val);
5329                         skip_emulated_instruction(vcpu);
5330                         return 1;
5331                 }
5332                 break;
5333         case 3: /* lmsw */
5334                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5335                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5336                 kvm_lmsw(vcpu, val);
5337
5338                 skip_emulated_instruction(vcpu);
5339                 return 1;
5340         default:
5341                 break;
5342         }
5343         vcpu->run->exit_reason = 0;
5344         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5345                (int)(exit_qualification >> 4) & 3, cr);
5346         return 0;
5347 }
5348
5349 static int handle_dr(struct kvm_vcpu *vcpu)
5350 {
5351         unsigned long exit_qualification;
5352         int dr, dr7, reg;
5353
5354         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5355         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5356
5357         /* First, if DR does not exist, trigger UD */
5358         if (!kvm_require_dr(vcpu, dr))
5359                 return 1;
5360
5361         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5362         if (!kvm_require_cpl(vcpu, 0))
5363                 return 1;
5364         dr7 = vmcs_readl(GUEST_DR7);
5365         if (dr7 & DR7_GD) {
5366                 /*
5367                  * As the vm-exit takes precedence over the debug trap, we
5368                  * need to emulate the latter, either for the host or the
5369                  * guest debugging itself.
5370                  */
5371                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5372                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5373                         vcpu->run->debug.arch.dr7 = dr7;
5374                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5375                         vcpu->run->debug.arch.exception = DB_VECTOR;
5376                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5377                         return 0;
5378                 } else {
5379                         vcpu->arch.dr6 &= ~15;
5380                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5381                         kvm_queue_exception(vcpu, DB_VECTOR);
5382                         return 1;
5383                 }
5384         }
5385
5386         if (vcpu->guest_debug == 0) {
5387                 u32 cpu_based_vm_exec_control;
5388
5389                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5390                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5391                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5392
5393                 /*
5394                  * No more DR vmexits; force a reload of the debug registers
5395                  * and reenter on this instruction.  The next vmexit will
5396                  * retrieve the full state of the debug registers.
5397                  */
5398                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5399                 return 1;
5400         }
5401
5402         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5403         if (exit_qualification & TYPE_MOV_FROM_DR) {
5404                 unsigned long val;
5405
5406                 if (kvm_get_dr(vcpu, dr, &val))
5407                         return 1;
5408                 kvm_register_write(vcpu, reg, val);
5409         } else
5410                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5411                         return 1;
5412
5413         skip_emulated_instruction(vcpu);
5414         return 1;
5415 }
5416
5417 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5418 {
5419         return vcpu->arch.dr6;
5420 }
5421
5422 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5423 {
5424 }
5425
5426 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5427 {
5428         u32 cpu_based_vm_exec_control;
5429
5430         get_debugreg(vcpu->arch.db[0], 0);
5431         get_debugreg(vcpu->arch.db[1], 1);
5432         get_debugreg(vcpu->arch.db[2], 2);
5433         get_debugreg(vcpu->arch.db[3], 3);
5434         get_debugreg(vcpu->arch.dr6, 6);
5435         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5436
5437         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5438
5439         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5440         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5441         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5442 }
5443
5444 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5445 {
5446         vmcs_writel(GUEST_DR7, val);
5447 }
5448
5449 static int handle_cpuid(struct kvm_vcpu *vcpu)
5450 {
5451         kvm_emulate_cpuid(vcpu);
5452         return 1;
5453 }
5454
5455 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5456 {
5457         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5458         u64 data;
5459
5460         if (vmx_get_msr(vcpu, ecx, &data)) {
5461                 trace_kvm_msr_read_ex(ecx);
5462                 kvm_inject_gp(vcpu, 0);
5463                 return 1;
5464         }
5465
5466         trace_kvm_msr_read(ecx, data);
5467
5468         /* FIXME: handling of bits 32:63 of rax, rdx */
5469         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5470         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5471         skip_emulated_instruction(vcpu);
5472         return 1;
5473 }
5474
5475 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5476 {
5477         struct msr_data msr;
5478         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5479         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5480                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5481
5482         msr.data = data;
5483         msr.index = ecx;
5484         msr.host_initiated = false;
5485         if (kvm_set_msr(vcpu, &msr) != 0) {
5486                 trace_kvm_msr_write_ex(ecx, data);
5487                 kvm_inject_gp(vcpu, 0);
5488                 return 1;
5489         }
5490
5491         trace_kvm_msr_write(ecx, data);
5492         skip_emulated_instruction(vcpu);
5493         return 1;
5494 }
5495
5496 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5497 {
5498         kvm_make_request(KVM_REQ_EVENT, vcpu);
5499         return 1;
5500 }
5501
5502 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5503 {
5504         u32 cpu_based_vm_exec_control;
5505
5506         /* clear pending irq */
5507         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5508         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5509         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5510
5511         kvm_make_request(KVM_REQ_EVENT, vcpu);
5512
5513         ++vcpu->stat.irq_window_exits;
5514
5515         /*
5516          * If the user space waits to inject interrupts, exit as soon as
5517          * possible
5518          */
5519         if (!irqchip_in_kernel(vcpu->kvm) &&
5520             vcpu->run->request_interrupt_window &&
5521             !kvm_cpu_has_interrupt(vcpu)) {
5522                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5523                 return 0;
5524         }
5525         return 1;
5526 }
5527
5528 static int handle_halt(struct kvm_vcpu *vcpu)
5529 {
5530         return kvm_emulate_halt(vcpu);
5531 }
5532
5533 static int handle_vmcall(struct kvm_vcpu *vcpu)
5534 {
5535         kvm_emulate_hypercall(vcpu);
5536         return 1;
5537 }
5538
5539 static int handle_invd(struct kvm_vcpu *vcpu)
5540 {
5541         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5542 }
5543
5544 static int handle_invlpg(struct kvm_vcpu *vcpu)
5545 {
5546         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5547
5548         kvm_mmu_invlpg(vcpu, exit_qualification);
5549         skip_emulated_instruction(vcpu);
5550         return 1;
5551 }
5552
5553 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5554 {
5555         int err;
5556
5557         err = kvm_rdpmc(vcpu);
5558         kvm_complete_insn_gp(vcpu, err);
5559
5560         return 1;
5561 }
5562
5563 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5564 {
5565         kvm_emulate_wbinvd(vcpu);
5566         return 1;
5567 }
5568
5569 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5570 {
5571         u64 new_bv = kvm_read_edx_eax(vcpu);
5572         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5573
5574         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5575                 skip_emulated_instruction(vcpu);
5576         return 1;
5577 }
5578
5579 static int handle_xsaves(struct kvm_vcpu *vcpu)
5580 {
5581         skip_emulated_instruction(vcpu);
5582         WARN(1, "this should never happen\n");
5583         return 1;
5584 }
5585
5586 static int handle_xrstors(struct kvm_vcpu *vcpu)
5587 {
5588         skip_emulated_instruction(vcpu);
5589         WARN(1, "this should never happen\n");
5590         return 1;
5591 }
5592
5593 static int handle_apic_access(struct kvm_vcpu *vcpu)
5594 {
5595         if (likely(fasteoi)) {
5596                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5597                 int access_type, offset;
5598
5599                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5600                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5601                 /*
5602                  * Sane guest uses MOV to write EOI, with written value
5603                  * not cared. So make a short-circuit here by avoiding
5604                  * heavy instruction emulation.
5605                  */
5606                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5607                     (offset == APIC_EOI)) {
5608                         kvm_lapic_set_eoi(vcpu);
5609                         skip_emulated_instruction(vcpu);
5610                         return 1;
5611                 }
5612         }
5613         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5614 }
5615
5616 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5617 {
5618         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5619         int vector = exit_qualification & 0xff;
5620
5621         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5622         kvm_apic_set_eoi_accelerated(vcpu, vector);
5623         return 1;
5624 }
5625
5626 static int handle_apic_write(struct kvm_vcpu *vcpu)
5627 {
5628         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5629         u32 offset = exit_qualification & 0xfff;
5630
5631         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5632         kvm_apic_write_nodecode(vcpu, offset);
5633         return 1;
5634 }
5635
5636 static int handle_task_switch(struct kvm_vcpu *vcpu)
5637 {
5638         struct vcpu_vmx *vmx = to_vmx(vcpu);
5639         unsigned long exit_qualification;
5640         bool has_error_code = false;
5641         u32 error_code = 0;
5642         u16 tss_selector;
5643         int reason, type, idt_v, idt_index;
5644
5645         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5646         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5647         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5648
5649         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5650
5651         reason = (u32)exit_qualification >> 30;
5652         if (reason == TASK_SWITCH_GATE && idt_v) {
5653                 switch (type) {
5654                 case INTR_TYPE_NMI_INTR:
5655                         vcpu->arch.nmi_injected = false;
5656                         vmx_set_nmi_mask(vcpu, true);
5657                         break;
5658                 case INTR_TYPE_EXT_INTR:
5659                 case INTR_TYPE_SOFT_INTR:
5660                         kvm_clear_interrupt_queue(vcpu);
5661                         break;
5662                 case INTR_TYPE_HARD_EXCEPTION:
5663                         if (vmx->idt_vectoring_info &
5664                             VECTORING_INFO_DELIVER_CODE_MASK) {
5665                                 has_error_code = true;
5666                                 error_code =
5667                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5668                         }
5669                         /* fall through */
5670                 case INTR_TYPE_SOFT_EXCEPTION:
5671                         kvm_clear_exception_queue(vcpu);
5672                         break;
5673                 default:
5674                         break;
5675                 }
5676         }
5677         tss_selector = exit_qualification;
5678
5679         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5680                        type != INTR_TYPE_EXT_INTR &&
5681                        type != INTR_TYPE_NMI_INTR))
5682                 skip_emulated_instruction(vcpu);
5683
5684         if (kvm_task_switch(vcpu, tss_selector,
5685                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5686                             has_error_code, error_code) == EMULATE_FAIL) {
5687                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5688                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5689                 vcpu->run->internal.ndata = 0;
5690                 return 0;
5691         }
5692
5693         /* clear all local breakpoint enable flags */
5694         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5695
5696         /*
5697          * TODO: What about debug traps on tss switch?
5698          *       Are we supposed to inject them and update dr6?
5699          */
5700
5701         return 1;
5702 }
5703
5704 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5705 {
5706         unsigned long exit_qualification;
5707         gpa_t gpa;
5708         u32 error_code;
5709         int gla_validity;
5710
5711         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5712
5713         gla_validity = (exit_qualification >> 7) & 0x3;
5714         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5715                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5716                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5717                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5718                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5719                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5720                         (long unsigned int)exit_qualification);
5721                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5722                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5723                 return 0;
5724         }
5725
5726         /*
5727          * EPT violation happened while executing iret from NMI,
5728          * "blocked by NMI" bit has to be set before next VM entry.
5729          * There are errata that may cause this bit to not be set:
5730          * AAK134, BY25.
5731          */
5732         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5733                         cpu_has_virtual_nmis() &&
5734                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5735                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5736
5737         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5738         trace_kvm_page_fault(gpa, exit_qualification);
5739
5740         /* It is a write fault? */
5741         error_code = exit_qualification & PFERR_WRITE_MASK;
5742         /* It is a fetch fault? */
5743         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5744         /* ept page table is present? */
5745         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5746
5747         vcpu->arch.exit_qualification = exit_qualification;
5748
5749         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5750 }
5751
5752 static u64 ept_rsvd_mask(u64 spte, int level)
5753 {
5754         int i;
5755         u64 mask = 0;
5756
5757         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5758                 mask |= (1ULL << i);
5759
5760         if (level == 4)
5761                 /* bits 7:3 reserved */
5762                 mask |= 0xf8;
5763         else if (spte & (1ULL << 7))
5764                 /*
5765                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5766                  * level == 1 if the hypervisor is using the ignored bit 7.
5767                  */
5768                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5769         else if (level > 1)
5770                 /* bits 6:3 reserved */
5771                 mask |= 0x78;
5772
5773         return mask;
5774 }
5775
5776 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5777                                        int level)
5778 {
5779         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5780
5781         /* 010b (write-only) */
5782         WARN_ON((spte & 0x7) == 0x2);
5783
5784         /* 110b (write/execute) */
5785         WARN_ON((spte & 0x7) == 0x6);
5786
5787         /* 100b (execute-only) and value not supported by logical processor */
5788         if (!cpu_has_vmx_ept_execute_only())
5789                 WARN_ON((spte & 0x7) == 0x4);
5790
5791         /* not 000b */
5792         if ((spte & 0x7)) {
5793                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5794
5795                 if (rsvd_bits != 0) {
5796                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5797                                          __func__, rsvd_bits);
5798                         WARN_ON(1);
5799                 }
5800
5801                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5802                 if ((rsvd_bits & 0x38) == 0) {
5803                         u64 ept_mem_type = (spte & 0x38) >> 3;
5804
5805                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5806                             ept_mem_type == 7) {
5807                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5808                                                 __func__, ept_mem_type);
5809                                 WARN_ON(1);
5810                         }
5811                 }
5812         }
5813 }
5814
5815 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5816 {
5817         u64 sptes[4];
5818         int nr_sptes, i, ret;
5819         gpa_t gpa;
5820
5821         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5822         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5823                 skip_emulated_instruction(vcpu);
5824                 return 1;
5825         }
5826
5827         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5828         if (likely(ret == RET_MMIO_PF_EMULATE))
5829                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5830                                               EMULATE_DONE;
5831
5832         if (unlikely(ret == RET_MMIO_PF_INVALID))
5833                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5834
5835         if (unlikely(ret == RET_MMIO_PF_RETRY))
5836                 return 1;
5837
5838         /* It is the real ept misconfig */
5839         printk(KERN_ERR "EPT: Misconfiguration.\n");
5840         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5841
5842         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5843
5844         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5845                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5846
5847         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5848         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5849
5850         return 0;
5851 }
5852
5853 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5854 {
5855         u32 cpu_based_vm_exec_control;
5856
5857         /* clear pending NMI */
5858         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5859         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5860         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5861         ++vcpu->stat.nmi_window_exits;
5862         kvm_make_request(KVM_REQ_EVENT, vcpu);
5863
5864         return 1;
5865 }
5866
5867 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5868 {
5869         struct vcpu_vmx *vmx = to_vmx(vcpu);
5870         enum emulation_result err = EMULATE_DONE;
5871         int ret = 1;
5872         u32 cpu_exec_ctrl;
5873         bool intr_window_requested;
5874         unsigned count = 130;
5875
5876         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5877         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5878
5879         while (vmx->emulation_required && count-- != 0) {
5880                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5881                         return handle_interrupt_window(&vmx->vcpu);
5882
5883                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5884                         return 1;
5885
5886                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5887
5888                 if (err == EMULATE_USER_EXIT) {
5889                         ++vcpu->stat.mmio_exits;
5890                         ret = 0;
5891                         goto out;
5892                 }
5893
5894                 if (err != EMULATE_DONE) {
5895                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5896                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5897                         vcpu->run->internal.ndata = 0;
5898                         return 0;
5899                 }
5900
5901                 if (vcpu->arch.halt_request) {
5902                         vcpu->arch.halt_request = 0;
5903                         ret = kvm_vcpu_halt(vcpu);
5904                         goto out;
5905                 }
5906
5907                 if (signal_pending(current))
5908                         goto out;
5909                 if (need_resched())
5910                         schedule();
5911         }
5912
5913 out:
5914         return ret;
5915 }
5916
5917 static int __grow_ple_window(int val)
5918 {
5919         if (ple_window_grow < 1)
5920                 return ple_window;
5921
5922         val = min(val, ple_window_actual_max);
5923
5924         if (ple_window_grow < ple_window)
5925                 val *= ple_window_grow;
5926         else
5927                 val += ple_window_grow;
5928
5929         return val;
5930 }
5931
5932 static int __shrink_ple_window(int val, int modifier, int minimum)
5933 {
5934         if (modifier < 1)
5935                 return ple_window;
5936
5937         if (modifier < ple_window)
5938                 val /= modifier;
5939         else
5940                 val -= modifier;
5941
5942         return max(val, minimum);
5943 }
5944
5945 static void grow_ple_window(struct kvm_vcpu *vcpu)
5946 {
5947         struct vcpu_vmx *vmx = to_vmx(vcpu);
5948         int old = vmx->ple_window;
5949
5950         vmx->ple_window = __grow_ple_window(old);
5951
5952         if (vmx->ple_window != old)
5953                 vmx->ple_window_dirty = true;
5954
5955         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5956 }
5957
5958 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5959 {
5960         struct vcpu_vmx *vmx = to_vmx(vcpu);
5961         int old = vmx->ple_window;
5962
5963         vmx->ple_window = __shrink_ple_window(old,
5964                                               ple_window_shrink, ple_window);
5965
5966         if (vmx->ple_window != old)
5967                 vmx->ple_window_dirty = true;
5968
5969         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5970 }
5971
5972 /*
5973  * ple_window_actual_max is computed to be one grow_ple_window() below
5974  * ple_window_max. (See __grow_ple_window for the reason.)
5975  * This prevents overflows, because ple_window_max is int.
5976  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5977  * this process.
5978  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5979  */
5980 static void update_ple_window_actual_max(void)
5981 {
5982         ple_window_actual_max =
5983                         __shrink_ple_window(max(ple_window_max, ple_window),
5984                                             ple_window_grow, INT_MIN);
5985 }
5986
5987 static __init int hardware_setup(void)
5988 {
5989         int r = -ENOMEM, i, msr;
5990
5991         rdmsrl_safe(MSR_EFER, &host_efer);
5992
5993         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5994                 kvm_define_shared_msr(i, vmx_msr_index[i]);
5995
5996         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5997         if (!vmx_io_bitmap_a)
5998                 return r;
5999
6000         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6001         if (!vmx_io_bitmap_b)
6002                 goto out;
6003
6004         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6005         if (!vmx_msr_bitmap_legacy)
6006                 goto out1;
6007
6008         vmx_msr_bitmap_legacy_x2apic =
6009                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6010         if (!vmx_msr_bitmap_legacy_x2apic)
6011                 goto out2;
6012
6013         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6014         if (!vmx_msr_bitmap_longmode)
6015                 goto out3;
6016
6017         vmx_msr_bitmap_longmode_x2apic =
6018                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6019         if (!vmx_msr_bitmap_longmode_x2apic)
6020                 goto out4;
6021
6022         if (nested) {
6023                 vmx_msr_bitmap_nested =
6024                         (unsigned long *)__get_free_page(GFP_KERNEL);
6025                 if (!vmx_msr_bitmap_nested)
6026                         goto out5;
6027         }
6028
6029         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6030         if (!vmx_vmread_bitmap)
6031                 goto out6;
6032
6033         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6034         if (!vmx_vmwrite_bitmap)
6035                 goto out7;
6036
6037         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6038         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6039
6040         /*
6041          * Allow direct access to the PC debug port (it is often used for I/O
6042          * delays, but the vmexits simply slow things down).
6043          */
6044         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6045         clear_bit(0x80, vmx_io_bitmap_a);
6046
6047         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6048
6049         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6050         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6051         if (nested)
6052                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6053
6054         if (setup_vmcs_config(&vmcs_config) < 0) {
6055                 r = -EIO;
6056                 goto out8;
6057         }
6058
6059         if (boot_cpu_has(X86_FEATURE_NX))
6060                 kvm_enable_efer_bits(EFER_NX);
6061
6062         if (!cpu_has_vmx_vpid())
6063                 enable_vpid = 0;
6064         if (!cpu_has_vmx_shadow_vmcs())
6065                 enable_shadow_vmcs = 0;
6066         if (enable_shadow_vmcs)
6067                 init_vmcs_shadow_fields();
6068
6069         if (!cpu_has_vmx_ept() ||
6070             !cpu_has_vmx_ept_4levels()) {
6071                 enable_ept = 0;
6072                 enable_unrestricted_guest = 0;
6073                 enable_ept_ad_bits = 0;
6074         }
6075
6076         if (!cpu_has_vmx_ept_ad_bits())
6077                 enable_ept_ad_bits = 0;
6078
6079         if (!cpu_has_vmx_unrestricted_guest())
6080                 enable_unrestricted_guest = 0;
6081
6082         if (!cpu_has_vmx_flexpriority())
6083                 flexpriority_enabled = 0;
6084
6085         /*
6086          * set_apic_access_page_addr() is used to reload apic access
6087          * page upon invalidation.  No need to do anything if not
6088          * using the APIC_ACCESS_ADDR VMCS field.
6089          */
6090         if (!flexpriority_enabled)
6091                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6092
6093         if (!cpu_has_vmx_tpr_shadow())
6094                 kvm_x86_ops->update_cr8_intercept = NULL;
6095
6096         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6097                 kvm_disable_largepages();
6098
6099         if (!cpu_has_vmx_ple())
6100                 ple_gap = 0;
6101
6102         if (!cpu_has_vmx_apicv())
6103                 enable_apicv = 0;
6104
6105         if (enable_apicv)
6106                 kvm_x86_ops->update_cr8_intercept = NULL;
6107         else {
6108                 kvm_x86_ops->hwapic_irr_update = NULL;
6109                 kvm_x86_ops->hwapic_isr_update = NULL;
6110                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6111                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6112         }
6113
6114         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6115         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6116         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6117         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6118         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6119         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6120         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6121
6122         memcpy(vmx_msr_bitmap_legacy_x2apic,
6123                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6124         memcpy(vmx_msr_bitmap_longmode_x2apic,
6125                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6126
6127         if (enable_apicv) {
6128                 for (msr = 0x800; msr <= 0x8ff; msr++)
6129                         vmx_disable_intercept_msr_read_x2apic(msr);
6130
6131                 /* According SDM, in x2apic mode, the whole id reg is used.
6132                  * But in KVM, it only use the highest eight bits. Need to
6133                  * intercept it */
6134                 vmx_enable_intercept_msr_read_x2apic(0x802);
6135                 /* TMCCT */
6136                 vmx_enable_intercept_msr_read_x2apic(0x839);
6137                 /* TPR */
6138                 vmx_disable_intercept_msr_write_x2apic(0x808);
6139                 /* EOI */
6140                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6141                 /* SELF-IPI */
6142                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6143         }
6144
6145         if (enable_ept) {
6146                 kvm_mmu_set_mask_ptes(0ull,
6147                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6148                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6149                         0ull, VMX_EPT_EXECUTABLE_MASK);
6150                 ept_set_mmio_spte_mask();
6151                 kvm_enable_tdp();
6152         } else
6153                 kvm_disable_tdp();
6154
6155         update_ple_window_actual_max();
6156
6157         /*
6158          * Only enable PML when hardware supports PML feature, and both EPT
6159          * and EPT A/D bit features are enabled -- PML depends on them to work.
6160          */
6161         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6162                 enable_pml = 0;
6163
6164         if (!enable_pml) {
6165                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6166                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6167                 kvm_x86_ops->flush_log_dirty = NULL;
6168                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6169         }
6170
6171         return alloc_kvm_area();
6172
6173 out8:
6174         free_page((unsigned long)vmx_vmwrite_bitmap);
6175 out7:
6176         free_page((unsigned long)vmx_vmread_bitmap);
6177 out6:
6178         if (nested)
6179                 free_page((unsigned long)vmx_msr_bitmap_nested);
6180 out5:
6181         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6182 out4:
6183         free_page((unsigned long)vmx_msr_bitmap_longmode);
6184 out3:
6185         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6186 out2:
6187         free_page((unsigned long)vmx_msr_bitmap_legacy);
6188 out1:
6189         free_page((unsigned long)vmx_io_bitmap_b);
6190 out:
6191         free_page((unsigned long)vmx_io_bitmap_a);
6192
6193     return r;
6194 }
6195
6196 static __exit void hardware_unsetup(void)
6197 {
6198         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6199         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6200         free_page((unsigned long)vmx_msr_bitmap_legacy);
6201         free_page((unsigned long)vmx_msr_bitmap_longmode);
6202         free_page((unsigned long)vmx_io_bitmap_b);
6203         free_page((unsigned long)vmx_io_bitmap_a);
6204         free_page((unsigned long)vmx_vmwrite_bitmap);
6205         free_page((unsigned long)vmx_vmread_bitmap);
6206         if (nested)
6207                 free_page((unsigned long)vmx_msr_bitmap_nested);
6208
6209         free_kvm_area();
6210 }
6211
6212 /*
6213  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6214  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6215  */
6216 static int handle_pause(struct kvm_vcpu *vcpu)
6217 {
6218         if (ple_gap)
6219                 grow_ple_window(vcpu);
6220
6221         skip_emulated_instruction(vcpu);
6222         kvm_vcpu_on_spin(vcpu);
6223
6224         return 1;
6225 }
6226
6227 static int handle_nop(struct kvm_vcpu *vcpu)
6228 {
6229         skip_emulated_instruction(vcpu);
6230         return 1;
6231 }
6232
6233 static int handle_mwait(struct kvm_vcpu *vcpu)
6234 {
6235         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6236         return handle_nop(vcpu);
6237 }
6238
6239 static int handle_monitor(struct kvm_vcpu *vcpu)
6240 {
6241         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6242         return handle_nop(vcpu);
6243 }
6244
6245 /*
6246  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6247  * We could reuse a single VMCS for all the L2 guests, but we also want the
6248  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6249  * allows keeping them loaded on the processor, and in the future will allow
6250  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6251  * every entry if they never change.
6252  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6253  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6254  *
6255  * The following functions allocate and free a vmcs02 in this pool.
6256  */
6257
6258 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6259 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6260 {
6261         struct vmcs02_list *item;
6262         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6263                 if (item->vmptr == vmx->nested.current_vmptr) {
6264                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6265                         return &item->vmcs02;
6266                 }
6267
6268         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6269                 /* Recycle the least recently used VMCS. */
6270                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6271                         struct vmcs02_list, list);
6272                 item->vmptr = vmx->nested.current_vmptr;
6273                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6274                 return &item->vmcs02;
6275         }
6276
6277         /* Create a new VMCS */
6278         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6279         if (!item)
6280                 return NULL;
6281         item->vmcs02.vmcs = alloc_vmcs();
6282         if (!item->vmcs02.vmcs) {
6283                 kfree(item);
6284                 return NULL;
6285         }
6286         loaded_vmcs_init(&item->vmcs02);
6287         item->vmptr = vmx->nested.current_vmptr;
6288         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6289         vmx->nested.vmcs02_num++;
6290         return &item->vmcs02;
6291 }
6292
6293 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6294 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6295 {
6296         struct vmcs02_list *item;
6297         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6298                 if (item->vmptr == vmptr) {
6299                         free_loaded_vmcs(&item->vmcs02);
6300                         list_del(&item->list);
6301                         kfree(item);
6302                         vmx->nested.vmcs02_num--;
6303                         return;
6304                 }
6305 }
6306
6307 /*
6308  * Free all VMCSs saved for this vcpu, except the one pointed by
6309  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6310  * must be &vmx->vmcs01.
6311  */
6312 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6313 {
6314         struct vmcs02_list *item, *n;
6315
6316         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6317         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6318                 /*
6319                  * Something will leak if the above WARN triggers.  Better than
6320                  * a use-after-free.
6321                  */
6322                 if (vmx->loaded_vmcs == &item->vmcs02)
6323                         continue;
6324
6325                 free_loaded_vmcs(&item->vmcs02);
6326                 list_del(&item->list);
6327                 kfree(item);
6328                 vmx->nested.vmcs02_num--;
6329         }
6330 }
6331
6332 /*
6333  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6334  * set the success or error code of an emulated VMX instruction, as specified
6335  * by Vol 2B, VMX Instruction Reference, "Conventions".
6336  */
6337 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6338 {
6339         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6340                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6341                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6342 }
6343
6344 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6345 {
6346         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6347                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6348                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6349                         | X86_EFLAGS_CF);
6350 }
6351
6352 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6353                                         u32 vm_instruction_error)
6354 {
6355         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6356                 /*
6357                  * failValid writes the error number to the current VMCS, which
6358                  * can't be done there isn't a current VMCS.
6359                  */
6360                 nested_vmx_failInvalid(vcpu);
6361                 return;
6362         }
6363         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6364                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6365                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6366                         | X86_EFLAGS_ZF);
6367         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6368         /*
6369          * We don't need to force a shadow sync because
6370          * VM_INSTRUCTION_ERROR is not shadowed
6371          */
6372 }
6373
6374 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6375 {
6376         /* TODO: not to reset guest simply here. */
6377         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6378         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6379 }
6380
6381 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6382 {
6383         struct vcpu_vmx *vmx =
6384                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6385
6386         vmx->nested.preemption_timer_expired = true;
6387         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6388         kvm_vcpu_kick(&vmx->vcpu);
6389
6390         return HRTIMER_NORESTART;
6391 }
6392
6393 /*
6394  * Decode the memory-address operand of a vmx instruction, as recorded on an
6395  * exit caused by such an instruction (run by a guest hypervisor).
6396  * On success, returns 0. When the operand is invalid, returns 1 and throws
6397  * #UD or #GP.
6398  */
6399 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6400                                  unsigned long exit_qualification,
6401                                  u32 vmx_instruction_info, gva_t *ret)
6402 {
6403         /*
6404          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6405          * Execution", on an exit, vmx_instruction_info holds most of the
6406          * addressing components of the operand. Only the displacement part
6407          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6408          * For how an actual address is calculated from all these components,
6409          * refer to Vol. 1, "Operand Addressing".
6410          */
6411         int  scaling = vmx_instruction_info & 3;
6412         int  addr_size = (vmx_instruction_info >> 7) & 7;
6413         bool is_reg = vmx_instruction_info & (1u << 10);
6414         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6415         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6416         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6417         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6418         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6419
6420         if (is_reg) {
6421                 kvm_queue_exception(vcpu, UD_VECTOR);
6422                 return 1;
6423         }
6424
6425         /* Addr = segment_base + offset */
6426         /* offset = base + [index * scale] + displacement */
6427         *ret = vmx_get_segment_base(vcpu, seg_reg);
6428         if (base_is_valid)
6429                 *ret += kvm_register_read(vcpu, base_reg);
6430         if (index_is_valid)
6431                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6432         *ret += exit_qualification; /* holds the displacement */
6433
6434         if (addr_size == 1) /* 32 bit */
6435                 *ret &= 0xffffffff;
6436
6437         /*
6438          * TODO: throw #GP (and return 1) in various cases that the VM*
6439          * instructions require it - e.g., offset beyond segment limit,
6440          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6441          * address, and so on. Currently these are not checked.
6442          */
6443         return 0;
6444 }
6445
6446 /*
6447  * This function performs the various checks including
6448  * - if it's 4KB aligned
6449  * - No bits beyond the physical address width are set
6450  * - Returns 0 on success or else 1
6451  * (Intel SDM Section 30.3)
6452  */
6453 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6454                                   gpa_t *vmpointer)
6455 {
6456         gva_t gva;
6457         gpa_t vmptr;
6458         struct x86_exception e;
6459         struct page *page;
6460         struct vcpu_vmx *vmx = to_vmx(vcpu);
6461         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6462
6463         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6464                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6465                 return 1;
6466
6467         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6468                                 sizeof(vmptr), &e)) {
6469                 kvm_inject_page_fault(vcpu, &e);
6470                 return 1;
6471         }
6472
6473         switch (exit_reason) {
6474         case EXIT_REASON_VMON:
6475                 /*
6476                  * SDM 3: 24.11.5
6477                  * The first 4 bytes of VMXON region contain the supported
6478                  * VMCS revision identifier
6479                  *
6480                  * Note - IA32_VMX_BASIC[48] will never be 1
6481                  * for the nested case;
6482                  * which replaces physical address width with 32
6483                  *
6484                  */
6485                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6486                         nested_vmx_failInvalid(vcpu);
6487                         skip_emulated_instruction(vcpu);
6488                         return 1;
6489                 }
6490
6491                 page = nested_get_page(vcpu, vmptr);
6492                 if (page == NULL ||
6493                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6494                         nested_vmx_failInvalid(vcpu);
6495                         kunmap(page);
6496                         skip_emulated_instruction(vcpu);
6497                         return 1;
6498                 }
6499                 kunmap(page);
6500                 vmx->nested.vmxon_ptr = vmptr;
6501                 break;
6502         case EXIT_REASON_VMCLEAR:
6503                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6504                         nested_vmx_failValid(vcpu,
6505                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6506                         skip_emulated_instruction(vcpu);
6507                         return 1;
6508                 }
6509
6510                 if (vmptr == vmx->nested.vmxon_ptr) {
6511                         nested_vmx_failValid(vcpu,
6512                                              VMXERR_VMCLEAR_VMXON_POINTER);
6513                         skip_emulated_instruction(vcpu);
6514                         return 1;
6515                 }
6516                 break;
6517         case EXIT_REASON_VMPTRLD:
6518                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6519                         nested_vmx_failValid(vcpu,
6520                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6521                         skip_emulated_instruction(vcpu);
6522                         return 1;
6523                 }
6524
6525                 if (vmptr == vmx->nested.vmxon_ptr) {
6526                         nested_vmx_failValid(vcpu,
6527                                              VMXERR_VMCLEAR_VMXON_POINTER);
6528                         skip_emulated_instruction(vcpu);
6529                         return 1;
6530                 }
6531                 break;
6532         default:
6533                 return 1; /* shouldn't happen */
6534         }
6535
6536         if (vmpointer)
6537                 *vmpointer = vmptr;
6538         return 0;
6539 }
6540
6541 /*
6542  * Emulate the VMXON instruction.
6543  * Currently, we just remember that VMX is active, and do not save or even
6544  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6545  * do not currently need to store anything in that guest-allocated memory
6546  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6547  * argument is different from the VMXON pointer (which the spec says they do).
6548  */
6549 static int handle_vmon(struct kvm_vcpu *vcpu)
6550 {
6551         struct kvm_segment cs;
6552         struct vcpu_vmx *vmx = to_vmx(vcpu);
6553         struct vmcs *shadow_vmcs;
6554         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6555                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6556
6557         /* The Intel VMX Instruction Reference lists a bunch of bits that
6558          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6559          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6560          * Otherwise, we should fail with #UD. We test these now:
6561          */
6562         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6563             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6564             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6565                 kvm_queue_exception(vcpu, UD_VECTOR);
6566                 return 1;
6567         }
6568
6569         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6570         if (is_long_mode(vcpu) && !cs.l) {
6571                 kvm_queue_exception(vcpu, UD_VECTOR);
6572                 return 1;
6573         }
6574
6575         if (vmx_get_cpl(vcpu)) {
6576                 kvm_inject_gp(vcpu, 0);
6577                 return 1;
6578         }
6579
6580         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6581                 return 1;
6582
6583         if (vmx->nested.vmxon) {
6584                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6585                 skip_emulated_instruction(vcpu);
6586                 return 1;
6587         }
6588
6589         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6590                         != VMXON_NEEDED_FEATURES) {
6591                 kvm_inject_gp(vcpu, 0);
6592                 return 1;
6593         }
6594
6595         if (enable_shadow_vmcs) {
6596                 shadow_vmcs = alloc_vmcs();
6597                 if (!shadow_vmcs)
6598                         return -ENOMEM;
6599                 /* mark vmcs as shadow */
6600                 shadow_vmcs->revision_id |= (1u << 31);
6601                 /* init shadow vmcs */
6602                 vmcs_clear(shadow_vmcs);
6603                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6604         }
6605
6606         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6607         vmx->nested.vmcs02_num = 0;
6608
6609         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6610                      HRTIMER_MODE_REL);
6611         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6612
6613         vmx->nested.vmxon = true;
6614
6615         skip_emulated_instruction(vcpu);
6616         nested_vmx_succeed(vcpu);
6617         return 1;
6618 }
6619
6620 /*
6621  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6622  * for running VMX instructions (except VMXON, whose prerequisites are
6623  * slightly different). It also specifies what exception to inject otherwise.
6624  */
6625 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6626 {
6627         struct kvm_segment cs;
6628         struct vcpu_vmx *vmx = to_vmx(vcpu);
6629
6630         if (!vmx->nested.vmxon) {
6631                 kvm_queue_exception(vcpu, UD_VECTOR);
6632                 return 0;
6633         }
6634
6635         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6636         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6637             (is_long_mode(vcpu) && !cs.l)) {
6638                 kvm_queue_exception(vcpu, UD_VECTOR);
6639                 return 0;
6640         }
6641
6642         if (vmx_get_cpl(vcpu)) {
6643                 kvm_inject_gp(vcpu, 0);
6644                 return 0;
6645         }
6646
6647         return 1;
6648 }
6649
6650 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6651 {
6652         u32 exec_control;
6653         if (vmx->nested.current_vmptr == -1ull)
6654                 return;
6655
6656         /* current_vmptr and current_vmcs12 are always set/reset together */
6657         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6658                 return;
6659
6660         if (enable_shadow_vmcs) {
6661                 /* copy to memory all shadowed fields in case
6662                    they were modified */
6663                 copy_shadow_to_vmcs12(vmx);
6664                 vmx->nested.sync_shadow_vmcs = false;
6665                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6666                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6667                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6668                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6669         }
6670         vmx->nested.posted_intr_nv = -1;
6671         kunmap(vmx->nested.current_vmcs12_page);
6672         nested_release_page(vmx->nested.current_vmcs12_page);
6673         vmx->nested.current_vmptr = -1ull;
6674         vmx->nested.current_vmcs12 = NULL;
6675 }
6676
6677 /*
6678  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6679  * just stops using VMX.
6680  */
6681 static void free_nested(struct vcpu_vmx *vmx)
6682 {
6683         if (!vmx->nested.vmxon)
6684                 return;
6685
6686         vmx->nested.vmxon = false;
6687         nested_release_vmcs12(vmx);
6688         if (enable_shadow_vmcs)
6689                 free_vmcs(vmx->nested.current_shadow_vmcs);
6690         /* Unpin physical memory we referred to in current vmcs02 */
6691         if (vmx->nested.apic_access_page) {
6692                 nested_release_page(vmx->nested.apic_access_page);
6693                 vmx->nested.apic_access_page = NULL;
6694         }
6695         if (vmx->nested.virtual_apic_page) {
6696                 nested_release_page(vmx->nested.virtual_apic_page);
6697                 vmx->nested.virtual_apic_page = NULL;
6698         }
6699         if (vmx->nested.pi_desc_page) {
6700                 kunmap(vmx->nested.pi_desc_page);
6701                 nested_release_page(vmx->nested.pi_desc_page);
6702                 vmx->nested.pi_desc_page = NULL;
6703                 vmx->nested.pi_desc = NULL;
6704         }
6705
6706         nested_free_all_saved_vmcss(vmx);
6707 }
6708
6709 /* Emulate the VMXOFF instruction */
6710 static int handle_vmoff(struct kvm_vcpu *vcpu)
6711 {
6712         if (!nested_vmx_check_permission(vcpu))
6713                 return 1;
6714         free_nested(to_vmx(vcpu));
6715         skip_emulated_instruction(vcpu);
6716         nested_vmx_succeed(vcpu);
6717         return 1;
6718 }
6719
6720 /* Emulate the VMCLEAR instruction */
6721 static int handle_vmclear(struct kvm_vcpu *vcpu)
6722 {
6723         struct vcpu_vmx *vmx = to_vmx(vcpu);
6724         gpa_t vmptr;
6725         struct vmcs12 *vmcs12;
6726         struct page *page;
6727
6728         if (!nested_vmx_check_permission(vcpu))
6729                 return 1;
6730
6731         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6732                 return 1;
6733
6734         if (vmptr == vmx->nested.current_vmptr)
6735                 nested_release_vmcs12(vmx);
6736
6737         page = nested_get_page(vcpu, vmptr);
6738         if (page == NULL) {
6739                 /*
6740                  * For accurate processor emulation, VMCLEAR beyond available
6741                  * physical memory should do nothing at all. However, it is
6742                  * possible that a nested vmx bug, not a guest hypervisor bug,
6743                  * resulted in this case, so let's shut down before doing any
6744                  * more damage:
6745                  */
6746                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6747                 return 1;
6748         }
6749         vmcs12 = kmap(page);
6750         vmcs12->launch_state = 0;
6751         kunmap(page);
6752         nested_release_page(page);
6753
6754         nested_free_vmcs02(vmx, vmptr);
6755
6756         skip_emulated_instruction(vcpu);
6757         nested_vmx_succeed(vcpu);
6758         return 1;
6759 }
6760
6761 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6762
6763 /* Emulate the VMLAUNCH instruction */
6764 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6765 {
6766         return nested_vmx_run(vcpu, true);
6767 }
6768
6769 /* Emulate the VMRESUME instruction */
6770 static int handle_vmresume(struct kvm_vcpu *vcpu)
6771 {
6772
6773         return nested_vmx_run(vcpu, false);
6774 }
6775
6776 enum vmcs_field_type {
6777         VMCS_FIELD_TYPE_U16 = 0,
6778         VMCS_FIELD_TYPE_U64 = 1,
6779         VMCS_FIELD_TYPE_U32 = 2,
6780         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6781 };
6782
6783 static inline int vmcs_field_type(unsigned long field)
6784 {
6785         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6786                 return VMCS_FIELD_TYPE_U32;
6787         return (field >> 13) & 0x3 ;
6788 }
6789
6790 static inline int vmcs_field_readonly(unsigned long field)
6791 {
6792         return (((field >> 10) & 0x3) == 1);
6793 }
6794
6795 /*
6796  * Read a vmcs12 field. Since these can have varying lengths and we return
6797  * one type, we chose the biggest type (u64) and zero-extend the return value
6798  * to that size. Note that the caller, handle_vmread, might need to use only
6799  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6800  * 64-bit fields are to be returned).
6801  */
6802 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6803                                   unsigned long field, u64 *ret)
6804 {
6805         short offset = vmcs_field_to_offset(field);
6806         char *p;
6807
6808         if (offset < 0)
6809                 return offset;
6810
6811         p = ((char *)(get_vmcs12(vcpu))) + offset;
6812
6813         switch (vmcs_field_type(field)) {
6814         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6815                 *ret = *((natural_width *)p);
6816                 return 0;
6817         case VMCS_FIELD_TYPE_U16:
6818                 *ret = *((u16 *)p);
6819                 return 0;
6820         case VMCS_FIELD_TYPE_U32:
6821                 *ret = *((u32 *)p);
6822                 return 0;
6823         case VMCS_FIELD_TYPE_U64:
6824                 *ret = *((u64 *)p);
6825                 return 0;
6826         default:
6827                 WARN_ON(1);
6828                 return -ENOENT;
6829         }
6830 }
6831
6832
6833 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6834                                    unsigned long field, u64 field_value){
6835         short offset = vmcs_field_to_offset(field);
6836         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6837         if (offset < 0)
6838                 return offset;
6839
6840         switch (vmcs_field_type(field)) {
6841         case VMCS_FIELD_TYPE_U16:
6842                 *(u16 *)p = field_value;
6843                 return 0;
6844         case VMCS_FIELD_TYPE_U32:
6845                 *(u32 *)p = field_value;
6846                 return 0;
6847         case VMCS_FIELD_TYPE_U64:
6848                 *(u64 *)p = field_value;
6849                 return 0;
6850         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6851                 *(natural_width *)p = field_value;
6852                 return 0;
6853         default:
6854                 WARN_ON(1);
6855                 return -ENOENT;
6856         }
6857
6858 }
6859
6860 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6861 {
6862         int i;
6863         unsigned long field;
6864         u64 field_value;
6865         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6866         const unsigned long *fields = shadow_read_write_fields;
6867         const int num_fields = max_shadow_read_write_fields;
6868
6869         preempt_disable();
6870
6871         vmcs_load(shadow_vmcs);
6872
6873         for (i = 0; i < num_fields; i++) {
6874                 field = fields[i];
6875                 switch (vmcs_field_type(field)) {
6876                 case VMCS_FIELD_TYPE_U16:
6877                         field_value = vmcs_read16(field);
6878                         break;
6879                 case VMCS_FIELD_TYPE_U32:
6880                         field_value = vmcs_read32(field);
6881                         break;
6882                 case VMCS_FIELD_TYPE_U64:
6883                         field_value = vmcs_read64(field);
6884                         break;
6885                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6886                         field_value = vmcs_readl(field);
6887                         break;
6888                 default:
6889                         WARN_ON(1);
6890                         continue;
6891                 }
6892                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6893         }
6894
6895         vmcs_clear(shadow_vmcs);
6896         vmcs_load(vmx->loaded_vmcs->vmcs);
6897
6898         preempt_enable();
6899 }
6900
6901 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6902 {
6903         const unsigned long *fields[] = {
6904                 shadow_read_write_fields,
6905                 shadow_read_only_fields
6906         };
6907         const int max_fields[] = {
6908                 max_shadow_read_write_fields,
6909                 max_shadow_read_only_fields
6910         };
6911         int i, q;
6912         unsigned long field;
6913         u64 field_value = 0;
6914         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6915
6916         vmcs_load(shadow_vmcs);
6917
6918         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6919                 for (i = 0; i < max_fields[q]; i++) {
6920                         field = fields[q][i];
6921                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6922
6923                         switch (vmcs_field_type(field)) {
6924                         case VMCS_FIELD_TYPE_U16:
6925                                 vmcs_write16(field, (u16)field_value);
6926                                 break;
6927                         case VMCS_FIELD_TYPE_U32:
6928                                 vmcs_write32(field, (u32)field_value);
6929                                 break;
6930                         case VMCS_FIELD_TYPE_U64:
6931                                 vmcs_write64(field, (u64)field_value);
6932                                 break;
6933                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6934                                 vmcs_writel(field, (long)field_value);
6935                                 break;
6936                         default:
6937                                 WARN_ON(1);
6938                                 break;
6939                         }
6940                 }
6941         }
6942
6943         vmcs_clear(shadow_vmcs);
6944         vmcs_load(vmx->loaded_vmcs->vmcs);
6945 }
6946
6947 /*
6948  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6949  * used before) all generate the same failure when it is missing.
6950  */
6951 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6952 {
6953         struct vcpu_vmx *vmx = to_vmx(vcpu);
6954         if (vmx->nested.current_vmptr == -1ull) {
6955                 nested_vmx_failInvalid(vcpu);
6956                 skip_emulated_instruction(vcpu);
6957                 return 0;
6958         }
6959         return 1;
6960 }
6961
6962 static int handle_vmread(struct kvm_vcpu *vcpu)
6963 {
6964         unsigned long field;
6965         u64 field_value;
6966         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6967         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6968         gva_t gva = 0;
6969
6970         if (!nested_vmx_check_permission(vcpu) ||
6971             !nested_vmx_check_vmcs12(vcpu))
6972                 return 1;
6973
6974         /* Decode instruction info and find the field to read */
6975         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6976         /* Read the field, zero-extended to a u64 field_value */
6977         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6978                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6979                 skip_emulated_instruction(vcpu);
6980                 return 1;
6981         }
6982         /*
6983          * Now copy part of this value to register or memory, as requested.
6984          * Note that the number of bits actually copied is 32 or 64 depending
6985          * on the guest's mode (32 or 64 bit), not on the given field's length.
6986          */
6987         if (vmx_instruction_info & (1u << 10)) {
6988                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6989                         field_value);
6990         } else {
6991                 if (get_vmx_mem_address(vcpu, exit_qualification,
6992                                 vmx_instruction_info, &gva))
6993                         return 1;
6994                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6995                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6996                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6997         }
6998
6999         nested_vmx_succeed(vcpu);
7000         skip_emulated_instruction(vcpu);
7001         return 1;
7002 }
7003
7004
7005 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7006 {
7007         unsigned long field;
7008         gva_t gva;
7009         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7010         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7011         /* The value to write might be 32 or 64 bits, depending on L1's long
7012          * mode, and eventually we need to write that into a field of several
7013          * possible lengths. The code below first zero-extends the value to 64
7014          * bit (field_value), and then copies only the approriate number of
7015          * bits into the vmcs12 field.
7016          */
7017         u64 field_value = 0;
7018         struct x86_exception e;
7019
7020         if (!nested_vmx_check_permission(vcpu) ||
7021             !nested_vmx_check_vmcs12(vcpu))
7022                 return 1;
7023
7024         if (vmx_instruction_info & (1u << 10))
7025                 field_value = kvm_register_readl(vcpu,
7026                         (((vmx_instruction_info) >> 3) & 0xf));
7027         else {
7028                 if (get_vmx_mem_address(vcpu, exit_qualification,
7029                                 vmx_instruction_info, &gva))
7030                         return 1;
7031                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7032                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7033                         kvm_inject_page_fault(vcpu, &e);
7034                         return 1;
7035                 }
7036         }
7037
7038
7039         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7040         if (vmcs_field_readonly(field)) {
7041                 nested_vmx_failValid(vcpu,
7042                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7043                 skip_emulated_instruction(vcpu);
7044                 return 1;
7045         }
7046
7047         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7048                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7049                 skip_emulated_instruction(vcpu);
7050                 return 1;
7051         }
7052
7053         nested_vmx_succeed(vcpu);
7054         skip_emulated_instruction(vcpu);
7055         return 1;
7056 }
7057
7058 /* Emulate the VMPTRLD instruction */
7059 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7060 {
7061         struct vcpu_vmx *vmx = to_vmx(vcpu);
7062         gpa_t vmptr;
7063         u32 exec_control;
7064
7065         if (!nested_vmx_check_permission(vcpu))
7066                 return 1;
7067
7068         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7069                 return 1;
7070
7071         if (vmx->nested.current_vmptr != vmptr) {
7072                 struct vmcs12 *new_vmcs12;
7073                 struct page *page;
7074                 page = nested_get_page(vcpu, vmptr);
7075                 if (page == NULL) {
7076                         nested_vmx_failInvalid(vcpu);
7077                         skip_emulated_instruction(vcpu);
7078                         return 1;
7079                 }
7080                 new_vmcs12 = kmap(page);
7081                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7082                         kunmap(page);
7083                         nested_release_page_clean(page);
7084                         nested_vmx_failValid(vcpu,
7085                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7086                         skip_emulated_instruction(vcpu);
7087                         return 1;
7088                 }
7089
7090                 nested_release_vmcs12(vmx);
7091                 vmx->nested.current_vmptr = vmptr;
7092                 vmx->nested.current_vmcs12 = new_vmcs12;
7093                 vmx->nested.current_vmcs12_page = page;
7094                 if (enable_shadow_vmcs) {
7095                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7096                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7097                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7098                         vmcs_write64(VMCS_LINK_POINTER,
7099                                      __pa(vmx->nested.current_shadow_vmcs));
7100                         vmx->nested.sync_shadow_vmcs = true;
7101                 }
7102         }
7103
7104         nested_vmx_succeed(vcpu);
7105         skip_emulated_instruction(vcpu);
7106         return 1;
7107 }
7108
7109 /* Emulate the VMPTRST instruction */
7110 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7111 {
7112         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7113         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7114         gva_t vmcs_gva;
7115         struct x86_exception e;
7116
7117         if (!nested_vmx_check_permission(vcpu))
7118                 return 1;
7119
7120         if (get_vmx_mem_address(vcpu, exit_qualification,
7121                         vmx_instruction_info, &vmcs_gva))
7122                 return 1;
7123         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7124         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7125                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7126                                  sizeof(u64), &e)) {
7127                 kvm_inject_page_fault(vcpu, &e);
7128                 return 1;
7129         }
7130         nested_vmx_succeed(vcpu);
7131         skip_emulated_instruction(vcpu);
7132         return 1;
7133 }
7134
7135 /* Emulate the INVEPT instruction */
7136 static int handle_invept(struct kvm_vcpu *vcpu)
7137 {
7138         struct vcpu_vmx *vmx = to_vmx(vcpu);
7139         u32 vmx_instruction_info, types;
7140         unsigned long type;
7141         gva_t gva;
7142         struct x86_exception e;
7143         struct {
7144                 u64 eptp, gpa;
7145         } operand;
7146
7147         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7148               SECONDARY_EXEC_ENABLE_EPT) ||
7149             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7150                 kvm_queue_exception(vcpu, UD_VECTOR);
7151                 return 1;
7152         }
7153
7154         if (!nested_vmx_check_permission(vcpu))
7155                 return 1;
7156
7157         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7158                 kvm_queue_exception(vcpu, UD_VECTOR);
7159                 return 1;
7160         }
7161
7162         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7163         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7164
7165         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7166
7167         if (!(types & (1UL << type))) {
7168                 nested_vmx_failValid(vcpu,
7169                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7170                 return 1;
7171         }
7172
7173         /* According to the Intel VMX instruction reference, the memory
7174          * operand is read even if it isn't needed (e.g., for type==global)
7175          */
7176         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7177                         vmx_instruction_info, &gva))
7178                 return 1;
7179         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7180                                 sizeof(operand), &e)) {
7181                 kvm_inject_page_fault(vcpu, &e);
7182                 return 1;
7183         }
7184
7185         switch (type) {
7186         case VMX_EPT_EXTENT_GLOBAL:
7187                 kvm_mmu_sync_roots(vcpu);
7188                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7189                 nested_vmx_succeed(vcpu);
7190                 break;
7191         default:
7192                 /* Trap single context invalidation invept calls */
7193                 BUG_ON(1);
7194                 break;
7195         }
7196
7197         skip_emulated_instruction(vcpu);
7198         return 1;
7199 }
7200
7201 static int handle_invvpid(struct kvm_vcpu *vcpu)
7202 {
7203         kvm_queue_exception(vcpu, UD_VECTOR);
7204         return 1;
7205 }
7206
7207 static int handle_pml_full(struct kvm_vcpu *vcpu)
7208 {
7209         unsigned long exit_qualification;
7210
7211         trace_kvm_pml_full(vcpu->vcpu_id);
7212
7213         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7214
7215         /*
7216          * PML buffer FULL happened while executing iret from NMI,
7217          * "blocked by NMI" bit has to be set before next VM entry.
7218          */
7219         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7220                         cpu_has_virtual_nmis() &&
7221                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7222                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7223                                 GUEST_INTR_STATE_NMI);
7224
7225         /*
7226          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7227          * here.., and there's no userspace involvement needed for PML.
7228          */
7229         return 1;
7230 }
7231
7232 /*
7233  * The exit handlers return 1 if the exit was handled fully and guest execution
7234  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7235  * to be done to userspace and return 0.
7236  */
7237 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7238         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7239         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7240         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7241         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7242         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7243         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7244         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7245         [EXIT_REASON_CPUID]                   = handle_cpuid,
7246         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7247         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7248         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7249         [EXIT_REASON_HLT]                     = handle_halt,
7250         [EXIT_REASON_INVD]                    = handle_invd,
7251         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7252         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7253         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7254         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7255         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7256         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7257         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7258         [EXIT_REASON_VMREAD]                  = handle_vmread,
7259         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7260         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7261         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7262         [EXIT_REASON_VMON]                    = handle_vmon,
7263         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7264         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7265         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7266         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7267         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7268         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7269         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7270         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7271         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7272         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7273         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7274         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7275         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7276         [EXIT_REASON_INVEPT]                  = handle_invept,
7277         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7278         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7279         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7280         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7281 };
7282
7283 static const int kvm_vmx_max_exit_handlers =
7284         ARRAY_SIZE(kvm_vmx_exit_handlers);
7285
7286 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7287                                        struct vmcs12 *vmcs12)
7288 {
7289         unsigned long exit_qualification;
7290         gpa_t bitmap, last_bitmap;
7291         unsigned int port;
7292         int size;
7293         u8 b;
7294
7295         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7296                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7297
7298         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7299
7300         port = exit_qualification >> 16;
7301         size = (exit_qualification & 7) + 1;
7302
7303         last_bitmap = (gpa_t)-1;
7304         b = -1;
7305
7306         while (size > 0) {
7307                 if (port < 0x8000)
7308                         bitmap = vmcs12->io_bitmap_a;
7309                 else if (port < 0x10000)
7310                         bitmap = vmcs12->io_bitmap_b;
7311                 else
7312                         return 1;
7313                 bitmap += (port & 0x7fff) / 8;
7314
7315                 if (last_bitmap != bitmap)
7316                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7317                                 return 1;
7318                 if (b & (1 << (port & 7)))
7319                         return 1;
7320
7321                 port++;
7322                 size--;
7323                 last_bitmap = bitmap;
7324         }
7325
7326         return 0;
7327 }
7328
7329 /*
7330  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7331  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7332  * disinterest in the current event (read or write a specific MSR) by using an
7333  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7334  */
7335 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7336         struct vmcs12 *vmcs12, u32 exit_reason)
7337 {
7338         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7339         gpa_t bitmap;
7340
7341         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7342                 return 1;
7343
7344         /*
7345          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7346          * for the four combinations of read/write and low/high MSR numbers.
7347          * First we need to figure out which of the four to use:
7348          */
7349         bitmap = vmcs12->msr_bitmap;
7350         if (exit_reason == EXIT_REASON_MSR_WRITE)
7351                 bitmap += 2048;
7352         if (msr_index >= 0xc0000000) {
7353                 msr_index -= 0xc0000000;
7354                 bitmap += 1024;
7355         }
7356
7357         /* Then read the msr_index'th bit from this bitmap: */
7358         if (msr_index < 1024*8) {
7359                 unsigned char b;
7360                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7361                         return 1;
7362                 return 1 & (b >> (msr_index & 7));
7363         } else
7364                 return 1; /* let L1 handle the wrong parameter */
7365 }
7366
7367 /*
7368  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7369  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7370  * intercept (via guest_host_mask etc.) the current event.
7371  */
7372 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7373         struct vmcs12 *vmcs12)
7374 {
7375         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7376         int cr = exit_qualification & 15;
7377         int reg = (exit_qualification >> 8) & 15;
7378         unsigned long val = kvm_register_readl(vcpu, reg);
7379
7380         switch ((exit_qualification >> 4) & 3) {
7381         case 0: /* mov to cr */
7382                 switch (cr) {
7383                 case 0:
7384                         if (vmcs12->cr0_guest_host_mask &
7385                             (val ^ vmcs12->cr0_read_shadow))
7386                                 return 1;
7387                         break;
7388                 case 3:
7389                         if ((vmcs12->cr3_target_count >= 1 &&
7390                                         vmcs12->cr3_target_value0 == val) ||
7391                                 (vmcs12->cr3_target_count >= 2 &&
7392                                         vmcs12->cr3_target_value1 == val) ||
7393                                 (vmcs12->cr3_target_count >= 3 &&
7394                                         vmcs12->cr3_target_value2 == val) ||
7395                                 (vmcs12->cr3_target_count >= 4 &&
7396                                         vmcs12->cr3_target_value3 == val))
7397                                 return 0;
7398                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7399                                 return 1;
7400                         break;
7401                 case 4:
7402                         if (vmcs12->cr4_guest_host_mask &
7403                             (vmcs12->cr4_read_shadow ^ val))
7404                                 return 1;
7405                         break;
7406                 case 8:
7407                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7408                                 return 1;
7409                         break;
7410                 }
7411                 break;
7412         case 2: /* clts */
7413                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7414                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7415                         return 1;
7416                 break;
7417         case 1: /* mov from cr */
7418                 switch (cr) {
7419                 case 3:
7420                         if (vmcs12->cpu_based_vm_exec_control &
7421                             CPU_BASED_CR3_STORE_EXITING)
7422                                 return 1;
7423                         break;
7424                 case 8:
7425                         if (vmcs12->cpu_based_vm_exec_control &
7426                             CPU_BASED_CR8_STORE_EXITING)
7427                                 return 1;
7428                         break;
7429                 }
7430                 break;
7431         case 3: /* lmsw */
7432                 /*
7433                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7434                  * cr0. Other attempted changes are ignored, with no exit.
7435                  */
7436                 if (vmcs12->cr0_guest_host_mask & 0xe &
7437                     (val ^ vmcs12->cr0_read_shadow))
7438                         return 1;
7439                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7440                     !(vmcs12->cr0_read_shadow & 0x1) &&
7441                     (val & 0x1))
7442                         return 1;
7443                 break;
7444         }
7445         return 0;
7446 }
7447
7448 /*
7449  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7450  * should handle it ourselves in L0 (and then continue L2). Only call this
7451  * when in is_guest_mode (L2).
7452  */
7453 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7454 {
7455         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7456         struct vcpu_vmx *vmx = to_vmx(vcpu);
7457         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7458         u32 exit_reason = vmx->exit_reason;
7459
7460         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7461                                 vmcs_readl(EXIT_QUALIFICATION),
7462                                 vmx->idt_vectoring_info,
7463                                 intr_info,
7464                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7465                                 KVM_ISA_VMX);
7466
7467         if (vmx->nested.nested_run_pending)
7468                 return 0;
7469
7470         if (unlikely(vmx->fail)) {
7471                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7472                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7473                 return 1;
7474         }
7475
7476         switch (exit_reason) {
7477         case EXIT_REASON_EXCEPTION_NMI:
7478                 if (!is_exception(intr_info))
7479                         return 0;
7480                 else if (is_page_fault(intr_info))
7481                         return enable_ept;
7482                 else if (is_no_device(intr_info) &&
7483                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7484                         return 0;
7485                 return vmcs12->exception_bitmap &
7486                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7487         case EXIT_REASON_EXTERNAL_INTERRUPT:
7488                 return 0;
7489         case EXIT_REASON_TRIPLE_FAULT:
7490                 return 1;
7491         case EXIT_REASON_PENDING_INTERRUPT:
7492                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7493         case EXIT_REASON_NMI_WINDOW:
7494                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7495         case EXIT_REASON_TASK_SWITCH:
7496                 return 1;
7497         case EXIT_REASON_CPUID:
7498                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7499                         return 0;
7500                 return 1;
7501         case EXIT_REASON_HLT:
7502                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7503         case EXIT_REASON_INVD:
7504                 return 1;
7505         case EXIT_REASON_INVLPG:
7506                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7507         case EXIT_REASON_RDPMC:
7508                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7509         case EXIT_REASON_RDTSC:
7510                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7511         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7512         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7513         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7514         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7515         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7516         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7517                 /*
7518                  * VMX instructions trap unconditionally. This allows L1 to
7519                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7520                  */
7521                 return 1;
7522         case EXIT_REASON_CR_ACCESS:
7523                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7524         case EXIT_REASON_DR_ACCESS:
7525                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7526         case EXIT_REASON_IO_INSTRUCTION:
7527                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7528         case EXIT_REASON_MSR_READ:
7529         case EXIT_REASON_MSR_WRITE:
7530                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7531         case EXIT_REASON_INVALID_STATE:
7532                 return 1;
7533         case EXIT_REASON_MWAIT_INSTRUCTION:
7534                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7535         case EXIT_REASON_MONITOR_INSTRUCTION:
7536                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7537         case EXIT_REASON_PAUSE_INSTRUCTION:
7538                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7539                         nested_cpu_has2(vmcs12,
7540                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7541         case EXIT_REASON_MCE_DURING_VMENTRY:
7542                 return 0;
7543         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7544                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7545         case EXIT_REASON_APIC_ACCESS:
7546                 return nested_cpu_has2(vmcs12,
7547                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7548         case EXIT_REASON_APIC_WRITE:
7549         case EXIT_REASON_EOI_INDUCED:
7550                 /* apic_write and eoi_induced should exit unconditionally. */
7551                 return 1;
7552         case EXIT_REASON_EPT_VIOLATION:
7553                 /*
7554                  * L0 always deals with the EPT violation. If nested EPT is
7555                  * used, and the nested mmu code discovers that the address is
7556                  * missing in the guest EPT table (EPT12), the EPT violation
7557                  * will be injected with nested_ept_inject_page_fault()
7558                  */
7559                 return 0;
7560         case EXIT_REASON_EPT_MISCONFIG:
7561                 /*
7562                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7563                  * table (shadow on EPT) or a merged EPT table that L0 built
7564                  * (EPT on EPT). So any problems with the structure of the
7565                  * table is L0's fault.
7566                  */
7567                 return 0;
7568         case EXIT_REASON_WBINVD:
7569                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7570         case EXIT_REASON_XSETBV:
7571                 return 1;
7572         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7573                 /*
7574                  * This should never happen, since it is not possible to
7575                  * set XSS to a non-zero value---neither in L1 nor in L2.
7576                  * If if it were, XSS would have to be checked against
7577                  * the XSS exit bitmap in vmcs12.
7578                  */
7579                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7580         default:
7581                 return 1;
7582         }
7583 }
7584
7585 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7586 {
7587         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7588         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7589 }
7590
7591 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7592 {
7593         struct page *pml_pg;
7594         u32 exec_control;
7595
7596         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7597         if (!pml_pg)
7598                 return -ENOMEM;
7599
7600         vmx->pml_pg = pml_pg;
7601
7602         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7603         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7604
7605         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7606         exec_control |= SECONDARY_EXEC_ENABLE_PML;
7607         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7608
7609         return 0;
7610 }
7611
7612 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7613 {
7614         u32 exec_control;
7615
7616         ASSERT(vmx->pml_pg);
7617         __free_page(vmx->pml_pg);
7618         vmx->pml_pg = NULL;
7619
7620         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7621         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7622         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7623 }
7624
7625 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7626 {
7627         struct kvm *kvm = vmx->vcpu.kvm;
7628         u64 *pml_buf;
7629         u16 pml_idx;
7630
7631         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7632
7633         /* Do nothing if PML buffer is empty */
7634         if (pml_idx == (PML_ENTITY_NUM - 1))
7635                 return;
7636
7637         /* PML index always points to next available PML buffer entity */
7638         if (pml_idx >= PML_ENTITY_NUM)
7639                 pml_idx = 0;
7640         else
7641                 pml_idx++;
7642
7643         pml_buf = page_address(vmx->pml_pg);
7644         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7645                 u64 gpa;
7646
7647                 gpa = pml_buf[pml_idx];
7648                 WARN_ON(gpa & (PAGE_SIZE - 1));
7649                 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7650         }
7651
7652         /* reset PML index */
7653         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7654 }
7655
7656 /*
7657  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7658  * Called before reporting dirty_bitmap to userspace.
7659  */
7660 static void kvm_flush_pml_buffers(struct kvm *kvm)
7661 {
7662         int i;
7663         struct kvm_vcpu *vcpu;
7664         /*
7665          * We only need to kick vcpu out of guest mode here, as PML buffer
7666          * is flushed at beginning of all VMEXITs, and it's obvious that only
7667          * vcpus running in guest are possible to have unflushed GPAs in PML
7668          * buffer.
7669          */
7670         kvm_for_each_vcpu(i, vcpu, kvm)
7671                 kvm_vcpu_kick(vcpu);
7672 }
7673
7674 /*
7675  * The guest has exited.  See if we can fix it or if we need userspace
7676  * assistance.
7677  */
7678 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7679 {
7680         struct vcpu_vmx *vmx = to_vmx(vcpu);
7681         u32 exit_reason = vmx->exit_reason;
7682         u32 vectoring_info = vmx->idt_vectoring_info;
7683
7684         /*
7685          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7686          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7687          * querying dirty_bitmap, we only need to kick all vcpus out of guest
7688          * mode as if vcpus is in root mode, the PML buffer must has been
7689          * flushed already.
7690          */
7691         if (enable_pml)
7692                 vmx_flush_pml_buffer(vmx);
7693
7694         /* If guest state is invalid, start emulating */
7695         if (vmx->emulation_required)
7696                 return handle_invalid_guest_state(vcpu);
7697
7698         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7699                 nested_vmx_vmexit(vcpu, exit_reason,
7700                                   vmcs_read32(VM_EXIT_INTR_INFO),
7701                                   vmcs_readl(EXIT_QUALIFICATION));
7702                 return 1;
7703         }
7704
7705         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7706                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7707                 vcpu->run->fail_entry.hardware_entry_failure_reason
7708                         = exit_reason;
7709                 return 0;
7710         }
7711
7712         if (unlikely(vmx->fail)) {
7713                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7714                 vcpu->run->fail_entry.hardware_entry_failure_reason
7715                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7716                 return 0;
7717         }
7718
7719         /*
7720          * Note:
7721          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7722          * delivery event since it indicates guest is accessing MMIO.
7723          * The vm-exit can be triggered again after return to guest that
7724          * will cause infinite loop.
7725          */
7726         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7727                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7728                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7729                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7730                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7731                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7732                 vcpu->run->internal.ndata = 2;
7733                 vcpu->run->internal.data[0] = vectoring_info;
7734                 vcpu->run->internal.data[1] = exit_reason;
7735                 return 0;
7736         }
7737
7738         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7739             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7740                                         get_vmcs12(vcpu))))) {
7741                 if (vmx_interrupt_allowed(vcpu)) {
7742                         vmx->soft_vnmi_blocked = 0;
7743                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7744                            vcpu->arch.nmi_pending) {
7745                         /*
7746                          * This CPU don't support us in finding the end of an
7747                          * NMI-blocked window if the guest runs with IRQs
7748                          * disabled. So we pull the trigger after 1 s of
7749                          * futile waiting, but inform the user about this.
7750                          */
7751                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7752                                "state on VCPU %d after 1 s timeout\n",
7753                                __func__, vcpu->vcpu_id);
7754                         vmx->soft_vnmi_blocked = 0;
7755                 }
7756         }
7757
7758         if (exit_reason < kvm_vmx_max_exit_handlers
7759             && kvm_vmx_exit_handlers[exit_reason])
7760                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7761         else {
7762                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7763                 kvm_queue_exception(vcpu, UD_VECTOR);
7764                 return 1;
7765         }
7766 }
7767
7768 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7769 {
7770         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7771
7772         if (is_guest_mode(vcpu) &&
7773                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7774                 return;
7775
7776         if (irr == -1 || tpr < irr) {
7777                 vmcs_write32(TPR_THRESHOLD, 0);
7778                 return;
7779         }
7780
7781         vmcs_write32(TPR_THRESHOLD, irr);
7782 }
7783
7784 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7785 {
7786         u32 sec_exec_control;
7787
7788         /*
7789          * There is not point to enable virtualize x2apic without enable
7790          * apicv
7791          */
7792         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7793                                 !vmx_vm_has_apicv(vcpu->kvm))
7794                 return;
7795
7796         if (!vm_need_tpr_shadow(vcpu->kvm))
7797                 return;
7798
7799         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7800
7801         if (set) {
7802                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7803                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7804         } else {
7805                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7806                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7807         }
7808         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7809
7810         vmx_set_msr_bitmap(vcpu);
7811 }
7812
7813 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7814 {
7815         struct vcpu_vmx *vmx = to_vmx(vcpu);
7816
7817         /*
7818          * Currently we do not handle the nested case where L2 has an
7819          * APIC access page of its own; that page is still pinned.
7820          * Hence, we skip the case where the VCPU is in guest mode _and_
7821          * L1 prepared an APIC access page for L2.
7822          *
7823          * For the case where L1 and L2 share the same APIC access page
7824          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7825          * in the vmcs12), this function will only update either the vmcs01
7826          * or the vmcs02.  If the former, the vmcs02 will be updated by
7827          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7828          * the next L2->L1 exit.
7829          */
7830         if (!is_guest_mode(vcpu) ||
7831             !nested_cpu_has2(vmx->nested.current_vmcs12,
7832                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7833                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7834 }
7835
7836 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7837 {
7838         u16 status;
7839         u8 old;
7840
7841         if (isr == -1)
7842                 isr = 0;
7843
7844         status = vmcs_read16(GUEST_INTR_STATUS);
7845         old = status >> 8;
7846         if (isr != old) {
7847                 status &= 0xff;
7848                 status |= isr << 8;
7849                 vmcs_write16(GUEST_INTR_STATUS, status);
7850         }
7851 }
7852
7853 static void vmx_set_rvi(int vector)
7854 {
7855         u16 status;
7856         u8 old;
7857
7858         if (vector == -1)
7859                 vector = 0;
7860
7861         status = vmcs_read16(GUEST_INTR_STATUS);
7862         old = (u8)status & 0xff;
7863         if ((u8)vector != old) {
7864                 status &= ~0xff;
7865                 status |= (u8)vector;
7866                 vmcs_write16(GUEST_INTR_STATUS, status);
7867         }
7868 }
7869
7870 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7871 {
7872         if (!is_guest_mode(vcpu)) {
7873                 vmx_set_rvi(max_irr);
7874                 return;
7875         }
7876
7877         if (max_irr == -1)
7878                 return;
7879
7880         /*
7881          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7882          * handles it.
7883          */
7884         if (nested_exit_on_intr(vcpu))
7885                 return;
7886
7887         /*
7888          * Else, fall back to pre-APICv interrupt injection since L2
7889          * is run without virtual interrupt delivery.
7890          */
7891         if (!kvm_event_needs_reinjection(vcpu) &&
7892             vmx_interrupt_allowed(vcpu)) {
7893                 kvm_queue_interrupt(vcpu, max_irr, false);
7894                 vmx_inject_irq(vcpu);
7895         }
7896 }
7897
7898 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7899 {
7900         if (!vmx_vm_has_apicv(vcpu->kvm))
7901                 return;
7902
7903         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7904         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7905         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7906         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7907 }
7908
7909 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7910 {
7911         u32 exit_intr_info;
7912
7913         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7914               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7915                 return;
7916
7917         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7918         exit_intr_info = vmx->exit_intr_info;
7919
7920         /* Handle machine checks before interrupts are enabled */
7921         if (is_machine_check(exit_intr_info))
7922                 kvm_machine_check();
7923
7924         /* We need to handle NMIs before interrupts are enabled */
7925         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7926             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7927                 kvm_before_handle_nmi(&vmx->vcpu);
7928                 asm("int $2");
7929                 kvm_after_handle_nmi(&vmx->vcpu);
7930         }
7931 }
7932
7933 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7934 {
7935         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7936
7937         /*
7938          * If external interrupt exists, IF bit is set in rflags/eflags on the
7939          * interrupt stack frame, and interrupt will be enabled on a return
7940          * from interrupt handler.
7941          */
7942         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7943                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7944                 unsigned int vector;
7945                 unsigned long entry;
7946                 gate_desc *desc;
7947                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7948 #ifdef CONFIG_X86_64
7949                 unsigned long tmp;
7950 #endif
7951
7952                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7953                 desc = (gate_desc *)vmx->host_idt_base + vector;
7954                 entry = gate_offset(*desc);
7955                 asm volatile(
7956 #ifdef CONFIG_X86_64
7957                         "mov %%" _ASM_SP ", %[sp]\n\t"
7958                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7959                         "push $%c[ss]\n\t"
7960                         "push %[sp]\n\t"
7961 #endif
7962                         "pushf\n\t"
7963                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7964                         __ASM_SIZE(push) " $%c[cs]\n\t"
7965                         "call *%[entry]\n\t"
7966                         :
7967 #ifdef CONFIG_X86_64
7968                         [sp]"=&r"(tmp)
7969 #endif
7970                         :
7971                         [entry]"r"(entry),
7972                         [ss]"i"(__KERNEL_DS),
7973                         [cs]"i"(__KERNEL_CS)
7974                         );
7975         } else
7976                 local_irq_enable();
7977 }
7978
7979 static bool vmx_mpx_supported(void)
7980 {
7981         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7982                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7983 }
7984
7985 static bool vmx_xsaves_supported(void)
7986 {
7987         return vmcs_config.cpu_based_2nd_exec_ctrl &
7988                 SECONDARY_EXEC_XSAVES;
7989 }
7990
7991 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7992 {
7993         u32 exit_intr_info;
7994         bool unblock_nmi;
7995         u8 vector;
7996         bool idtv_info_valid;
7997
7998         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7999
8000         if (cpu_has_virtual_nmis()) {
8001                 if (vmx->nmi_known_unmasked)
8002                         return;
8003                 /*
8004                  * Can't use vmx->exit_intr_info since we're not sure what
8005                  * the exit reason is.
8006                  */
8007                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8008                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8009                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8010                 /*
8011                  * SDM 3: 27.7.1.2 (September 2008)
8012                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8013                  * a guest IRET fault.
8014                  * SDM 3: 23.2.2 (September 2008)
8015                  * Bit 12 is undefined in any of the following cases:
8016                  *  If the VM exit sets the valid bit in the IDT-vectoring
8017                  *   information field.
8018                  *  If the VM exit is due to a double fault.
8019                  */
8020                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8021                     vector != DF_VECTOR && !idtv_info_valid)
8022                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8023                                       GUEST_INTR_STATE_NMI);
8024                 else
8025                         vmx->nmi_known_unmasked =
8026                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8027                                   & GUEST_INTR_STATE_NMI);
8028         } else if (unlikely(vmx->soft_vnmi_blocked))
8029                 vmx->vnmi_blocked_time +=
8030                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8031 }
8032
8033 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8034                                       u32 idt_vectoring_info,
8035                                       int instr_len_field,
8036                                       int error_code_field)
8037 {
8038         u8 vector;
8039         int type;
8040         bool idtv_info_valid;
8041
8042         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8043
8044         vcpu->arch.nmi_injected = false;
8045         kvm_clear_exception_queue(vcpu);
8046         kvm_clear_interrupt_queue(vcpu);
8047
8048         if (!idtv_info_valid)
8049                 return;
8050
8051         kvm_make_request(KVM_REQ_EVENT, vcpu);
8052
8053         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8054         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8055
8056         switch (type) {
8057         case INTR_TYPE_NMI_INTR:
8058                 vcpu->arch.nmi_injected = true;
8059                 /*
8060                  * SDM 3: 27.7.1.2 (September 2008)
8061                  * Clear bit "block by NMI" before VM entry if a NMI
8062                  * delivery faulted.
8063                  */
8064                 vmx_set_nmi_mask(vcpu, false);
8065                 break;
8066         case INTR_TYPE_SOFT_EXCEPTION:
8067                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8068                 /* fall through */
8069         case INTR_TYPE_HARD_EXCEPTION:
8070                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8071                         u32 err = vmcs_read32(error_code_field);
8072                         kvm_requeue_exception_e(vcpu, vector, err);
8073                 } else
8074                         kvm_requeue_exception(vcpu, vector);
8075                 break;
8076         case INTR_TYPE_SOFT_INTR:
8077                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8078                 /* fall through */
8079         case INTR_TYPE_EXT_INTR:
8080                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8081                 break;
8082         default:
8083                 break;
8084         }
8085 }
8086
8087 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8088 {
8089         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8090                                   VM_EXIT_INSTRUCTION_LEN,
8091                                   IDT_VECTORING_ERROR_CODE);
8092 }
8093
8094 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8095 {
8096         __vmx_complete_interrupts(vcpu,
8097                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8098                                   VM_ENTRY_INSTRUCTION_LEN,
8099                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8100
8101         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8102 }
8103
8104 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8105 {
8106         int i, nr_msrs;
8107         struct perf_guest_switch_msr *msrs;
8108
8109         msrs = perf_guest_get_msrs(&nr_msrs);
8110
8111         if (!msrs)
8112                 return;
8113
8114         for (i = 0; i < nr_msrs; i++)
8115                 if (msrs[i].host == msrs[i].guest)
8116                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8117                 else
8118                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8119                                         msrs[i].host);
8120 }
8121
8122 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8123 {
8124         struct vcpu_vmx *vmx = to_vmx(vcpu);
8125         unsigned long debugctlmsr, cr4;
8126
8127         /* Record the guest's net vcpu time for enforced NMI injections. */
8128         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8129                 vmx->entry_time = ktime_get();
8130
8131         /* Don't enter VMX if guest state is invalid, let the exit handler
8132            start emulation until we arrive back to a valid state */
8133         if (vmx->emulation_required)
8134                 return;
8135
8136         if (vmx->ple_window_dirty) {
8137                 vmx->ple_window_dirty = false;
8138                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8139         }
8140
8141         if (vmx->nested.sync_shadow_vmcs) {
8142                 copy_vmcs12_to_shadow(vmx);
8143                 vmx->nested.sync_shadow_vmcs = false;
8144         }
8145
8146         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8147                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8148         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8149                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8150
8151         cr4 = cr4_read_shadow();
8152         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8153                 vmcs_writel(HOST_CR4, cr4);
8154                 vmx->host_state.vmcs_host_cr4 = cr4;
8155         }
8156
8157         /* When single-stepping over STI and MOV SS, we must clear the
8158          * corresponding interruptibility bits in the guest state. Otherwise
8159          * vmentry fails as it then expects bit 14 (BS) in pending debug
8160          * exceptions being set, but that's not correct for the guest debugging
8161          * case. */
8162         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8163                 vmx_set_interrupt_shadow(vcpu, 0);
8164
8165         atomic_switch_perf_msrs(vmx);
8166         debugctlmsr = get_debugctlmsr();
8167
8168         vmx->__launched = vmx->loaded_vmcs->launched;
8169         asm(
8170                 /* Store host registers */
8171                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8172                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8173                 "push %%" _ASM_CX " \n\t"
8174                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8175                 "je 1f \n\t"
8176                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8177                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8178                 "1: \n\t"
8179                 /* Reload cr2 if changed */
8180                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8181                 "mov %%cr2, %%" _ASM_DX " \n\t"
8182                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8183                 "je 2f \n\t"
8184                 "mov %%" _ASM_AX", %%cr2 \n\t"
8185                 "2: \n\t"
8186                 /* Check if vmlaunch of vmresume is needed */
8187                 "cmpl $0, %c[launched](%0) \n\t"
8188                 /* Load guest registers.  Don't clobber flags. */
8189                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8190                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8191                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8192                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8193                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8194                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8195 #ifdef CONFIG_X86_64
8196                 "mov %c[r8](%0),  %%r8  \n\t"
8197                 "mov %c[r9](%0),  %%r9  \n\t"
8198                 "mov %c[r10](%0), %%r10 \n\t"
8199                 "mov %c[r11](%0), %%r11 \n\t"
8200                 "mov %c[r12](%0), %%r12 \n\t"
8201                 "mov %c[r13](%0), %%r13 \n\t"
8202                 "mov %c[r14](%0), %%r14 \n\t"
8203                 "mov %c[r15](%0), %%r15 \n\t"
8204 #endif
8205                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8206
8207                 /* Enter guest mode */
8208                 "jne 1f \n\t"
8209                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8210                 "jmp 2f \n\t"
8211                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8212                 "2: "
8213                 /* Save guest registers, load host registers, keep flags */
8214                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8215                 "pop %0 \n\t"
8216                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8217                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8218                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8219                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8220                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8221                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8222                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8223 #ifdef CONFIG_X86_64
8224                 "mov %%r8,  %c[r8](%0) \n\t"
8225                 "mov %%r9,  %c[r9](%0) \n\t"
8226                 "mov %%r10, %c[r10](%0) \n\t"
8227                 "mov %%r11, %c[r11](%0) \n\t"
8228                 "mov %%r12, %c[r12](%0) \n\t"
8229                 "mov %%r13, %c[r13](%0) \n\t"
8230                 "mov %%r14, %c[r14](%0) \n\t"
8231                 "mov %%r15, %c[r15](%0) \n\t"
8232 #endif
8233                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8234                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8235
8236                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8237                 "setbe %c[fail](%0) \n\t"
8238                 ".pushsection .rodata \n\t"
8239                 ".global vmx_return \n\t"
8240                 "vmx_return: " _ASM_PTR " 2b \n\t"
8241                 ".popsection"
8242               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8243                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8244                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8245                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8246                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8247                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8248                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8249                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8250                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8251                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8252                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8253 #ifdef CONFIG_X86_64
8254                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8255                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8256                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8257                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8258                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8259                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8260                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8261                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8262 #endif
8263                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8264                 [wordsize]"i"(sizeof(ulong))
8265               : "cc", "memory"
8266 #ifdef CONFIG_X86_64
8267                 , "rax", "rbx", "rdi", "rsi"
8268                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8269 #else
8270                 , "eax", "ebx", "edi", "esi"
8271 #endif
8272               );
8273
8274         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8275         if (debugctlmsr)
8276                 update_debugctlmsr(debugctlmsr);
8277
8278 #ifndef CONFIG_X86_64
8279         /*
8280          * The sysexit path does not restore ds/es, so we must set them to
8281          * a reasonable value ourselves.
8282          *
8283          * We can't defer this to vmx_load_host_state() since that function
8284          * may be executed in interrupt context, which saves and restore segments
8285          * around it, nullifying its effect.
8286          */
8287         loadsegment(ds, __USER_DS);
8288         loadsegment(es, __USER_DS);
8289 #endif
8290
8291         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8292                                   | (1 << VCPU_EXREG_RFLAGS)
8293                                   | (1 << VCPU_EXREG_PDPTR)
8294                                   | (1 << VCPU_EXREG_SEGMENTS)
8295                                   | (1 << VCPU_EXREG_CR3));
8296         vcpu->arch.regs_dirty = 0;
8297
8298         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8299
8300         vmx->loaded_vmcs->launched = 1;
8301
8302         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8303         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8304
8305         /*
8306          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8307          * we did not inject a still-pending event to L1 now because of
8308          * nested_run_pending, we need to re-enable this bit.
8309          */
8310         if (vmx->nested.nested_run_pending)
8311                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8312
8313         vmx->nested.nested_run_pending = 0;
8314
8315         vmx_complete_atomic_exit(vmx);
8316         vmx_recover_nmi_blocking(vmx);
8317         vmx_complete_interrupts(vmx);
8318 }
8319
8320 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8321 {
8322         struct vcpu_vmx *vmx = to_vmx(vcpu);
8323         int cpu;
8324
8325         if (vmx->loaded_vmcs == &vmx->vmcs01)
8326                 return;
8327
8328         cpu = get_cpu();
8329         vmx->loaded_vmcs = &vmx->vmcs01;
8330         vmx_vcpu_put(vcpu);
8331         vmx_vcpu_load(vcpu, cpu);
8332         vcpu->cpu = cpu;
8333         put_cpu();
8334 }
8335
8336 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8337 {
8338         struct vcpu_vmx *vmx = to_vmx(vcpu);
8339
8340         if (enable_pml)
8341                 vmx_disable_pml(vmx);
8342         free_vpid(vmx);
8343         leave_guest_mode(vcpu);
8344         vmx_load_vmcs01(vcpu);
8345         free_nested(vmx);
8346         free_loaded_vmcs(vmx->loaded_vmcs);
8347         kfree(vmx->guest_msrs);
8348         kvm_vcpu_uninit(vcpu);
8349         kmem_cache_free(kvm_vcpu_cache, vmx);
8350 }
8351
8352 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8353 {
8354         int err;
8355         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8356         int cpu;
8357
8358         if (!vmx)
8359                 return ERR_PTR(-ENOMEM);
8360
8361         allocate_vpid(vmx);
8362
8363         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8364         if (err)
8365                 goto free_vcpu;
8366
8367         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8368         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8369                      > PAGE_SIZE);
8370
8371         err = -ENOMEM;
8372         if (!vmx->guest_msrs) {
8373                 goto uninit_vcpu;
8374         }
8375
8376         vmx->loaded_vmcs = &vmx->vmcs01;
8377         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8378         if (!vmx->loaded_vmcs->vmcs)
8379                 goto free_msrs;
8380         if (!vmm_exclusive)
8381                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8382         loaded_vmcs_init(vmx->loaded_vmcs);
8383         if (!vmm_exclusive)
8384                 kvm_cpu_vmxoff();
8385
8386         cpu = get_cpu();
8387         vmx_vcpu_load(&vmx->vcpu, cpu);
8388         vmx->vcpu.cpu = cpu;
8389         err = vmx_vcpu_setup(vmx);
8390         vmx_vcpu_put(&vmx->vcpu);
8391         put_cpu();
8392         if (err)
8393                 goto free_vmcs;
8394         if (vm_need_virtualize_apic_accesses(kvm)) {
8395                 err = alloc_apic_access_page(kvm);
8396                 if (err)
8397                         goto free_vmcs;
8398         }
8399
8400         if (enable_ept) {
8401                 if (!kvm->arch.ept_identity_map_addr)
8402                         kvm->arch.ept_identity_map_addr =
8403                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8404                 err = init_rmode_identity_map(kvm);
8405                 if (err)
8406                         goto free_vmcs;
8407         }
8408
8409         if (nested)
8410                 nested_vmx_setup_ctls_msrs(vmx);
8411
8412         vmx->nested.posted_intr_nv = -1;
8413         vmx->nested.current_vmptr = -1ull;
8414         vmx->nested.current_vmcs12 = NULL;
8415
8416         /*
8417          * If PML is turned on, failure on enabling PML just results in failure
8418          * of creating the vcpu, therefore we can simplify PML logic (by
8419          * avoiding dealing with cases, such as enabling PML partially on vcpus
8420          * for the guest, etc.
8421          */
8422         if (enable_pml) {
8423                 err = vmx_enable_pml(vmx);
8424                 if (err)
8425                         goto free_vmcs;
8426         }
8427
8428         return &vmx->vcpu;
8429
8430 free_vmcs:
8431         free_loaded_vmcs(vmx->loaded_vmcs);
8432 free_msrs:
8433         kfree(vmx->guest_msrs);
8434 uninit_vcpu:
8435         kvm_vcpu_uninit(&vmx->vcpu);
8436 free_vcpu:
8437         free_vpid(vmx);
8438         kmem_cache_free(kvm_vcpu_cache, vmx);
8439         return ERR_PTR(err);
8440 }
8441
8442 static void __init vmx_check_processor_compat(void *rtn)
8443 {
8444         struct vmcs_config vmcs_conf;
8445
8446         *(int *)rtn = 0;
8447         if (setup_vmcs_config(&vmcs_conf) < 0)
8448                 *(int *)rtn = -EIO;
8449         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8450                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8451                                 smp_processor_id());
8452                 *(int *)rtn = -EIO;
8453         }
8454 }
8455
8456 static int get_ept_level(void)
8457 {
8458         return VMX_EPT_DEFAULT_GAW + 1;
8459 }
8460
8461 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8462 {
8463         u64 ret;
8464
8465         /* For VT-d and EPT combination
8466          * 1. MMIO: always map as UC
8467          * 2. EPT with VT-d:
8468          *   a. VT-d without snooping control feature: can't guarantee the
8469          *      result, try to trust guest.
8470          *   b. VT-d with snooping control feature: snooping control feature of
8471          *      VT-d engine can guarantee the cache correctness. Just set it
8472          *      to WB to keep consistent with host. So the same as item 3.
8473          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8474          *    consistent with host MTRR
8475          */
8476         if (is_mmio)
8477                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8478         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8479                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8480                       VMX_EPT_MT_EPTE_SHIFT;
8481         else
8482                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8483                         | VMX_EPT_IPAT_BIT;
8484
8485         return ret;
8486 }
8487
8488 static int vmx_get_lpage_level(void)
8489 {
8490         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8491                 return PT_DIRECTORY_LEVEL;
8492         else
8493                 /* For shadow and EPT supported 1GB page */
8494                 return PT_PDPE_LEVEL;
8495 }
8496
8497 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8498 {
8499         struct kvm_cpuid_entry2 *best;
8500         struct vcpu_vmx *vmx = to_vmx(vcpu);
8501         u32 exec_control;
8502
8503         vmx->rdtscp_enabled = false;
8504         if (vmx_rdtscp_supported()) {
8505                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8506                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8507                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8508                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8509                                 vmx->rdtscp_enabled = true;
8510                         else {
8511                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8512                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8513                                                 exec_control);
8514                         }
8515                 }
8516         }
8517
8518         /* Exposing INVPCID only when PCID is exposed */
8519         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8520         if (vmx_invpcid_supported() &&
8521             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8522             guest_cpuid_has_pcid(vcpu)) {
8523                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8524                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8525                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8526                              exec_control);
8527         } else {
8528                 if (cpu_has_secondary_exec_ctrls()) {
8529                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8530                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8531                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8532                                      exec_control);
8533                 }
8534                 if (best)
8535                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8536         }
8537 }
8538
8539 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8540 {
8541         if (func == 1 && nested)
8542                 entry->ecx |= bit(X86_FEATURE_VMX);
8543 }
8544
8545 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8546                 struct x86_exception *fault)
8547 {
8548         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8549         u32 exit_reason;
8550
8551         if (fault->error_code & PFERR_RSVD_MASK)
8552                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8553         else
8554                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8555         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8556         vmcs12->guest_physical_address = fault->address;
8557 }
8558
8559 /* Callbacks for nested_ept_init_mmu_context: */
8560
8561 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8562 {
8563         /* return the page table to be shadowed - in our case, EPT12 */
8564         return get_vmcs12(vcpu)->ept_pointer;
8565 }
8566
8567 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8568 {
8569         WARN_ON(mmu_is_nested(vcpu));
8570         kvm_init_shadow_ept_mmu(vcpu,
8571                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8572                         VMX_EPT_EXECUTE_ONLY_BIT);
8573         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8574         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8575         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8576
8577         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8578 }
8579
8580 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8581 {
8582         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8583 }
8584
8585 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8586                                             u16 error_code)
8587 {
8588         bool inequality, bit;
8589
8590         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8591         inequality =
8592                 (error_code & vmcs12->page_fault_error_code_mask) !=
8593                  vmcs12->page_fault_error_code_match;
8594         return inequality ^ bit;
8595 }
8596
8597 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8598                 struct x86_exception *fault)
8599 {
8600         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8601
8602         WARN_ON(!is_guest_mode(vcpu));
8603
8604         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8605                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8606                                   vmcs_read32(VM_EXIT_INTR_INFO),
8607                                   vmcs_readl(EXIT_QUALIFICATION));
8608         else
8609                 kvm_inject_page_fault(vcpu, fault);
8610 }
8611
8612 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8613                                         struct vmcs12 *vmcs12)
8614 {
8615         struct vcpu_vmx *vmx = to_vmx(vcpu);
8616
8617         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8618                 /* TODO: Also verify bits beyond physical address width are 0 */
8619                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
8620                         return false;
8621
8622                 /*
8623                  * Translate L1 physical address to host physical
8624                  * address for vmcs02. Keep the page pinned, so this
8625                  * physical address remains valid. We keep a reference
8626                  * to it so we can release it later.
8627                  */
8628                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8629                         nested_release_page(vmx->nested.apic_access_page);
8630                 vmx->nested.apic_access_page =
8631                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8632         }
8633
8634         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8635                 /* TODO: Also verify bits beyond physical address width are 0 */
8636                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8637                         return false;
8638
8639                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8640                         nested_release_page(vmx->nested.virtual_apic_page);
8641                 vmx->nested.virtual_apic_page =
8642                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8643
8644                 /*
8645                  * Failing the vm entry is _not_ what the processor does
8646                  * but it's basically the only possibility we have.
8647                  * We could still enter the guest if CR8 load exits are
8648                  * enabled, CR8 store exits are enabled, and virtualize APIC
8649                  * access is disabled; in this case the processor would never
8650                  * use the TPR shadow and we could simply clear the bit from
8651                  * the execution control.  But such a configuration is useless,
8652                  * so let's keep the code simple.
8653                  */
8654                 if (!vmx->nested.virtual_apic_page)
8655                         return false;
8656         }
8657
8658         if (nested_cpu_has_posted_intr(vmcs12)) {
8659                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64))
8660                         return false;
8661
8662                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8663                         kunmap(vmx->nested.pi_desc_page);
8664                         nested_release_page(vmx->nested.pi_desc_page);
8665                 }
8666                 vmx->nested.pi_desc_page =
8667                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8668                 if (!vmx->nested.pi_desc_page)
8669                         return false;
8670
8671                 vmx->nested.pi_desc =
8672                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8673                 if (!vmx->nested.pi_desc) {
8674                         nested_release_page_clean(vmx->nested.pi_desc_page);
8675                         return false;
8676                 }
8677                 vmx->nested.pi_desc =
8678                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
8679                         (unsigned long)(vmcs12->posted_intr_desc_addr &
8680                         (PAGE_SIZE - 1)));
8681         }
8682
8683         return true;
8684 }
8685
8686 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8687 {
8688         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8689         struct vcpu_vmx *vmx = to_vmx(vcpu);
8690
8691         if (vcpu->arch.virtual_tsc_khz == 0)
8692                 return;
8693
8694         /* Make sure short timeouts reliably trigger an immediate vmexit.
8695          * hrtimer_start does not guarantee this. */
8696         if (preemption_timeout <= 1) {
8697                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8698                 return;
8699         }
8700
8701         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8702         preemption_timeout *= 1000000;
8703         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8704         hrtimer_start(&vmx->nested.preemption_timer,
8705                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8706 }
8707
8708 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8709                                                 struct vmcs12 *vmcs12)
8710 {
8711         int maxphyaddr;
8712         u64 addr;
8713
8714         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8715                 return 0;
8716
8717         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8718                 WARN_ON(1);
8719                 return -EINVAL;
8720         }
8721         maxphyaddr = cpuid_maxphyaddr(vcpu);
8722
8723         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8724            ((addr + PAGE_SIZE) >> maxphyaddr))
8725                 return -EINVAL;
8726
8727         return 0;
8728 }
8729
8730 /*
8731  * Merge L0's and L1's MSR bitmap, return false to indicate that
8732  * we do not use the hardware.
8733  */
8734 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8735                                                struct vmcs12 *vmcs12)
8736 {
8737         int msr;
8738         struct page *page;
8739         unsigned long *msr_bitmap;
8740
8741         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8742                 return false;
8743
8744         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8745         if (!page) {
8746                 WARN_ON(1);
8747                 return false;
8748         }
8749         msr_bitmap = (unsigned long *)kmap(page);
8750         if (!msr_bitmap) {
8751                 nested_release_page_clean(page);
8752                 WARN_ON(1);
8753                 return false;
8754         }
8755
8756         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8757                 if (nested_cpu_has_apic_reg_virt(vmcs12))
8758                         for (msr = 0x800; msr <= 0x8ff; msr++)
8759                                 nested_vmx_disable_intercept_for_msr(
8760                                         msr_bitmap,
8761                                         vmx_msr_bitmap_nested,
8762                                         msr, MSR_TYPE_R);
8763                 /* TPR is allowed */
8764                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8765                                 vmx_msr_bitmap_nested,
8766                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8767                                 MSR_TYPE_R | MSR_TYPE_W);
8768                 if (nested_cpu_has_vid(vmcs12)) {
8769                         /* EOI and self-IPI are allowed */
8770                         nested_vmx_disable_intercept_for_msr(
8771                                 msr_bitmap,
8772                                 vmx_msr_bitmap_nested,
8773                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8774                                 MSR_TYPE_W);
8775                         nested_vmx_disable_intercept_for_msr(
8776                                 msr_bitmap,
8777                                 vmx_msr_bitmap_nested,
8778                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8779                                 MSR_TYPE_W);
8780                 }
8781         } else {
8782                 /*
8783                  * Enable reading intercept of all the x2apic
8784                  * MSRs. We should not rely on vmcs12 to do any
8785                  * optimizations here, it may have been modified
8786                  * by L1.
8787                  */
8788                 for (msr = 0x800; msr <= 0x8ff; msr++)
8789                         __vmx_enable_intercept_for_msr(
8790                                 vmx_msr_bitmap_nested,
8791                                 msr,
8792                                 MSR_TYPE_R);
8793
8794                 __vmx_enable_intercept_for_msr(
8795                                 vmx_msr_bitmap_nested,
8796                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8797                                 MSR_TYPE_W);
8798                 __vmx_enable_intercept_for_msr(
8799                                 vmx_msr_bitmap_nested,
8800                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8801                                 MSR_TYPE_W);
8802                 __vmx_enable_intercept_for_msr(
8803                                 vmx_msr_bitmap_nested,
8804                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8805                                 MSR_TYPE_W);
8806         }
8807         kunmap(page);
8808         nested_release_page_clean(page);
8809
8810         return true;
8811 }
8812
8813 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8814                                            struct vmcs12 *vmcs12)
8815 {
8816         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8817             !nested_cpu_has_apic_reg_virt(vmcs12) &&
8818             !nested_cpu_has_vid(vmcs12) &&
8819             !nested_cpu_has_posted_intr(vmcs12))
8820                 return 0;
8821
8822         /*
8823          * If virtualize x2apic mode is enabled,
8824          * virtualize apic access must be disabled.
8825          */
8826         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8827             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8828                 return -EINVAL;
8829
8830         /*
8831          * If virtual interrupt delivery is enabled,
8832          * we must exit on external interrupts.
8833          */
8834         if (nested_cpu_has_vid(vmcs12) &&
8835            !nested_exit_on_intr(vcpu))
8836                 return -EINVAL;
8837
8838         /*
8839          * bits 15:8 should be zero in posted_intr_nv,
8840          * the descriptor address has been already checked
8841          * in nested_get_vmcs12_pages.
8842          */
8843         if (nested_cpu_has_posted_intr(vmcs12) &&
8844            (!nested_cpu_has_vid(vmcs12) ||
8845             !nested_exit_intr_ack_set(vcpu) ||
8846             vmcs12->posted_intr_nv & 0xff00))
8847                 return -EINVAL;
8848
8849         /* tpr shadow is needed by all apicv features. */
8850         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8851                 return -EINVAL;
8852
8853         return 0;
8854 }
8855
8856 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8857                                        unsigned long count_field,
8858                                        unsigned long addr_field,
8859                                        int maxphyaddr)
8860 {
8861         u64 count, addr;
8862
8863         if (vmcs12_read_any(vcpu, count_field, &count) ||
8864             vmcs12_read_any(vcpu, addr_field, &addr)) {
8865                 WARN_ON(1);
8866                 return -EINVAL;
8867         }
8868         if (count == 0)
8869                 return 0;
8870         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8871             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8872                 pr_warn_ratelimited(
8873                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8874                         addr_field, maxphyaddr, count, addr);
8875                 return -EINVAL;
8876         }
8877         return 0;
8878 }
8879
8880 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8881                                                 struct vmcs12 *vmcs12)
8882 {
8883         int maxphyaddr;
8884
8885         if (vmcs12->vm_exit_msr_load_count == 0 &&
8886             vmcs12->vm_exit_msr_store_count == 0 &&
8887             vmcs12->vm_entry_msr_load_count == 0)
8888                 return 0; /* Fast path */
8889         maxphyaddr = cpuid_maxphyaddr(vcpu);
8890         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8891                                         VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8892             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8893                                         VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8894             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8895                                         VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8896                 return -EINVAL;
8897         return 0;
8898 }
8899
8900 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8901                                        struct vmx_msr_entry *e)
8902 {
8903         /* x2APIC MSR accesses are not allowed */
8904         if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8905                 return -EINVAL;
8906         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8907             e->index == MSR_IA32_UCODE_REV)
8908                 return -EINVAL;
8909         if (e->reserved != 0)
8910                 return -EINVAL;
8911         return 0;
8912 }
8913
8914 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8915                                      struct vmx_msr_entry *e)
8916 {
8917         if (e->index == MSR_FS_BASE ||
8918             e->index == MSR_GS_BASE ||
8919             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8920             nested_vmx_msr_check_common(vcpu, e))
8921                 return -EINVAL;
8922         return 0;
8923 }
8924
8925 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8926                                       struct vmx_msr_entry *e)
8927 {
8928         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8929             nested_vmx_msr_check_common(vcpu, e))
8930                 return -EINVAL;
8931         return 0;
8932 }
8933
8934 /*
8935  * Load guest's/host's msr at nested entry/exit.
8936  * return 0 for success, entry index for failure.
8937  */
8938 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8939 {
8940         u32 i;
8941         struct vmx_msr_entry e;
8942         struct msr_data msr;
8943
8944         msr.host_initiated = false;
8945         for (i = 0; i < count; i++) {
8946                 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8947                                    &e, sizeof(e))) {
8948                         pr_warn_ratelimited(
8949                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8950                                 __func__, i, gpa + i * sizeof(e));
8951                         goto fail;
8952                 }
8953                 if (nested_vmx_load_msr_check(vcpu, &e)) {
8954                         pr_warn_ratelimited(
8955                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8956                                 __func__, i, e.index, e.reserved);
8957                         goto fail;
8958                 }
8959                 msr.index = e.index;
8960                 msr.data = e.value;
8961                 if (kvm_set_msr(vcpu, &msr)) {
8962                         pr_warn_ratelimited(
8963                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8964                                 __func__, i, e.index, e.value);
8965                         goto fail;
8966                 }
8967         }
8968         return 0;
8969 fail:
8970         return i + 1;
8971 }
8972
8973 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8974 {
8975         u32 i;
8976         struct vmx_msr_entry e;
8977
8978         for (i = 0; i < count; i++) {
8979                 if (kvm_read_guest(vcpu->kvm,
8980                                    gpa + i * sizeof(e),
8981                                    &e, 2 * sizeof(u32))) {
8982                         pr_warn_ratelimited(
8983                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8984                                 __func__, i, gpa + i * sizeof(e));
8985                         return -EINVAL;
8986                 }
8987                 if (nested_vmx_store_msr_check(vcpu, &e)) {
8988                         pr_warn_ratelimited(
8989                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8990                                 __func__, i, e.index, e.reserved);
8991                         return -EINVAL;
8992                 }
8993                 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8994                         pr_warn_ratelimited(
8995                                 "%s cannot read MSR (%u, 0x%x)\n",
8996                                 __func__, i, e.index);
8997                         return -EINVAL;
8998                 }
8999                 if (kvm_write_guest(vcpu->kvm,
9000                                     gpa + i * sizeof(e) +
9001                                         offsetof(struct vmx_msr_entry, value),
9002                                     &e.value, sizeof(e.value))) {
9003                         pr_warn_ratelimited(
9004                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9005                                 __func__, i, e.index, e.value);
9006                         return -EINVAL;
9007                 }
9008         }
9009         return 0;
9010 }
9011
9012 /*
9013  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9014  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9015  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9016  * guest in a way that will both be appropriate to L1's requests, and our
9017  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9018  * function also has additional necessary side-effects, like setting various
9019  * vcpu->arch fields.
9020  */
9021 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9022 {
9023         struct vcpu_vmx *vmx = to_vmx(vcpu);
9024         u32 exec_control;
9025
9026         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9027         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9028         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9029         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9030         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9031         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9032         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9033         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9034         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9035         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9036         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9037         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9038         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9039         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9040         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9041         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9042         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9043         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9044         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9045         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9046         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9047         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9048         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9049         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9050         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9051         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9052         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9053         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9054         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9055         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9056         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9057         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9058         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9059         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9060         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9061         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9062
9063         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9064                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9065                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9066         } else {
9067                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9068                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9069         }
9070         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9071                 vmcs12->vm_entry_intr_info_field);
9072         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9073                 vmcs12->vm_entry_exception_error_code);
9074         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9075                 vmcs12->vm_entry_instruction_len);
9076         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9077                 vmcs12->guest_interruptibility_info);
9078         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9079         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9080         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9081                 vmcs12->guest_pending_dbg_exceptions);
9082         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9083         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9084
9085         if (nested_cpu_has_xsaves(vmcs12))
9086                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9087         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9088
9089         exec_control = vmcs12->pin_based_vm_exec_control;
9090         exec_control |= vmcs_config.pin_based_exec_ctrl;
9091         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9092
9093         if (nested_cpu_has_posted_intr(vmcs12)) {
9094                 /*
9095                  * Note that we use L0's vector here and in
9096                  * vmx_deliver_nested_posted_interrupt.
9097                  */
9098                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9099                 vmx->nested.pi_pending = false;
9100                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9101                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9102                         page_to_phys(vmx->nested.pi_desc_page) +
9103                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9104                         (PAGE_SIZE - 1)));
9105         } else
9106                 exec_control &= ~PIN_BASED_POSTED_INTR;
9107
9108         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9109
9110         vmx->nested.preemption_timer_expired = false;
9111         if (nested_cpu_has_preemption_timer(vmcs12))
9112                 vmx_start_preemption_timer(vcpu);
9113
9114         /*
9115          * Whether page-faults are trapped is determined by a combination of
9116          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9117          * If enable_ept, L0 doesn't care about page faults and we should
9118          * set all of these to L1's desires. However, if !enable_ept, L0 does
9119          * care about (at least some) page faults, and because it is not easy
9120          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9121          * to exit on each and every L2 page fault. This is done by setting
9122          * MASK=MATCH=0 and (see below) EB.PF=1.
9123          * Note that below we don't need special code to set EB.PF beyond the
9124          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9125          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9126          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9127          *
9128          * A problem with this approach (when !enable_ept) is that L1 may be
9129          * injected with more page faults than it asked for. This could have
9130          * caused problems, but in practice existing hypervisors don't care.
9131          * To fix this, we will need to emulate the PFEC checking (on the L1
9132          * page tables), using walk_addr(), when injecting PFs to L1.
9133          */
9134         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9135                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9136         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9137                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9138
9139         if (cpu_has_secondary_exec_ctrls()) {
9140                 exec_control = vmx_secondary_exec_control(vmx);
9141                 if (!vmx->rdtscp_enabled)
9142                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
9143                 /* Take the following fields only from vmcs12 */
9144                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9145                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9146                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9147                 if (nested_cpu_has(vmcs12,
9148                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9149                         exec_control |= vmcs12->secondary_vm_exec_control;
9150
9151                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9152                         /*
9153                          * If translation failed, no matter: This feature asks
9154                          * to exit when accessing the given address, and if it
9155                          * can never be accessed, this feature won't do
9156                          * anything anyway.
9157                          */
9158                         if (!vmx->nested.apic_access_page)
9159                                 exec_control &=
9160                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9161                         else
9162                                 vmcs_write64(APIC_ACCESS_ADDR,
9163                                   page_to_phys(vmx->nested.apic_access_page));
9164                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9165                             (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9166                         exec_control |=
9167                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9168                         kvm_vcpu_reload_apic_access_page(vcpu);
9169                 }
9170
9171                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9172                         vmcs_write64(EOI_EXIT_BITMAP0,
9173                                 vmcs12->eoi_exit_bitmap0);
9174                         vmcs_write64(EOI_EXIT_BITMAP1,
9175                                 vmcs12->eoi_exit_bitmap1);
9176                         vmcs_write64(EOI_EXIT_BITMAP2,
9177                                 vmcs12->eoi_exit_bitmap2);
9178                         vmcs_write64(EOI_EXIT_BITMAP3,
9179                                 vmcs12->eoi_exit_bitmap3);
9180                         vmcs_write16(GUEST_INTR_STATUS,
9181                                 vmcs12->guest_intr_status);
9182                 }
9183
9184                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9185         }
9186
9187
9188         /*
9189          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9190          * Some constant fields are set here by vmx_set_constant_host_state().
9191          * Other fields are different per CPU, and will be set later when
9192          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9193          */
9194         vmx_set_constant_host_state(vmx);
9195
9196         /*
9197          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9198          * entry, but only if the current (host) sp changed from the value
9199          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9200          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9201          * here we just force the write to happen on entry.
9202          */
9203         vmx->host_rsp = 0;
9204
9205         exec_control = vmx_exec_control(vmx); /* L0's desires */
9206         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9207         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9208         exec_control &= ~CPU_BASED_TPR_SHADOW;
9209         exec_control |= vmcs12->cpu_based_vm_exec_control;
9210
9211         if (exec_control & CPU_BASED_TPR_SHADOW) {
9212                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9213                                 page_to_phys(vmx->nested.virtual_apic_page));
9214                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9215         }
9216
9217         if (cpu_has_vmx_msr_bitmap() &&
9218             exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9219             nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
9220                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
9221         } else
9222                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9223
9224         /*
9225          * Merging of IO bitmap not currently supported.
9226          * Rather, exit every time.
9227          */
9228         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9229         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9230
9231         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9232
9233         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9234          * bitwise-or of what L1 wants to trap for L2, and what we want to
9235          * trap. Note that CR0.TS also needs updating - we do this later.
9236          */
9237         update_exception_bitmap(vcpu);
9238         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9239         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9240
9241         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9242          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9243          * bits are further modified by vmx_set_efer() below.
9244          */
9245         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9246
9247         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9248          * emulated by vmx_set_efer(), below.
9249          */
9250         vm_entry_controls_init(vmx,
9251                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9252                         ~VM_ENTRY_IA32E_MODE) |
9253                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9254
9255         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9256                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9257                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9258         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9259                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9260
9261
9262         set_cr4_guest_host_mask(vmx);
9263
9264         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9265                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9266
9267         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9268                 vmcs_write64(TSC_OFFSET,
9269                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9270         else
9271                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9272
9273         if (enable_vpid) {
9274                 /*
9275                  * Trivially support vpid by letting L2s share their parent
9276                  * L1's vpid. TODO: move to a more elaborate solution, giving
9277                  * each L2 its own vpid and exposing the vpid feature to L1.
9278                  */
9279                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9280                 vmx_flush_tlb(vcpu);
9281         }
9282
9283         if (nested_cpu_has_ept(vmcs12)) {
9284                 kvm_mmu_unload(vcpu);
9285                 nested_ept_init_mmu_context(vcpu);
9286         }
9287
9288         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9289                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9290         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9291                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9292         else
9293                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9294         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9295         vmx_set_efer(vcpu, vcpu->arch.efer);
9296
9297         /*
9298          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9299          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9300          * The CR0_READ_SHADOW is what L2 should have expected to read given
9301          * the specifications by L1; It's not enough to take
9302          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9303          * have more bits than L1 expected.
9304          */
9305         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9306         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9307
9308         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9309         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9310
9311         /* shadow page tables on either EPT or shadow page tables */
9312         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9313         kvm_mmu_reset_context(vcpu);
9314
9315         if (!enable_ept)
9316                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9317
9318         /*
9319          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9320          */
9321         if (enable_ept) {
9322                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9323                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9324                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9325                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9326         }
9327
9328         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9329         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9330 }
9331
9332 /*
9333  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9334  * for running an L2 nested guest.
9335  */
9336 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9337 {
9338         struct vmcs12 *vmcs12;
9339         struct vcpu_vmx *vmx = to_vmx(vcpu);
9340         int cpu;
9341         struct loaded_vmcs *vmcs02;
9342         bool ia32e;
9343         u32 msr_entry_idx;
9344
9345         if (!nested_vmx_check_permission(vcpu) ||
9346             !nested_vmx_check_vmcs12(vcpu))
9347                 return 1;
9348
9349         skip_emulated_instruction(vcpu);
9350         vmcs12 = get_vmcs12(vcpu);
9351
9352         if (enable_shadow_vmcs)
9353                 copy_shadow_to_vmcs12(vmx);
9354
9355         /*
9356          * The nested entry process starts with enforcing various prerequisites
9357          * on vmcs12 as required by the Intel SDM, and act appropriately when
9358          * they fail: As the SDM explains, some conditions should cause the
9359          * instruction to fail, while others will cause the instruction to seem
9360          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9361          * To speed up the normal (success) code path, we should avoid checking
9362          * for misconfigurations which will anyway be caught by the processor
9363          * when using the merged vmcs02.
9364          */
9365         if (vmcs12->launch_state == launch) {
9366                 nested_vmx_failValid(vcpu,
9367                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9368                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9369                 return 1;
9370         }
9371
9372         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9373             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9374                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9375                 return 1;
9376         }
9377
9378         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9379                 /*TODO: Also verify bits beyond physical address width are 0*/
9380                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9381                 return 1;
9382         }
9383
9384         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9385                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9386                 return 1;
9387         }
9388
9389         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9390                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9391                 return 1;
9392         }
9393
9394         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9395                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9396                 return 1;
9397         }
9398
9399         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9400                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9401                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9402             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9403                                 vmx->nested.nested_vmx_secondary_ctls_low,
9404                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9405             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9406                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9407                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9408             !vmx_control_verify(vmcs12->vm_exit_controls,
9409                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9410                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9411             !vmx_control_verify(vmcs12->vm_entry_controls,
9412                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9413                                 vmx->nested.nested_vmx_entry_ctls_high))
9414         {
9415                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9416                 return 1;
9417         }
9418
9419         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9420             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9421                 nested_vmx_failValid(vcpu,
9422                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9423                 return 1;
9424         }
9425
9426         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9427             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9428                 nested_vmx_entry_failure(vcpu, vmcs12,
9429                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9430                 return 1;
9431         }
9432         if (vmcs12->vmcs_link_pointer != -1ull) {
9433                 nested_vmx_entry_failure(vcpu, vmcs12,
9434                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9435                 return 1;
9436         }
9437
9438         /*
9439          * If the load IA32_EFER VM-entry control is 1, the following checks
9440          * are performed on the field for the IA32_EFER MSR:
9441          * - Bits reserved in the IA32_EFER MSR must be 0.
9442          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9443          *   the IA-32e mode guest VM-exit control. It must also be identical
9444          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9445          *   CR0.PG) is 1.
9446          */
9447         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9448                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9449                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9450                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9451                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9452                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9453                         nested_vmx_entry_failure(vcpu, vmcs12,
9454                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9455                         return 1;
9456                 }
9457         }
9458
9459         /*
9460          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9461          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9462          * the values of the LMA and LME bits in the field must each be that of
9463          * the host address-space size VM-exit control.
9464          */
9465         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9466                 ia32e = (vmcs12->vm_exit_controls &
9467                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9468                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9469                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9470                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9471                         nested_vmx_entry_failure(vcpu, vmcs12,
9472                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9473                         return 1;
9474                 }
9475         }
9476
9477         /*
9478          * We're finally done with prerequisite checking, and can start with
9479          * the nested entry.
9480          */
9481
9482         vmcs02 = nested_get_current_vmcs02(vmx);
9483         if (!vmcs02)
9484                 return -ENOMEM;
9485
9486         enter_guest_mode(vcpu);
9487
9488         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9489
9490         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9491                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9492
9493         cpu = get_cpu();
9494         vmx->loaded_vmcs = vmcs02;
9495         vmx_vcpu_put(vcpu);
9496         vmx_vcpu_load(vcpu, cpu);
9497         vcpu->cpu = cpu;
9498         put_cpu();
9499
9500         vmx_segment_cache_clear(vmx);
9501
9502         prepare_vmcs02(vcpu, vmcs12);
9503
9504         msr_entry_idx = nested_vmx_load_msr(vcpu,
9505                                             vmcs12->vm_entry_msr_load_addr,
9506                                             vmcs12->vm_entry_msr_load_count);
9507         if (msr_entry_idx) {
9508                 leave_guest_mode(vcpu);
9509                 vmx_load_vmcs01(vcpu);
9510                 nested_vmx_entry_failure(vcpu, vmcs12,
9511                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9512                 return 1;
9513         }
9514
9515         vmcs12->launch_state = 1;
9516
9517         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9518                 return kvm_vcpu_halt(vcpu);
9519
9520         vmx->nested.nested_run_pending = 1;
9521
9522         /*
9523          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9524          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9525          * returned as far as L1 is concerned. It will only return (and set
9526          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9527          */
9528         return 1;
9529 }
9530
9531 /*
9532  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9533  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9534  * This function returns the new value we should put in vmcs12.guest_cr0.
9535  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9536  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9537  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9538  *     didn't trap the bit, because if L1 did, so would L0).
9539  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9540  *     been modified by L2, and L1 knows it. So just leave the old value of
9541  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9542  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9543  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9544  *     changed these bits, and therefore they need to be updated, but L0
9545  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9546  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9547  */
9548 static inline unsigned long
9549 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9550 {
9551         return
9552         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9553         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9554         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9555                         vcpu->arch.cr0_guest_owned_bits));
9556 }
9557
9558 static inline unsigned long
9559 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9560 {
9561         return
9562         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9563         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9564         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9565                         vcpu->arch.cr4_guest_owned_bits));
9566 }
9567
9568 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9569                                        struct vmcs12 *vmcs12)
9570 {
9571         u32 idt_vectoring;
9572         unsigned int nr;
9573
9574         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9575                 nr = vcpu->arch.exception.nr;
9576                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9577
9578                 if (kvm_exception_is_soft(nr)) {
9579                         vmcs12->vm_exit_instruction_len =
9580                                 vcpu->arch.event_exit_inst_len;
9581                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9582                 } else
9583                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9584
9585                 if (vcpu->arch.exception.has_error_code) {
9586                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9587                         vmcs12->idt_vectoring_error_code =
9588                                 vcpu->arch.exception.error_code;
9589                 }
9590
9591                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9592         } else if (vcpu->arch.nmi_injected) {
9593                 vmcs12->idt_vectoring_info_field =
9594                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9595         } else if (vcpu->arch.interrupt.pending) {
9596                 nr = vcpu->arch.interrupt.nr;
9597                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9598
9599                 if (vcpu->arch.interrupt.soft) {
9600                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9601                         vmcs12->vm_entry_instruction_len =
9602                                 vcpu->arch.event_exit_inst_len;
9603                 } else
9604                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9605
9606                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9607         }
9608 }
9609
9610 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9611 {
9612         struct vcpu_vmx *vmx = to_vmx(vcpu);
9613
9614         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9615             vmx->nested.preemption_timer_expired) {
9616                 if (vmx->nested.nested_run_pending)
9617                         return -EBUSY;
9618                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9619                 return 0;
9620         }
9621
9622         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9623                 if (vmx->nested.nested_run_pending ||
9624                     vcpu->arch.interrupt.pending)
9625                         return -EBUSY;
9626                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9627                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
9628                                   INTR_INFO_VALID_MASK, 0);
9629                 /*
9630                  * The NMI-triggered VM exit counts as injection:
9631                  * clear this one and block further NMIs.
9632                  */
9633                 vcpu->arch.nmi_pending = 0;
9634                 vmx_set_nmi_mask(vcpu, true);
9635                 return 0;
9636         }
9637
9638         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9639             nested_exit_on_intr(vcpu)) {
9640                 if (vmx->nested.nested_run_pending)
9641                         return -EBUSY;
9642                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9643                 return 0;
9644         }
9645
9646         return vmx_complete_nested_posted_interrupt(vcpu);
9647 }
9648
9649 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9650 {
9651         ktime_t remaining =
9652                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9653         u64 value;
9654
9655         if (ktime_to_ns(remaining) <= 0)
9656                 return 0;
9657
9658         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9659         do_div(value, 1000000);
9660         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9661 }
9662
9663 /*
9664  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9665  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9666  * and this function updates it to reflect the changes to the guest state while
9667  * L2 was running (and perhaps made some exits which were handled directly by L0
9668  * without going back to L1), and to reflect the exit reason.
9669  * Note that we do not have to copy here all VMCS fields, just those that
9670  * could have changed by the L2 guest or the exit - i.e., the guest-state and
9671  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9672  * which already writes to vmcs12 directly.
9673  */
9674 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9675                            u32 exit_reason, u32 exit_intr_info,
9676                            unsigned long exit_qualification)
9677 {
9678         /* update guest state fields: */
9679         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9680         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9681
9682         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9683         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9684         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9685
9686         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9687         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9688         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9689         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9690         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9691         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9692         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9693         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9694         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9695         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9696         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9697         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9698         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9699         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9700         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9701         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9702         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9703         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9704         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9705         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9706         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9707         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9708         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9709         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9710         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9711         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9712         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9713         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9714         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9715         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9716         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9717         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9718         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9719         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9720         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9721         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9722
9723         vmcs12->guest_interruptibility_info =
9724                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9725         vmcs12->guest_pending_dbg_exceptions =
9726                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9727         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9728                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9729         else
9730                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9731
9732         if (nested_cpu_has_preemption_timer(vmcs12)) {
9733                 if (vmcs12->vm_exit_controls &
9734                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9735                         vmcs12->vmx_preemption_timer_value =
9736                                 vmx_get_preemption_timer_value(vcpu);
9737                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9738         }
9739
9740         /*
9741          * In some cases (usually, nested EPT), L2 is allowed to change its
9742          * own CR3 without exiting. If it has changed it, we must keep it.
9743          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9744          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9745          *
9746          * Additionally, restore L2's PDPTR to vmcs12.
9747          */
9748         if (enable_ept) {
9749                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9750                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9751                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9752                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9753                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9754         }
9755
9756         if (nested_cpu_has_vid(vmcs12))
9757                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9758
9759         vmcs12->vm_entry_controls =
9760                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9761                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9762
9763         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9764                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9765                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9766         }
9767
9768         /* TODO: These cannot have changed unless we have MSR bitmaps and
9769          * the relevant bit asks not to trap the change */
9770         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9771                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9772         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9773                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9774         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9775         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9776         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9777         if (vmx_mpx_supported())
9778                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9779         if (nested_cpu_has_xsaves(vmcs12))
9780                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9781
9782         /* update exit information fields: */
9783
9784         vmcs12->vm_exit_reason = exit_reason;
9785         vmcs12->exit_qualification = exit_qualification;
9786
9787         vmcs12->vm_exit_intr_info = exit_intr_info;
9788         if ((vmcs12->vm_exit_intr_info &
9789              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9790             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9791                 vmcs12->vm_exit_intr_error_code =
9792                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9793         vmcs12->idt_vectoring_info_field = 0;
9794         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9795         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9796
9797         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9798                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9799                  * instead of reading the real value. */
9800                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9801
9802                 /*
9803                  * Transfer the event that L0 or L1 may wanted to inject into
9804                  * L2 to IDT_VECTORING_INFO_FIELD.
9805                  */
9806                 vmcs12_save_pending_event(vcpu, vmcs12);
9807         }
9808
9809         /*
9810          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9811          * preserved above and would only end up incorrectly in L1.
9812          */
9813         vcpu->arch.nmi_injected = false;
9814         kvm_clear_exception_queue(vcpu);
9815         kvm_clear_interrupt_queue(vcpu);
9816 }
9817
9818 /*
9819  * A part of what we need to when the nested L2 guest exits and we want to
9820  * run its L1 parent, is to reset L1's guest state to the host state specified
9821  * in vmcs12.
9822  * This function is to be called not only on normal nested exit, but also on
9823  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9824  * Failures During or After Loading Guest State").
9825  * This function should be called when the active VMCS is L1's (vmcs01).
9826  */
9827 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9828                                    struct vmcs12 *vmcs12)
9829 {
9830         struct kvm_segment seg;
9831
9832         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9833                 vcpu->arch.efer = vmcs12->host_ia32_efer;
9834         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9835                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9836         else
9837                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9838         vmx_set_efer(vcpu, vcpu->arch.efer);
9839
9840         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9841         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9842         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9843         /*
9844          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9845          * actually changed, because it depends on the current state of
9846          * fpu_active (which may have changed).
9847          * Note that vmx_set_cr0 refers to efer set above.
9848          */
9849         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9850         /*
9851          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9852          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9853          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9854          */
9855         update_exception_bitmap(vcpu);
9856         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9857         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9858
9859         /*
9860          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9861          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9862          */
9863         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9864         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9865
9866         nested_ept_uninit_mmu_context(vcpu);
9867
9868         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9869         kvm_mmu_reset_context(vcpu);
9870
9871         if (!enable_ept)
9872                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9873
9874         if (enable_vpid) {
9875                 /*
9876                  * Trivially support vpid by letting L2s share their parent
9877                  * L1's vpid. TODO: move to a more elaborate solution, giving
9878                  * each L2 its own vpid and exposing the vpid feature to L1.
9879                  */
9880                 vmx_flush_tlb(vcpu);
9881         }
9882
9883
9884         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9885         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9886         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9887         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9888         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9889
9890         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9891         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9892                 vmcs_write64(GUEST_BNDCFGS, 0);
9893
9894         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9895                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9896                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9897         }
9898         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9899                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9900                         vmcs12->host_ia32_perf_global_ctrl);
9901
9902         /* Set L1 segment info according to Intel SDM
9903             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9904         seg = (struct kvm_segment) {
9905                 .base = 0,
9906                 .limit = 0xFFFFFFFF,
9907                 .selector = vmcs12->host_cs_selector,
9908                 .type = 11,
9909                 .present = 1,
9910                 .s = 1,
9911                 .g = 1
9912         };
9913         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9914                 seg.l = 1;
9915         else
9916                 seg.db = 1;
9917         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9918         seg = (struct kvm_segment) {
9919                 .base = 0,
9920                 .limit = 0xFFFFFFFF,
9921                 .type = 3,
9922                 .present = 1,
9923                 .s = 1,
9924                 .db = 1,
9925                 .g = 1
9926         };
9927         seg.selector = vmcs12->host_ds_selector;
9928         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9929         seg.selector = vmcs12->host_es_selector;
9930         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9931         seg.selector = vmcs12->host_ss_selector;
9932         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9933         seg.selector = vmcs12->host_fs_selector;
9934         seg.base = vmcs12->host_fs_base;
9935         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9936         seg.selector = vmcs12->host_gs_selector;
9937         seg.base = vmcs12->host_gs_base;
9938         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9939         seg = (struct kvm_segment) {
9940                 .base = vmcs12->host_tr_base,
9941                 .limit = 0x67,
9942                 .selector = vmcs12->host_tr_selector,
9943                 .type = 11,
9944                 .present = 1
9945         };
9946         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9947
9948         kvm_set_dr(vcpu, 7, 0x400);
9949         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9950
9951         if (cpu_has_vmx_msr_bitmap())
9952                 vmx_set_msr_bitmap(vcpu);
9953
9954         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9955                                 vmcs12->vm_exit_msr_load_count))
9956                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9957 }
9958
9959 /*
9960  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9961  * and modify vmcs12 to make it see what it would expect to see there if
9962  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9963  */
9964 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9965                               u32 exit_intr_info,
9966                               unsigned long exit_qualification)
9967 {
9968         struct vcpu_vmx *vmx = to_vmx(vcpu);
9969         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9970
9971         /* trying to cancel vmlaunch/vmresume is a bug */
9972         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9973
9974         leave_guest_mode(vcpu);
9975         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9976                        exit_qualification);
9977
9978         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9979                                  vmcs12->vm_exit_msr_store_count))
9980                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9981
9982         vmx_load_vmcs01(vcpu);
9983
9984         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9985             && nested_exit_intr_ack_set(vcpu)) {
9986                 int irq = kvm_cpu_get_interrupt(vcpu);
9987                 WARN_ON(irq < 0);
9988                 vmcs12->vm_exit_intr_info = irq |
9989                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9990         }
9991
9992         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9993                                        vmcs12->exit_qualification,
9994                                        vmcs12->idt_vectoring_info_field,
9995                                        vmcs12->vm_exit_intr_info,
9996                                        vmcs12->vm_exit_intr_error_code,
9997                                        KVM_ISA_VMX);
9998
9999         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10000         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10001         vmx_segment_cache_clear(vmx);
10002
10003         /* if no vmcs02 cache requested, remove the one we used */
10004         if (VMCS02_POOL_SIZE == 0)
10005                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10006
10007         load_vmcs12_host_state(vcpu, vmcs12);
10008
10009         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10010         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10011
10012         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10013         vmx->host_rsp = 0;
10014
10015         /* Unpin physical memory we referred to in vmcs02 */
10016         if (vmx->nested.apic_access_page) {
10017                 nested_release_page(vmx->nested.apic_access_page);
10018                 vmx->nested.apic_access_page = NULL;
10019         }
10020         if (vmx->nested.virtual_apic_page) {
10021                 nested_release_page(vmx->nested.virtual_apic_page);
10022                 vmx->nested.virtual_apic_page = NULL;
10023         }
10024         if (vmx->nested.pi_desc_page) {
10025                 kunmap(vmx->nested.pi_desc_page);
10026                 nested_release_page(vmx->nested.pi_desc_page);
10027                 vmx->nested.pi_desc_page = NULL;
10028                 vmx->nested.pi_desc = NULL;
10029         }
10030
10031         /*
10032          * We are now running in L2, mmu_notifier will force to reload the
10033          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10034          */
10035         kvm_vcpu_reload_apic_access_page(vcpu);
10036
10037         /*
10038          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10039          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10040          * success or failure flag accordingly.
10041          */
10042         if (unlikely(vmx->fail)) {
10043                 vmx->fail = 0;
10044                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10045         } else
10046                 nested_vmx_succeed(vcpu);
10047         if (enable_shadow_vmcs)
10048                 vmx->nested.sync_shadow_vmcs = true;
10049
10050         /* in case we halted in L2 */
10051         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10052 }
10053
10054 /*
10055  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10056  */
10057 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10058 {
10059         if (is_guest_mode(vcpu))
10060                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10061         free_nested(to_vmx(vcpu));
10062 }
10063
10064 /*
10065  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10066  * 23.7 "VM-entry failures during or after loading guest state" (this also
10067  * lists the acceptable exit-reason and exit-qualification parameters).
10068  * It should only be called before L2 actually succeeded to run, and when
10069  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10070  */
10071 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10072                         struct vmcs12 *vmcs12,
10073                         u32 reason, unsigned long qualification)
10074 {
10075         load_vmcs12_host_state(vcpu, vmcs12);
10076         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10077         vmcs12->exit_qualification = qualification;
10078         nested_vmx_succeed(vcpu);
10079         if (enable_shadow_vmcs)
10080                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10081 }
10082
10083 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10084                                struct x86_instruction_info *info,
10085                                enum x86_intercept_stage stage)
10086 {
10087         return X86EMUL_CONTINUE;
10088 }
10089
10090 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10091 {
10092         if (ple_gap)
10093                 shrink_ple_window(vcpu);
10094 }
10095
10096 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10097                                      struct kvm_memory_slot *slot)
10098 {
10099         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10100         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10101 }
10102
10103 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10104                                        struct kvm_memory_slot *slot)
10105 {
10106         kvm_mmu_slot_set_dirty(kvm, slot);
10107 }
10108
10109 static void vmx_flush_log_dirty(struct kvm *kvm)
10110 {
10111         kvm_flush_pml_buffers(kvm);
10112 }
10113
10114 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10115                                            struct kvm_memory_slot *memslot,
10116                                            gfn_t offset, unsigned long mask)
10117 {
10118         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10119 }
10120
10121 static struct kvm_x86_ops vmx_x86_ops = {
10122         .cpu_has_kvm_support = cpu_has_kvm_support,
10123         .disabled_by_bios = vmx_disabled_by_bios,
10124         .hardware_setup = hardware_setup,
10125         .hardware_unsetup = hardware_unsetup,
10126         .check_processor_compatibility = vmx_check_processor_compat,
10127         .hardware_enable = hardware_enable,
10128         .hardware_disable = hardware_disable,
10129         .cpu_has_accelerated_tpr = report_flexpriority,
10130
10131         .vcpu_create = vmx_create_vcpu,
10132         .vcpu_free = vmx_free_vcpu,
10133         .vcpu_reset = vmx_vcpu_reset,
10134
10135         .prepare_guest_switch = vmx_save_host_state,
10136         .vcpu_load = vmx_vcpu_load,
10137         .vcpu_put = vmx_vcpu_put,
10138
10139         .update_db_bp_intercept = update_exception_bitmap,
10140         .get_msr = vmx_get_msr,
10141         .set_msr = vmx_set_msr,
10142         .get_segment_base = vmx_get_segment_base,
10143         .get_segment = vmx_get_segment,
10144         .set_segment = vmx_set_segment,
10145         .get_cpl = vmx_get_cpl,
10146         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10147         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10148         .decache_cr3 = vmx_decache_cr3,
10149         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10150         .set_cr0 = vmx_set_cr0,
10151         .set_cr3 = vmx_set_cr3,
10152         .set_cr4 = vmx_set_cr4,
10153         .set_efer = vmx_set_efer,
10154         .get_idt = vmx_get_idt,
10155         .set_idt = vmx_set_idt,
10156         .get_gdt = vmx_get_gdt,
10157         .set_gdt = vmx_set_gdt,
10158         .get_dr6 = vmx_get_dr6,
10159         .set_dr6 = vmx_set_dr6,
10160         .set_dr7 = vmx_set_dr7,
10161         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10162         .cache_reg = vmx_cache_reg,
10163         .get_rflags = vmx_get_rflags,
10164         .set_rflags = vmx_set_rflags,
10165         .fpu_deactivate = vmx_fpu_deactivate,
10166
10167         .tlb_flush = vmx_flush_tlb,
10168
10169         .run = vmx_vcpu_run,
10170         .handle_exit = vmx_handle_exit,
10171         .skip_emulated_instruction = skip_emulated_instruction,
10172         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10173         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10174         .patch_hypercall = vmx_patch_hypercall,
10175         .set_irq = vmx_inject_irq,
10176         .set_nmi = vmx_inject_nmi,
10177         .queue_exception = vmx_queue_exception,
10178         .cancel_injection = vmx_cancel_injection,
10179         .interrupt_allowed = vmx_interrupt_allowed,
10180         .nmi_allowed = vmx_nmi_allowed,
10181         .get_nmi_mask = vmx_get_nmi_mask,
10182         .set_nmi_mask = vmx_set_nmi_mask,
10183         .enable_nmi_window = enable_nmi_window,
10184         .enable_irq_window = enable_irq_window,
10185         .update_cr8_intercept = update_cr8_intercept,
10186         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10187         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10188         .vm_has_apicv = vmx_vm_has_apicv,
10189         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10190         .hwapic_irr_update = vmx_hwapic_irr_update,
10191         .hwapic_isr_update = vmx_hwapic_isr_update,
10192         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10193         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10194
10195         .set_tss_addr = vmx_set_tss_addr,
10196         .get_tdp_level = get_ept_level,
10197         .get_mt_mask = vmx_get_mt_mask,
10198
10199         .get_exit_info = vmx_get_exit_info,
10200
10201         .get_lpage_level = vmx_get_lpage_level,
10202
10203         .cpuid_update = vmx_cpuid_update,
10204
10205         .rdtscp_supported = vmx_rdtscp_supported,
10206         .invpcid_supported = vmx_invpcid_supported,
10207
10208         .set_supported_cpuid = vmx_set_supported_cpuid,
10209
10210         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10211
10212         .set_tsc_khz = vmx_set_tsc_khz,
10213         .read_tsc_offset = vmx_read_tsc_offset,
10214         .write_tsc_offset = vmx_write_tsc_offset,
10215         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10216         .compute_tsc_offset = vmx_compute_tsc_offset,
10217         .read_l1_tsc = vmx_read_l1_tsc,
10218
10219         .set_tdp_cr3 = vmx_set_cr3,
10220
10221         .check_intercept = vmx_check_intercept,
10222         .handle_external_intr = vmx_handle_external_intr,
10223         .mpx_supported = vmx_mpx_supported,
10224         .xsaves_supported = vmx_xsaves_supported,
10225
10226         .check_nested_events = vmx_check_nested_events,
10227
10228         .sched_in = vmx_sched_in,
10229
10230         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10231         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10232         .flush_log_dirty = vmx_flush_log_dirty,
10233         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10234 };
10235
10236 static int __init vmx_init(void)
10237 {
10238         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10239                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10240         if (r)
10241                 return r;
10242
10243 #ifdef CONFIG_KEXEC
10244         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10245                            crash_vmclear_local_loaded_vmcss);
10246 #endif
10247
10248         return 0;
10249 }
10250
10251 static void __exit vmx_exit(void)
10252 {
10253 #ifdef CONFIG_KEXEC
10254         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10255         synchronize_rcu();
10256 #endif
10257
10258         kvm_exit();
10259 }
10260
10261 module_init(vmx_init)
10262 module_exit(vmx_exit)