2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
43 #include <asm/fpu/internal.h>
44 #include <asm/perf_event.h>
45 #include <asm/debugreg.h>
46 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64 static bool __read_mostly enable_vpid = 1;
65 module_param_named(vpid, enable_vpid, bool, 0444);
67 static bool __read_mostly flexpriority_enabled = 1;
68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
70 static bool __read_mostly enable_ept = 1;
71 module_param_named(ept, enable_ept, bool, S_IRUGO);
73 static bool __read_mostly enable_unrestricted_guest = 1;
74 module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
77 static bool __read_mostly enable_ept_ad_bits = 1;
78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80 static bool __read_mostly emulate_invalid_guest_state = true;
81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
83 static bool __read_mostly vmm_exclusive = 1;
84 module_param(vmm_exclusive, bool, S_IRUGO);
86 static bool __read_mostly fasteoi = 1;
87 module_param(fasteoi, bool, S_IRUGO);
89 static bool __read_mostly enable_apicv = 1;
90 module_param(enable_apicv, bool, S_IRUGO);
92 static bool __read_mostly enable_shadow_vmcs = 1;
93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested = 0;
100 module_param(nested, bool, S_IRUGO);
102 static u64 __read_mostly host_xss;
104 static bool __read_mostly enable_pml = 1;
105 module_param_named(pml, enable_pml, bool, S_IRUGO);
107 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
108 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
109 #define KVM_VM_CR0_ALWAYS_ON \
110 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
111 #define KVM_CR4_GUEST_OWNED_BITS \
112 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
113 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
115 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
116 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
123 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
124 * ple_gap: upper bound on the amount of time between two successive
125 * executions of PAUSE in a loop. Also indicate if ple enabled.
126 * According to test, this time is usually smaller than 128 cycles.
127 * ple_window: upper bound on the amount of time a guest is allowed to execute
128 * in a PAUSE loop. Tests indicate that most spinlocks are held for
129 * less than 2^12 cycles
130 * Time is measured based on a counter that runs at the same rate as the TSC,
131 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 #define KVM_VMX_DEFAULT_PLE_GAP 128
134 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
135 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
138 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
141 module_param(ple_gap, int, S_IRUGO);
143 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
144 module_param(ple_window, int, S_IRUGO);
146 /* Default doubles per-vcpu window every exit. */
147 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
148 module_param(ple_window_grow, int, S_IRUGO);
150 /* Default resets per-vcpu window every exit to ple_window. */
151 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
152 module_param(ple_window_shrink, int, S_IRUGO);
154 /* Default is to compute the maximum so we can never overflow. */
155 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
156 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157 module_param(ple_window_max, int, S_IRUGO);
159 extern const ulong vmx_return;
161 #define NR_AUTOLOAD_MSRS 8
162 #define VMCS02_POOL_SIZE 1
171 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
172 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
173 * loaded on this CPU (so we can clear them if the CPU goes down).
179 struct list_head loaded_vmcss_on_cpu_link;
182 struct shared_msr_entry {
189 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
190 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
191 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
192 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
193 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
194 * More than one of these structures may exist, if L1 runs multiple L2 guests.
195 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
196 * underlying hardware which will be used to run L2.
197 * This structure is packed to ensure that its layout is identical across
198 * machines (necessary for live migration).
199 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 typedef u64 natural_width;
202 struct __packed vmcs12 {
203 /* According to the Intel spec, a VMCS region must start with the
204 * following two fields. Then follow implementation-specific data.
209 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
210 u32 padding[7]; /* room for future expansion */
215 u64 vm_exit_msr_store_addr;
216 u64 vm_exit_msr_load_addr;
217 u64 vm_entry_msr_load_addr;
219 u64 virtual_apic_page_addr;
220 u64 apic_access_addr;
221 u64 posted_intr_desc_addr;
223 u64 eoi_exit_bitmap0;
224 u64 eoi_exit_bitmap1;
225 u64 eoi_exit_bitmap2;
226 u64 eoi_exit_bitmap3;
228 u64 guest_physical_address;
229 u64 vmcs_link_pointer;
230 u64 guest_ia32_debugctl;
233 u64 guest_ia32_perf_global_ctrl;
241 u64 host_ia32_perf_global_ctrl;
242 u64 padding64[8]; /* room for future expansion */
244 * To allow migration of L1 (complete with its L2 guests) between
245 * machines of different natural widths (32 or 64 bit), we cannot have
246 * unsigned long fields with no explict size. We use u64 (aliased
247 * natural_width) instead. Luckily, x86 is little-endian.
249 natural_width cr0_guest_host_mask;
250 natural_width cr4_guest_host_mask;
251 natural_width cr0_read_shadow;
252 natural_width cr4_read_shadow;
253 natural_width cr3_target_value0;
254 natural_width cr3_target_value1;
255 natural_width cr3_target_value2;
256 natural_width cr3_target_value3;
257 natural_width exit_qualification;
258 natural_width guest_linear_address;
259 natural_width guest_cr0;
260 natural_width guest_cr3;
261 natural_width guest_cr4;
262 natural_width guest_es_base;
263 natural_width guest_cs_base;
264 natural_width guest_ss_base;
265 natural_width guest_ds_base;
266 natural_width guest_fs_base;
267 natural_width guest_gs_base;
268 natural_width guest_ldtr_base;
269 natural_width guest_tr_base;
270 natural_width guest_gdtr_base;
271 natural_width guest_idtr_base;
272 natural_width guest_dr7;
273 natural_width guest_rsp;
274 natural_width guest_rip;
275 natural_width guest_rflags;
276 natural_width guest_pending_dbg_exceptions;
277 natural_width guest_sysenter_esp;
278 natural_width guest_sysenter_eip;
279 natural_width host_cr0;
280 natural_width host_cr3;
281 natural_width host_cr4;
282 natural_width host_fs_base;
283 natural_width host_gs_base;
284 natural_width host_tr_base;
285 natural_width host_gdtr_base;
286 natural_width host_idtr_base;
287 natural_width host_ia32_sysenter_esp;
288 natural_width host_ia32_sysenter_eip;
289 natural_width host_rsp;
290 natural_width host_rip;
291 natural_width paddingl[8]; /* room for future expansion */
292 u32 pin_based_vm_exec_control;
293 u32 cpu_based_vm_exec_control;
294 u32 exception_bitmap;
295 u32 page_fault_error_code_mask;
296 u32 page_fault_error_code_match;
297 u32 cr3_target_count;
298 u32 vm_exit_controls;
299 u32 vm_exit_msr_store_count;
300 u32 vm_exit_msr_load_count;
301 u32 vm_entry_controls;
302 u32 vm_entry_msr_load_count;
303 u32 vm_entry_intr_info_field;
304 u32 vm_entry_exception_error_code;
305 u32 vm_entry_instruction_len;
307 u32 secondary_vm_exec_control;
308 u32 vm_instruction_error;
310 u32 vm_exit_intr_info;
311 u32 vm_exit_intr_error_code;
312 u32 idt_vectoring_info_field;
313 u32 idt_vectoring_error_code;
314 u32 vm_exit_instruction_len;
315 u32 vmx_instruction_info;
322 u32 guest_ldtr_limit;
324 u32 guest_gdtr_limit;
325 u32 guest_idtr_limit;
326 u32 guest_es_ar_bytes;
327 u32 guest_cs_ar_bytes;
328 u32 guest_ss_ar_bytes;
329 u32 guest_ds_ar_bytes;
330 u32 guest_fs_ar_bytes;
331 u32 guest_gs_ar_bytes;
332 u32 guest_ldtr_ar_bytes;
333 u32 guest_tr_ar_bytes;
334 u32 guest_interruptibility_info;
335 u32 guest_activity_state;
336 u32 guest_sysenter_cs;
337 u32 host_ia32_sysenter_cs;
338 u32 vmx_preemption_timer_value;
339 u32 padding32[7]; /* room for future expansion */
340 u16 virtual_processor_id;
342 u16 guest_es_selector;
343 u16 guest_cs_selector;
344 u16 guest_ss_selector;
345 u16 guest_ds_selector;
346 u16 guest_fs_selector;
347 u16 guest_gs_selector;
348 u16 guest_ldtr_selector;
349 u16 guest_tr_selector;
350 u16 guest_intr_status;
351 u16 host_es_selector;
352 u16 host_cs_selector;
353 u16 host_ss_selector;
354 u16 host_ds_selector;
355 u16 host_fs_selector;
356 u16 host_gs_selector;
357 u16 host_tr_selector;
361 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
362 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
363 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 #define VMCS12_REVISION 0x11e57ed0
368 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
369 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
370 * current implementation, 4K are reserved to avoid future complications.
372 #define VMCS12_SIZE 0x1000
374 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
376 struct list_head list;
378 struct loaded_vmcs vmcs02;
382 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
383 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
386 /* Has the level1 guest done vmxon? */
390 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 /* The host-usable pointer to the above */
393 struct page *current_vmcs12_page;
394 struct vmcs12 *current_vmcs12;
395 struct vmcs *current_shadow_vmcs;
397 * Indicates if the shadow vmcs must be updated with the
398 * data hold by vmcs12
400 bool sync_shadow_vmcs;
402 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
403 struct list_head vmcs02_pool;
405 u64 vmcs01_tsc_offset;
406 /* L2 must run next, and mustn't decide to exit to L1. */
407 bool nested_run_pending;
409 * Guest pages referred to in vmcs02 with host-physical pointers, so
410 * we must keep them pinned while L2 runs.
412 struct page *apic_access_page;
413 struct page *virtual_apic_page;
414 struct page *pi_desc_page;
415 struct pi_desc *pi_desc;
418 u64 msr_ia32_feature_control;
420 struct hrtimer preemption_timer;
421 bool preemption_timer_expired;
423 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
426 u32 nested_vmx_procbased_ctls_low;
427 u32 nested_vmx_procbased_ctls_high;
428 u32 nested_vmx_true_procbased_ctls_low;
429 u32 nested_vmx_secondary_ctls_low;
430 u32 nested_vmx_secondary_ctls_high;
431 u32 nested_vmx_pinbased_ctls_low;
432 u32 nested_vmx_pinbased_ctls_high;
433 u32 nested_vmx_exit_ctls_low;
434 u32 nested_vmx_exit_ctls_high;
435 u32 nested_vmx_true_exit_ctls_low;
436 u32 nested_vmx_entry_ctls_low;
437 u32 nested_vmx_entry_ctls_high;
438 u32 nested_vmx_true_entry_ctls_low;
439 u32 nested_vmx_misc_low;
440 u32 nested_vmx_misc_high;
441 u32 nested_vmx_ept_caps;
444 #define POSTED_INTR_ON 0
445 /* Posted-Interrupt Descriptor */
447 u32 pir[8]; /* Posted interrupt requested */
448 u32 control; /* bit 0 of control is outstanding notification bit */
452 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454 return test_and_set_bit(POSTED_INTR_ON,
455 (unsigned long *)&pi_desc->control);
458 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460 return test_and_clear_bit(POSTED_INTR_ON,
461 (unsigned long *)&pi_desc->control);
464 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
470 struct kvm_vcpu vcpu;
471 unsigned long host_rsp;
473 bool nmi_known_unmasked;
475 u32 idt_vectoring_info;
477 struct shared_msr_entry *guest_msrs;
480 unsigned long host_idt_base;
482 u64 msr_host_kernel_gs_base;
483 u64 msr_guest_kernel_gs_base;
485 u32 vm_entry_controls_shadow;
486 u32 vm_exit_controls_shadow;
488 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
489 * non-nested (L1) guest, it always points to vmcs01. For a nested
490 * guest (L2), it points to a different VMCS.
492 struct loaded_vmcs vmcs01;
493 struct loaded_vmcs *loaded_vmcs;
494 bool __launched; /* temporary, used in vmx_vcpu_run */
495 struct msr_autoload {
497 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
498 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
502 u16 fs_sel, gs_sel, ldt_sel;
506 int gs_ldt_reload_needed;
507 int fs_reload_needed;
508 u64 msr_host_bndcfgs;
509 unsigned long vmcs_host_cr4; /* May not match real cr4 */
514 struct kvm_segment segs[8];
517 u32 bitmask; /* 4 bits per segment (1 bit per field) */
518 struct kvm_save_segment {
526 bool emulation_required;
528 /* Support for vnmi-less CPUs */
529 int soft_vnmi_blocked;
531 s64 vnmi_blocked_time;
536 /* Posted interrupt descriptor */
537 struct pi_desc pi_desc;
539 /* Support for a guest hypervisor (nested VMX) */
540 struct nested_vmx nested;
542 /* Dynamic PLE window. */
544 bool ple_window_dirty;
546 /* Support for PML */
547 #define PML_ENTITY_NUM 512
551 enum segment_cache_field {
560 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562 return container_of(vcpu, struct vcpu_vmx, vcpu);
565 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
566 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
567 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
568 [number##_HIGH] = VMCS12_OFFSET(name)+4
571 static unsigned long shadow_read_only_fields[] = {
573 * We do NOT shadow fields that are modified when L0
574 * traps and emulates any vmx instruction (e.g. VMPTRLD,
575 * VMXON...) executed by L1.
576 * For example, VM_INSTRUCTION_ERROR is read
577 * by L1 if a vmx instruction fails (part of the error path).
578 * Note the code assumes this logic. If for some reason
579 * we start shadowing these fields then we need to
580 * force a shadow sync when L0 emulates vmx instructions
581 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
582 * by nested_vmx_failValid)
586 VM_EXIT_INSTRUCTION_LEN,
587 IDT_VECTORING_INFO_FIELD,
588 IDT_VECTORING_ERROR_CODE,
589 VM_EXIT_INTR_ERROR_CODE,
591 GUEST_LINEAR_ADDRESS,
592 GUEST_PHYSICAL_ADDRESS
594 static int max_shadow_read_only_fields =
595 ARRAY_SIZE(shadow_read_only_fields);
597 static unsigned long shadow_read_write_fields[] = {
604 GUEST_INTERRUPTIBILITY_INFO,
617 CPU_BASED_VM_EXEC_CONTROL,
618 VM_ENTRY_EXCEPTION_ERROR_CODE,
619 VM_ENTRY_INTR_INFO_FIELD,
620 VM_ENTRY_INSTRUCTION_LEN,
621 VM_ENTRY_EXCEPTION_ERROR_CODE,
627 static int max_shadow_read_write_fields =
628 ARRAY_SIZE(shadow_read_write_fields);
630 static const unsigned short vmcs_field_to_offset_table[] = {
631 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
632 FIELD(POSTED_INTR_NV, posted_intr_nv),
633 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
634 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
635 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
636 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
637 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
638 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
639 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
640 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
641 FIELD(GUEST_INTR_STATUS, guest_intr_status),
642 FIELD(HOST_ES_SELECTOR, host_es_selector),
643 FIELD(HOST_CS_SELECTOR, host_cs_selector),
644 FIELD(HOST_SS_SELECTOR, host_ss_selector),
645 FIELD(HOST_DS_SELECTOR, host_ds_selector),
646 FIELD(HOST_FS_SELECTOR, host_fs_selector),
647 FIELD(HOST_GS_SELECTOR, host_gs_selector),
648 FIELD(HOST_TR_SELECTOR, host_tr_selector),
649 FIELD64(IO_BITMAP_A, io_bitmap_a),
650 FIELD64(IO_BITMAP_B, io_bitmap_b),
651 FIELD64(MSR_BITMAP, msr_bitmap),
652 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
653 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
654 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
655 FIELD64(TSC_OFFSET, tsc_offset),
656 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
657 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
658 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
659 FIELD64(EPT_POINTER, ept_pointer),
660 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
661 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
662 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
663 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
664 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
665 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
666 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
667 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
668 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
669 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
670 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
671 FIELD64(GUEST_PDPTR0, guest_pdptr0),
672 FIELD64(GUEST_PDPTR1, guest_pdptr1),
673 FIELD64(GUEST_PDPTR2, guest_pdptr2),
674 FIELD64(GUEST_PDPTR3, guest_pdptr3),
675 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
676 FIELD64(HOST_IA32_PAT, host_ia32_pat),
677 FIELD64(HOST_IA32_EFER, host_ia32_efer),
678 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
679 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
680 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
681 FIELD(EXCEPTION_BITMAP, exception_bitmap),
682 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
683 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
684 FIELD(CR3_TARGET_COUNT, cr3_target_count),
685 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
686 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
687 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
688 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
689 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
690 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
691 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
692 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
693 FIELD(TPR_THRESHOLD, tpr_threshold),
694 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
695 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
696 FIELD(VM_EXIT_REASON, vm_exit_reason),
697 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
698 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
699 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
700 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
701 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
702 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
703 FIELD(GUEST_ES_LIMIT, guest_es_limit),
704 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
705 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
706 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
707 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
708 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
709 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
710 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
711 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
712 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
713 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
714 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
715 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
716 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
717 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
718 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
719 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
720 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
721 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
722 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
723 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
724 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
725 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
726 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
727 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
728 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
729 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
730 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
731 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
732 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
733 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
734 FIELD(EXIT_QUALIFICATION, exit_qualification),
735 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
736 FIELD(GUEST_CR0, guest_cr0),
737 FIELD(GUEST_CR3, guest_cr3),
738 FIELD(GUEST_CR4, guest_cr4),
739 FIELD(GUEST_ES_BASE, guest_es_base),
740 FIELD(GUEST_CS_BASE, guest_cs_base),
741 FIELD(GUEST_SS_BASE, guest_ss_base),
742 FIELD(GUEST_DS_BASE, guest_ds_base),
743 FIELD(GUEST_FS_BASE, guest_fs_base),
744 FIELD(GUEST_GS_BASE, guest_gs_base),
745 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
746 FIELD(GUEST_TR_BASE, guest_tr_base),
747 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
748 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
749 FIELD(GUEST_DR7, guest_dr7),
750 FIELD(GUEST_RSP, guest_rsp),
751 FIELD(GUEST_RIP, guest_rip),
752 FIELD(GUEST_RFLAGS, guest_rflags),
753 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
754 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
755 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
756 FIELD(HOST_CR0, host_cr0),
757 FIELD(HOST_CR3, host_cr3),
758 FIELD(HOST_CR4, host_cr4),
759 FIELD(HOST_FS_BASE, host_fs_base),
760 FIELD(HOST_GS_BASE, host_gs_base),
761 FIELD(HOST_TR_BASE, host_tr_base),
762 FIELD(HOST_GDTR_BASE, host_gdtr_base),
763 FIELD(HOST_IDTR_BASE, host_idtr_base),
764 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
765 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
766 FIELD(HOST_RSP, host_rsp),
767 FIELD(HOST_RIP, host_rip),
770 static inline short vmcs_field_to_offset(unsigned long field)
772 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
775 vmcs_field_to_offset_table[field] == 0)
778 return vmcs_field_to_offset_table[field];
781 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783 return to_vmx(vcpu)->nested.current_vmcs12;
786 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
789 if (is_error_page(page))
795 static void nested_release_page(struct page *page)
797 kvm_release_page_dirty(page);
800 static void nested_release_page_clean(struct page *page)
802 kvm_release_page_clean(page);
805 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
806 static u64 construct_eptp(unsigned long root_hpa);
807 static void kvm_cpu_vmxon(u64 addr);
808 static void kvm_cpu_vmxoff(void);
809 static bool vmx_mpx_supported(void);
810 static bool vmx_xsaves_supported(void);
811 static int vmx_vm_has_apicv(struct kvm *kvm);
812 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
813 static void vmx_set_segment(struct kvm_vcpu *vcpu,
814 struct kvm_segment *var, int seg);
815 static void vmx_get_segment(struct kvm_vcpu *vcpu,
816 struct kvm_segment *var, int seg);
817 static bool guest_state_valid(struct kvm_vcpu *vcpu);
818 static u32 vmx_segment_access_rights(struct kvm_segment *var);
819 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
820 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
821 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
822 static int alloc_identity_pagetable(struct kvm *kvm);
824 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
825 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
827 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
828 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
831 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
833 static unsigned long *vmx_io_bitmap_a;
834 static unsigned long *vmx_io_bitmap_b;
835 static unsigned long *vmx_msr_bitmap_legacy;
836 static unsigned long *vmx_msr_bitmap_longmode;
837 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
838 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
839 static unsigned long *vmx_msr_bitmap_nested;
840 static unsigned long *vmx_vmread_bitmap;
841 static unsigned long *vmx_vmwrite_bitmap;
843 static bool cpu_has_load_ia32_efer;
844 static bool cpu_has_load_perf_global_ctrl;
846 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
847 static DEFINE_SPINLOCK(vmx_vpid_lock);
849 static struct vmcs_config {
853 u32 pin_based_exec_ctrl;
854 u32 cpu_based_exec_ctrl;
855 u32 cpu_based_2nd_exec_ctrl;
860 static struct vmx_capability {
865 #define VMX_SEGMENT_FIELD(seg) \
866 [VCPU_SREG_##seg] = { \
867 .selector = GUEST_##seg##_SELECTOR, \
868 .base = GUEST_##seg##_BASE, \
869 .limit = GUEST_##seg##_LIMIT, \
870 .ar_bytes = GUEST_##seg##_AR_BYTES, \
873 static const struct kvm_vmx_segment_field {
878 } kvm_vmx_segment_fields[] = {
879 VMX_SEGMENT_FIELD(CS),
880 VMX_SEGMENT_FIELD(DS),
881 VMX_SEGMENT_FIELD(ES),
882 VMX_SEGMENT_FIELD(FS),
883 VMX_SEGMENT_FIELD(GS),
884 VMX_SEGMENT_FIELD(SS),
885 VMX_SEGMENT_FIELD(TR),
886 VMX_SEGMENT_FIELD(LDTR),
889 static u64 host_efer;
891 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
894 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
895 * away by decrementing the array size.
897 static const u32 vmx_msr_index[] = {
899 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
901 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
904 static inline bool is_page_fault(u32 intr_info)
906 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
907 INTR_INFO_VALID_MASK)) ==
908 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
911 static inline bool is_no_device(u32 intr_info)
913 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
914 INTR_INFO_VALID_MASK)) ==
915 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
918 static inline bool is_invalid_opcode(u32 intr_info)
920 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
921 INTR_INFO_VALID_MASK)) ==
922 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
925 static inline bool is_external_interrupt(u32 intr_info)
927 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
928 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
931 static inline bool is_machine_check(u32 intr_info)
933 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
934 INTR_INFO_VALID_MASK)) ==
935 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
938 static inline bool cpu_has_vmx_msr_bitmap(void)
940 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
943 static inline bool cpu_has_vmx_tpr_shadow(void)
945 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
948 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
950 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
953 static inline bool cpu_has_secondary_exec_ctrls(void)
955 return vmcs_config.cpu_based_exec_ctrl &
956 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
959 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
961 return vmcs_config.cpu_based_2nd_exec_ctrl &
962 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
965 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967 return vmcs_config.cpu_based_2nd_exec_ctrl &
968 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
971 static inline bool cpu_has_vmx_apic_register_virt(void)
973 return vmcs_config.cpu_based_2nd_exec_ctrl &
974 SECONDARY_EXEC_APIC_REGISTER_VIRT;
977 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
983 static inline bool cpu_has_vmx_posted_intr(void)
985 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
988 static inline bool cpu_has_vmx_apicv(void)
990 return cpu_has_vmx_apic_register_virt() &&
991 cpu_has_vmx_virtual_intr_delivery() &&
992 cpu_has_vmx_posted_intr();
995 static inline bool cpu_has_vmx_flexpriority(void)
997 return cpu_has_vmx_tpr_shadow() &&
998 cpu_has_vmx_virtualize_apic_accesses();
1001 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1006 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1011 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1016 static inline bool cpu_has_vmx_ept_4levels(void)
1018 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1021 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 return vmx_capability.ept & VMX_EPT_AD_BIT;
1026 static inline bool cpu_has_vmx_invept_context(void)
1028 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1031 static inline bool cpu_has_vmx_invept_global(void)
1033 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1036 static inline bool cpu_has_vmx_invvpid_single(void)
1038 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1041 static inline bool cpu_has_vmx_invvpid_global(void)
1043 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1046 static inline bool cpu_has_vmx_ept(void)
1048 return vmcs_config.cpu_based_2nd_exec_ctrl &
1049 SECONDARY_EXEC_ENABLE_EPT;
1052 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 return vmcs_config.cpu_based_2nd_exec_ctrl &
1055 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1058 static inline bool cpu_has_vmx_ple(void)
1060 return vmcs_config.cpu_based_2nd_exec_ctrl &
1061 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1064 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 return flexpriority_enabled && irqchip_in_kernel(kvm);
1069 static inline bool cpu_has_vmx_vpid(void)
1071 return vmcs_config.cpu_based_2nd_exec_ctrl &
1072 SECONDARY_EXEC_ENABLE_VPID;
1075 static inline bool cpu_has_vmx_rdtscp(void)
1077 return vmcs_config.cpu_based_2nd_exec_ctrl &
1078 SECONDARY_EXEC_RDTSCP;
1081 static inline bool cpu_has_vmx_invpcid(void)
1083 return vmcs_config.cpu_based_2nd_exec_ctrl &
1084 SECONDARY_EXEC_ENABLE_INVPCID;
1087 static inline bool cpu_has_virtual_nmis(void)
1089 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1092 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 return vmcs_config.cpu_based_2nd_exec_ctrl &
1095 SECONDARY_EXEC_WBINVD_EXITING;
1098 static inline bool cpu_has_vmx_shadow_vmcs(void)
1101 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1102 /* check if the cpu supports writing r/o exit information fields */
1103 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1106 return vmcs_config.cpu_based_2nd_exec_ctrl &
1107 SECONDARY_EXEC_SHADOW_VMCS;
1110 static inline bool cpu_has_vmx_pml(void)
1112 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1115 static inline bool report_flexpriority(void)
1117 return flexpriority_enabled;
1120 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 return vmcs12->cpu_based_vm_exec_control & bit;
1125 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 return (vmcs12->cpu_based_vm_exec_control &
1128 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1129 (vmcs12->secondary_vm_exec_control & bit);
1132 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1137 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 return vmcs12->pin_based_vm_exec_control &
1140 PIN_BASED_VMX_PREEMPTION_TIMER;
1143 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1148 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1151 vmx_xsaves_supported();
1154 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1159 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1164 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1169 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1174 static inline bool is_exception(u32 intr_info)
1176 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1177 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1180 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182 unsigned long exit_qualification);
1183 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1184 struct vmcs12 *vmcs12,
1185 u32 reason, unsigned long qualification);
1187 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1191 for (i = 0; i < vmx->nmsrs; ++i)
1192 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1197 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1203 } operand = { vpid, 0, gva };
1205 asm volatile (__ex(ASM_VMX_INVVPID)
1206 /* CF==1 or ZF==1 --> rc = -1 */
1207 "; ja 1f ; ud2 ; 1:"
1208 : : "a"(&operand), "c"(ext) : "cc", "memory");
1211 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1215 } operand = {eptp, gpa};
1217 asm volatile (__ex(ASM_VMX_INVEPT)
1218 /* CF==1 or ZF==1 --> rc = -1 */
1219 "; ja 1f ; ud2 ; 1:\n"
1220 : : "a" (&operand), "c" (ext) : "cc", "memory");
1223 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1227 i = __find_msr_index(vmx, msr);
1229 return &vmx->guest_msrs[i];
1233 static void vmcs_clear(struct vmcs *vmcs)
1235 u64 phys_addr = __pa(vmcs);
1238 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1239 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1242 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1246 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 vmcs_clear(loaded_vmcs->vmcs);
1249 loaded_vmcs->cpu = -1;
1250 loaded_vmcs->launched = 0;
1253 static void vmcs_load(struct vmcs *vmcs)
1255 u64 phys_addr = __pa(vmcs);
1258 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1259 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1262 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1268 * This bitmap is used to indicate whether the vmclear
1269 * operation is enabled on all cpus. All disabled by
1272 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274 static inline void crash_enable_local_vmclear(int cpu)
1276 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1279 static inline void crash_disable_local_vmclear(int cpu)
1281 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1284 static inline int crash_local_vmclear_enabled(int cpu)
1286 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1289 static void crash_vmclear_local_loaded_vmcss(void)
1291 int cpu = raw_smp_processor_id();
1292 struct loaded_vmcs *v;
1294 if (!crash_local_vmclear_enabled(cpu))
1297 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1298 loaded_vmcss_on_cpu_link)
1299 vmcs_clear(v->vmcs);
1302 static inline void crash_enable_local_vmclear(int cpu) { }
1303 static inline void crash_disable_local_vmclear(int cpu) { }
1304 #endif /* CONFIG_KEXEC */
1306 static void __loaded_vmcs_clear(void *arg)
1308 struct loaded_vmcs *loaded_vmcs = arg;
1309 int cpu = raw_smp_processor_id();
1311 if (loaded_vmcs->cpu != cpu)
1312 return; /* vcpu migration can race with cpu offline */
1313 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1314 per_cpu(current_vmcs, cpu) = NULL;
1315 crash_disable_local_vmclear(cpu);
1316 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1319 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1320 * is before setting loaded_vmcs->vcpu to -1 which is done in
1321 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1322 * then adds the vmcs into percpu list before it is deleted.
1326 loaded_vmcs_init(loaded_vmcs);
1327 crash_enable_local_vmclear(cpu);
1330 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 int cpu = loaded_vmcs->cpu;
1335 smp_call_function_single(cpu,
1336 __loaded_vmcs_clear, loaded_vmcs, 1);
1339 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1344 if (cpu_has_vmx_invvpid_single())
1345 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1348 static inline void vpid_sync_vcpu_global(void)
1350 if (cpu_has_vmx_invvpid_global())
1351 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1354 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 if (cpu_has_vmx_invvpid_single())
1357 vpid_sync_vcpu_single(vmx);
1359 vpid_sync_vcpu_global();
1362 static inline void ept_sync_global(void)
1364 if (cpu_has_vmx_invept_global())
1365 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1368 static inline void ept_sync_context(u64 eptp)
1371 if (cpu_has_vmx_invept_context())
1372 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1378 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 unsigned long value;
1382 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1383 : "=a"(value) : "d"(field) : "cc");
1387 static __always_inline u16 vmcs_read16(unsigned long field)
1389 return vmcs_readl(field);
1392 static __always_inline u32 vmcs_read32(unsigned long field)
1394 return vmcs_readl(field);
1397 static __always_inline u64 vmcs_read64(unsigned long field)
1399 #ifdef CONFIG_X86_64
1400 return vmcs_readl(field);
1402 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1406 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1409 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1413 static void vmcs_writel(unsigned long field, unsigned long value)
1417 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1418 : "=q"(error) : "a"(value), "d"(field) : "cc");
1419 if (unlikely(error))
1420 vmwrite_error(field, value);
1423 static void vmcs_write16(unsigned long field, u16 value)
1425 vmcs_writel(field, value);
1428 static void vmcs_write32(unsigned long field, u32 value)
1430 vmcs_writel(field, value);
1433 static void vmcs_write64(unsigned long field, u64 value)
1435 vmcs_writel(field, value);
1436 #ifndef CONFIG_X86_64
1438 vmcs_writel(field+1, value >> 32);
1442 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 vmcs_writel(field, vmcs_readl(field) & ~mask);
1447 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 vmcs_writel(field, vmcs_readl(field) | mask);
1452 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 vmcs_write32(VM_ENTRY_CONTROLS, val);
1455 vmx->vm_entry_controls_shadow = val;
1458 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 if (vmx->vm_entry_controls_shadow != val)
1461 vm_entry_controls_init(vmx, val);
1464 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 return vmx->vm_entry_controls_shadow;
1470 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1475 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1480 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 vmcs_write32(VM_EXIT_CONTROLS, val);
1483 vmx->vm_exit_controls_shadow = val;
1486 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 if (vmx->vm_exit_controls_shadow != val)
1489 vm_exit_controls_init(vmx, val);
1492 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 return vmx->vm_exit_controls_shadow;
1498 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1503 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1508 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 vmx->segment_cache.bitmask = 0;
1513 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1517 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1520 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1521 vmx->segment_cache.bitmask = 0;
1523 ret = vmx->segment_cache.bitmask & mask;
1524 vmx->segment_cache.bitmask |= mask;
1528 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 u16 *p = &vmx->segment_cache.seg[seg].selector;
1532 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1533 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1537 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 ulong *p = &vmx->segment_cache.seg[seg].base;
1541 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1542 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1546 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 u32 *p = &vmx->segment_cache.seg[seg].limit;
1550 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1551 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1555 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 u32 *p = &vmx->segment_cache.seg[seg].ar;
1559 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1560 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1564 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1568 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1569 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1570 if ((vcpu->guest_debug &
1571 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1573 eb |= 1u << BP_VECTOR;
1574 if (to_vmx(vcpu)->rmode.vm86_active)
1577 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1578 if (vcpu->fpu_active)
1579 eb &= ~(1u << NM_VECTOR);
1581 /* When we are running a nested L2 guest and L1 specified for it a
1582 * certain exception bitmap, we must trap the same exceptions and pass
1583 * them to L1. When running L2, we will only handle the exceptions
1584 * specified above if L1 did not want them.
1586 if (is_guest_mode(vcpu))
1587 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589 vmcs_write32(EXCEPTION_BITMAP, eb);
1592 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1593 unsigned long entry, unsigned long exit)
1595 vm_entry_controls_clearbit(vmx, entry);
1596 vm_exit_controls_clearbit(vmx, exit);
1599 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1602 struct msr_autoload *m = &vmx->msr_autoload;
1606 if (cpu_has_load_ia32_efer) {
1607 clear_atomic_switch_msr_special(vmx,
1608 VM_ENTRY_LOAD_IA32_EFER,
1609 VM_EXIT_LOAD_IA32_EFER);
1613 case MSR_CORE_PERF_GLOBAL_CTRL:
1614 if (cpu_has_load_perf_global_ctrl) {
1615 clear_atomic_switch_msr_special(vmx,
1616 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1617 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1623 for (i = 0; i < m->nr; ++i)
1624 if (m->guest[i].index == msr)
1630 m->guest[i] = m->guest[m->nr];
1631 m->host[i] = m->host[m->nr];
1632 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1633 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1636 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1637 unsigned long entry, unsigned long exit,
1638 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1639 u64 guest_val, u64 host_val)
1641 vmcs_write64(guest_val_vmcs, guest_val);
1642 vmcs_write64(host_val_vmcs, host_val);
1643 vm_entry_controls_setbit(vmx, entry);
1644 vm_exit_controls_setbit(vmx, exit);
1647 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1648 u64 guest_val, u64 host_val)
1651 struct msr_autoload *m = &vmx->msr_autoload;
1655 if (cpu_has_load_ia32_efer) {
1656 add_atomic_switch_msr_special(vmx,
1657 VM_ENTRY_LOAD_IA32_EFER,
1658 VM_EXIT_LOAD_IA32_EFER,
1661 guest_val, host_val);
1665 case MSR_CORE_PERF_GLOBAL_CTRL:
1666 if (cpu_has_load_perf_global_ctrl) {
1667 add_atomic_switch_msr_special(vmx,
1668 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1669 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 GUEST_IA32_PERF_GLOBAL_CTRL,
1671 HOST_IA32_PERF_GLOBAL_CTRL,
1672 guest_val, host_val);
1678 for (i = 0; i < m->nr; ++i)
1679 if (m->guest[i].index == msr)
1682 if (i == NR_AUTOLOAD_MSRS) {
1683 printk_once(KERN_WARNING "Not enough msr switch entries. "
1684 "Can't add msr %x\n", msr);
1686 } else if (i == m->nr) {
1688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1692 m->guest[i].index = msr;
1693 m->guest[i].value = guest_val;
1694 m->host[i].index = msr;
1695 m->host[i].value = host_val;
1698 static void reload_tss(void)
1701 * VT restores TR but not its size. Useless.
1703 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1704 struct desc_struct *descs;
1706 descs = (void *)gdt->address;
1707 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1711 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1716 guest_efer = vmx->vcpu.arch.efer;
1719 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1722 ignore_bits = EFER_NX | EFER_SCE;
1723 #ifdef CONFIG_X86_64
1724 ignore_bits |= EFER_LMA | EFER_LME;
1725 /* SCE is meaningful only in long mode on Intel */
1726 if (guest_efer & EFER_LMA)
1727 ignore_bits &= ~(u64)EFER_SCE;
1729 guest_efer &= ~ignore_bits;
1730 guest_efer |= host_efer & ignore_bits;
1731 vmx->guest_msrs[efer_offset].data = guest_efer;
1732 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734 clear_atomic_switch_msr(vmx, MSR_EFER);
1737 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1738 * On CPUs that support "load IA32_EFER", always switch EFER
1739 * atomically, since it's faster than switching it manually.
1741 if (cpu_has_load_ia32_efer ||
1742 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1743 guest_efer = vmx->vcpu.arch.efer;
1744 if (!(guest_efer & EFER_LMA))
1745 guest_efer &= ~EFER_LME;
1746 if (guest_efer != host_efer)
1747 add_atomic_switch_msr(vmx, MSR_EFER,
1748 guest_efer, host_efer);
1755 static unsigned long segment_base(u16 selector)
1757 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1758 struct desc_struct *d;
1759 unsigned long table_base;
1762 if (!(selector & ~3))
1765 table_base = gdt->address;
1767 if (selector & 4) { /* from ldt */
1768 u16 ldt_selector = kvm_read_ldt();
1770 if (!(ldt_selector & ~3))
1773 table_base = segment_base(ldt_selector);
1775 d = (struct desc_struct *)(table_base + (selector & ~7));
1776 v = get_desc_base(d);
1777 #ifdef CONFIG_X86_64
1778 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1779 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1784 static inline unsigned long kvm_read_tr_base(void)
1787 asm("str %0" : "=g"(tr));
1788 return segment_base(tr);
1791 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 struct vcpu_vmx *vmx = to_vmx(vcpu);
1796 if (vmx->host_state.loaded)
1799 vmx->host_state.loaded = 1;
1801 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1802 * allow segment selectors with cpl > 0 or ti == 1.
1804 vmx->host_state.ldt_sel = kvm_read_ldt();
1805 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1806 savesegment(fs, vmx->host_state.fs_sel);
1807 if (!(vmx->host_state.fs_sel & 7)) {
1808 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1809 vmx->host_state.fs_reload_needed = 0;
1811 vmcs_write16(HOST_FS_SELECTOR, 0);
1812 vmx->host_state.fs_reload_needed = 1;
1814 savesegment(gs, vmx->host_state.gs_sel);
1815 if (!(vmx->host_state.gs_sel & 7))
1816 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818 vmcs_write16(HOST_GS_SELECTOR, 0);
1819 vmx->host_state.gs_ldt_reload_needed = 1;
1822 #ifdef CONFIG_X86_64
1823 savesegment(ds, vmx->host_state.ds_sel);
1824 savesegment(es, vmx->host_state.es_sel);
1827 #ifdef CONFIG_X86_64
1828 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1829 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1832 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1835 #ifdef CONFIG_X86_64
1836 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1837 if (is_long_mode(&vmx->vcpu))
1838 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 if (boot_cpu_has(X86_FEATURE_MPX))
1841 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1842 for (i = 0; i < vmx->save_nmsrs; ++i)
1843 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1844 vmx->guest_msrs[i].data,
1845 vmx->guest_msrs[i].mask);
1848 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 if (!vmx->host_state.loaded)
1853 ++vmx->vcpu.stat.host_state_reload;
1854 vmx->host_state.loaded = 0;
1855 #ifdef CONFIG_X86_64
1856 if (is_long_mode(&vmx->vcpu))
1857 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 if (vmx->host_state.gs_ldt_reload_needed) {
1860 kvm_load_ldt(vmx->host_state.ldt_sel);
1861 #ifdef CONFIG_X86_64
1862 load_gs_index(vmx->host_state.gs_sel);
1864 loadsegment(gs, vmx->host_state.gs_sel);
1867 if (vmx->host_state.fs_reload_needed)
1868 loadsegment(fs, vmx->host_state.fs_sel);
1869 #ifdef CONFIG_X86_64
1870 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1871 loadsegment(ds, vmx->host_state.ds_sel);
1872 loadsegment(es, vmx->host_state.es_sel);
1876 #ifdef CONFIG_X86_64
1877 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 if (vmx->host_state.msr_host_bndcfgs)
1880 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882 * If the FPU is not active (through the host task or
1883 * the guest vcpu), then restore the cr0.TS bit.
1885 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1887 load_gdt(this_cpu_ptr(&host_gdt));
1890 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1893 __vmx_load_host_state(vmx);
1898 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1899 * vcpu mutex is already taken.
1901 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 struct vcpu_vmx *vmx = to_vmx(vcpu);
1904 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1907 kvm_cpu_vmxon(phys_addr);
1908 else if (vmx->loaded_vmcs->cpu != cpu)
1909 loaded_vmcs_clear(vmx->loaded_vmcs);
1911 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1912 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1913 vmcs_load(vmx->loaded_vmcs->vmcs);
1916 if (vmx->loaded_vmcs->cpu != cpu) {
1917 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1918 unsigned long sysenter_esp;
1920 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1921 local_irq_disable();
1922 crash_disable_local_vmclear(cpu);
1925 * Read loaded_vmcs->cpu should be before fetching
1926 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1927 * See the comments in __loaded_vmcs_clear().
1931 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1932 &per_cpu(loaded_vmcss_on_cpu, cpu));
1933 crash_enable_local_vmclear(cpu);
1937 * Linux uses per-cpu TSS and GDT, so set these when switching
1940 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1941 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1943 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1944 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1945 vmx->loaded_vmcs->cpu = cpu;
1949 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 __vmx_load_host_state(to_vmx(vcpu));
1952 if (!vmm_exclusive) {
1953 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1959 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1963 if (vcpu->fpu_active)
1965 vcpu->fpu_active = 1;
1966 cr0 = vmcs_readl(GUEST_CR0);
1967 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1968 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1969 vmcs_writel(GUEST_CR0, cr0);
1970 update_exception_bitmap(vcpu);
1971 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1972 if (is_guest_mode(vcpu))
1973 vcpu->arch.cr0_guest_owned_bits &=
1974 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1975 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1978 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1981 * Return the cr0 value that a nested guest would read. This is a combination
1982 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1983 * its hypervisor (cr0_read_shadow).
1985 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1988 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1993 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1996 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1999 * set this *before* calling this function.
2001 vmx_decache_cr0_guest_bits(vcpu);
2002 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2003 update_exception_bitmap(vcpu);
2004 vcpu->arch.cr0_guest_owned_bits = 0;
2005 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2006 if (is_guest_mode(vcpu)) {
2008 * L1's specified read shadow might not contain the TS bit,
2009 * so now that we turned on shadowing of this bit, we need to
2010 * set this bit of the shadow. Like in nested_vmx_run we need
2011 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2012 * up-to-date here because we just decached cr0.TS (and we'll
2013 * only update vmcs12->guest_cr0 on nested exit).
2015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2016 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2017 (vcpu->arch.cr0 & X86_CR0_TS);
2018 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2023 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 unsigned long rflags, save_rflags;
2027 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2028 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2029 rflags = vmcs_readl(GUEST_RFLAGS);
2030 if (to_vmx(vcpu)->rmode.vm86_active) {
2031 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2032 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2033 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035 to_vmx(vcpu)->rflags = rflags;
2037 return to_vmx(vcpu)->rflags;
2040 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2043 to_vmx(vcpu)->rflags = rflags;
2044 if (to_vmx(vcpu)->rmode.vm86_active) {
2045 to_vmx(vcpu)->rmode.save_rflags = rflags;
2046 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048 vmcs_writel(GUEST_RFLAGS, rflags);
2051 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2056 if (interruptibility & GUEST_INTR_STATE_STI)
2057 ret |= KVM_X86_SHADOW_INT_STI;
2058 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2059 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2064 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2067 u32 interruptibility = interruptibility_old;
2069 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2072 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2073 else if (mask & KVM_X86_SHADOW_INT_STI)
2074 interruptibility |= GUEST_INTR_STATE_STI;
2076 if ((interruptibility != interruptibility_old))
2077 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2080 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2084 rip = kvm_rip_read(vcpu);
2085 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2086 kvm_rip_write(vcpu, rip);
2088 /* skipping an emulated instruction also counts */
2089 vmx_set_interrupt_shadow(vcpu, 0);
2093 * KVM wants to inject page-faults which it got to the guest. This function
2094 * checks whether in a nested guest, we need to inject them to L1 or L2.
2096 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100 if (!(vmcs12->exception_bitmap & (1u << nr)))
2103 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2104 vmcs_read32(VM_EXIT_INTR_INFO),
2105 vmcs_readl(EXIT_QUALIFICATION));
2109 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2110 bool has_error_code, u32 error_code,
2113 struct vcpu_vmx *vmx = to_vmx(vcpu);
2114 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116 if (!reinject && is_guest_mode(vcpu) &&
2117 nested_vmx_check_exception(vcpu, nr))
2120 if (has_error_code) {
2121 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2122 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2125 if (vmx->rmode.vm86_active) {
2127 if (kvm_exception_is_soft(nr))
2128 inc_eip = vcpu->arch.event_exit_inst_len;
2129 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2130 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2134 if (kvm_exception_is_soft(nr)) {
2135 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2136 vmx->vcpu.arch.event_exit_inst_len);
2137 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2144 static bool vmx_rdtscp_supported(void)
2146 return cpu_has_vmx_rdtscp();
2149 static bool vmx_invpcid_supported(void)
2151 return cpu_has_vmx_invpcid() && enable_ept;
2155 * Swap MSR entry in host/guest MSR entry array.
2157 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 struct shared_msr_entry tmp;
2161 tmp = vmx->guest_msrs[to];
2162 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2163 vmx->guest_msrs[from] = tmp;
2166 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 unsigned long *msr_bitmap;
2170 if (is_guest_mode(vcpu))
2171 msr_bitmap = vmx_msr_bitmap_nested;
2172 else if (irqchip_in_kernel(vcpu->kvm) &&
2173 apic_x2apic_mode(vcpu->arch.apic)) {
2174 if (is_long_mode(vcpu))
2175 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179 if (is_long_mode(vcpu))
2180 msr_bitmap = vmx_msr_bitmap_longmode;
2182 msr_bitmap = vmx_msr_bitmap_legacy;
2185 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2189 * Set up the vmcs to automatically save and restore system
2190 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2191 * mode, as fiddling with msrs is very expensive.
2193 static void setup_msrs(struct vcpu_vmx *vmx)
2195 int save_nmsrs, index;
2198 #ifdef CONFIG_X86_64
2199 if (is_long_mode(&vmx->vcpu)) {
2200 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2202 move_msr_up(vmx, index, save_nmsrs++);
2203 index = __find_msr_index(vmx, MSR_LSTAR);
2205 move_msr_up(vmx, index, save_nmsrs++);
2206 index = __find_msr_index(vmx, MSR_CSTAR);
2208 move_msr_up(vmx, index, save_nmsrs++);
2209 index = __find_msr_index(vmx, MSR_TSC_AUX);
2210 if (index >= 0 && vmx->rdtscp_enabled)
2211 move_msr_up(vmx, index, save_nmsrs++);
2213 * MSR_STAR is only needed on long mode guests, and only
2214 * if efer.sce is enabled.
2216 index = __find_msr_index(vmx, MSR_STAR);
2217 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2218 move_msr_up(vmx, index, save_nmsrs++);
2221 index = __find_msr_index(vmx, MSR_EFER);
2222 if (index >= 0 && update_transition_efer(vmx, index))
2223 move_msr_up(vmx, index, save_nmsrs++);
2225 vmx->save_nmsrs = save_nmsrs;
2227 if (cpu_has_vmx_msr_bitmap())
2228 vmx_set_msr_bitmap(&vmx->vcpu);
2232 * reads and returns guest's timestamp counter "register"
2233 * guest_tsc = host_tsc + tsc_offset -- 21.3
2235 static u64 guest_read_tsc(void)
2237 u64 host_tsc, tsc_offset;
2240 tsc_offset = vmcs_read64(TSC_OFFSET);
2241 return host_tsc + tsc_offset;
2245 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2246 * counter, even if a nested guest (L2) is currently running.
2248 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2252 tsc_offset = is_guest_mode(vcpu) ?
2253 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2254 vmcs_read64(TSC_OFFSET);
2255 return host_tsc + tsc_offset;
2259 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2260 * software catchup for faster rates on slower CPUs.
2262 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2267 if (user_tsc_khz > tsc_khz) {
2268 vcpu->arch.tsc_catchup = 1;
2269 vcpu->arch.tsc_always_catchup = 1;
2271 WARN(1, "user requested TSC rate below hardware speed\n");
2274 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276 return vmcs_read64(TSC_OFFSET);
2280 * writes 'offset' into guest's timestamp counter offset register
2282 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2284 if (is_guest_mode(vcpu)) {
2286 * We're here if L1 chose not to trap WRMSR to TSC. According
2287 * to the spec, this should set L1's TSC; The offset that L1
2288 * set for L2 remains unchanged, and still needs to be added
2289 * to the newly set TSC to get L2's TSC.
2291 struct vmcs12 *vmcs12;
2292 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2293 /* recalculate vmcs02.TSC_OFFSET: */
2294 vmcs12 = get_vmcs12(vcpu);
2295 vmcs_write64(TSC_OFFSET, offset +
2296 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2297 vmcs12->tsc_offset : 0));
2299 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2300 vmcs_read64(TSC_OFFSET), offset);
2301 vmcs_write64(TSC_OFFSET, offset);
2305 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2307 u64 offset = vmcs_read64(TSC_OFFSET);
2309 vmcs_write64(TSC_OFFSET, offset + adjustment);
2310 if (is_guest_mode(vcpu)) {
2311 /* Even when running L2, the adjustment needs to apply to L1 */
2312 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2314 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2315 offset + adjustment);
2318 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320 return target_tsc - native_read_tsc();
2323 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2326 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2330 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2331 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2332 * all guests if the "nested" module option is off, and can also be disabled
2333 * for a single guest by disabling its VMX cpuid bit.
2335 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337 return nested && guest_cpuid_has_vmx(vcpu);
2341 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2342 * returned for the various VMX controls MSRs when nested VMX is enabled.
2343 * The same values should also be used to verify that vmcs12 control fields are
2344 * valid during nested entry from L1 to L2.
2345 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2346 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2347 * bit in the high half is on if the corresponding bit in the control field
2348 * may be on. See also vmx_control_verify().
2350 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2353 * Note that as a general rule, the high half of the MSRs (bits in
2354 * the control fields which may be 1) should be initialized by the
2355 * intersection of the underlying hardware's MSR (i.e., features which
2356 * can be supported) and the list of features we want to expose -
2357 * because they are known to be properly supported in our code.
2358 * Also, usually, the low half of the MSRs (bits which must be 1) can
2359 * be set to 0, meaning that L1 may turn off any of these bits. The
2360 * reason is that if one of these bits is necessary, it will appear
2361 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2362 * fields of vmcs01 and vmcs02, will turn these bits off - and
2363 * nested_vmx_exit_handled() will not pass related exits to L1.
2364 * These rules have exceptions below.
2367 /* pin-based controls */
2368 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2369 vmx->nested.nested_vmx_pinbased_ctls_low,
2370 vmx->nested.nested_vmx_pinbased_ctls_high);
2371 vmx->nested.nested_vmx_pinbased_ctls_low |=
2372 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2373 vmx->nested.nested_vmx_pinbased_ctls_high &=
2374 PIN_BASED_EXT_INTR_MASK |
2375 PIN_BASED_NMI_EXITING |
2376 PIN_BASED_VIRTUAL_NMIS;
2377 vmx->nested.nested_vmx_pinbased_ctls_high |=
2378 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2379 PIN_BASED_VMX_PREEMPTION_TIMER;
2380 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2381 vmx->nested.nested_vmx_pinbased_ctls_high |=
2382 PIN_BASED_POSTED_INTR;
2385 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2386 vmx->nested.nested_vmx_exit_ctls_low,
2387 vmx->nested.nested_vmx_exit_ctls_high);
2388 vmx->nested.nested_vmx_exit_ctls_low =
2389 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2391 vmx->nested.nested_vmx_exit_ctls_high &=
2392 #ifdef CONFIG_X86_64
2393 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2395 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2396 vmx->nested.nested_vmx_exit_ctls_high |=
2397 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2398 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2399 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401 if (vmx_mpx_supported())
2402 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2404 /* We support free control of debug control saving. */
2405 vmx->nested.nested_vmx_true_exit_ctls_low =
2406 vmx->nested.nested_vmx_exit_ctls_low &
2407 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409 /* entry controls */
2410 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2411 vmx->nested.nested_vmx_entry_ctls_low,
2412 vmx->nested.nested_vmx_entry_ctls_high);
2413 vmx->nested.nested_vmx_entry_ctls_low =
2414 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2415 vmx->nested.nested_vmx_entry_ctls_high &=
2416 #ifdef CONFIG_X86_64
2417 VM_ENTRY_IA32E_MODE |
2419 VM_ENTRY_LOAD_IA32_PAT;
2420 vmx->nested.nested_vmx_entry_ctls_high |=
2421 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2422 if (vmx_mpx_supported())
2423 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2425 /* We support free control of debug control loading. */
2426 vmx->nested.nested_vmx_true_entry_ctls_low =
2427 vmx->nested.nested_vmx_entry_ctls_low &
2428 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430 /* cpu-based controls */
2431 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2432 vmx->nested.nested_vmx_procbased_ctls_low,
2433 vmx->nested.nested_vmx_procbased_ctls_high);
2434 vmx->nested.nested_vmx_procbased_ctls_low =
2435 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2436 vmx->nested.nested_vmx_procbased_ctls_high &=
2437 CPU_BASED_VIRTUAL_INTR_PENDING |
2438 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2439 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2440 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2441 CPU_BASED_CR3_STORE_EXITING |
2442 #ifdef CONFIG_X86_64
2443 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2446 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2447 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2448 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2449 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451 * We can allow some features even when not supported by the
2452 * hardware. For example, L1 can specify an MSR bitmap - and we
2453 * can use it to avoid exits to L1 - even when L0 runs L2
2454 * without MSR bitmaps.
2456 vmx->nested.nested_vmx_procbased_ctls_high |=
2457 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2458 CPU_BASED_USE_MSR_BITMAPS;
2460 /* We support free control of CR3 access interception. */
2461 vmx->nested.nested_vmx_true_procbased_ctls_low =
2462 vmx->nested.nested_vmx_procbased_ctls_low &
2463 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465 /* secondary cpu-based controls */
2466 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2467 vmx->nested.nested_vmx_secondary_ctls_low,
2468 vmx->nested.nested_vmx_secondary_ctls_high);
2469 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2470 vmx->nested.nested_vmx_secondary_ctls_high &=
2471 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2472 SECONDARY_EXEC_RDTSCP |
2473 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2475 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2476 SECONDARY_EXEC_WBINVD_EXITING |
2477 SECONDARY_EXEC_XSAVES;
2480 /* nested EPT: emulate EPT also to L1 */
2481 vmx->nested.nested_vmx_secondary_ctls_high |=
2482 SECONDARY_EXEC_ENABLE_EPT;
2483 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2484 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2488 * For nested guests, we don't do anything specific
2489 * for single context invalidation. Hence, only advertise
2490 * support for global context invalidation.
2492 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2494 vmx->nested.nested_vmx_ept_caps = 0;
2496 if (enable_unrestricted_guest)
2497 vmx->nested.nested_vmx_secondary_ctls_high |=
2498 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500 /* miscellaneous data */
2501 rdmsr(MSR_IA32_VMX_MISC,
2502 vmx->nested.nested_vmx_misc_low,
2503 vmx->nested.nested_vmx_misc_high);
2504 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2505 vmx->nested.nested_vmx_misc_low |=
2506 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2507 VMX_MISC_ACTIVITY_HLT;
2508 vmx->nested.nested_vmx_misc_high = 0;
2511 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2514 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516 return ((control & high) | low) == control;
2519 static inline u64 vmx_control_msr(u32 low, u32 high)
2521 return low | ((u64)high << 32);
2524 /* Returns 0 on success, non-0 otherwise. */
2525 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527 struct vcpu_vmx *vmx = to_vmx(vcpu);
2529 switch (msr_index) {
2530 case MSR_IA32_VMX_BASIC:
2532 * This MSR reports some information about VMX support. We
2533 * should return information about the VMX we emulate for the
2534 * guest, and the VMCS structure we give it - not about the
2535 * VMX support of the underlying hardware.
2537 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2538 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2539 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2542 case MSR_IA32_VMX_PINBASED_CTLS:
2543 *pdata = vmx_control_msr(
2544 vmx->nested.nested_vmx_pinbased_ctls_low,
2545 vmx->nested.nested_vmx_pinbased_ctls_high);
2547 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2548 *pdata = vmx_control_msr(
2549 vmx->nested.nested_vmx_true_procbased_ctls_low,
2550 vmx->nested.nested_vmx_procbased_ctls_high);
2552 case MSR_IA32_VMX_PROCBASED_CTLS:
2553 *pdata = vmx_control_msr(
2554 vmx->nested.nested_vmx_procbased_ctls_low,
2555 vmx->nested.nested_vmx_procbased_ctls_high);
2557 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2558 *pdata = vmx_control_msr(
2559 vmx->nested.nested_vmx_true_exit_ctls_low,
2560 vmx->nested.nested_vmx_exit_ctls_high);
2562 case MSR_IA32_VMX_EXIT_CTLS:
2563 *pdata = vmx_control_msr(
2564 vmx->nested.nested_vmx_exit_ctls_low,
2565 vmx->nested.nested_vmx_exit_ctls_high);
2567 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2568 *pdata = vmx_control_msr(
2569 vmx->nested.nested_vmx_true_entry_ctls_low,
2570 vmx->nested.nested_vmx_entry_ctls_high);
2572 case MSR_IA32_VMX_ENTRY_CTLS:
2573 *pdata = vmx_control_msr(
2574 vmx->nested.nested_vmx_entry_ctls_low,
2575 vmx->nested.nested_vmx_entry_ctls_high);
2577 case MSR_IA32_VMX_MISC:
2578 *pdata = vmx_control_msr(
2579 vmx->nested.nested_vmx_misc_low,
2580 vmx->nested.nested_vmx_misc_high);
2583 * These MSRs specify bits which the guest must keep fixed (on or off)
2584 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2585 * We picked the standard core2 setting.
2587 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2588 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2589 case MSR_IA32_VMX_CR0_FIXED0:
2590 *pdata = VMXON_CR0_ALWAYSON;
2592 case MSR_IA32_VMX_CR0_FIXED1:
2595 case MSR_IA32_VMX_CR4_FIXED0:
2596 *pdata = VMXON_CR4_ALWAYSON;
2598 case MSR_IA32_VMX_CR4_FIXED1:
2601 case MSR_IA32_VMX_VMCS_ENUM:
2602 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2604 case MSR_IA32_VMX_PROCBASED_CTLS2:
2605 *pdata = vmx_control_msr(
2606 vmx->nested.nested_vmx_secondary_ctls_low,
2607 vmx->nested.nested_vmx_secondary_ctls_high);
2609 case MSR_IA32_VMX_EPT_VPID_CAP:
2610 /* Currently, no nested vpid support */
2611 *pdata = vmx->nested.nested_vmx_ept_caps;
2621 * Reads an msr value (of 'msr_index') into 'pdata'.
2622 * Returns 0 on success, non-0 otherwise.
2623 * Assumes vcpu_load() was already called.
2625 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2628 struct shared_msr_entry *msr;
2631 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2635 switch (msr_index) {
2636 #ifdef CONFIG_X86_64
2638 data = vmcs_readl(GUEST_FS_BASE);
2641 data = vmcs_readl(GUEST_GS_BASE);
2643 case MSR_KERNEL_GS_BASE:
2644 vmx_load_host_state(to_vmx(vcpu));
2645 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2649 return kvm_get_msr_common(vcpu, msr_index, pdata);
2651 data = guest_read_tsc();
2653 case MSR_IA32_SYSENTER_CS:
2654 data = vmcs_read32(GUEST_SYSENTER_CS);
2656 case MSR_IA32_SYSENTER_EIP:
2657 data = vmcs_readl(GUEST_SYSENTER_EIP);
2659 case MSR_IA32_SYSENTER_ESP:
2660 data = vmcs_readl(GUEST_SYSENTER_ESP);
2662 case MSR_IA32_BNDCFGS:
2663 if (!vmx_mpx_supported())
2665 data = vmcs_read64(GUEST_BNDCFGS);
2667 case MSR_IA32_FEATURE_CONTROL:
2668 if (!nested_vmx_allowed(vcpu))
2670 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2672 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2673 if (!nested_vmx_allowed(vcpu))
2675 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2677 if (!vmx_xsaves_supported())
2679 data = vcpu->arch.ia32_xss;
2682 if (!to_vmx(vcpu)->rdtscp_enabled)
2684 /* Otherwise falls through */
2686 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2691 return kvm_get_msr_common(vcpu, msr_index, pdata);
2698 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2701 * Writes msr value into into the appropriate "register".
2702 * Returns 0 on success, non-0 otherwise.
2703 * Assumes vcpu_load() was already called.
2705 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2707 struct vcpu_vmx *vmx = to_vmx(vcpu);
2708 struct shared_msr_entry *msr;
2710 u32 msr_index = msr_info->index;
2711 u64 data = msr_info->data;
2713 switch (msr_index) {
2715 ret = kvm_set_msr_common(vcpu, msr_info);
2717 #ifdef CONFIG_X86_64
2719 vmx_segment_cache_clear(vmx);
2720 vmcs_writel(GUEST_FS_BASE, data);
2723 vmx_segment_cache_clear(vmx);
2724 vmcs_writel(GUEST_GS_BASE, data);
2726 case MSR_KERNEL_GS_BASE:
2727 vmx_load_host_state(vmx);
2728 vmx->msr_guest_kernel_gs_base = data;
2731 case MSR_IA32_SYSENTER_CS:
2732 vmcs_write32(GUEST_SYSENTER_CS, data);
2734 case MSR_IA32_SYSENTER_EIP:
2735 vmcs_writel(GUEST_SYSENTER_EIP, data);
2737 case MSR_IA32_SYSENTER_ESP:
2738 vmcs_writel(GUEST_SYSENTER_ESP, data);
2740 case MSR_IA32_BNDCFGS:
2741 if (!vmx_mpx_supported())
2743 vmcs_write64(GUEST_BNDCFGS, data);
2746 kvm_write_tsc(vcpu, msr_info);
2748 case MSR_IA32_CR_PAT:
2749 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2750 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2752 vmcs_write64(GUEST_IA32_PAT, data);
2753 vcpu->arch.pat = data;
2756 ret = kvm_set_msr_common(vcpu, msr_info);
2758 case MSR_IA32_TSC_ADJUST:
2759 ret = kvm_set_msr_common(vcpu, msr_info);
2761 case MSR_IA32_FEATURE_CONTROL:
2762 if (!nested_vmx_allowed(vcpu) ||
2763 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2764 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2766 vmx->nested.msr_ia32_feature_control = data;
2767 if (msr_info->host_initiated && data == 0)
2768 vmx_leave_nested(vcpu);
2770 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2771 return 1; /* they are read-only */
2773 if (!vmx_xsaves_supported())
2776 * The only supported bit as of Skylake is bit 8, but
2777 * it is not supported on KVM.
2781 vcpu->arch.ia32_xss = data;
2782 if (vcpu->arch.ia32_xss != host_xss)
2783 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2784 vcpu->arch.ia32_xss, host_xss);
2786 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2789 if (!vmx->rdtscp_enabled)
2791 /* Check reserved bit, higher 32 bits should be zero */
2792 if ((data >> 32) != 0)
2794 /* Otherwise falls through */
2796 msr = find_msr_entry(vmx, msr_index);
2798 u64 old_msr_data = msr->data;
2800 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2802 ret = kvm_set_shared_msr(msr->index, msr->data,
2806 msr->data = old_msr_data;
2810 ret = kvm_set_msr_common(vcpu, msr_info);
2816 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2818 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2821 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2824 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2826 case VCPU_EXREG_PDPTR:
2828 ept_save_pdptrs(vcpu);
2835 static __init int cpu_has_kvm_support(void)
2837 return cpu_has_vmx();
2840 static __init int vmx_disabled_by_bios(void)
2844 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2845 if (msr & FEATURE_CONTROL_LOCKED) {
2846 /* launched w/ TXT and VMX disabled */
2847 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2850 /* launched w/o TXT and VMX only enabled w/ TXT */
2851 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2852 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2853 && !tboot_enabled()) {
2854 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2855 "activate TXT before enabling KVM\n");
2858 /* launched w/o TXT and VMX disabled */
2859 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2860 && !tboot_enabled())
2867 static void kvm_cpu_vmxon(u64 addr)
2869 asm volatile (ASM_VMX_VMXON_RAX
2870 : : "a"(&addr), "m"(addr)
2874 static int hardware_enable(void)
2876 int cpu = raw_smp_processor_id();
2877 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2880 if (cr4_read_shadow() & X86_CR4_VMXE)
2883 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2886 * Now we can enable the vmclear operation in kdump
2887 * since the loaded_vmcss_on_cpu list on this cpu
2888 * has been initialized.
2890 * Though the cpu is not in VMX operation now, there
2891 * is no problem to enable the vmclear operation
2892 * for the loaded_vmcss_on_cpu list is empty!
2894 crash_enable_local_vmclear(cpu);
2896 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2898 test_bits = FEATURE_CONTROL_LOCKED;
2899 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2900 if (tboot_enabled())
2901 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2903 if ((old & test_bits) != test_bits) {
2904 /* enable and lock */
2905 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2907 cr4_set_bits(X86_CR4_VMXE);
2909 if (vmm_exclusive) {
2910 kvm_cpu_vmxon(phys_addr);
2914 native_store_gdt(this_cpu_ptr(&host_gdt));
2919 static void vmclear_local_loaded_vmcss(void)
2921 int cpu = raw_smp_processor_id();
2922 struct loaded_vmcs *v, *n;
2924 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2925 loaded_vmcss_on_cpu_link)
2926 __loaded_vmcs_clear(v);
2930 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2933 static void kvm_cpu_vmxoff(void)
2935 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2938 static void hardware_disable(void)
2940 if (vmm_exclusive) {
2941 vmclear_local_loaded_vmcss();
2944 cr4_clear_bits(X86_CR4_VMXE);
2947 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2948 u32 msr, u32 *result)
2950 u32 vmx_msr_low, vmx_msr_high;
2951 u32 ctl = ctl_min | ctl_opt;
2953 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2955 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2956 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2958 /* Ensure minimum (required) set of control bits are supported. */
2966 static __init bool allow_1_setting(u32 msr, u32 ctl)
2968 u32 vmx_msr_low, vmx_msr_high;
2970 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2971 return vmx_msr_high & ctl;
2974 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2976 u32 vmx_msr_low, vmx_msr_high;
2977 u32 min, opt, min2, opt2;
2978 u32 _pin_based_exec_control = 0;
2979 u32 _cpu_based_exec_control = 0;
2980 u32 _cpu_based_2nd_exec_control = 0;
2981 u32 _vmexit_control = 0;
2982 u32 _vmentry_control = 0;
2984 min = CPU_BASED_HLT_EXITING |
2985 #ifdef CONFIG_X86_64
2986 CPU_BASED_CR8_LOAD_EXITING |
2987 CPU_BASED_CR8_STORE_EXITING |
2989 CPU_BASED_CR3_LOAD_EXITING |
2990 CPU_BASED_CR3_STORE_EXITING |
2991 CPU_BASED_USE_IO_BITMAPS |
2992 CPU_BASED_MOV_DR_EXITING |
2993 CPU_BASED_USE_TSC_OFFSETING |
2994 CPU_BASED_MWAIT_EXITING |
2995 CPU_BASED_MONITOR_EXITING |
2996 CPU_BASED_INVLPG_EXITING |
2997 CPU_BASED_RDPMC_EXITING;
2999 opt = CPU_BASED_TPR_SHADOW |
3000 CPU_BASED_USE_MSR_BITMAPS |
3001 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3002 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3003 &_cpu_based_exec_control) < 0)
3005 #ifdef CONFIG_X86_64
3006 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3007 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3008 ~CPU_BASED_CR8_STORE_EXITING;
3010 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3012 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3013 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3014 SECONDARY_EXEC_WBINVD_EXITING |
3015 SECONDARY_EXEC_ENABLE_VPID |
3016 SECONDARY_EXEC_ENABLE_EPT |
3017 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3018 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3019 SECONDARY_EXEC_RDTSCP |
3020 SECONDARY_EXEC_ENABLE_INVPCID |
3021 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3022 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3023 SECONDARY_EXEC_SHADOW_VMCS |
3024 SECONDARY_EXEC_XSAVES |
3025 SECONDARY_EXEC_ENABLE_PML;
3026 if (adjust_vmx_controls(min2, opt2,
3027 MSR_IA32_VMX_PROCBASED_CTLS2,
3028 &_cpu_based_2nd_exec_control) < 0)
3031 #ifndef CONFIG_X86_64
3032 if (!(_cpu_based_2nd_exec_control &
3033 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3034 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3037 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3038 _cpu_based_2nd_exec_control &= ~(
3039 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3040 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3041 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3043 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3044 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3046 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3047 CPU_BASED_CR3_STORE_EXITING |
3048 CPU_BASED_INVLPG_EXITING);
3049 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3050 vmx_capability.ept, vmx_capability.vpid);
3053 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3054 #ifdef CONFIG_X86_64
3055 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3057 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3058 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3059 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3060 &_vmexit_control) < 0)
3063 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3064 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3065 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3066 &_pin_based_exec_control) < 0)
3069 if (!(_cpu_based_2nd_exec_control &
3070 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3071 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3072 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3074 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3075 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3076 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3077 &_vmentry_control) < 0)
3080 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3082 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3083 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3086 #ifdef CONFIG_X86_64
3087 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3088 if (vmx_msr_high & (1u<<16))
3092 /* Require Write-Back (WB) memory type for VMCS accesses. */
3093 if (((vmx_msr_high >> 18) & 15) != 6)
3096 vmcs_conf->size = vmx_msr_high & 0x1fff;
3097 vmcs_conf->order = get_order(vmcs_config.size);
3098 vmcs_conf->revision_id = vmx_msr_low;
3100 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3101 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3102 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3103 vmcs_conf->vmexit_ctrl = _vmexit_control;
3104 vmcs_conf->vmentry_ctrl = _vmentry_control;
3106 cpu_has_load_ia32_efer =
3107 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108 VM_ENTRY_LOAD_IA32_EFER)
3109 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110 VM_EXIT_LOAD_IA32_EFER);
3112 cpu_has_load_perf_global_ctrl =
3113 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3114 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3115 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3116 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3119 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3120 * but due to arrata below it can't be used. Workaround is to use
3121 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3123 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3128 * BC86,AAY89,BD102 (model 44)
3132 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3133 switch (boot_cpu_data.x86_model) {
3139 cpu_has_load_perf_global_ctrl = false;
3140 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3141 "does not work properly. Using workaround\n");
3149 rdmsrl(MSR_IA32_XSS, host_xss);
3154 static struct vmcs *alloc_vmcs_cpu(int cpu)
3156 int node = cpu_to_node(cpu);
3160 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3163 vmcs = page_address(pages);
3164 memset(vmcs, 0, vmcs_config.size);
3165 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3169 static struct vmcs *alloc_vmcs(void)
3171 return alloc_vmcs_cpu(raw_smp_processor_id());
3174 static void free_vmcs(struct vmcs *vmcs)
3176 free_pages((unsigned long)vmcs, vmcs_config.order);
3180 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3182 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3184 if (!loaded_vmcs->vmcs)
3186 loaded_vmcs_clear(loaded_vmcs);
3187 free_vmcs(loaded_vmcs->vmcs);
3188 loaded_vmcs->vmcs = NULL;
3191 static void free_kvm_area(void)
3195 for_each_possible_cpu(cpu) {
3196 free_vmcs(per_cpu(vmxarea, cpu));
3197 per_cpu(vmxarea, cpu) = NULL;
3201 static void init_vmcs_shadow_fields(void)
3205 /* No checks for read only fields yet */
3207 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3208 switch (shadow_read_write_fields[i]) {
3210 if (!vmx_mpx_supported())
3218 shadow_read_write_fields[j] =
3219 shadow_read_write_fields[i];
3222 max_shadow_read_write_fields = j;
3224 /* shadowed fields guest access without vmexit */
3225 for (i = 0; i < max_shadow_read_write_fields; i++) {
3226 clear_bit(shadow_read_write_fields[i],
3227 vmx_vmwrite_bitmap);
3228 clear_bit(shadow_read_write_fields[i],
3231 for (i = 0; i < max_shadow_read_only_fields; i++)
3232 clear_bit(shadow_read_only_fields[i],
3236 static __init int alloc_kvm_area(void)
3240 for_each_possible_cpu(cpu) {
3243 vmcs = alloc_vmcs_cpu(cpu);
3249 per_cpu(vmxarea, cpu) = vmcs;
3254 static bool emulation_required(struct kvm_vcpu *vcpu)
3256 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3259 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3260 struct kvm_segment *save)
3262 if (!emulate_invalid_guest_state) {
3264 * CS and SS RPL should be equal during guest entry according
3265 * to VMX spec, but in reality it is not always so. Since vcpu
3266 * is in the middle of the transition from real mode to
3267 * protected mode it is safe to assume that RPL 0 is a good
3270 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3271 save->selector &= ~SEGMENT_RPL_MASK;
3272 save->dpl = save->selector & SEGMENT_RPL_MASK;
3275 vmx_set_segment(vcpu, save, seg);
3278 static void enter_pmode(struct kvm_vcpu *vcpu)
3280 unsigned long flags;
3281 struct vcpu_vmx *vmx = to_vmx(vcpu);
3284 * Update real mode segment cache. It may be not up-to-date if sement
3285 * register was written while vcpu was in a guest mode.
3287 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3289 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3290 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3291 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3292 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3294 vmx->rmode.vm86_active = 0;
3296 vmx_segment_cache_clear(vmx);
3298 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3300 flags = vmcs_readl(GUEST_RFLAGS);
3301 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3302 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3303 vmcs_writel(GUEST_RFLAGS, flags);
3305 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3306 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3308 update_exception_bitmap(vcpu);
3310 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3311 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3312 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3313 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3314 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3315 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3318 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3320 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3321 struct kvm_segment var = *save;
3324 if (seg == VCPU_SREG_CS)
3327 if (!emulate_invalid_guest_state) {
3328 var.selector = var.base >> 4;
3329 var.base = var.base & 0xffff0;
3339 if (save->base & 0xf)
3340 printk_once(KERN_WARNING "kvm: segment base is not "
3341 "paragraph aligned when entering "
3342 "protected mode (seg=%d)", seg);
3345 vmcs_write16(sf->selector, var.selector);
3346 vmcs_write32(sf->base, var.base);
3347 vmcs_write32(sf->limit, var.limit);
3348 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3351 static void enter_rmode(struct kvm_vcpu *vcpu)
3353 unsigned long flags;
3354 struct vcpu_vmx *vmx = to_vmx(vcpu);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3359 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3360 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3361 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3362 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3364 vmx->rmode.vm86_active = 1;
3367 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3368 * vcpu. Warn the user that an update is overdue.
3370 if (!vcpu->kvm->arch.tss_addr)
3371 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3372 "called before entering vcpu\n");
3374 vmx_segment_cache_clear(vmx);
3376 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3377 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3378 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3380 flags = vmcs_readl(GUEST_RFLAGS);
3381 vmx->rmode.save_rflags = flags;
3383 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3385 vmcs_writel(GUEST_RFLAGS, flags);
3386 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3387 update_exception_bitmap(vcpu);
3389 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3390 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3391 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3392 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3393 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3394 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3396 kvm_mmu_reset_context(vcpu);
3399 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3401 struct vcpu_vmx *vmx = to_vmx(vcpu);
3402 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3408 * Force kernel_gs_base reloading before EFER changes, as control
3409 * of this msr depends on is_long_mode().
3411 vmx_load_host_state(to_vmx(vcpu));
3412 vcpu->arch.efer = efer;
3413 if (efer & EFER_LMA) {
3414 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3417 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3419 msr->data = efer & ~EFER_LME;
3424 #ifdef CONFIG_X86_64
3426 static void enter_lmode(struct kvm_vcpu *vcpu)
3430 vmx_segment_cache_clear(to_vmx(vcpu));
3432 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3433 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3434 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3436 vmcs_write32(GUEST_TR_AR_BYTES,
3437 (guest_tr_ar & ~AR_TYPE_MASK)
3438 | AR_TYPE_BUSY_64_TSS);
3440 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3443 static void exit_lmode(struct kvm_vcpu *vcpu)
3445 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3446 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3451 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3453 vpid_sync_context(to_vmx(vcpu));
3455 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3457 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3461 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3463 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3465 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3466 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3469 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3471 if (enable_ept && is_paging(vcpu))
3472 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3473 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3476 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3478 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3480 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3481 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3484 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3486 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3488 if (!test_bit(VCPU_EXREG_PDPTR,
3489 (unsigned long *)&vcpu->arch.regs_dirty))
3492 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3493 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3494 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3495 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3496 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3500 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3502 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3504 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3505 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3506 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3507 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3508 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3511 __set_bit(VCPU_EXREG_PDPTR,
3512 (unsigned long *)&vcpu->arch.regs_avail);
3513 __set_bit(VCPU_EXREG_PDPTR,
3514 (unsigned long *)&vcpu->arch.regs_dirty);
3517 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3519 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3521 struct kvm_vcpu *vcpu)
3523 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3524 vmx_decache_cr3(vcpu);
3525 if (!(cr0 & X86_CR0_PG)) {
3526 /* From paging/starting to nonpaging */
3527 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3528 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3529 (CPU_BASED_CR3_LOAD_EXITING |
3530 CPU_BASED_CR3_STORE_EXITING));
3531 vcpu->arch.cr0 = cr0;
3532 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3533 } else if (!is_paging(vcpu)) {
3534 /* From nonpaging to paging */
3535 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3536 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3537 ~(CPU_BASED_CR3_LOAD_EXITING |
3538 CPU_BASED_CR3_STORE_EXITING));
3539 vcpu->arch.cr0 = cr0;
3540 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3543 if (!(cr0 & X86_CR0_WP))
3544 *hw_cr0 &= ~X86_CR0_WP;
3547 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3549 struct vcpu_vmx *vmx = to_vmx(vcpu);
3550 unsigned long hw_cr0;
3552 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3553 if (enable_unrestricted_guest)
3554 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3556 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3558 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3561 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3565 #ifdef CONFIG_X86_64
3566 if (vcpu->arch.efer & EFER_LME) {
3567 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3569 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3575 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3577 if (!vcpu->fpu_active)
3578 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3580 vmcs_writel(CR0_READ_SHADOW, cr0);
3581 vmcs_writel(GUEST_CR0, hw_cr0);
3582 vcpu->arch.cr0 = cr0;
3584 /* depends on vcpu->arch.cr0 to be set to a new value */
3585 vmx->emulation_required = emulation_required(vcpu);
3588 static u64 construct_eptp(unsigned long root_hpa)
3592 /* TODO write the value reading from MSR */
3593 eptp = VMX_EPT_DEFAULT_MT |
3594 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3595 if (enable_ept_ad_bits)
3596 eptp |= VMX_EPT_AD_ENABLE_BIT;
3597 eptp |= (root_hpa & PAGE_MASK);
3602 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3604 unsigned long guest_cr3;
3609 eptp = construct_eptp(cr3);
3610 vmcs_write64(EPT_POINTER, eptp);
3611 if (is_paging(vcpu) || is_guest_mode(vcpu))
3612 guest_cr3 = kvm_read_cr3(vcpu);
3614 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3615 ept_load_pdptrs(vcpu);
3618 vmx_flush_tlb(vcpu);
3619 vmcs_writel(GUEST_CR3, guest_cr3);
3622 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3625 * Pass through host's Machine Check Enable value to hw_cr4, which
3626 * is in force while we are in guest mode. Do not let guests control
3627 * this bit, even if host CR4.MCE == 0.
3629 unsigned long hw_cr4 =
3630 (cr4_read_shadow() & X86_CR4_MCE) |
3631 (cr4 & ~X86_CR4_MCE) |
3632 (to_vmx(vcpu)->rmode.vm86_active ?
3633 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3635 if (cr4 & X86_CR4_VMXE) {
3637 * To use VMXON (and later other VMX instructions), a guest
3638 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3639 * So basically the check on whether to allow nested VMX
3642 if (!nested_vmx_allowed(vcpu))
3645 if (to_vmx(vcpu)->nested.vmxon &&
3646 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3649 vcpu->arch.cr4 = cr4;
3651 if (!is_paging(vcpu)) {
3652 hw_cr4 &= ~X86_CR4_PAE;
3653 hw_cr4 |= X86_CR4_PSE;
3655 * SMEP/SMAP is disabled if CPU is in non-paging mode
3656 * in hardware. However KVM always uses paging mode to
3657 * emulate guest non-paging mode with TDP.
3658 * To emulate this behavior, SMEP/SMAP needs to be
3659 * manually disabled when guest switches to non-paging
3662 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3663 } else if (!(cr4 & X86_CR4_PAE)) {
3664 hw_cr4 &= ~X86_CR4_PAE;
3668 vmcs_writel(CR4_READ_SHADOW, cr4);
3669 vmcs_writel(GUEST_CR4, hw_cr4);
3673 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3674 struct kvm_segment *var, int seg)
3676 struct vcpu_vmx *vmx = to_vmx(vcpu);
3679 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3680 *var = vmx->rmode.segs[seg];
3681 if (seg == VCPU_SREG_TR
3682 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3684 var->base = vmx_read_guest_seg_base(vmx, seg);
3685 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3688 var->base = vmx_read_guest_seg_base(vmx, seg);
3689 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3690 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3691 ar = vmx_read_guest_seg_ar(vmx, seg);
3692 var->unusable = (ar >> 16) & 1;
3693 var->type = ar & 15;
3694 var->s = (ar >> 4) & 1;
3695 var->dpl = (ar >> 5) & 3;
3697 * Some userspaces do not preserve unusable property. Since usable
3698 * segment has to be present according to VMX spec we can use present
3699 * property to amend userspace bug by making unusable segment always
3700 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3701 * segment as unusable.
3703 var->present = !var->unusable;
3704 var->avl = (ar >> 12) & 1;
3705 var->l = (ar >> 13) & 1;
3706 var->db = (ar >> 14) & 1;
3707 var->g = (ar >> 15) & 1;
3710 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3712 struct kvm_segment s;
3714 if (to_vmx(vcpu)->rmode.vm86_active) {
3715 vmx_get_segment(vcpu, &s, seg);
3718 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3721 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3723 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725 if (unlikely(vmx->rmode.vm86_active))
3728 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3733 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3737 if (var->unusable || !var->present)
3740 ar = var->type & 15;
3741 ar |= (var->s & 1) << 4;
3742 ar |= (var->dpl & 3) << 5;
3743 ar |= (var->present & 1) << 7;
3744 ar |= (var->avl & 1) << 12;
3745 ar |= (var->l & 1) << 13;
3746 ar |= (var->db & 1) << 14;
3747 ar |= (var->g & 1) << 15;
3753 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3754 struct kvm_segment *var, int seg)
3756 struct vcpu_vmx *vmx = to_vmx(vcpu);
3757 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3759 vmx_segment_cache_clear(vmx);
3761 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3762 vmx->rmode.segs[seg] = *var;
3763 if (seg == VCPU_SREG_TR)
3764 vmcs_write16(sf->selector, var->selector);
3766 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3770 vmcs_writel(sf->base, var->base);
3771 vmcs_write32(sf->limit, var->limit);
3772 vmcs_write16(sf->selector, var->selector);
3775 * Fix the "Accessed" bit in AR field of segment registers for older
3777 * IA32 arch specifies that at the time of processor reset the
3778 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3779 * is setting it to 0 in the userland code. This causes invalid guest
3780 * state vmexit when "unrestricted guest" mode is turned on.
3781 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3782 * tree. Newer qemu binaries with that qemu fix would not need this
3785 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3786 var->type |= 0x1; /* Accessed */
3788 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3791 vmx->emulation_required = emulation_required(vcpu);
3794 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3796 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3798 *db = (ar >> 14) & 1;
3799 *l = (ar >> 13) & 1;
3802 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3804 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3805 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3808 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3810 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3811 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3814 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3816 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3817 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3820 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3822 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3823 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3826 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3828 struct kvm_segment var;
3831 vmx_get_segment(vcpu, &var, seg);
3833 if (seg == VCPU_SREG_CS)
3835 ar = vmx_segment_access_rights(&var);
3837 if (var.base != (var.selector << 4))
3839 if (var.limit != 0xffff)
3847 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3849 struct kvm_segment cs;
3850 unsigned int cs_rpl;
3852 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3853 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3857 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3861 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3862 if (cs.dpl > cs_rpl)
3865 if (cs.dpl != cs_rpl)
3871 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3875 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3877 struct kvm_segment ss;
3878 unsigned int ss_rpl;
3880 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3881 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3885 if (ss.type != 3 && ss.type != 7)
3889 if (ss.dpl != ss_rpl) /* DPL != RPL */
3897 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3899 struct kvm_segment var;
3902 vmx_get_segment(vcpu, &var, seg);
3903 rpl = var.selector & SEGMENT_RPL_MASK;
3911 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3912 if (var.dpl < rpl) /* DPL < RPL */
3916 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3922 static bool tr_valid(struct kvm_vcpu *vcpu)
3924 struct kvm_segment tr;
3926 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3930 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3932 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3940 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3942 struct kvm_segment ldtr;
3944 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3948 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
3958 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3960 struct kvm_segment cs, ss;
3962 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3963 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3965 return ((cs.selector & SEGMENT_RPL_MASK) ==
3966 (ss.selector & SEGMENT_RPL_MASK));
3970 * Check if guest state is valid. Returns true if valid, false if
3972 * We assume that registers are always usable
3974 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3976 if (enable_unrestricted_guest)
3979 /* real mode guest state checks */
3980 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3981 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3983 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3985 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3987 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3989 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3991 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3994 /* protected mode guest state checks */
3995 if (!cs_ss_rpl_check(vcpu))
3997 if (!code_segment_valid(vcpu))
3999 if (!stack_segment_valid(vcpu))
4001 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4003 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4005 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4007 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4009 if (!tr_valid(vcpu))
4011 if (!ldtr_valid(vcpu))
4015 * - Add checks on RIP
4016 * - Add checks on RFLAGS
4022 static int init_rmode_tss(struct kvm *kvm)
4028 idx = srcu_read_lock(&kvm->srcu);
4029 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4030 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4033 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4034 r = kvm_write_guest_page(kvm, fn++, &data,
4035 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4038 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4041 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4045 r = kvm_write_guest_page(kvm, fn, &data,
4046 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4049 srcu_read_unlock(&kvm->srcu, idx);
4053 static int init_rmode_identity_map(struct kvm *kvm)
4056 pfn_t identity_map_pfn;
4062 /* Protect kvm->arch.ept_identity_pagetable_done. */
4063 mutex_lock(&kvm->slots_lock);
4065 if (likely(kvm->arch.ept_identity_pagetable_done))
4068 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4070 r = alloc_identity_pagetable(kvm);
4074 idx = srcu_read_lock(&kvm->srcu);
4075 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4078 /* Set up identity-mapping pagetable for EPT in real mode */
4079 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4080 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4081 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4082 r = kvm_write_guest_page(kvm, identity_map_pfn,
4083 &tmp, i * sizeof(tmp), sizeof(tmp));
4087 kvm->arch.ept_identity_pagetable_done = true;
4090 srcu_read_unlock(&kvm->srcu, idx);
4093 mutex_unlock(&kvm->slots_lock);
4097 static void seg_setup(int seg)
4099 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4102 vmcs_write16(sf->selector, 0);
4103 vmcs_writel(sf->base, 0);
4104 vmcs_write32(sf->limit, 0xffff);
4106 if (seg == VCPU_SREG_CS)
4107 ar |= 0x08; /* code segment */
4109 vmcs_write32(sf->ar_bytes, ar);
4112 static int alloc_apic_access_page(struct kvm *kvm)
4115 struct kvm_userspace_memory_region kvm_userspace_mem;
4118 mutex_lock(&kvm->slots_lock);
4119 if (kvm->arch.apic_access_page_done)
4121 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4122 kvm_userspace_mem.flags = 0;
4123 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4124 kvm_userspace_mem.memory_size = PAGE_SIZE;
4125 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4129 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4130 if (is_error_page(page)) {
4136 * Do not pin the page in memory, so that memory hot-unplug
4137 * is able to migrate it.
4140 kvm->arch.apic_access_page_done = true;
4142 mutex_unlock(&kvm->slots_lock);
4146 static int alloc_identity_pagetable(struct kvm *kvm)
4148 /* Called with kvm->slots_lock held. */
4150 struct kvm_userspace_memory_region kvm_userspace_mem;
4153 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4155 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4156 kvm_userspace_mem.flags = 0;
4157 kvm_userspace_mem.guest_phys_addr =
4158 kvm->arch.ept_identity_map_addr;
4159 kvm_userspace_mem.memory_size = PAGE_SIZE;
4160 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4165 static void allocate_vpid(struct vcpu_vmx *vmx)
4172 spin_lock(&vmx_vpid_lock);
4173 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4174 if (vpid < VMX_NR_VPIDS) {
4176 __set_bit(vpid, vmx_vpid_bitmap);
4178 spin_unlock(&vmx_vpid_lock);
4181 static void free_vpid(struct vcpu_vmx *vmx)
4185 spin_lock(&vmx_vpid_lock);
4187 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4188 spin_unlock(&vmx_vpid_lock);
4191 #define MSR_TYPE_R 1
4192 #define MSR_TYPE_W 2
4193 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4196 int f = sizeof(unsigned long);
4198 if (!cpu_has_vmx_msr_bitmap())
4202 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4203 * have the write-low and read-high bitmap offsets the wrong way round.
4204 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4206 if (msr <= 0x1fff) {
4207 if (type & MSR_TYPE_R)
4209 __clear_bit(msr, msr_bitmap + 0x000 / f);
4211 if (type & MSR_TYPE_W)
4213 __clear_bit(msr, msr_bitmap + 0x800 / f);
4215 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4217 if (type & MSR_TYPE_R)
4219 __clear_bit(msr, msr_bitmap + 0x400 / f);
4221 if (type & MSR_TYPE_W)
4223 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4228 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4231 int f = sizeof(unsigned long);
4233 if (!cpu_has_vmx_msr_bitmap())
4237 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4238 * have the write-low and read-high bitmap offsets the wrong way round.
4239 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4241 if (msr <= 0x1fff) {
4242 if (type & MSR_TYPE_R)
4244 __set_bit(msr, msr_bitmap + 0x000 / f);
4246 if (type & MSR_TYPE_W)
4248 __set_bit(msr, msr_bitmap + 0x800 / f);
4250 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4252 if (type & MSR_TYPE_R)
4254 __set_bit(msr, msr_bitmap + 0x400 / f);
4256 if (type & MSR_TYPE_W)
4258 __set_bit(msr, msr_bitmap + 0xc00 / f);
4264 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4265 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4267 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4268 unsigned long *msr_bitmap_nested,
4271 int f = sizeof(unsigned long);
4273 if (!cpu_has_vmx_msr_bitmap()) {
4279 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4280 * have the write-low and read-high bitmap offsets the wrong way round.
4281 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4283 if (msr <= 0x1fff) {
4284 if (type & MSR_TYPE_R &&
4285 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4287 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4289 if (type & MSR_TYPE_W &&
4290 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4292 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4294 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4296 if (type & MSR_TYPE_R &&
4297 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4299 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4301 if (type & MSR_TYPE_W &&
4302 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4304 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4309 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4312 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4313 msr, MSR_TYPE_R | MSR_TYPE_W);
4314 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4315 msr, MSR_TYPE_R | MSR_TYPE_W);
4318 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4320 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4322 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4326 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4328 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4330 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4334 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4336 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4338 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4342 static int vmx_vm_has_apicv(struct kvm *kvm)
4344 return enable_apicv && irqchip_in_kernel(kvm);
4347 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4349 struct vcpu_vmx *vmx = to_vmx(vcpu);
4354 if (vmx->nested.pi_desc &&
4355 vmx->nested.pi_pending) {
4356 vmx->nested.pi_pending = false;
4357 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4360 max_irr = find_last_bit(
4361 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4366 vapic_page = kmap(vmx->nested.virtual_apic_page);
4371 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4372 kunmap(vmx->nested.virtual_apic_page);
4374 status = vmcs_read16(GUEST_INTR_STATUS);
4375 if ((u8)max_irr > ((u8)status & 0xff)) {
4377 status |= (u8)max_irr;
4378 vmcs_write16(GUEST_INTR_STATUS, status);
4384 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4387 if (vcpu->mode == IN_GUEST_MODE) {
4388 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4389 POSTED_INTR_VECTOR);
4396 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4399 struct vcpu_vmx *vmx = to_vmx(vcpu);
4401 if (is_guest_mode(vcpu) &&
4402 vector == vmx->nested.posted_intr_nv) {
4403 /* the PIR and ON have been set by L1. */
4404 kvm_vcpu_trigger_posted_interrupt(vcpu);
4406 * If a posted intr is not recognized by hardware,
4407 * we will accomplish it in the next vmentry.
4409 vmx->nested.pi_pending = true;
4410 kvm_make_request(KVM_REQ_EVENT, vcpu);
4416 * Send interrupt to vcpu via posted interrupt way.
4417 * 1. If target vcpu is running(non-root mode), send posted interrupt
4418 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4419 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4420 * interrupt from PIR in next vmentry.
4422 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4424 struct vcpu_vmx *vmx = to_vmx(vcpu);
4427 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4431 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4434 r = pi_test_and_set_on(&vmx->pi_desc);
4435 kvm_make_request(KVM_REQ_EVENT, vcpu);
4436 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4437 kvm_vcpu_kick(vcpu);
4440 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4442 struct vcpu_vmx *vmx = to_vmx(vcpu);
4444 if (!pi_test_and_clear_on(&vmx->pi_desc))
4447 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4450 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4456 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4457 * will not change in the lifetime of the guest.
4458 * Note that host-state that does change is set elsewhere. E.g., host-state
4459 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4461 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4468 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4469 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4471 /* Save the most likely value for this task's CR4 in the VMCS. */
4472 cr4 = cr4_read_shadow();
4473 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4474 vmx->host_state.vmcs_host_cr4 = cr4;
4476 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4477 #ifdef CONFIG_X86_64
4479 * Load null selectors, so we can avoid reloading them in
4480 * __vmx_load_host_state(), in case userspace uses the null selectors
4481 * too (the expected case).
4483 vmcs_write16(HOST_DS_SELECTOR, 0);
4484 vmcs_write16(HOST_ES_SELECTOR, 0);
4486 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4487 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4489 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4490 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4492 native_store_idt(&dt);
4493 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4494 vmx->host_idt_base = dt.address;
4496 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4498 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4499 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4500 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4501 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4503 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4504 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4505 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4509 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4511 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4513 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4514 if (is_guest_mode(&vmx->vcpu))
4515 vmx->vcpu.arch.cr4_guest_owned_bits &=
4516 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4517 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4520 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4522 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4524 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4525 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4526 return pin_based_exec_ctrl;
4529 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4531 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4533 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4534 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4536 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4537 exec_control &= ~CPU_BASED_TPR_SHADOW;
4538 #ifdef CONFIG_X86_64
4539 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4540 CPU_BASED_CR8_LOAD_EXITING;
4544 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4545 CPU_BASED_CR3_LOAD_EXITING |
4546 CPU_BASED_INVLPG_EXITING;
4547 return exec_control;
4550 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4552 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4553 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4554 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4556 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4558 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4559 enable_unrestricted_guest = 0;
4560 /* Enable INVPCID for non-ept guests may cause performance regression. */
4561 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4563 if (!enable_unrestricted_guest)
4564 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4566 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4567 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4568 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4569 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4570 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4571 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4573 We can NOT enable shadow_vmcs here because we don't have yet
4576 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4577 /* PML is enabled/disabled in creating/destorying vcpu */
4578 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4580 return exec_control;
4583 static void ept_set_mmio_spte_mask(void)
4586 * EPT Misconfigurations can be generated if the value of bits 2:0
4587 * of an EPT paging-structure entry is 110b (write/execute).
4588 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4591 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4594 #define VMX_XSS_EXIT_BITMAP 0
4596 * Sets up the vmcs for emulated real mode.
4598 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4600 #ifdef CONFIG_X86_64
4606 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4607 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4609 if (enable_shadow_vmcs) {
4610 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4611 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4613 if (cpu_has_vmx_msr_bitmap())
4614 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4616 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4619 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4621 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4623 if (cpu_has_secondary_exec_ctrls()) {
4624 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4625 vmx_secondary_exec_control(vmx));
4628 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4629 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4630 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4631 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4632 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4634 vmcs_write16(GUEST_INTR_STATUS, 0);
4636 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4637 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4641 vmcs_write32(PLE_GAP, ple_gap);
4642 vmx->ple_window = ple_window;
4643 vmx->ple_window_dirty = true;
4646 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4647 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4648 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4650 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4651 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4652 vmx_set_constant_host_state(vmx);
4653 #ifdef CONFIG_X86_64
4654 rdmsrl(MSR_FS_BASE, a);
4655 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4656 rdmsrl(MSR_GS_BASE, a);
4657 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4659 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4660 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4663 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4664 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4665 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4666 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4667 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4669 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4670 u32 msr_low, msr_high;
4672 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4673 host_pat = msr_low | ((u64) msr_high << 32);
4674 /* Write the default value follow host pat */
4675 vmcs_write64(GUEST_IA32_PAT, host_pat);
4676 /* Keep arch.pat sync with GUEST_IA32_PAT */
4677 vmx->vcpu.arch.pat = host_pat;
4680 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4681 u32 index = vmx_msr_index[i];
4682 u32 data_low, data_high;
4685 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4687 if (wrmsr_safe(index, data_low, data_high) < 0)
4689 vmx->guest_msrs[j].index = i;
4690 vmx->guest_msrs[j].data = 0;
4691 vmx->guest_msrs[j].mask = -1ull;
4696 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4698 /* 22.2.1, 20.8.1 */
4699 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4701 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4702 set_cr4_guest_host_mask(vmx);
4704 if (vmx_xsaves_supported())
4705 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4710 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4712 struct vcpu_vmx *vmx = to_vmx(vcpu);
4713 struct msr_data apic_base_msr;
4715 vmx->rmode.vm86_active = 0;
4717 vmx->soft_vnmi_blocked = 0;
4719 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4720 kvm_set_cr8(&vmx->vcpu, 0);
4721 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4722 if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
4723 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4724 apic_base_msr.host_initiated = true;
4725 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4727 vmx_segment_cache_clear(vmx);
4729 seg_setup(VCPU_SREG_CS);
4730 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4731 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4733 seg_setup(VCPU_SREG_DS);
4734 seg_setup(VCPU_SREG_ES);
4735 seg_setup(VCPU_SREG_FS);
4736 seg_setup(VCPU_SREG_GS);
4737 seg_setup(VCPU_SREG_SS);
4739 vmcs_write16(GUEST_TR_SELECTOR, 0);
4740 vmcs_writel(GUEST_TR_BASE, 0);
4741 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4742 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4744 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4745 vmcs_writel(GUEST_LDTR_BASE, 0);
4746 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4747 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4749 vmcs_write32(GUEST_SYSENTER_CS, 0);
4750 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4751 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4753 vmcs_writel(GUEST_RFLAGS, 0x02);
4754 kvm_rip_write(vcpu, 0xfff0);
4756 vmcs_writel(GUEST_GDTR_BASE, 0);
4757 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4759 vmcs_writel(GUEST_IDTR_BASE, 0);
4760 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4762 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4763 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4764 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4766 /* Special registers */
4767 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4771 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4773 if (cpu_has_vmx_tpr_shadow()) {
4774 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4775 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4776 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4777 __pa(vmx->vcpu.arch.apic->regs));
4778 vmcs_write32(TPR_THRESHOLD, 0);
4781 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4783 if (vmx_vm_has_apicv(vcpu->kvm))
4784 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4787 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4789 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4790 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4791 vmx_set_cr4(&vmx->vcpu, 0);
4792 vmx_set_efer(&vmx->vcpu, 0);
4793 vmx_fpu_activate(&vmx->vcpu);
4794 update_exception_bitmap(&vmx->vcpu);
4796 vpid_sync_context(vmx);
4800 * In nested virtualization, check if L1 asked to exit on external interrupts.
4801 * For most existing hypervisors, this will always return true.
4803 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4805 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4806 PIN_BASED_EXT_INTR_MASK;
4810 * In nested virtualization, check if L1 has set
4811 * VM_EXIT_ACK_INTR_ON_EXIT
4813 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4815 return get_vmcs12(vcpu)->vm_exit_controls &
4816 VM_EXIT_ACK_INTR_ON_EXIT;
4819 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4821 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4822 PIN_BASED_NMI_EXITING;
4825 static void enable_irq_window(struct kvm_vcpu *vcpu)
4827 u32 cpu_based_vm_exec_control;
4829 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4830 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4831 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4834 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4836 u32 cpu_based_vm_exec_control;
4838 if (!cpu_has_virtual_nmis() ||
4839 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4840 enable_irq_window(vcpu);
4844 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4845 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4846 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4849 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4851 struct vcpu_vmx *vmx = to_vmx(vcpu);
4853 int irq = vcpu->arch.interrupt.nr;
4855 trace_kvm_inj_virq(irq);
4857 ++vcpu->stat.irq_injections;
4858 if (vmx->rmode.vm86_active) {
4860 if (vcpu->arch.interrupt.soft)
4861 inc_eip = vcpu->arch.event_exit_inst_len;
4862 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4863 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4866 intr = irq | INTR_INFO_VALID_MASK;
4867 if (vcpu->arch.interrupt.soft) {
4868 intr |= INTR_TYPE_SOFT_INTR;
4869 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4870 vmx->vcpu.arch.event_exit_inst_len);
4872 intr |= INTR_TYPE_EXT_INTR;
4873 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4876 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4878 struct vcpu_vmx *vmx = to_vmx(vcpu);
4880 if (is_guest_mode(vcpu))
4883 if (!cpu_has_virtual_nmis()) {
4885 * Tracking the NMI-blocked state in software is built upon
4886 * finding the next open IRQ window. This, in turn, depends on
4887 * well-behaving guests: They have to keep IRQs disabled at
4888 * least as long as the NMI handler runs. Otherwise we may
4889 * cause NMI nesting, maybe breaking the guest. But as this is
4890 * highly unlikely, we can live with the residual risk.
4892 vmx->soft_vnmi_blocked = 1;
4893 vmx->vnmi_blocked_time = 0;
4896 ++vcpu->stat.nmi_injections;
4897 vmx->nmi_known_unmasked = false;
4898 if (vmx->rmode.vm86_active) {
4899 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4900 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4903 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4904 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4909 if (!cpu_has_virtual_nmis())
4910 return to_vmx(vcpu)->soft_vnmi_blocked;
4911 if (to_vmx(vcpu)->nmi_known_unmasked)
4913 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4916 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4918 struct vcpu_vmx *vmx = to_vmx(vcpu);
4920 if (!cpu_has_virtual_nmis()) {
4921 if (vmx->soft_vnmi_blocked != masked) {
4922 vmx->soft_vnmi_blocked = masked;
4923 vmx->vnmi_blocked_time = 0;
4926 vmx->nmi_known_unmasked = !masked;
4928 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4929 GUEST_INTR_STATE_NMI);
4931 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4932 GUEST_INTR_STATE_NMI);
4936 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4938 if (to_vmx(vcpu)->nested.nested_run_pending)
4941 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4944 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4945 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4946 | GUEST_INTR_STATE_NMI));
4949 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4951 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4952 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4953 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4954 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4957 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4960 struct kvm_userspace_memory_region tss_mem = {
4961 .slot = TSS_PRIVATE_MEMSLOT,
4962 .guest_phys_addr = addr,
4963 .memory_size = PAGE_SIZE * 3,
4967 ret = kvm_set_memory_region(kvm, &tss_mem);
4970 kvm->arch.tss_addr = addr;
4971 return init_rmode_tss(kvm);
4974 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4979 * Update instruction length as we may reinject the exception
4980 * from user space while in guest debugging mode.
4982 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4983 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4984 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4988 if (vcpu->guest_debug &
4989 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5006 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5007 int vec, u32 err_code)
5010 * Instruction with address size override prefix opcode 0x67
5011 * Cause the #SS fault with 0 error code in VM86 mode.
5013 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5014 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5015 if (vcpu->arch.halt_request) {
5016 vcpu->arch.halt_request = 0;
5017 return kvm_vcpu_halt(vcpu);
5025 * Forward all other exceptions that are valid in real mode.
5026 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5027 * the required debugging infrastructure rework.
5029 kvm_queue_exception(vcpu, vec);
5034 * Trigger machine check on the host. We assume all the MSRs are already set up
5035 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5036 * We pass a fake environment to the machine check handler because we want
5037 * the guest to be always treated like user space, no matter what context
5038 * it used internally.
5040 static void kvm_machine_check(void)
5042 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5043 struct pt_regs regs = {
5044 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5045 .flags = X86_EFLAGS_IF,
5048 do_machine_check(®s, 0);
5052 static int handle_machine_check(struct kvm_vcpu *vcpu)
5054 /* already handled by vcpu_run */
5058 static int handle_exception(struct kvm_vcpu *vcpu)
5060 struct vcpu_vmx *vmx = to_vmx(vcpu);
5061 struct kvm_run *kvm_run = vcpu->run;
5062 u32 intr_info, ex_no, error_code;
5063 unsigned long cr2, rip, dr6;
5065 enum emulation_result er;
5067 vect_info = vmx->idt_vectoring_info;
5068 intr_info = vmx->exit_intr_info;
5070 if (is_machine_check(intr_info))
5071 return handle_machine_check(vcpu);
5073 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5074 return 1; /* already handled by vmx_vcpu_run() */
5076 if (is_no_device(intr_info)) {
5077 vmx_fpu_activate(vcpu);
5081 if (is_invalid_opcode(intr_info)) {
5082 if (is_guest_mode(vcpu)) {
5083 kvm_queue_exception(vcpu, UD_VECTOR);
5086 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5087 if (er != EMULATE_DONE)
5088 kvm_queue_exception(vcpu, UD_VECTOR);
5093 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5094 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5097 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5098 * MMIO, it is better to report an internal error.
5099 * See the comments in vmx_handle_exit.
5101 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5102 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5103 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5104 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5105 vcpu->run->internal.ndata = 3;
5106 vcpu->run->internal.data[0] = vect_info;
5107 vcpu->run->internal.data[1] = intr_info;
5108 vcpu->run->internal.data[2] = error_code;
5112 if (is_page_fault(intr_info)) {
5113 /* EPT won't cause page fault directly */
5115 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5116 trace_kvm_page_fault(cr2, error_code);
5118 if (kvm_event_needs_reinjection(vcpu))
5119 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5120 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5123 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5125 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5126 return handle_rmode_exception(vcpu, ex_no, error_code);
5130 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5131 if (!(vcpu->guest_debug &
5132 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5133 vcpu->arch.dr6 &= ~15;
5134 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5135 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5136 skip_emulated_instruction(vcpu);
5138 kvm_queue_exception(vcpu, DB_VECTOR);
5141 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5142 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5146 * Update instruction length as we may reinject #BP from
5147 * user space while in guest debugging mode. Reading it for
5148 * #DB as well causes no harm, it is not used in that case.
5150 vmx->vcpu.arch.event_exit_inst_len =
5151 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5152 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5153 rip = kvm_rip_read(vcpu);
5154 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5155 kvm_run->debug.arch.exception = ex_no;
5158 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5159 kvm_run->ex.exception = ex_no;
5160 kvm_run->ex.error_code = error_code;
5166 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5168 ++vcpu->stat.irq_exits;
5172 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5174 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5178 static int handle_io(struct kvm_vcpu *vcpu)
5180 unsigned long exit_qualification;
5181 int size, in, string;
5184 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5185 string = (exit_qualification & 16) != 0;
5186 in = (exit_qualification & 8) != 0;
5188 ++vcpu->stat.io_exits;
5191 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5193 port = exit_qualification >> 16;
5194 size = (exit_qualification & 7) + 1;
5195 skip_emulated_instruction(vcpu);
5197 return kvm_fast_pio_out(vcpu, size, port);
5201 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5204 * Patch in the VMCALL instruction:
5206 hypercall[0] = 0x0f;
5207 hypercall[1] = 0x01;
5208 hypercall[2] = 0xc1;
5211 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5213 unsigned long always_on = VMXON_CR0_ALWAYSON;
5214 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5216 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5217 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5218 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5219 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5220 return (val & always_on) == always_on;
5223 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5224 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5226 if (is_guest_mode(vcpu)) {
5227 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5228 unsigned long orig_val = val;
5231 * We get here when L2 changed cr0 in a way that did not change
5232 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5233 * but did change L0 shadowed bits. So we first calculate the
5234 * effective cr0 value that L1 would like to write into the
5235 * hardware. It consists of the L2-owned bits from the new
5236 * value combined with the L1-owned bits from L1's guest_cr0.
5238 val = (val & ~vmcs12->cr0_guest_host_mask) |
5239 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5241 if (!nested_cr0_valid(vcpu, val))
5244 if (kvm_set_cr0(vcpu, val))
5246 vmcs_writel(CR0_READ_SHADOW, orig_val);
5249 if (to_vmx(vcpu)->nested.vmxon &&
5250 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5252 return kvm_set_cr0(vcpu, val);
5256 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5258 if (is_guest_mode(vcpu)) {
5259 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5260 unsigned long orig_val = val;
5262 /* analogously to handle_set_cr0 */
5263 val = (val & ~vmcs12->cr4_guest_host_mask) |
5264 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5265 if (kvm_set_cr4(vcpu, val))
5267 vmcs_writel(CR4_READ_SHADOW, orig_val);
5270 return kvm_set_cr4(vcpu, val);
5273 /* called to set cr0 as approriate for clts instruction exit. */
5274 static void handle_clts(struct kvm_vcpu *vcpu)
5276 if (is_guest_mode(vcpu)) {
5278 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5279 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5280 * just pretend it's off (also in arch.cr0 for fpu_activate).
5282 vmcs_writel(CR0_READ_SHADOW,
5283 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5284 vcpu->arch.cr0 &= ~X86_CR0_TS;
5286 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5289 static int handle_cr(struct kvm_vcpu *vcpu)
5291 unsigned long exit_qualification, val;
5296 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5297 cr = exit_qualification & 15;
5298 reg = (exit_qualification >> 8) & 15;
5299 switch ((exit_qualification >> 4) & 3) {
5300 case 0: /* mov to cr */
5301 val = kvm_register_readl(vcpu, reg);
5302 trace_kvm_cr_write(cr, val);
5305 err = handle_set_cr0(vcpu, val);
5306 kvm_complete_insn_gp(vcpu, err);
5309 err = kvm_set_cr3(vcpu, val);
5310 kvm_complete_insn_gp(vcpu, err);
5313 err = handle_set_cr4(vcpu, val);
5314 kvm_complete_insn_gp(vcpu, err);
5317 u8 cr8_prev = kvm_get_cr8(vcpu);
5319 err = kvm_set_cr8(vcpu, cr8);
5320 kvm_complete_insn_gp(vcpu, err);
5321 if (irqchip_in_kernel(vcpu->kvm))
5323 if (cr8_prev <= cr8)
5325 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5332 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5333 skip_emulated_instruction(vcpu);
5334 vmx_fpu_activate(vcpu);
5336 case 1: /*mov from cr*/
5339 val = kvm_read_cr3(vcpu);
5340 kvm_register_write(vcpu, reg, val);
5341 trace_kvm_cr_read(cr, val);
5342 skip_emulated_instruction(vcpu);
5345 val = kvm_get_cr8(vcpu);
5346 kvm_register_write(vcpu, reg, val);
5347 trace_kvm_cr_read(cr, val);
5348 skip_emulated_instruction(vcpu);
5353 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5354 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5355 kvm_lmsw(vcpu, val);
5357 skip_emulated_instruction(vcpu);
5362 vcpu->run->exit_reason = 0;
5363 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5364 (int)(exit_qualification >> 4) & 3, cr);
5368 static int handle_dr(struct kvm_vcpu *vcpu)
5370 unsigned long exit_qualification;
5373 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5374 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5376 /* First, if DR does not exist, trigger UD */
5377 if (!kvm_require_dr(vcpu, dr))
5380 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5381 if (!kvm_require_cpl(vcpu, 0))
5383 dr7 = vmcs_readl(GUEST_DR7);
5386 * As the vm-exit takes precedence over the debug trap, we
5387 * need to emulate the latter, either for the host or the
5388 * guest debugging itself.
5390 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5391 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5392 vcpu->run->debug.arch.dr7 = dr7;
5393 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5394 vcpu->run->debug.arch.exception = DB_VECTOR;
5395 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5398 vcpu->arch.dr6 &= ~15;
5399 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5400 kvm_queue_exception(vcpu, DB_VECTOR);
5405 if (vcpu->guest_debug == 0) {
5406 u32 cpu_based_vm_exec_control;
5408 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5409 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5410 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5413 * No more DR vmexits; force a reload of the debug registers
5414 * and reenter on this instruction. The next vmexit will
5415 * retrieve the full state of the debug registers.
5417 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5421 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5422 if (exit_qualification & TYPE_MOV_FROM_DR) {
5425 if (kvm_get_dr(vcpu, dr, &val))
5427 kvm_register_write(vcpu, reg, val);
5429 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5432 skip_emulated_instruction(vcpu);
5436 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5438 return vcpu->arch.dr6;
5441 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5445 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5447 u32 cpu_based_vm_exec_control;
5449 get_debugreg(vcpu->arch.db[0], 0);
5450 get_debugreg(vcpu->arch.db[1], 1);
5451 get_debugreg(vcpu->arch.db[2], 2);
5452 get_debugreg(vcpu->arch.db[3], 3);
5453 get_debugreg(vcpu->arch.dr6, 6);
5454 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5456 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5458 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5459 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5463 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5465 vmcs_writel(GUEST_DR7, val);
5468 static int handle_cpuid(struct kvm_vcpu *vcpu)
5470 kvm_emulate_cpuid(vcpu);
5474 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5476 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5479 if (vmx_get_msr(vcpu, ecx, &data)) {
5480 trace_kvm_msr_read_ex(ecx);
5481 kvm_inject_gp(vcpu, 0);
5485 trace_kvm_msr_read(ecx, data);
5487 /* FIXME: handling of bits 32:63 of rax, rdx */
5488 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5489 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5490 skip_emulated_instruction(vcpu);
5494 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5496 struct msr_data msr;
5497 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5498 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5499 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5503 msr.host_initiated = false;
5504 if (kvm_set_msr(vcpu, &msr) != 0) {
5505 trace_kvm_msr_write_ex(ecx, data);
5506 kvm_inject_gp(vcpu, 0);
5510 trace_kvm_msr_write(ecx, data);
5511 skip_emulated_instruction(vcpu);
5515 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5517 kvm_make_request(KVM_REQ_EVENT, vcpu);
5521 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5523 u32 cpu_based_vm_exec_control;
5525 /* clear pending irq */
5526 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5527 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5530 kvm_make_request(KVM_REQ_EVENT, vcpu);
5532 ++vcpu->stat.irq_window_exits;
5535 * If the user space waits to inject interrupts, exit as soon as
5538 if (!irqchip_in_kernel(vcpu->kvm) &&
5539 vcpu->run->request_interrupt_window &&
5540 !kvm_cpu_has_interrupt(vcpu)) {
5541 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5547 static int handle_halt(struct kvm_vcpu *vcpu)
5549 return kvm_emulate_halt(vcpu);
5552 static int handle_vmcall(struct kvm_vcpu *vcpu)
5554 kvm_emulate_hypercall(vcpu);
5558 static int handle_invd(struct kvm_vcpu *vcpu)
5560 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5563 static int handle_invlpg(struct kvm_vcpu *vcpu)
5565 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5567 kvm_mmu_invlpg(vcpu, exit_qualification);
5568 skip_emulated_instruction(vcpu);
5572 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5576 err = kvm_rdpmc(vcpu);
5577 kvm_complete_insn_gp(vcpu, err);
5582 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5584 kvm_emulate_wbinvd(vcpu);
5588 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5590 u64 new_bv = kvm_read_edx_eax(vcpu);
5591 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5593 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5594 skip_emulated_instruction(vcpu);
5598 static int handle_xsaves(struct kvm_vcpu *vcpu)
5600 skip_emulated_instruction(vcpu);
5601 WARN(1, "this should never happen\n");
5605 static int handle_xrstors(struct kvm_vcpu *vcpu)
5607 skip_emulated_instruction(vcpu);
5608 WARN(1, "this should never happen\n");
5612 static int handle_apic_access(struct kvm_vcpu *vcpu)
5614 if (likely(fasteoi)) {
5615 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5616 int access_type, offset;
5618 access_type = exit_qualification & APIC_ACCESS_TYPE;
5619 offset = exit_qualification & APIC_ACCESS_OFFSET;
5621 * Sane guest uses MOV to write EOI, with written value
5622 * not cared. So make a short-circuit here by avoiding
5623 * heavy instruction emulation.
5625 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5626 (offset == APIC_EOI)) {
5627 kvm_lapic_set_eoi(vcpu);
5628 skip_emulated_instruction(vcpu);
5632 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5635 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5637 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5638 int vector = exit_qualification & 0xff;
5640 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5641 kvm_apic_set_eoi_accelerated(vcpu, vector);
5645 static int handle_apic_write(struct kvm_vcpu *vcpu)
5647 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5648 u32 offset = exit_qualification & 0xfff;
5650 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5651 kvm_apic_write_nodecode(vcpu, offset);
5655 static int handle_task_switch(struct kvm_vcpu *vcpu)
5657 struct vcpu_vmx *vmx = to_vmx(vcpu);
5658 unsigned long exit_qualification;
5659 bool has_error_code = false;
5662 int reason, type, idt_v, idt_index;
5664 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5665 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5666 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5668 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5670 reason = (u32)exit_qualification >> 30;
5671 if (reason == TASK_SWITCH_GATE && idt_v) {
5673 case INTR_TYPE_NMI_INTR:
5674 vcpu->arch.nmi_injected = false;
5675 vmx_set_nmi_mask(vcpu, true);
5677 case INTR_TYPE_EXT_INTR:
5678 case INTR_TYPE_SOFT_INTR:
5679 kvm_clear_interrupt_queue(vcpu);
5681 case INTR_TYPE_HARD_EXCEPTION:
5682 if (vmx->idt_vectoring_info &
5683 VECTORING_INFO_DELIVER_CODE_MASK) {
5684 has_error_code = true;
5686 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5689 case INTR_TYPE_SOFT_EXCEPTION:
5690 kvm_clear_exception_queue(vcpu);
5696 tss_selector = exit_qualification;
5698 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5699 type != INTR_TYPE_EXT_INTR &&
5700 type != INTR_TYPE_NMI_INTR))
5701 skip_emulated_instruction(vcpu);
5703 if (kvm_task_switch(vcpu, tss_selector,
5704 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5705 has_error_code, error_code) == EMULATE_FAIL) {
5706 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5707 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5708 vcpu->run->internal.ndata = 0;
5712 /* clear all local breakpoint enable flags */
5713 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5716 * TODO: What about debug traps on tss switch?
5717 * Are we supposed to inject them and update dr6?
5723 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5725 unsigned long exit_qualification;
5730 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5732 gla_validity = (exit_qualification >> 7) & 0x3;
5733 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5734 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5735 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5736 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5737 vmcs_readl(GUEST_LINEAR_ADDRESS));
5738 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5739 (long unsigned int)exit_qualification);
5740 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5741 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5746 * EPT violation happened while executing iret from NMI,
5747 * "blocked by NMI" bit has to be set before next VM entry.
5748 * There are errata that may cause this bit to not be set:
5751 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5752 cpu_has_virtual_nmis() &&
5753 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5754 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5756 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5757 trace_kvm_page_fault(gpa, exit_qualification);
5759 /* It is a write fault? */
5760 error_code = exit_qualification & PFERR_WRITE_MASK;
5761 /* It is a fetch fault? */
5762 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5763 /* ept page table is present? */
5764 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5766 vcpu->arch.exit_qualification = exit_qualification;
5768 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5771 static u64 ept_rsvd_mask(u64 spte, int level)
5776 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5777 mask |= (1ULL << i);
5780 /* bits 7:3 reserved */
5782 else if (spte & (1ULL << 7))
5784 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5785 * level == 1 if the hypervisor is using the ignored bit 7.
5787 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5789 /* bits 6:3 reserved */
5795 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5798 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5800 /* 010b (write-only) */
5801 WARN_ON((spte & 0x7) == 0x2);
5803 /* 110b (write/execute) */
5804 WARN_ON((spte & 0x7) == 0x6);
5806 /* 100b (execute-only) and value not supported by logical processor */
5807 if (!cpu_has_vmx_ept_execute_only())
5808 WARN_ON((spte & 0x7) == 0x4);
5812 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5814 if (rsvd_bits != 0) {
5815 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5816 __func__, rsvd_bits);
5820 /* bits 5:3 are _not_ reserved for large page or leaf page */
5821 if ((rsvd_bits & 0x38) == 0) {
5822 u64 ept_mem_type = (spte & 0x38) >> 3;
5824 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5825 ept_mem_type == 7) {
5826 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5827 __func__, ept_mem_type);
5834 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5837 int nr_sptes, i, ret;
5840 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5841 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5842 skip_emulated_instruction(vcpu);
5846 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5847 if (likely(ret == RET_MMIO_PF_EMULATE))
5848 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5851 if (unlikely(ret == RET_MMIO_PF_INVALID))
5852 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5854 if (unlikely(ret == RET_MMIO_PF_RETRY))
5857 /* It is the real ept misconfig */
5858 printk(KERN_ERR "EPT: Misconfiguration.\n");
5859 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5861 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5863 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5864 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5866 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5867 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5872 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5874 u32 cpu_based_vm_exec_control;
5876 /* clear pending NMI */
5877 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5878 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5879 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5880 ++vcpu->stat.nmi_window_exits;
5881 kvm_make_request(KVM_REQ_EVENT, vcpu);
5886 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5888 struct vcpu_vmx *vmx = to_vmx(vcpu);
5889 enum emulation_result err = EMULATE_DONE;
5892 bool intr_window_requested;
5893 unsigned count = 130;
5895 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5896 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5898 while (vmx->emulation_required && count-- != 0) {
5899 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5900 return handle_interrupt_window(&vmx->vcpu);
5902 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5905 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5907 if (err == EMULATE_USER_EXIT) {
5908 ++vcpu->stat.mmio_exits;
5913 if (err != EMULATE_DONE) {
5914 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5915 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5916 vcpu->run->internal.ndata = 0;
5920 if (vcpu->arch.halt_request) {
5921 vcpu->arch.halt_request = 0;
5922 ret = kvm_vcpu_halt(vcpu);
5926 if (signal_pending(current))
5936 static int __grow_ple_window(int val)
5938 if (ple_window_grow < 1)
5941 val = min(val, ple_window_actual_max);
5943 if (ple_window_grow < ple_window)
5944 val *= ple_window_grow;
5946 val += ple_window_grow;
5951 static int __shrink_ple_window(int val, int modifier, int minimum)
5956 if (modifier < ple_window)
5961 return max(val, minimum);
5964 static void grow_ple_window(struct kvm_vcpu *vcpu)
5966 struct vcpu_vmx *vmx = to_vmx(vcpu);
5967 int old = vmx->ple_window;
5969 vmx->ple_window = __grow_ple_window(old);
5971 if (vmx->ple_window != old)
5972 vmx->ple_window_dirty = true;
5974 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5977 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5979 struct vcpu_vmx *vmx = to_vmx(vcpu);
5980 int old = vmx->ple_window;
5982 vmx->ple_window = __shrink_ple_window(old,
5983 ple_window_shrink, ple_window);
5985 if (vmx->ple_window != old)
5986 vmx->ple_window_dirty = true;
5988 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5992 * ple_window_actual_max is computed to be one grow_ple_window() below
5993 * ple_window_max. (See __grow_ple_window for the reason.)
5994 * This prevents overflows, because ple_window_max is int.
5995 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5997 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5999 static void update_ple_window_actual_max(void)
6001 ple_window_actual_max =
6002 __shrink_ple_window(max(ple_window_max, ple_window),
6003 ple_window_grow, INT_MIN);
6006 static __init int hardware_setup(void)
6008 int r = -ENOMEM, i, msr;
6010 rdmsrl_safe(MSR_EFER, &host_efer);
6012 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6013 kvm_define_shared_msr(i, vmx_msr_index[i]);
6015 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6016 if (!vmx_io_bitmap_a)
6019 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6020 if (!vmx_io_bitmap_b)
6023 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6024 if (!vmx_msr_bitmap_legacy)
6027 vmx_msr_bitmap_legacy_x2apic =
6028 (unsigned long *)__get_free_page(GFP_KERNEL);
6029 if (!vmx_msr_bitmap_legacy_x2apic)
6032 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6033 if (!vmx_msr_bitmap_longmode)
6036 vmx_msr_bitmap_longmode_x2apic =
6037 (unsigned long *)__get_free_page(GFP_KERNEL);
6038 if (!vmx_msr_bitmap_longmode_x2apic)
6042 vmx_msr_bitmap_nested =
6043 (unsigned long *)__get_free_page(GFP_KERNEL);
6044 if (!vmx_msr_bitmap_nested)
6048 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6049 if (!vmx_vmread_bitmap)
6052 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6053 if (!vmx_vmwrite_bitmap)
6056 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6057 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6060 * Allow direct access to the PC debug port (it is often used for I/O
6061 * delays, but the vmexits simply slow things down).
6063 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6064 clear_bit(0x80, vmx_io_bitmap_a);
6066 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6068 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6069 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6071 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6073 if (setup_vmcs_config(&vmcs_config) < 0) {
6078 if (boot_cpu_has(X86_FEATURE_NX))
6079 kvm_enable_efer_bits(EFER_NX);
6081 if (!cpu_has_vmx_vpid())
6083 if (!cpu_has_vmx_shadow_vmcs())
6084 enable_shadow_vmcs = 0;
6085 if (enable_shadow_vmcs)
6086 init_vmcs_shadow_fields();
6088 if (!cpu_has_vmx_ept() ||
6089 !cpu_has_vmx_ept_4levels()) {
6091 enable_unrestricted_guest = 0;
6092 enable_ept_ad_bits = 0;
6095 if (!cpu_has_vmx_ept_ad_bits())
6096 enable_ept_ad_bits = 0;
6098 if (!cpu_has_vmx_unrestricted_guest())
6099 enable_unrestricted_guest = 0;
6101 if (!cpu_has_vmx_flexpriority())
6102 flexpriority_enabled = 0;
6105 * set_apic_access_page_addr() is used to reload apic access
6106 * page upon invalidation. No need to do anything if not
6107 * using the APIC_ACCESS_ADDR VMCS field.
6109 if (!flexpriority_enabled)
6110 kvm_x86_ops->set_apic_access_page_addr = NULL;
6112 if (!cpu_has_vmx_tpr_shadow())
6113 kvm_x86_ops->update_cr8_intercept = NULL;
6115 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6116 kvm_disable_largepages();
6118 if (!cpu_has_vmx_ple())
6121 if (!cpu_has_vmx_apicv())
6125 kvm_x86_ops->update_cr8_intercept = NULL;
6127 kvm_x86_ops->hwapic_irr_update = NULL;
6128 kvm_x86_ops->hwapic_isr_update = NULL;
6129 kvm_x86_ops->deliver_posted_interrupt = NULL;
6130 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6133 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6134 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6135 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6136 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6137 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6138 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6139 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6141 memcpy(vmx_msr_bitmap_legacy_x2apic,
6142 vmx_msr_bitmap_legacy, PAGE_SIZE);
6143 memcpy(vmx_msr_bitmap_longmode_x2apic,
6144 vmx_msr_bitmap_longmode, PAGE_SIZE);
6147 for (msr = 0x800; msr <= 0x8ff; msr++)
6148 vmx_disable_intercept_msr_read_x2apic(msr);
6150 /* According SDM, in x2apic mode, the whole id reg is used.
6151 * But in KVM, it only use the highest eight bits. Need to
6153 vmx_enable_intercept_msr_read_x2apic(0x802);
6155 vmx_enable_intercept_msr_read_x2apic(0x839);
6157 vmx_disable_intercept_msr_write_x2apic(0x808);
6159 vmx_disable_intercept_msr_write_x2apic(0x80b);
6161 vmx_disable_intercept_msr_write_x2apic(0x83f);
6165 kvm_mmu_set_mask_ptes(0ull,
6166 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6167 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6168 0ull, VMX_EPT_EXECUTABLE_MASK);
6169 ept_set_mmio_spte_mask();
6174 update_ple_window_actual_max();
6177 * Only enable PML when hardware supports PML feature, and both EPT
6178 * and EPT A/D bit features are enabled -- PML depends on them to work.
6180 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6184 kvm_x86_ops->slot_enable_log_dirty = NULL;
6185 kvm_x86_ops->slot_disable_log_dirty = NULL;
6186 kvm_x86_ops->flush_log_dirty = NULL;
6187 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6190 return alloc_kvm_area();
6193 free_page((unsigned long)vmx_vmwrite_bitmap);
6195 free_page((unsigned long)vmx_vmread_bitmap);
6198 free_page((unsigned long)vmx_msr_bitmap_nested);
6200 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6202 free_page((unsigned long)vmx_msr_bitmap_longmode);
6204 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6206 free_page((unsigned long)vmx_msr_bitmap_legacy);
6208 free_page((unsigned long)vmx_io_bitmap_b);
6210 free_page((unsigned long)vmx_io_bitmap_a);
6215 static __exit void hardware_unsetup(void)
6217 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6218 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6219 free_page((unsigned long)vmx_msr_bitmap_legacy);
6220 free_page((unsigned long)vmx_msr_bitmap_longmode);
6221 free_page((unsigned long)vmx_io_bitmap_b);
6222 free_page((unsigned long)vmx_io_bitmap_a);
6223 free_page((unsigned long)vmx_vmwrite_bitmap);
6224 free_page((unsigned long)vmx_vmread_bitmap);
6226 free_page((unsigned long)vmx_msr_bitmap_nested);
6232 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6233 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6235 static int handle_pause(struct kvm_vcpu *vcpu)
6238 grow_ple_window(vcpu);
6240 skip_emulated_instruction(vcpu);
6241 kvm_vcpu_on_spin(vcpu);
6246 static int handle_nop(struct kvm_vcpu *vcpu)
6248 skip_emulated_instruction(vcpu);
6252 static int handle_mwait(struct kvm_vcpu *vcpu)
6254 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6255 return handle_nop(vcpu);
6258 static int handle_monitor(struct kvm_vcpu *vcpu)
6260 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6261 return handle_nop(vcpu);
6265 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6266 * We could reuse a single VMCS for all the L2 guests, but we also want the
6267 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6268 * allows keeping them loaded on the processor, and in the future will allow
6269 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6270 * every entry if they never change.
6271 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6272 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6274 * The following functions allocate and free a vmcs02 in this pool.
6277 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6278 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6280 struct vmcs02_list *item;
6281 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6282 if (item->vmptr == vmx->nested.current_vmptr) {
6283 list_move(&item->list, &vmx->nested.vmcs02_pool);
6284 return &item->vmcs02;
6287 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6288 /* Recycle the least recently used VMCS. */
6289 item = list_entry(vmx->nested.vmcs02_pool.prev,
6290 struct vmcs02_list, list);
6291 item->vmptr = vmx->nested.current_vmptr;
6292 list_move(&item->list, &vmx->nested.vmcs02_pool);
6293 return &item->vmcs02;
6296 /* Create a new VMCS */
6297 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6300 item->vmcs02.vmcs = alloc_vmcs();
6301 if (!item->vmcs02.vmcs) {
6305 loaded_vmcs_init(&item->vmcs02);
6306 item->vmptr = vmx->nested.current_vmptr;
6307 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6308 vmx->nested.vmcs02_num++;
6309 return &item->vmcs02;
6312 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6313 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6315 struct vmcs02_list *item;
6316 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6317 if (item->vmptr == vmptr) {
6318 free_loaded_vmcs(&item->vmcs02);
6319 list_del(&item->list);
6321 vmx->nested.vmcs02_num--;
6327 * Free all VMCSs saved for this vcpu, except the one pointed by
6328 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6329 * must be &vmx->vmcs01.
6331 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6333 struct vmcs02_list *item, *n;
6335 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6336 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6338 * Something will leak if the above WARN triggers. Better than
6341 if (vmx->loaded_vmcs == &item->vmcs02)
6344 free_loaded_vmcs(&item->vmcs02);
6345 list_del(&item->list);
6347 vmx->nested.vmcs02_num--;
6352 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6353 * set the success or error code of an emulated VMX instruction, as specified
6354 * by Vol 2B, VMX Instruction Reference, "Conventions".
6356 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6358 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6359 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6360 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6363 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6365 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6366 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6367 X86_EFLAGS_SF | X86_EFLAGS_OF))
6371 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6372 u32 vm_instruction_error)
6374 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6376 * failValid writes the error number to the current VMCS, which
6377 * can't be done there isn't a current VMCS.
6379 nested_vmx_failInvalid(vcpu);
6382 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6383 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6384 X86_EFLAGS_SF | X86_EFLAGS_OF))
6386 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6388 * We don't need to force a shadow sync because
6389 * VM_INSTRUCTION_ERROR is not shadowed
6393 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6395 /* TODO: not to reset guest simply here. */
6396 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6397 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6400 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6402 struct vcpu_vmx *vmx =
6403 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6405 vmx->nested.preemption_timer_expired = true;
6406 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6407 kvm_vcpu_kick(&vmx->vcpu);
6409 return HRTIMER_NORESTART;
6413 * Decode the memory-address operand of a vmx instruction, as recorded on an
6414 * exit caused by such an instruction (run by a guest hypervisor).
6415 * On success, returns 0. When the operand is invalid, returns 1 and throws
6418 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6419 unsigned long exit_qualification,
6420 u32 vmx_instruction_info, gva_t *ret)
6423 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6424 * Execution", on an exit, vmx_instruction_info holds most of the
6425 * addressing components of the operand. Only the displacement part
6426 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6427 * For how an actual address is calculated from all these components,
6428 * refer to Vol. 1, "Operand Addressing".
6430 int scaling = vmx_instruction_info & 3;
6431 int addr_size = (vmx_instruction_info >> 7) & 7;
6432 bool is_reg = vmx_instruction_info & (1u << 10);
6433 int seg_reg = (vmx_instruction_info >> 15) & 7;
6434 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6435 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6436 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6437 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6440 kvm_queue_exception(vcpu, UD_VECTOR);
6444 /* Addr = segment_base + offset */
6445 /* offset = base + [index * scale] + displacement */
6446 *ret = vmx_get_segment_base(vcpu, seg_reg);
6448 *ret += kvm_register_read(vcpu, base_reg);
6450 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6451 *ret += exit_qualification; /* holds the displacement */
6453 if (addr_size == 1) /* 32 bit */
6457 * TODO: throw #GP (and return 1) in various cases that the VM*
6458 * instructions require it - e.g., offset beyond segment limit,
6459 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6460 * address, and so on. Currently these are not checked.
6466 * This function performs the various checks including
6467 * - if it's 4KB aligned
6468 * - No bits beyond the physical address width are set
6469 * - Returns 0 on success or else 1
6470 * (Intel SDM Section 30.3)
6472 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6477 struct x86_exception e;
6479 struct vcpu_vmx *vmx = to_vmx(vcpu);
6480 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6482 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6483 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6486 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6487 sizeof(vmptr), &e)) {
6488 kvm_inject_page_fault(vcpu, &e);
6492 switch (exit_reason) {
6493 case EXIT_REASON_VMON:
6496 * The first 4 bytes of VMXON region contain the supported
6497 * VMCS revision identifier
6499 * Note - IA32_VMX_BASIC[48] will never be 1
6500 * for the nested case;
6501 * which replaces physical address width with 32
6504 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6505 nested_vmx_failInvalid(vcpu);
6506 skip_emulated_instruction(vcpu);
6510 page = nested_get_page(vcpu, vmptr);
6512 *(u32 *)kmap(page) != VMCS12_REVISION) {
6513 nested_vmx_failInvalid(vcpu);
6515 skip_emulated_instruction(vcpu);
6519 vmx->nested.vmxon_ptr = vmptr;
6521 case EXIT_REASON_VMCLEAR:
6522 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6523 nested_vmx_failValid(vcpu,
6524 VMXERR_VMCLEAR_INVALID_ADDRESS);
6525 skip_emulated_instruction(vcpu);
6529 if (vmptr == vmx->nested.vmxon_ptr) {
6530 nested_vmx_failValid(vcpu,
6531 VMXERR_VMCLEAR_VMXON_POINTER);
6532 skip_emulated_instruction(vcpu);
6536 case EXIT_REASON_VMPTRLD:
6537 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6538 nested_vmx_failValid(vcpu,
6539 VMXERR_VMPTRLD_INVALID_ADDRESS);
6540 skip_emulated_instruction(vcpu);
6544 if (vmptr == vmx->nested.vmxon_ptr) {
6545 nested_vmx_failValid(vcpu,
6546 VMXERR_VMCLEAR_VMXON_POINTER);
6547 skip_emulated_instruction(vcpu);
6552 return 1; /* shouldn't happen */
6561 * Emulate the VMXON instruction.
6562 * Currently, we just remember that VMX is active, and do not save or even
6563 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6564 * do not currently need to store anything in that guest-allocated memory
6565 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6566 * argument is different from the VMXON pointer (which the spec says they do).
6568 static int handle_vmon(struct kvm_vcpu *vcpu)
6570 struct kvm_segment cs;
6571 struct vcpu_vmx *vmx = to_vmx(vcpu);
6572 struct vmcs *shadow_vmcs;
6573 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6574 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6576 /* The Intel VMX Instruction Reference lists a bunch of bits that
6577 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6578 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6579 * Otherwise, we should fail with #UD. We test these now:
6581 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6582 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6583 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6584 kvm_queue_exception(vcpu, UD_VECTOR);
6588 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6589 if (is_long_mode(vcpu) && !cs.l) {
6590 kvm_queue_exception(vcpu, UD_VECTOR);
6594 if (vmx_get_cpl(vcpu)) {
6595 kvm_inject_gp(vcpu, 0);
6599 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6602 if (vmx->nested.vmxon) {
6603 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6604 skip_emulated_instruction(vcpu);
6608 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6609 != VMXON_NEEDED_FEATURES) {
6610 kvm_inject_gp(vcpu, 0);
6614 if (enable_shadow_vmcs) {
6615 shadow_vmcs = alloc_vmcs();
6618 /* mark vmcs as shadow */
6619 shadow_vmcs->revision_id |= (1u << 31);
6620 /* init shadow vmcs */
6621 vmcs_clear(shadow_vmcs);
6622 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6625 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6626 vmx->nested.vmcs02_num = 0;
6628 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6630 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6632 vmx->nested.vmxon = true;
6634 skip_emulated_instruction(vcpu);
6635 nested_vmx_succeed(vcpu);
6640 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6641 * for running VMX instructions (except VMXON, whose prerequisites are
6642 * slightly different). It also specifies what exception to inject otherwise.
6644 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6646 struct kvm_segment cs;
6647 struct vcpu_vmx *vmx = to_vmx(vcpu);
6649 if (!vmx->nested.vmxon) {
6650 kvm_queue_exception(vcpu, UD_VECTOR);
6654 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6655 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6656 (is_long_mode(vcpu) && !cs.l)) {
6657 kvm_queue_exception(vcpu, UD_VECTOR);
6661 if (vmx_get_cpl(vcpu)) {
6662 kvm_inject_gp(vcpu, 0);
6669 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6672 if (vmx->nested.current_vmptr == -1ull)
6675 /* current_vmptr and current_vmcs12 are always set/reset together */
6676 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6679 if (enable_shadow_vmcs) {
6680 /* copy to memory all shadowed fields in case
6681 they were modified */
6682 copy_shadow_to_vmcs12(vmx);
6683 vmx->nested.sync_shadow_vmcs = false;
6684 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6685 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6686 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6687 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6689 vmx->nested.posted_intr_nv = -1;
6690 kunmap(vmx->nested.current_vmcs12_page);
6691 nested_release_page(vmx->nested.current_vmcs12_page);
6692 vmx->nested.current_vmptr = -1ull;
6693 vmx->nested.current_vmcs12 = NULL;
6697 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6698 * just stops using VMX.
6700 static void free_nested(struct vcpu_vmx *vmx)
6702 if (!vmx->nested.vmxon)
6705 vmx->nested.vmxon = false;
6706 nested_release_vmcs12(vmx);
6707 if (enable_shadow_vmcs)
6708 free_vmcs(vmx->nested.current_shadow_vmcs);
6709 /* Unpin physical memory we referred to in current vmcs02 */
6710 if (vmx->nested.apic_access_page) {
6711 nested_release_page(vmx->nested.apic_access_page);
6712 vmx->nested.apic_access_page = NULL;
6714 if (vmx->nested.virtual_apic_page) {
6715 nested_release_page(vmx->nested.virtual_apic_page);
6716 vmx->nested.virtual_apic_page = NULL;
6718 if (vmx->nested.pi_desc_page) {
6719 kunmap(vmx->nested.pi_desc_page);
6720 nested_release_page(vmx->nested.pi_desc_page);
6721 vmx->nested.pi_desc_page = NULL;
6722 vmx->nested.pi_desc = NULL;
6725 nested_free_all_saved_vmcss(vmx);
6728 /* Emulate the VMXOFF instruction */
6729 static int handle_vmoff(struct kvm_vcpu *vcpu)
6731 if (!nested_vmx_check_permission(vcpu))
6733 free_nested(to_vmx(vcpu));
6734 skip_emulated_instruction(vcpu);
6735 nested_vmx_succeed(vcpu);
6739 /* Emulate the VMCLEAR instruction */
6740 static int handle_vmclear(struct kvm_vcpu *vcpu)
6742 struct vcpu_vmx *vmx = to_vmx(vcpu);
6744 struct vmcs12 *vmcs12;
6747 if (!nested_vmx_check_permission(vcpu))
6750 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6753 if (vmptr == vmx->nested.current_vmptr)
6754 nested_release_vmcs12(vmx);
6756 page = nested_get_page(vcpu, vmptr);
6759 * For accurate processor emulation, VMCLEAR beyond available
6760 * physical memory should do nothing at all. However, it is
6761 * possible that a nested vmx bug, not a guest hypervisor bug,
6762 * resulted in this case, so let's shut down before doing any
6765 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6768 vmcs12 = kmap(page);
6769 vmcs12->launch_state = 0;
6771 nested_release_page(page);
6773 nested_free_vmcs02(vmx, vmptr);
6775 skip_emulated_instruction(vcpu);
6776 nested_vmx_succeed(vcpu);
6780 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6782 /* Emulate the VMLAUNCH instruction */
6783 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6785 return nested_vmx_run(vcpu, true);
6788 /* Emulate the VMRESUME instruction */
6789 static int handle_vmresume(struct kvm_vcpu *vcpu)
6792 return nested_vmx_run(vcpu, false);
6795 enum vmcs_field_type {
6796 VMCS_FIELD_TYPE_U16 = 0,
6797 VMCS_FIELD_TYPE_U64 = 1,
6798 VMCS_FIELD_TYPE_U32 = 2,
6799 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6802 static inline int vmcs_field_type(unsigned long field)
6804 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6805 return VMCS_FIELD_TYPE_U32;
6806 return (field >> 13) & 0x3 ;
6809 static inline int vmcs_field_readonly(unsigned long field)
6811 return (((field >> 10) & 0x3) == 1);
6815 * Read a vmcs12 field. Since these can have varying lengths and we return
6816 * one type, we chose the biggest type (u64) and zero-extend the return value
6817 * to that size. Note that the caller, handle_vmread, might need to use only
6818 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6819 * 64-bit fields are to be returned).
6821 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6822 unsigned long field, u64 *ret)
6824 short offset = vmcs_field_to_offset(field);
6830 p = ((char *)(get_vmcs12(vcpu))) + offset;
6832 switch (vmcs_field_type(field)) {
6833 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6834 *ret = *((natural_width *)p);
6836 case VMCS_FIELD_TYPE_U16:
6839 case VMCS_FIELD_TYPE_U32:
6842 case VMCS_FIELD_TYPE_U64:
6852 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6853 unsigned long field, u64 field_value){
6854 short offset = vmcs_field_to_offset(field);
6855 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6859 switch (vmcs_field_type(field)) {
6860 case VMCS_FIELD_TYPE_U16:
6861 *(u16 *)p = field_value;
6863 case VMCS_FIELD_TYPE_U32:
6864 *(u32 *)p = field_value;
6866 case VMCS_FIELD_TYPE_U64:
6867 *(u64 *)p = field_value;
6869 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6870 *(natural_width *)p = field_value;
6879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6882 unsigned long field;
6884 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6885 const unsigned long *fields = shadow_read_write_fields;
6886 const int num_fields = max_shadow_read_write_fields;
6890 vmcs_load(shadow_vmcs);
6892 for (i = 0; i < num_fields; i++) {
6894 switch (vmcs_field_type(field)) {
6895 case VMCS_FIELD_TYPE_U16:
6896 field_value = vmcs_read16(field);
6898 case VMCS_FIELD_TYPE_U32:
6899 field_value = vmcs_read32(field);
6901 case VMCS_FIELD_TYPE_U64:
6902 field_value = vmcs_read64(field);
6904 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6905 field_value = vmcs_readl(field);
6911 vmcs12_write_any(&vmx->vcpu, field, field_value);
6914 vmcs_clear(shadow_vmcs);
6915 vmcs_load(vmx->loaded_vmcs->vmcs);
6920 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6922 const unsigned long *fields[] = {
6923 shadow_read_write_fields,
6924 shadow_read_only_fields
6926 const int max_fields[] = {
6927 max_shadow_read_write_fields,
6928 max_shadow_read_only_fields
6931 unsigned long field;
6932 u64 field_value = 0;
6933 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6935 vmcs_load(shadow_vmcs);
6937 for (q = 0; q < ARRAY_SIZE(fields); q++) {
6938 for (i = 0; i < max_fields[q]; i++) {
6939 field = fields[q][i];
6940 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6942 switch (vmcs_field_type(field)) {
6943 case VMCS_FIELD_TYPE_U16:
6944 vmcs_write16(field, (u16)field_value);
6946 case VMCS_FIELD_TYPE_U32:
6947 vmcs_write32(field, (u32)field_value);
6949 case VMCS_FIELD_TYPE_U64:
6950 vmcs_write64(field, (u64)field_value);
6952 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6953 vmcs_writel(field, (long)field_value);
6962 vmcs_clear(shadow_vmcs);
6963 vmcs_load(vmx->loaded_vmcs->vmcs);
6967 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6968 * used before) all generate the same failure when it is missing.
6970 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6972 struct vcpu_vmx *vmx = to_vmx(vcpu);
6973 if (vmx->nested.current_vmptr == -1ull) {
6974 nested_vmx_failInvalid(vcpu);
6975 skip_emulated_instruction(vcpu);
6981 static int handle_vmread(struct kvm_vcpu *vcpu)
6983 unsigned long field;
6985 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6986 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6989 if (!nested_vmx_check_permission(vcpu) ||
6990 !nested_vmx_check_vmcs12(vcpu))
6993 /* Decode instruction info and find the field to read */
6994 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6995 /* Read the field, zero-extended to a u64 field_value */
6996 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6997 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6998 skip_emulated_instruction(vcpu);
7002 * Now copy part of this value to register or memory, as requested.
7003 * Note that the number of bits actually copied is 32 or 64 depending
7004 * on the guest's mode (32 or 64 bit), not on the given field's length.
7006 if (vmx_instruction_info & (1u << 10)) {
7007 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7010 if (get_vmx_mem_address(vcpu, exit_qualification,
7011 vmx_instruction_info, &gva))
7013 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7014 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7015 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7018 nested_vmx_succeed(vcpu);
7019 skip_emulated_instruction(vcpu);
7024 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7026 unsigned long field;
7028 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7029 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7030 /* The value to write might be 32 or 64 bits, depending on L1's long
7031 * mode, and eventually we need to write that into a field of several
7032 * possible lengths. The code below first zero-extends the value to 64
7033 * bit (field_value), and then copies only the approriate number of
7034 * bits into the vmcs12 field.
7036 u64 field_value = 0;
7037 struct x86_exception e;
7039 if (!nested_vmx_check_permission(vcpu) ||
7040 !nested_vmx_check_vmcs12(vcpu))
7043 if (vmx_instruction_info & (1u << 10))
7044 field_value = kvm_register_readl(vcpu,
7045 (((vmx_instruction_info) >> 3) & 0xf));
7047 if (get_vmx_mem_address(vcpu, exit_qualification,
7048 vmx_instruction_info, &gva))
7050 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7051 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7052 kvm_inject_page_fault(vcpu, &e);
7058 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7059 if (vmcs_field_readonly(field)) {
7060 nested_vmx_failValid(vcpu,
7061 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7062 skip_emulated_instruction(vcpu);
7066 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7067 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7068 skip_emulated_instruction(vcpu);
7072 nested_vmx_succeed(vcpu);
7073 skip_emulated_instruction(vcpu);
7077 /* Emulate the VMPTRLD instruction */
7078 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7080 struct vcpu_vmx *vmx = to_vmx(vcpu);
7084 if (!nested_vmx_check_permission(vcpu))
7087 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7090 if (vmx->nested.current_vmptr != vmptr) {
7091 struct vmcs12 *new_vmcs12;
7093 page = nested_get_page(vcpu, vmptr);
7095 nested_vmx_failInvalid(vcpu);
7096 skip_emulated_instruction(vcpu);
7099 new_vmcs12 = kmap(page);
7100 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7102 nested_release_page_clean(page);
7103 nested_vmx_failValid(vcpu,
7104 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7105 skip_emulated_instruction(vcpu);
7109 nested_release_vmcs12(vmx);
7110 vmx->nested.current_vmptr = vmptr;
7111 vmx->nested.current_vmcs12 = new_vmcs12;
7112 vmx->nested.current_vmcs12_page = page;
7113 if (enable_shadow_vmcs) {
7114 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7115 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7116 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7117 vmcs_write64(VMCS_LINK_POINTER,
7118 __pa(vmx->nested.current_shadow_vmcs));
7119 vmx->nested.sync_shadow_vmcs = true;
7123 nested_vmx_succeed(vcpu);
7124 skip_emulated_instruction(vcpu);
7128 /* Emulate the VMPTRST instruction */
7129 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7131 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7132 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7134 struct x86_exception e;
7136 if (!nested_vmx_check_permission(vcpu))
7139 if (get_vmx_mem_address(vcpu, exit_qualification,
7140 vmx_instruction_info, &vmcs_gva))
7142 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7143 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7144 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7146 kvm_inject_page_fault(vcpu, &e);
7149 nested_vmx_succeed(vcpu);
7150 skip_emulated_instruction(vcpu);
7154 /* Emulate the INVEPT instruction */
7155 static int handle_invept(struct kvm_vcpu *vcpu)
7157 struct vcpu_vmx *vmx = to_vmx(vcpu);
7158 u32 vmx_instruction_info, types;
7161 struct x86_exception e;
7166 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7167 SECONDARY_EXEC_ENABLE_EPT) ||
7168 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7169 kvm_queue_exception(vcpu, UD_VECTOR);
7173 if (!nested_vmx_check_permission(vcpu))
7176 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7177 kvm_queue_exception(vcpu, UD_VECTOR);
7181 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7182 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7184 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7186 if (!(types & (1UL << type))) {
7187 nested_vmx_failValid(vcpu,
7188 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7192 /* According to the Intel VMX instruction reference, the memory
7193 * operand is read even if it isn't needed (e.g., for type==global)
7195 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7196 vmx_instruction_info, &gva))
7198 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7199 sizeof(operand), &e)) {
7200 kvm_inject_page_fault(vcpu, &e);
7205 case VMX_EPT_EXTENT_GLOBAL:
7206 kvm_mmu_sync_roots(vcpu);
7207 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7208 nested_vmx_succeed(vcpu);
7211 /* Trap single context invalidation invept calls */
7216 skip_emulated_instruction(vcpu);
7220 static int handle_invvpid(struct kvm_vcpu *vcpu)
7222 kvm_queue_exception(vcpu, UD_VECTOR);
7226 static int handle_pml_full(struct kvm_vcpu *vcpu)
7228 unsigned long exit_qualification;
7230 trace_kvm_pml_full(vcpu->vcpu_id);
7232 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7235 * PML buffer FULL happened while executing iret from NMI,
7236 * "blocked by NMI" bit has to be set before next VM entry.
7238 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7239 cpu_has_virtual_nmis() &&
7240 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7241 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7242 GUEST_INTR_STATE_NMI);
7245 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7246 * here.., and there's no userspace involvement needed for PML.
7252 * The exit handlers return 1 if the exit was handled fully and guest execution
7253 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7254 * to be done to userspace and return 0.
7256 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7257 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7258 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7259 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7260 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7261 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7262 [EXIT_REASON_CR_ACCESS] = handle_cr,
7263 [EXIT_REASON_DR_ACCESS] = handle_dr,
7264 [EXIT_REASON_CPUID] = handle_cpuid,
7265 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7266 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7267 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7268 [EXIT_REASON_HLT] = handle_halt,
7269 [EXIT_REASON_INVD] = handle_invd,
7270 [EXIT_REASON_INVLPG] = handle_invlpg,
7271 [EXIT_REASON_RDPMC] = handle_rdpmc,
7272 [EXIT_REASON_VMCALL] = handle_vmcall,
7273 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7274 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7275 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7276 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7277 [EXIT_REASON_VMREAD] = handle_vmread,
7278 [EXIT_REASON_VMRESUME] = handle_vmresume,
7279 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7280 [EXIT_REASON_VMOFF] = handle_vmoff,
7281 [EXIT_REASON_VMON] = handle_vmon,
7282 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7283 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7284 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7285 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7286 [EXIT_REASON_WBINVD] = handle_wbinvd,
7287 [EXIT_REASON_XSETBV] = handle_xsetbv,
7288 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7289 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7290 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7291 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7292 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7293 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7294 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7295 [EXIT_REASON_INVEPT] = handle_invept,
7296 [EXIT_REASON_INVVPID] = handle_invvpid,
7297 [EXIT_REASON_XSAVES] = handle_xsaves,
7298 [EXIT_REASON_XRSTORS] = handle_xrstors,
7299 [EXIT_REASON_PML_FULL] = handle_pml_full,
7302 static const int kvm_vmx_max_exit_handlers =
7303 ARRAY_SIZE(kvm_vmx_exit_handlers);
7305 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7306 struct vmcs12 *vmcs12)
7308 unsigned long exit_qualification;
7309 gpa_t bitmap, last_bitmap;
7314 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7315 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7317 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7319 port = exit_qualification >> 16;
7320 size = (exit_qualification & 7) + 1;
7322 last_bitmap = (gpa_t)-1;
7327 bitmap = vmcs12->io_bitmap_a;
7328 else if (port < 0x10000)
7329 bitmap = vmcs12->io_bitmap_b;
7332 bitmap += (port & 0x7fff) / 8;
7334 if (last_bitmap != bitmap)
7335 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7337 if (b & (1 << (port & 7)))
7342 last_bitmap = bitmap;
7349 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7350 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7351 * disinterest in the current event (read or write a specific MSR) by using an
7352 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7354 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7355 struct vmcs12 *vmcs12, u32 exit_reason)
7357 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7360 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7364 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7365 * for the four combinations of read/write and low/high MSR numbers.
7366 * First we need to figure out which of the four to use:
7368 bitmap = vmcs12->msr_bitmap;
7369 if (exit_reason == EXIT_REASON_MSR_WRITE)
7371 if (msr_index >= 0xc0000000) {
7372 msr_index -= 0xc0000000;
7376 /* Then read the msr_index'th bit from this bitmap: */
7377 if (msr_index < 1024*8) {
7379 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7381 return 1 & (b >> (msr_index & 7));
7383 return true; /* let L1 handle the wrong parameter */
7387 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7388 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7389 * intercept (via guest_host_mask etc.) the current event.
7391 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7392 struct vmcs12 *vmcs12)
7394 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7395 int cr = exit_qualification & 15;
7396 int reg = (exit_qualification >> 8) & 15;
7397 unsigned long val = kvm_register_readl(vcpu, reg);
7399 switch ((exit_qualification >> 4) & 3) {
7400 case 0: /* mov to cr */
7403 if (vmcs12->cr0_guest_host_mask &
7404 (val ^ vmcs12->cr0_read_shadow))
7408 if ((vmcs12->cr3_target_count >= 1 &&
7409 vmcs12->cr3_target_value0 == val) ||
7410 (vmcs12->cr3_target_count >= 2 &&
7411 vmcs12->cr3_target_value1 == val) ||
7412 (vmcs12->cr3_target_count >= 3 &&
7413 vmcs12->cr3_target_value2 == val) ||
7414 (vmcs12->cr3_target_count >= 4 &&
7415 vmcs12->cr3_target_value3 == val))
7417 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7421 if (vmcs12->cr4_guest_host_mask &
7422 (vmcs12->cr4_read_shadow ^ val))
7426 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7432 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7433 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7436 case 1: /* mov from cr */
7439 if (vmcs12->cpu_based_vm_exec_control &
7440 CPU_BASED_CR3_STORE_EXITING)
7444 if (vmcs12->cpu_based_vm_exec_control &
7445 CPU_BASED_CR8_STORE_EXITING)
7452 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7453 * cr0. Other attempted changes are ignored, with no exit.
7455 if (vmcs12->cr0_guest_host_mask & 0xe &
7456 (val ^ vmcs12->cr0_read_shadow))
7458 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7459 !(vmcs12->cr0_read_shadow & 0x1) &&
7468 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7469 * should handle it ourselves in L0 (and then continue L2). Only call this
7470 * when in is_guest_mode (L2).
7472 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7474 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7475 struct vcpu_vmx *vmx = to_vmx(vcpu);
7476 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7477 u32 exit_reason = vmx->exit_reason;
7479 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7480 vmcs_readl(EXIT_QUALIFICATION),
7481 vmx->idt_vectoring_info,
7483 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7486 if (vmx->nested.nested_run_pending)
7489 if (unlikely(vmx->fail)) {
7490 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7491 vmcs_read32(VM_INSTRUCTION_ERROR));
7495 switch (exit_reason) {
7496 case EXIT_REASON_EXCEPTION_NMI:
7497 if (!is_exception(intr_info))
7499 else if (is_page_fault(intr_info))
7501 else if (is_no_device(intr_info) &&
7502 !(vmcs12->guest_cr0 & X86_CR0_TS))
7504 return vmcs12->exception_bitmap &
7505 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7506 case EXIT_REASON_EXTERNAL_INTERRUPT:
7508 case EXIT_REASON_TRIPLE_FAULT:
7510 case EXIT_REASON_PENDING_INTERRUPT:
7511 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7512 case EXIT_REASON_NMI_WINDOW:
7513 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7514 case EXIT_REASON_TASK_SWITCH:
7516 case EXIT_REASON_CPUID:
7517 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7520 case EXIT_REASON_HLT:
7521 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7522 case EXIT_REASON_INVD:
7524 case EXIT_REASON_INVLPG:
7525 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7526 case EXIT_REASON_RDPMC:
7527 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7528 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7529 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7530 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7531 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7532 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7533 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7534 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7535 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7537 * VMX instructions trap unconditionally. This allows L1 to
7538 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7541 case EXIT_REASON_CR_ACCESS:
7542 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7543 case EXIT_REASON_DR_ACCESS:
7544 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7545 case EXIT_REASON_IO_INSTRUCTION:
7546 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7547 case EXIT_REASON_MSR_READ:
7548 case EXIT_REASON_MSR_WRITE:
7549 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7550 case EXIT_REASON_INVALID_STATE:
7552 case EXIT_REASON_MWAIT_INSTRUCTION:
7553 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7554 case EXIT_REASON_MONITOR_INSTRUCTION:
7555 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7556 case EXIT_REASON_PAUSE_INSTRUCTION:
7557 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7558 nested_cpu_has2(vmcs12,
7559 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7560 case EXIT_REASON_MCE_DURING_VMENTRY:
7562 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7563 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7564 case EXIT_REASON_APIC_ACCESS:
7565 return nested_cpu_has2(vmcs12,
7566 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7567 case EXIT_REASON_APIC_WRITE:
7568 case EXIT_REASON_EOI_INDUCED:
7569 /* apic_write and eoi_induced should exit unconditionally. */
7571 case EXIT_REASON_EPT_VIOLATION:
7573 * L0 always deals with the EPT violation. If nested EPT is
7574 * used, and the nested mmu code discovers that the address is
7575 * missing in the guest EPT table (EPT12), the EPT violation
7576 * will be injected with nested_ept_inject_page_fault()
7579 case EXIT_REASON_EPT_MISCONFIG:
7581 * L2 never uses directly L1's EPT, but rather L0's own EPT
7582 * table (shadow on EPT) or a merged EPT table that L0 built
7583 * (EPT on EPT). So any problems with the structure of the
7584 * table is L0's fault.
7587 case EXIT_REASON_WBINVD:
7588 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7589 case EXIT_REASON_XSETBV:
7591 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7593 * This should never happen, since it is not possible to
7594 * set XSS to a non-zero value---neither in L1 nor in L2.
7595 * If if it were, XSS would have to be checked against
7596 * the XSS exit bitmap in vmcs12.
7598 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7604 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7606 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7607 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7610 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7612 struct page *pml_pg;
7615 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7619 vmx->pml_pg = pml_pg;
7621 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7622 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7624 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7625 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7626 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7631 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7635 ASSERT(vmx->pml_pg);
7636 __free_page(vmx->pml_pg);
7639 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7640 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7641 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7644 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7646 struct kvm *kvm = vmx->vcpu.kvm;
7650 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7652 /* Do nothing if PML buffer is empty */
7653 if (pml_idx == (PML_ENTITY_NUM - 1))
7656 /* PML index always points to next available PML buffer entity */
7657 if (pml_idx >= PML_ENTITY_NUM)
7662 pml_buf = page_address(vmx->pml_pg);
7663 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7666 gpa = pml_buf[pml_idx];
7667 WARN_ON(gpa & (PAGE_SIZE - 1));
7668 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7671 /* reset PML index */
7672 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7676 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7677 * Called before reporting dirty_bitmap to userspace.
7679 static void kvm_flush_pml_buffers(struct kvm *kvm)
7682 struct kvm_vcpu *vcpu;
7684 * We only need to kick vcpu out of guest mode here, as PML buffer
7685 * is flushed at beginning of all VMEXITs, and it's obvious that only
7686 * vcpus running in guest are possible to have unflushed GPAs in PML
7689 kvm_for_each_vcpu(i, vcpu, kvm)
7690 kvm_vcpu_kick(vcpu);
7694 * The guest has exited. See if we can fix it or if we need userspace
7697 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7699 struct vcpu_vmx *vmx = to_vmx(vcpu);
7700 u32 exit_reason = vmx->exit_reason;
7701 u32 vectoring_info = vmx->idt_vectoring_info;
7704 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7705 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7706 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7707 * mode as if vcpus is in root mode, the PML buffer must has been
7711 vmx_flush_pml_buffer(vmx);
7713 /* If guest state is invalid, start emulating */
7714 if (vmx->emulation_required)
7715 return handle_invalid_guest_state(vcpu);
7717 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7718 nested_vmx_vmexit(vcpu, exit_reason,
7719 vmcs_read32(VM_EXIT_INTR_INFO),
7720 vmcs_readl(EXIT_QUALIFICATION));
7724 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7725 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7726 vcpu->run->fail_entry.hardware_entry_failure_reason
7731 if (unlikely(vmx->fail)) {
7732 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7733 vcpu->run->fail_entry.hardware_entry_failure_reason
7734 = vmcs_read32(VM_INSTRUCTION_ERROR);
7740 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7741 * delivery event since it indicates guest is accessing MMIO.
7742 * The vm-exit can be triggered again after return to guest that
7743 * will cause infinite loop.
7745 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7746 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7747 exit_reason != EXIT_REASON_EPT_VIOLATION &&
7748 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7749 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7750 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7751 vcpu->run->internal.ndata = 2;
7752 vcpu->run->internal.data[0] = vectoring_info;
7753 vcpu->run->internal.data[1] = exit_reason;
7757 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7758 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7759 get_vmcs12(vcpu))))) {
7760 if (vmx_interrupt_allowed(vcpu)) {
7761 vmx->soft_vnmi_blocked = 0;
7762 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7763 vcpu->arch.nmi_pending) {
7765 * This CPU don't support us in finding the end of an
7766 * NMI-blocked window if the guest runs with IRQs
7767 * disabled. So we pull the trigger after 1 s of
7768 * futile waiting, but inform the user about this.
7770 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7771 "state on VCPU %d after 1 s timeout\n",
7772 __func__, vcpu->vcpu_id);
7773 vmx->soft_vnmi_blocked = 0;
7777 if (exit_reason < kvm_vmx_max_exit_handlers
7778 && kvm_vmx_exit_handlers[exit_reason])
7779 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7781 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7782 kvm_queue_exception(vcpu, UD_VECTOR);
7787 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7789 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7791 if (is_guest_mode(vcpu) &&
7792 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7795 if (irr == -1 || tpr < irr) {
7796 vmcs_write32(TPR_THRESHOLD, 0);
7800 vmcs_write32(TPR_THRESHOLD, irr);
7803 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7805 u32 sec_exec_control;
7808 * There is not point to enable virtualize x2apic without enable
7811 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7812 !vmx_vm_has_apicv(vcpu->kvm))
7815 if (!vm_need_tpr_shadow(vcpu->kvm))
7818 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7821 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7822 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7824 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7825 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7827 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7829 vmx_set_msr_bitmap(vcpu);
7832 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7834 struct vcpu_vmx *vmx = to_vmx(vcpu);
7837 * Currently we do not handle the nested case where L2 has an
7838 * APIC access page of its own; that page is still pinned.
7839 * Hence, we skip the case where the VCPU is in guest mode _and_
7840 * L1 prepared an APIC access page for L2.
7842 * For the case where L1 and L2 share the same APIC access page
7843 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7844 * in the vmcs12), this function will only update either the vmcs01
7845 * or the vmcs02. If the former, the vmcs02 will be updated by
7846 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7847 * the next L2->L1 exit.
7849 if (!is_guest_mode(vcpu) ||
7850 !nested_cpu_has2(vmx->nested.current_vmcs12,
7851 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7852 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7855 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7863 status = vmcs_read16(GUEST_INTR_STATUS);
7868 vmcs_write16(GUEST_INTR_STATUS, status);
7872 static void vmx_set_rvi(int vector)
7880 status = vmcs_read16(GUEST_INTR_STATUS);
7881 old = (u8)status & 0xff;
7882 if ((u8)vector != old) {
7884 status |= (u8)vector;
7885 vmcs_write16(GUEST_INTR_STATUS, status);
7889 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7891 if (!is_guest_mode(vcpu)) {
7892 vmx_set_rvi(max_irr);
7900 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7903 if (nested_exit_on_intr(vcpu))
7907 * Else, fall back to pre-APICv interrupt injection since L2
7908 * is run without virtual interrupt delivery.
7910 if (!kvm_event_needs_reinjection(vcpu) &&
7911 vmx_interrupt_allowed(vcpu)) {
7912 kvm_queue_interrupt(vcpu, max_irr, false);
7913 vmx_inject_irq(vcpu);
7917 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7919 if (!vmx_vm_has_apicv(vcpu->kvm))
7922 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7923 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7924 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7925 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7928 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7932 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7933 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7936 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7937 exit_intr_info = vmx->exit_intr_info;
7939 /* Handle machine checks before interrupts are enabled */
7940 if (is_machine_check(exit_intr_info))
7941 kvm_machine_check();
7943 /* We need to handle NMIs before interrupts are enabled */
7944 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7945 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7946 kvm_before_handle_nmi(&vmx->vcpu);
7948 kvm_after_handle_nmi(&vmx->vcpu);
7952 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7954 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7957 * If external interrupt exists, IF bit is set in rflags/eflags on the
7958 * interrupt stack frame, and interrupt will be enabled on a return
7959 * from interrupt handler.
7961 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7962 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7963 unsigned int vector;
7964 unsigned long entry;
7966 struct vcpu_vmx *vmx = to_vmx(vcpu);
7967 #ifdef CONFIG_X86_64
7971 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7972 desc = (gate_desc *)vmx->host_idt_base + vector;
7973 entry = gate_offset(*desc);
7975 #ifdef CONFIG_X86_64
7976 "mov %%" _ASM_SP ", %[sp]\n\t"
7977 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7982 "orl $0x200, (%%" _ASM_SP ")\n\t"
7983 __ASM_SIZE(push) " $%c[cs]\n\t"
7984 "call *%[entry]\n\t"
7986 #ifdef CONFIG_X86_64
7991 [ss]"i"(__KERNEL_DS),
7992 [cs]"i"(__KERNEL_CS)
7998 static bool vmx_mpx_supported(void)
8000 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8001 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8004 static bool vmx_xsaves_supported(void)
8006 return vmcs_config.cpu_based_2nd_exec_ctrl &
8007 SECONDARY_EXEC_XSAVES;
8010 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8015 bool idtv_info_valid;
8017 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8019 if (cpu_has_virtual_nmis()) {
8020 if (vmx->nmi_known_unmasked)
8023 * Can't use vmx->exit_intr_info since we're not sure what
8024 * the exit reason is.
8026 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8027 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8028 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8030 * SDM 3: 27.7.1.2 (September 2008)
8031 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8032 * a guest IRET fault.
8033 * SDM 3: 23.2.2 (September 2008)
8034 * Bit 12 is undefined in any of the following cases:
8035 * If the VM exit sets the valid bit in the IDT-vectoring
8036 * information field.
8037 * If the VM exit is due to a double fault.
8039 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8040 vector != DF_VECTOR && !idtv_info_valid)
8041 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8042 GUEST_INTR_STATE_NMI);
8044 vmx->nmi_known_unmasked =
8045 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8046 & GUEST_INTR_STATE_NMI);
8047 } else if (unlikely(vmx->soft_vnmi_blocked))
8048 vmx->vnmi_blocked_time +=
8049 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8052 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8053 u32 idt_vectoring_info,
8054 int instr_len_field,
8055 int error_code_field)
8059 bool idtv_info_valid;
8061 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8063 vcpu->arch.nmi_injected = false;
8064 kvm_clear_exception_queue(vcpu);
8065 kvm_clear_interrupt_queue(vcpu);
8067 if (!idtv_info_valid)
8070 kvm_make_request(KVM_REQ_EVENT, vcpu);
8072 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8073 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8076 case INTR_TYPE_NMI_INTR:
8077 vcpu->arch.nmi_injected = true;
8079 * SDM 3: 27.7.1.2 (September 2008)
8080 * Clear bit "block by NMI" before VM entry if a NMI
8083 vmx_set_nmi_mask(vcpu, false);
8085 case INTR_TYPE_SOFT_EXCEPTION:
8086 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8088 case INTR_TYPE_HARD_EXCEPTION:
8089 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8090 u32 err = vmcs_read32(error_code_field);
8091 kvm_requeue_exception_e(vcpu, vector, err);
8093 kvm_requeue_exception(vcpu, vector);
8095 case INTR_TYPE_SOFT_INTR:
8096 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8098 case INTR_TYPE_EXT_INTR:
8099 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8106 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8108 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8109 VM_EXIT_INSTRUCTION_LEN,
8110 IDT_VECTORING_ERROR_CODE);
8113 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8115 __vmx_complete_interrupts(vcpu,
8116 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8117 VM_ENTRY_INSTRUCTION_LEN,
8118 VM_ENTRY_EXCEPTION_ERROR_CODE);
8120 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8123 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8126 struct perf_guest_switch_msr *msrs;
8128 msrs = perf_guest_get_msrs(&nr_msrs);
8133 for (i = 0; i < nr_msrs; i++)
8134 if (msrs[i].host == msrs[i].guest)
8135 clear_atomic_switch_msr(vmx, msrs[i].msr);
8137 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8141 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8143 struct vcpu_vmx *vmx = to_vmx(vcpu);
8144 unsigned long debugctlmsr, cr4;
8146 /* Record the guest's net vcpu time for enforced NMI injections. */
8147 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8148 vmx->entry_time = ktime_get();
8150 /* Don't enter VMX if guest state is invalid, let the exit handler
8151 start emulation until we arrive back to a valid state */
8152 if (vmx->emulation_required)
8155 if (vmx->ple_window_dirty) {
8156 vmx->ple_window_dirty = false;
8157 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8160 if (vmx->nested.sync_shadow_vmcs) {
8161 copy_vmcs12_to_shadow(vmx);
8162 vmx->nested.sync_shadow_vmcs = false;
8165 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8166 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8167 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8168 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8170 cr4 = cr4_read_shadow();
8171 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8172 vmcs_writel(HOST_CR4, cr4);
8173 vmx->host_state.vmcs_host_cr4 = cr4;
8176 /* When single-stepping over STI and MOV SS, we must clear the
8177 * corresponding interruptibility bits in the guest state. Otherwise
8178 * vmentry fails as it then expects bit 14 (BS) in pending debug
8179 * exceptions being set, but that's not correct for the guest debugging
8181 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8182 vmx_set_interrupt_shadow(vcpu, 0);
8184 atomic_switch_perf_msrs(vmx);
8185 debugctlmsr = get_debugctlmsr();
8187 vmx->__launched = vmx->loaded_vmcs->launched;
8189 /* Store host registers */
8190 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8191 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8192 "push %%" _ASM_CX " \n\t"
8193 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8195 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8196 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8198 /* Reload cr2 if changed */
8199 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8200 "mov %%cr2, %%" _ASM_DX " \n\t"
8201 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8203 "mov %%" _ASM_AX", %%cr2 \n\t"
8205 /* Check if vmlaunch of vmresume is needed */
8206 "cmpl $0, %c[launched](%0) \n\t"
8207 /* Load guest registers. Don't clobber flags. */
8208 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8209 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8210 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8211 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8212 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8213 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8214 #ifdef CONFIG_X86_64
8215 "mov %c[r8](%0), %%r8 \n\t"
8216 "mov %c[r9](%0), %%r9 \n\t"
8217 "mov %c[r10](%0), %%r10 \n\t"
8218 "mov %c[r11](%0), %%r11 \n\t"
8219 "mov %c[r12](%0), %%r12 \n\t"
8220 "mov %c[r13](%0), %%r13 \n\t"
8221 "mov %c[r14](%0), %%r14 \n\t"
8222 "mov %c[r15](%0), %%r15 \n\t"
8224 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8226 /* Enter guest mode */
8228 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8230 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8232 /* Save guest registers, load host registers, keep flags */
8233 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8235 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8236 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8237 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8238 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8239 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8240 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8241 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8242 #ifdef CONFIG_X86_64
8243 "mov %%r8, %c[r8](%0) \n\t"
8244 "mov %%r9, %c[r9](%0) \n\t"
8245 "mov %%r10, %c[r10](%0) \n\t"
8246 "mov %%r11, %c[r11](%0) \n\t"
8247 "mov %%r12, %c[r12](%0) \n\t"
8248 "mov %%r13, %c[r13](%0) \n\t"
8249 "mov %%r14, %c[r14](%0) \n\t"
8250 "mov %%r15, %c[r15](%0) \n\t"
8252 "mov %%cr2, %%" _ASM_AX " \n\t"
8253 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8255 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8256 "setbe %c[fail](%0) \n\t"
8257 ".pushsection .rodata \n\t"
8258 ".global vmx_return \n\t"
8259 "vmx_return: " _ASM_PTR " 2b \n\t"
8261 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8262 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8263 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8264 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8265 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8266 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8267 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8268 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8269 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8270 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8271 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8272 #ifdef CONFIG_X86_64
8273 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8274 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8275 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8276 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8277 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8278 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8279 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8280 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8282 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8283 [wordsize]"i"(sizeof(ulong))
8285 #ifdef CONFIG_X86_64
8286 , "rax", "rbx", "rdi", "rsi"
8287 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8289 , "eax", "ebx", "edi", "esi"
8293 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8295 update_debugctlmsr(debugctlmsr);
8297 #ifndef CONFIG_X86_64
8299 * The sysexit path does not restore ds/es, so we must set them to
8300 * a reasonable value ourselves.
8302 * We can't defer this to vmx_load_host_state() since that function
8303 * may be executed in interrupt context, which saves and restore segments
8304 * around it, nullifying its effect.
8306 loadsegment(ds, __USER_DS);
8307 loadsegment(es, __USER_DS);
8310 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8311 | (1 << VCPU_EXREG_RFLAGS)
8312 | (1 << VCPU_EXREG_PDPTR)
8313 | (1 << VCPU_EXREG_SEGMENTS)
8314 | (1 << VCPU_EXREG_CR3));
8315 vcpu->arch.regs_dirty = 0;
8317 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8319 vmx->loaded_vmcs->launched = 1;
8321 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8322 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8325 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8326 * we did not inject a still-pending event to L1 now because of
8327 * nested_run_pending, we need to re-enable this bit.
8329 if (vmx->nested.nested_run_pending)
8330 kvm_make_request(KVM_REQ_EVENT, vcpu);
8332 vmx->nested.nested_run_pending = 0;
8334 vmx_complete_atomic_exit(vmx);
8335 vmx_recover_nmi_blocking(vmx);
8336 vmx_complete_interrupts(vmx);
8339 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8341 struct vcpu_vmx *vmx = to_vmx(vcpu);
8344 if (vmx->loaded_vmcs == &vmx->vmcs01)
8348 vmx->loaded_vmcs = &vmx->vmcs01;
8350 vmx_vcpu_load(vcpu, cpu);
8355 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8357 struct vcpu_vmx *vmx = to_vmx(vcpu);
8360 vmx_disable_pml(vmx);
8362 leave_guest_mode(vcpu);
8363 vmx_load_vmcs01(vcpu);
8365 free_loaded_vmcs(vmx->loaded_vmcs);
8366 kfree(vmx->guest_msrs);
8367 kvm_vcpu_uninit(vcpu);
8368 kmem_cache_free(kvm_vcpu_cache, vmx);
8371 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8374 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8378 return ERR_PTR(-ENOMEM);
8382 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8386 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8387 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8391 if (!vmx->guest_msrs) {
8395 vmx->loaded_vmcs = &vmx->vmcs01;
8396 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8397 if (!vmx->loaded_vmcs->vmcs)
8400 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8401 loaded_vmcs_init(vmx->loaded_vmcs);
8406 vmx_vcpu_load(&vmx->vcpu, cpu);
8407 vmx->vcpu.cpu = cpu;
8408 err = vmx_vcpu_setup(vmx);
8409 vmx_vcpu_put(&vmx->vcpu);
8413 if (vm_need_virtualize_apic_accesses(kvm)) {
8414 err = alloc_apic_access_page(kvm);
8420 if (!kvm->arch.ept_identity_map_addr)
8421 kvm->arch.ept_identity_map_addr =
8422 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8423 err = init_rmode_identity_map(kvm);
8429 nested_vmx_setup_ctls_msrs(vmx);
8431 vmx->nested.posted_intr_nv = -1;
8432 vmx->nested.current_vmptr = -1ull;
8433 vmx->nested.current_vmcs12 = NULL;
8436 * If PML is turned on, failure on enabling PML just results in failure
8437 * of creating the vcpu, therefore we can simplify PML logic (by
8438 * avoiding dealing with cases, such as enabling PML partially on vcpus
8439 * for the guest, etc.
8442 err = vmx_enable_pml(vmx);
8450 free_loaded_vmcs(vmx->loaded_vmcs);
8452 kfree(vmx->guest_msrs);
8454 kvm_vcpu_uninit(&vmx->vcpu);
8457 kmem_cache_free(kvm_vcpu_cache, vmx);
8458 return ERR_PTR(err);
8461 static void __init vmx_check_processor_compat(void *rtn)
8463 struct vmcs_config vmcs_conf;
8466 if (setup_vmcs_config(&vmcs_conf) < 0)
8468 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8469 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8470 smp_processor_id());
8475 static int get_ept_level(void)
8477 return VMX_EPT_DEFAULT_GAW + 1;
8480 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8484 /* For VT-d and EPT combination
8485 * 1. MMIO: always map as UC
8487 * a. VT-d without snooping control feature: can't guarantee the
8488 * result, try to trust guest.
8489 * b. VT-d with snooping control feature: snooping control feature of
8490 * VT-d engine can guarantee the cache correctness. Just set it
8491 * to WB to keep consistent with host. So the same as item 3.
8492 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8493 * consistent with host MTRR
8496 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8497 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8498 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8499 VMX_EPT_MT_EPTE_SHIFT;
8501 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8507 static int vmx_get_lpage_level(void)
8509 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8510 return PT_DIRECTORY_LEVEL;
8512 /* For shadow and EPT supported 1GB page */
8513 return PT_PDPE_LEVEL;
8516 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8518 struct kvm_cpuid_entry2 *best;
8519 struct vcpu_vmx *vmx = to_vmx(vcpu);
8522 vmx->rdtscp_enabled = false;
8523 if (vmx_rdtscp_supported()) {
8524 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8525 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8526 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8527 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8528 vmx->rdtscp_enabled = true;
8530 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8531 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8535 if (nested && !vmx->rdtscp_enabled)
8536 vmx->nested.nested_vmx_secondary_ctls_high &=
8537 ~SECONDARY_EXEC_RDTSCP;
8540 /* Exposing INVPCID only when PCID is exposed */
8541 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8542 if (vmx_invpcid_supported() &&
8543 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8544 guest_cpuid_has_pcid(vcpu)) {
8545 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8546 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8547 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8550 if (cpu_has_secondary_exec_ctrls()) {
8551 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8552 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8553 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8557 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8561 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8563 if (func == 1 && nested)
8564 entry->ecx |= bit(X86_FEATURE_VMX);
8567 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8568 struct x86_exception *fault)
8570 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8573 if (fault->error_code & PFERR_RSVD_MASK)
8574 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8576 exit_reason = EXIT_REASON_EPT_VIOLATION;
8577 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8578 vmcs12->guest_physical_address = fault->address;
8581 /* Callbacks for nested_ept_init_mmu_context: */
8583 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8585 /* return the page table to be shadowed - in our case, EPT12 */
8586 return get_vmcs12(vcpu)->ept_pointer;
8589 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8591 WARN_ON(mmu_is_nested(vcpu));
8592 kvm_init_shadow_ept_mmu(vcpu,
8593 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8594 VMX_EPT_EXECUTE_ONLY_BIT);
8595 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8596 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8597 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8599 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
8602 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8604 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8607 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8610 bool inequality, bit;
8612 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8614 (error_code & vmcs12->page_fault_error_code_mask) !=
8615 vmcs12->page_fault_error_code_match;
8616 return inequality ^ bit;
8619 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8620 struct x86_exception *fault)
8622 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8624 WARN_ON(!is_guest_mode(vcpu));
8626 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8627 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8628 vmcs_read32(VM_EXIT_INTR_INFO),
8629 vmcs_readl(EXIT_QUALIFICATION));
8631 kvm_inject_page_fault(vcpu, fault);
8634 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8635 struct vmcs12 *vmcs12)
8637 struct vcpu_vmx *vmx = to_vmx(vcpu);
8638 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8640 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8641 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8642 vmcs12->apic_access_addr >> maxphyaddr)
8646 * Translate L1 physical address to host physical
8647 * address for vmcs02. Keep the page pinned, so this
8648 * physical address remains valid. We keep a reference
8649 * to it so we can release it later.
8651 if (vmx->nested.apic_access_page) /* shouldn't happen */
8652 nested_release_page(vmx->nested.apic_access_page);
8653 vmx->nested.apic_access_page =
8654 nested_get_page(vcpu, vmcs12->apic_access_addr);
8657 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8658 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8659 vmcs12->virtual_apic_page_addr >> maxphyaddr)
8662 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8663 nested_release_page(vmx->nested.virtual_apic_page);
8664 vmx->nested.virtual_apic_page =
8665 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8668 * Failing the vm entry is _not_ what the processor does
8669 * but it's basically the only possibility we have.
8670 * We could still enter the guest if CR8 load exits are
8671 * enabled, CR8 store exits are enabled, and virtualize APIC
8672 * access is disabled; in this case the processor would never
8673 * use the TPR shadow and we could simply clear the bit from
8674 * the execution control. But such a configuration is useless,
8675 * so let's keep the code simple.
8677 if (!vmx->nested.virtual_apic_page)
8681 if (nested_cpu_has_posted_intr(vmcs12)) {
8682 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8683 vmcs12->posted_intr_desc_addr >> maxphyaddr)
8686 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8687 kunmap(vmx->nested.pi_desc_page);
8688 nested_release_page(vmx->nested.pi_desc_page);
8690 vmx->nested.pi_desc_page =
8691 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8692 if (!vmx->nested.pi_desc_page)
8695 vmx->nested.pi_desc =
8696 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8697 if (!vmx->nested.pi_desc) {
8698 nested_release_page_clean(vmx->nested.pi_desc_page);
8701 vmx->nested.pi_desc =
8702 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8703 (unsigned long)(vmcs12->posted_intr_desc_addr &
8710 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8712 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8713 struct vcpu_vmx *vmx = to_vmx(vcpu);
8715 if (vcpu->arch.virtual_tsc_khz == 0)
8718 /* Make sure short timeouts reliably trigger an immediate vmexit.
8719 * hrtimer_start does not guarantee this. */
8720 if (preemption_timeout <= 1) {
8721 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8725 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8726 preemption_timeout *= 1000000;
8727 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8728 hrtimer_start(&vmx->nested.preemption_timer,
8729 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8732 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8733 struct vmcs12 *vmcs12)
8738 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8741 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8745 maxphyaddr = cpuid_maxphyaddr(vcpu);
8747 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8748 ((addr + PAGE_SIZE) >> maxphyaddr))
8755 * Merge L0's and L1's MSR bitmap, return false to indicate that
8756 * we do not use the hardware.
8758 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8759 struct vmcs12 *vmcs12)
8763 unsigned long *msr_bitmap;
8765 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8768 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8773 msr_bitmap = (unsigned long *)kmap(page);
8775 nested_release_page_clean(page);
8780 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8781 if (nested_cpu_has_apic_reg_virt(vmcs12))
8782 for (msr = 0x800; msr <= 0x8ff; msr++)
8783 nested_vmx_disable_intercept_for_msr(
8785 vmx_msr_bitmap_nested,
8787 /* TPR is allowed */
8788 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8789 vmx_msr_bitmap_nested,
8790 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8791 MSR_TYPE_R | MSR_TYPE_W);
8792 if (nested_cpu_has_vid(vmcs12)) {
8793 /* EOI and self-IPI are allowed */
8794 nested_vmx_disable_intercept_for_msr(
8796 vmx_msr_bitmap_nested,
8797 APIC_BASE_MSR + (APIC_EOI >> 4),
8799 nested_vmx_disable_intercept_for_msr(
8801 vmx_msr_bitmap_nested,
8802 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8807 * Enable reading intercept of all the x2apic
8808 * MSRs. We should not rely on vmcs12 to do any
8809 * optimizations here, it may have been modified
8812 for (msr = 0x800; msr <= 0x8ff; msr++)
8813 __vmx_enable_intercept_for_msr(
8814 vmx_msr_bitmap_nested,
8818 __vmx_enable_intercept_for_msr(
8819 vmx_msr_bitmap_nested,
8820 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8822 __vmx_enable_intercept_for_msr(
8823 vmx_msr_bitmap_nested,
8824 APIC_BASE_MSR + (APIC_EOI >> 4),
8826 __vmx_enable_intercept_for_msr(
8827 vmx_msr_bitmap_nested,
8828 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8832 nested_release_page_clean(page);
8837 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8838 struct vmcs12 *vmcs12)
8840 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8841 !nested_cpu_has_apic_reg_virt(vmcs12) &&
8842 !nested_cpu_has_vid(vmcs12) &&
8843 !nested_cpu_has_posted_intr(vmcs12))
8847 * If virtualize x2apic mode is enabled,
8848 * virtualize apic access must be disabled.
8850 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8851 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8855 * If virtual interrupt delivery is enabled,
8856 * we must exit on external interrupts.
8858 if (nested_cpu_has_vid(vmcs12) &&
8859 !nested_exit_on_intr(vcpu))
8863 * bits 15:8 should be zero in posted_intr_nv,
8864 * the descriptor address has been already checked
8865 * in nested_get_vmcs12_pages.
8867 if (nested_cpu_has_posted_intr(vmcs12) &&
8868 (!nested_cpu_has_vid(vmcs12) ||
8869 !nested_exit_intr_ack_set(vcpu) ||
8870 vmcs12->posted_intr_nv & 0xff00))
8873 /* tpr shadow is needed by all apicv features. */
8874 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8880 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8881 unsigned long count_field,
8882 unsigned long addr_field)
8887 if (vmcs12_read_any(vcpu, count_field, &count) ||
8888 vmcs12_read_any(vcpu, addr_field, &addr)) {
8894 maxphyaddr = cpuid_maxphyaddr(vcpu);
8895 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8896 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8897 pr_warn_ratelimited(
8898 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8899 addr_field, maxphyaddr, count, addr);
8905 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8906 struct vmcs12 *vmcs12)
8908 if (vmcs12->vm_exit_msr_load_count == 0 &&
8909 vmcs12->vm_exit_msr_store_count == 0 &&
8910 vmcs12->vm_entry_msr_load_count == 0)
8911 return 0; /* Fast path */
8912 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8913 VM_EXIT_MSR_LOAD_ADDR) ||
8914 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8915 VM_EXIT_MSR_STORE_ADDR) ||
8916 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8917 VM_ENTRY_MSR_LOAD_ADDR))
8922 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8923 struct vmx_msr_entry *e)
8925 /* x2APIC MSR accesses are not allowed */
8926 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8928 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8929 e->index == MSR_IA32_UCODE_REV)
8931 if (e->reserved != 0)
8936 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8937 struct vmx_msr_entry *e)
8939 if (e->index == MSR_FS_BASE ||
8940 e->index == MSR_GS_BASE ||
8941 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8942 nested_vmx_msr_check_common(vcpu, e))
8947 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8948 struct vmx_msr_entry *e)
8950 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8951 nested_vmx_msr_check_common(vcpu, e))
8957 * Load guest's/host's msr at nested entry/exit.
8958 * return 0 for success, entry index for failure.
8960 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8963 struct vmx_msr_entry e;
8964 struct msr_data msr;
8966 msr.host_initiated = false;
8967 for (i = 0; i < count; i++) {
8968 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8970 pr_warn_ratelimited(
8971 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8972 __func__, i, gpa + i * sizeof(e));
8975 if (nested_vmx_load_msr_check(vcpu, &e)) {
8976 pr_warn_ratelimited(
8977 "%s check failed (%u, 0x%x, 0x%x)\n",
8978 __func__, i, e.index, e.reserved);
8981 msr.index = e.index;
8983 if (kvm_set_msr(vcpu, &msr)) {
8984 pr_warn_ratelimited(
8985 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8986 __func__, i, e.index, e.value);
8995 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8998 struct vmx_msr_entry e;
9000 for (i = 0; i < count; i++) {
9001 if (kvm_read_guest(vcpu->kvm,
9002 gpa + i * sizeof(e),
9003 &e, 2 * sizeof(u32))) {
9004 pr_warn_ratelimited(
9005 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9006 __func__, i, gpa + i * sizeof(e));
9009 if (nested_vmx_store_msr_check(vcpu, &e)) {
9010 pr_warn_ratelimited(
9011 "%s check failed (%u, 0x%x, 0x%x)\n",
9012 __func__, i, e.index, e.reserved);
9015 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9016 pr_warn_ratelimited(
9017 "%s cannot read MSR (%u, 0x%x)\n",
9018 __func__, i, e.index);
9021 if (kvm_write_guest(vcpu->kvm,
9022 gpa + i * sizeof(e) +
9023 offsetof(struct vmx_msr_entry, value),
9024 &e.value, sizeof(e.value))) {
9025 pr_warn_ratelimited(
9026 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9027 __func__, i, e.index, e.value);
9035 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9036 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9037 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9038 * guest in a way that will both be appropriate to L1's requests, and our
9039 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9040 * function also has additional necessary side-effects, like setting various
9041 * vcpu->arch fields.
9043 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9045 struct vcpu_vmx *vmx = to_vmx(vcpu);
9048 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9049 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9050 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9051 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9052 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9053 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9054 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9055 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9056 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9057 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9058 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9059 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9060 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9061 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9062 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9063 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9064 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9065 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9066 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9067 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9068 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9069 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9070 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9071 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9072 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9073 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9074 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9075 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9076 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9077 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9078 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9079 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9080 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9081 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9082 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9083 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9085 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9086 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9087 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9089 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9090 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9092 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9093 vmcs12->vm_entry_intr_info_field);
9094 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9095 vmcs12->vm_entry_exception_error_code);
9096 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9097 vmcs12->vm_entry_instruction_len);
9098 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9099 vmcs12->guest_interruptibility_info);
9100 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9101 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9102 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9103 vmcs12->guest_pending_dbg_exceptions);
9104 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9105 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9107 if (nested_cpu_has_xsaves(vmcs12))
9108 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9109 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9111 exec_control = vmcs12->pin_based_vm_exec_control;
9112 exec_control |= vmcs_config.pin_based_exec_ctrl;
9113 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9115 if (nested_cpu_has_posted_intr(vmcs12)) {
9117 * Note that we use L0's vector here and in
9118 * vmx_deliver_nested_posted_interrupt.
9120 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9121 vmx->nested.pi_pending = false;
9122 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9123 vmcs_write64(POSTED_INTR_DESC_ADDR,
9124 page_to_phys(vmx->nested.pi_desc_page) +
9125 (unsigned long)(vmcs12->posted_intr_desc_addr &
9128 exec_control &= ~PIN_BASED_POSTED_INTR;
9130 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9132 vmx->nested.preemption_timer_expired = false;
9133 if (nested_cpu_has_preemption_timer(vmcs12))
9134 vmx_start_preemption_timer(vcpu);
9137 * Whether page-faults are trapped is determined by a combination of
9138 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9139 * If enable_ept, L0 doesn't care about page faults and we should
9140 * set all of these to L1's desires. However, if !enable_ept, L0 does
9141 * care about (at least some) page faults, and because it is not easy
9142 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9143 * to exit on each and every L2 page fault. This is done by setting
9144 * MASK=MATCH=0 and (see below) EB.PF=1.
9145 * Note that below we don't need special code to set EB.PF beyond the
9146 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9147 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9148 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9150 * A problem with this approach (when !enable_ept) is that L1 may be
9151 * injected with more page faults than it asked for. This could have
9152 * caused problems, but in practice existing hypervisors don't care.
9153 * To fix this, we will need to emulate the PFEC checking (on the L1
9154 * page tables), using walk_addr(), when injecting PFs to L1.
9156 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9157 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9158 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9159 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9161 if (cpu_has_secondary_exec_ctrls()) {
9162 exec_control = vmx_secondary_exec_control(vmx);
9163 if (!vmx->rdtscp_enabled)
9164 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9165 /* Take the following fields only from vmcs12 */
9166 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9167 SECONDARY_EXEC_RDTSCP |
9168 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9169 SECONDARY_EXEC_APIC_REGISTER_VIRT);
9170 if (nested_cpu_has(vmcs12,
9171 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9172 exec_control |= vmcs12->secondary_vm_exec_control;
9174 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9176 * If translation failed, no matter: This feature asks
9177 * to exit when accessing the given address, and if it
9178 * can never be accessed, this feature won't do
9181 if (!vmx->nested.apic_access_page)
9183 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9185 vmcs_write64(APIC_ACCESS_ADDR,
9186 page_to_phys(vmx->nested.apic_access_page));
9187 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9188 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9190 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9191 kvm_vcpu_reload_apic_access_page(vcpu);
9194 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9195 vmcs_write64(EOI_EXIT_BITMAP0,
9196 vmcs12->eoi_exit_bitmap0);
9197 vmcs_write64(EOI_EXIT_BITMAP1,
9198 vmcs12->eoi_exit_bitmap1);
9199 vmcs_write64(EOI_EXIT_BITMAP2,
9200 vmcs12->eoi_exit_bitmap2);
9201 vmcs_write64(EOI_EXIT_BITMAP3,
9202 vmcs12->eoi_exit_bitmap3);
9203 vmcs_write16(GUEST_INTR_STATUS,
9204 vmcs12->guest_intr_status);
9207 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9212 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9213 * Some constant fields are set here by vmx_set_constant_host_state().
9214 * Other fields are different per CPU, and will be set later when
9215 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9217 vmx_set_constant_host_state(vmx);
9220 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9221 * entry, but only if the current (host) sp changed from the value
9222 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9223 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9224 * here we just force the write to happen on entry.
9228 exec_control = vmx_exec_control(vmx); /* L0's desires */
9229 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9230 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9231 exec_control &= ~CPU_BASED_TPR_SHADOW;
9232 exec_control |= vmcs12->cpu_based_vm_exec_control;
9234 if (exec_control & CPU_BASED_TPR_SHADOW) {
9235 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9236 page_to_phys(vmx->nested.virtual_apic_page));
9237 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9240 if (cpu_has_vmx_msr_bitmap() &&
9241 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9242 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9243 /* MSR_BITMAP will be set by following vmx_set_efer. */
9245 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9248 * Merging of IO bitmap not currently supported.
9249 * Rather, exit every time.
9251 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9252 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9254 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9256 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9257 * bitwise-or of what L1 wants to trap for L2, and what we want to
9258 * trap. Note that CR0.TS also needs updating - we do this later.
9260 update_exception_bitmap(vcpu);
9261 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9262 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9264 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9265 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9266 * bits are further modified by vmx_set_efer() below.
9268 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9270 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9271 * emulated by vmx_set_efer(), below.
9273 vm_entry_controls_init(vmx,
9274 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9275 ~VM_ENTRY_IA32E_MODE) |
9276 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9278 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9279 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9280 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9281 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9282 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9285 set_cr4_guest_host_mask(vmx);
9287 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9288 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9290 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9291 vmcs_write64(TSC_OFFSET,
9292 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9294 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9298 * Trivially support vpid by letting L2s share their parent
9299 * L1's vpid. TODO: move to a more elaborate solution, giving
9300 * each L2 its own vpid and exposing the vpid feature to L1.
9302 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9303 vmx_flush_tlb(vcpu);
9306 if (nested_cpu_has_ept(vmcs12)) {
9307 kvm_mmu_unload(vcpu);
9308 nested_ept_init_mmu_context(vcpu);
9311 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9312 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9313 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9314 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9316 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9317 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9318 vmx_set_efer(vcpu, vcpu->arch.efer);
9321 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9322 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9323 * The CR0_READ_SHADOW is what L2 should have expected to read given
9324 * the specifications by L1; It's not enough to take
9325 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9326 * have more bits than L1 expected.
9328 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9329 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9331 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9332 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9334 /* shadow page tables on either EPT or shadow page tables */
9335 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9336 kvm_mmu_reset_context(vcpu);
9339 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9342 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9345 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9346 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9347 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9348 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9351 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9352 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9356 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9357 * for running an L2 nested guest.
9359 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9361 struct vmcs12 *vmcs12;
9362 struct vcpu_vmx *vmx = to_vmx(vcpu);
9364 struct loaded_vmcs *vmcs02;
9368 if (!nested_vmx_check_permission(vcpu) ||
9369 !nested_vmx_check_vmcs12(vcpu))
9372 skip_emulated_instruction(vcpu);
9373 vmcs12 = get_vmcs12(vcpu);
9375 if (enable_shadow_vmcs)
9376 copy_shadow_to_vmcs12(vmx);
9379 * The nested entry process starts with enforcing various prerequisites
9380 * on vmcs12 as required by the Intel SDM, and act appropriately when
9381 * they fail: As the SDM explains, some conditions should cause the
9382 * instruction to fail, while others will cause the instruction to seem
9383 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9384 * To speed up the normal (success) code path, we should avoid checking
9385 * for misconfigurations which will anyway be caught by the processor
9386 * when using the merged vmcs02.
9388 if (vmcs12->launch_state == launch) {
9389 nested_vmx_failValid(vcpu,
9390 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9391 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9395 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9396 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9397 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9401 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9402 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9406 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9407 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9411 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9412 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9416 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9417 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9421 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9422 vmx->nested.nested_vmx_true_procbased_ctls_low,
9423 vmx->nested.nested_vmx_procbased_ctls_high) ||
9424 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9425 vmx->nested.nested_vmx_secondary_ctls_low,
9426 vmx->nested.nested_vmx_secondary_ctls_high) ||
9427 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9428 vmx->nested.nested_vmx_pinbased_ctls_low,
9429 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9430 !vmx_control_verify(vmcs12->vm_exit_controls,
9431 vmx->nested.nested_vmx_true_exit_ctls_low,
9432 vmx->nested.nested_vmx_exit_ctls_high) ||
9433 !vmx_control_verify(vmcs12->vm_entry_controls,
9434 vmx->nested.nested_vmx_true_entry_ctls_low,
9435 vmx->nested.nested_vmx_entry_ctls_high))
9437 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9441 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9442 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9443 nested_vmx_failValid(vcpu,
9444 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9448 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9449 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9450 nested_vmx_entry_failure(vcpu, vmcs12,
9451 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9454 if (vmcs12->vmcs_link_pointer != -1ull) {
9455 nested_vmx_entry_failure(vcpu, vmcs12,
9456 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9461 * If the load IA32_EFER VM-entry control is 1, the following checks
9462 * are performed on the field for the IA32_EFER MSR:
9463 * - Bits reserved in the IA32_EFER MSR must be 0.
9464 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9465 * the IA-32e mode guest VM-exit control. It must also be identical
9466 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9469 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9470 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9471 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9472 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9473 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9474 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9475 nested_vmx_entry_failure(vcpu, vmcs12,
9476 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9482 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9483 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9484 * the values of the LMA and LME bits in the field must each be that of
9485 * the host address-space size VM-exit control.
9487 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9488 ia32e = (vmcs12->vm_exit_controls &
9489 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9490 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9491 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9492 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9493 nested_vmx_entry_failure(vcpu, vmcs12,
9494 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9500 * We're finally done with prerequisite checking, and can start with
9504 vmcs02 = nested_get_current_vmcs02(vmx);
9508 enter_guest_mode(vcpu);
9510 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9512 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9513 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9516 vmx->loaded_vmcs = vmcs02;
9518 vmx_vcpu_load(vcpu, cpu);
9522 vmx_segment_cache_clear(vmx);
9524 prepare_vmcs02(vcpu, vmcs12);
9526 msr_entry_idx = nested_vmx_load_msr(vcpu,
9527 vmcs12->vm_entry_msr_load_addr,
9528 vmcs12->vm_entry_msr_load_count);
9529 if (msr_entry_idx) {
9530 leave_guest_mode(vcpu);
9531 vmx_load_vmcs01(vcpu);
9532 nested_vmx_entry_failure(vcpu, vmcs12,
9533 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9537 vmcs12->launch_state = 1;
9539 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9540 return kvm_vcpu_halt(vcpu);
9542 vmx->nested.nested_run_pending = 1;
9545 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9546 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9547 * returned as far as L1 is concerned. It will only return (and set
9548 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9554 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9555 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9556 * This function returns the new value we should put in vmcs12.guest_cr0.
9557 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9558 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9559 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9560 * didn't trap the bit, because if L1 did, so would L0).
9561 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9562 * been modified by L2, and L1 knows it. So just leave the old value of
9563 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9564 * isn't relevant, because if L0 traps this bit it can set it to anything.
9565 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9566 * changed these bits, and therefore they need to be updated, but L0
9567 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9568 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9570 static inline unsigned long
9571 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9574 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9575 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9576 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9577 vcpu->arch.cr0_guest_owned_bits));
9580 static inline unsigned long
9581 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9584 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9585 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9586 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9587 vcpu->arch.cr4_guest_owned_bits));
9590 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9591 struct vmcs12 *vmcs12)
9596 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9597 nr = vcpu->arch.exception.nr;
9598 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9600 if (kvm_exception_is_soft(nr)) {
9601 vmcs12->vm_exit_instruction_len =
9602 vcpu->arch.event_exit_inst_len;
9603 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9605 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9607 if (vcpu->arch.exception.has_error_code) {
9608 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9609 vmcs12->idt_vectoring_error_code =
9610 vcpu->arch.exception.error_code;
9613 vmcs12->idt_vectoring_info_field = idt_vectoring;
9614 } else if (vcpu->arch.nmi_injected) {
9615 vmcs12->idt_vectoring_info_field =
9616 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9617 } else if (vcpu->arch.interrupt.pending) {
9618 nr = vcpu->arch.interrupt.nr;
9619 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9621 if (vcpu->arch.interrupt.soft) {
9622 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9623 vmcs12->vm_entry_instruction_len =
9624 vcpu->arch.event_exit_inst_len;
9626 idt_vectoring |= INTR_TYPE_EXT_INTR;
9628 vmcs12->idt_vectoring_info_field = idt_vectoring;
9632 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9634 struct vcpu_vmx *vmx = to_vmx(vcpu);
9636 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9637 vmx->nested.preemption_timer_expired) {
9638 if (vmx->nested.nested_run_pending)
9640 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9644 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9645 if (vmx->nested.nested_run_pending ||
9646 vcpu->arch.interrupt.pending)
9648 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9649 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9650 INTR_INFO_VALID_MASK, 0);
9652 * The NMI-triggered VM exit counts as injection:
9653 * clear this one and block further NMIs.
9655 vcpu->arch.nmi_pending = 0;
9656 vmx_set_nmi_mask(vcpu, true);
9660 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9661 nested_exit_on_intr(vcpu)) {
9662 if (vmx->nested.nested_run_pending)
9664 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9668 return vmx_complete_nested_posted_interrupt(vcpu);
9671 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9674 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9677 if (ktime_to_ns(remaining) <= 0)
9680 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9681 do_div(value, 1000000);
9682 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9686 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9687 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9688 * and this function updates it to reflect the changes to the guest state while
9689 * L2 was running (and perhaps made some exits which were handled directly by L0
9690 * without going back to L1), and to reflect the exit reason.
9691 * Note that we do not have to copy here all VMCS fields, just those that
9692 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9693 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9694 * which already writes to vmcs12 directly.
9696 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9697 u32 exit_reason, u32 exit_intr_info,
9698 unsigned long exit_qualification)
9700 /* update guest state fields: */
9701 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9702 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9704 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9705 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9706 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9708 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9709 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9710 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9711 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9712 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9713 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9714 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9715 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9716 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9717 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9718 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9719 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9720 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9721 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9722 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9723 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9724 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9725 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9726 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9727 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9728 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9729 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9730 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9731 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9732 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9733 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9734 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9735 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9736 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9737 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9738 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9739 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9740 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9741 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9742 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9743 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9745 vmcs12->guest_interruptibility_info =
9746 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9747 vmcs12->guest_pending_dbg_exceptions =
9748 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9749 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9750 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9752 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9754 if (nested_cpu_has_preemption_timer(vmcs12)) {
9755 if (vmcs12->vm_exit_controls &
9756 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9757 vmcs12->vmx_preemption_timer_value =
9758 vmx_get_preemption_timer_value(vcpu);
9759 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9763 * In some cases (usually, nested EPT), L2 is allowed to change its
9764 * own CR3 without exiting. If it has changed it, we must keep it.
9765 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9766 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9768 * Additionally, restore L2's PDPTR to vmcs12.
9771 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9772 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9773 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9774 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9775 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9778 if (nested_cpu_has_vid(vmcs12))
9779 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9781 vmcs12->vm_entry_controls =
9782 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9783 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9785 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9786 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9787 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9790 /* TODO: These cannot have changed unless we have MSR bitmaps and
9791 * the relevant bit asks not to trap the change */
9792 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9793 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9794 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9795 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9796 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9797 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9798 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9799 if (vmx_mpx_supported())
9800 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9801 if (nested_cpu_has_xsaves(vmcs12))
9802 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9804 /* update exit information fields: */
9806 vmcs12->vm_exit_reason = exit_reason;
9807 vmcs12->exit_qualification = exit_qualification;
9809 vmcs12->vm_exit_intr_info = exit_intr_info;
9810 if ((vmcs12->vm_exit_intr_info &
9811 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9812 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9813 vmcs12->vm_exit_intr_error_code =
9814 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9815 vmcs12->idt_vectoring_info_field = 0;
9816 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9817 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9819 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9820 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9821 * instead of reading the real value. */
9822 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9825 * Transfer the event that L0 or L1 may wanted to inject into
9826 * L2 to IDT_VECTORING_INFO_FIELD.
9828 vmcs12_save_pending_event(vcpu, vmcs12);
9832 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9833 * preserved above and would only end up incorrectly in L1.
9835 vcpu->arch.nmi_injected = false;
9836 kvm_clear_exception_queue(vcpu);
9837 kvm_clear_interrupt_queue(vcpu);
9841 * A part of what we need to when the nested L2 guest exits and we want to
9842 * run its L1 parent, is to reset L1's guest state to the host state specified
9844 * This function is to be called not only on normal nested exit, but also on
9845 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9846 * Failures During or After Loading Guest State").
9847 * This function should be called when the active VMCS is L1's (vmcs01).
9849 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9850 struct vmcs12 *vmcs12)
9852 struct kvm_segment seg;
9854 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9855 vcpu->arch.efer = vmcs12->host_ia32_efer;
9856 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9857 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9859 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9860 vmx_set_efer(vcpu, vcpu->arch.efer);
9862 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9863 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9864 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9866 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9867 * actually changed, because it depends on the current state of
9868 * fpu_active (which may have changed).
9869 * Note that vmx_set_cr0 refers to efer set above.
9871 vmx_set_cr0(vcpu, vmcs12->host_cr0);
9873 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9874 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9875 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9877 update_exception_bitmap(vcpu);
9878 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9879 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9882 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9883 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9885 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9886 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9888 nested_ept_uninit_mmu_context(vcpu);
9890 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9891 kvm_mmu_reset_context(vcpu);
9894 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9898 * Trivially support vpid by letting L2s share their parent
9899 * L1's vpid. TODO: move to a more elaborate solution, giving
9900 * each L2 its own vpid and exposing the vpid feature to L1.
9902 vmx_flush_tlb(vcpu);
9906 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9907 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9908 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9909 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9910 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9912 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9913 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9914 vmcs_write64(GUEST_BNDCFGS, 0);
9916 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9917 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9918 vcpu->arch.pat = vmcs12->host_ia32_pat;
9920 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9921 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9922 vmcs12->host_ia32_perf_global_ctrl);
9924 /* Set L1 segment info according to Intel SDM
9925 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9926 seg = (struct kvm_segment) {
9928 .limit = 0xFFFFFFFF,
9929 .selector = vmcs12->host_cs_selector,
9935 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9939 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9940 seg = (struct kvm_segment) {
9942 .limit = 0xFFFFFFFF,
9949 seg.selector = vmcs12->host_ds_selector;
9950 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9951 seg.selector = vmcs12->host_es_selector;
9952 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9953 seg.selector = vmcs12->host_ss_selector;
9954 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9955 seg.selector = vmcs12->host_fs_selector;
9956 seg.base = vmcs12->host_fs_base;
9957 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9958 seg.selector = vmcs12->host_gs_selector;
9959 seg.base = vmcs12->host_gs_base;
9960 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9961 seg = (struct kvm_segment) {
9962 .base = vmcs12->host_tr_base,
9964 .selector = vmcs12->host_tr_selector,
9968 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9970 kvm_set_dr(vcpu, 7, 0x400);
9971 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9973 if (cpu_has_vmx_msr_bitmap())
9974 vmx_set_msr_bitmap(vcpu);
9976 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9977 vmcs12->vm_exit_msr_load_count))
9978 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9982 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9983 * and modify vmcs12 to make it see what it would expect to see there if
9984 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9986 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9988 unsigned long exit_qualification)
9990 struct vcpu_vmx *vmx = to_vmx(vcpu);
9991 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9993 /* trying to cancel vmlaunch/vmresume is a bug */
9994 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9996 leave_guest_mode(vcpu);
9997 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9998 exit_qualification);
10000 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10001 vmcs12->vm_exit_msr_store_count))
10002 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10004 vmx_load_vmcs01(vcpu);
10006 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10007 && nested_exit_intr_ack_set(vcpu)) {
10008 int irq = kvm_cpu_get_interrupt(vcpu);
10010 vmcs12->vm_exit_intr_info = irq |
10011 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10014 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10015 vmcs12->exit_qualification,
10016 vmcs12->idt_vectoring_info_field,
10017 vmcs12->vm_exit_intr_info,
10018 vmcs12->vm_exit_intr_error_code,
10021 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10022 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10023 vmx_segment_cache_clear(vmx);
10025 /* if no vmcs02 cache requested, remove the one we used */
10026 if (VMCS02_POOL_SIZE == 0)
10027 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10029 load_vmcs12_host_state(vcpu, vmcs12);
10031 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10032 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10034 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10037 /* Unpin physical memory we referred to in vmcs02 */
10038 if (vmx->nested.apic_access_page) {
10039 nested_release_page(vmx->nested.apic_access_page);
10040 vmx->nested.apic_access_page = NULL;
10042 if (vmx->nested.virtual_apic_page) {
10043 nested_release_page(vmx->nested.virtual_apic_page);
10044 vmx->nested.virtual_apic_page = NULL;
10046 if (vmx->nested.pi_desc_page) {
10047 kunmap(vmx->nested.pi_desc_page);
10048 nested_release_page(vmx->nested.pi_desc_page);
10049 vmx->nested.pi_desc_page = NULL;
10050 vmx->nested.pi_desc = NULL;
10054 * We are now running in L2, mmu_notifier will force to reload the
10055 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10057 kvm_vcpu_reload_apic_access_page(vcpu);
10060 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10061 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10062 * success or failure flag accordingly.
10064 if (unlikely(vmx->fail)) {
10066 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10068 nested_vmx_succeed(vcpu);
10069 if (enable_shadow_vmcs)
10070 vmx->nested.sync_shadow_vmcs = true;
10072 /* in case we halted in L2 */
10073 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10077 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10079 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10081 if (is_guest_mode(vcpu))
10082 nested_vmx_vmexit(vcpu, -1, 0, 0);
10083 free_nested(to_vmx(vcpu));
10087 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10088 * 23.7 "VM-entry failures during or after loading guest state" (this also
10089 * lists the acceptable exit-reason and exit-qualification parameters).
10090 * It should only be called before L2 actually succeeded to run, and when
10091 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10093 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10094 struct vmcs12 *vmcs12,
10095 u32 reason, unsigned long qualification)
10097 load_vmcs12_host_state(vcpu, vmcs12);
10098 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10099 vmcs12->exit_qualification = qualification;
10100 nested_vmx_succeed(vcpu);
10101 if (enable_shadow_vmcs)
10102 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10105 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10106 struct x86_instruction_info *info,
10107 enum x86_intercept_stage stage)
10109 return X86EMUL_CONTINUE;
10112 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10115 shrink_ple_window(vcpu);
10118 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10119 struct kvm_memory_slot *slot)
10121 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10122 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10125 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10126 struct kvm_memory_slot *slot)
10128 kvm_mmu_slot_set_dirty(kvm, slot);
10131 static void vmx_flush_log_dirty(struct kvm *kvm)
10133 kvm_flush_pml_buffers(kvm);
10136 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10137 struct kvm_memory_slot *memslot,
10138 gfn_t offset, unsigned long mask)
10140 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10143 static struct kvm_x86_ops vmx_x86_ops = {
10144 .cpu_has_kvm_support = cpu_has_kvm_support,
10145 .disabled_by_bios = vmx_disabled_by_bios,
10146 .hardware_setup = hardware_setup,
10147 .hardware_unsetup = hardware_unsetup,
10148 .check_processor_compatibility = vmx_check_processor_compat,
10149 .hardware_enable = hardware_enable,
10150 .hardware_disable = hardware_disable,
10151 .cpu_has_accelerated_tpr = report_flexpriority,
10153 .vcpu_create = vmx_create_vcpu,
10154 .vcpu_free = vmx_free_vcpu,
10155 .vcpu_reset = vmx_vcpu_reset,
10157 .prepare_guest_switch = vmx_save_host_state,
10158 .vcpu_load = vmx_vcpu_load,
10159 .vcpu_put = vmx_vcpu_put,
10161 .update_db_bp_intercept = update_exception_bitmap,
10162 .get_msr = vmx_get_msr,
10163 .set_msr = vmx_set_msr,
10164 .get_segment_base = vmx_get_segment_base,
10165 .get_segment = vmx_get_segment,
10166 .set_segment = vmx_set_segment,
10167 .get_cpl = vmx_get_cpl,
10168 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10169 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10170 .decache_cr3 = vmx_decache_cr3,
10171 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10172 .set_cr0 = vmx_set_cr0,
10173 .set_cr3 = vmx_set_cr3,
10174 .set_cr4 = vmx_set_cr4,
10175 .set_efer = vmx_set_efer,
10176 .get_idt = vmx_get_idt,
10177 .set_idt = vmx_set_idt,
10178 .get_gdt = vmx_get_gdt,
10179 .set_gdt = vmx_set_gdt,
10180 .get_dr6 = vmx_get_dr6,
10181 .set_dr6 = vmx_set_dr6,
10182 .set_dr7 = vmx_set_dr7,
10183 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10184 .cache_reg = vmx_cache_reg,
10185 .get_rflags = vmx_get_rflags,
10186 .set_rflags = vmx_set_rflags,
10187 .fpu_activate = vmx_fpu_activate,
10188 .fpu_deactivate = vmx_fpu_deactivate,
10190 .tlb_flush = vmx_flush_tlb,
10192 .run = vmx_vcpu_run,
10193 .handle_exit = vmx_handle_exit,
10194 .skip_emulated_instruction = skip_emulated_instruction,
10195 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10196 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10197 .patch_hypercall = vmx_patch_hypercall,
10198 .set_irq = vmx_inject_irq,
10199 .set_nmi = vmx_inject_nmi,
10200 .queue_exception = vmx_queue_exception,
10201 .cancel_injection = vmx_cancel_injection,
10202 .interrupt_allowed = vmx_interrupt_allowed,
10203 .nmi_allowed = vmx_nmi_allowed,
10204 .get_nmi_mask = vmx_get_nmi_mask,
10205 .set_nmi_mask = vmx_set_nmi_mask,
10206 .enable_nmi_window = enable_nmi_window,
10207 .enable_irq_window = enable_irq_window,
10208 .update_cr8_intercept = update_cr8_intercept,
10209 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10210 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10211 .vm_has_apicv = vmx_vm_has_apicv,
10212 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10213 .hwapic_irr_update = vmx_hwapic_irr_update,
10214 .hwapic_isr_update = vmx_hwapic_isr_update,
10215 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10216 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10218 .set_tss_addr = vmx_set_tss_addr,
10219 .get_tdp_level = get_ept_level,
10220 .get_mt_mask = vmx_get_mt_mask,
10222 .get_exit_info = vmx_get_exit_info,
10224 .get_lpage_level = vmx_get_lpage_level,
10226 .cpuid_update = vmx_cpuid_update,
10228 .rdtscp_supported = vmx_rdtscp_supported,
10229 .invpcid_supported = vmx_invpcid_supported,
10231 .set_supported_cpuid = vmx_set_supported_cpuid,
10233 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10235 .set_tsc_khz = vmx_set_tsc_khz,
10236 .read_tsc_offset = vmx_read_tsc_offset,
10237 .write_tsc_offset = vmx_write_tsc_offset,
10238 .adjust_tsc_offset = vmx_adjust_tsc_offset,
10239 .compute_tsc_offset = vmx_compute_tsc_offset,
10240 .read_l1_tsc = vmx_read_l1_tsc,
10242 .set_tdp_cr3 = vmx_set_cr3,
10244 .check_intercept = vmx_check_intercept,
10245 .handle_external_intr = vmx_handle_external_intr,
10246 .mpx_supported = vmx_mpx_supported,
10247 .xsaves_supported = vmx_xsaves_supported,
10249 .check_nested_events = vmx_check_nested_events,
10251 .sched_in = vmx_sched_in,
10253 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10254 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10255 .flush_log_dirty = vmx_flush_log_dirty,
10256 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10259 static int __init vmx_init(void)
10261 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10262 __alignof__(struct vcpu_vmx), THIS_MODULE);
10266 #ifdef CONFIG_KEXEC
10267 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10268 crash_vmclear_local_loaded_vmcss);
10274 static void __exit vmx_exit(void)
10276 #ifdef CONFIG_KEXEC
10277 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10284 module_init(vmx_init)
10285 module_exit(vmx_exit)