arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/fpu/internal.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/debugreg.h>
  46 #include <asm/kexec.h>
  47 #include <asm/apic.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 static u64 __read_mostly host_xss;
 103
 104 static bool __read_mostly enable_pml = 1;
 105 module_param_named(pml, enable_pml, bool, S_IRUGO);
 106
 107 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 108 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 109 #define KVM_VM_CR0_ALWAYS_ON                                            \
 110         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 111 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 112         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 113          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 114
 115 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 116 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 117
 118 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 119
 120 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 121
 122 /*
 123  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 124  * ple_gap:    upper bound on the amount of time between two successive
 125  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 126  *             According to test, this time is usually smaller than 128 cycles.
 127  * ple_window: upper bound on the amount of time a guest is allowed to execute
 128  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 129  *             less than 2^12 cycles
 130  * Time is measured based on a counter that runs at the same rate as the TSC,
 131  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 132  */
 133 #define KVM_VMX_DEFAULT_PLE_GAP           128
 134 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 135 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 136 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 137 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 138                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 139
 140 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 141 module_param(ple_gap, int, S_IRUGO);
 142
 143 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 144 module_param(ple_window, int, S_IRUGO);
 145
 146 /* Default doubles per-vcpu window every exit. */
 147 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 148 module_param(ple_window_grow, int, S_IRUGO);
 149
 150 /* Default resets per-vcpu window every exit to ple_window. */
 151 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 152 module_param(ple_window_shrink, int, S_IRUGO);
 153
 154 /* Default is to compute the maximum so we can never overflow. */
 155 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 156 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 157 module_param(ple_window_max, int, S_IRUGO);
 158
 159 extern const ulong vmx_return;
 160
 161 #define NR_AUTOLOAD_MSRS 8
 162 #define VMCS02_POOL_SIZE 1
 163
 164 struct vmcs {
 165         u32 revision_id;
 166         u32 abort;
 167         char data[0];
 168 };
 169
 170 /*
 171  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 172  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 173  * loaded on this CPU (so we can clear them if the CPU goes down).
 174  */
 175 struct loaded_vmcs {
 176         struct vmcs *vmcs;
 177         int cpu;
 178         int launched;
 179         struct list_head loaded_vmcss_on_cpu_link;
 180 };
 181
 182 struct shared_msr_entry {
 183         unsigned index;
 184         u64 data;
 185         u64 mask;
 186 };
 187
 188 /*
 189  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 190  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 191  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 192  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 193  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 194  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 195  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 196  * underlying hardware which will be used to run L2.
 197  * This structure is packed to ensure that its layout is identical across
 198  * machines (necessary for live migration).
 199  * If there are changes in this struct, VMCS12_REVISION must be changed.
 200  */
 201 typedef u64 natural_width;
 202 struct __packed vmcs12 {
 203         /* According to the Intel spec, a VMCS region must start with the
 204          * following two fields. Then follow implementation-specific data.
 205          */
 206         u32 revision_id;
 207         u32 abort;
 208
 209         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 210         u32 padding[7]; /* room for future expansion */
 211
 212         u64 io_bitmap_a;
 213         u64 io_bitmap_b;
 214         u64 msr_bitmap;
 215         u64 vm_exit_msr_store_addr;
 216         u64 vm_exit_msr_load_addr;
 217         u64 vm_entry_msr_load_addr;
 218         u64 tsc_offset;
 219         u64 virtual_apic_page_addr;
 220         u64 apic_access_addr;
 221         u64 posted_intr_desc_addr;
 222         u64 ept_pointer;
 223         u64 eoi_exit_bitmap0;
 224         u64 eoi_exit_bitmap1;
 225         u64 eoi_exit_bitmap2;
 226         u64 eoi_exit_bitmap3;
 227         u64 xss_exit_bitmap;
 228         u64 guest_physical_address;
 229         u64 vmcs_link_pointer;
 230         u64 guest_ia32_debugctl;
 231         u64 guest_ia32_pat;
 232         u64 guest_ia32_efer;
 233         u64 guest_ia32_perf_global_ctrl;
 234         u64 guest_pdptr0;
 235         u64 guest_pdptr1;
 236         u64 guest_pdptr2;
 237         u64 guest_pdptr3;
 238         u64 guest_bndcfgs;
 239         u64 host_ia32_pat;
 240         u64 host_ia32_efer;
 241         u64 host_ia32_perf_global_ctrl;
 242         u64 padding64[8]; /* room for future expansion */
 243         /*
 244          * To allow migration of L1 (complete with its L2 guests) between
 245          * machines of different natural widths (32 or 64 bit), we cannot have
 246          * unsigned long fields with no explict size. We use u64 (aliased
 247          * natural_width) instead. Luckily, x86 is little-endian.
 248          */
 249         natural_width cr0_guest_host_mask;
 250         natural_width cr4_guest_host_mask;
 251         natural_width cr0_read_shadow;
 252         natural_width cr4_read_shadow;
 253         natural_width cr3_target_value0;
 254         natural_width cr3_target_value1;
 255         natural_width cr3_target_value2;
 256         natural_width cr3_target_value3;
 257         natural_width exit_qualification;
 258         natural_width guest_linear_address;
 259         natural_width guest_cr0;
 260         natural_width guest_cr3;
 261         natural_width guest_cr4;
 262         natural_width guest_es_base;
 263         natural_width guest_cs_base;
 264         natural_width guest_ss_base;
 265         natural_width guest_ds_base;
 266         natural_width guest_fs_base;
 267         natural_width guest_gs_base;
 268         natural_width guest_ldtr_base;
 269         natural_width guest_tr_base;
 270         natural_width guest_gdtr_base;
 271         natural_width guest_idtr_base;
 272         natural_width guest_dr7;
 273         natural_width guest_rsp;
 274         natural_width guest_rip;
 275         natural_width guest_rflags;
 276         natural_width guest_pending_dbg_exceptions;
 277         natural_width guest_sysenter_esp;
 278         natural_width guest_sysenter_eip;
 279         natural_width host_cr0;
 280         natural_width host_cr3;
 281         natural_width host_cr4;
 282         natural_width host_fs_base;
 283         natural_width host_gs_base;
 284         natural_width host_tr_base;
 285         natural_width host_gdtr_base;
 286         natural_width host_idtr_base;
 287         natural_width host_ia32_sysenter_esp;
 288         natural_width host_ia32_sysenter_eip;
 289         natural_width host_rsp;
 290         natural_width host_rip;
 291         natural_width paddingl[8]; /* room for future expansion */
 292         u32 pin_based_vm_exec_control;
 293         u32 cpu_based_vm_exec_control;
 294         u32 exception_bitmap;
 295         u32 page_fault_error_code_mask;
 296         u32 page_fault_error_code_match;
 297         u32 cr3_target_count;
 298         u32 vm_exit_controls;
 299         u32 vm_exit_msr_store_count;
 300         u32 vm_exit_msr_load_count;
 301         u32 vm_entry_controls;
 302         u32 vm_entry_msr_load_count;
 303         u32 vm_entry_intr_info_field;
 304         u32 vm_entry_exception_error_code;
 305         u32 vm_entry_instruction_len;
 306         u32 tpr_threshold;
 307         u32 secondary_vm_exec_control;
 308         u32 vm_instruction_error;
 309         u32 vm_exit_reason;
 310         u32 vm_exit_intr_info;
 311         u32 vm_exit_intr_error_code;
 312         u32 idt_vectoring_info_field;
 313         u32 idt_vectoring_error_code;
 314         u32 vm_exit_instruction_len;
 315         u32 vmx_instruction_info;
 316         u32 guest_es_limit;
 317         u32 guest_cs_limit;
 318         u32 guest_ss_limit;
 319         u32 guest_ds_limit;
 320         u32 guest_fs_limit;
 321         u32 guest_gs_limit;
 322         u32 guest_ldtr_limit;
 323         u32 guest_tr_limit;
 324         u32 guest_gdtr_limit;
 325         u32 guest_idtr_limit;
 326         u32 guest_es_ar_bytes;
 327         u32 guest_cs_ar_bytes;
 328         u32 guest_ss_ar_bytes;
 329         u32 guest_ds_ar_bytes;
 330         u32 guest_fs_ar_bytes;
 331         u32 guest_gs_ar_bytes;
 332         u32 guest_ldtr_ar_bytes;
 333         u32 guest_tr_ar_bytes;
 334         u32 guest_interruptibility_info;
 335         u32 guest_activity_state;
 336         u32 guest_sysenter_cs;
 337         u32 host_ia32_sysenter_cs;
 338         u32 vmx_preemption_timer_value;
 339         u32 padding32[7]; /* room for future expansion */
 340         u16 virtual_processor_id;
 341         u16 posted_intr_nv;
 342         u16 guest_es_selector;
 343         u16 guest_cs_selector;
 344         u16 guest_ss_selector;
 345         u16 guest_ds_selector;
 346         u16 guest_fs_selector;
 347         u16 guest_gs_selector;
 348         u16 guest_ldtr_selector;
 349         u16 guest_tr_selector;
 350         u16 guest_intr_status;
 351         u16 host_es_selector;
 352         u16 host_cs_selector;
 353         u16 host_ss_selector;
 354         u16 host_ds_selector;
 355         u16 host_fs_selector;
 356         u16 host_gs_selector;
 357         u16 host_tr_selector;
 358 };
 359
 360 /*
 361  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 362  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 363  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 364  */
 365 #define VMCS12_REVISION 0x11e57ed0
 366
 367 /*
 368  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 369  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 370  * current implementation, 4K are reserved to avoid future complications.
 371  */
 372 #define VMCS12_SIZE 0x1000
 373
 374 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 375 struct vmcs02_list {
 376         struct list_head list;
 377         gpa_t vmptr;
 378         struct loaded_vmcs vmcs02;
 379 };
 380
 381 /*
 382  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 383  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 384  */
 385 struct nested_vmx {
 386         /* Has the level1 guest done vmxon? */
 387         bool vmxon;
 388         gpa_t vmxon_ptr;
 389
 390         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 391         gpa_t current_vmptr;
 392         /* The host-usable pointer to the above */
 393         struct page *current_vmcs12_page;
 394         struct vmcs12 *current_vmcs12;
 395         struct vmcs *current_shadow_vmcs;
 396         /*
 397          * Indicates if the shadow vmcs must be updated with the
 398          * data hold by vmcs12
 399          */
 400         bool sync_shadow_vmcs;
 401
 402         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 403         struct list_head vmcs02_pool;
 404         int vmcs02_num;
 405         u64 vmcs01_tsc_offset;
 406         /* L2 must run next, and mustn't decide to exit to L1. */
 407         bool nested_run_pending;
 408         /*
 409          * Guest pages referred to in vmcs02 with host-physical pointers, so
 410          * we must keep them pinned while L2 runs.
 411          */
 412         struct page *apic_access_page;
 413         struct page *virtual_apic_page;
 414         struct page *pi_desc_page;
 415         struct pi_desc *pi_desc;
 416         bool pi_pending;
 417         u16 posted_intr_nv;
 418         u64 msr_ia32_feature_control;
 419
 420         struct hrtimer preemption_timer;
 421         bool preemption_timer_expired;
 422
 423         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 424         u64 vmcs01_debugctl;
 425
 426         u32 nested_vmx_procbased_ctls_low;
 427         u32 nested_vmx_procbased_ctls_high;
 428         u32 nested_vmx_true_procbased_ctls_low;
 429         u32 nested_vmx_secondary_ctls_low;
 430         u32 nested_vmx_secondary_ctls_high;
 431         u32 nested_vmx_pinbased_ctls_low;
 432         u32 nested_vmx_pinbased_ctls_high;
 433         u32 nested_vmx_exit_ctls_low;
 434         u32 nested_vmx_exit_ctls_high;
 435         u32 nested_vmx_true_exit_ctls_low;
 436         u32 nested_vmx_entry_ctls_low;
 437         u32 nested_vmx_entry_ctls_high;
 438         u32 nested_vmx_true_entry_ctls_low;
 439         u32 nested_vmx_misc_low;
 440         u32 nested_vmx_misc_high;
 441         u32 nested_vmx_ept_caps;
 442 };
 443
 444 #define POSTED_INTR_ON  0
 445 /* Posted-Interrupt Descriptor */
 446 struct pi_desc {
 447         u32 pir[8];     /* Posted interrupt requested */
 448         u32 control;    /* bit 0 of control is outstanding notification bit */
 449         u32 rsvd[7];
 450 } __aligned(64);
 451
 452 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 453 {
 454         return test_and_set_bit(POSTED_INTR_ON,
 455                         (unsigned long *)&pi_desc->control);
 456 }
 457
 458 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 459 {
 460         return test_and_clear_bit(POSTED_INTR_ON,
 461                         (unsigned long *)&pi_desc->control);
 462 }
 463
 464 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 465 {
 466         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 467 }
 468
 469 struct vcpu_vmx {
 470         struct kvm_vcpu       vcpu;
 471         unsigned long         host_rsp;
 472         u8                    fail;
 473         bool                  nmi_known_unmasked;
 474         u32                   exit_intr_info;
 475         u32                   idt_vectoring_info;
 476         ulong                 rflags;
 477         struct shared_msr_entry *guest_msrs;
 478         int                   nmsrs;
 479         int                   save_nmsrs;
 480         unsigned long         host_idt_base;
 481 #ifdef CONFIG_X86_64
 482         u64                   msr_host_kernel_gs_base;
 483         u64                   msr_guest_kernel_gs_base;
 484 #endif
 485         u32 vm_entry_controls_shadow;
 486         u32 vm_exit_controls_shadow;
 487         /*
 488          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 489          * non-nested (L1) guest, it always points to vmcs01. For a nested
 490          * guest (L2), it points to a different VMCS.
 491          */
 492         struct loaded_vmcs    vmcs01;
 493         struct loaded_vmcs   *loaded_vmcs;
 494         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 495         struct msr_autoload {
 496                 unsigned nr;
 497                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 498                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 499         } msr_autoload;
 500         struct {
 501                 int           loaded;
 502                 u16           fs_sel, gs_sel, ldt_sel;
 503 #ifdef CONFIG_X86_64
 504                 u16           ds_sel, es_sel;
 505 #endif
 506                 int           gs_ldt_reload_needed;
 507                 int           fs_reload_needed;
 508                 u64           msr_host_bndcfgs;
 509                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 510         } host_state;
 511         struct {
 512                 int vm86_active;
 513                 ulong save_rflags;
 514                 struct kvm_segment segs[8];
 515         } rmode;
 516         struct {
 517                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 518                 struct kvm_save_segment {
 519                         u16 selector;
 520                         unsigned long base;
 521                         u32 limit;
 522                         u32 ar;
 523                 } seg[8];
 524         } segment_cache;
 525         int vpid;
 526         bool emulation_required;
 527
 528         /* Support for vnmi-less CPUs */
 529         int soft_vnmi_blocked;
 530         ktime_t entry_time;
 531         s64 vnmi_blocked_time;
 532         u32 exit_reason;
 533
 534         bool rdtscp_enabled;
 535
 536         /* Posted interrupt descriptor */
 537         struct pi_desc pi_desc;
 538
 539         /* Support for a guest hypervisor (nested VMX) */
 540         struct nested_vmx nested;
 541
 542         /* Dynamic PLE window. */
 543         int ple_window;
 544         bool ple_window_dirty;
 545
 546         /* Support for PML */
 547 #define PML_ENTITY_NUM          512
 548         struct page *pml_pg;
 549 };
 550
 551 enum segment_cache_field {
 552         SEG_FIELD_SEL = 0,
 553         SEG_FIELD_BASE = 1,
 554         SEG_FIELD_LIMIT = 2,
 555         SEG_FIELD_AR = 3,
 556
 557         SEG_FIELD_NR = 4
 558 };
 559
 560 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 561 {
 562         return container_of(vcpu, struct vcpu_vmx, vcpu);
 563 }
 564
 565 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 566 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 567 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 568                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 569
 570
 571 static unsigned long shadow_read_only_fields[] = {
 572         /*
 573          * We do NOT shadow fields that are modified when L0
 574          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 575          * VMXON...) executed by L1.
 576          * For example, VM_INSTRUCTION_ERROR is read
 577          * by L1 if a vmx instruction fails (part of the error path).
 578          * Note the code assumes this logic. If for some reason
 579          * we start shadowing these fields then we need to
 580          * force a shadow sync when L0 emulates vmx instructions
 581          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 582          * by nested_vmx_failValid)
 583          */
 584         VM_EXIT_REASON,
 585         VM_EXIT_INTR_INFO,
 586         VM_EXIT_INSTRUCTION_LEN,
 587         IDT_VECTORING_INFO_FIELD,
 588         IDT_VECTORING_ERROR_CODE,
 589         VM_EXIT_INTR_ERROR_CODE,
 590         EXIT_QUALIFICATION,
 591         GUEST_LINEAR_ADDRESS,
 592         GUEST_PHYSICAL_ADDRESS
 593 };
 594 static int max_shadow_read_only_fields =
 595         ARRAY_SIZE(shadow_read_only_fields);
 596
 597 static unsigned long shadow_read_write_fields[] = {
 598         TPR_THRESHOLD,
 599         GUEST_RIP,
 600         GUEST_RSP,
 601         GUEST_CR0,
 602         GUEST_CR3,
 603         GUEST_CR4,
 604         GUEST_INTERRUPTIBILITY_INFO,
 605         GUEST_RFLAGS,
 606         GUEST_CS_SELECTOR,
 607         GUEST_CS_AR_BYTES,
 608         GUEST_CS_LIMIT,
 609         GUEST_CS_BASE,
 610         GUEST_ES_BASE,
 611         GUEST_BNDCFGS,
 612         CR0_GUEST_HOST_MASK,
 613         CR0_READ_SHADOW,
 614         CR4_READ_SHADOW,
 615         TSC_OFFSET,
 616         EXCEPTION_BITMAP,
 617         CPU_BASED_VM_EXEC_CONTROL,
 618         VM_ENTRY_EXCEPTION_ERROR_CODE,
 619         VM_ENTRY_INTR_INFO_FIELD,
 620         VM_ENTRY_INSTRUCTION_LEN,
 621         VM_ENTRY_EXCEPTION_ERROR_CODE,
 622         HOST_FS_BASE,
 623         HOST_GS_BASE,
 624         HOST_FS_SELECTOR,
 625         HOST_GS_SELECTOR
 626 };
 627 static int max_shadow_read_write_fields =
 628         ARRAY_SIZE(shadow_read_write_fields);
 629
 630 static const unsigned short vmcs_field_to_offset_table[] = {
 631         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 632         FIELD(POSTED_INTR_NV, posted_intr_nv),
 633         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 634         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 635         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 636         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 637         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 638         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 639         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 640         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 641         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 642         FIELD(HOST_ES_SELECTOR, host_es_selector),
 643         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 644         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 645         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 646         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 647         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 648         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 649         FIELD64(IO_BITMAP_A, io_bitmap_a),
 650         FIELD64(IO_BITMAP_B, io_bitmap_b),
 651         FIELD64(MSR_BITMAP, msr_bitmap),
 652         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 653         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 654         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 655         FIELD64(TSC_OFFSET, tsc_offset),
 656         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 657         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 658         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 659         FIELD64(EPT_POINTER, ept_pointer),
 660         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 661         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 662         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 663         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 664         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 665         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 666         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 667         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 668         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 669         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 670         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 671         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 672         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 673         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 674         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 675         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 676         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 677         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 678         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 679         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 680         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 681         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 682         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 683         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 684         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 685         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 686         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 687         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 688         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 689         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 690         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 691         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 692         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 693         FIELD(TPR_THRESHOLD, tpr_threshold),
 694         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 695         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 696         FIELD(VM_EXIT_REASON, vm_exit_reason),
 697         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 698         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 699         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 700         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 701         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 702         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 703         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 704         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 705         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 706         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 707         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 708         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 709         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 710         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 711         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 712         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 713         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 714         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 715         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 716         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 717         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 718         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 719         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 720         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 721         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 722         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 723         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 724         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 725         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 726         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 727         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 728         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 729         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 730         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 731         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 732         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 733         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 734         FIELD(EXIT_QUALIFICATION, exit_qualification),
 735         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 736         FIELD(GUEST_CR0, guest_cr0),
 737         FIELD(GUEST_CR3, guest_cr3),
 738         FIELD(GUEST_CR4, guest_cr4),
 739         FIELD(GUEST_ES_BASE, guest_es_base),
 740         FIELD(GUEST_CS_BASE, guest_cs_base),
 741         FIELD(GUEST_SS_BASE, guest_ss_base),
 742         FIELD(GUEST_DS_BASE, guest_ds_base),
 743         FIELD(GUEST_FS_BASE, guest_fs_base),
 744         FIELD(GUEST_GS_BASE, guest_gs_base),
 745         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 746         FIELD(GUEST_TR_BASE, guest_tr_base),
 747         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 748         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 749         FIELD(GUEST_DR7, guest_dr7),
 750         FIELD(GUEST_RSP, guest_rsp),
 751         FIELD(GUEST_RIP, guest_rip),
 752         FIELD(GUEST_RFLAGS, guest_rflags),
 753         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 754         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 755         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 756         FIELD(HOST_CR0, host_cr0),
 757         FIELD(HOST_CR3, host_cr3),
 758         FIELD(HOST_CR4, host_cr4),
 759         FIELD(HOST_FS_BASE, host_fs_base),
 760         FIELD(HOST_GS_BASE, host_gs_base),
 761         FIELD(HOST_TR_BASE, host_tr_base),
 762         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 763         FIELD(HOST_IDTR_BASE, host_idtr_base),
 764         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 765         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 766         FIELD(HOST_RSP, host_rsp),
 767         FIELD(HOST_RIP, host_rip),
 768 };
 769
 770 static inline short vmcs_field_to_offset(unsigned long field)
 771 {
 772         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 773
 774         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 775             vmcs_field_to_offset_table[field] == 0)
 776                 return -ENOENT;
 777
 778         return vmcs_field_to_offset_table[field];
 779 }
 780
 781 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 782 {
 783         return to_vmx(vcpu)->nested.current_vmcs12;
 784 }
 785
 786 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 787 {
 788         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 789         if (is_error_page(page))
 790                 return NULL;
 791
 792         return page;
 793 }
 794
 795 static void nested_release_page(struct page *page)
 796 {
 797         kvm_release_page_dirty(page);
 798 }
 799
 800 static void nested_release_page_clean(struct page *page)
 801 {
 802         kvm_release_page_clean(page);
 803 }
 804
 805 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 806 static u64 construct_eptp(unsigned long root_hpa);
 807 static void kvm_cpu_vmxon(u64 addr);
 808 static void kvm_cpu_vmxoff(void);
 809 static bool vmx_mpx_supported(void);
 810 static bool vmx_xsaves_supported(void);
 811 static int vmx_vm_has_apicv(struct kvm *kvm);
 812 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 813 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 814                             struct kvm_segment *var, int seg);
 815 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 816                             struct kvm_segment *var, int seg);
 817 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 818 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 819 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 820 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 821 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 822 static int alloc_identity_pagetable(struct kvm *kvm);
 823
 824 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 825 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 826 /*
 827  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 828  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 829  */
 830 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 831 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 832
 833 static unsigned long *vmx_io_bitmap_a;
 834 static unsigned long *vmx_io_bitmap_b;
 835 static unsigned long *vmx_msr_bitmap_legacy;
 836 static unsigned long *vmx_msr_bitmap_longmode;
 837 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 838 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 839 static unsigned long *vmx_msr_bitmap_nested;
 840 static unsigned long *vmx_vmread_bitmap;
 841 static unsigned long *vmx_vmwrite_bitmap;
 842
 843 static bool cpu_has_load_ia32_efer;
 844 static bool cpu_has_load_perf_global_ctrl;
 845
 846 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 847 static DEFINE_SPINLOCK(vmx_vpid_lock);
 848
 849 static struct vmcs_config {
 850         int size;
 851         int order;
 852         u32 revision_id;
 853         u32 pin_based_exec_ctrl;
 854         u32 cpu_based_exec_ctrl;
 855         u32 cpu_based_2nd_exec_ctrl;
 856         u32 vmexit_ctrl;
 857         u32 vmentry_ctrl;
 858 } vmcs_config;
 859
 860 static struct vmx_capability {
 861         u32 ept;
 862         u32 vpid;
 863 } vmx_capability;
 864
 865 #define VMX_SEGMENT_FIELD(seg)                                  \
 866         [VCPU_SREG_##seg] = {                                   \
 867                 .selector = GUEST_##seg##_SELECTOR,             \
 868                 .base = GUEST_##seg##_BASE,                     \
 869                 .limit = GUEST_##seg##_LIMIT,                   \
 870                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 871         }
 872
 873 static const struct kvm_vmx_segment_field {
 874         unsigned selector;
 875         unsigned base;
 876         unsigned limit;
 877         unsigned ar_bytes;
 878 } kvm_vmx_segment_fields[] = {
 879         VMX_SEGMENT_FIELD(CS),
 880         VMX_SEGMENT_FIELD(DS),
 881         VMX_SEGMENT_FIELD(ES),
 882         VMX_SEGMENT_FIELD(FS),
 883         VMX_SEGMENT_FIELD(GS),
 884         VMX_SEGMENT_FIELD(SS),
 885         VMX_SEGMENT_FIELD(TR),
 886         VMX_SEGMENT_FIELD(LDTR),
 887 };
 888
 889 static u64 host_efer;
 890
 891 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 892
 893 /*
 894  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 895  * away by decrementing the array size.
 896  */
 897 static const u32 vmx_msr_index[] = {
 898 #ifdef CONFIG_X86_64
 899         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 900 #endif
 901         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 902 };
 903
 904 static inline bool is_page_fault(u32 intr_info)
 905 {
 906         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 907                              INTR_INFO_VALID_MASK)) ==
 908                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 909 }
 910
 911 static inline bool is_no_device(u32 intr_info)
 912 {
 913         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 914                              INTR_INFO_VALID_MASK)) ==
 915                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 916 }
 917
 918 static inline bool is_invalid_opcode(u32 intr_info)
 919 {
 920         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 921                              INTR_INFO_VALID_MASK)) ==
 922                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 923 }
 924
 925 static inline bool is_external_interrupt(u32 intr_info)
 926 {
 927         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 928                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 929 }
 930
 931 static inline bool is_machine_check(u32 intr_info)
 932 {
 933         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 934                              INTR_INFO_VALID_MASK)) ==
 935                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 936 }
 937
 938 static inline bool cpu_has_vmx_msr_bitmap(void)
 939 {
 940         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 941 }
 942
 943 static inline bool cpu_has_vmx_tpr_shadow(void)
 944 {
 945         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 946 }
 947
 948 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 949 {
 950         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 951 }
 952
 953 static inline bool cpu_has_secondary_exec_ctrls(void)
 954 {
 955         return vmcs_config.cpu_based_exec_ctrl &
 956                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 957 }
 958
 959 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 960 {
 961         return vmcs_config.cpu_based_2nd_exec_ctrl &
 962                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 963 }
 964
 965 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 966 {
 967         return vmcs_config.cpu_based_2nd_exec_ctrl &
 968                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 969 }
 970
 971 static inline bool cpu_has_vmx_apic_register_virt(void)
 972 {
 973         return vmcs_config.cpu_based_2nd_exec_ctrl &
 974                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 975 }
 976
 977 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 981 }
 982
 983 static inline bool cpu_has_vmx_posted_intr(void)
 984 {
 985         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 986 }
 987
 988 static inline bool cpu_has_vmx_apicv(void)
 989 {
 990         return cpu_has_vmx_apic_register_virt() &&
 991                 cpu_has_vmx_virtual_intr_delivery() &&
 992                 cpu_has_vmx_posted_intr();
 993 }
 994
 995 static inline bool cpu_has_vmx_flexpriority(void)
 996 {
 997         return cpu_has_vmx_tpr_shadow() &&
 998                 cpu_has_vmx_virtualize_apic_accesses();
 999 }
1000
1001 static inline bool cpu_has_vmx_ept_execute_only(void)
1002 {
1003         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1004 }
1005
1006 static inline bool cpu_has_vmx_ept_2m_page(void)
1007 {
1008         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1009 }
1010
1011 static inline bool cpu_has_vmx_ept_1g_page(void)
1012 {
1013         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1014 }
1015
1016 static inline bool cpu_has_vmx_ept_4levels(void)
1017 {
1018         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1019 }
1020
1021 static inline bool cpu_has_vmx_ept_ad_bits(void)
1022 {
1023         return vmx_capability.ept & VMX_EPT_AD_BIT;
1024 }
1025
1026 static inline bool cpu_has_vmx_invept_context(void)
1027 {
1028         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1029 }
1030
1031 static inline bool cpu_has_vmx_invept_global(void)
1032 {
1033         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1034 }
1035
1036 static inline bool cpu_has_vmx_invvpid_single(void)
1037 {
1038         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1039 }
1040
1041 static inline bool cpu_has_vmx_invvpid_global(void)
1042 {
1043         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1044 }
1045
1046 static inline bool cpu_has_vmx_ept(void)
1047 {
1048         return vmcs_config.cpu_based_2nd_exec_ctrl &
1049                 SECONDARY_EXEC_ENABLE_EPT;
1050 }
1051
1052 static inline bool cpu_has_vmx_unrestricted_guest(void)
1053 {
1054         return vmcs_config.cpu_based_2nd_exec_ctrl &
1055                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1056 }
1057
1058 static inline bool cpu_has_vmx_ple(void)
1059 {
1060         return vmcs_config.cpu_based_2nd_exec_ctrl &
1061                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1062 }
1063
1064 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1065 {
1066         return flexpriority_enabled && irqchip_in_kernel(kvm);
1067 }
1068
1069 static inline bool cpu_has_vmx_vpid(void)
1070 {
1071         return vmcs_config.cpu_based_2nd_exec_ctrl &
1072                 SECONDARY_EXEC_ENABLE_VPID;
1073 }
1074
1075 static inline bool cpu_has_vmx_rdtscp(void)
1076 {
1077         return vmcs_config.cpu_based_2nd_exec_ctrl &
1078                 SECONDARY_EXEC_RDTSCP;
1079 }
1080
1081 static inline bool cpu_has_vmx_invpcid(void)
1082 {
1083         return vmcs_config.cpu_based_2nd_exec_ctrl &
1084                 SECONDARY_EXEC_ENABLE_INVPCID;
1085 }
1086
1087 static inline bool cpu_has_virtual_nmis(void)
1088 {
1089         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1090 }
1091
1092 static inline bool cpu_has_vmx_wbinvd_exit(void)
1093 {
1094         return vmcs_config.cpu_based_2nd_exec_ctrl &
1095                 SECONDARY_EXEC_WBINVD_EXITING;
1096 }
1097
1098 static inline bool cpu_has_vmx_shadow_vmcs(void)
1099 {
1100         u64 vmx_msr;
1101         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1102         /* check if the cpu supports writing r/o exit information fields */
1103         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1104                 return false;
1105
1106         return vmcs_config.cpu_based_2nd_exec_ctrl &
1107                 SECONDARY_EXEC_SHADOW_VMCS;
1108 }
1109
1110 static inline bool cpu_has_vmx_pml(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1113 }
1114
1115 static inline bool report_flexpriority(void)
1116 {
1117         return flexpriority_enabled;
1118 }
1119
1120 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1121 {
1122         return vmcs12->cpu_based_vm_exec_control & bit;
1123 }
1124
1125 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1126 {
1127         return (vmcs12->cpu_based_vm_exec_control &
1128                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1129                 (vmcs12->secondary_vm_exec_control & bit);
1130 }
1131
1132 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1133 {
1134         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1135 }
1136
1137 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1138 {
1139         return vmcs12->pin_based_vm_exec_control &
1140                 PIN_BASED_VMX_PREEMPTION_TIMER;
1141 }
1142
1143 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1144 {
1145         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1146 }
1147
1148 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1149 {
1150         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1151                 vmx_xsaves_supported();
1152 }
1153
1154 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1155 {
1156         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1157 }
1158
1159 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1160 {
1161         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1162 }
1163
1164 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1165 {
1166         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1167 }
1168
1169 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1170 {
1171         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1172 }
1173
1174 static inline bool is_exception(u32 intr_info)
1175 {
1176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1177                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1178 }
1179
1180 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1181                               u32 exit_intr_info,
1182                               unsigned long exit_qualification);
1183 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1184                         struct vmcs12 *vmcs12,
1185                         u32 reason, unsigned long qualification);
1186
1187 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1188 {
1189         int i;
1190
1191         for (i = 0; i < vmx->nmsrs; ++i)
1192                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1193                         return i;
1194         return -1;
1195 }
1196
1197 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1198 {
1199     struct {
1200         u64 vpid : 16;
1201         u64 rsvd : 48;
1202         u64 gva;
1203     } operand = { vpid, 0, gva };
1204
1205     asm volatile (__ex(ASM_VMX_INVVPID)
1206                   /* CF==1 or ZF==1 --> rc = -1 */
1207                   "; ja 1f ; ud2 ; 1:"
1208                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1209 }
1210
1211 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1212 {
1213         struct {
1214                 u64 eptp, gpa;
1215         } operand = {eptp, gpa};
1216
1217         asm volatile (__ex(ASM_VMX_INVEPT)
1218                         /* CF==1 or ZF==1 --> rc = -1 */
1219                         "; ja 1f ; ud2 ; 1:\n"
1220                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1221 }
1222
1223 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1224 {
1225         int i;
1226
1227         i = __find_msr_index(vmx, msr);
1228         if (i >= 0)
1229                 return &vmx->guest_msrs[i];
1230         return NULL;
1231 }
1232
1233 static void vmcs_clear(struct vmcs *vmcs)
1234 {
1235         u64 phys_addr = __pa(vmcs);
1236         u8 error;
1237
1238         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1239                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1240                       : "cc", "memory");
1241         if (error)
1242                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1243                        vmcs, phys_addr);
1244 }
1245
1246 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1247 {
1248         vmcs_clear(loaded_vmcs->vmcs);
1249         loaded_vmcs->cpu = -1;
1250         loaded_vmcs->launched = 0;
1251 }
1252
1253 static void vmcs_load(struct vmcs *vmcs)
1254 {
1255         u64 phys_addr = __pa(vmcs);
1256         u8 error;
1257
1258         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1259                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1260                         : "cc", "memory");
1261         if (error)
1262                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1263                        vmcs, phys_addr);
1264 }
1265
1266 #ifdef CONFIG_KEXEC
1267 /*
1268  * This bitmap is used to indicate whether the vmclear
1269  * operation is enabled on all cpus. All disabled by
1270  * default.
1271  */
1272 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1273
1274 static inline void crash_enable_local_vmclear(int cpu)
1275 {
1276         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1277 }
1278
1279 static inline void crash_disable_local_vmclear(int cpu)
1280 {
1281         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1282 }
1283
1284 static inline int crash_local_vmclear_enabled(int cpu)
1285 {
1286         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1287 }
1288
1289 static void crash_vmclear_local_loaded_vmcss(void)
1290 {
1291         int cpu = raw_smp_processor_id();
1292         struct loaded_vmcs *v;
1293
1294         if (!crash_local_vmclear_enabled(cpu))
1295                 return;
1296
1297         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1298                             loaded_vmcss_on_cpu_link)
1299                 vmcs_clear(v->vmcs);
1300 }
1301 #else
1302 static inline void crash_enable_local_vmclear(int cpu) { }
1303 static inline void crash_disable_local_vmclear(int cpu) { }
1304 #endif /* CONFIG_KEXEC */
1305
1306 static void __loaded_vmcs_clear(void *arg)
1307 {
1308         struct loaded_vmcs *loaded_vmcs = arg;
1309         int cpu = raw_smp_processor_id();
1310
1311         if (loaded_vmcs->cpu != cpu)
1312                 return; /* vcpu migration can race with cpu offline */
1313         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1314                 per_cpu(current_vmcs, cpu) = NULL;
1315         crash_disable_local_vmclear(cpu);
1316         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1317
1318         /*
1319          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1320          * is before setting loaded_vmcs->vcpu to -1 which is done in
1321          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1322          * then adds the vmcs into percpu list before it is deleted.
1323          */
1324         smp_wmb();
1325
1326         loaded_vmcs_init(loaded_vmcs);
1327         crash_enable_local_vmclear(cpu);
1328 }
1329
1330 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1331 {
1332         int cpu = loaded_vmcs->cpu;
1333
1334         if (cpu != -1)
1335                 smp_call_function_single(cpu,
1336                          __loaded_vmcs_clear, loaded_vmcs, 1);
1337 }
1338
1339 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1340 {
1341         if (vmx->vpid == 0)
1342                 return;
1343
1344         if (cpu_has_vmx_invvpid_single())
1345                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1346 }
1347
1348 static inline void vpid_sync_vcpu_global(void)
1349 {
1350         if (cpu_has_vmx_invvpid_global())
1351                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1352 }
1353
1354 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1355 {
1356         if (cpu_has_vmx_invvpid_single())
1357                 vpid_sync_vcpu_single(vmx);
1358         else
1359                 vpid_sync_vcpu_global();
1360 }
1361
1362 static inline void ept_sync_global(void)
1363 {
1364         if (cpu_has_vmx_invept_global())
1365                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1366 }
1367
1368 static inline void ept_sync_context(u64 eptp)
1369 {
1370         if (enable_ept) {
1371                 if (cpu_has_vmx_invept_context())
1372                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1373                 else
1374                         ept_sync_global();
1375         }
1376 }
1377
1378 static __always_inline unsigned long vmcs_readl(unsigned long field)
1379 {
1380         unsigned long value;
1381
1382         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1383                       : "=a"(value) : "d"(field) : "cc");
1384         return value;
1385 }
1386
1387 static __always_inline u16 vmcs_read16(unsigned long field)
1388 {
1389         return vmcs_readl(field);
1390 }
1391
1392 static __always_inline u32 vmcs_read32(unsigned long field)
1393 {
1394         return vmcs_readl(field);
1395 }
1396
1397 static __always_inline u64 vmcs_read64(unsigned long field)
1398 {
1399 #ifdef CONFIG_X86_64
1400         return vmcs_readl(field);
1401 #else
1402         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1403 #endif
1404 }
1405
1406 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1407 {
1408         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1409                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1410         dump_stack();
1411 }
1412
1413 static void vmcs_writel(unsigned long field, unsigned long value)
1414 {
1415         u8 error;
1416
1417         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1418                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1419         if (unlikely(error))
1420                 vmwrite_error(field, value);
1421 }
1422
1423 static void vmcs_write16(unsigned long field, u16 value)
1424 {
1425         vmcs_writel(field, value);
1426 }
1427
1428 static void vmcs_write32(unsigned long field, u32 value)
1429 {
1430         vmcs_writel(field, value);
1431 }
1432
1433 static void vmcs_write64(unsigned long field, u64 value)
1434 {
1435         vmcs_writel(field, value);
1436 #ifndef CONFIG_X86_64
1437         asm volatile ("");
1438         vmcs_writel(field+1, value >> 32);
1439 #endif
1440 }
1441
1442 static void vmcs_clear_bits(unsigned long field, u32 mask)
1443 {
1444         vmcs_writel(field, vmcs_readl(field) & ~mask);
1445 }
1446
1447 static void vmcs_set_bits(unsigned long field, u32 mask)
1448 {
1449         vmcs_writel(field, vmcs_readl(field) | mask);
1450 }
1451
1452 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1453 {
1454         vmcs_write32(VM_ENTRY_CONTROLS, val);
1455         vmx->vm_entry_controls_shadow = val;
1456 }
1457
1458 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1459 {
1460         if (vmx->vm_entry_controls_shadow != val)
1461                 vm_entry_controls_init(vmx, val);
1462 }
1463
1464 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1465 {
1466         return vmx->vm_entry_controls_shadow;
1467 }
1468
1469
1470 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1471 {
1472         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1473 }
1474
1475 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1476 {
1477         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1478 }
1479
1480 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1481 {
1482         vmcs_write32(VM_EXIT_CONTROLS, val);
1483         vmx->vm_exit_controls_shadow = val;
1484 }
1485
1486 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1487 {
1488         if (vmx->vm_exit_controls_shadow != val)
1489                 vm_exit_controls_init(vmx, val);
1490 }
1491
1492 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1493 {
1494         return vmx->vm_exit_controls_shadow;
1495 }
1496
1497
1498 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1499 {
1500         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1501 }
1502
1503 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1504 {
1505         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1506 }
1507
1508 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1509 {
1510         vmx->segment_cache.bitmask = 0;
1511 }
1512
1513 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1514                                        unsigned field)
1515 {
1516         bool ret;
1517         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1518
1519         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1520                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1521                 vmx->segment_cache.bitmask = 0;
1522         }
1523         ret = vmx->segment_cache.bitmask & mask;
1524         vmx->segment_cache.bitmask |= mask;
1525         return ret;
1526 }
1527
1528 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1529 {
1530         u16 *p = &vmx->segment_cache.seg[seg].selector;
1531
1532         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1533                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1534         return *p;
1535 }
1536
1537 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1538 {
1539         ulong *p = &vmx->segment_cache.seg[seg].base;
1540
1541         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1542                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1543         return *p;
1544 }
1545
1546 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1547 {
1548         u32 *p = &vmx->segment_cache.seg[seg].limit;
1549
1550         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1551                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1552         return *p;
1553 }
1554
1555 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1556 {
1557         u32 *p = &vmx->segment_cache.seg[seg].ar;
1558
1559         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1560                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1561         return *p;
1562 }
1563
1564 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1565 {
1566         u32 eb;
1567
1568         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1569              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1570         if ((vcpu->guest_debug &
1571              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1572             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1573                 eb |= 1u << BP_VECTOR;
1574         if (to_vmx(vcpu)->rmode.vm86_active)
1575                 eb = ~0;
1576         if (enable_ept)
1577                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1578         if (vcpu->fpu_active)
1579                 eb &= ~(1u << NM_VECTOR);
1580
1581         /* When we are running a nested L2 guest and L1 specified for it a
1582          * certain exception bitmap, we must trap the same exceptions and pass
1583          * them to L1. When running L2, we will only handle the exceptions
1584          * specified above if L1 did not want them.
1585          */
1586         if (is_guest_mode(vcpu))
1587                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1588
1589         vmcs_write32(EXCEPTION_BITMAP, eb);
1590 }
1591
1592 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1593                 unsigned long entry, unsigned long exit)
1594 {
1595         vm_entry_controls_clearbit(vmx, entry);
1596         vm_exit_controls_clearbit(vmx, exit);
1597 }
1598
1599 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1600 {
1601         unsigned i;
1602         struct msr_autoload *m = &vmx->msr_autoload;
1603
1604         switch (msr) {
1605         case MSR_EFER:
1606                 if (cpu_has_load_ia32_efer) {
1607                         clear_atomic_switch_msr_special(vmx,
1608                                         VM_ENTRY_LOAD_IA32_EFER,
1609                                         VM_EXIT_LOAD_IA32_EFER);
1610                         return;
1611                 }
1612                 break;
1613         case MSR_CORE_PERF_GLOBAL_CTRL:
1614                 if (cpu_has_load_perf_global_ctrl) {
1615                         clear_atomic_switch_msr_special(vmx,
1616                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1617                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1618                         return;
1619                 }
1620                 break;
1621         }
1622
1623         for (i = 0; i < m->nr; ++i)
1624                 if (m->guest[i].index == msr)
1625                         break;
1626
1627         if (i == m->nr)
1628                 return;
1629         --m->nr;
1630         m->guest[i] = m->guest[m->nr];
1631         m->host[i] = m->host[m->nr];
1632         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1633         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1634 }
1635
1636 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1637                 unsigned long entry, unsigned long exit,
1638                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1639                 u64 guest_val, u64 host_val)
1640 {
1641         vmcs_write64(guest_val_vmcs, guest_val);
1642         vmcs_write64(host_val_vmcs, host_val);
1643         vm_entry_controls_setbit(vmx, entry);
1644         vm_exit_controls_setbit(vmx, exit);
1645 }
1646
1647 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1648                                   u64 guest_val, u64 host_val)
1649 {
1650         unsigned i;
1651         struct msr_autoload *m = &vmx->msr_autoload;
1652
1653         switch (msr) {
1654         case MSR_EFER:
1655                 if (cpu_has_load_ia32_efer) {
1656                         add_atomic_switch_msr_special(vmx,
1657                                         VM_ENTRY_LOAD_IA32_EFER,
1658                                         VM_EXIT_LOAD_IA32_EFER,
1659                                         GUEST_IA32_EFER,
1660                                         HOST_IA32_EFER,
1661                                         guest_val, host_val);
1662                         return;
1663                 }
1664                 break;
1665         case MSR_CORE_PERF_GLOBAL_CTRL:
1666                 if (cpu_has_load_perf_global_ctrl) {
1667                         add_atomic_switch_msr_special(vmx,
1668                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1669                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1671                                         HOST_IA32_PERF_GLOBAL_CTRL,
1672                                         guest_val, host_val);
1673                         return;
1674                 }
1675                 break;
1676         }
1677
1678         for (i = 0; i < m->nr; ++i)
1679                 if (m->guest[i].index == msr)
1680                         break;
1681
1682         if (i == NR_AUTOLOAD_MSRS) {
1683                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1684                                 "Can't add msr %x\n", msr);
1685                 return;
1686         } else if (i == m->nr) {
1687                 ++m->nr;
1688                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1689                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1690         }
1691
1692         m->guest[i].index = msr;
1693         m->guest[i].value = guest_val;
1694         m->host[i].index = msr;
1695         m->host[i].value = host_val;
1696 }
1697
1698 static void reload_tss(void)
1699 {
1700         /*
1701          * VT restores TR but not its size.  Useless.
1702          */
1703         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1704         struct desc_struct *descs;
1705
1706         descs = (void *)gdt->address;
1707         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1708         load_TR_desc();
1709 }
1710
1711 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1712 {
1713         u64 guest_efer;
1714         u64 ignore_bits;
1715
1716         guest_efer = vmx->vcpu.arch.efer;
1717
1718         /*
1719          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1720          * outside long mode
1721          */
1722         ignore_bits = EFER_NX | EFER_SCE;
1723 #ifdef CONFIG_X86_64
1724         ignore_bits |= EFER_LMA | EFER_LME;
1725         /* SCE is meaningful only in long mode on Intel */
1726         if (guest_efer & EFER_LMA)
1727                 ignore_bits &= ~(u64)EFER_SCE;
1728 #endif
1729         guest_efer &= ~ignore_bits;
1730         guest_efer |= host_efer & ignore_bits;
1731         vmx->guest_msrs[efer_offset].data = guest_efer;
1732         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1733
1734         clear_atomic_switch_msr(vmx, MSR_EFER);
1735
1736         /*
1737          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1738          * On CPUs that support "load IA32_EFER", always switch EFER
1739          * atomically, since it's faster than switching it manually.
1740          */
1741         if (cpu_has_load_ia32_efer ||
1742             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1743                 guest_efer = vmx->vcpu.arch.efer;
1744                 if (!(guest_efer & EFER_LMA))
1745                         guest_efer &= ~EFER_LME;
1746                 if (guest_efer != host_efer)
1747                         add_atomic_switch_msr(vmx, MSR_EFER,
1748                                               guest_efer, host_efer);
1749                 return false;
1750         }
1751
1752         return true;
1753 }
1754
1755 static unsigned long segment_base(u16 selector)
1756 {
1757         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1758         struct desc_struct *d;
1759         unsigned long table_base;
1760         unsigned long v;
1761
1762         if (!(selector & ~3))
1763                 return 0;
1764
1765         table_base = gdt->address;
1766
1767         if (selector & 4) {           /* from ldt */
1768                 u16 ldt_selector = kvm_read_ldt();
1769
1770                 if (!(ldt_selector & ~3))
1771                         return 0;
1772
1773                 table_base = segment_base(ldt_selector);
1774         }
1775         d = (struct desc_struct *)(table_base + (selector & ~7));
1776         v = get_desc_base(d);
1777 #ifdef CONFIG_X86_64
1778        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1779                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1780 #endif
1781         return v;
1782 }
1783
1784 static inline unsigned long kvm_read_tr_base(void)
1785 {
1786         u16 tr;
1787         asm("str %0" : "=g"(tr));
1788         return segment_base(tr);
1789 }
1790
1791 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1792 {
1793         struct vcpu_vmx *vmx = to_vmx(vcpu);
1794         int i;
1795
1796         if (vmx->host_state.loaded)
1797                 return;
1798
1799         vmx->host_state.loaded = 1;
1800         /*
1801          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1802          * allow segment selectors with cpl > 0 or ti == 1.
1803          */
1804         vmx->host_state.ldt_sel = kvm_read_ldt();
1805         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1806         savesegment(fs, vmx->host_state.fs_sel);
1807         if (!(vmx->host_state.fs_sel & 7)) {
1808                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1809                 vmx->host_state.fs_reload_needed = 0;
1810         } else {
1811                 vmcs_write16(HOST_FS_SELECTOR, 0);
1812                 vmx->host_state.fs_reload_needed = 1;
1813         }
1814         savesegment(gs, vmx->host_state.gs_sel);
1815         if (!(vmx->host_state.gs_sel & 7))
1816                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1817         else {
1818                 vmcs_write16(HOST_GS_SELECTOR, 0);
1819                 vmx->host_state.gs_ldt_reload_needed = 1;
1820         }
1821
1822 #ifdef CONFIG_X86_64
1823         savesegment(ds, vmx->host_state.ds_sel);
1824         savesegment(es, vmx->host_state.es_sel);
1825 #endif
1826
1827 #ifdef CONFIG_X86_64
1828         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1829         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1830 #else
1831         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1832         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1833 #endif
1834
1835 #ifdef CONFIG_X86_64
1836         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1837         if (is_long_mode(&vmx->vcpu))
1838                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1839 #endif
1840         if (boot_cpu_has(X86_FEATURE_MPX))
1841                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1842         for (i = 0; i < vmx->save_nmsrs; ++i)
1843                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1844                                    vmx->guest_msrs[i].data,
1845                                    vmx->guest_msrs[i].mask);
1846 }
1847
1848 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1849 {
1850         if (!vmx->host_state.loaded)
1851                 return;
1852
1853         ++vmx->vcpu.stat.host_state_reload;
1854         vmx->host_state.loaded = 0;
1855 #ifdef CONFIG_X86_64
1856         if (is_long_mode(&vmx->vcpu))
1857                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1858 #endif
1859         if (vmx->host_state.gs_ldt_reload_needed) {
1860                 kvm_load_ldt(vmx->host_state.ldt_sel);
1861 #ifdef CONFIG_X86_64
1862                 load_gs_index(vmx->host_state.gs_sel);
1863 #else
1864                 loadsegment(gs, vmx->host_state.gs_sel);
1865 #endif
1866         }
1867         if (vmx->host_state.fs_reload_needed)
1868                 loadsegment(fs, vmx->host_state.fs_sel);
1869 #ifdef CONFIG_X86_64
1870         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1871                 loadsegment(ds, vmx->host_state.ds_sel);
1872                 loadsegment(es, vmx->host_state.es_sel);
1873         }
1874 #endif
1875         reload_tss();
1876 #ifdef CONFIG_X86_64
1877         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1878 #endif
1879         if (vmx->host_state.msr_host_bndcfgs)
1880                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1881         /*
1882          * If the FPU is not active (through the host task or
1883          * the guest vcpu), then restore the cr0.TS bit.
1884          */
1885         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1886                 stts();
1887         load_gdt(this_cpu_ptr(&host_gdt));
1888 }
1889
1890 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1891 {
1892         preempt_disable();
1893         __vmx_load_host_state(vmx);
1894         preempt_enable();
1895 }
1896
1897 /*
1898  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1899  * vcpu mutex is already taken.
1900  */
1901 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1902 {
1903         struct vcpu_vmx *vmx = to_vmx(vcpu);
1904         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1905
1906         if (!vmm_exclusive)
1907                 kvm_cpu_vmxon(phys_addr);
1908         else if (vmx->loaded_vmcs->cpu != cpu)
1909                 loaded_vmcs_clear(vmx->loaded_vmcs);
1910
1911         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1912                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1913                 vmcs_load(vmx->loaded_vmcs->vmcs);
1914         }
1915
1916         if (vmx->loaded_vmcs->cpu != cpu) {
1917                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1918                 unsigned long sysenter_esp;
1919
1920                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1921                 local_irq_disable();
1922                 crash_disable_local_vmclear(cpu);
1923
1924                 /*
1925                  * Read loaded_vmcs->cpu should be before fetching
1926                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1927                  * See the comments in __loaded_vmcs_clear().
1928                  */
1929                 smp_rmb();
1930
1931                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1932                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1933                 crash_enable_local_vmclear(cpu);
1934                 local_irq_enable();
1935
1936                 /*
1937                  * Linux uses per-cpu TSS and GDT, so set these when switching
1938                  * processors.
1939                  */
1940                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1941                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1942
1943                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1944                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1945                 vmx->loaded_vmcs->cpu = cpu;
1946         }
1947 }
1948
1949 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1950 {
1951         __vmx_load_host_state(to_vmx(vcpu));
1952         if (!vmm_exclusive) {
1953                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1954                 vcpu->cpu = -1;
1955                 kvm_cpu_vmxoff();
1956         }
1957 }
1958
1959 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1960 {
1961         ulong cr0;
1962
1963         if (vcpu->fpu_active)
1964                 return;
1965         vcpu->fpu_active = 1;
1966         cr0 = vmcs_readl(GUEST_CR0);
1967         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1968         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1969         vmcs_writel(GUEST_CR0, cr0);
1970         update_exception_bitmap(vcpu);
1971         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1972         if (is_guest_mode(vcpu))
1973                 vcpu->arch.cr0_guest_owned_bits &=
1974                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1975         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1976 }
1977
1978 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1979
1980 /*
1981  * Return the cr0 value that a nested guest would read. This is a combination
1982  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1983  * its hypervisor (cr0_read_shadow).
1984  */
1985 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1986 {
1987         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1988                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1989 }
1990 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1991 {
1992         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1993                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1994 }
1995
1996 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1997 {
1998         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1999          * set this *before* calling this function.
2000          */
2001         vmx_decache_cr0_guest_bits(vcpu);
2002         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2003         update_exception_bitmap(vcpu);
2004         vcpu->arch.cr0_guest_owned_bits = 0;
2005         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2006         if (is_guest_mode(vcpu)) {
2007                 /*
2008                  * L1's specified read shadow might not contain the TS bit,
2009                  * so now that we turned on shadowing of this bit, we need to
2010                  * set this bit of the shadow. Like in nested_vmx_run we need
2011                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2012                  * up-to-date here because we just decached cr0.TS (and we'll
2013                  * only update vmcs12->guest_cr0 on nested exit).
2014                  */
2015                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2016                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2017                         (vcpu->arch.cr0 & X86_CR0_TS);
2018                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2019         } else
2020                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2021 }
2022
2023 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2024 {
2025         unsigned long rflags, save_rflags;
2026
2027         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2028                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2029                 rflags = vmcs_readl(GUEST_RFLAGS);
2030                 if (to_vmx(vcpu)->rmode.vm86_active) {
2031                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2032                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2033                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2034                 }
2035                 to_vmx(vcpu)->rflags = rflags;
2036         }
2037         return to_vmx(vcpu)->rflags;
2038 }
2039
2040 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2041 {
2042         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2043         to_vmx(vcpu)->rflags = rflags;
2044         if (to_vmx(vcpu)->rmode.vm86_active) {
2045                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2046                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2047         }
2048         vmcs_writel(GUEST_RFLAGS, rflags);
2049 }
2050
2051 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2052 {
2053         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2054         int ret = 0;
2055
2056         if (interruptibility & GUEST_INTR_STATE_STI)
2057                 ret |= KVM_X86_SHADOW_INT_STI;
2058         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2059                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2060
2061         return ret;
2062 }
2063
2064 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2065 {
2066         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2067         u32 interruptibility = interruptibility_old;
2068
2069         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2070
2071         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2072                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2073         else if (mask & KVM_X86_SHADOW_INT_STI)
2074                 interruptibility |= GUEST_INTR_STATE_STI;
2075
2076         if ((interruptibility != interruptibility_old))
2077                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2078 }
2079
2080 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2081 {
2082         unsigned long rip;
2083
2084         rip = kvm_rip_read(vcpu);
2085         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2086         kvm_rip_write(vcpu, rip);
2087
2088         /* skipping an emulated instruction also counts */
2089         vmx_set_interrupt_shadow(vcpu, 0);
2090 }
2091
2092 /*
2093  * KVM wants to inject page-faults which it got to the guest. This function
2094  * checks whether in a nested guest, we need to inject them to L1 or L2.
2095  */
2096 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2097 {
2098         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2099
2100         if (!(vmcs12->exception_bitmap & (1u << nr)))
2101                 return 0;
2102
2103         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2104                           vmcs_read32(VM_EXIT_INTR_INFO),
2105                           vmcs_readl(EXIT_QUALIFICATION));
2106         return 1;
2107 }
2108
2109 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2110                                 bool has_error_code, u32 error_code,
2111                                 bool reinject)
2112 {
2113         struct vcpu_vmx *vmx = to_vmx(vcpu);
2114         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2115
2116         if (!reinject && is_guest_mode(vcpu) &&
2117             nested_vmx_check_exception(vcpu, nr))
2118                 return;
2119
2120         if (has_error_code) {
2121                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2122                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2123         }
2124
2125         if (vmx->rmode.vm86_active) {
2126                 int inc_eip = 0;
2127                 if (kvm_exception_is_soft(nr))
2128                         inc_eip = vcpu->arch.event_exit_inst_len;
2129                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2130                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2131                 return;
2132         }
2133
2134         if (kvm_exception_is_soft(nr)) {
2135                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2136                              vmx->vcpu.arch.event_exit_inst_len);
2137                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2138         } else
2139                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2140
2141         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2142 }
2143
2144 static bool vmx_rdtscp_supported(void)
2145 {
2146         return cpu_has_vmx_rdtscp();
2147 }
2148
2149 static bool vmx_invpcid_supported(void)
2150 {
2151         return cpu_has_vmx_invpcid() && enable_ept;
2152 }
2153
2154 /*
2155  * Swap MSR entry in host/guest MSR entry array.
2156  */
2157 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2158 {
2159         struct shared_msr_entry tmp;
2160
2161         tmp = vmx->guest_msrs[to];
2162         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2163         vmx->guest_msrs[from] = tmp;
2164 }
2165
2166 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2167 {
2168         unsigned long *msr_bitmap;
2169
2170         if (is_guest_mode(vcpu))
2171                 msr_bitmap = vmx_msr_bitmap_nested;
2172         else if (irqchip_in_kernel(vcpu->kvm) &&
2173                 apic_x2apic_mode(vcpu->arch.apic)) {
2174                 if (is_long_mode(vcpu))
2175                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2176                 else
2177                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2178         } else {
2179                 if (is_long_mode(vcpu))
2180                         msr_bitmap = vmx_msr_bitmap_longmode;
2181                 else
2182                         msr_bitmap = vmx_msr_bitmap_legacy;
2183         }
2184
2185         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2186 }
2187
2188 /*
2189  * Set up the vmcs to automatically save and restore system
2190  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2191  * mode, as fiddling with msrs is very expensive.
2192  */
2193 static void setup_msrs(struct vcpu_vmx *vmx)
2194 {
2195         int save_nmsrs, index;
2196
2197         save_nmsrs = 0;
2198 #ifdef CONFIG_X86_64
2199         if (is_long_mode(&vmx->vcpu)) {
2200                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2201                 if (index >= 0)
2202                         move_msr_up(vmx, index, save_nmsrs++);
2203                 index = __find_msr_index(vmx, MSR_LSTAR);
2204                 if (index >= 0)
2205                         move_msr_up(vmx, index, save_nmsrs++);
2206                 index = __find_msr_index(vmx, MSR_CSTAR);
2207                 if (index >= 0)
2208                         move_msr_up(vmx, index, save_nmsrs++);
2209                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2210                 if (index >= 0 && vmx->rdtscp_enabled)
2211                         move_msr_up(vmx, index, save_nmsrs++);
2212                 /*
2213                  * MSR_STAR is only needed on long mode guests, and only
2214                  * if efer.sce is enabled.
2215                  */
2216                 index = __find_msr_index(vmx, MSR_STAR);
2217                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2218                         move_msr_up(vmx, index, save_nmsrs++);
2219         }
2220 #endif
2221         index = __find_msr_index(vmx, MSR_EFER);
2222         if (index >= 0 && update_transition_efer(vmx, index))
2223                 move_msr_up(vmx, index, save_nmsrs++);
2224
2225         vmx->save_nmsrs = save_nmsrs;
2226
2227         if (cpu_has_vmx_msr_bitmap())
2228                 vmx_set_msr_bitmap(&vmx->vcpu);
2229 }
2230
2231 /*
2232  * reads and returns guest's timestamp counter "register"
2233  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2234  */
2235 static u64 guest_read_tsc(void)
2236 {
2237         u64 host_tsc, tsc_offset;
2238
2239         rdtscll(host_tsc);
2240         tsc_offset = vmcs_read64(TSC_OFFSET);
2241         return host_tsc + tsc_offset;
2242 }
2243
2244 /*
2245  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2246  * counter, even if a nested guest (L2) is currently running.
2247  */
2248 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2249 {
2250         u64 tsc_offset;
2251
2252         tsc_offset = is_guest_mode(vcpu) ?
2253                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2254                 vmcs_read64(TSC_OFFSET);
2255         return host_tsc + tsc_offset;
2256 }
2257
2258 /*
2259  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2260  * software catchup for faster rates on slower CPUs.
2261  */
2262 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2263 {
2264         if (!scale)
2265                 return;
2266
2267         if (user_tsc_khz > tsc_khz) {
2268                 vcpu->arch.tsc_catchup = 1;
2269                 vcpu->arch.tsc_always_catchup = 1;
2270         } else
2271                 WARN(1, "user requested TSC rate below hardware speed\n");
2272 }
2273
2274 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2275 {
2276         return vmcs_read64(TSC_OFFSET);
2277 }
2278
2279 /*
2280  * writes 'offset' into guest's timestamp counter offset register
2281  */
2282 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2283 {
2284         if (is_guest_mode(vcpu)) {
2285                 /*
2286                  * We're here if L1 chose not to trap WRMSR to TSC. According
2287                  * to the spec, this should set L1's TSC; The offset that L1
2288                  * set for L2 remains unchanged, and still needs to be added
2289                  * to the newly set TSC to get L2's TSC.
2290                  */
2291                 struct vmcs12 *vmcs12;
2292                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2293                 /* recalculate vmcs02.TSC_OFFSET: */
2294                 vmcs12 = get_vmcs12(vcpu);
2295                 vmcs_write64(TSC_OFFSET, offset +
2296                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2297                          vmcs12->tsc_offset : 0));
2298         } else {
2299                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2300                                            vmcs_read64(TSC_OFFSET), offset);
2301                 vmcs_write64(TSC_OFFSET, offset);
2302         }
2303 }
2304
2305 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2306 {
2307         u64 offset = vmcs_read64(TSC_OFFSET);
2308
2309         vmcs_write64(TSC_OFFSET, offset + adjustment);
2310         if (is_guest_mode(vcpu)) {
2311                 /* Even when running L2, the adjustment needs to apply to L1 */
2312                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2313         } else
2314                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2315                                            offset + adjustment);
2316 }
2317
2318 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2319 {
2320         return target_tsc - native_read_tsc();
2321 }
2322
2323 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2324 {
2325         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2326         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2327 }
2328
2329 /*
2330  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2331  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2332  * all guests if the "nested" module option is off, and can also be disabled
2333  * for a single guest by disabling its VMX cpuid bit.
2334  */
2335 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2336 {
2337         return nested && guest_cpuid_has_vmx(vcpu);
2338 }
2339
2340 /*
2341  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2342  * returned for the various VMX controls MSRs when nested VMX is enabled.
2343  * The same values should also be used to verify that vmcs12 control fields are
2344  * valid during nested entry from L1 to L2.
2345  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2346  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2347  * bit in the high half is on if the corresponding bit in the control field
2348  * may be on. See also vmx_control_verify().
2349  */
2350 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2351 {
2352         /*
2353          * Note that as a general rule, the high half of the MSRs (bits in
2354          * the control fields which may be 1) should be initialized by the
2355          * intersection of the underlying hardware's MSR (i.e., features which
2356          * can be supported) and the list of features we want to expose -
2357          * because they are known to be properly supported in our code.
2358          * Also, usually, the low half of the MSRs (bits which must be 1) can
2359          * be set to 0, meaning that L1 may turn off any of these bits. The
2360          * reason is that if one of these bits is necessary, it will appear
2361          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2362          * fields of vmcs01 and vmcs02, will turn these bits off - and
2363          * nested_vmx_exit_handled() will not pass related exits to L1.
2364          * These rules have exceptions below.
2365          */
2366
2367         /* pin-based controls */
2368         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2369                 vmx->nested.nested_vmx_pinbased_ctls_low,
2370                 vmx->nested.nested_vmx_pinbased_ctls_high);
2371         vmx->nested.nested_vmx_pinbased_ctls_low |=
2372                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2373         vmx->nested.nested_vmx_pinbased_ctls_high &=
2374                 PIN_BASED_EXT_INTR_MASK |
2375                 PIN_BASED_NMI_EXITING |
2376                 PIN_BASED_VIRTUAL_NMIS;
2377         vmx->nested.nested_vmx_pinbased_ctls_high |=
2378                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2379                 PIN_BASED_VMX_PREEMPTION_TIMER;
2380         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2381                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2382                         PIN_BASED_POSTED_INTR;
2383
2384         /* exit controls */
2385         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2386                 vmx->nested.nested_vmx_exit_ctls_low,
2387                 vmx->nested.nested_vmx_exit_ctls_high);
2388         vmx->nested.nested_vmx_exit_ctls_low =
2389                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2390
2391         vmx->nested.nested_vmx_exit_ctls_high &=
2392 #ifdef CONFIG_X86_64
2393                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2394 #endif
2395                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2396         vmx->nested.nested_vmx_exit_ctls_high |=
2397                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2398                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2399                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2400
2401         if (vmx_mpx_supported())
2402                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2403
2404         /* We support free control of debug control saving. */
2405         vmx->nested.nested_vmx_true_exit_ctls_low =
2406                 vmx->nested.nested_vmx_exit_ctls_low &
2407                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2408
2409         /* entry controls */
2410         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2411                 vmx->nested.nested_vmx_entry_ctls_low,
2412                 vmx->nested.nested_vmx_entry_ctls_high);
2413         vmx->nested.nested_vmx_entry_ctls_low =
2414                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2415         vmx->nested.nested_vmx_entry_ctls_high &=
2416 #ifdef CONFIG_X86_64
2417                 VM_ENTRY_IA32E_MODE |
2418 #endif
2419                 VM_ENTRY_LOAD_IA32_PAT;
2420         vmx->nested.nested_vmx_entry_ctls_high |=
2421                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2422         if (vmx_mpx_supported())
2423                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2424
2425         /* We support free control of debug control loading. */
2426         vmx->nested.nested_vmx_true_entry_ctls_low =
2427                 vmx->nested.nested_vmx_entry_ctls_low &
2428                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2429
2430         /* cpu-based controls */
2431         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2432                 vmx->nested.nested_vmx_procbased_ctls_low,
2433                 vmx->nested.nested_vmx_procbased_ctls_high);
2434         vmx->nested.nested_vmx_procbased_ctls_low =
2435                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2436         vmx->nested.nested_vmx_procbased_ctls_high &=
2437                 CPU_BASED_VIRTUAL_INTR_PENDING |
2438                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2439                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2440                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2441                 CPU_BASED_CR3_STORE_EXITING |
2442 #ifdef CONFIG_X86_64
2443                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2444 #endif
2445                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2446                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2447                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2448                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2449                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2450         /*
2451          * We can allow some features even when not supported by the
2452          * hardware. For example, L1 can specify an MSR bitmap - and we
2453          * can use it to avoid exits to L1 - even when L0 runs L2
2454          * without MSR bitmaps.
2455          */
2456         vmx->nested.nested_vmx_procbased_ctls_high |=
2457                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2458                 CPU_BASED_USE_MSR_BITMAPS;
2459
2460         /* We support free control of CR3 access interception. */
2461         vmx->nested.nested_vmx_true_procbased_ctls_low =
2462                 vmx->nested.nested_vmx_procbased_ctls_low &
2463                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2464
2465         /* secondary cpu-based controls */
2466         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2467                 vmx->nested.nested_vmx_secondary_ctls_low,
2468                 vmx->nested.nested_vmx_secondary_ctls_high);
2469         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2470         vmx->nested.nested_vmx_secondary_ctls_high &=
2471                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2472                 SECONDARY_EXEC_RDTSCP |
2473                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2474                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2475                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2476                 SECONDARY_EXEC_WBINVD_EXITING |
2477                 SECONDARY_EXEC_XSAVES;
2478
2479         if (enable_ept) {
2480                 /* nested EPT: emulate EPT also to L1 */
2481                 vmx->nested.nested_vmx_secondary_ctls_high |=
2482                         SECONDARY_EXEC_ENABLE_EPT;
2483                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2484                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2485                          VMX_EPT_INVEPT_BIT;
2486                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2487                 /*
2488                  * For nested guests, we don't do anything specific
2489                  * for single context invalidation. Hence, only advertise
2490                  * support for global context invalidation.
2491                  */
2492                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2493         } else
2494                 vmx->nested.nested_vmx_ept_caps = 0;
2495
2496         if (enable_unrestricted_guest)
2497                 vmx->nested.nested_vmx_secondary_ctls_high |=
2498                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499
2500         /* miscellaneous data */
2501         rdmsr(MSR_IA32_VMX_MISC,
2502                 vmx->nested.nested_vmx_misc_low,
2503                 vmx->nested.nested_vmx_misc_high);
2504         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2505         vmx->nested.nested_vmx_misc_low |=
2506                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2507                 VMX_MISC_ACTIVITY_HLT;
2508         vmx->nested.nested_vmx_misc_high = 0;
2509 }
2510
2511 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2512 {
2513         /*
2514          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2515          */
2516         return ((control & high) | low) == control;
2517 }
2518
2519 static inline u64 vmx_control_msr(u32 low, u32 high)
2520 {
2521         return low | ((u64)high << 32);
2522 }
2523
2524 /* Returns 0 on success, non-0 otherwise. */
2525 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2526 {
2527         struct vcpu_vmx *vmx = to_vmx(vcpu);
2528
2529         switch (msr_index) {
2530         case MSR_IA32_VMX_BASIC:
2531                 /*
2532                  * This MSR reports some information about VMX support. We
2533                  * should return information about the VMX we emulate for the
2534                  * guest, and the VMCS structure we give it - not about the
2535                  * VMX support of the underlying hardware.
2536                  */
2537                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2538                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2539                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2540                 break;
2541         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2542         case MSR_IA32_VMX_PINBASED_CTLS:
2543                 *pdata = vmx_control_msr(
2544                         vmx->nested.nested_vmx_pinbased_ctls_low,
2545                         vmx->nested.nested_vmx_pinbased_ctls_high);
2546                 break;
2547         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2548                 *pdata = vmx_control_msr(
2549                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2550                         vmx->nested.nested_vmx_procbased_ctls_high);
2551                 break;
2552         case MSR_IA32_VMX_PROCBASED_CTLS:
2553                 *pdata = vmx_control_msr(
2554                         vmx->nested.nested_vmx_procbased_ctls_low,
2555                         vmx->nested.nested_vmx_procbased_ctls_high);
2556                 break;
2557         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2558                 *pdata = vmx_control_msr(
2559                         vmx->nested.nested_vmx_true_exit_ctls_low,
2560                         vmx->nested.nested_vmx_exit_ctls_high);
2561                 break;
2562         case MSR_IA32_VMX_EXIT_CTLS:
2563                 *pdata = vmx_control_msr(
2564                         vmx->nested.nested_vmx_exit_ctls_low,
2565                         vmx->nested.nested_vmx_exit_ctls_high);
2566                 break;
2567         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2568                 *pdata = vmx_control_msr(
2569                         vmx->nested.nested_vmx_true_entry_ctls_low,
2570                         vmx->nested.nested_vmx_entry_ctls_high);
2571                 break;
2572         case MSR_IA32_VMX_ENTRY_CTLS:
2573                 *pdata = vmx_control_msr(
2574                         vmx->nested.nested_vmx_entry_ctls_low,
2575                         vmx->nested.nested_vmx_entry_ctls_high);
2576                 break;
2577         case MSR_IA32_VMX_MISC:
2578                 *pdata = vmx_control_msr(
2579                         vmx->nested.nested_vmx_misc_low,
2580                         vmx->nested.nested_vmx_misc_high);
2581                 break;
2582         /*
2583          * These MSRs specify bits which the guest must keep fixed (on or off)
2584          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2585          * We picked the standard core2 setting.
2586          */
2587 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2588 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2589         case MSR_IA32_VMX_CR0_FIXED0:
2590                 *pdata = VMXON_CR0_ALWAYSON;
2591                 break;
2592         case MSR_IA32_VMX_CR0_FIXED1:
2593                 *pdata = -1ULL;
2594                 break;
2595         case MSR_IA32_VMX_CR4_FIXED0:
2596                 *pdata = VMXON_CR4_ALWAYSON;
2597                 break;
2598         case MSR_IA32_VMX_CR4_FIXED1:
2599                 *pdata = -1ULL;
2600                 break;
2601         case MSR_IA32_VMX_VMCS_ENUM:
2602                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2603                 break;
2604         case MSR_IA32_VMX_PROCBASED_CTLS2:
2605                 *pdata = vmx_control_msr(
2606                         vmx->nested.nested_vmx_secondary_ctls_low,
2607                         vmx->nested.nested_vmx_secondary_ctls_high);
2608                 break;
2609         case MSR_IA32_VMX_EPT_VPID_CAP:
2610                 /* Currently, no nested vpid support */
2611                 *pdata = vmx->nested.nested_vmx_ept_caps;
2612                 break;
2613         default:
2614                 return 1;
2615         }
2616
2617         return 0;
2618 }
2619
2620 /*
2621  * Reads an msr value (of 'msr_index') into 'pdata'.
2622  * Returns 0 on success, non-0 otherwise.
2623  * Assumes vcpu_load() was already called.
2624  */
2625 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2626 {
2627         u64 data;
2628         struct shared_msr_entry *msr;
2629
2630         if (!pdata) {
2631                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2632                 return -EINVAL;
2633         }
2634
2635         switch (msr_index) {
2636 #ifdef CONFIG_X86_64
2637         case MSR_FS_BASE:
2638                 data = vmcs_readl(GUEST_FS_BASE);
2639                 break;
2640         case MSR_GS_BASE:
2641                 data = vmcs_readl(GUEST_GS_BASE);
2642                 break;
2643         case MSR_KERNEL_GS_BASE:
2644                 vmx_load_host_state(to_vmx(vcpu));
2645                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2646                 break;
2647 #endif
2648         case MSR_EFER:
2649                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2650         case MSR_IA32_TSC:
2651                 data = guest_read_tsc();
2652                 break;
2653         case MSR_IA32_SYSENTER_CS:
2654                 data = vmcs_read32(GUEST_SYSENTER_CS);
2655                 break;
2656         case MSR_IA32_SYSENTER_EIP:
2657                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2658                 break;
2659         case MSR_IA32_SYSENTER_ESP:
2660                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2661                 break;
2662         case MSR_IA32_BNDCFGS:
2663                 if (!vmx_mpx_supported())
2664                         return 1;
2665                 data = vmcs_read64(GUEST_BNDCFGS);
2666                 break;
2667         case MSR_IA32_FEATURE_CONTROL:
2668                 if (!nested_vmx_allowed(vcpu))
2669                         return 1;
2670                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2671                 break;
2672         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2673                 if (!nested_vmx_allowed(vcpu))
2674                         return 1;
2675                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2676         case MSR_IA32_XSS:
2677                 if (!vmx_xsaves_supported())
2678                         return 1;
2679                 data = vcpu->arch.ia32_xss;
2680                 break;
2681         case MSR_TSC_AUX:
2682                 if (!to_vmx(vcpu)->rdtscp_enabled)
2683                         return 1;
2684                 /* Otherwise falls through */
2685         default:
2686                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2687                 if (msr) {
2688                         data = msr->data;
2689                         break;
2690                 }
2691                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2692         }
2693
2694         *pdata = data;
2695         return 0;
2696 }
2697
2698 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2699
2700 /*
2701  * Writes msr value into into the appropriate "register".
2702  * Returns 0 on success, non-0 otherwise.
2703  * Assumes vcpu_load() was already called.
2704  */
2705 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2706 {
2707         struct vcpu_vmx *vmx = to_vmx(vcpu);
2708         struct shared_msr_entry *msr;
2709         int ret = 0;
2710         u32 msr_index = msr_info->index;
2711         u64 data = msr_info->data;
2712
2713         switch (msr_index) {
2714         case MSR_EFER:
2715                 ret = kvm_set_msr_common(vcpu, msr_info);
2716                 break;
2717 #ifdef CONFIG_X86_64
2718         case MSR_FS_BASE:
2719                 vmx_segment_cache_clear(vmx);
2720                 vmcs_writel(GUEST_FS_BASE, data);
2721                 break;
2722         case MSR_GS_BASE:
2723                 vmx_segment_cache_clear(vmx);
2724                 vmcs_writel(GUEST_GS_BASE, data);
2725                 break;
2726         case MSR_KERNEL_GS_BASE:
2727                 vmx_load_host_state(vmx);
2728                 vmx->msr_guest_kernel_gs_base = data;
2729                 break;
2730 #endif
2731         case MSR_IA32_SYSENTER_CS:
2732                 vmcs_write32(GUEST_SYSENTER_CS, data);
2733                 break;
2734         case MSR_IA32_SYSENTER_EIP:
2735                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2736                 break;
2737         case MSR_IA32_SYSENTER_ESP:
2738                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2739                 break;
2740         case MSR_IA32_BNDCFGS:
2741                 if (!vmx_mpx_supported())
2742                         return 1;
2743                 vmcs_write64(GUEST_BNDCFGS, data);
2744                 break;
2745         case MSR_IA32_TSC:
2746                 kvm_write_tsc(vcpu, msr_info);
2747                 break;
2748         case MSR_IA32_CR_PAT:
2749                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2750                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2751                                 return 1;
2752                         vmcs_write64(GUEST_IA32_PAT, data);
2753                         vcpu->arch.pat = data;
2754                         break;
2755                 }
2756                 ret = kvm_set_msr_common(vcpu, msr_info);
2757                 break;
2758         case MSR_IA32_TSC_ADJUST:
2759                 ret = kvm_set_msr_common(vcpu, msr_info);
2760                 break;
2761         case MSR_IA32_FEATURE_CONTROL:
2762                 if (!nested_vmx_allowed(vcpu) ||
2763                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2764                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2765                         return 1;
2766                 vmx->nested.msr_ia32_feature_control = data;
2767                 if (msr_info->host_initiated && data == 0)
2768                         vmx_leave_nested(vcpu);
2769                 break;
2770         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2771                 return 1; /* they are read-only */
2772         case MSR_IA32_XSS:
2773                 if (!vmx_xsaves_supported())
2774                         return 1;
2775                 /*
2776                  * The only supported bit as of Skylake is bit 8, but
2777                  * it is not supported on KVM.
2778                  */
2779                 if (data != 0)
2780                         return 1;
2781                 vcpu->arch.ia32_xss = data;
2782                 if (vcpu->arch.ia32_xss != host_xss)
2783                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2784                                 vcpu->arch.ia32_xss, host_xss);
2785                 else
2786                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2787                 break;
2788         case MSR_TSC_AUX:
2789                 if (!vmx->rdtscp_enabled)
2790                         return 1;
2791                 /* Check reserved bit, higher 32 bits should be zero */
2792                 if ((data >> 32) != 0)
2793                         return 1;
2794                 /* Otherwise falls through */
2795         default:
2796                 msr = find_msr_entry(vmx, msr_index);
2797                 if (msr) {
2798                         u64 old_msr_data = msr->data;
2799                         msr->data = data;
2800                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2801                                 preempt_disable();
2802                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2803                                                          msr->mask);
2804                                 preempt_enable();
2805                                 if (ret)
2806                                         msr->data = old_msr_data;
2807                         }
2808                         break;
2809                 }
2810                 ret = kvm_set_msr_common(vcpu, msr_info);
2811         }
2812
2813         return ret;
2814 }
2815
2816 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2817 {
2818         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2819         switch (reg) {
2820         case VCPU_REGS_RSP:
2821                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2822                 break;
2823         case VCPU_REGS_RIP:
2824                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2825                 break;
2826         case VCPU_EXREG_PDPTR:
2827                 if (enable_ept)
2828                         ept_save_pdptrs(vcpu);
2829                 break;
2830         default:
2831                 break;
2832         }
2833 }
2834
2835 static __init int cpu_has_kvm_support(void)
2836 {
2837         return cpu_has_vmx();
2838 }
2839
2840 static __init int vmx_disabled_by_bios(void)
2841 {
2842         u64 msr;
2843
2844         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2845         if (msr & FEATURE_CONTROL_LOCKED) {
2846                 /* launched w/ TXT and VMX disabled */
2847                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2848                         && tboot_enabled())
2849                         return 1;
2850                 /* launched w/o TXT and VMX only enabled w/ TXT */
2851                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2852                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2853                         && !tboot_enabled()) {
2854                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2855                                 "activate TXT before enabling KVM\n");
2856                         return 1;
2857                 }
2858                 /* launched w/o TXT and VMX disabled */
2859                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2860                         && !tboot_enabled())
2861                         return 1;
2862         }
2863
2864         return 0;
2865 }
2866
2867 static void kvm_cpu_vmxon(u64 addr)
2868 {
2869         asm volatile (ASM_VMX_VMXON_RAX
2870                         : : "a"(&addr), "m"(addr)
2871                         : "memory", "cc");
2872 }
2873
2874 static int hardware_enable(void)
2875 {
2876         int cpu = raw_smp_processor_id();
2877         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2878         u64 old, test_bits;
2879
2880         if (cr4_read_shadow() & X86_CR4_VMXE)
2881                 return -EBUSY;
2882
2883         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2884
2885         /*
2886          * Now we can enable the vmclear operation in kdump
2887          * since the loaded_vmcss_on_cpu list on this cpu
2888          * has been initialized.
2889          *
2890          * Though the cpu is not in VMX operation now, there
2891          * is no problem to enable the vmclear operation
2892          * for the loaded_vmcss_on_cpu list is empty!
2893          */
2894         crash_enable_local_vmclear(cpu);
2895
2896         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2897
2898         test_bits = FEATURE_CONTROL_LOCKED;
2899         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2900         if (tboot_enabled())
2901                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2902
2903         if ((old & test_bits) != test_bits) {
2904                 /* enable and lock */
2905                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2906         }
2907         cr4_set_bits(X86_CR4_VMXE);
2908
2909         if (vmm_exclusive) {
2910                 kvm_cpu_vmxon(phys_addr);
2911                 ept_sync_global();
2912         }
2913
2914         native_store_gdt(this_cpu_ptr(&host_gdt));
2915
2916         return 0;
2917 }
2918
2919 static void vmclear_local_loaded_vmcss(void)
2920 {
2921         int cpu = raw_smp_processor_id();
2922         struct loaded_vmcs *v, *n;
2923
2924         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2925                                  loaded_vmcss_on_cpu_link)
2926                 __loaded_vmcs_clear(v);
2927 }
2928
2929
2930 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2931  * tricks.
2932  */
2933 static void kvm_cpu_vmxoff(void)
2934 {
2935         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2936 }
2937
2938 static void hardware_disable(void)
2939 {
2940         if (vmm_exclusive) {
2941                 vmclear_local_loaded_vmcss();
2942                 kvm_cpu_vmxoff();
2943         }
2944         cr4_clear_bits(X86_CR4_VMXE);
2945 }
2946
2947 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2948                                       u32 msr, u32 *result)
2949 {
2950         u32 vmx_msr_low, vmx_msr_high;
2951         u32 ctl = ctl_min | ctl_opt;
2952
2953         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2954
2955         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2956         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2957
2958         /* Ensure minimum (required) set of control bits are supported. */
2959         if (ctl_min & ~ctl)
2960                 return -EIO;
2961
2962         *result = ctl;
2963         return 0;
2964 }
2965
2966 static __init bool allow_1_setting(u32 msr, u32 ctl)
2967 {
2968         u32 vmx_msr_low, vmx_msr_high;
2969
2970         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2971         return vmx_msr_high & ctl;
2972 }
2973
2974 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2975 {
2976         u32 vmx_msr_low, vmx_msr_high;
2977         u32 min, opt, min2, opt2;
2978         u32 _pin_based_exec_control = 0;
2979         u32 _cpu_based_exec_control = 0;
2980         u32 _cpu_based_2nd_exec_control = 0;
2981         u32 _vmexit_control = 0;
2982         u32 _vmentry_control = 0;
2983
2984         min = CPU_BASED_HLT_EXITING |
2985 #ifdef CONFIG_X86_64
2986               CPU_BASED_CR8_LOAD_EXITING |
2987               CPU_BASED_CR8_STORE_EXITING |
2988 #endif
2989               CPU_BASED_CR3_LOAD_EXITING |
2990               CPU_BASED_CR3_STORE_EXITING |
2991               CPU_BASED_USE_IO_BITMAPS |
2992               CPU_BASED_MOV_DR_EXITING |
2993               CPU_BASED_USE_TSC_OFFSETING |
2994               CPU_BASED_MWAIT_EXITING |
2995               CPU_BASED_MONITOR_EXITING |
2996               CPU_BASED_INVLPG_EXITING |
2997               CPU_BASED_RDPMC_EXITING;
2998
2999         opt = CPU_BASED_TPR_SHADOW |
3000               CPU_BASED_USE_MSR_BITMAPS |
3001               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3002         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3003                                 &_cpu_based_exec_control) < 0)
3004                 return -EIO;
3005 #ifdef CONFIG_X86_64
3006         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3007                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3008                                            ~CPU_BASED_CR8_STORE_EXITING;
3009 #endif
3010         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3011                 min2 = 0;
3012                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3013                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3014                         SECONDARY_EXEC_WBINVD_EXITING |
3015                         SECONDARY_EXEC_ENABLE_VPID |
3016                         SECONDARY_EXEC_ENABLE_EPT |
3017                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3018                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3019                         SECONDARY_EXEC_RDTSCP |
3020                         SECONDARY_EXEC_ENABLE_INVPCID |
3021                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3022                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3023                         SECONDARY_EXEC_SHADOW_VMCS |
3024                         SECONDARY_EXEC_XSAVES |
3025                         SECONDARY_EXEC_ENABLE_PML;
3026                 if (adjust_vmx_controls(min2, opt2,
3027                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3028                                         &_cpu_based_2nd_exec_control) < 0)
3029                         return -EIO;
3030         }
3031 #ifndef CONFIG_X86_64
3032         if (!(_cpu_based_2nd_exec_control &
3033                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3034                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3035 #endif
3036
3037         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3038                 _cpu_based_2nd_exec_control &= ~(
3039                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3040                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3041                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3042
3043         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3044                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3045                    enabled */
3046                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3047                                              CPU_BASED_CR3_STORE_EXITING |
3048                                              CPU_BASED_INVLPG_EXITING);
3049                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3050                       vmx_capability.ept, vmx_capability.vpid);
3051         }
3052
3053         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3054 #ifdef CONFIG_X86_64
3055         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3056 #endif
3057         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3058                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3059         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3060                                 &_vmexit_control) < 0)
3061                 return -EIO;
3062
3063         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3064         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3065         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3066                                 &_pin_based_exec_control) < 0)
3067                 return -EIO;
3068
3069         if (!(_cpu_based_2nd_exec_control &
3070                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3071                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3072                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3073
3074         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3075         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3076         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3077                                 &_vmentry_control) < 0)
3078                 return -EIO;
3079
3080         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3081
3082         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3083         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3084                 return -EIO;
3085
3086 #ifdef CONFIG_X86_64
3087         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3088         if (vmx_msr_high & (1u<<16))
3089                 return -EIO;
3090 #endif
3091
3092         /* Require Write-Back (WB) memory type for VMCS accesses. */
3093         if (((vmx_msr_high >> 18) & 15) != 6)
3094                 return -EIO;
3095
3096         vmcs_conf->size = vmx_msr_high & 0x1fff;
3097         vmcs_conf->order = get_order(vmcs_config.size);
3098         vmcs_conf->revision_id = vmx_msr_low;
3099
3100         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3101         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3102         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3103         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3104         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3105
3106         cpu_has_load_ia32_efer =
3107                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108                                 VM_ENTRY_LOAD_IA32_EFER)
3109                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110                                    VM_EXIT_LOAD_IA32_EFER);
3111
3112         cpu_has_load_perf_global_ctrl =
3113                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3114                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3115                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3116                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3117
3118         /*
3119          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3120          * but due to arrata below it can't be used. Workaround is to use
3121          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3122          *
3123          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3124          *
3125          * AAK155             (model 26)
3126          * AAP115             (model 30)
3127          * AAT100             (model 37)
3128          * BC86,AAY89,BD102   (model 44)
3129          * BA97               (model 46)
3130          *
3131          */
3132         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3133                 switch (boot_cpu_data.x86_model) {
3134                 case 26:
3135                 case 30:
3136                 case 37:
3137                 case 44:
3138                 case 46:
3139                         cpu_has_load_perf_global_ctrl = false;
3140                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3141                                         "does not work properly. Using workaround\n");
3142                         break;
3143                 default:
3144                         break;
3145                 }
3146         }
3147
3148         if (cpu_has_xsaves)
3149                 rdmsrl(MSR_IA32_XSS, host_xss);
3150
3151         return 0;
3152 }
3153
3154 static struct vmcs *alloc_vmcs_cpu(int cpu)
3155 {
3156         int node = cpu_to_node(cpu);
3157         struct page *pages;
3158         struct vmcs *vmcs;
3159
3160         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3161         if (!pages)
3162                 return NULL;
3163         vmcs = page_address(pages);
3164         memset(vmcs, 0, vmcs_config.size);
3165         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3166         return vmcs;
3167 }
3168
3169 static struct vmcs *alloc_vmcs(void)
3170 {
3171         return alloc_vmcs_cpu(raw_smp_processor_id());
3172 }
3173
3174 static void free_vmcs(struct vmcs *vmcs)
3175 {
3176         free_pages((unsigned long)vmcs, vmcs_config.order);
3177 }
3178
3179 /*
3180  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3181  */
3182 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3183 {
3184         if (!loaded_vmcs->vmcs)
3185                 return;
3186         loaded_vmcs_clear(loaded_vmcs);
3187         free_vmcs(loaded_vmcs->vmcs);
3188         loaded_vmcs->vmcs = NULL;
3189 }
3190
3191 static void free_kvm_area(void)
3192 {
3193         int cpu;
3194
3195         for_each_possible_cpu(cpu) {
3196                 free_vmcs(per_cpu(vmxarea, cpu));
3197                 per_cpu(vmxarea, cpu) = NULL;
3198         }
3199 }
3200
3201 static void init_vmcs_shadow_fields(void)
3202 {
3203         int i, j;
3204
3205         /* No checks for read only fields yet */
3206
3207         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3208                 switch (shadow_read_write_fields[i]) {
3209                 case GUEST_BNDCFGS:
3210                         if (!vmx_mpx_supported())
3211                                 continue;
3212                         break;
3213                 default:
3214                         break;
3215                 }
3216
3217                 if (j < i)
3218                         shadow_read_write_fields[j] =
3219                                 shadow_read_write_fields[i];
3220                 j++;
3221         }
3222         max_shadow_read_write_fields = j;
3223
3224         /* shadowed fields guest access without vmexit */
3225         for (i = 0; i < max_shadow_read_write_fields; i++) {
3226                 clear_bit(shadow_read_write_fields[i],
3227                           vmx_vmwrite_bitmap);
3228                 clear_bit(shadow_read_write_fields[i],
3229                           vmx_vmread_bitmap);
3230         }
3231         for (i = 0; i < max_shadow_read_only_fields; i++)
3232                 clear_bit(shadow_read_only_fields[i],
3233                           vmx_vmread_bitmap);
3234 }
3235
3236 static __init int alloc_kvm_area(void)
3237 {
3238         int cpu;
3239
3240         for_each_possible_cpu(cpu) {
3241                 struct vmcs *vmcs;
3242
3243                 vmcs = alloc_vmcs_cpu(cpu);
3244                 if (!vmcs) {
3245                         free_kvm_area();
3246                         return -ENOMEM;
3247                 }
3248
3249                 per_cpu(vmxarea, cpu) = vmcs;
3250         }
3251         return 0;
3252 }
3253
3254 static bool emulation_required(struct kvm_vcpu *vcpu)
3255 {
3256         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3257 }
3258
3259 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3260                 struct kvm_segment *save)
3261 {
3262         if (!emulate_invalid_guest_state) {
3263                 /*
3264                  * CS and SS RPL should be equal during guest entry according
3265                  * to VMX spec, but in reality it is not always so. Since vcpu
3266                  * is in the middle of the transition from real mode to
3267                  * protected mode it is safe to assume that RPL 0 is a good
3268                  * default value.
3269                  */
3270                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3271                         save->selector &= ~SEGMENT_RPL_MASK;
3272                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3273                 save->s = 1;
3274         }
3275         vmx_set_segment(vcpu, save, seg);
3276 }
3277
3278 static void enter_pmode(struct kvm_vcpu *vcpu)
3279 {
3280         unsigned long flags;
3281         struct vcpu_vmx *vmx = to_vmx(vcpu);
3282
3283         /*
3284          * Update real mode segment cache. It may be not up-to-date if sement
3285          * register was written while vcpu was in a guest mode.
3286          */
3287         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3288         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3289         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3290         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3291         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3292         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3293
3294         vmx->rmode.vm86_active = 0;
3295
3296         vmx_segment_cache_clear(vmx);
3297
3298         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3299
3300         flags = vmcs_readl(GUEST_RFLAGS);
3301         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3302         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3303         vmcs_writel(GUEST_RFLAGS, flags);
3304
3305         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3306                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3307
3308         update_exception_bitmap(vcpu);
3309
3310         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3311         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3312         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3313         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3314         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3315         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3316 }
3317
3318 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3319 {
3320         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3321         struct kvm_segment var = *save;
3322
3323         var.dpl = 0x3;
3324         if (seg == VCPU_SREG_CS)
3325                 var.type = 0x3;
3326
3327         if (!emulate_invalid_guest_state) {
3328                 var.selector = var.base >> 4;
3329                 var.base = var.base & 0xffff0;
3330                 var.limit = 0xffff;
3331                 var.g = 0;
3332                 var.db = 0;
3333                 var.present = 1;
3334                 var.s = 1;
3335                 var.l = 0;
3336                 var.unusable = 0;
3337                 var.type = 0x3;
3338                 var.avl = 0;
3339                 if (save->base & 0xf)
3340                         printk_once(KERN_WARNING "kvm: segment base is not "
3341                                         "paragraph aligned when entering "
3342                                         "protected mode (seg=%d)", seg);
3343         }
3344
3345         vmcs_write16(sf->selector, var.selector);
3346         vmcs_write32(sf->base, var.base);
3347         vmcs_write32(sf->limit, var.limit);
3348         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3349 }
3350
3351 static void enter_rmode(struct kvm_vcpu *vcpu)
3352 {
3353         unsigned long flags;
3354         struct vcpu_vmx *vmx = to_vmx(vcpu);
3355
3356         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3358         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3359         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3360         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3361         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3363
3364         vmx->rmode.vm86_active = 1;
3365
3366         /*
3367          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3368          * vcpu. Warn the user that an update is overdue.
3369          */
3370         if (!vcpu->kvm->arch.tss_addr)
3371                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3372                              "called before entering vcpu\n");
3373
3374         vmx_segment_cache_clear(vmx);
3375
3376         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3377         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3378         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3379
3380         flags = vmcs_readl(GUEST_RFLAGS);
3381         vmx->rmode.save_rflags = flags;
3382
3383         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3384
3385         vmcs_writel(GUEST_RFLAGS, flags);
3386         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3387         update_exception_bitmap(vcpu);
3388
3389         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3390         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3391         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3392         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3393         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3394         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3395
3396         kvm_mmu_reset_context(vcpu);
3397 }
3398
3399 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3400 {
3401         struct vcpu_vmx *vmx = to_vmx(vcpu);
3402         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3403
3404         if (!msr)
3405                 return;
3406
3407         /*
3408          * Force kernel_gs_base reloading before EFER changes, as control
3409          * of this msr depends on is_long_mode().
3410          */
3411         vmx_load_host_state(to_vmx(vcpu));
3412         vcpu->arch.efer = efer;
3413         if (efer & EFER_LMA) {
3414                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3415                 msr->data = efer;
3416         } else {
3417                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3418
3419                 msr->data = efer & ~EFER_LME;
3420         }
3421         setup_msrs(vmx);
3422 }
3423
3424 #ifdef CONFIG_X86_64
3425
3426 static void enter_lmode(struct kvm_vcpu *vcpu)
3427 {
3428         u32 guest_tr_ar;
3429
3430         vmx_segment_cache_clear(to_vmx(vcpu));
3431
3432         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3433         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3434                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3435                                      __func__);
3436                 vmcs_write32(GUEST_TR_AR_BYTES,
3437                              (guest_tr_ar & ~AR_TYPE_MASK)
3438                              | AR_TYPE_BUSY_64_TSS);
3439         }
3440         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3441 }
3442
3443 static void exit_lmode(struct kvm_vcpu *vcpu)
3444 {
3445         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3446         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3447 }
3448
3449 #endif
3450
3451 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3452 {
3453         vpid_sync_context(to_vmx(vcpu));
3454         if (enable_ept) {
3455                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3456                         return;
3457                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3458         }
3459 }
3460
3461 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3462 {
3463         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3464
3465         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3466         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3467 }
3468
3469 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3470 {
3471         if (enable_ept && is_paging(vcpu))
3472                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3473         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3474 }
3475
3476 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3477 {
3478         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3479
3480         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3481         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3482 }
3483
3484 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3485 {
3486         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3487
3488         if (!test_bit(VCPU_EXREG_PDPTR,
3489                       (unsigned long *)&vcpu->arch.regs_dirty))
3490                 return;
3491
3492         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3493                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3494                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3495                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3496                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3497         }
3498 }
3499
3500 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3501 {
3502         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3503
3504         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3505                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3506                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3507                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3508                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3509         }
3510
3511         __set_bit(VCPU_EXREG_PDPTR,
3512                   (unsigned long *)&vcpu->arch.regs_avail);
3513         __set_bit(VCPU_EXREG_PDPTR,
3514                   (unsigned long *)&vcpu->arch.regs_dirty);
3515 }
3516
3517 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3518
3519 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3520                                         unsigned long cr0,
3521                                         struct kvm_vcpu *vcpu)
3522 {
3523         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3524                 vmx_decache_cr3(vcpu);
3525         if (!(cr0 & X86_CR0_PG)) {
3526                 /* From paging/starting to nonpaging */
3527                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3528                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3529                              (CPU_BASED_CR3_LOAD_EXITING |
3530                               CPU_BASED_CR3_STORE_EXITING));
3531                 vcpu->arch.cr0 = cr0;
3532                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3533         } else if (!is_paging(vcpu)) {
3534                 /* From nonpaging to paging */
3535                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3536                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3537                              ~(CPU_BASED_CR3_LOAD_EXITING |
3538                                CPU_BASED_CR3_STORE_EXITING));
3539                 vcpu->arch.cr0 = cr0;
3540                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3541         }
3542
3543         if (!(cr0 & X86_CR0_WP))
3544                 *hw_cr0 &= ~X86_CR0_WP;
3545 }
3546
3547 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3548 {
3549         struct vcpu_vmx *vmx = to_vmx(vcpu);
3550         unsigned long hw_cr0;
3551
3552         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3553         if (enable_unrestricted_guest)
3554                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3555         else {
3556                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3557
3558                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3559                         enter_pmode(vcpu);
3560
3561                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3562                         enter_rmode(vcpu);
3563         }
3564
3565 #ifdef CONFIG_X86_64
3566         if (vcpu->arch.efer & EFER_LME) {
3567                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3568                         enter_lmode(vcpu);
3569                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3570                         exit_lmode(vcpu);
3571         }
3572 #endif
3573
3574         if (enable_ept)
3575                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3576
3577         if (!vcpu->fpu_active)
3578                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3579
3580         vmcs_writel(CR0_READ_SHADOW, cr0);
3581         vmcs_writel(GUEST_CR0, hw_cr0);
3582         vcpu->arch.cr0 = cr0;
3583
3584         /* depends on vcpu->arch.cr0 to be set to a new value */
3585         vmx->emulation_required = emulation_required(vcpu);
3586 }
3587
3588 static u64 construct_eptp(unsigned long root_hpa)
3589 {
3590         u64 eptp;
3591
3592         /* TODO write the value reading from MSR */
3593         eptp = VMX_EPT_DEFAULT_MT |
3594                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3595         if (enable_ept_ad_bits)
3596                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3597         eptp |= (root_hpa & PAGE_MASK);
3598
3599         return eptp;
3600 }
3601
3602 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3603 {
3604         unsigned long guest_cr3;
3605         u64 eptp;
3606
3607         guest_cr3 = cr3;
3608         if (enable_ept) {
3609                 eptp = construct_eptp(cr3);
3610                 vmcs_write64(EPT_POINTER, eptp);
3611                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3612                         guest_cr3 = kvm_read_cr3(vcpu);
3613                 else
3614                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3615                 ept_load_pdptrs(vcpu);
3616         }
3617
3618         vmx_flush_tlb(vcpu);
3619         vmcs_writel(GUEST_CR3, guest_cr3);
3620 }
3621
3622 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3623 {
3624         /*
3625          * Pass through host's Machine Check Enable value to hw_cr4, which
3626          * is in force while we are in guest mode.  Do not let guests control
3627          * this bit, even if host CR4.MCE == 0.
3628          */
3629         unsigned long hw_cr4 =
3630                 (cr4_read_shadow() & X86_CR4_MCE) |
3631                 (cr4 & ~X86_CR4_MCE) |
3632                 (to_vmx(vcpu)->rmode.vm86_active ?
3633                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3634
3635         if (cr4 & X86_CR4_VMXE) {
3636                 /*
3637                  * To use VMXON (and later other VMX instructions), a guest
3638                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3639                  * So basically the check on whether to allow nested VMX
3640                  * is here.
3641                  */
3642                 if (!nested_vmx_allowed(vcpu))
3643                         return 1;
3644         }
3645         if (to_vmx(vcpu)->nested.vmxon &&
3646             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3647                 return 1;
3648
3649         vcpu->arch.cr4 = cr4;
3650         if (enable_ept) {
3651                 if (!is_paging(vcpu)) {
3652                         hw_cr4 &= ~X86_CR4_PAE;
3653                         hw_cr4 |= X86_CR4_PSE;
3654                         /*
3655                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3656                          * in hardware. However KVM always uses paging mode to
3657                          * emulate guest non-paging mode with TDP.
3658                          * To emulate this behavior, SMEP/SMAP needs to be
3659                          * manually disabled when guest switches to non-paging
3660                          * mode.
3661                          */
3662                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3663                 } else if (!(cr4 & X86_CR4_PAE)) {
3664                         hw_cr4 &= ~X86_CR4_PAE;
3665                 }
3666         }
3667
3668         vmcs_writel(CR4_READ_SHADOW, cr4);
3669         vmcs_writel(GUEST_CR4, hw_cr4);
3670         return 0;
3671 }
3672
3673 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3674                             struct kvm_segment *var, int seg)
3675 {
3676         struct vcpu_vmx *vmx = to_vmx(vcpu);
3677         u32 ar;
3678
3679         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3680                 *var = vmx->rmode.segs[seg];
3681                 if (seg == VCPU_SREG_TR
3682                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3683                         return;
3684                 var->base = vmx_read_guest_seg_base(vmx, seg);
3685                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3686                 return;
3687         }
3688         var->base = vmx_read_guest_seg_base(vmx, seg);
3689         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3690         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3691         ar = vmx_read_guest_seg_ar(vmx, seg);
3692         var->unusable = (ar >> 16) & 1;
3693         var->type = ar & 15;
3694         var->s = (ar >> 4) & 1;
3695         var->dpl = (ar >> 5) & 3;
3696         /*
3697          * Some userspaces do not preserve unusable property. Since usable
3698          * segment has to be present according to VMX spec we can use present
3699          * property to amend userspace bug by making unusable segment always
3700          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3701          * segment as unusable.
3702          */
3703         var->present = !var->unusable;
3704         var->avl = (ar >> 12) & 1;
3705         var->l = (ar >> 13) & 1;
3706         var->db = (ar >> 14) & 1;
3707         var->g = (ar >> 15) & 1;
3708 }
3709
3710 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3711 {
3712         struct kvm_segment s;
3713
3714         if (to_vmx(vcpu)->rmode.vm86_active) {
3715                 vmx_get_segment(vcpu, &s, seg);
3716                 return s.base;
3717         }
3718         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3719 }
3720
3721 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3722 {
3723         struct vcpu_vmx *vmx = to_vmx(vcpu);
3724
3725         if (unlikely(vmx->rmode.vm86_active))
3726                 return 0;
3727         else {
3728                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3729                 return AR_DPL(ar);
3730         }
3731 }
3732
3733 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3734 {
3735         u32 ar;
3736
3737         if (var->unusable || !var->present)
3738                 ar = 1 << 16;
3739         else {
3740                 ar = var->type & 15;
3741                 ar |= (var->s & 1) << 4;
3742                 ar |= (var->dpl & 3) << 5;
3743                 ar |= (var->present & 1) << 7;
3744                 ar |= (var->avl & 1) << 12;
3745                 ar |= (var->l & 1) << 13;
3746                 ar |= (var->db & 1) << 14;
3747                 ar |= (var->g & 1) << 15;
3748         }
3749
3750         return ar;
3751 }
3752
3753 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3754                             struct kvm_segment *var, int seg)
3755 {
3756         struct vcpu_vmx *vmx = to_vmx(vcpu);
3757         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3758
3759         vmx_segment_cache_clear(vmx);
3760
3761         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3762                 vmx->rmode.segs[seg] = *var;
3763                 if (seg == VCPU_SREG_TR)
3764                         vmcs_write16(sf->selector, var->selector);
3765                 else if (var->s)
3766                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3767                 goto out;
3768         }
3769
3770         vmcs_writel(sf->base, var->base);
3771         vmcs_write32(sf->limit, var->limit);
3772         vmcs_write16(sf->selector, var->selector);
3773
3774         /*
3775          *   Fix the "Accessed" bit in AR field of segment registers for older
3776          * qemu binaries.
3777          *   IA32 arch specifies that at the time of processor reset the
3778          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3779          * is setting it to 0 in the userland code. This causes invalid guest
3780          * state vmexit when "unrestricted guest" mode is turned on.
3781          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3782          * tree. Newer qemu binaries with that qemu fix would not need this
3783          * kvm hack.
3784          */
3785         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3786                 var->type |= 0x1; /* Accessed */
3787
3788         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3789
3790 out:
3791         vmx->emulation_required = emulation_required(vcpu);
3792 }
3793
3794 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3795 {
3796         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3797
3798         *db = (ar >> 14) & 1;
3799         *l = (ar >> 13) & 1;
3800 }
3801
3802 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3803 {
3804         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3805         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3806 }
3807
3808 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3809 {
3810         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3811         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3812 }
3813
3814 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3815 {
3816         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3817         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3818 }
3819
3820 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3821 {
3822         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3823         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3824 }
3825
3826 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3827 {
3828         struct kvm_segment var;
3829         u32 ar;
3830
3831         vmx_get_segment(vcpu, &var, seg);
3832         var.dpl = 0x3;
3833         if (seg == VCPU_SREG_CS)
3834                 var.type = 0x3;
3835         ar = vmx_segment_access_rights(&var);
3836
3837         if (var.base != (var.selector << 4))
3838                 return false;
3839         if (var.limit != 0xffff)
3840                 return false;
3841         if (ar != 0xf3)
3842                 return false;
3843
3844         return true;
3845 }
3846
3847 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3848 {
3849         struct kvm_segment cs;
3850         unsigned int cs_rpl;
3851
3852         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3853         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3854
3855         if (cs.unusable)
3856                 return false;
3857         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3858                 return false;
3859         if (!cs.s)
3860                 return false;
3861         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3862                 if (cs.dpl > cs_rpl)
3863                         return false;
3864         } else {
3865                 if (cs.dpl != cs_rpl)
3866                         return false;
3867         }
3868         if (!cs.present)
3869                 return false;
3870
3871         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3872         return true;
3873 }
3874
3875 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3876 {
3877         struct kvm_segment ss;
3878         unsigned int ss_rpl;
3879
3880         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3881         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3882
3883         if (ss.unusable)
3884                 return true;
3885         if (ss.type != 3 && ss.type != 7)
3886                 return false;
3887         if (!ss.s)
3888                 return false;
3889         if (ss.dpl != ss_rpl) /* DPL != RPL */
3890                 return false;
3891         if (!ss.present)
3892                 return false;
3893
3894         return true;
3895 }
3896
3897 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3898 {
3899         struct kvm_segment var;
3900         unsigned int rpl;
3901
3902         vmx_get_segment(vcpu, &var, seg);
3903         rpl = var.selector & SEGMENT_RPL_MASK;
3904
3905         if (var.unusable)
3906                 return true;
3907         if (!var.s)
3908                 return false;
3909         if (!var.present)
3910                 return false;
3911         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3912                 if (var.dpl < rpl) /* DPL < RPL */
3913                         return false;
3914         }
3915
3916         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3917          * rights flags
3918          */
3919         return true;
3920 }
3921
3922 static bool tr_valid(struct kvm_vcpu *vcpu)
3923 {
3924         struct kvm_segment tr;
3925
3926         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3927
3928         if (tr.unusable)
3929                 return false;
3930         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
3931                 return false;
3932         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3933                 return false;
3934         if (!tr.present)
3935                 return false;
3936
3937         return true;
3938 }
3939
3940 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3941 {
3942         struct kvm_segment ldtr;
3943
3944         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3945
3946         if (ldtr.unusable)
3947                 return true;
3948         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
3949                 return false;
3950         if (ldtr.type != 2)
3951                 return false;
3952         if (!ldtr.present)
3953                 return false;
3954
3955         return true;
3956 }
3957
3958 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3959 {
3960         struct kvm_segment cs, ss;
3961
3962         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3963         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3964
3965         return ((cs.selector & SEGMENT_RPL_MASK) ==
3966                  (ss.selector & SEGMENT_RPL_MASK));
3967 }
3968
3969 /*
3970  * Check if guest state is valid. Returns true if valid, false if
3971  * not.
3972  * We assume that registers are always usable
3973  */
3974 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3975 {
3976         if (enable_unrestricted_guest)
3977                 return true;
3978
3979         /* real mode guest state checks */
3980         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3981                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3982                         return false;
3983                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3984                         return false;
3985                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3986                         return false;
3987                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3988                         return false;
3989                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3990                         return false;
3991                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3992                         return false;
3993         } else {
3994         /* protected mode guest state checks */
3995                 if (!cs_ss_rpl_check(vcpu))
3996                         return false;
3997                 if (!code_segment_valid(vcpu))
3998                         return false;
3999                 if (!stack_segment_valid(vcpu))
4000                         return false;
4001                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4002                         return false;
4003                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4004                         return false;
4005                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4006                         return false;
4007                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4008                         return false;
4009                 if (!tr_valid(vcpu))
4010                         return false;
4011                 if (!ldtr_valid(vcpu))
4012                         return false;
4013         }
4014         /* TODO:
4015          * - Add checks on RIP
4016          * - Add checks on RFLAGS
4017          */
4018
4019         return true;
4020 }
4021
4022 static int init_rmode_tss(struct kvm *kvm)
4023 {
4024         gfn_t fn;
4025         u16 data = 0;
4026         int idx, r;
4027
4028         idx = srcu_read_lock(&kvm->srcu);
4029         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4030         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4031         if (r < 0)
4032                 goto out;
4033         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4034         r = kvm_write_guest_page(kvm, fn++, &data,
4035                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4036         if (r < 0)
4037                 goto out;
4038         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4039         if (r < 0)
4040                 goto out;
4041         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4042         if (r < 0)
4043                 goto out;
4044         data = ~0;
4045         r = kvm_write_guest_page(kvm, fn, &data,
4046                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4047                                  sizeof(u8));
4048 out:
4049         srcu_read_unlock(&kvm->srcu, idx);
4050         return r;
4051 }
4052
4053 static int init_rmode_identity_map(struct kvm *kvm)
4054 {
4055         int i, idx, r = 0;
4056         pfn_t identity_map_pfn;
4057         u32 tmp;
4058
4059         if (!enable_ept)
4060                 return 0;
4061
4062         /* Protect kvm->arch.ept_identity_pagetable_done. */
4063         mutex_lock(&kvm->slots_lock);
4064
4065         if (likely(kvm->arch.ept_identity_pagetable_done))
4066                 goto out2;
4067
4068         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4069
4070         r = alloc_identity_pagetable(kvm);
4071         if (r < 0)
4072                 goto out2;
4073
4074         idx = srcu_read_lock(&kvm->srcu);
4075         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4076         if (r < 0)
4077                 goto out;
4078         /* Set up identity-mapping pagetable for EPT in real mode */
4079         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4080                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4081                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4082                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4083                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4084                 if (r < 0)
4085                         goto out;
4086         }
4087         kvm->arch.ept_identity_pagetable_done = true;
4088
4089 out:
4090         srcu_read_unlock(&kvm->srcu, idx);
4091
4092 out2:
4093         mutex_unlock(&kvm->slots_lock);
4094         return r;
4095 }
4096
4097 static void seg_setup(int seg)
4098 {
4099         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4100         unsigned int ar;
4101
4102         vmcs_write16(sf->selector, 0);
4103         vmcs_writel(sf->base, 0);
4104         vmcs_write32(sf->limit, 0xffff);
4105         ar = 0x93;
4106         if (seg == VCPU_SREG_CS)
4107                 ar |= 0x08; /* code segment */
4108
4109         vmcs_write32(sf->ar_bytes, ar);
4110 }
4111
4112 static int alloc_apic_access_page(struct kvm *kvm)
4113 {
4114         struct page *page;
4115         struct kvm_userspace_memory_region kvm_userspace_mem;
4116         int r = 0;
4117
4118         mutex_lock(&kvm->slots_lock);
4119         if (kvm->arch.apic_access_page_done)
4120                 goto out;
4121         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4122         kvm_userspace_mem.flags = 0;
4123         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4124         kvm_userspace_mem.memory_size = PAGE_SIZE;
4125         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4126         if (r)
4127                 goto out;
4128
4129         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4130         if (is_error_page(page)) {
4131                 r = -EFAULT;
4132                 goto out;
4133         }
4134
4135         /*
4136          * Do not pin the page in memory, so that memory hot-unplug
4137          * is able to migrate it.
4138          */
4139         put_page(page);
4140         kvm->arch.apic_access_page_done = true;
4141 out:
4142         mutex_unlock(&kvm->slots_lock);
4143         return r;
4144 }
4145
4146 static int alloc_identity_pagetable(struct kvm *kvm)
4147 {
4148         /* Called with kvm->slots_lock held. */
4149
4150         struct kvm_userspace_memory_region kvm_userspace_mem;
4151         int r = 0;
4152
4153         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4154
4155         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4156         kvm_userspace_mem.flags = 0;
4157         kvm_userspace_mem.guest_phys_addr =
4158                 kvm->arch.ept_identity_map_addr;
4159         kvm_userspace_mem.memory_size = PAGE_SIZE;
4160         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4161
4162         return r;
4163 }
4164
4165 static void allocate_vpid(struct vcpu_vmx *vmx)
4166 {
4167         int vpid;
4168
4169         vmx->vpid = 0;
4170         if (!enable_vpid)
4171                 return;
4172         spin_lock(&vmx_vpid_lock);
4173         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4174         if (vpid < VMX_NR_VPIDS) {
4175                 vmx->vpid = vpid;
4176                 __set_bit(vpid, vmx_vpid_bitmap);
4177         }
4178         spin_unlock(&vmx_vpid_lock);
4179 }
4180
4181 static void free_vpid(struct vcpu_vmx *vmx)
4182 {
4183         if (!enable_vpid)
4184                 return;
4185         spin_lock(&vmx_vpid_lock);
4186         if (vmx->vpid != 0)
4187                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4188         spin_unlock(&vmx_vpid_lock);
4189 }
4190
4191 #define MSR_TYPE_R      1
4192 #define MSR_TYPE_W      2
4193 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4194                                                 u32 msr, int type)
4195 {
4196         int f = sizeof(unsigned long);
4197
4198         if (!cpu_has_vmx_msr_bitmap())
4199                 return;
4200
4201         /*
4202          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4203          * have the write-low and read-high bitmap offsets the wrong way round.
4204          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4205          */
4206         if (msr <= 0x1fff) {
4207                 if (type & MSR_TYPE_R)
4208                         /* read-low */
4209                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4210
4211                 if (type & MSR_TYPE_W)
4212                         /* write-low */
4213                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4214
4215         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4216                 msr &= 0x1fff;
4217                 if (type & MSR_TYPE_R)
4218                         /* read-high */
4219                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4220
4221                 if (type & MSR_TYPE_W)
4222                         /* write-high */
4223                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4224
4225         }
4226 }
4227
4228 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4229                                                 u32 msr, int type)
4230 {
4231         int f = sizeof(unsigned long);
4232
4233         if (!cpu_has_vmx_msr_bitmap())
4234                 return;
4235
4236         /*
4237          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4238          * have the write-low and read-high bitmap offsets the wrong way round.
4239          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4240          */
4241         if (msr <= 0x1fff) {
4242                 if (type & MSR_TYPE_R)
4243                         /* read-low */
4244                         __set_bit(msr, msr_bitmap + 0x000 / f);
4245
4246                 if (type & MSR_TYPE_W)
4247                         /* write-low */
4248                         __set_bit(msr, msr_bitmap + 0x800 / f);
4249
4250         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4251                 msr &= 0x1fff;
4252                 if (type & MSR_TYPE_R)
4253                         /* read-high */
4254                         __set_bit(msr, msr_bitmap + 0x400 / f);
4255
4256                 if (type & MSR_TYPE_W)
4257                         /* write-high */
4258                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4259
4260         }
4261 }
4262
4263 /*
4264  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4265  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4266  */
4267 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4268                                                unsigned long *msr_bitmap_nested,
4269                                                u32 msr, int type)
4270 {
4271         int f = sizeof(unsigned long);
4272
4273         if (!cpu_has_vmx_msr_bitmap()) {
4274                 WARN_ON(1);
4275                 return;
4276         }
4277
4278         /*
4279          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4280          * have the write-low and read-high bitmap offsets the wrong way round.
4281          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4282          */
4283         if (msr <= 0x1fff) {
4284                 if (type & MSR_TYPE_R &&
4285                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4286                         /* read-low */
4287                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4288
4289                 if (type & MSR_TYPE_W &&
4290                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4291                         /* write-low */
4292                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4293
4294         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4295                 msr &= 0x1fff;
4296                 if (type & MSR_TYPE_R &&
4297                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4298                         /* read-high */
4299                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4300
4301                 if (type & MSR_TYPE_W &&
4302                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4303                         /* write-high */
4304                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4305
4306         }
4307 }
4308
4309 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4310 {
4311         if (!longmode_only)
4312                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4313                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4314         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4315                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4316 }
4317
4318 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4319 {
4320         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4321                         msr, MSR_TYPE_R);
4322         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4323                         msr, MSR_TYPE_R);
4324 }
4325
4326 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4327 {
4328         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4329                         msr, MSR_TYPE_R);
4330         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4331                         msr, MSR_TYPE_R);
4332 }
4333
4334 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4335 {
4336         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4337                         msr, MSR_TYPE_W);
4338         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4339                         msr, MSR_TYPE_W);
4340 }
4341
4342 static int vmx_vm_has_apicv(struct kvm *kvm)
4343 {
4344         return enable_apicv && irqchip_in_kernel(kvm);
4345 }
4346
4347 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4348 {
4349         struct vcpu_vmx *vmx = to_vmx(vcpu);
4350         int max_irr;
4351         void *vapic_page;
4352         u16 status;
4353
4354         if (vmx->nested.pi_desc &&
4355             vmx->nested.pi_pending) {
4356                 vmx->nested.pi_pending = false;
4357                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4358                         return 0;
4359
4360                 max_irr = find_last_bit(
4361                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4362
4363                 if (max_irr == 256)
4364                         return 0;
4365
4366                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4367                 if (!vapic_page) {
4368                         WARN_ON(1);
4369                         return -ENOMEM;
4370                 }
4371                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4372                 kunmap(vmx->nested.virtual_apic_page);
4373
4374                 status = vmcs_read16(GUEST_INTR_STATUS);
4375                 if ((u8)max_irr > ((u8)status & 0xff)) {
4376                         status &= ~0xff;
4377                         status |= (u8)max_irr;
4378                         vmcs_write16(GUEST_INTR_STATUS, status);
4379                 }
4380         }
4381         return 0;
4382 }
4383
4384 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4385 {
4386 #ifdef CONFIG_SMP
4387         if (vcpu->mode == IN_GUEST_MODE) {
4388                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4389                                 POSTED_INTR_VECTOR);
4390                 return true;
4391         }
4392 #endif
4393         return false;
4394 }
4395
4396 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4397                                                 int vector)
4398 {
4399         struct vcpu_vmx *vmx = to_vmx(vcpu);
4400
4401         if (is_guest_mode(vcpu) &&
4402             vector == vmx->nested.posted_intr_nv) {
4403                 /* the PIR and ON have been set by L1. */
4404                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4405                 /*
4406                  * If a posted intr is not recognized by hardware,
4407                  * we will accomplish it in the next vmentry.
4408                  */
4409                 vmx->nested.pi_pending = true;
4410                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4411                 return 0;
4412         }
4413         return -1;
4414 }
4415 /*
4416  * Send interrupt to vcpu via posted interrupt way.
4417  * 1. If target vcpu is running(non-root mode), send posted interrupt
4418  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4419  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4420  * interrupt from PIR in next vmentry.
4421  */
4422 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4423 {
4424         struct vcpu_vmx *vmx = to_vmx(vcpu);
4425         int r;
4426
4427         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4428         if (!r)
4429                 return;
4430
4431         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4432                 return;
4433
4434         r = pi_test_and_set_on(&vmx->pi_desc);
4435         kvm_make_request(KVM_REQ_EVENT, vcpu);
4436         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4437                 kvm_vcpu_kick(vcpu);
4438 }
4439
4440 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4441 {
4442         struct vcpu_vmx *vmx = to_vmx(vcpu);
4443
4444         if (!pi_test_and_clear_on(&vmx->pi_desc))
4445                 return;
4446
4447         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4448 }
4449
4450 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4451 {
4452         return;
4453 }
4454
4455 /*
4456  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4457  * will not change in the lifetime of the guest.
4458  * Note that host-state that does change is set elsewhere. E.g., host-state
4459  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4460  */
4461 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4462 {
4463         u32 low32, high32;
4464         unsigned long tmpl;
4465         struct desc_ptr dt;
4466         unsigned long cr4;
4467
4468         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4469         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4470
4471         /* Save the most likely value for this task's CR4 in the VMCS. */
4472         cr4 = cr4_read_shadow();
4473         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4474         vmx->host_state.vmcs_host_cr4 = cr4;
4475
4476         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4477 #ifdef CONFIG_X86_64
4478         /*
4479          * Load null selectors, so we can avoid reloading them in
4480          * __vmx_load_host_state(), in case userspace uses the null selectors
4481          * too (the expected case).
4482          */
4483         vmcs_write16(HOST_DS_SELECTOR, 0);
4484         vmcs_write16(HOST_ES_SELECTOR, 0);
4485 #else
4486         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4487         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4488 #endif
4489         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4490         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4491
4492         native_store_idt(&dt);
4493         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4494         vmx->host_idt_base = dt.address;
4495
4496         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4497
4498         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4499         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4500         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4501         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4502
4503         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4504                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4505                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4506         }
4507 }
4508
4509 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4510 {
4511         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4512         if (enable_ept)
4513                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4514         if (is_guest_mode(&vmx->vcpu))
4515                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4516                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4517         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4518 }
4519
4520 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4521 {
4522         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4523
4524         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4525                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4526         return pin_based_exec_ctrl;
4527 }
4528
4529 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4530 {
4531         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4532
4533         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4534                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4535
4536         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4537                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4538 #ifdef CONFIG_X86_64
4539                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4540                                 CPU_BASED_CR8_LOAD_EXITING;
4541 #endif
4542         }
4543         if (!enable_ept)
4544                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4545                                 CPU_BASED_CR3_LOAD_EXITING  |
4546                                 CPU_BASED_INVLPG_EXITING;
4547         return exec_control;
4548 }
4549
4550 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4551 {
4552         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4553         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4554                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4555         if (vmx->vpid == 0)
4556                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4557         if (!enable_ept) {
4558                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4559                 enable_unrestricted_guest = 0;
4560                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4561                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4562         }
4563         if (!enable_unrestricted_guest)
4564                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4565         if (!ple_gap)
4566                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4567         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4568                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4569                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4570         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4571         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4572            (handle_vmptrld).
4573            We can NOT enable shadow_vmcs here because we don't have yet
4574            a current VMCS12
4575         */
4576         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4577         /* PML is enabled/disabled in creating/destorying vcpu */
4578         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4579
4580         return exec_control;
4581 }
4582
4583 static void ept_set_mmio_spte_mask(void)
4584 {
4585         /*
4586          * EPT Misconfigurations can be generated if the value of bits 2:0
4587          * of an EPT paging-structure entry is 110b (write/execute).
4588          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4589          * spte.
4590          */
4591         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4592 }
4593
4594 #define VMX_XSS_EXIT_BITMAP 0
4595 /*
4596  * Sets up the vmcs for emulated real mode.
4597  */
4598 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4599 {
4600 #ifdef CONFIG_X86_64
4601         unsigned long a;
4602 #endif
4603         int i;
4604
4605         /* I/O */
4606         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4607         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4608
4609         if (enable_shadow_vmcs) {
4610                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4611                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4612         }
4613         if (cpu_has_vmx_msr_bitmap())
4614                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4615
4616         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4617
4618         /* Control */
4619         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4620
4621         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4622
4623         if (cpu_has_secondary_exec_ctrls()) {
4624                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4625                                 vmx_secondary_exec_control(vmx));
4626         }
4627
4628         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4629                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4630                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4631                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4632                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4633
4634                 vmcs_write16(GUEST_INTR_STATUS, 0);
4635
4636                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4637                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4638         }
4639
4640         if (ple_gap) {
4641                 vmcs_write32(PLE_GAP, ple_gap);
4642                 vmx->ple_window = ple_window;
4643                 vmx->ple_window_dirty = true;
4644         }
4645
4646         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4647         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4648         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4649
4650         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4651         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4652         vmx_set_constant_host_state(vmx);
4653 #ifdef CONFIG_X86_64
4654         rdmsrl(MSR_FS_BASE, a);
4655         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4656         rdmsrl(MSR_GS_BASE, a);
4657         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4658 #else
4659         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4660         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4661 #endif
4662
4663         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4664         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4665         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4666         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4667         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4668
4669         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4670                 u32 msr_low, msr_high;
4671                 u64 host_pat;
4672                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4673                 host_pat = msr_low | ((u64) msr_high << 32);
4674                 /* Write the default value follow host pat */
4675                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4676                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4677                 vmx->vcpu.arch.pat = host_pat;
4678         }
4679
4680         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4681                 u32 index = vmx_msr_index[i];
4682                 u32 data_low, data_high;
4683                 int j = vmx->nmsrs;
4684
4685                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4686                         continue;
4687                 if (wrmsr_safe(index, data_low, data_high) < 0)
4688                         continue;
4689                 vmx->guest_msrs[j].index = i;
4690                 vmx->guest_msrs[j].data = 0;
4691                 vmx->guest_msrs[j].mask = -1ull;
4692                 ++vmx->nmsrs;
4693         }
4694
4695
4696         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4697
4698         /* 22.2.1, 20.8.1 */
4699         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4700
4701         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4702         set_cr4_guest_host_mask(vmx);
4703
4704         if (vmx_xsaves_supported())
4705                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4706
4707         return 0;
4708 }
4709
4710 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4711 {
4712         struct vcpu_vmx *vmx = to_vmx(vcpu);
4713         struct msr_data apic_base_msr;
4714
4715         vmx->rmode.vm86_active = 0;
4716
4717         vmx->soft_vnmi_blocked = 0;
4718
4719         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4720         kvm_set_cr8(&vmx->vcpu, 0);
4721         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4722         if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
4723                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4724         apic_base_msr.host_initiated = true;
4725         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4726
4727         vmx_segment_cache_clear(vmx);
4728
4729         seg_setup(VCPU_SREG_CS);
4730         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4731         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4732
4733         seg_setup(VCPU_SREG_DS);
4734         seg_setup(VCPU_SREG_ES);
4735         seg_setup(VCPU_SREG_FS);
4736         seg_setup(VCPU_SREG_GS);
4737         seg_setup(VCPU_SREG_SS);
4738
4739         vmcs_write16(GUEST_TR_SELECTOR, 0);
4740         vmcs_writel(GUEST_TR_BASE, 0);
4741         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4742         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4743
4744         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4745         vmcs_writel(GUEST_LDTR_BASE, 0);
4746         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4747         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4748
4749         vmcs_write32(GUEST_SYSENTER_CS, 0);
4750         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4751         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4752
4753         vmcs_writel(GUEST_RFLAGS, 0x02);
4754         kvm_rip_write(vcpu, 0xfff0);
4755
4756         vmcs_writel(GUEST_GDTR_BASE, 0);
4757         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4758
4759         vmcs_writel(GUEST_IDTR_BASE, 0);
4760         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4761
4762         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4763         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4764         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4765
4766         /* Special registers */
4767         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4768
4769         setup_msrs(vmx);
4770
4771         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4772
4773         if (cpu_has_vmx_tpr_shadow()) {
4774                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4775                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4776                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4777                                      __pa(vmx->vcpu.arch.apic->regs));
4778                 vmcs_write32(TPR_THRESHOLD, 0);
4779         }
4780
4781         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4782
4783         if (vmx_vm_has_apicv(vcpu->kvm))
4784                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4785
4786         if (vmx->vpid != 0)
4787                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4788
4789         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4790         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4791         vmx_set_cr4(&vmx->vcpu, 0);
4792         vmx_set_efer(&vmx->vcpu, 0);
4793         vmx_fpu_activate(&vmx->vcpu);
4794         update_exception_bitmap(&vmx->vcpu);
4795
4796         vpid_sync_context(vmx);
4797 }
4798
4799 /*
4800  * In nested virtualization, check if L1 asked to exit on external interrupts.
4801  * For most existing hypervisors, this will always return true.
4802  */
4803 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4804 {
4805         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4806                 PIN_BASED_EXT_INTR_MASK;
4807 }
4808
4809 /*
4810  * In nested virtualization, check if L1 has set
4811  * VM_EXIT_ACK_INTR_ON_EXIT
4812  */
4813 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4814 {
4815         return get_vmcs12(vcpu)->vm_exit_controls &
4816                 VM_EXIT_ACK_INTR_ON_EXIT;
4817 }
4818
4819 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4820 {
4821         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4822                 PIN_BASED_NMI_EXITING;
4823 }
4824
4825 static void enable_irq_window(struct kvm_vcpu *vcpu)
4826 {
4827         u32 cpu_based_vm_exec_control;
4828
4829         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4830         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4831         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4832 }
4833
4834 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4835 {
4836         u32 cpu_based_vm_exec_control;
4837
4838         if (!cpu_has_virtual_nmis() ||
4839             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4840                 enable_irq_window(vcpu);
4841                 return;
4842         }
4843
4844         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4845         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4846         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4847 }
4848
4849 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4850 {
4851         struct vcpu_vmx *vmx = to_vmx(vcpu);
4852         uint32_t intr;
4853         int irq = vcpu->arch.interrupt.nr;
4854
4855         trace_kvm_inj_virq(irq);
4856
4857         ++vcpu->stat.irq_injections;
4858         if (vmx->rmode.vm86_active) {
4859                 int inc_eip = 0;
4860                 if (vcpu->arch.interrupt.soft)
4861                         inc_eip = vcpu->arch.event_exit_inst_len;
4862                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4863                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4864                 return;
4865         }
4866         intr = irq | INTR_INFO_VALID_MASK;
4867         if (vcpu->arch.interrupt.soft) {
4868                 intr |= INTR_TYPE_SOFT_INTR;
4869                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4870                              vmx->vcpu.arch.event_exit_inst_len);
4871         } else
4872                 intr |= INTR_TYPE_EXT_INTR;
4873         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4874 }
4875
4876 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4877 {
4878         struct vcpu_vmx *vmx = to_vmx(vcpu);
4879
4880         if (is_guest_mode(vcpu))
4881                 return;
4882
4883         if (!cpu_has_virtual_nmis()) {
4884                 /*
4885                  * Tracking the NMI-blocked state in software is built upon
4886                  * finding the next open IRQ window. This, in turn, depends on
4887                  * well-behaving guests: They have to keep IRQs disabled at
4888                  * least as long as the NMI handler runs. Otherwise we may
4889                  * cause NMI nesting, maybe breaking the guest. But as this is
4890                  * highly unlikely, we can live with the residual risk.
4891                  */
4892                 vmx->soft_vnmi_blocked = 1;
4893                 vmx->vnmi_blocked_time = 0;
4894         }
4895
4896         ++vcpu->stat.nmi_injections;
4897         vmx->nmi_known_unmasked = false;
4898         if (vmx->rmode.vm86_active) {
4899                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4900                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4901                 return;
4902         }
4903         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4904                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4905 }
4906
4907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4908 {
4909         if (!cpu_has_virtual_nmis())
4910                 return to_vmx(vcpu)->soft_vnmi_blocked;
4911         if (to_vmx(vcpu)->nmi_known_unmasked)
4912                 return false;
4913         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4914 }
4915
4916 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4917 {
4918         struct vcpu_vmx *vmx = to_vmx(vcpu);
4919
4920         if (!cpu_has_virtual_nmis()) {
4921                 if (vmx->soft_vnmi_blocked != masked) {
4922                         vmx->soft_vnmi_blocked = masked;
4923                         vmx->vnmi_blocked_time = 0;
4924                 }
4925         } else {
4926                 vmx->nmi_known_unmasked = !masked;
4927                 if (masked)
4928                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4929                                       GUEST_INTR_STATE_NMI);
4930                 else
4931                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4932                                         GUEST_INTR_STATE_NMI);
4933         }
4934 }
4935
4936 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4937 {
4938         if (to_vmx(vcpu)->nested.nested_run_pending)
4939                 return 0;
4940
4941         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4942                 return 0;
4943
4944         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4945                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4946                    | GUEST_INTR_STATE_NMI));
4947 }
4948
4949 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4950 {
4951         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4952                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4953                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4954                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4955 }
4956
4957 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4958 {
4959         int ret;
4960         struct kvm_userspace_memory_region tss_mem = {
4961                 .slot = TSS_PRIVATE_MEMSLOT,
4962                 .guest_phys_addr = addr,
4963                 .memory_size = PAGE_SIZE * 3,
4964                 .flags = 0,
4965         };
4966
4967         ret = kvm_set_memory_region(kvm, &tss_mem);
4968         if (ret)
4969                 return ret;
4970         kvm->arch.tss_addr = addr;
4971         return init_rmode_tss(kvm);
4972 }
4973
4974 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4975 {
4976         switch (vec) {
4977         case BP_VECTOR:
4978                 /*
4979                  * Update instruction length as we may reinject the exception
4980                  * from user space while in guest debugging mode.
4981                  */
4982                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4983                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4984                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4985                         return false;
4986                 /* fall through */
4987         case DB_VECTOR:
4988                 if (vcpu->guest_debug &
4989                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4990                         return false;
4991                 /* fall through */
4992         case DE_VECTOR:
4993         case OF_VECTOR:
4994         case BR_VECTOR:
4995         case UD_VECTOR:
4996         case DF_VECTOR:
4997         case SS_VECTOR:
4998         case GP_VECTOR:
4999         case MF_VECTOR:
5000                 return true;
5001         break;
5002         }
5003         return false;
5004 }
5005
5006 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5007                                   int vec, u32 err_code)
5008 {
5009         /*
5010          * Instruction with address size override prefix opcode 0x67
5011          * Cause the #SS fault with 0 error code in VM86 mode.
5012          */
5013         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5014                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5015                         if (vcpu->arch.halt_request) {
5016                                 vcpu->arch.halt_request = 0;
5017                                 return kvm_vcpu_halt(vcpu);
5018                         }
5019                         return 1;
5020                 }
5021                 return 0;
5022         }
5023
5024         /*
5025          * Forward all other exceptions that are valid in real mode.
5026          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5027          *        the required debugging infrastructure rework.
5028          */
5029         kvm_queue_exception(vcpu, vec);
5030         return 1;
5031 }
5032
5033 /*
5034  * Trigger machine check on the host. We assume all the MSRs are already set up
5035  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5036  * We pass a fake environment to the machine check handler because we want
5037  * the guest to be always treated like user space, no matter what context
5038  * it used internally.
5039  */
5040 static void kvm_machine_check(void)
5041 {
5042 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5043         struct pt_regs regs = {
5044                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5045                 .flags = X86_EFLAGS_IF,
5046         };
5047
5048         do_machine_check(&regs, 0);
5049 #endif
5050 }
5051
5052 static int handle_machine_check(struct kvm_vcpu *vcpu)
5053 {
5054         /* already handled by vcpu_run */
5055         return 1;
5056 }
5057
5058 static int handle_exception(struct kvm_vcpu *vcpu)
5059 {
5060         struct vcpu_vmx *vmx = to_vmx(vcpu);
5061         struct kvm_run *kvm_run = vcpu->run;
5062         u32 intr_info, ex_no, error_code;
5063         unsigned long cr2, rip, dr6;
5064         u32 vect_info;
5065         enum emulation_result er;
5066
5067         vect_info = vmx->idt_vectoring_info;
5068         intr_info = vmx->exit_intr_info;
5069
5070         if (is_machine_check(intr_info))
5071                 return handle_machine_check(vcpu);
5072
5073         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5074                 return 1;  /* already handled by vmx_vcpu_run() */
5075
5076         if (is_no_device(intr_info)) {
5077                 vmx_fpu_activate(vcpu);
5078                 return 1;
5079         }
5080
5081         if (is_invalid_opcode(intr_info)) {
5082                 if (is_guest_mode(vcpu)) {
5083                         kvm_queue_exception(vcpu, UD_VECTOR);
5084                         return 1;
5085                 }
5086                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5087                 if (er != EMULATE_DONE)
5088                         kvm_queue_exception(vcpu, UD_VECTOR);
5089                 return 1;
5090         }
5091
5092         error_code = 0;
5093         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5094                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5095
5096         /*
5097          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5098          * MMIO, it is better to report an internal error.
5099          * See the comments in vmx_handle_exit.
5100          */
5101         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5102             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5103                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5104                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5105                 vcpu->run->internal.ndata = 3;
5106                 vcpu->run->internal.data[0] = vect_info;
5107                 vcpu->run->internal.data[1] = intr_info;
5108                 vcpu->run->internal.data[2] = error_code;
5109                 return 0;
5110         }
5111
5112         if (is_page_fault(intr_info)) {
5113                 /* EPT won't cause page fault directly */
5114                 BUG_ON(enable_ept);
5115                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5116                 trace_kvm_page_fault(cr2, error_code);
5117
5118                 if (kvm_event_needs_reinjection(vcpu))
5119                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5120                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5121         }
5122
5123         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5124
5125         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5126                 return handle_rmode_exception(vcpu, ex_no, error_code);
5127
5128         switch (ex_no) {
5129         case DB_VECTOR:
5130                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5131                 if (!(vcpu->guest_debug &
5132                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5133                         vcpu->arch.dr6 &= ~15;
5134                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5135                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5136                                 skip_emulated_instruction(vcpu);
5137
5138                         kvm_queue_exception(vcpu, DB_VECTOR);
5139                         return 1;
5140                 }
5141                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5142                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5143                 /* fall through */
5144         case BP_VECTOR:
5145                 /*
5146                  * Update instruction length as we may reinject #BP from
5147                  * user space while in guest debugging mode. Reading it for
5148                  * #DB as well causes no harm, it is not used in that case.
5149                  */
5150                 vmx->vcpu.arch.event_exit_inst_len =
5151                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5152                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5153                 rip = kvm_rip_read(vcpu);
5154                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5155                 kvm_run->debug.arch.exception = ex_no;
5156                 break;
5157         default:
5158                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5159                 kvm_run->ex.exception = ex_no;
5160                 kvm_run->ex.error_code = error_code;
5161                 break;
5162         }
5163         return 0;
5164 }
5165
5166 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5167 {
5168         ++vcpu->stat.irq_exits;
5169         return 1;
5170 }
5171
5172 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5173 {
5174         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5175         return 0;
5176 }
5177
5178 static int handle_io(struct kvm_vcpu *vcpu)
5179 {
5180         unsigned long exit_qualification;
5181         int size, in, string;
5182         unsigned port;
5183
5184         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5185         string = (exit_qualification & 16) != 0;
5186         in = (exit_qualification & 8) != 0;
5187
5188         ++vcpu->stat.io_exits;
5189
5190         if (string || in)
5191                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5192
5193         port = exit_qualification >> 16;
5194         size = (exit_qualification & 7) + 1;
5195         skip_emulated_instruction(vcpu);
5196
5197         return kvm_fast_pio_out(vcpu, size, port);
5198 }
5199
5200 static void
5201 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5202 {
5203         /*
5204          * Patch in the VMCALL instruction:
5205          */
5206         hypercall[0] = 0x0f;
5207         hypercall[1] = 0x01;
5208         hypercall[2] = 0xc1;
5209 }
5210
5211 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5212 {
5213         unsigned long always_on = VMXON_CR0_ALWAYSON;
5214         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5215
5216         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5217                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5218             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5219                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5220         return (val & always_on) == always_on;
5221 }
5222
5223 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5224 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5225 {
5226         if (is_guest_mode(vcpu)) {
5227                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5228                 unsigned long orig_val = val;
5229
5230                 /*
5231                  * We get here when L2 changed cr0 in a way that did not change
5232                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5233                  * but did change L0 shadowed bits. So we first calculate the
5234                  * effective cr0 value that L1 would like to write into the
5235                  * hardware. It consists of the L2-owned bits from the new
5236                  * value combined with the L1-owned bits from L1's guest_cr0.
5237                  */
5238                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5239                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5240
5241                 if (!nested_cr0_valid(vcpu, val))
5242                         return 1;
5243
5244                 if (kvm_set_cr0(vcpu, val))
5245                         return 1;
5246                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5247                 return 0;
5248         } else {
5249                 if (to_vmx(vcpu)->nested.vmxon &&
5250                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5251                         return 1;
5252                 return kvm_set_cr0(vcpu, val);
5253         }
5254 }
5255
5256 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5257 {
5258         if (is_guest_mode(vcpu)) {
5259                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5260                 unsigned long orig_val = val;
5261
5262                 /* analogously to handle_set_cr0 */
5263                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5264                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5265                 if (kvm_set_cr4(vcpu, val))
5266                         return 1;
5267                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5268                 return 0;
5269         } else
5270                 return kvm_set_cr4(vcpu, val);
5271 }
5272
5273 /* called to set cr0 as approriate for clts instruction exit. */
5274 static void handle_clts(struct kvm_vcpu *vcpu)
5275 {
5276         if (is_guest_mode(vcpu)) {
5277                 /*
5278                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5279                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5280                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5281                  */
5282                 vmcs_writel(CR0_READ_SHADOW,
5283                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5284                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5285         } else
5286                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5287 }
5288
5289 static int handle_cr(struct kvm_vcpu *vcpu)
5290 {
5291         unsigned long exit_qualification, val;
5292         int cr;
5293         int reg;
5294         int err;
5295
5296         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5297         cr = exit_qualification & 15;
5298         reg = (exit_qualification >> 8) & 15;
5299         switch ((exit_qualification >> 4) & 3) {
5300         case 0: /* mov to cr */
5301                 val = kvm_register_readl(vcpu, reg);
5302                 trace_kvm_cr_write(cr, val);
5303                 switch (cr) {
5304                 case 0:
5305                         err = handle_set_cr0(vcpu, val);
5306                         kvm_complete_insn_gp(vcpu, err);
5307                         return 1;
5308                 case 3:
5309                         err = kvm_set_cr3(vcpu, val);
5310                         kvm_complete_insn_gp(vcpu, err);
5311                         return 1;
5312                 case 4:
5313                         err = handle_set_cr4(vcpu, val);
5314                         kvm_complete_insn_gp(vcpu, err);
5315                         return 1;
5316                 case 8: {
5317                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5318                                 u8 cr8 = (u8)val;
5319                                 err = kvm_set_cr8(vcpu, cr8);
5320                                 kvm_complete_insn_gp(vcpu, err);
5321                                 if (irqchip_in_kernel(vcpu->kvm))
5322                                         return 1;
5323                                 if (cr8_prev <= cr8)
5324                                         return 1;
5325                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5326                                 return 0;
5327                         }
5328                 }
5329                 break;
5330         case 2: /* clts */
5331                 handle_clts(vcpu);
5332                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5333                 skip_emulated_instruction(vcpu);
5334                 vmx_fpu_activate(vcpu);
5335                 return 1;
5336         case 1: /*mov from cr*/
5337                 switch (cr) {
5338                 case 3:
5339                         val = kvm_read_cr3(vcpu);
5340                         kvm_register_write(vcpu, reg, val);
5341                         trace_kvm_cr_read(cr, val);
5342                         skip_emulated_instruction(vcpu);
5343                         return 1;
5344                 case 8:
5345                         val = kvm_get_cr8(vcpu);
5346                         kvm_register_write(vcpu, reg, val);
5347                         trace_kvm_cr_read(cr, val);
5348                         skip_emulated_instruction(vcpu);
5349                         return 1;
5350                 }
5351                 break;
5352         case 3: /* lmsw */
5353                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5354                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5355                 kvm_lmsw(vcpu, val);
5356
5357                 skip_emulated_instruction(vcpu);
5358                 return 1;
5359         default:
5360                 break;
5361         }
5362         vcpu->run->exit_reason = 0;
5363         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5364                (int)(exit_qualification >> 4) & 3, cr);
5365         return 0;
5366 }
5367
5368 static int handle_dr(struct kvm_vcpu *vcpu)
5369 {
5370         unsigned long exit_qualification;
5371         int dr, dr7, reg;
5372
5373         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5374         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5375
5376         /* First, if DR does not exist, trigger UD */
5377         if (!kvm_require_dr(vcpu, dr))
5378                 return 1;
5379
5380         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5381         if (!kvm_require_cpl(vcpu, 0))
5382                 return 1;
5383         dr7 = vmcs_readl(GUEST_DR7);
5384         if (dr7 & DR7_GD) {
5385                 /*
5386                  * As the vm-exit takes precedence over the debug trap, we
5387                  * need to emulate the latter, either for the host or the
5388                  * guest debugging itself.
5389                  */
5390                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5391                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5392                         vcpu->run->debug.arch.dr7 = dr7;
5393                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5394                         vcpu->run->debug.arch.exception = DB_VECTOR;
5395                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5396                         return 0;
5397                 } else {
5398                         vcpu->arch.dr6 &= ~15;
5399                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5400                         kvm_queue_exception(vcpu, DB_VECTOR);
5401                         return 1;
5402                 }
5403         }
5404
5405         if (vcpu->guest_debug == 0) {
5406                 u32 cpu_based_vm_exec_control;
5407
5408                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5409                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5410                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5411
5412                 /*
5413                  * No more DR vmexits; force a reload of the debug registers
5414                  * and reenter on this instruction.  The next vmexit will
5415                  * retrieve the full state of the debug registers.
5416                  */
5417                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5418                 return 1;
5419         }
5420
5421         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5422         if (exit_qualification & TYPE_MOV_FROM_DR) {
5423                 unsigned long val;
5424
5425                 if (kvm_get_dr(vcpu, dr, &val))
5426                         return 1;
5427                 kvm_register_write(vcpu, reg, val);
5428         } else
5429                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5430                         return 1;
5431
5432         skip_emulated_instruction(vcpu);
5433         return 1;
5434 }
5435
5436 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5437 {
5438         return vcpu->arch.dr6;
5439 }
5440
5441 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5442 {
5443 }
5444
5445 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5446 {
5447         u32 cpu_based_vm_exec_control;
5448
5449         get_debugreg(vcpu->arch.db[0], 0);
5450         get_debugreg(vcpu->arch.db[1], 1);
5451         get_debugreg(vcpu->arch.db[2], 2);
5452         get_debugreg(vcpu->arch.db[3], 3);
5453         get_debugreg(vcpu->arch.dr6, 6);
5454         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5455
5456         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5457
5458         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5459         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5460         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5461 }
5462
5463 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5464 {
5465         vmcs_writel(GUEST_DR7, val);
5466 }
5467
5468 static int handle_cpuid(struct kvm_vcpu *vcpu)
5469 {
5470         kvm_emulate_cpuid(vcpu);
5471         return 1;
5472 }
5473
5474 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5475 {
5476         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5477         u64 data;
5478
5479         if (vmx_get_msr(vcpu, ecx, &data)) {
5480                 trace_kvm_msr_read_ex(ecx);
5481                 kvm_inject_gp(vcpu, 0);
5482                 return 1;
5483         }
5484
5485         trace_kvm_msr_read(ecx, data);
5486
5487         /* FIXME: handling of bits 32:63 of rax, rdx */
5488         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5489         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5490         skip_emulated_instruction(vcpu);
5491         return 1;
5492 }
5493
5494 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5495 {
5496         struct msr_data msr;
5497         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5498         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5499                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5500
5501         msr.data = data;
5502         msr.index = ecx;
5503         msr.host_initiated = false;
5504         if (kvm_set_msr(vcpu, &msr) != 0) {
5505                 trace_kvm_msr_write_ex(ecx, data);
5506                 kvm_inject_gp(vcpu, 0);
5507                 return 1;
5508         }
5509
5510         trace_kvm_msr_write(ecx, data);
5511         skip_emulated_instruction(vcpu);
5512         return 1;
5513 }
5514
5515 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5516 {
5517         kvm_make_request(KVM_REQ_EVENT, vcpu);
5518         return 1;
5519 }
5520
5521 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5522 {
5523         u32 cpu_based_vm_exec_control;
5524
5525         /* clear pending irq */
5526         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5527         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5528         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5529
5530         kvm_make_request(KVM_REQ_EVENT, vcpu);
5531
5532         ++vcpu->stat.irq_window_exits;
5533
5534         /*
5535          * If the user space waits to inject interrupts, exit as soon as
5536          * possible
5537          */
5538         if (!irqchip_in_kernel(vcpu->kvm) &&
5539             vcpu->run->request_interrupt_window &&
5540             !kvm_cpu_has_interrupt(vcpu)) {
5541                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5542                 return 0;
5543         }
5544         return 1;
5545 }
5546
5547 static int handle_halt(struct kvm_vcpu *vcpu)
5548 {
5549         return kvm_emulate_halt(vcpu);
5550 }
5551
5552 static int handle_vmcall(struct kvm_vcpu *vcpu)
5553 {
5554         kvm_emulate_hypercall(vcpu);
5555         return 1;
5556 }
5557
5558 static int handle_invd(struct kvm_vcpu *vcpu)
5559 {
5560         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5561 }
5562
5563 static int handle_invlpg(struct kvm_vcpu *vcpu)
5564 {
5565         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5566
5567         kvm_mmu_invlpg(vcpu, exit_qualification);
5568         skip_emulated_instruction(vcpu);
5569         return 1;
5570 }
5571
5572 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5573 {
5574         int err;
5575
5576         err = kvm_rdpmc(vcpu);
5577         kvm_complete_insn_gp(vcpu, err);
5578
5579         return 1;
5580 }
5581
5582 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5583 {
5584         kvm_emulate_wbinvd(vcpu);
5585         return 1;
5586 }
5587
5588 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5589 {
5590         u64 new_bv = kvm_read_edx_eax(vcpu);
5591         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5592
5593         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5594                 skip_emulated_instruction(vcpu);
5595         return 1;
5596 }
5597
5598 static int handle_xsaves(struct kvm_vcpu *vcpu)
5599 {
5600         skip_emulated_instruction(vcpu);
5601         WARN(1, "this should never happen\n");
5602         return 1;
5603 }
5604
5605 static int handle_xrstors(struct kvm_vcpu *vcpu)
5606 {
5607         skip_emulated_instruction(vcpu);
5608         WARN(1, "this should never happen\n");
5609         return 1;
5610 }
5611
5612 static int handle_apic_access(struct kvm_vcpu *vcpu)
5613 {
5614         if (likely(fasteoi)) {
5615                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5616                 int access_type, offset;
5617
5618                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5619                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5620                 /*
5621                  * Sane guest uses MOV to write EOI, with written value
5622                  * not cared. So make a short-circuit here by avoiding
5623                  * heavy instruction emulation.
5624                  */
5625                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5626                     (offset == APIC_EOI)) {
5627                         kvm_lapic_set_eoi(vcpu);
5628                         skip_emulated_instruction(vcpu);
5629                         return 1;
5630                 }
5631         }
5632         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5633 }
5634
5635 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5636 {
5637         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5638         int vector = exit_qualification & 0xff;
5639
5640         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5641         kvm_apic_set_eoi_accelerated(vcpu, vector);
5642         return 1;
5643 }
5644
5645 static int handle_apic_write(struct kvm_vcpu *vcpu)
5646 {
5647         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5648         u32 offset = exit_qualification & 0xfff;
5649
5650         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5651         kvm_apic_write_nodecode(vcpu, offset);
5652         return 1;
5653 }
5654
5655 static int handle_task_switch(struct kvm_vcpu *vcpu)
5656 {
5657         struct vcpu_vmx *vmx = to_vmx(vcpu);
5658         unsigned long exit_qualification;
5659         bool has_error_code = false;
5660         u32 error_code = 0;
5661         u16 tss_selector;
5662         int reason, type, idt_v, idt_index;
5663
5664         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5665         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5666         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5667
5668         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5669
5670         reason = (u32)exit_qualification >> 30;
5671         if (reason == TASK_SWITCH_GATE && idt_v) {
5672                 switch (type) {
5673                 case INTR_TYPE_NMI_INTR:
5674                         vcpu->arch.nmi_injected = false;
5675                         vmx_set_nmi_mask(vcpu, true);
5676                         break;
5677                 case INTR_TYPE_EXT_INTR:
5678                 case INTR_TYPE_SOFT_INTR:
5679                         kvm_clear_interrupt_queue(vcpu);
5680                         break;
5681                 case INTR_TYPE_HARD_EXCEPTION:
5682                         if (vmx->idt_vectoring_info &
5683                             VECTORING_INFO_DELIVER_CODE_MASK) {
5684                                 has_error_code = true;
5685                                 error_code =
5686                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5687                         }
5688                         /* fall through */
5689                 case INTR_TYPE_SOFT_EXCEPTION:
5690                         kvm_clear_exception_queue(vcpu);
5691                         break;
5692                 default:
5693                         break;
5694                 }
5695         }
5696         tss_selector = exit_qualification;
5697
5698         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5699                        type != INTR_TYPE_EXT_INTR &&
5700                        type != INTR_TYPE_NMI_INTR))
5701                 skip_emulated_instruction(vcpu);
5702
5703         if (kvm_task_switch(vcpu, tss_selector,
5704                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5705                             has_error_code, error_code) == EMULATE_FAIL) {
5706                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5707                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5708                 vcpu->run->internal.ndata = 0;
5709                 return 0;
5710         }
5711
5712         /* clear all local breakpoint enable flags */
5713         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5714
5715         /*
5716          * TODO: What about debug traps on tss switch?
5717          *       Are we supposed to inject them and update dr6?
5718          */
5719
5720         return 1;
5721 }
5722
5723 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5724 {
5725         unsigned long exit_qualification;
5726         gpa_t gpa;
5727         u32 error_code;
5728         int gla_validity;
5729
5730         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5731
5732         gla_validity = (exit_qualification >> 7) & 0x3;
5733         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5734                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5735                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5736                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5737                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5738                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5739                         (long unsigned int)exit_qualification);
5740                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5741                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5742                 return 0;
5743         }
5744
5745         /*
5746          * EPT violation happened while executing iret from NMI,
5747          * "blocked by NMI" bit has to be set before next VM entry.
5748          * There are errata that may cause this bit to not be set:
5749          * AAK134, BY25.
5750          */
5751         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5752                         cpu_has_virtual_nmis() &&
5753                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5754                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5755
5756         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5757         trace_kvm_page_fault(gpa, exit_qualification);
5758
5759         /* It is a write fault? */
5760         error_code = exit_qualification & PFERR_WRITE_MASK;
5761         /* It is a fetch fault? */
5762         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5763         /* ept page table is present? */
5764         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5765
5766         vcpu->arch.exit_qualification = exit_qualification;
5767
5768         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5769 }
5770
5771 static u64 ept_rsvd_mask(u64 spte, int level)
5772 {
5773         int i;
5774         u64 mask = 0;
5775
5776         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5777                 mask |= (1ULL << i);
5778
5779         if (level == 4)
5780                 /* bits 7:3 reserved */
5781                 mask |= 0xf8;
5782         else if (spte & (1ULL << 7))
5783                 /*
5784                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5785                  * level == 1 if the hypervisor is using the ignored bit 7.
5786                  */
5787                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5788         else if (level > 1)
5789                 /* bits 6:3 reserved */
5790                 mask |= 0x78;
5791
5792         return mask;
5793 }
5794
5795 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5796                                        int level)
5797 {
5798         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5799
5800         /* 010b (write-only) */
5801         WARN_ON((spte & 0x7) == 0x2);
5802
5803         /* 110b (write/execute) */
5804         WARN_ON((spte & 0x7) == 0x6);
5805
5806         /* 100b (execute-only) and value not supported by logical processor */
5807         if (!cpu_has_vmx_ept_execute_only())
5808                 WARN_ON((spte & 0x7) == 0x4);
5809
5810         /* not 000b */
5811         if ((spte & 0x7)) {
5812                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5813
5814                 if (rsvd_bits != 0) {
5815                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5816                                          __func__, rsvd_bits);
5817                         WARN_ON(1);
5818                 }
5819
5820                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5821                 if ((rsvd_bits & 0x38) == 0) {
5822                         u64 ept_mem_type = (spte & 0x38) >> 3;
5823
5824                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5825                             ept_mem_type == 7) {
5826                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5827                                                 __func__, ept_mem_type);
5828                                 WARN_ON(1);
5829                         }
5830                 }
5831         }
5832 }
5833
5834 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5835 {
5836         u64 sptes[4];
5837         int nr_sptes, i, ret;
5838         gpa_t gpa;
5839
5840         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5841         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5842                 skip_emulated_instruction(vcpu);
5843                 return 1;
5844         }
5845
5846         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5847         if (likely(ret == RET_MMIO_PF_EMULATE))
5848                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5849                                               EMULATE_DONE;
5850
5851         if (unlikely(ret == RET_MMIO_PF_INVALID))
5852                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5853
5854         if (unlikely(ret == RET_MMIO_PF_RETRY))
5855                 return 1;
5856
5857         /* It is the real ept misconfig */
5858         printk(KERN_ERR "EPT: Misconfiguration.\n");
5859         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5860
5861         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5862
5863         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5864                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5865
5866         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5867         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5868
5869         return 0;
5870 }
5871
5872 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5873 {
5874         u32 cpu_based_vm_exec_control;
5875
5876         /* clear pending NMI */
5877         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5878         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5879         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5880         ++vcpu->stat.nmi_window_exits;
5881         kvm_make_request(KVM_REQ_EVENT, vcpu);
5882
5883         return 1;
5884 }
5885
5886 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5887 {
5888         struct vcpu_vmx *vmx = to_vmx(vcpu);
5889         enum emulation_result err = EMULATE_DONE;
5890         int ret = 1;
5891         u32 cpu_exec_ctrl;
5892         bool intr_window_requested;
5893         unsigned count = 130;
5894
5895         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5896         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5897
5898         while (vmx->emulation_required && count-- != 0) {
5899                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5900                         return handle_interrupt_window(&vmx->vcpu);
5901
5902                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5903                         return 1;
5904
5905                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5906
5907                 if (err == EMULATE_USER_EXIT) {
5908                         ++vcpu->stat.mmio_exits;
5909                         ret = 0;
5910                         goto out;
5911                 }
5912
5913                 if (err != EMULATE_DONE) {
5914                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5915                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5916                         vcpu->run->internal.ndata = 0;
5917                         return 0;
5918                 }
5919
5920                 if (vcpu->arch.halt_request) {
5921                         vcpu->arch.halt_request = 0;
5922                         ret = kvm_vcpu_halt(vcpu);
5923                         goto out;
5924                 }
5925
5926                 if (signal_pending(current))
5927                         goto out;
5928                 if (need_resched())
5929                         schedule();
5930         }
5931
5932 out:
5933         return ret;
5934 }
5935
5936 static int __grow_ple_window(int val)
5937 {
5938         if (ple_window_grow < 1)
5939                 return ple_window;
5940
5941         val = min(val, ple_window_actual_max);
5942
5943         if (ple_window_grow < ple_window)
5944                 val *= ple_window_grow;
5945         else
5946                 val += ple_window_grow;
5947
5948         return val;
5949 }
5950
5951 static int __shrink_ple_window(int val, int modifier, int minimum)
5952 {
5953         if (modifier < 1)
5954                 return ple_window;
5955
5956         if (modifier < ple_window)
5957                 val /= modifier;
5958         else
5959                 val -= modifier;
5960
5961         return max(val, minimum);
5962 }
5963
5964 static void grow_ple_window(struct kvm_vcpu *vcpu)
5965 {
5966         struct vcpu_vmx *vmx = to_vmx(vcpu);
5967         int old = vmx->ple_window;
5968
5969         vmx->ple_window = __grow_ple_window(old);
5970
5971         if (vmx->ple_window != old)
5972                 vmx->ple_window_dirty = true;
5973
5974         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5975 }
5976
5977 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5978 {
5979         struct vcpu_vmx *vmx = to_vmx(vcpu);
5980         int old = vmx->ple_window;
5981
5982         vmx->ple_window = __shrink_ple_window(old,
5983                                               ple_window_shrink, ple_window);
5984
5985         if (vmx->ple_window != old)
5986                 vmx->ple_window_dirty = true;
5987
5988         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5989 }
5990
5991 /*
5992  * ple_window_actual_max is computed to be one grow_ple_window() below
5993  * ple_window_max. (See __grow_ple_window for the reason.)
5994  * This prevents overflows, because ple_window_max is int.
5995  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5996  * this process.
5997  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5998  */
5999 static void update_ple_window_actual_max(void)
6000 {
6001         ple_window_actual_max =
6002                         __shrink_ple_window(max(ple_window_max, ple_window),
6003                                             ple_window_grow, INT_MIN);
6004 }
6005
6006 static __init int hardware_setup(void)
6007 {
6008         int r = -ENOMEM, i, msr;
6009
6010         rdmsrl_safe(MSR_EFER, &host_efer);
6011
6012         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6013                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6014
6015         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6016         if (!vmx_io_bitmap_a)
6017                 return r;
6018
6019         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6020         if (!vmx_io_bitmap_b)
6021                 goto out;
6022
6023         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6024         if (!vmx_msr_bitmap_legacy)
6025                 goto out1;
6026
6027         vmx_msr_bitmap_legacy_x2apic =
6028                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6029         if (!vmx_msr_bitmap_legacy_x2apic)
6030                 goto out2;
6031
6032         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6033         if (!vmx_msr_bitmap_longmode)
6034                 goto out3;
6035
6036         vmx_msr_bitmap_longmode_x2apic =
6037                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6038         if (!vmx_msr_bitmap_longmode_x2apic)
6039                 goto out4;
6040
6041         if (nested) {
6042                 vmx_msr_bitmap_nested =
6043                         (unsigned long *)__get_free_page(GFP_KERNEL);
6044                 if (!vmx_msr_bitmap_nested)
6045                         goto out5;
6046         }
6047
6048         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6049         if (!vmx_vmread_bitmap)
6050                 goto out6;
6051
6052         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6053         if (!vmx_vmwrite_bitmap)
6054                 goto out7;
6055
6056         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6057         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6058
6059         /*
6060          * Allow direct access to the PC debug port (it is often used for I/O
6061          * delays, but the vmexits simply slow things down).
6062          */
6063         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6064         clear_bit(0x80, vmx_io_bitmap_a);
6065
6066         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6067
6068         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6069         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6070         if (nested)
6071                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6072
6073         if (setup_vmcs_config(&vmcs_config) < 0) {
6074                 r = -EIO;
6075                 goto out8;
6076         }
6077
6078         if (boot_cpu_has(X86_FEATURE_NX))
6079                 kvm_enable_efer_bits(EFER_NX);
6080
6081         if (!cpu_has_vmx_vpid())
6082                 enable_vpid = 0;
6083         if (!cpu_has_vmx_shadow_vmcs())
6084                 enable_shadow_vmcs = 0;
6085         if (enable_shadow_vmcs)
6086                 init_vmcs_shadow_fields();
6087
6088         if (!cpu_has_vmx_ept() ||
6089             !cpu_has_vmx_ept_4levels()) {
6090                 enable_ept = 0;
6091                 enable_unrestricted_guest = 0;
6092                 enable_ept_ad_bits = 0;
6093         }
6094
6095         if (!cpu_has_vmx_ept_ad_bits())
6096                 enable_ept_ad_bits = 0;
6097
6098         if (!cpu_has_vmx_unrestricted_guest())
6099                 enable_unrestricted_guest = 0;
6100
6101         if (!cpu_has_vmx_flexpriority())
6102                 flexpriority_enabled = 0;
6103
6104         /*
6105          * set_apic_access_page_addr() is used to reload apic access
6106          * page upon invalidation.  No need to do anything if not
6107          * using the APIC_ACCESS_ADDR VMCS field.
6108          */
6109         if (!flexpriority_enabled)
6110                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6111
6112         if (!cpu_has_vmx_tpr_shadow())
6113                 kvm_x86_ops->update_cr8_intercept = NULL;
6114
6115         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6116                 kvm_disable_largepages();
6117
6118         if (!cpu_has_vmx_ple())
6119                 ple_gap = 0;
6120
6121         if (!cpu_has_vmx_apicv())
6122                 enable_apicv = 0;
6123
6124         if (enable_apicv)
6125                 kvm_x86_ops->update_cr8_intercept = NULL;
6126         else {
6127                 kvm_x86_ops->hwapic_irr_update = NULL;
6128                 kvm_x86_ops->hwapic_isr_update = NULL;
6129                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6130                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6131         }
6132
6133         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6134         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6135         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6136         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6137         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6138         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6139         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6140
6141         memcpy(vmx_msr_bitmap_legacy_x2apic,
6142                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6143         memcpy(vmx_msr_bitmap_longmode_x2apic,
6144                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6145
6146         if (enable_apicv) {
6147                 for (msr = 0x800; msr <= 0x8ff; msr++)
6148                         vmx_disable_intercept_msr_read_x2apic(msr);
6149
6150                 /* According SDM, in x2apic mode, the whole id reg is used.
6151                  * But in KVM, it only use the highest eight bits. Need to
6152                  * intercept it */
6153                 vmx_enable_intercept_msr_read_x2apic(0x802);
6154                 /* TMCCT */
6155                 vmx_enable_intercept_msr_read_x2apic(0x839);
6156                 /* TPR */
6157                 vmx_disable_intercept_msr_write_x2apic(0x808);
6158                 /* EOI */
6159                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6160                 /* SELF-IPI */
6161                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6162         }
6163
6164         if (enable_ept) {
6165                 kvm_mmu_set_mask_ptes(0ull,
6166                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6167                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6168                         0ull, VMX_EPT_EXECUTABLE_MASK);
6169                 ept_set_mmio_spte_mask();
6170                 kvm_enable_tdp();
6171         } else
6172                 kvm_disable_tdp();
6173
6174         update_ple_window_actual_max();
6175
6176         /*
6177          * Only enable PML when hardware supports PML feature, and both EPT
6178          * and EPT A/D bit features are enabled -- PML depends on them to work.
6179          */
6180         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6181                 enable_pml = 0;
6182
6183         if (!enable_pml) {
6184                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6185                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6186                 kvm_x86_ops->flush_log_dirty = NULL;
6187                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6188         }
6189
6190         return alloc_kvm_area();
6191
6192 out8:
6193         free_page((unsigned long)vmx_vmwrite_bitmap);
6194 out7:
6195         free_page((unsigned long)vmx_vmread_bitmap);
6196 out6:
6197         if (nested)
6198                 free_page((unsigned long)vmx_msr_bitmap_nested);
6199 out5:
6200         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6201 out4:
6202         free_page((unsigned long)vmx_msr_bitmap_longmode);
6203 out3:
6204         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6205 out2:
6206         free_page((unsigned long)vmx_msr_bitmap_legacy);
6207 out1:
6208         free_page((unsigned long)vmx_io_bitmap_b);
6209 out:
6210         free_page((unsigned long)vmx_io_bitmap_a);
6211
6212     return r;
6213 }
6214
6215 static __exit void hardware_unsetup(void)
6216 {
6217         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6218         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6219         free_page((unsigned long)vmx_msr_bitmap_legacy);
6220         free_page((unsigned long)vmx_msr_bitmap_longmode);
6221         free_page((unsigned long)vmx_io_bitmap_b);
6222         free_page((unsigned long)vmx_io_bitmap_a);
6223         free_page((unsigned long)vmx_vmwrite_bitmap);
6224         free_page((unsigned long)vmx_vmread_bitmap);
6225         if (nested)
6226                 free_page((unsigned long)vmx_msr_bitmap_nested);
6227
6228         free_kvm_area();
6229 }
6230
6231 /*
6232  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6233  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6234  */
6235 static int handle_pause(struct kvm_vcpu *vcpu)
6236 {
6237         if (ple_gap)
6238                 grow_ple_window(vcpu);
6239
6240         skip_emulated_instruction(vcpu);
6241         kvm_vcpu_on_spin(vcpu);
6242
6243         return 1;
6244 }
6245
6246 static int handle_nop(struct kvm_vcpu *vcpu)
6247 {
6248         skip_emulated_instruction(vcpu);
6249         return 1;
6250 }
6251
6252 static int handle_mwait(struct kvm_vcpu *vcpu)
6253 {
6254         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6255         return handle_nop(vcpu);
6256 }
6257
6258 static int handle_monitor(struct kvm_vcpu *vcpu)
6259 {
6260         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6261         return handle_nop(vcpu);
6262 }
6263
6264 /*
6265  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6266  * We could reuse a single VMCS for all the L2 guests, but we also want the
6267  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6268  * allows keeping them loaded on the processor, and in the future will allow
6269  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6270  * every entry if they never change.
6271  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6272  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6273  *
6274  * The following functions allocate and free a vmcs02 in this pool.
6275  */
6276
6277 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6278 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6279 {
6280         struct vmcs02_list *item;
6281         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6282                 if (item->vmptr == vmx->nested.current_vmptr) {
6283                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6284                         return &item->vmcs02;
6285                 }
6286
6287         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6288                 /* Recycle the least recently used VMCS. */
6289                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6290                         struct vmcs02_list, list);
6291                 item->vmptr = vmx->nested.current_vmptr;
6292                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6293                 return &item->vmcs02;
6294         }
6295
6296         /* Create a new VMCS */
6297         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6298         if (!item)
6299                 return NULL;
6300         item->vmcs02.vmcs = alloc_vmcs();
6301         if (!item->vmcs02.vmcs) {
6302                 kfree(item);
6303                 return NULL;
6304         }
6305         loaded_vmcs_init(&item->vmcs02);
6306         item->vmptr = vmx->nested.current_vmptr;
6307         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6308         vmx->nested.vmcs02_num++;
6309         return &item->vmcs02;
6310 }
6311
6312 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6313 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6314 {
6315         struct vmcs02_list *item;
6316         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6317                 if (item->vmptr == vmptr) {
6318                         free_loaded_vmcs(&item->vmcs02);
6319                         list_del(&item->list);
6320                         kfree(item);
6321                         vmx->nested.vmcs02_num--;
6322                         return;
6323                 }
6324 }
6325
6326 /*
6327  * Free all VMCSs saved for this vcpu, except the one pointed by
6328  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6329  * must be &vmx->vmcs01.
6330  */
6331 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6332 {
6333         struct vmcs02_list *item, *n;
6334
6335         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6336         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6337                 /*
6338                  * Something will leak if the above WARN triggers.  Better than
6339                  * a use-after-free.
6340                  */
6341                 if (vmx->loaded_vmcs == &item->vmcs02)
6342                         continue;
6343
6344                 free_loaded_vmcs(&item->vmcs02);
6345                 list_del(&item->list);
6346                 kfree(item);
6347                 vmx->nested.vmcs02_num--;
6348         }
6349 }
6350
6351 /*
6352  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6353  * set the success or error code of an emulated VMX instruction, as specified
6354  * by Vol 2B, VMX Instruction Reference, "Conventions".
6355  */
6356 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6357 {
6358         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6359                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6360                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6361 }
6362
6363 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6364 {
6365         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6366                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6367                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6368                         | X86_EFLAGS_CF);
6369 }
6370
6371 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6372                                         u32 vm_instruction_error)
6373 {
6374         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6375                 /*
6376                  * failValid writes the error number to the current VMCS, which
6377                  * can't be done there isn't a current VMCS.
6378                  */
6379                 nested_vmx_failInvalid(vcpu);
6380                 return;
6381         }
6382         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6383                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6384                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6385                         | X86_EFLAGS_ZF);
6386         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6387         /*
6388          * We don't need to force a shadow sync because
6389          * VM_INSTRUCTION_ERROR is not shadowed
6390          */
6391 }
6392
6393 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6394 {
6395         /* TODO: not to reset guest simply here. */
6396         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6397         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6398 }
6399
6400 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6401 {
6402         struct vcpu_vmx *vmx =
6403                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6404
6405         vmx->nested.preemption_timer_expired = true;
6406         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6407         kvm_vcpu_kick(&vmx->vcpu);
6408
6409         return HRTIMER_NORESTART;
6410 }
6411
6412 /*
6413  * Decode the memory-address operand of a vmx instruction, as recorded on an
6414  * exit caused by such an instruction (run by a guest hypervisor).
6415  * On success, returns 0. When the operand is invalid, returns 1 and throws
6416  * #UD or #GP.
6417  */
6418 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6419                                  unsigned long exit_qualification,
6420                                  u32 vmx_instruction_info, gva_t *ret)
6421 {
6422         /*
6423          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6424          * Execution", on an exit, vmx_instruction_info holds most of the
6425          * addressing components of the operand. Only the displacement part
6426          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6427          * For how an actual address is calculated from all these components,
6428          * refer to Vol. 1, "Operand Addressing".
6429          */
6430         int  scaling = vmx_instruction_info & 3;
6431         int  addr_size = (vmx_instruction_info >> 7) & 7;
6432         bool is_reg = vmx_instruction_info & (1u << 10);
6433         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6434         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6435         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6436         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6437         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6438
6439         if (is_reg) {
6440                 kvm_queue_exception(vcpu, UD_VECTOR);
6441                 return 1;
6442         }
6443
6444         /* Addr = segment_base + offset */
6445         /* offset = base + [index * scale] + displacement */
6446         *ret = vmx_get_segment_base(vcpu, seg_reg);
6447         if (base_is_valid)
6448                 *ret += kvm_register_read(vcpu, base_reg);
6449         if (index_is_valid)
6450                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6451         *ret += exit_qualification; /* holds the displacement */
6452
6453         if (addr_size == 1) /* 32 bit */
6454                 *ret &= 0xffffffff;
6455
6456         /*
6457          * TODO: throw #GP (and return 1) in various cases that the VM*
6458          * instructions require it - e.g., offset beyond segment limit,
6459          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6460          * address, and so on. Currently these are not checked.
6461          */
6462         return 0;
6463 }
6464
6465 /*
6466  * This function performs the various checks including
6467  * - if it's 4KB aligned
6468  * - No bits beyond the physical address width are set
6469  * - Returns 0 on success or else 1
6470  * (Intel SDM Section 30.3)
6471  */
6472 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6473                                   gpa_t *vmpointer)
6474 {
6475         gva_t gva;
6476         gpa_t vmptr;
6477         struct x86_exception e;
6478         struct page *page;
6479         struct vcpu_vmx *vmx = to_vmx(vcpu);
6480         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6481
6482         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6483                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6484                 return 1;
6485
6486         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6487                                 sizeof(vmptr), &e)) {
6488                 kvm_inject_page_fault(vcpu, &e);
6489                 return 1;
6490         }
6491
6492         switch (exit_reason) {
6493         case EXIT_REASON_VMON:
6494                 /*
6495                  * SDM 3: 24.11.5
6496                  * The first 4 bytes of VMXON region contain the supported
6497                  * VMCS revision identifier
6498                  *
6499                  * Note - IA32_VMX_BASIC[48] will never be 1
6500                  * for the nested case;
6501                  * which replaces physical address width with 32
6502                  *
6503                  */
6504                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6505                         nested_vmx_failInvalid(vcpu);
6506                         skip_emulated_instruction(vcpu);
6507                         return 1;
6508                 }
6509
6510                 page = nested_get_page(vcpu, vmptr);
6511                 if (page == NULL ||
6512                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6513                         nested_vmx_failInvalid(vcpu);
6514                         kunmap(page);
6515                         skip_emulated_instruction(vcpu);
6516                         return 1;
6517                 }
6518                 kunmap(page);
6519                 vmx->nested.vmxon_ptr = vmptr;
6520                 break;
6521         case EXIT_REASON_VMCLEAR:
6522                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6523                         nested_vmx_failValid(vcpu,
6524                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6525                         skip_emulated_instruction(vcpu);
6526                         return 1;
6527                 }
6528
6529                 if (vmptr == vmx->nested.vmxon_ptr) {
6530                         nested_vmx_failValid(vcpu,
6531                                              VMXERR_VMCLEAR_VMXON_POINTER);
6532                         skip_emulated_instruction(vcpu);
6533                         return 1;
6534                 }
6535                 break;
6536         case EXIT_REASON_VMPTRLD:
6537                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6538                         nested_vmx_failValid(vcpu,
6539                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6540                         skip_emulated_instruction(vcpu);
6541                         return 1;
6542                 }
6543
6544                 if (vmptr == vmx->nested.vmxon_ptr) {
6545                         nested_vmx_failValid(vcpu,
6546                                              VMXERR_VMCLEAR_VMXON_POINTER);
6547                         skip_emulated_instruction(vcpu);
6548                         return 1;
6549                 }
6550                 break;
6551         default:
6552                 return 1; /* shouldn't happen */
6553         }
6554
6555         if (vmpointer)
6556                 *vmpointer = vmptr;
6557         return 0;
6558 }
6559
6560 /*
6561  * Emulate the VMXON instruction.
6562  * Currently, we just remember that VMX is active, and do not save or even
6563  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6564  * do not currently need to store anything in that guest-allocated memory
6565  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6566  * argument is different from the VMXON pointer (which the spec says they do).
6567  */
6568 static int handle_vmon(struct kvm_vcpu *vcpu)
6569 {
6570         struct kvm_segment cs;
6571         struct vcpu_vmx *vmx = to_vmx(vcpu);
6572         struct vmcs *shadow_vmcs;
6573         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6574                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6575
6576         /* The Intel VMX Instruction Reference lists a bunch of bits that
6577          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6578          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6579          * Otherwise, we should fail with #UD. We test these now:
6580          */
6581         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6582             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6583             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6584                 kvm_queue_exception(vcpu, UD_VECTOR);
6585                 return 1;
6586         }
6587
6588         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6589         if (is_long_mode(vcpu) && !cs.l) {
6590                 kvm_queue_exception(vcpu, UD_VECTOR);
6591                 return 1;
6592         }
6593
6594         if (vmx_get_cpl(vcpu)) {
6595                 kvm_inject_gp(vcpu, 0);
6596                 return 1;
6597         }
6598
6599         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6600                 return 1;
6601
6602         if (vmx->nested.vmxon) {
6603                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6604                 skip_emulated_instruction(vcpu);
6605                 return 1;
6606         }
6607
6608         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6609                         != VMXON_NEEDED_FEATURES) {
6610                 kvm_inject_gp(vcpu, 0);
6611                 return 1;
6612         }
6613
6614         if (enable_shadow_vmcs) {
6615                 shadow_vmcs = alloc_vmcs();
6616                 if (!shadow_vmcs)
6617                         return -ENOMEM;
6618                 /* mark vmcs as shadow */
6619                 shadow_vmcs->revision_id |= (1u << 31);
6620                 /* init shadow vmcs */
6621                 vmcs_clear(shadow_vmcs);
6622                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6623         }
6624
6625         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6626         vmx->nested.vmcs02_num = 0;
6627
6628         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6629                      HRTIMER_MODE_REL);
6630         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6631
6632         vmx->nested.vmxon = true;
6633
6634         skip_emulated_instruction(vcpu);
6635         nested_vmx_succeed(vcpu);
6636         return 1;
6637 }
6638
6639 /*
6640  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6641  * for running VMX instructions (except VMXON, whose prerequisites are
6642  * slightly different). It also specifies what exception to inject otherwise.
6643  */
6644 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6645 {
6646         struct kvm_segment cs;
6647         struct vcpu_vmx *vmx = to_vmx(vcpu);
6648
6649         if (!vmx->nested.vmxon) {
6650                 kvm_queue_exception(vcpu, UD_VECTOR);
6651                 return 0;
6652         }
6653
6654         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6655         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6656             (is_long_mode(vcpu) && !cs.l)) {
6657                 kvm_queue_exception(vcpu, UD_VECTOR);
6658                 return 0;
6659         }
6660
6661         if (vmx_get_cpl(vcpu)) {
6662                 kvm_inject_gp(vcpu, 0);
6663                 return 0;
6664         }
6665
6666         return 1;
6667 }
6668
6669 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6670 {
6671         u32 exec_control;
6672         if (vmx->nested.current_vmptr == -1ull)
6673                 return;
6674
6675         /* current_vmptr and current_vmcs12 are always set/reset together */
6676         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6677                 return;
6678
6679         if (enable_shadow_vmcs) {
6680                 /* copy to memory all shadowed fields in case
6681                    they were modified */
6682                 copy_shadow_to_vmcs12(vmx);
6683                 vmx->nested.sync_shadow_vmcs = false;
6684                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6685                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6686                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6687                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6688         }
6689         vmx->nested.posted_intr_nv = -1;
6690         kunmap(vmx->nested.current_vmcs12_page);
6691         nested_release_page(vmx->nested.current_vmcs12_page);
6692         vmx->nested.current_vmptr = -1ull;
6693         vmx->nested.current_vmcs12 = NULL;
6694 }
6695
6696 /*
6697  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6698  * just stops using VMX.
6699  */
6700 static void free_nested(struct vcpu_vmx *vmx)
6701 {
6702         if (!vmx->nested.vmxon)
6703                 return;
6704
6705         vmx->nested.vmxon = false;
6706         nested_release_vmcs12(vmx);
6707         if (enable_shadow_vmcs)
6708                 free_vmcs(vmx->nested.current_shadow_vmcs);
6709         /* Unpin physical memory we referred to in current vmcs02 */
6710         if (vmx->nested.apic_access_page) {
6711                 nested_release_page(vmx->nested.apic_access_page);
6712                 vmx->nested.apic_access_page = NULL;
6713         }
6714         if (vmx->nested.virtual_apic_page) {
6715                 nested_release_page(vmx->nested.virtual_apic_page);
6716                 vmx->nested.virtual_apic_page = NULL;
6717         }
6718         if (vmx->nested.pi_desc_page) {
6719                 kunmap(vmx->nested.pi_desc_page);
6720                 nested_release_page(vmx->nested.pi_desc_page);
6721                 vmx->nested.pi_desc_page = NULL;
6722                 vmx->nested.pi_desc = NULL;
6723         }
6724
6725         nested_free_all_saved_vmcss(vmx);
6726 }
6727
6728 /* Emulate the VMXOFF instruction */
6729 static int handle_vmoff(struct kvm_vcpu *vcpu)
6730 {
6731         if (!nested_vmx_check_permission(vcpu))
6732                 return 1;
6733         free_nested(to_vmx(vcpu));
6734         skip_emulated_instruction(vcpu);
6735         nested_vmx_succeed(vcpu);
6736         return 1;
6737 }
6738
6739 /* Emulate the VMCLEAR instruction */
6740 static int handle_vmclear(struct kvm_vcpu *vcpu)
6741 {
6742         struct vcpu_vmx *vmx = to_vmx(vcpu);
6743         gpa_t vmptr;
6744         struct vmcs12 *vmcs12;
6745         struct page *page;
6746
6747         if (!nested_vmx_check_permission(vcpu))
6748                 return 1;
6749
6750         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6751                 return 1;
6752
6753         if (vmptr == vmx->nested.current_vmptr)
6754                 nested_release_vmcs12(vmx);
6755
6756         page = nested_get_page(vcpu, vmptr);
6757         if (page == NULL) {
6758                 /*
6759                  * For accurate processor emulation, VMCLEAR beyond available
6760                  * physical memory should do nothing at all. However, it is
6761                  * possible that a nested vmx bug, not a guest hypervisor bug,
6762                  * resulted in this case, so let's shut down before doing any
6763                  * more damage:
6764                  */
6765                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6766                 return 1;
6767         }
6768         vmcs12 = kmap(page);
6769         vmcs12->launch_state = 0;
6770         kunmap(page);
6771         nested_release_page(page);
6772
6773         nested_free_vmcs02(vmx, vmptr);
6774
6775         skip_emulated_instruction(vcpu);
6776         nested_vmx_succeed(vcpu);
6777         return 1;
6778 }
6779
6780 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6781
6782 /* Emulate the VMLAUNCH instruction */
6783 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6784 {
6785         return nested_vmx_run(vcpu, true);
6786 }
6787
6788 /* Emulate the VMRESUME instruction */
6789 static int handle_vmresume(struct kvm_vcpu *vcpu)
6790 {
6791
6792         return nested_vmx_run(vcpu, false);
6793 }
6794
6795 enum vmcs_field_type {
6796         VMCS_FIELD_TYPE_U16 = 0,
6797         VMCS_FIELD_TYPE_U64 = 1,
6798         VMCS_FIELD_TYPE_U32 = 2,
6799         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6800 };
6801
6802 static inline int vmcs_field_type(unsigned long field)
6803 {
6804         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6805                 return VMCS_FIELD_TYPE_U32;
6806         return (field >> 13) & 0x3 ;
6807 }
6808
6809 static inline int vmcs_field_readonly(unsigned long field)
6810 {
6811         return (((field >> 10) & 0x3) == 1);
6812 }
6813
6814 /*
6815  * Read a vmcs12 field. Since these can have varying lengths and we return
6816  * one type, we chose the biggest type (u64) and zero-extend the return value
6817  * to that size. Note that the caller, handle_vmread, might need to use only
6818  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6819  * 64-bit fields are to be returned).
6820  */
6821 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6822                                   unsigned long field, u64 *ret)
6823 {
6824         short offset = vmcs_field_to_offset(field);
6825         char *p;
6826
6827         if (offset < 0)
6828                 return offset;
6829
6830         p = ((char *)(get_vmcs12(vcpu))) + offset;
6831
6832         switch (vmcs_field_type(field)) {
6833         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6834                 *ret = *((natural_width *)p);
6835                 return 0;
6836         case VMCS_FIELD_TYPE_U16:
6837                 *ret = *((u16 *)p);
6838                 return 0;
6839         case VMCS_FIELD_TYPE_U32:
6840                 *ret = *((u32 *)p);
6841                 return 0;
6842         case VMCS_FIELD_TYPE_U64:
6843                 *ret = *((u64 *)p);
6844                 return 0;
6845         default:
6846                 WARN_ON(1);
6847                 return -ENOENT;
6848         }
6849 }
6850
6851
6852 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6853                                    unsigned long field, u64 field_value){
6854         short offset = vmcs_field_to_offset(field);
6855         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6856         if (offset < 0)
6857                 return offset;
6858
6859         switch (vmcs_field_type(field)) {
6860         case VMCS_FIELD_TYPE_U16:
6861                 *(u16 *)p = field_value;
6862                 return 0;
6863         case VMCS_FIELD_TYPE_U32:
6864                 *(u32 *)p = field_value;
6865                 return 0;
6866         case VMCS_FIELD_TYPE_U64:
6867                 *(u64 *)p = field_value;
6868                 return 0;
6869         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6870                 *(natural_width *)p = field_value;
6871                 return 0;
6872         default:
6873                 WARN_ON(1);
6874                 return -ENOENT;
6875         }
6876
6877 }
6878
6879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6880 {
6881         int i;
6882         unsigned long field;
6883         u64 field_value;
6884         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6885         const unsigned long *fields = shadow_read_write_fields;
6886         const int num_fields = max_shadow_read_write_fields;
6887
6888         preempt_disable();
6889
6890         vmcs_load(shadow_vmcs);
6891
6892         for (i = 0; i < num_fields; i++) {
6893                 field = fields[i];
6894                 switch (vmcs_field_type(field)) {
6895                 case VMCS_FIELD_TYPE_U16:
6896                         field_value = vmcs_read16(field);
6897                         break;
6898                 case VMCS_FIELD_TYPE_U32:
6899                         field_value = vmcs_read32(field);
6900                         break;
6901                 case VMCS_FIELD_TYPE_U64:
6902                         field_value = vmcs_read64(field);
6903                         break;
6904                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6905                         field_value = vmcs_readl(field);
6906                         break;
6907                 default:
6908                         WARN_ON(1);
6909                         continue;
6910                 }
6911                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6912         }
6913
6914         vmcs_clear(shadow_vmcs);
6915         vmcs_load(vmx->loaded_vmcs->vmcs);
6916
6917         preempt_enable();
6918 }
6919
6920 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6921 {
6922         const unsigned long *fields[] = {
6923                 shadow_read_write_fields,
6924                 shadow_read_only_fields
6925         };
6926         const int max_fields[] = {
6927                 max_shadow_read_write_fields,
6928                 max_shadow_read_only_fields
6929         };
6930         int i, q;
6931         unsigned long field;
6932         u64 field_value = 0;
6933         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6934
6935         vmcs_load(shadow_vmcs);
6936
6937         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6938                 for (i = 0; i < max_fields[q]; i++) {
6939                         field = fields[q][i];
6940                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6941
6942                         switch (vmcs_field_type(field)) {
6943                         case VMCS_FIELD_TYPE_U16:
6944                                 vmcs_write16(field, (u16)field_value);
6945                                 break;
6946                         case VMCS_FIELD_TYPE_U32:
6947                                 vmcs_write32(field, (u32)field_value);
6948                                 break;
6949                         case VMCS_FIELD_TYPE_U64:
6950                                 vmcs_write64(field, (u64)field_value);
6951                                 break;
6952                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6953                                 vmcs_writel(field, (long)field_value);
6954                                 break;
6955                         default:
6956                                 WARN_ON(1);
6957                                 break;
6958                         }
6959                 }
6960         }
6961
6962         vmcs_clear(shadow_vmcs);
6963         vmcs_load(vmx->loaded_vmcs->vmcs);
6964 }
6965
6966 /*
6967  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6968  * used before) all generate the same failure when it is missing.
6969  */
6970 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6971 {
6972         struct vcpu_vmx *vmx = to_vmx(vcpu);
6973         if (vmx->nested.current_vmptr == -1ull) {
6974                 nested_vmx_failInvalid(vcpu);
6975                 skip_emulated_instruction(vcpu);
6976                 return 0;
6977         }
6978         return 1;
6979 }
6980
6981 static int handle_vmread(struct kvm_vcpu *vcpu)
6982 {
6983         unsigned long field;
6984         u64 field_value;
6985         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6986         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6987         gva_t gva = 0;
6988
6989         if (!nested_vmx_check_permission(vcpu) ||
6990             !nested_vmx_check_vmcs12(vcpu))
6991                 return 1;
6992
6993         /* Decode instruction info and find the field to read */
6994         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6995         /* Read the field, zero-extended to a u64 field_value */
6996         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6997                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6998                 skip_emulated_instruction(vcpu);
6999                 return 1;
7000         }
7001         /*
7002          * Now copy part of this value to register or memory, as requested.
7003          * Note that the number of bits actually copied is 32 or 64 depending
7004          * on the guest's mode (32 or 64 bit), not on the given field's length.
7005          */
7006         if (vmx_instruction_info & (1u << 10)) {
7007                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7008                         field_value);
7009         } else {
7010                 if (get_vmx_mem_address(vcpu, exit_qualification,
7011                                 vmx_instruction_info, &gva))
7012                         return 1;
7013                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7014                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7015                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7016         }
7017
7018         nested_vmx_succeed(vcpu);
7019         skip_emulated_instruction(vcpu);
7020         return 1;
7021 }
7022
7023
7024 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7025 {
7026         unsigned long field;
7027         gva_t gva;
7028         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7029         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7030         /* The value to write might be 32 or 64 bits, depending on L1's long
7031          * mode, and eventually we need to write that into a field of several
7032          * possible lengths. The code below first zero-extends the value to 64
7033          * bit (field_value), and then copies only the approriate number of
7034          * bits into the vmcs12 field.
7035          */
7036         u64 field_value = 0;
7037         struct x86_exception e;
7038
7039         if (!nested_vmx_check_permission(vcpu) ||
7040             !nested_vmx_check_vmcs12(vcpu))
7041                 return 1;
7042
7043         if (vmx_instruction_info & (1u << 10))
7044                 field_value = kvm_register_readl(vcpu,
7045                         (((vmx_instruction_info) >> 3) & 0xf));
7046         else {
7047                 if (get_vmx_mem_address(vcpu, exit_qualification,
7048                                 vmx_instruction_info, &gva))
7049                         return 1;
7050                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7051                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7052                         kvm_inject_page_fault(vcpu, &e);
7053                         return 1;
7054                 }
7055         }
7056
7057
7058         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7059         if (vmcs_field_readonly(field)) {
7060                 nested_vmx_failValid(vcpu,
7061                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7062                 skip_emulated_instruction(vcpu);
7063                 return 1;
7064         }
7065
7066         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7067                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7068                 skip_emulated_instruction(vcpu);
7069                 return 1;
7070         }
7071
7072         nested_vmx_succeed(vcpu);
7073         skip_emulated_instruction(vcpu);
7074         return 1;
7075 }
7076
7077 /* Emulate the VMPTRLD instruction */
7078 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7079 {
7080         struct vcpu_vmx *vmx = to_vmx(vcpu);
7081         gpa_t vmptr;
7082         u32 exec_control;
7083
7084         if (!nested_vmx_check_permission(vcpu))
7085                 return 1;
7086
7087         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7088                 return 1;
7089
7090         if (vmx->nested.current_vmptr != vmptr) {
7091                 struct vmcs12 *new_vmcs12;
7092                 struct page *page;
7093                 page = nested_get_page(vcpu, vmptr);
7094                 if (page == NULL) {
7095                         nested_vmx_failInvalid(vcpu);
7096                         skip_emulated_instruction(vcpu);
7097                         return 1;
7098                 }
7099                 new_vmcs12 = kmap(page);
7100                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7101                         kunmap(page);
7102                         nested_release_page_clean(page);
7103                         nested_vmx_failValid(vcpu,
7104                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7105                         skip_emulated_instruction(vcpu);
7106                         return 1;
7107                 }
7108
7109                 nested_release_vmcs12(vmx);
7110                 vmx->nested.current_vmptr = vmptr;
7111                 vmx->nested.current_vmcs12 = new_vmcs12;
7112                 vmx->nested.current_vmcs12_page = page;
7113                 if (enable_shadow_vmcs) {
7114                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7115                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7116                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7117                         vmcs_write64(VMCS_LINK_POINTER,
7118                                      __pa(vmx->nested.current_shadow_vmcs));
7119                         vmx->nested.sync_shadow_vmcs = true;
7120                 }
7121         }
7122
7123         nested_vmx_succeed(vcpu);
7124         skip_emulated_instruction(vcpu);
7125         return 1;
7126 }
7127
7128 /* Emulate the VMPTRST instruction */
7129 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7130 {
7131         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7132         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7133         gva_t vmcs_gva;
7134         struct x86_exception e;
7135
7136         if (!nested_vmx_check_permission(vcpu))
7137                 return 1;
7138
7139         if (get_vmx_mem_address(vcpu, exit_qualification,
7140                         vmx_instruction_info, &vmcs_gva))
7141                 return 1;
7142         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7143         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7144                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7145                                  sizeof(u64), &e)) {
7146                 kvm_inject_page_fault(vcpu, &e);
7147                 return 1;
7148         }
7149         nested_vmx_succeed(vcpu);
7150         skip_emulated_instruction(vcpu);
7151         return 1;
7152 }
7153
7154 /* Emulate the INVEPT instruction */
7155 static int handle_invept(struct kvm_vcpu *vcpu)
7156 {
7157         struct vcpu_vmx *vmx = to_vmx(vcpu);
7158         u32 vmx_instruction_info, types;
7159         unsigned long type;
7160         gva_t gva;
7161         struct x86_exception e;
7162         struct {
7163                 u64 eptp, gpa;
7164         } operand;
7165
7166         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7167               SECONDARY_EXEC_ENABLE_EPT) ||
7168             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7169                 kvm_queue_exception(vcpu, UD_VECTOR);
7170                 return 1;
7171         }
7172
7173         if (!nested_vmx_check_permission(vcpu))
7174                 return 1;
7175
7176         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7177                 kvm_queue_exception(vcpu, UD_VECTOR);
7178                 return 1;
7179         }
7180
7181         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7182         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7183
7184         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7185
7186         if (!(types & (1UL << type))) {
7187                 nested_vmx_failValid(vcpu,
7188                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7189                 return 1;
7190         }
7191
7192         /* According to the Intel VMX instruction reference, the memory
7193          * operand is read even if it isn't needed (e.g., for type==global)
7194          */
7195         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7196                         vmx_instruction_info, &gva))
7197                 return 1;
7198         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7199                                 sizeof(operand), &e)) {
7200                 kvm_inject_page_fault(vcpu, &e);
7201                 return 1;
7202         }
7203
7204         switch (type) {
7205         case VMX_EPT_EXTENT_GLOBAL:
7206                 kvm_mmu_sync_roots(vcpu);
7207                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7208                 nested_vmx_succeed(vcpu);
7209                 break;
7210         default:
7211                 /* Trap single context invalidation invept calls */
7212                 BUG_ON(1);
7213                 break;
7214         }
7215
7216         skip_emulated_instruction(vcpu);
7217         return 1;
7218 }
7219
7220 static int handle_invvpid(struct kvm_vcpu *vcpu)
7221 {
7222         kvm_queue_exception(vcpu, UD_VECTOR);
7223         return 1;
7224 }
7225
7226 static int handle_pml_full(struct kvm_vcpu *vcpu)
7227 {
7228         unsigned long exit_qualification;
7229
7230         trace_kvm_pml_full(vcpu->vcpu_id);
7231
7232         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7233
7234         /*
7235          * PML buffer FULL happened while executing iret from NMI,
7236          * "blocked by NMI" bit has to be set before next VM entry.
7237          */
7238         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7239                         cpu_has_virtual_nmis() &&
7240                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7241                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7242                                 GUEST_INTR_STATE_NMI);
7243
7244         /*
7245          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7246          * here.., and there's no userspace involvement needed for PML.
7247          */
7248         return 1;
7249 }
7250
7251 /*
7252  * The exit handlers return 1 if the exit was handled fully and guest execution
7253  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7254  * to be done to userspace and return 0.
7255  */
7256 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7257         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7258         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7259         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7260         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7261         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7262         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7263         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7264         [EXIT_REASON_CPUID]                   = handle_cpuid,
7265         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7266         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7267         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7268         [EXIT_REASON_HLT]                     = handle_halt,
7269         [EXIT_REASON_INVD]                    = handle_invd,
7270         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7271         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7272         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7273         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7274         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7275         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7276         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7277         [EXIT_REASON_VMREAD]                  = handle_vmread,
7278         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7279         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7280         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7281         [EXIT_REASON_VMON]                    = handle_vmon,
7282         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7283         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7284         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7285         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7286         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7287         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7288         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7289         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7290         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7291         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7292         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7293         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7294         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7295         [EXIT_REASON_INVEPT]                  = handle_invept,
7296         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7297         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7298         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7299         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7300 };
7301
7302 static const int kvm_vmx_max_exit_handlers =
7303         ARRAY_SIZE(kvm_vmx_exit_handlers);
7304
7305 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7306                                        struct vmcs12 *vmcs12)
7307 {
7308         unsigned long exit_qualification;
7309         gpa_t bitmap, last_bitmap;
7310         unsigned int port;
7311         int size;
7312         u8 b;
7313
7314         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7315                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7316
7317         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7318
7319         port = exit_qualification >> 16;
7320         size = (exit_qualification & 7) + 1;
7321
7322         last_bitmap = (gpa_t)-1;
7323         b = -1;
7324
7325         while (size > 0) {
7326                 if (port < 0x8000)
7327                         bitmap = vmcs12->io_bitmap_a;
7328                 else if (port < 0x10000)
7329                         bitmap = vmcs12->io_bitmap_b;
7330                 else
7331                         return true;
7332                 bitmap += (port & 0x7fff) / 8;
7333
7334                 if (last_bitmap != bitmap)
7335                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7336                                 return true;
7337                 if (b & (1 << (port & 7)))
7338                         return true;
7339
7340                 port++;
7341                 size--;
7342                 last_bitmap = bitmap;
7343         }
7344
7345         return false;
7346 }
7347
7348 /*
7349  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7350  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7351  * disinterest in the current event (read or write a specific MSR) by using an
7352  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7353  */
7354 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7355         struct vmcs12 *vmcs12, u32 exit_reason)
7356 {
7357         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7358         gpa_t bitmap;
7359
7360         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7361                 return true;
7362
7363         /*
7364          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7365          * for the four combinations of read/write and low/high MSR numbers.
7366          * First we need to figure out which of the four to use:
7367          */
7368         bitmap = vmcs12->msr_bitmap;
7369         if (exit_reason == EXIT_REASON_MSR_WRITE)
7370                 bitmap += 2048;
7371         if (msr_index >= 0xc0000000) {
7372                 msr_index -= 0xc0000000;
7373                 bitmap += 1024;
7374         }
7375
7376         /* Then read the msr_index'th bit from this bitmap: */
7377         if (msr_index < 1024*8) {
7378                 unsigned char b;
7379                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7380                         return true;
7381                 return 1 & (b >> (msr_index & 7));
7382         } else
7383                 return true; /* let L1 handle the wrong parameter */
7384 }
7385
7386 /*
7387  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7388  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7389  * intercept (via guest_host_mask etc.) the current event.
7390  */
7391 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7392         struct vmcs12 *vmcs12)
7393 {
7394         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7395         int cr = exit_qualification & 15;
7396         int reg = (exit_qualification >> 8) & 15;
7397         unsigned long val = kvm_register_readl(vcpu, reg);
7398
7399         switch ((exit_qualification >> 4) & 3) {
7400         case 0: /* mov to cr */
7401                 switch (cr) {
7402                 case 0:
7403                         if (vmcs12->cr0_guest_host_mask &
7404                             (val ^ vmcs12->cr0_read_shadow))
7405                                 return true;
7406                         break;
7407                 case 3:
7408                         if ((vmcs12->cr3_target_count >= 1 &&
7409                                         vmcs12->cr3_target_value0 == val) ||
7410                                 (vmcs12->cr3_target_count >= 2 &&
7411                                         vmcs12->cr3_target_value1 == val) ||
7412                                 (vmcs12->cr3_target_count >= 3 &&
7413                                         vmcs12->cr3_target_value2 == val) ||
7414                                 (vmcs12->cr3_target_count >= 4 &&
7415                                         vmcs12->cr3_target_value3 == val))
7416                                 return false;
7417                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7418                                 return true;
7419                         break;
7420                 case 4:
7421                         if (vmcs12->cr4_guest_host_mask &
7422                             (vmcs12->cr4_read_shadow ^ val))
7423                                 return true;
7424                         break;
7425                 case 8:
7426                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7427                                 return true;
7428                         break;
7429                 }
7430                 break;
7431         case 2: /* clts */
7432                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7433                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7434                         return true;
7435                 break;
7436         case 1: /* mov from cr */
7437                 switch (cr) {
7438                 case 3:
7439                         if (vmcs12->cpu_based_vm_exec_control &
7440                             CPU_BASED_CR3_STORE_EXITING)
7441                                 return true;
7442                         break;
7443                 case 8:
7444                         if (vmcs12->cpu_based_vm_exec_control &
7445                             CPU_BASED_CR8_STORE_EXITING)
7446                                 return true;
7447                         break;
7448                 }
7449                 break;
7450         case 3: /* lmsw */
7451                 /*
7452                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7453                  * cr0. Other attempted changes are ignored, with no exit.
7454                  */
7455                 if (vmcs12->cr0_guest_host_mask & 0xe &
7456                     (val ^ vmcs12->cr0_read_shadow))
7457                         return true;
7458                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7459                     !(vmcs12->cr0_read_shadow & 0x1) &&
7460                     (val & 0x1))
7461                         return true;
7462                 break;
7463         }
7464         return false;
7465 }
7466
7467 /*
7468  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7469  * should handle it ourselves in L0 (and then continue L2). Only call this
7470  * when in is_guest_mode (L2).
7471  */
7472 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7473 {
7474         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7475         struct vcpu_vmx *vmx = to_vmx(vcpu);
7476         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7477         u32 exit_reason = vmx->exit_reason;
7478
7479         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7480                                 vmcs_readl(EXIT_QUALIFICATION),
7481                                 vmx->idt_vectoring_info,
7482                                 intr_info,
7483                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7484                                 KVM_ISA_VMX);
7485
7486         if (vmx->nested.nested_run_pending)
7487                 return false;
7488
7489         if (unlikely(vmx->fail)) {
7490                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7491                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7492                 return true;
7493         }
7494
7495         switch (exit_reason) {
7496         case EXIT_REASON_EXCEPTION_NMI:
7497                 if (!is_exception(intr_info))
7498                         return false;
7499                 else if (is_page_fault(intr_info))
7500                         return enable_ept;
7501                 else if (is_no_device(intr_info) &&
7502                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7503                         return false;
7504                 return vmcs12->exception_bitmap &
7505                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7506         case EXIT_REASON_EXTERNAL_INTERRUPT:
7507                 return false;
7508         case EXIT_REASON_TRIPLE_FAULT:
7509                 return true;
7510         case EXIT_REASON_PENDING_INTERRUPT:
7511                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7512         case EXIT_REASON_NMI_WINDOW:
7513                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7514         case EXIT_REASON_TASK_SWITCH:
7515                 return true;
7516         case EXIT_REASON_CPUID:
7517                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7518                         return false;
7519                 return true;
7520         case EXIT_REASON_HLT:
7521                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7522         case EXIT_REASON_INVD:
7523                 return true;
7524         case EXIT_REASON_INVLPG:
7525                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7526         case EXIT_REASON_RDPMC:
7527                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7528         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7529                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7530         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7531         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7532         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7533         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7534         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7535         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7536                 /*
7537                  * VMX instructions trap unconditionally. This allows L1 to
7538                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7539                  */
7540                 return true;
7541         case EXIT_REASON_CR_ACCESS:
7542                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7543         case EXIT_REASON_DR_ACCESS:
7544                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7545         case EXIT_REASON_IO_INSTRUCTION:
7546                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7547         case EXIT_REASON_MSR_READ:
7548         case EXIT_REASON_MSR_WRITE:
7549                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7550         case EXIT_REASON_INVALID_STATE:
7551                 return true;
7552         case EXIT_REASON_MWAIT_INSTRUCTION:
7553                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7554         case EXIT_REASON_MONITOR_INSTRUCTION:
7555                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7556         case EXIT_REASON_PAUSE_INSTRUCTION:
7557                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7558                         nested_cpu_has2(vmcs12,
7559                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7560         case EXIT_REASON_MCE_DURING_VMENTRY:
7561                 return false;
7562         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7563                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7564         case EXIT_REASON_APIC_ACCESS:
7565                 return nested_cpu_has2(vmcs12,
7566                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7567         case EXIT_REASON_APIC_WRITE:
7568         case EXIT_REASON_EOI_INDUCED:
7569                 /* apic_write and eoi_induced should exit unconditionally. */
7570                 return true;
7571         case EXIT_REASON_EPT_VIOLATION:
7572                 /*
7573                  * L0 always deals with the EPT violation. If nested EPT is
7574                  * used, and the nested mmu code discovers that the address is
7575                  * missing in the guest EPT table (EPT12), the EPT violation
7576                  * will be injected with nested_ept_inject_page_fault()
7577                  */
7578                 return false;
7579         case EXIT_REASON_EPT_MISCONFIG:
7580                 /*
7581                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7582                  * table (shadow on EPT) or a merged EPT table that L0 built
7583                  * (EPT on EPT). So any problems with the structure of the
7584                  * table is L0's fault.
7585                  */
7586                 return false;
7587         case EXIT_REASON_WBINVD:
7588                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7589         case EXIT_REASON_XSETBV:
7590                 return true;
7591         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7592                 /*
7593                  * This should never happen, since it is not possible to
7594                  * set XSS to a non-zero value---neither in L1 nor in L2.
7595                  * If if it were, XSS would have to be checked against
7596                  * the XSS exit bitmap in vmcs12.
7597                  */
7598                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7599         default:
7600                 return true;
7601         }
7602 }
7603
7604 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7605 {
7606         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7607         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7608 }
7609
7610 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7611 {
7612         struct page *pml_pg;
7613         u32 exec_control;
7614
7615         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7616         if (!pml_pg)
7617                 return -ENOMEM;
7618
7619         vmx->pml_pg = pml_pg;
7620
7621         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7622         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7623
7624         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7625         exec_control |= SECONDARY_EXEC_ENABLE_PML;
7626         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7627
7628         return 0;
7629 }
7630
7631 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7632 {
7633         u32 exec_control;
7634
7635         ASSERT(vmx->pml_pg);
7636         __free_page(vmx->pml_pg);
7637         vmx->pml_pg = NULL;
7638
7639         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7640         exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7641         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7642 }
7643
7644 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7645 {
7646         struct kvm *kvm = vmx->vcpu.kvm;
7647         u64 *pml_buf;
7648         u16 pml_idx;
7649
7650         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7651
7652         /* Do nothing if PML buffer is empty */
7653         if (pml_idx == (PML_ENTITY_NUM - 1))
7654                 return;
7655
7656         /* PML index always points to next available PML buffer entity */
7657         if (pml_idx >= PML_ENTITY_NUM)
7658                 pml_idx = 0;
7659         else
7660                 pml_idx++;
7661
7662         pml_buf = page_address(vmx->pml_pg);
7663         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7664                 u64 gpa;
7665
7666                 gpa = pml_buf[pml_idx];
7667                 WARN_ON(gpa & (PAGE_SIZE - 1));
7668                 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7669         }
7670
7671         /* reset PML index */
7672         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7673 }
7674
7675 /*
7676  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7677  * Called before reporting dirty_bitmap to userspace.
7678  */
7679 static void kvm_flush_pml_buffers(struct kvm *kvm)
7680 {
7681         int i;
7682         struct kvm_vcpu *vcpu;
7683         /*
7684          * We only need to kick vcpu out of guest mode here, as PML buffer
7685          * is flushed at beginning of all VMEXITs, and it's obvious that only
7686          * vcpus running in guest are possible to have unflushed GPAs in PML
7687          * buffer.
7688          */
7689         kvm_for_each_vcpu(i, vcpu, kvm)
7690                 kvm_vcpu_kick(vcpu);
7691 }
7692
7693 /*
7694  * The guest has exited.  See if we can fix it or if we need userspace
7695  * assistance.
7696  */
7697 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7698 {
7699         struct vcpu_vmx *vmx = to_vmx(vcpu);
7700         u32 exit_reason = vmx->exit_reason;
7701         u32 vectoring_info = vmx->idt_vectoring_info;
7702
7703         /*
7704          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7705          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7706          * querying dirty_bitmap, we only need to kick all vcpus out of guest
7707          * mode as if vcpus is in root mode, the PML buffer must has been
7708          * flushed already.
7709          */
7710         if (enable_pml)
7711                 vmx_flush_pml_buffer(vmx);
7712
7713         /* If guest state is invalid, start emulating */
7714         if (vmx->emulation_required)
7715                 return handle_invalid_guest_state(vcpu);
7716
7717         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7718                 nested_vmx_vmexit(vcpu, exit_reason,
7719                                   vmcs_read32(VM_EXIT_INTR_INFO),
7720                                   vmcs_readl(EXIT_QUALIFICATION));
7721                 return 1;
7722         }
7723
7724         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7725                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7726                 vcpu->run->fail_entry.hardware_entry_failure_reason
7727                         = exit_reason;
7728                 return 0;
7729         }
7730
7731         if (unlikely(vmx->fail)) {
7732                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7733                 vcpu->run->fail_entry.hardware_entry_failure_reason
7734                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7735                 return 0;
7736         }
7737
7738         /*
7739          * Note:
7740          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7741          * delivery event since it indicates guest is accessing MMIO.
7742          * The vm-exit can be triggered again after return to guest that
7743          * will cause infinite loop.
7744          */
7745         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7746                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7747                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7748                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7749                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7750                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7751                 vcpu->run->internal.ndata = 2;
7752                 vcpu->run->internal.data[0] = vectoring_info;
7753                 vcpu->run->internal.data[1] = exit_reason;
7754                 return 0;
7755         }
7756
7757         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7758             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7759                                         get_vmcs12(vcpu))))) {
7760                 if (vmx_interrupt_allowed(vcpu)) {
7761                         vmx->soft_vnmi_blocked = 0;
7762                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7763                            vcpu->arch.nmi_pending) {
7764                         /*
7765                          * This CPU don't support us in finding the end of an
7766                          * NMI-blocked window if the guest runs with IRQs
7767                          * disabled. So we pull the trigger after 1 s of
7768                          * futile waiting, but inform the user about this.
7769                          */
7770                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7771                                "state on VCPU %d after 1 s timeout\n",
7772                                __func__, vcpu->vcpu_id);
7773                         vmx->soft_vnmi_blocked = 0;
7774                 }
7775         }
7776
7777         if (exit_reason < kvm_vmx_max_exit_handlers
7778             && kvm_vmx_exit_handlers[exit_reason])
7779                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7780         else {
7781                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7782                 kvm_queue_exception(vcpu, UD_VECTOR);
7783                 return 1;
7784         }
7785 }
7786
7787 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7788 {
7789         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7790
7791         if (is_guest_mode(vcpu) &&
7792                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7793                 return;
7794
7795         if (irr == -1 || tpr < irr) {
7796                 vmcs_write32(TPR_THRESHOLD, 0);
7797                 return;
7798         }
7799
7800         vmcs_write32(TPR_THRESHOLD, irr);
7801 }
7802
7803 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7804 {
7805         u32 sec_exec_control;
7806
7807         /*
7808          * There is not point to enable virtualize x2apic without enable
7809          * apicv
7810          */
7811         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7812                                 !vmx_vm_has_apicv(vcpu->kvm))
7813                 return;
7814
7815         if (!vm_need_tpr_shadow(vcpu->kvm))
7816                 return;
7817
7818         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7819
7820         if (set) {
7821                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7822                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7823         } else {
7824                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7825                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7826         }
7827         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7828
7829         vmx_set_msr_bitmap(vcpu);
7830 }
7831
7832 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7833 {
7834         struct vcpu_vmx *vmx = to_vmx(vcpu);
7835
7836         /*
7837          * Currently we do not handle the nested case where L2 has an
7838          * APIC access page of its own; that page is still pinned.
7839          * Hence, we skip the case where the VCPU is in guest mode _and_
7840          * L1 prepared an APIC access page for L2.
7841          *
7842          * For the case where L1 and L2 share the same APIC access page
7843          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7844          * in the vmcs12), this function will only update either the vmcs01
7845          * or the vmcs02.  If the former, the vmcs02 will be updated by
7846          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7847          * the next L2->L1 exit.
7848          */
7849         if (!is_guest_mode(vcpu) ||
7850             !nested_cpu_has2(vmx->nested.current_vmcs12,
7851                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7852                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7853 }
7854
7855 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7856 {
7857         u16 status;
7858         u8 old;
7859
7860         if (isr == -1)
7861                 isr = 0;
7862
7863         status = vmcs_read16(GUEST_INTR_STATUS);
7864         old = status >> 8;
7865         if (isr != old) {
7866                 status &= 0xff;
7867                 status |= isr << 8;
7868                 vmcs_write16(GUEST_INTR_STATUS, status);
7869         }
7870 }
7871
7872 static void vmx_set_rvi(int vector)
7873 {
7874         u16 status;
7875         u8 old;
7876
7877         if (vector == -1)
7878                 vector = 0;
7879
7880         status = vmcs_read16(GUEST_INTR_STATUS);
7881         old = (u8)status & 0xff;
7882         if ((u8)vector != old) {
7883                 status &= ~0xff;
7884                 status |= (u8)vector;
7885                 vmcs_write16(GUEST_INTR_STATUS, status);
7886         }
7887 }
7888
7889 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7890 {
7891         if (!is_guest_mode(vcpu)) {
7892                 vmx_set_rvi(max_irr);
7893                 return;
7894         }
7895
7896         if (max_irr == -1)
7897                 return;
7898
7899         /*
7900          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7901          * handles it.
7902          */
7903         if (nested_exit_on_intr(vcpu))
7904                 return;
7905
7906         /*
7907          * Else, fall back to pre-APICv interrupt injection since L2
7908          * is run without virtual interrupt delivery.
7909          */
7910         if (!kvm_event_needs_reinjection(vcpu) &&
7911             vmx_interrupt_allowed(vcpu)) {
7912                 kvm_queue_interrupt(vcpu, max_irr, false);
7913                 vmx_inject_irq(vcpu);
7914         }
7915 }
7916
7917 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7918 {
7919         if (!vmx_vm_has_apicv(vcpu->kvm))
7920                 return;
7921
7922         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7923         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7924         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7925         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7926 }
7927
7928 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7929 {
7930         u32 exit_intr_info;
7931
7932         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7933               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7934                 return;
7935
7936         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7937         exit_intr_info = vmx->exit_intr_info;
7938
7939         /* Handle machine checks before interrupts are enabled */
7940         if (is_machine_check(exit_intr_info))
7941                 kvm_machine_check();
7942
7943         /* We need to handle NMIs before interrupts are enabled */
7944         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7945             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7946                 kvm_before_handle_nmi(&vmx->vcpu);
7947                 asm("int $2");
7948                 kvm_after_handle_nmi(&vmx->vcpu);
7949         }
7950 }
7951
7952 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7953 {
7954         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7955
7956         /*
7957          * If external interrupt exists, IF bit is set in rflags/eflags on the
7958          * interrupt stack frame, and interrupt will be enabled on a return
7959          * from interrupt handler.
7960          */
7961         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7962                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7963                 unsigned int vector;
7964                 unsigned long entry;
7965                 gate_desc *desc;
7966                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7967 #ifdef CONFIG_X86_64
7968                 unsigned long tmp;
7969 #endif
7970
7971                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7972                 desc = (gate_desc *)vmx->host_idt_base + vector;
7973                 entry = gate_offset(*desc);
7974                 asm volatile(
7975 #ifdef CONFIG_X86_64
7976                         "mov %%" _ASM_SP ", %[sp]\n\t"
7977                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7978                         "push $%c[ss]\n\t"
7979                         "push %[sp]\n\t"
7980 #endif
7981                         "pushf\n\t"
7982                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7983                         __ASM_SIZE(push) " $%c[cs]\n\t"
7984                         "call *%[entry]\n\t"
7985                         :
7986 #ifdef CONFIG_X86_64
7987                         [sp]"=&r"(tmp)
7988 #endif
7989                         :
7990                         [entry]"r"(entry),
7991                         [ss]"i"(__KERNEL_DS),
7992                         [cs]"i"(__KERNEL_CS)
7993                         );
7994         } else
7995                 local_irq_enable();
7996 }
7997
7998 static bool vmx_mpx_supported(void)
7999 {
8000         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8001                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8002 }
8003
8004 static bool vmx_xsaves_supported(void)
8005 {
8006         return vmcs_config.cpu_based_2nd_exec_ctrl &
8007                 SECONDARY_EXEC_XSAVES;
8008 }
8009
8010 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8011 {
8012         u32 exit_intr_info;
8013         bool unblock_nmi;
8014         u8 vector;
8015         bool idtv_info_valid;
8016
8017         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8018
8019         if (cpu_has_virtual_nmis()) {
8020                 if (vmx->nmi_known_unmasked)
8021                         return;
8022                 /*
8023                  * Can't use vmx->exit_intr_info since we're not sure what
8024                  * the exit reason is.
8025                  */
8026                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8027                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8028                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8029                 /*
8030                  * SDM 3: 27.7.1.2 (September 2008)
8031                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8032                  * a guest IRET fault.
8033                  * SDM 3: 23.2.2 (September 2008)
8034                  * Bit 12 is undefined in any of the following cases:
8035                  *  If the VM exit sets the valid bit in the IDT-vectoring
8036                  *   information field.
8037                  *  If the VM exit is due to a double fault.
8038                  */
8039                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8040                     vector != DF_VECTOR && !idtv_info_valid)
8041                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8042                                       GUEST_INTR_STATE_NMI);
8043                 else
8044                         vmx->nmi_known_unmasked =
8045                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8046                                   & GUEST_INTR_STATE_NMI);
8047         } else if (unlikely(vmx->soft_vnmi_blocked))
8048                 vmx->vnmi_blocked_time +=
8049                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8050 }
8051
8052 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8053                                       u32 idt_vectoring_info,
8054                                       int instr_len_field,
8055                                       int error_code_field)
8056 {
8057         u8 vector;
8058         int type;
8059         bool idtv_info_valid;
8060
8061         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8062
8063         vcpu->arch.nmi_injected = false;
8064         kvm_clear_exception_queue(vcpu);
8065         kvm_clear_interrupt_queue(vcpu);
8066
8067         if (!idtv_info_valid)
8068                 return;
8069
8070         kvm_make_request(KVM_REQ_EVENT, vcpu);
8071
8072         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8073         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8074
8075         switch (type) {
8076         case INTR_TYPE_NMI_INTR:
8077                 vcpu->arch.nmi_injected = true;
8078                 /*
8079                  * SDM 3: 27.7.1.2 (September 2008)
8080                  * Clear bit "block by NMI" before VM entry if a NMI
8081                  * delivery faulted.
8082                  */
8083                 vmx_set_nmi_mask(vcpu, false);
8084                 break;
8085         case INTR_TYPE_SOFT_EXCEPTION:
8086                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8087                 /* fall through */
8088         case INTR_TYPE_HARD_EXCEPTION:
8089                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8090                         u32 err = vmcs_read32(error_code_field);
8091                         kvm_requeue_exception_e(vcpu, vector, err);
8092                 } else
8093                         kvm_requeue_exception(vcpu, vector);
8094                 break;
8095         case INTR_TYPE_SOFT_INTR:
8096                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8097                 /* fall through */
8098         case INTR_TYPE_EXT_INTR:
8099                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8100                 break;
8101         default:
8102                 break;
8103         }
8104 }
8105
8106 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8107 {
8108         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8109                                   VM_EXIT_INSTRUCTION_LEN,
8110                                   IDT_VECTORING_ERROR_CODE);
8111 }
8112
8113 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8114 {
8115         __vmx_complete_interrupts(vcpu,
8116                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8117                                   VM_ENTRY_INSTRUCTION_LEN,
8118                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8119
8120         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8121 }
8122
8123 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8124 {
8125         int i, nr_msrs;
8126         struct perf_guest_switch_msr *msrs;
8127
8128         msrs = perf_guest_get_msrs(&nr_msrs);
8129
8130         if (!msrs)
8131                 return;
8132
8133         for (i = 0; i < nr_msrs; i++)
8134                 if (msrs[i].host == msrs[i].guest)
8135                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8136                 else
8137                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8138                                         msrs[i].host);
8139 }
8140
8141 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8142 {
8143         struct vcpu_vmx *vmx = to_vmx(vcpu);
8144         unsigned long debugctlmsr, cr4;
8145
8146         /* Record the guest's net vcpu time for enforced NMI injections. */
8147         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8148                 vmx->entry_time = ktime_get();
8149
8150         /* Don't enter VMX if guest state is invalid, let the exit handler
8151            start emulation until we arrive back to a valid state */
8152         if (vmx->emulation_required)
8153                 return;
8154
8155         if (vmx->ple_window_dirty) {
8156                 vmx->ple_window_dirty = false;
8157                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8158         }
8159
8160         if (vmx->nested.sync_shadow_vmcs) {
8161                 copy_vmcs12_to_shadow(vmx);
8162                 vmx->nested.sync_shadow_vmcs = false;
8163         }
8164
8165         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8166                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8167         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8168                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8169
8170         cr4 = cr4_read_shadow();
8171         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8172                 vmcs_writel(HOST_CR4, cr4);
8173                 vmx->host_state.vmcs_host_cr4 = cr4;
8174         }
8175
8176         /* When single-stepping over STI and MOV SS, we must clear the
8177          * corresponding interruptibility bits in the guest state. Otherwise
8178          * vmentry fails as it then expects bit 14 (BS) in pending debug
8179          * exceptions being set, but that's not correct for the guest debugging
8180          * case. */
8181         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8182                 vmx_set_interrupt_shadow(vcpu, 0);
8183
8184         atomic_switch_perf_msrs(vmx);
8185         debugctlmsr = get_debugctlmsr();
8186
8187         vmx->__launched = vmx->loaded_vmcs->launched;
8188         asm(
8189                 /* Store host registers */
8190                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8191                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8192                 "push %%" _ASM_CX " \n\t"
8193                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8194                 "je 1f \n\t"
8195                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8196                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8197                 "1: \n\t"
8198                 /* Reload cr2 if changed */
8199                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8200                 "mov %%cr2, %%" _ASM_DX " \n\t"
8201                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8202                 "je 2f \n\t"
8203                 "mov %%" _ASM_AX", %%cr2 \n\t"
8204                 "2: \n\t"
8205                 /* Check if vmlaunch of vmresume is needed */
8206                 "cmpl $0, %c[launched](%0) \n\t"
8207                 /* Load guest registers.  Don't clobber flags. */
8208                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8209                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8210                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8211                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8212                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8213                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8214 #ifdef CONFIG_X86_64
8215                 "mov %c[r8](%0),  %%r8  \n\t"
8216                 "mov %c[r9](%0),  %%r9  \n\t"
8217                 "mov %c[r10](%0), %%r10 \n\t"
8218                 "mov %c[r11](%0), %%r11 \n\t"
8219                 "mov %c[r12](%0), %%r12 \n\t"
8220                 "mov %c[r13](%0), %%r13 \n\t"
8221                 "mov %c[r14](%0), %%r14 \n\t"
8222                 "mov %c[r15](%0), %%r15 \n\t"
8223 #endif
8224                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8225
8226                 /* Enter guest mode */
8227                 "jne 1f \n\t"
8228                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8229                 "jmp 2f \n\t"
8230                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8231                 "2: "
8232                 /* Save guest registers, load host registers, keep flags */
8233                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8234                 "pop %0 \n\t"
8235                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8236                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8237                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8238                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8239                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8240                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8241                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8242 #ifdef CONFIG_X86_64
8243                 "mov %%r8,  %c[r8](%0) \n\t"
8244                 "mov %%r9,  %c[r9](%0) \n\t"
8245                 "mov %%r10, %c[r10](%0) \n\t"
8246                 "mov %%r11, %c[r11](%0) \n\t"
8247                 "mov %%r12, %c[r12](%0) \n\t"
8248                 "mov %%r13, %c[r13](%0) \n\t"
8249                 "mov %%r14, %c[r14](%0) \n\t"
8250                 "mov %%r15, %c[r15](%0) \n\t"
8251 #endif
8252                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8253                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8254
8255                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8256                 "setbe %c[fail](%0) \n\t"
8257                 ".pushsection .rodata \n\t"
8258                 ".global vmx_return \n\t"
8259                 "vmx_return: " _ASM_PTR " 2b \n\t"
8260                 ".popsection"
8261               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8262                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8263                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8264                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8265                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8266                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8267                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8268                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8269                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8270                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8271                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8272 #ifdef CONFIG_X86_64
8273                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8274                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8275                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8276                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8277                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8278                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8279                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8280                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8281 #endif
8282                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8283                 [wordsize]"i"(sizeof(ulong))
8284               : "cc", "memory"
8285 #ifdef CONFIG_X86_64
8286                 , "rax", "rbx", "rdi", "rsi"
8287                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8288 #else
8289                 , "eax", "ebx", "edi", "esi"
8290 #endif
8291               );
8292
8293         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8294         if (debugctlmsr)
8295                 update_debugctlmsr(debugctlmsr);
8296
8297 #ifndef CONFIG_X86_64
8298         /*
8299          * The sysexit path does not restore ds/es, so we must set them to
8300          * a reasonable value ourselves.
8301          *
8302          * We can't defer this to vmx_load_host_state() since that function
8303          * may be executed in interrupt context, which saves and restore segments
8304          * around it, nullifying its effect.
8305          */
8306         loadsegment(ds, __USER_DS);
8307         loadsegment(es, __USER_DS);
8308 #endif
8309
8310         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8311                                   | (1 << VCPU_EXREG_RFLAGS)
8312                                   | (1 << VCPU_EXREG_PDPTR)
8313                                   | (1 << VCPU_EXREG_SEGMENTS)
8314                                   | (1 << VCPU_EXREG_CR3));
8315         vcpu->arch.regs_dirty = 0;
8316
8317         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8318
8319         vmx->loaded_vmcs->launched = 1;
8320
8321         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8322         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8323
8324         /*
8325          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8326          * we did not inject a still-pending event to L1 now because of
8327          * nested_run_pending, we need to re-enable this bit.
8328          */
8329         if (vmx->nested.nested_run_pending)
8330                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8331
8332         vmx->nested.nested_run_pending = 0;
8333
8334         vmx_complete_atomic_exit(vmx);
8335         vmx_recover_nmi_blocking(vmx);
8336         vmx_complete_interrupts(vmx);
8337 }
8338
8339 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8340 {
8341         struct vcpu_vmx *vmx = to_vmx(vcpu);
8342         int cpu;
8343
8344         if (vmx->loaded_vmcs == &vmx->vmcs01)
8345                 return;
8346
8347         cpu = get_cpu();
8348         vmx->loaded_vmcs = &vmx->vmcs01;
8349         vmx_vcpu_put(vcpu);
8350         vmx_vcpu_load(vcpu, cpu);
8351         vcpu->cpu = cpu;
8352         put_cpu();
8353 }
8354
8355 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8356 {
8357         struct vcpu_vmx *vmx = to_vmx(vcpu);
8358
8359         if (enable_pml)
8360                 vmx_disable_pml(vmx);
8361         free_vpid(vmx);
8362         leave_guest_mode(vcpu);
8363         vmx_load_vmcs01(vcpu);
8364         free_nested(vmx);
8365         free_loaded_vmcs(vmx->loaded_vmcs);
8366         kfree(vmx->guest_msrs);
8367         kvm_vcpu_uninit(vcpu);
8368         kmem_cache_free(kvm_vcpu_cache, vmx);
8369 }
8370
8371 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8372 {
8373         int err;
8374         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8375         int cpu;
8376
8377         if (!vmx)
8378                 return ERR_PTR(-ENOMEM);
8379
8380         allocate_vpid(vmx);
8381
8382         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8383         if (err)
8384                 goto free_vcpu;
8385
8386         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8387         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8388                      > PAGE_SIZE);
8389
8390         err = -ENOMEM;
8391         if (!vmx->guest_msrs) {
8392                 goto uninit_vcpu;
8393         }
8394
8395         vmx->loaded_vmcs = &vmx->vmcs01;
8396         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8397         if (!vmx->loaded_vmcs->vmcs)
8398                 goto free_msrs;
8399         if (!vmm_exclusive)
8400                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8401         loaded_vmcs_init(vmx->loaded_vmcs);
8402         if (!vmm_exclusive)
8403                 kvm_cpu_vmxoff();
8404
8405         cpu = get_cpu();
8406         vmx_vcpu_load(&vmx->vcpu, cpu);
8407         vmx->vcpu.cpu = cpu;
8408         err = vmx_vcpu_setup(vmx);
8409         vmx_vcpu_put(&vmx->vcpu);
8410         put_cpu();
8411         if (err)
8412                 goto free_vmcs;
8413         if (vm_need_virtualize_apic_accesses(kvm)) {
8414                 err = alloc_apic_access_page(kvm);
8415                 if (err)
8416                         goto free_vmcs;
8417         }
8418
8419         if (enable_ept) {
8420                 if (!kvm->arch.ept_identity_map_addr)
8421                         kvm->arch.ept_identity_map_addr =
8422                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8423                 err = init_rmode_identity_map(kvm);
8424                 if (err)
8425                         goto free_vmcs;
8426         }
8427
8428         if (nested)
8429                 nested_vmx_setup_ctls_msrs(vmx);
8430
8431         vmx->nested.posted_intr_nv = -1;
8432         vmx->nested.current_vmptr = -1ull;
8433         vmx->nested.current_vmcs12 = NULL;
8434
8435         /*
8436          * If PML is turned on, failure on enabling PML just results in failure
8437          * of creating the vcpu, therefore we can simplify PML logic (by
8438          * avoiding dealing with cases, such as enabling PML partially on vcpus
8439          * for the guest, etc.
8440          */
8441         if (enable_pml) {
8442                 err = vmx_enable_pml(vmx);
8443                 if (err)
8444                         goto free_vmcs;
8445         }
8446
8447         return &vmx->vcpu;
8448
8449 free_vmcs:
8450         free_loaded_vmcs(vmx->loaded_vmcs);
8451 free_msrs:
8452         kfree(vmx->guest_msrs);
8453 uninit_vcpu:
8454         kvm_vcpu_uninit(&vmx->vcpu);
8455 free_vcpu:
8456         free_vpid(vmx);
8457         kmem_cache_free(kvm_vcpu_cache, vmx);
8458         return ERR_PTR(err);
8459 }
8460
8461 static void __init vmx_check_processor_compat(void *rtn)
8462 {
8463         struct vmcs_config vmcs_conf;
8464
8465         *(int *)rtn = 0;
8466         if (setup_vmcs_config(&vmcs_conf) < 0)
8467                 *(int *)rtn = -EIO;
8468         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8469                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8470                                 smp_processor_id());
8471                 *(int *)rtn = -EIO;
8472         }
8473 }
8474
8475 static int get_ept_level(void)
8476 {
8477         return VMX_EPT_DEFAULT_GAW + 1;
8478 }
8479
8480 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8481 {
8482         u64 ret;
8483
8484         /* For VT-d and EPT combination
8485          * 1. MMIO: always map as UC
8486          * 2. EPT with VT-d:
8487          *   a. VT-d without snooping control feature: can't guarantee the
8488          *      result, try to trust guest.
8489          *   b. VT-d with snooping control feature: snooping control feature of
8490          *      VT-d engine can guarantee the cache correctness. Just set it
8491          *      to WB to keep consistent with host. So the same as item 3.
8492          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8493          *    consistent with host MTRR
8494          */
8495         if (is_mmio)
8496                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8497         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8498                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8499                       VMX_EPT_MT_EPTE_SHIFT;
8500         else
8501                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8502                         | VMX_EPT_IPAT_BIT;
8503
8504         return ret;
8505 }
8506
8507 static int vmx_get_lpage_level(void)
8508 {
8509         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8510                 return PT_DIRECTORY_LEVEL;
8511         else
8512                 /* For shadow and EPT supported 1GB page */
8513                 return PT_PDPE_LEVEL;
8514 }
8515
8516 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8517 {
8518         struct kvm_cpuid_entry2 *best;
8519         struct vcpu_vmx *vmx = to_vmx(vcpu);
8520         u32 exec_control;
8521
8522         vmx->rdtscp_enabled = false;
8523         if (vmx_rdtscp_supported()) {
8524                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8525                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8526                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8527                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8528                                 vmx->rdtscp_enabled = true;
8529                         else {
8530                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8531                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8532                                                 exec_control);
8533                         }
8534                 }
8535                 if (nested && !vmx->rdtscp_enabled)
8536                         vmx->nested.nested_vmx_secondary_ctls_high &=
8537                                 ~SECONDARY_EXEC_RDTSCP;
8538         }
8539
8540         /* Exposing INVPCID only when PCID is exposed */
8541         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8542         if (vmx_invpcid_supported() &&
8543             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8544             guest_cpuid_has_pcid(vcpu)) {
8545                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8546                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8547                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8548                              exec_control);
8549         } else {
8550                 if (cpu_has_secondary_exec_ctrls()) {
8551                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8552                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8553                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8554                                      exec_control);
8555                 }
8556                 if (best)
8557                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8558         }
8559 }
8560
8561 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8562 {
8563         if (func == 1 && nested)
8564                 entry->ecx |= bit(X86_FEATURE_VMX);
8565 }
8566
8567 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8568                 struct x86_exception *fault)
8569 {
8570         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8571         u32 exit_reason;
8572
8573         if (fault->error_code & PFERR_RSVD_MASK)
8574                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8575         else
8576                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8577         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8578         vmcs12->guest_physical_address = fault->address;
8579 }
8580
8581 /* Callbacks for nested_ept_init_mmu_context: */
8582
8583 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8584 {
8585         /* return the page table to be shadowed - in our case, EPT12 */
8586         return get_vmcs12(vcpu)->ept_pointer;
8587 }
8588
8589 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8590 {
8591         WARN_ON(mmu_is_nested(vcpu));
8592         kvm_init_shadow_ept_mmu(vcpu,
8593                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8594                         VMX_EPT_EXECUTE_ONLY_BIT);
8595         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8596         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8597         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8598
8599         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8600 }
8601
8602 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8603 {
8604         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8605 }
8606
8607 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8608                                             u16 error_code)
8609 {
8610         bool inequality, bit;
8611
8612         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8613         inequality =
8614                 (error_code & vmcs12->page_fault_error_code_mask) !=
8615                  vmcs12->page_fault_error_code_match;
8616         return inequality ^ bit;
8617 }
8618
8619 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8620                 struct x86_exception *fault)
8621 {
8622         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8623
8624         WARN_ON(!is_guest_mode(vcpu));
8625
8626         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8627                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8628                                   vmcs_read32(VM_EXIT_INTR_INFO),
8629                                   vmcs_readl(EXIT_QUALIFICATION));
8630         else
8631                 kvm_inject_page_fault(vcpu, fault);
8632 }
8633
8634 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8635                                         struct vmcs12 *vmcs12)
8636 {
8637         struct vcpu_vmx *vmx = to_vmx(vcpu);
8638         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8639
8640         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8641                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8642                     vmcs12->apic_access_addr >> maxphyaddr)
8643                         return false;
8644
8645                 /*
8646                  * Translate L1 physical address to host physical
8647                  * address for vmcs02. Keep the page pinned, so this
8648                  * physical address remains valid. We keep a reference
8649                  * to it so we can release it later.
8650                  */
8651                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8652                         nested_release_page(vmx->nested.apic_access_page);
8653                 vmx->nested.apic_access_page =
8654                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8655         }
8656
8657         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8658                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8659                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
8660                         return false;
8661
8662                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8663                         nested_release_page(vmx->nested.virtual_apic_page);
8664                 vmx->nested.virtual_apic_page =
8665                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8666
8667                 /*
8668                  * Failing the vm entry is _not_ what the processor does
8669                  * but it's basically the only possibility we have.
8670                  * We could still enter the guest if CR8 load exits are
8671                  * enabled, CR8 store exits are enabled, and virtualize APIC
8672                  * access is disabled; in this case the processor would never
8673                  * use the TPR shadow and we could simply clear the bit from
8674                  * the execution control.  But such a configuration is useless,
8675                  * so let's keep the code simple.
8676                  */
8677                 if (!vmx->nested.virtual_apic_page)
8678                         return false;
8679         }
8680
8681         if (nested_cpu_has_posted_intr(vmcs12)) {
8682                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8683                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
8684                         return false;
8685
8686                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8687                         kunmap(vmx->nested.pi_desc_page);
8688                         nested_release_page(vmx->nested.pi_desc_page);
8689                 }
8690                 vmx->nested.pi_desc_page =
8691                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8692                 if (!vmx->nested.pi_desc_page)
8693                         return false;
8694
8695                 vmx->nested.pi_desc =
8696                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8697                 if (!vmx->nested.pi_desc) {
8698                         nested_release_page_clean(vmx->nested.pi_desc_page);
8699                         return false;
8700                 }
8701                 vmx->nested.pi_desc =
8702                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
8703                         (unsigned long)(vmcs12->posted_intr_desc_addr &
8704                         (PAGE_SIZE - 1)));
8705         }
8706
8707         return true;
8708 }
8709
8710 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8711 {
8712         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8713         struct vcpu_vmx *vmx = to_vmx(vcpu);
8714
8715         if (vcpu->arch.virtual_tsc_khz == 0)
8716                 return;
8717
8718         /* Make sure short timeouts reliably trigger an immediate vmexit.
8719          * hrtimer_start does not guarantee this. */
8720         if (preemption_timeout <= 1) {
8721                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8722                 return;
8723         }
8724
8725         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8726         preemption_timeout *= 1000000;
8727         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8728         hrtimer_start(&vmx->nested.preemption_timer,
8729                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8730 }
8731
8732 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8733                                                 struct vmcs12 *vmcs12)
8734 {
8735         int maxphyaddr;
8736         u64 addr;
8737
8738         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8739                 return 0;
8740
8741         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8742                 WARN_ON(1);
8743                 return -EINVAL;
8744         }
8745         maxphyaddr = cpuid_maxphyaddr(vcpu);
8746
8747         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8748            ((addr + PAGE_SIZE) >> maxphyaddr))
8749                 return -EINVAL;
8750
8751         return 0;
8752 }
8753
8754 /*
8755  * Merge L0's and L1's MSR bitmap, return false to indicate that
8756  * we do not use the hardware.
8757  */
8758 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8759                                                struct vmcs12 *vmcs12)
8760 {
8761         int msr;
8762         struct page *page;
8763         unsigned long *msr_bitmap;
8764
8765         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8766                 return false;
8767
8768         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8769         if (!page) {
8770                 WARN_ON(1);
8771                 return false;
8772         }
8773         msr_bitmap = (unsigned long *)kmap(page);
8774         if (!msr_bitmap) {
8775                 nested_release_page_clean(page);
8776                 WARN_ON(1);
8777                 return false;
8778         }
8779
8780         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8781                 if (nested_cpu_has_apic_reg_virt(vmcs12))
8782                         for (msr = 0x800; msr <= 0x8ff; msr++)
8783                                 nested_vmx_disable_intercept_for_msr(
8784                                         msr_bitmap,
8785                                         vmx_msr_bitmap_nested,
8786                                         msr, MSR_TYPE_R);
8787                 /* TPR is allowed */
8788                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8789                                 vmx_msr_bitmap_nested,
8790                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8791                                 MSR_TYPE_R | MSR_TYPE_W);
8792                 if (nested_cpu_has_vid(vmcs12)) {
8793                         /* EOI and self-IPI are allowed */
8794                         nested_vmx_disable_intercept_for_msr(
8795                                 msr_bitmap,
8796                                 vmx_msr_bitmap_nested,
8797                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8798                                 MSR_TYPE_W);
8799                         nested_vmx_disable_intercept_for_msr(
8800                                 msr_bitmap,
8801                                 vmx_msr_bitmap_nested,
8802                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8803                                 MSR_TYPE_W);
8804                 }
8805         } else {
8806                 /*
8807                  * Enable reading intercept of all the x2apic
8808                  * MSRs. We should not rely on vmcs12 to do any
8809                  * optimizations here, it may have been modified
8810                  * by L1.
8811                  */
8812                 for (msr = 0x800; msr <= 0x8ff; msr++)
8813                         __vmx_enable_intercept_for_msr(
8814                                 vmx_msr_bitmap_nested,
8815                                 msr,
8816                                 MSR_TYPE_R);
8817
8818                 __vmx_enable_intercept_for_msr(
8819                                 vmx_msr_bitmap_nested,
8820                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8821                                 MSR_TYPE_W);
8822                 __vmx_enable_intercept_for_msr(
8823                                 vmx_msr_bitmap_nested,
8824                                 APIC_BASE_MSR + (APIC_EOI >> 4),
8825                                 MSR_TYPE_W);
8826                 __vmx_enable_intercept_for_msr(
8827                                 vmx_msr_bitmap_nested,
8828                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8829                                 MSR_TYPE_W);
8830         }
8831         kunmap(page);
8832         nested_release_page_clean(page);
8833
8834         return true;
8835 }
8836
8837 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8838                                            struct vmcs12 *vmcs12)
8839 {
8840         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8841             !nested_cpu_has_apic_reg_virt(vmcs12) &&
8842             !nested_cpu_has_vid(vmcs12) &&
8843             !nested_cpu_has_posted_intr(vmcs12))
8844                 return 0;
8845
8846         /*
8847          * If virtualize x2apic mode is enabled,
8848          * virtualize apic access must be disabled.
8849          */
8850         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8851             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8852                 return -EINVAL;
8853
8854         /*
8855          * If virtual interrupt delivery is enabled,
8856          * we must exit on external interrupts.
8857          */
8858         if (nested_cpu_has_vid(vmcs12) &&
8859            !nested_exit_on_intr(vcpu))
8860                 return -EINVAL;
8861
8862         /*
8863          * bits 15:8 should be zero in posted_intr_nv,
8864          * the descriptor address has been already checked
8865          * in nested_get_vmcs12_pages.
8866          */
8867         if (nested_cpu_has_posted_intr(vmcs12) &&
8868            (!nested_cpu_has_vid(vmcs12) ||
8869             !nested_exit_intr_ack_set(vcpu) ||
8870             vmcs12->posted_intr_nv & 0xff00))
8871                 return -EINVAL;
8872
8873         /* tpr shadow is needed by all apicv features. */
8874         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8875                 return -EINVAL;
8876
8877         return 0;
8878 }
8879
8880 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8881                                        unsigned long count_field,
8882                                        unsigned long addr_field)
8883 {
8884         int maxphyaddr;
8885         u64 count, addr;
8886
8887         if (vmcs12_read_any(vcpu, count_field, &count) ||
8888             vmcs12_read_any(vcpu, addr_field, &addr)) {
8889                 WARN_ON(1);
8890                 return -EINVAL;
8891         }
8892         if (count == 0)
8893                 return 0;
8894         maxphyaddr = cpuid_maxphyaddr(vcpu);
8895         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8896             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8897                 pr_warn_ratelimited(
8898                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8899                         addr_field, maxphyaddr, count, addr);
8900                 return -EINVAL;
8901         }
8902         return 0;
8903 }
8904
8905 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8906                                                 struct vmcs12 *vmcs12)
8907 {
8908         if (vmcs12->vm_exit_msr_load_count == 0 &&
8909             vmcs12->vm_exit_msr_store_count == 0 &&
8910             vmcs12->vm_entry_msr_load_count == 0)
8911                 return 0; /* Fast path */
8912         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8913                                         VM_EXIT_MSR_LOAD_ADDR) ||
8914             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8915                                         VM_EXIT_MSR_STORE_ADDR) ||
8916             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8917                                         VM_ENTRY_MSR_LOAD_ADDR))
8918                 return -EINVAL;
8919         return 0;
8920 }
8921
8922 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8923                                        struct vmx_msr_entry *e)
8924 {
8925         /* x2APIC MSR accesses are not allowed */
8926         if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8927                 return -EINVAL;
8928         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8929             e->index == MSR_IA32_UCODE_REV)
8930                 return -EINVAL;
8931         if (e->reserved != 0)
8932                 return -EINVAL;
8933         return 0;
8934 }
8935
8936 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8937                                      struct vmx_msr_entry *e)
8938 {
8939         if (e->index == MSR_FS_BASE ||
8940             e->index == MSR_GS_BASE ||
8941             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8942             nested_vmx_msr_check_common(vcpu, e))
8943                 return -EINVAL;
8944         return 0;
8945 }
8946
8947 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8948                                       struct vmx_msr_entry *e)
8949 {
8950         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8951             nested_vmx_msr_check_common(vcpu, e))
8952                 return -EINVAL;
8953         return 0;
8954 }
8955
8956 /*
8957  * Load guest's/host's msr at nested entry/exit.
8958  * return 0 for success, entry index for failure.
8959  */
8960 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8961 {
8962         u32 i;
8963         struct vmx_msr_entry e;
8964         struct msr_data msr;
8965
8966         msr.host_initiated = false;
8967         for (i = 0; i < count; i++) {
8968                 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8969                                    &e, sizeof(e))) {
8970                         pr_warn_ratelimited(
8971                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8972                                 __func__, i, gpa + i * sizeof(e));
8973                         goto fail;
8974                 }
8975                 if (nested_vmx_load_msr_check(vcpu, &e)) {
8976                         pr_warn_ratelimited(
8977                                 "%s check failed (%u, 0x%x, 0x%x)\n",
8978                                 __func__, i, e.index, e.reserved);
8979                         goto fail;
8980                 }
8981                 msr.index = e.index;
8982                 msr.data = e.value;
8983                 if (kvm_set_msr(vcpu, &msr)) {
8984                         pr_warn_ratelimited(
8985                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8986                                 __func__, i, e.index, e.value);
8987                         goto fail;
8988                 }
8989         }
8990         return 0;
8991 fail:
8992         return i + 1;
8993 }
8994
8995 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8996 {
8997         u32 i;
8998         struct vmx_msr_entry e;
8999
9000         for (i = 0; i < count; i++) {
9001                 if (kvm_read_guest(vcpu->kvm,
9002                                    gpa + i * sizeof(e),
9003                                    &e, 2 * sizeof(u32))) {
9004                         pr_warn_ratelimited(
9005                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9006                                 __func__, i, gpa + i * sizeof(e));
9007                         return -EINVAL;
9008                 }
9009                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9010                         pr_warn_ratelimited(
9011                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9012                                 __func__, i, e.index, e.reserved);
9013                         return -EINVAL;
9014                 }
9015                 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9016                         pr_warn_ratelimited(
9017                                 "%s cannot read MSR (%u, 0x%x)\n",
9018                                 __func__, i, e.index);
9019                         return -EINVAL;
9020                 }
9021                 if (kvm_write_guest(vcpu->kvm,
9022                                     gpa + i * sizeof(e) +
9023                                         offsetof(struct vmx_msr_entry, value),
9024                                     &e.value, sizeof(e.value))) {
9025                         pr_warn_ratelimited(
9026                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9027                                 __func__, i, e.index, e.value);
9028                         return -EINVAL;
9029                 }
9030         }
9031         return 0;
9032 }
9033
9034 /*
9035  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9036  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9037  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9038  * guest in a way that will both be appropriate to L1's requests, and our
9039  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9040  * function also has additional necessary side-effects, like setting various
9041  * vcpu->arch fields.
9042  */
9043 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9044 {
9045         struct vcpu_vmx *vmx = to_vmx(vcpu);
9046         u32 exec_control;
9047
9048         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9049         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9050         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9051         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9052         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9053         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9054         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9055         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9056         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9057         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9058         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9059         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9060         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9061         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9062         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9063         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9064         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9065         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9066         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9067         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9068         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9069         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9070         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9071         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9072         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9073         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9074         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9075         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9076         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9077         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9078         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9079         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9080         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9081         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9082         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9083         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9084
9085         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9086                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9087                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9088         } else {
9089                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9090                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9091         }
9092         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9093                 vmcs12->vm_entry_intr_info_field);
9094         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9095                 vmcs12->vm_entry_exception_error_code);
9096         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9097                 vmcs12->vm_entry_instruction_len);
9098         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9099                 vmcs12->guest_interruptibility_info);
9100         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9101         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9102         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9103                 vmcs12->guest_pending_dbg_exceptions);
9104         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9105         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9106
9107         if (nested_cpu_has_xsaves(vmcs12))
9108                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9109         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9110
9111         exec_control = vmcs12->pin_based_vm_exec_control;
9112         exec_control |= vmcs_config.pin_based_exec_ctrl;
9113         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9114
9115         if (nested_cpu_has_posted_intr(vmcs12)) {
9116                 /*
9117                  * Note that we use L0's vector here and in
9118                  * vmx_deliver_nested_posted_interrupt.
9119                  */
9120                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9121                 vmx->nested.pi_pending = false;
9122                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9123                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9124                         page_to_phys(vmx->nested.pi_desc_page) +
9125                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9126                         (PAGE_SIZE - 1)));
9127         } else
9128                 exec_control &= ~PIN_BASED_POSTED_INTR;
9129
9130         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9131
9132         vmx->nested.preemption_timer_expired = false;
9133         if (nested_cpu_has_preemption_timer(vmcs12))
9134                 vmx_start_preemption_timer(vcpu);
9135
9136         /*
9137          * Whether page-faults are trapped is determined by a combination of
9138          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9139          * If enable_ept, L0 doesn't care about page faults and we should
9140          * set all of these to L1's desires. However, if !enable_ept, L0 does
9141          * care about (at least some) page faults, and because it is not easy
9142          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9143          * to exit on each and every L2 page fault. This is done by setting
9144          * MASK=MATCH=0 and (see below) EB.PF=1.
9145          * Note that below we don't need special code to set EB.PF beyond the
9146          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9147          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9148          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9149          *
9150          * A problem with this approach (when !enable_ept) is that L1 may be
9151          * injected with more page faults than it asked for. This could have
9152          * caused problems, but in practice existing hypervisors don't care.
9153          * To fix this, we will need to emulate the PFEC checking (on the L1
9154          * page tables), using walk_addr(), when injecting PFs to L1.
9155          */
9156         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9157                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9158         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9159                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9160
9161         if (cpu_has_secondary_exec_ctrls()) {
9162                 exec_control = vmx_secondary_exec_control(vmx);
9163                 if (!vmx->rdtscp_enabled)
9164                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
9165                 /* Take the following fields only from vmcs12 */
9166                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9167                                   SECONDARY_EXEC_RDTSCP |
9168                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9169                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9170                 if (nested_cpu_has(vmcs12,
9171                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9172                         exec_control |= vmcs12->secondary_vm_exec_control;
9173
9174                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9175                         /*
9176                          * If translation failed, no matter: This feature asks
9177                          * to exit when accessing the given address, and if it
9178                          * can never be accessed, this feature won't do
9179                          * anything anyway.
9180                          */
9181                         if (!vmx->nested.apic_access_page)
9182                                 exec_control &=
9183                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9184                         else
9185                                 vmcs_write64(APIC_ACCESS_ADDR,
9186                                   page_to_phys(vmx->nested.apic_access_page));
9187                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9188                             (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9189                         exec_control |=
9190                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9191                         kvm_vcpu_reload_apic_access_page(vcpu);
9192                 }
9193
9194                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9195                         vmcs_write64(EOI_EXIT_BITMAP0,
9196                                 vmcs12->eoi_exit_bitmap0);
9197                         vmcs_write64(EOI_EXIT_BITMAP1,
9198                                 vmcs12->eoi_exit_bitmap1);
9199                         vmcs_write64(EOI_EXIT_BITMAP2,
9200                                 vmcs12->eoi_exit_bitmap2);
9201                         vmcs_write64(EOI_EXIT_BITMAP3,
9202                                 vmcs12->eoi_exit_bitmap3);
9203                         vmcs_write16(GUEST_INTR_STATUS,
9204                                 vmcs12->guest_intr_status);
9205                 }
9206
9207                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9208         }
9209
9210
9211         /*
9212          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9213          * Some constant fields are set here by vmx_set_constant_host_state().
9214          * Other fields are different per CPU, and will be set later when
9215          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9216          */
9217         vmx_set_constant_host_state(vmx);
9218
9219         /*
9220          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9221          * entry, but only if the current (host) sp changed from the value
9222          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9223          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9224          * here we just force the write to happen on entry.
9225          */
9226         vmx->host_rsp = 0;
9227
9228         exec_control = vmx_exec_control(vmx); /* L0's desires */
9229         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9230         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9231         exec_control &= ~CPU_BASED_TPR_SHADOW;
9232         exec_control |= vmcs12->cpu_based_vm_exec_control;
9233
9234         if (exec_control & CPU_BASED_TPR_SHADOW) {
9235                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9236                                 page_to_phys(vmx->nested.virtual_apic_page));
9237                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9238         }
9239
9240         if (cpu_has_vmx_msr_bitmap() &&
9241             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9242                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9243                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9244         } else
9245                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9246
9247         /*
9248          * Merging of IO bitmap not currently supported.
9249          * Rather, exit every time.
9250          */
9251         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9252         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9253
9254         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9255
9256         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9257          * bitwise-or of what L1 wants to trap for L2, and what we want to
9258          * trap. Note that CR0.TS also needs updating - we do this later.
9259          */
9260         update_exception_bitmap(vcpu);
9261         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9262         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9263
9264         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9265          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9266          * bits are further modified by vmx_set_efer() below.
9267          */
9268         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9269
9270         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9271          * emulated by vmx_set_efer(), below.
9272          */
9273         vm_entry_controls_init(vmx,
9274                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9275                         ~VM_ENTRY_IA32E_MODE) |
9276                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9277
9278         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9279                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9280                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9281         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9282                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9283
9284
9285         set_cr4_guest_host_mask(vmx);
9286
9287         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9288                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9289
9290         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9291                 vmcs_write64(TSC_OFFSET,
9292                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9293         else
9294                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9295
9296         if (enable_vpid) {
9297                 /*
9298                  * Trivially support vpid by letting L2s share their parent
9299                  * L1's vpid. TODO: move to a more elaborate solution, giving
9300                  * each L2 its own vpid and exposing the vpid feature to L1.
9301                  */
9302                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9303                 vmx_flush_tlb(vcpu);
9304         }
9305
9306         if (nested_cpu_has_ept(vmcs12)) {
9307                 kvm_mmu_unload(vcpu);
9308                 nested_ept_init_mmu_context(vcpu);
9309         }
9310
9311         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9312                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9313         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9314                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9315         else
9316                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9317         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9318         vmx_set_efer(vcpu, vcpu->arch.efer);
9319
9320         /*
9321          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9322          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9323          * The CR0_READ_SHADOW is what L2 should have expected to read given
9324          * the specifications by L1; It's not enough to take
9325          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9326          * have more bits than L1 expected.
9327          */
9328         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9329         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9330
9331         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9332         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9333
9334         /* shadow page tables on either EPT or shadow page tables */
9335         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9336         kvm_mmu_reset_context(vcpu);
9337
9338         if (!enable_ept)
9339                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9340
9341         /*
9342          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9343          */
9344         if (enable_ept) {
9345                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9346                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9347                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9348                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9349         }
9350
9351         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9352         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9353 }
9354
9355 /*
9356  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9357  * for running an L2 nested guest.
9358  */
9359 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9360 {
9361         struct vmcs12 *vmcs12;
9362         struct vcpu_vmx *vmx = to_vmx(vcpu);
9363         int cpu;
9364         struct loaded_vmcs *vmcs02;
9365         bool ia32e;
9366         u32 msr_entry_idx;
9367
9368         if (!nested_vmx_check_permission(vcpu) ||
9369             !nested_vmx_check_vmcs12(vcpu))
9370                 return 1;
9371
9372         skip_emulated_instruction(vcpu);
9373         vmcs12 = get_vmcs12(vcpu);
9374
9375         if (enable_shadow_vmcs)
9376                 copy_shadow_to_vmcs12(vmx);
9377
9378         /*
9379          * The nested entry process starts with enforcing various prerequisites
9380          * on vmcs12 as required by the Intel SDM, and act appropriately when
9381          * they fail: As the SDM explains, some conditions should cause the
9382          * instruction to fail, while others will cause the instruction to seem
9383          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9384          * To speed up the normal (success) code path, we should avoid checking
9385          * for misconfigurations which will anyway be caught by the processor
9386          * when using the merged vmcs02.
9387          */
9388         if (vmcs12->launch_state == launch) {
9389                 nested_vmx_failValid(vcpu,
9390                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9391                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9392                 return 1;
9393         }
9394
9395         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9396             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9397                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9398                 return 1;
9399         }
9400
9401         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9402                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9403                 return 1;
9404         }
9405
9406         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9407                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9408                 return 1;
9409         }
9410
9411         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9412                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9413                 return 1;
9414         }
9415
9416         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9417                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9418                 return 1;
9419         }
9420
9421         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9422                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9423                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9424             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9425                                 vmx->nested.nested_vmx_secondary_ctls_low,
9426                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9427             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9428                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9429                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9430             !vmx_control_verify(vmcs12->vm_exit_controls,
9431                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9432                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9433             !vmx_control_verify(vmcs12->vm_entry_controls,
9434                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9435                                 vmx->nested.nested_vmx_entry_ctls_high))
9436         {
9437                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9438                 return 1;
9439         }
9440
9441         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9442             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9443                 nested_vmx_failValid(vcpu,
9444                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9445                 return 1;
9446         }
9447
9448         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9449             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9450                 nested_vmx_entry_failure(vcpu, vmcs12,
9451                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9452                 return 1;
9453         }
9454         if (vmcs12->vmcs_link_pointer != -1ull) {
9455                 nested_vmx_entry_failure(vcpu, vmcs12,
9456                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9457                 return 1;
9458         }
9459
9460         /*
9461          * If the load IA32_EFER VM-entry control is 1, the following checks
9462          * are performed on the field for the IA32_EFER MSR:
9463          * - Bits reserved in the IA32_EFER MSR must be 0.
9464          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9465          *   the IA-32e mode guest VM-exit control. It must also be identical
9466          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9467          *   CR0.PG) is 1.
9468          */
9469         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9470                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9471                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9472                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9473                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9474                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9475                         nested_vmx_entry_failure(vcpu, vmcs12,
9476                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9477                         return 1;
9478                 }
9479         }
9480
9481         /*
9482          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9483          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9484          * the values of the LMA and LME bits in the field must each be that of
9485          * the host address-space size VM-exit control.
9486          */
9487         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9488                 ia32e = (vmcs12->vm_exit_controls &
9489                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9490                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9491                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9492                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9493                         nested_vmx_entry_failure(vcpu, vmcs12,
9494                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9495                         return 1;
9496                 }
9497         }
9498
9499         /*
9500          * We're finally done with prerequisite checking, and can start with
9501          * the nested entry.
9502          */
9503
9504         vmcs02 = nested_get_current_vmcs02(vmx);
9505         if (!vmcs02)
9506                 return -ENOMEM;
9507
9508         enter_guest_mode(vcpu);
9509
9510         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9511
9512         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9513                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9514
9515         cpu = get_cpu();
9516         vmx->loaded_vmcs = vmcs02;
9517         vmx_vcpu_put(vcpu);
9518         vmx_vcpu_load(vcpu, cpu);
9519         vcpu->cpu = cpu;
9520         put_cpu();
9521
9522         vmx_segment_cache_clear(vmx);
9523
9524         prepare_vmcs02(vcpu, vmcs12);
9525
9526         msr_entry_idx = nested_vmx_load_msr(vcpu,
9527                                             vmcs12->vm_entry_msr_load_addr,
9528                                             vmcs12->vm_entry_msr_load_count);
9529         if (msr_entry_idx) {
9530                 leave_guest_mode(vcpu);
9531                 vmx_load_vmcs01(vcpu);
9532                 nested_vmx_entry_failure(vcpu, vmcs12,
9533                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9534                 return 1;
9535         }
9536
9537         vmcs12->launch_state = 1;
9538
9539         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9540                 return kvm_vcpu_halt(vcpu);
9541
9542         vmx->nested.nested_run_pending = 1;
9543
9544         /*
9545          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9546          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9547          * returned as far as L1 is concerned. It will only return (and set
9548          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9549          */
9550         return 1;
9551 }
9552
9553 /*
9554  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9555  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9556  * This function returns the new value we should put in vmcs12.guest_cr0.
9557  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9558  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9559  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9560  *     didn't trap the bit, because if L1 did, so would L0).
9561  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9562  *     been modified by L2, and L1 knows it. So just leave the old value of
9563  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9564  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9565  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9566  *     changed these bits, and therefore they need to be updated, but L0
9567  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9568  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9569  */
9570 static inline unsigned long
9571 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9572 {
9573         return
9574         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9575         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9576         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9577                         vcpu->arch.cr0_guest_owned_bits));
9578 }
9579
9580 static inline unsigned long
9581 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9582 {
9583         return
9584         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9585         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9586         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9587                         vcpu->arch.cr4_guest_owned_bits));
9588 }
9589
9590 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9591                                        struct vmcs12 *vmcs12)
9592 {
9593         u32 idt_vectoring;
9594         unsigned int nr;
9595
9596         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9597                 nr = vcpu->arch.exception.nr;
9598                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9599
9600                 if (kvm_exception_is_soft(nr)) {
9601                         vmcs12->vm_exit_instruction_len =
9602                                 vcpu->arch.event_exit_inst_len;
9603                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9604                 } else
9605                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9606
9607                 if (vcpu->arch.exception.has_error_code) {
9608                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9609                         vmcs12->idt_vectoring_error_code =
9610                                 vcpu->arch.exception.error_code;
9611                 }
9612
9613                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9614         } else if (vcpu->arch.nmi_injected) {
9615                 vmcs12->idt_vectoring_info_field =
9616                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9617         } else if (vcpu->arch.interrupt.pending) {
9618                 nr = vcpu->arch.interrupt.nr;
9619                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9620
9621                 if (vcpu->arch.interrupt.soft) {
9622                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
9623                         vmcs12->vm_entry_instruction_len =
9624                                 vcpu->arch.event_exit_inst_len;
9625                 } else
9626                         idt_vectoring |= INTR_TYPE_EXT_INTR;
9627
9628                 vmcs12->idt_vectoring_info_field = idt_vectoring;
9629         }
9630 }
9631
9632 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9633 {
9634         struct vcpu_vmx *vmx = to_vmx(vcpu);
9635
9636         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9637             vmx->nested.preemption_timer_expired) {
9638                 if (vmx->nested.nested_run_pending)
9639                         return -EBUSY;
9640                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9641                 return 0;
9642         }
9643
9644         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9645                 if (vmx->nested.nested_run_pending ||
9646                     vcpu->arch.interrupt.pending)
9647                         return -EBUSY;
9648                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9649                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
9650                                   INTR_INFO_VALID_MASK, 0);
9651                 /*
9652                  * The NMI-triggered VM exit counts as injection:
9653                  * clear this one and block further NMIs.
9654                  */
9655                 vcpu->arch.nmi_pending = 0;
9656                 vmx_set_nmi_mask(vcpu, true);
9657                 return 0;
9658         }
9659
9660         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9661             nested_exit_on_intr(vcpu)) {
9662                 if (vmx->nested.nested_run_pending)
9663                         return -EBUSY;
9664                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9665                 return 0;
9666         }
9667
9668         return vmx_complete_nested_posted_interrupt(vcpu);
9669 }
9670
9671 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9672 {
9673         ktime_t remaining =
9674                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9675         u64 value;
9676
9677         if (ktime_to_ns(remaining) <= 0)
9678                 return 0;
9679
9680         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9681         do_div(value, 1000000);
9682         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9683 }
9684
9685 /*
9686  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9687  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9688  * and this function updates it to reflect the changes to the guest state while
9689  * L2 was running (and perhaps made some exits which were handled directly by L0
9690  * without going back to L1), and to reflect the exit reason.
9691  * Note that we do not have to copy here all VMCS fields, just those that
9692  * could have changed by the L2 guest or the exit - i.e., the guest-state and
9693  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9694  * which already writes to vmcs12 directly.
9695  */
9696 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9697                            u32 exit_reason, u32 exit_intr_info,
9698                            unsigned long exit_qualification)
9699 {
9700         /* update guest state fields: */
9701         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9702         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9703
9704         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9705         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9706         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9707
9708         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9709         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9710         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9711         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9712         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9713         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9714         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9715         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9716         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9717         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9718         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9719         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9720         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9721         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9722         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9723         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9724         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9725         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9726         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9727         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9728         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9729         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9730         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9731         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9732         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9733         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9734         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9735         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9736         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9737         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9738         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9739         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9740         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9741         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9742         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9743         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9744
9745         vmcs12->guest_interruptibility_info =
9746                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9747         vmcs12->guest_pending_dbg_exceptions =
9748                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9749         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9750                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9751         else
9752                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9753
9754         if (nested_cpu_has_preemption_timer(vmcs12)) {
9755                 if (vmcs12->vm_exit_controls &
9756                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9757                         vmcs12->vmx_preemption_timer_value =
9758                                 vmx_get_preemption_timer_value(vcpu);
9759                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9760         }
9761
9762         /*
9763          * In some cases (usually, nested EPT), L2 is allowed to change its
9764          * own CR3 without exiting. If it has changed it, we must keep it.
9765          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9766          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9767          *
9768          * Additionally, restore L2's PDPTR to vmcs12.
9769          */
9770         if (enable_ept) {
9771                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9772                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9773                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9774                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9775                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9776         }
9777
9778         if (nested_cpu_has_vid(vmcs12))
9779                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9780
9781         vmcs12->vm_entry_controls =
9782                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9783                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9784
9785         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9786                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9787                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9788         }
9789
9790         /* TODO: These cannot have changed unless we have MSR bitmaps and
9791          * the relevant bit asks not to trap the change */
9792         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9793                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9794         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9795                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9796         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9797         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9798         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9799         if (vmx_mpx_supported())
9800                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9801         if (nested_cpu_has_xsaves(vmcs12))
9802                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9803
9804         /* update exit information fields: */
9805
9806         vmcs12->vm_exit_reason = exit_reason;
9807         vmcs12->exit_qualification = exit_qualification;
9808
9809         vmcs12->vm_exit_intr_info = exit_intr_info;
9810         if ((vmcs12->vm_exit_intr_info &
9811              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9812             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9813                 vmcs12->vm_exit_intr_error_code =
9814                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9815         vmcs12->idt_vectoring_info_field = 0;
9816         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9817         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9818
9819         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9820                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9821                  * instead of reading the real value. */
9822                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9823
9824                 /*
9825                  * Transfer the event that L0 or L1 may wanted to inject into
9826                  * L2 to IDT_VECTORING_INFO_FIELD.
9827                  */
9828                 vmcs12_save_pending_event(vcpu, vmcs12);
9829         }
9830
9831         /*
9832          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9833          * preserved above and would only end up incorrectly in L1.
9834          */
9835         vcpu->arch.nmi_injected = false;
9836         kvm_clear_exception_queue(vcpu);
9837         kvm_clear_interrupt_queue(vcpu);
9838 }
9839
9840 /*
9841  * A part of what we need to when the nested L2 guest exits and we want to
9842  * run its L1 parent, is to reset L1's guest state to the host state specified
9843  * in vmcs12.
9844  * This function is to be called not only on normal nested exit, but also on
9845  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9846  * Failures During or After Loading Guest State").
9847  * This function should be called when the active VMCS is L1's (vmcs01).
9848  */
9849 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9850                                    struct vmcs12 *vmcs12)
9851 {
9852         struct kvm_segment seg;
9853
9854         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9855                 vcpu->arch.efer = vmcs12->host_ia32_efer;
9856         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9857                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9858         else
9859                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9860         vmx_set_efer(vcpu, vcpu->arch.efer);
9861
9862         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9863         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9864         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9865         /*
9866          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9867          * actually changed, because it depends on the current state of
9868          * fpu_active (which may have changed).
9869          * Note that vmx_set_cr0 refers to efer set above.
9870          */
9871         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9872         /*
9873          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9874          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9875          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9876          */
9877         update_exception_bitmap(vcpu);
9878         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9879         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9880
9881         /*
9882          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9883          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9884          */
9885         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9886         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9887
9888         nested_ept_uninit_mmu_context(vcpu);
9889
9890         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9891         kvm_mmu_reset_context(vcpu);
9892
9893         if (!enable_ept)
9894                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9895
9896         if (enable_vpid) {
9897                 /*
9898                  * Trivially support vpid by letting L2s share their parent
9899                  * L1's vpid. TODO: move to a more elaborate solution, giving
9900                  * each L2 its own vpid and exposing the vpid feature to L1.
9901                  */
9902                 vmx_flush_tlb(vcpu);
9903         }
9904
9905
9906         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9907         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9908         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9909         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9910         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9911
9912         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9913         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9914                 vmcs_write64(GUEST_BNDCFGS, 0);
9915
9916         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9917                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9918                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9919         }
9920         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9921                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9922                         vmcs12->host_ia32_perf_global_ctrl);
9923
9924         /* Set L1 segment info according to Intel SDM
9925             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9926         seg = (struct kvm_segment) {
9927                 .base = 0,
9928                 .limit = 0xFFFFFFFF,
9929                 .selector = vmcs12->host_cs_selector,
9930                 .type = 11,
9931                 .present = 1,
9932                 .s = 1,
9933                 .g = 1
9934         };
9935         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9936                 seg.l = 1;
9937         else
9938                 seg.db = 1;
9939         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9940         seg = (struct kvm_segment) {
9941                 .base = 0,
9942                 .limit = 0xFFFFFFFF,
9943                 .type = 3,
9944                 .present = 1,
9945                 .s = 1,
9946                 .db = 1,
9947                 .g = 1
9948         };
9949         seg.selector = vmcs12->host_ds_selector;
9950         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9951         seg.selector = vmcs12->host_es_selector;
9952         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9953         seg.selector = vmcs12->host_ss_selector;
9954         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9955         seg.selector = vmcs12->host_fs_selector;
9956         seg.base = vmcs12->host_fs_base;
9957         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9958         seg.selector = vmcs12->host_gs_selector;
9959         seg.base = vmcs12->host_gs_base;
9960         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9961         seg = (struct kvm_segment) {
9962                 .base = vmcs12->host_tr_base,
9963                 .limit = 0x67,
9964                 .selector = vmcs12->host_tr_selector,
9965                 .type = 11,
9966                 .present = 1
9967         };
9968         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9969
9970         kvm_set_dr(vcpu, 7, 0x400);
9971         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9972
9973         if (cpu_has_vmx_msr_bitmap())
9974                 vmx_set_msr_bitmap(vcpu);
9975
9976         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9977                                 vmcs12->vm_exit_msr_load_count))
9978                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9979 }
9980
9981 /*
9982  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9983  * and modify vmcs12 to make it see what it would expect to see there if
9984  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9985  */
9986 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9987                               u32 exit_intr_info,
9988                               unsigned long exit_qualification)
9989 {
9990         struct vcpu_vmx *vmx = to_vmx(vcpu);
9991         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9992
9993         /* trying to cancel vmlaunch/vmresume is a bug */
9994         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9995
9996         leave_guest_mode(vcpu);
9997         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9998                        exit_qualification);
9999
10000         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10001                                  vmcs12->vm_exit_msr_store_count))
10002                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10003
10004         vmx_load_vmcs01(vcpu);
10005
10006         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10007             && nested_exit_intr_ack_set(vcpu)) {
10008                 int irq = kvm_cpu_get_interrupt(vcpu);
10009                 WARN_ON(irq < 0);
10010                 vmcs12->vm_exit_intr_info = irq |
10011                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10012         }
10013
10014         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10015                                        vmcs12->exit_qualification,
10016                                        vmcs12->idt_vectoring_info_field,
10017                                        vmcs12->vm_exit_intr_info,
10018                                        vmcs12->vm_exit_intr_error_code,
10019                                        KVM_ISA_VMX);
10020
10021         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10022         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10023         vmx_segment_cache_clear(vmx);
10024
10025         /* if no vmcs02 cache requested, remove the one we used */
10026         if (VMCS02_POOL_SIZE == 0)
10027                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10028
10029         load_vmcs12_host_state(vcpu, vmcs12);
10030
10031         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10032         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10033
10034         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10035         vmx->host_rsp = 0;
10036
10037         /* Unpin physical memory we referred to in vmcs02 */
10038         if (vmx->nested.apic_access_page) {
10039                 nested_release_page(vmx->nested.apic_access_page);
10040                 vmx->nested.apic_access_page = NULL;
10041         }
10042         if (vmx->nested.virtual_apic_page) {
10043                 nested_release_page(vmx->nested.virtual_apic_page);
10044                 vmx->nested.virtual_apic_page = NULL;
10045         }
10046         if (vmx->nested.pi_desc_page) {
10047                 kunmap(vmx->nested.pi_desc_page);
10048                 nested_release_page(vmx->nested.pi_desc_page);
10049                 vmx->nested.pi_desc_page = NULL;
10050                 vmx->nested.pi_desc = NULL;
10051         }
10052
10053         /*
10054          * We are now running in L2, mmu_notifier will force to reload the
10055          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10056          */
10057         kvm_vcpu_reload_apic_access_page(vcpu);
10058
10059         /*
10060          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10061          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10062          * success or failure flag accordingly.
10063          */
10064         if (unlikely(vmx->fail)) {
10065                 vmx->fail = 0;
10066                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10067         } else
10068                 nested_vmx_succeed(vcpu);
10069         if (enable_shadow_vmcs)
10070                 vmx->nested.sync_shadow_vmcs = true;
10071
10072         /* in case we halted in L2 */
10073         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10074 }
10075
10076 /*
10077  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10078  */
10079 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10080 {
10081         if (is_guest_mode(vcpu))
10082                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10083         free_nested(to_vmx(vcpu));
10084 }
10085
10086 /*
10087  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10088  * 23.7 "VM-entry failures during or after loading guest state" (this also
10089  * lists the acceptable exit-reason and exit-qualification parameters).
10090  * It should only be called before L2 actually succeeded to run, and when
10091  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10092  */
10093 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10094                         struct vmcs12 *vmcs12,
10095                         u32 reason, unsigned long qualification)
10096 {
10097         load_vmcs12_host_state(vcpu, vmcs12);
10098         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10099         vmcs12->exit_qualification = qualification;
10100         nested_vmx_succeed(vcpu);
10101         if (enable_shadow_vmcs)
10102                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10103 }
10104
10105 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10106                                struct x86_instruction_info *info,
10107                                enum x86_intercept_stage stage)
10108 {
10109         return X86EMUL_CONTINUE;
10110 }
10111
10112 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10113 {
10114         if (ple_gap)
10115                 shrink_ple_window(vcpu);
10116 }
10117
10118 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10119                                      struct kvm_memory_slot *slot)
10120 {
10121         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10122         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10123 }
10124
10125 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10126                                        struct kvm_memory_slot *slot)
10127 {
10128         kvm_mmu_slot_set_dirty(kvm, slot);
10129 }
10130
10131 static void vmx_flush_log_dirty(struct kvm *kvm)
10132 {
10133         kvm_flush_pml_buffers(kvm);
10134 }
10135
10136 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10137                                            struct kvm_memory_slot *memslot,
10138                                            gfn_t offset, unsigned long mask)
10139 {
10140         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10141 }
10142
10143 static struct kvm_x86_ops vmx_x86_ops = {
10144         .cpu_has_kvm_support = cpu_has_kvm_support,
10145         .disabled_by_bios = vmx_disabled_by_bios,
10146         .hardware_setup = hardware_setup,
10147         .hardware_unsetup = hardware_unsetup,
10148         .check_processor_compatibility = vmx_check_processor_compat,
10149         .hardware_enable = hardware_enable,
10150         .hardware_disable = hardware_disable,
10151         .cpu_has_accelerated_tpr = report_flexpriority,
10152
10153         .vcpu_create = vmx_create_vcpu,
10154         .vcpu_free = vmx_free_vcpu,
10155         .vcpu_reset = vmx_vcpu_reset,
10156
10157         .prepare_guest_switch = vmx_save_host_state,
10158         .vcpu_load = vmx_vcpu_load,
10159         .vcpu_put = vmx_vcpu_put,
10160
10161         .update_db_bp_intercept = update_exception_bitmap,
10162         .get_msr = vmx_get_msr,
10163         .set_msr = vmx_set_msr,
10164         .get_segment_base = vmx_get_segment_base,
10165         .get_segment = vmx_get_segment,
10166         .set_segment = vmx_set_segment,
10167         .get_cpl = vmx_get_cpl,
10168         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10169         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10170         .decache_cr3 = vmx_decache_cr3,
10171         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10172         .set_cr0 = vmx_set_cr0,
10173         .set_cr3 = vmx_set_cr3,
10174         .set_cr4 = vmx_set_cr4,
10175         .set_efer = vmx_set_efer,
10176         .get_idt = vmx_get_idt,
10177         .set_idt = vmx_set_idt,
10178         .get_gdt = vmx_get_gdt,
10179         .set_gdt = vmx_set_gdt,
10180         .get_dr6 = vmx_get_dr6,
10181         .set_dr6 = vmx_set_dr6,
10182         .set_dr7 = vmx_set_dr7,
10183         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10184         .cache_reg = vmx_cache_reg,
10185         .get_rflags = vmx_get_rflags,
10186         .set_rflags = vmx_set_rflags,
10187         .fpu_activate = vmx_fpu_activate,
10188         .fpu_deactivate = vmx_fpu_deactivate,
10189
10190         .tlb_flush = vmx_flush_tlb,
10191
10192         .run = vmx_vcpu_run,
10193         .handle_exit = vmx_handle_exit,
10194         .skip_emulated_instruction = skip_emulated_instruction,
10195         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10196         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10197         .patch_hypercall = vmx_patch_hypercall,
10198         .set_irq = vmx_inject_irq,
10199         .set_nmi = vmx_inject_nmi,
10200         .queue_exception = vmx_queue_exception,
10201         .cancel_injection = vmx_cancel_injection,
10202         .interrupt_allowed = vmx_interrupt_allowed,
10203         .nmi_allowed = vmx_nmi_allowed,
10204         .get_nmi_mask = vmx_get_nmi_mask,
10205         .set_nmi_mask = vmx_set_nmi_mask,
10206         .enable_nmi_window = enable_nmi_window,
10207         .enable_irq_window = enable_irq_window,
10208         .update_cr8_intercept = update_cr8_intercept,
10209         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10210         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10211         .vm_has_apicv = vmx_vm_has_apicv,
10212         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10213         .hwapic_irr_update = vmx_hwapic_irr_update,
10214         .hwapic_isr_update = vmx_hwapic_isr_update,
10215         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10216         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10217
10218         .set_tss_addr = vmx_set_tss_addr,
10219         .get_tdp_level = get_ept_level,
10220         .get_mt_mask = vmx_get_mt_mask,
10221
10222         .get_exit_info = vmx_get_exit_info,
10223
10224         .get_lpage_level = vmx_get_lpage_level,
10225
10226         .cpuid_update = vmx_cpuid_update,
10227
10228         .rdtscp_supported = vmx_rdtscp_supported,
10229         .invpcid_supported = vmx_invpcid_supported,
10230
10231         .set_supported_cpuid = vmx_set_supported_cpuid,
10232
10233         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10234
10235         .set_tsc_khz = vmx_set_tsc_khz,
10236         .read_tsc_offset = vmx_read_tsc_offset,
10237         .write_tsc_offset = vmx_write_tsc_offset,
10238         .adjust_tsc_offset = vmx_adjust_tsc_offset,
10239         .compute_tsc_offset = vmx_compute_tsc_offset,
10240         .read_l1_tsc = vmx_read_l1_tsc,
10241
10242         .set_tdp_cr3 = vmx_set_cr3,
10243
10244         .check_intercept = vmx_check_intercept,
10245         .handle_external_intr = vmx_handle_external_intr,
10246         .mpx_supported = vmx_mpx_supported,
10247         .xsaves_supported = vmx_xsaves_supported,
10248
10249         .check_nested_events = vmx_check_nested_events,
10250
10251         .sched_in = vmx_sched_in,
10252
10253         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10254         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10255         .flush_log_dirty = vmx_flush_log_dirty,
10256         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10257 };
10258
10259 static int __init vmx_init(void)
10260 {
10261         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10262                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10263         if (r)
10264                 return r;
10265
10266 #ifdef CONFIG_KEXEC
10267         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10268                            crash_vmclear_local_loaded_vmcss);
10269 #endif
10270
10271         return 0;
10272 }
10273
10274 static void __exit vmx_exit(void)
10275 {
10276 #ifdef CONFIG_KEXEC
10277         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10278         synchronize_rcu();
10279 #endif
10280
10281         kvm_exit();
10282 }
10283
10284 module_init(vmx_init)
10285 module_exit(vmx_exit)