2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
38 unsigned force_split : 1;
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
49 static DEFINE_SPINLOCK(cpa_lock);
51 #define CPA_FLUSHTLB 1
53 #define CPA_PAGES_ARRAY 4
56 static unsigned long direct_pages_count[PG_LEVEL_NUM];
58 void update_page_count(int level, unsigned long pages)
60 /* Protect against CPA */
62 direct_pages_count[level] += pages;
63 spin_unlock(&pgd_lock);
66 static void split_page_count(int level)
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
72 void arch_report_meminfo(struct seq_file *m)
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
90 static inline void split_page_count(int level) { }
95 static inline unsigned long highmap_start_pfn(void)
97 return __pa(_text) >> PAGE_SHIFT;
100 static inline unsigned long highmap_end_pfn(void)
102 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 # define debug_pagealloc 1
110 # define debug_pagealloc 0
114 within(unsigned long addr, unsigned long start, unsigned long end)
116 return addr >= start && addr < end;
124 * clflush_cache_range - flush a cache range with clflush
125 * @vaddr: virtual start address
126 * @size: number of bytes to flush
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
131 void clflush_cache_range(void *vaddr, unsigned int size)
133 void *vend = vaddr + size - 1;
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
140 * Flush any possible final partial cacheline:
146 EXPORT_SYMBOL_GPL(clflush_cache_range);
148 static void __cpa_flush_all(void *arg)
150 unsigned long cache = (unsigned long)arg;
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
158 if (cache && boot_cpu_data.x86 >= 4)
162 static void cpa_flush_all(unsigned long cache)
164 BUG_ON(irqs_disabled());
166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
169 static void __cpa_flush_range(void *arg)
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
179 static void cpa_flush_range(unsigned long start, int numpages, int cache)
181 unsigned int i, level;
184 BUG_ON(irqs_disabled());
185 WARN_ON(PAGE_ALIGN(start) != start);
187 on_each_cpu(__cpa_flush_range, NULL, 1);
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
202 * Only flush present addresses:
204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
205 clflush_cache_range((void *) addr, PAGE_SIZE);
209 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
212 unsigned int i, level;
213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
215 BUG_ON(irqs_disabled());
217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
219 if (!cache || do_wbinvd)
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
228 for (i = 0; i < numpages; i++) {
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
237 pte = lookup_address(addr, &level);
240 * Only flush present addresses:
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
243 clflush_cache_range((void *)addr, PAGE_SIZE);
248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
253 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
256 pgprot_t forbidden = __pgprot(0);
259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
262 #ifdef CONFIG_PCI_BIOS
263 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
268 * The kernel text needs to be executable for obvious reasons
269 * Does not cover __inittext since that is gone later on. On
270 * 64bit we do not enforce !NX on the low mapping
272 if (within(address, (unsigned long)_text, (unsigned long)_etext))
273 pgprot_val(forbidden) |= _PAGE_NX;
276 * The .rodata section needs to be read-only. Using the pfn
277 * catches all aliases.
279 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
280 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
281 pgprot_val(forbidden) |= _PAGE_RW;
283 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
285 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
286 * kernel text mappings for the large page aligned text, rodata sections
287 * will be always read-only. For the kernel identity mappings covering
288 * the holes caused by this alignment can be anything that user asks.
290 * This will preserve the large page mappings for kernel text/data
293 if (kernel_set_to_readonly &&
294 within(address, (unsigned long)_text,
295 (unsigned long)__end_rodata_hpage_align)) {
299 * Don't enforce the !RW mapping for the kernel text mapping,
300 * if the current mapping is already using small page mapping.
301 * No need to work hard to preserve large page mappings in this
304 * This also fixes the Linux Xen paravirt guest boot failure
305 * (because of unexpected read-only mappings for kernel identity
306 * mappings). In this paravirt guest case, the kernel text
307 * mapping and the kernel identity mapping share the same
308 * page-table pages. Thus we can't really use different
309 * protections for the kernel text and identity mappings. Also,
310 * these shared mappings are made of small page mappings.
311 * Thus this don't enforce !RW mapping for small page kernel
312 * text mapping logic will help Linux Xen parvirt guest boot
315 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
316 pgprot_val(forbidden) |= _PAGE_RW;
320 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
326 * Lookup the page table entry for a virtual address. Return a pointer
327 * to the entry and the level of the mapping.
329 * Note: We return pud and pmd either when the entry is marked large
330 * or when the present bit is not set. Otherwise we would return a
331 * pointer to a nonexisting mapping.
333 pte_t *lookup_address(unsigned long address, unsigned int *level)
335 pgd_t *pgd = pgd_offset_k(address);
339 *level = PG_LEVEL_NONE;
344 pud = pud_offset(pgd, address);
348 *level = PG_LEVEL_1G;
349 if (pud_large(*pud) || !pud_present(*pud))
352 pmd = pmd_offset(pud, address);
356 *level = PG_LEVEL_2M;
357 if (pmd_large(*pmd) || !pmd_present(*pmd))
360 *level = PG_LEVEL_4K;
362 return pte_offset_kernel(pmd, address);
364 EXPORT_SYMBOL_GPL(lookup_address);
367 * Set the new pmd in all the pgds we know about:
369 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
372 set_pte_atomic(kpte, pte);
374 if (!SHARED_KERNEL_PMD) {
377 list_for_each_entry(page, &pgd_list, lru) {
382 pgd = (pgd_t *)page_address(page) + pgd_index(address);
383 pud = pud_offset(pgd, address);
384 pmd = pmd_offset(pud, address);
385 set_pte_atomic((pte_t *)pmd, pte);
392 try_preserve_large_page(pte_t *kpte, unsigned long address,
393 struct cpa_data *cpa)
395 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
396 pte_t new_pte, old_pte, *tmp;
397 pgprot_t old_prot, new_prot, req_prot;
401 if (cpa->force_split)
404 spin_lock(&pgd_lock);
406 * Check for races, another CPU might have split this page
409 tmp = lookup_address(address, &level);
415 psize = PMD_PAGE_SIZE;
416 pmask = PMD_PAGE_MASK;
420 psize = PUD_PAGE_SIZE;
421 pmask = PUD_PAGE_MASK;
430 * Calculate the number of pages, which fit into this large
431 * page starting at address:
433 nextpage_addr = (address + psize) & pmask;
434 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
435 if (numpages < cpa->numpages)
436 cpa->numpages = numpages;
439 * We are safe now. Check whether the new pgprot is the same:
442 old_prot = new_prot = req_prot = pte_pgprot(old_pte);
444 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
445 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
448 * Set the PSE and GLOBAL flags only if the PRESENT flag is
449 * set otherwise pmd_present/pmd_huge will return true even on
450 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
451 * for the ancient hardware that doesn't support it.
453 if (pgprot_val(new_prot) & _PAGE_PRESENT)
454 pgprot_val(new_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
456 pgprot_val(new_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
458 new_prot = canon_pgprot(new_prot);
461 * old_pte points to the large page base address. So we need
462 * to add the offset of the virtual address:
464 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
467 new_prot = static_protections(req_prot, address, pfn);
470 * We need to check the full range, whether
471 * static_protection() requires a different pgprot for one of
472 * the pages in the range we try to preserve:
474 addr = address & pmask;
475 pfn = pte_pfn(old_pte);
476 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
477 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
479 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
484 * If there are no changes, return. maxpages has been updated
487 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
493 * We need to change the attributes. Check, whether we can
494 * change the large page in one go. We request a split, when
495 * the address is not aligned and the number of pages is
496 * smaller than the number of pages in the large page. Note
497 * that we limited the number of possible pages already to
498 * the number of pages in the large page.
500 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
502 * The address is aligned and the number of pages
503 * covers the full page.
505 new_pte = pfn_pte(pte_pfn(old_pte), new_prot);
506 __set_pmd_pte(kpte, address, new_pte);
507 cpa->flags |= CPA_FLUSHTLB;
512 spin_unlock(&pgd_lock);
517 static int split_large_page(pte_t *kpte, unsigned long address)
519 unsigned long pfn, pfninc = 1;
520 unsigned int i, level;
525 if (!debug_pagealloc)
526 spin_unlock(&cpa_lock);
527 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
528 if (!debug_pagealloc)
529 spin_lock(&cpa_lock);
533 spin_lock(&pgd_lock);
535 * Check for races, another CPU might have split this page
538 tmp = lookup_address(address, &level);
542 pbase = (pte_t *)page_address(base);
543 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
544 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
546 * If we ever want to utilize the PAT bit, we need to
547 * update this function to make sure it's converted from
548 * bit 12 to bit 7 when we cross from the 2MB level to
551 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
554 if (level == PG_LEVEL_1G) {
555 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
557 * Set the PSE flags only if the PRESENT flag is set
558 * otherwise pmd_present/pmd_huge will return true
559 * even on a non present pmd.
561 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
562 pgprot_val(ref_prot) |= _PAGE_PSE;
564 pgprot_val(ref_prot) &= ~_PAGE_PSE;
569 * Set the GLOBAL flags only if the PRESENT flag is set
570 * otherwise pmd/pte_present will return true even on a non
571 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
572 * for the ancient hardware that doesn't support it.
574 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
575 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
577 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
580 * Get the target pfn from the original entry:
582 pfn = pte_pfn(*kpte);
583 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
584 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
586 if (address >= (unsigned long)__va(0) &&
587 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
588 split_page_count(level);
591 if (address >= (unsigned long)__va(1UL<<32) &&
592 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
593 split_page_count(level);
597 * Install the new, split up pagetable.
599 * We use the standard kernel pagetable protections for the new
600 * pagetable protections, the actual ptes set above control the
601 * primary protection behavior:
603 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
606 * Intel Atom errata AAH41 workaround.
608 * The real fix should be in hw or in a microcode update, but
609 * we also probabilistically try to reduce the window of having
610 * a large TLB mixed with 4K TLBs while instruction fetches are
619 * If we dropped out via the lookup_address check under
620 * pgd_lock then stick the page back into the pool:
624 spin_unlock(&pgd_lock);
629 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
633 * Ignore all non primary paths.
639 * Ignore the NULL PTE for kernel identity mapping, as it is expected
641 * Also set numpages to '1' indicating that we processed cpa req for
642 * one virtual address page and its pfn. TBD: numpages can be set based
643 * on the initial value and the level returned by lookup_address().
645 if (within(vaddr, PAGE_OFFSET,
646 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
648 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
651 WARN(1, KERN_WARNING "CPA: called for zero pte. "
652 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
659 static int __change_page_attr(struct cpa_data *cpa, int primary)
661 unsigned long address;
664 pte_t *kpte, old_pte;
666 if (cpa->flags & CPA_PAGES_ARRAY) {
667 struct page *page = cpa->pages[cpa->curpage];
668 if (unlikely(PageHighMem(page)))
670 address = (unsigned long)page_address(page);
671 } else if (cpa->flags & CPA_ARRAY)
672 address = cpa->vaddr[cpa->curpage];
674 address = *cpa->vaddr;
676 kpte = lookup_address(address, &level);
678 return __cpa_process_fault(cpa, address, primary);
681 if (!pte_val(old_pte))
682 return __cpa_process_fault(cpa, address, primary);
684 if (level == PG_LEVEL_4K) {
686 pgprot_t new_prot = pte_pgprot(old_pte);
687 unsigned long pfn = pte_pfn(old_pte);
689 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
690 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
692 new_prot = static_protections(new_prot, address, pfn);
695 * Set the GLOBAL flags only if the PRESENT flag is
696 * set otherwise pte_present will return true even on
697 * a non present pte. The canon_pgprot will clear
698 * _PAGE_GLOBAL for the ancient hardware that doesn't
701 if (pgprot_val(new_prot) & _PAGE_PRESENT)
702 pgprot_val(new_prot) |= _PAGE_GLOBAL;
704 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
707 * We need to keep the pfn from the existing PTE,
708 * after all we're only going to change it's attributes
709 * not the memory it points to
711 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
714 * Do we really change anything ?
716 if (pte_val(old_pte) != pte_val(new_pte)) {
717 set_pte_atomic(kpte, new_pte);
718 cpa->flags |= CPA_FLUSHTLB;
725 * Check, whether we can keep the large page intact
726 * and just change the pte:
728 do_split = try_preserve_large_page(kpte, address, cpa);
730 * When the range fits into the existing large page,
731 * return. cp->numpages and cpa->tlbflush have been updated in
738 * We have to split the large page:
740 err = split_large_page(kpte, address);
743 * Do a global flush tlb after splitting the large page
744 * and before we do the actual change page attribute in the PTE.
746 * With out this, we violate the TLB application note, that says
747 * "The TLBs may contain both ordinary and large-page
748 * translations for a 4-KByte range of linear addresses. This
749 * may occur if software modifies the paging structures so that
750 * the page size used for the address range changes. If the two
751 * translations differ with respect to page frame or attributes
752 * (e.g., permissions), processor behavior is undefined and may
753 * be implementation-specific."
755 * We do this global tlb flush inside the cpa_lock, so that we
756 * don't allow any other cpu, with stale tlb entries change the
757 * page attribute in parallel, that also falls into the
758 * just split large page entry.
767 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
769 static int cpa_process_alias(struct cpa_data *cpa)
771 struct cpa_data alias_cpa;
772 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
776 if (cpa->pfn >= max_pfn_mapped)
780 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
784 * No need to redo, when the primary call touched the direct
787 if (cpa->flags & CPA_PAGES_ARRAY) {
788 struct page *page = cpa->pages[cpa->curpage];
789 if (unlikely(PageHighMem(page)))
791 vaddr = (unsigned long)page_address(page);
792 } else if (cpa->flags & CPA_ARRAY)
793 vaddr = cpa->vaddr[cpa->curpage];
797 if (!(within(vaddr, PAGE_OFFSET,
798 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
801 alias_cpa.vaddr = &laddr;
802 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
804 ret = __change_page_attr_set_clr(&alias_cpa, 0);
811 * If the primary call didn't touch the high mapping already
812 * and the physical address is inside the kernel map, we need
813 * to touch the high mapped kernel as well:
815 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
816 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
817 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
818 __START_KERNEL_map - phys_base;
820 alias_cpa.vaddr = &temp_cpa_vaddr;
821 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
824 * The high mapping range is imprecise, so ignore the
827 __change_page_attr_set_clr(&alias_cpa, 0);
834 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
836 int ret, numpages = cpa->numpages;
840 * Store the remaining nr of pages for the large page
841 * preservation check.
843 cpa->numpages = numpages;
844 /* for array changes, we can't use large page */
845 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
848 if (!debug_pagealloc)
849 spin_lock(&cpa_lock);
850 ret = __change_page_attr(cpa, checkalias);
851 if (!debug_pagealloc)
852 spin_unlock(&cpa_lock);
857 ret = cpa_process_alias(cpa);
863 * Adjust the number of pages with the result of the
864 * CPA operation. Either a large page has been
865 * preserved or a single page update happened.
867 BUG_ON(cpa->numpages > numpages);
868 numpages -= cpa->numpages;
869 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
872 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
878 static inline int cache_attr(pgprot_t attr)
880 return pgprot_val(attr) &
881 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
884 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
885 pgprot_t mask_set, pgprot_t mask_clr,
886 int force_split, int in_flag,
890 int ret, cache, checkalias;
891 unsigned long baddr = 0;
894 * Check, if we are requested to change a not supported
897 mask_set = canon_pgprot(mask_set);
898 mask_clr = canon_pgprot(mask_clr);
899 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
902 /* Ensure we are PAGE_SIZE aligned */
903 if (in_flag & CPA_ARRAY) {
905 for (i = 0; i < numpages; i++) {
906 if (addr[i] & ~PAGE_MASK) {
907 addr[i] &= PAGE_MASK;
911 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
913 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
914 * No need to cehck in that case
916 if (*addr & ~PAGE_MASK) {
919 * People should not be passing in unaligned addresses:
924 * Save address for cache flush. *addr is modified in the call
925 * to __change_page_attr_set_clr() below.
930 /* Must avoid aliasing mappings in the highmem code */
937 cpa.numpages = numpages;
938 cpa.mask_set = mask_set;
939 cpa.mask_clr = mask_clr;
942 cpa.force_split = force_split;
944 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
945 cpa.flags |= in_flag;
947 /* No alias checking for _NX bit modifications */
948 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
950 ret = __change_page_attr_set_clr(&cpa, checkalias);
953 * Check whether we really changed something:
955 if (!(cpa.flags & CPA_FLUSHTLB))
959 * No need to flush, when we did not set any of the caching
962 cache = cache_attr(mask_set);
965 * On success we use clflush, when the CPU supports it to
966 * avoid the wbindv. If the CPU does not support it and in the
967 * error case we fall back to cpa_flush_all (which uses
970 if (!ret && cpu_has_clflush) {
971 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
972 cpa_flush_array(addr, numpages, cache,
975 cpa_flush_range(baddr, numpages, cache);
977 cpa_flush_all(cache);
983 static inline int change_page_attr_set(unsigned long *addr, int numpages,
984 pgprot_t mask, int array)
986 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
987 (array ? CPA_ARRAY : 0), NULL);
990 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
991 pgprot_t mask, int array)
993 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
994 (array ? CPA_ARRAY : 0), NULL);
997 static inline int cpa_set_pages_array(struct page **pages, int numpages,
1000 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1001 CPA_PAGES_ARRAY, pages);
1004 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1007 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1008 CPA_PAGES_ARRAY, pages);
1011 int _set_memory_uc(unsigned long addr, int numpages)
1014 * for now UC MINUS. see comments in ioremap_nocache()
1016 return change_page_attr_set(&addr, numpages,
1017 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1020 int set_memory_uc(unsigned long addr, int numpages)
1025 * for now UC MINUS. see comments in ioremap_nocache()
1027 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1028 _PAGE_CACHE_UC_MINUS, NULL);
1032 ret = _set_memory_uc(addr, numpages);
1039 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1043 EXPORT_SYMBOL(set_memory_uc);
1045 static int _set_memory_array(unsigned long *addr, int addrinarray,
1046 unsigned long new_type)
1052 * for now UC MINUS. see comments in ioremap_nocache()
1054 for (i = 0; i < addrinarray; i++) {
1055 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1061 ret = change_page_attr_set(addr, addrinarray,
1062 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1064 if (!ret && new_type == _PAGE_CACHE_WC)
1065 ret = change_page_attr_set_clr(addr, addrinarray,
1066 __pgprot(_PAGE_CACHE_WC),
1067 __pgprot(_PAGE_CACHE_MASK),
1068 0, CPA_ARRAY, NULL);
1075 for (j = 0; j < i; j++)
1076 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1081 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1083 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1085 EXPORT_SYMBOL(set_memory_array_uc);
1087 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1089 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1091 EXPORT_SYMBOL(set_memory_array_wc);
1093 int _set_memory_wc(unsigned long addr, int numpages)
1096 unsigned long addr_copy = addr;
1098 ret = change_page_attr_set(&addr, numpages,
1099 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1101 ret = change_page_attr_set_clr(&addr_copy, numpages,
1102 __pgprot(_PAGE_CACHE_WC),
1103 __pgprot(_PAGE_CACHE_MASK),
1109 int set_memory_wc(unsigned long addr, int numpages)
1114 return set_memory_uc(addr, numpages);
1116 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1117 _PAGE_CACHE_WC, NULL);
1121 ret = _set_memory_wc(addr, numpages);
1128 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1132 EXPORT_SYMBOL(set_memory_wc);
1134 int _set_memory_wb(unsigned long addr, int numpages)
1136 return change_page_attr_clear(&addr, numpages,
1137 __pgprot(_PAGE_CACHE_MASK), 0);
1140 int set_memory_wb(unsigned long addr, int numpages)
1144 ret = _set_memory_wb(addr, numpages);
1148 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1151 EXPORT_SYMBOL(set_memory_wb);
1153 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1158 ret = change_page_attr_clear(addr, addrinarray,
1159 __pgprot(_PAGE_CACHE_MASK), 1);
1163 for (i = 0; i < addrinarray; i++)
1164 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1168 EXPORT_SYMBOL(set_memory_array_wb);
1170 int set_memory_x(unsigned long addr, int numpages)
1172 if (!(__supported_pte_mask & _PAGE_NX))
1175 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1177 EXPORT_SYMBOL(set_memory_x);
1179 int set_memory_nx(unsigned long addr, int numpages)
1181 if (!(__supported_pte_mask & _PAGE_NX))
1184 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1186 EXPORT_SYMBOL(set_memory_nx);
1188 int set_memory_ro(unsigned long addr, int numpages)
1190 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1192 EXPORT_SYMBOL_GPL(set_memory_ro);
1194 int set_memory_rw(unsigned long addr, int numpages)
1196 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1198 EXPORT_SYMBOL_GPL(set_memory_rw);
1200 int set_memory_np(unsigned long addr, int numpages)
1202 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1205 int set_memory_4k(unsigned long addr, int numpages)
1207 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1208 __pgprot(0), 1, 0, NULL);
1211 int set_pages_uc(struct page *page, int numpages)
1213 unsigned long addr = (unsigned long)page_address(page);
1215 return set_memory_uc(addr, numpages);
1217 EXPORT_SYMBOL(set_pages_uc);
1219 static int _set_pages_array(struct page **pages, int addrinarray,
1220 unsigned long new_type)
1222 unsigned long start;
1228 for (i = 0; i < addrinarray; i++) {
1229 if (PageHighMem(pages[i]))
1231 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1232 end = start + PAGE_SIZE;
1233 if (reserve_memtype(start, end, new_type, NULL))
1237 ret = cpa_set_pages_array(pages, addrinarray,
1238 __pgprot(_PAGE_CACHE_UC_MINUS));
1239 if (!ret && new_type == _PAGE_CACHE_WC)
1240 ret = change_page_attr_set_clr(NULL, addrinarray,
1241 __pgprot(_PAGE_CACHE_WC),
1242 __pgprot(_PAGE_CACHE_MASK),
1243 0, CPA_PAGES_ARRAY, pages);
1246 return 0; /* Success */
1249 for (i = 0; i < free_idx; i++) {
1250 if (PageHighMem(pages[i]))
1252 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1253 end = start + PAGE_SIZE;
1254 free_memtype(start, end);
1259 int set_pages_array_uc(struct page **pages, int addrinarray)
1261 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1263 EXPORT_SYMBOL(set_pages_array_uc);
1265 int set_pages_array_wc(struct page **pages, int addrinarray)
1267 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1269 EXPORT_SYMBOL(set_pages_array_wc);
1271 int set_pages_wb(struct page *page, int numpages)
1273 unsigned long addr = (unsigned long)page_address(page);
1275 return set_memory_wb(addr, numpages);
1277 EXPORT_SYMBOL(set_pages_wb);
1279 int set_pages_array_wb(struct page **pages, int addrinarray)
1282 unsigned long start;
1286 retval = cpa_clear_pages_array(pages, addrinarray,
1287 __pgprot(_PAGE_CACHE_MASK));
1291 for (i = 0; i < addrinarray; i++) {
1292 if (PageHighMem(pages[i]))
1294 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1295 end = start + PAGE_SIZE;
1296 free_memtype(start, end);
1301 EXPORT_SYMBOL(set_pages_array_wb);
1303 int set_pages_x(struct page *page, int numpages)
1305 unsigned long addr = (unsigned long)page_address(page);
1307 return set_memory_x(addr, numpages);
1309 EXPORT_SYMBOL(set_pages_x);
1311 int set_pages_nx(struct page *page, int numpages)
1313 unsigned long addr = (unsigned long)page_address(page);
1315 return set_memory_nx(addr, numpages);
1317 EXPORT_SYMBOL(set_pages_nx);
1319 int set_pages_ro(struct page *page, int numpages)
1321 unsigned long addr = (unsigned long)page_address(page);
1323 return set_memory_ro(addr, numpages);
1326 int set_pages_rw(struct page *page, int numpages)
1328 unsigned long addr = (unsigned long)page_address(page);
1330 return set_memory_rw(addr, numpages);
1333 #ifdef CONFIG_DEBUG_PAGEALLOC
1335 static int __set_pages_p(struct page *page, int numpages)
1337 unsigned long tempaddr = (unsigned long) page_address(page);
1338 struct cpa_data cpa = { .vaddr = &tempaddr,
1339 .numpages = numpages,
1340 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1341 .mask_clr = __pgprot(0),
1345 * No alias checking needed for setting present flag. otherwise,
1346 * we may need to break large pages for 64-bit kernel text
1347 * mappings (this adds to complexity if we want to do this from
1348 * atomic context especially). Let's keep it simple!
1350 return __change_page_attr_set_clr(&cpa, 0);
1353 static int __set_pages_np(struct page *page, int numpages)
1355 unsigned long tempaddr = (unsigned long) page_address(page);
1356 struct cpa_data cpa = { .vaddr = &tempaddr,
1357 .numpages = numpages,
1358 .mask_set = __pgprot(0),
1359 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1363 * No alias checking needed for setting not present flag. otherwise,
1364 * we may need to break large pages for 64-bit kernel text
1365 * mappings (this adds to complexity if we want to do this from
1366 * atomic context especially). Let's keep it simple!
1368 return __change_page_attr_set_clr(&cpa, 0);
1371 void kernel_map_pages(struct page *page, int numpages, int enable)
1373 if (PageHighMem(page))
1376 debug_check_no_locks_freed(page_address(page),
1377 numpages * PAGE_SIZE);
1381 * The return value is ignored as the calls cannot fail.
1382 * Large pages for identity mappings are not used at boot time
1383 * and hence no memory allocations during large page split.
1386 __set_pages_p(page, numpages);
1388 __set_pages_np(page, numpages);
1391 * We should perform an IPI and flush all tlbs,
1392 * but that can deadlock->flush only current cpu:
1397 #ifdef CONFIG_HIBERNATION
1399 bool kernel_page_present(struct page *page)
1404 if (PageHighMem(page))
1407 pte = lookup_address((unsigned long)page_address(page), &level);
1408 return (pte_val(*pte) & _PAGE_PRESENT);
1411 #endif /* CONFIG_HIBERNATION */
1413 #endif /* CONFIG_DEBUG_PAGEALLOC */
1416 * The testcases use internal knowledge of the implementation that shouldn't
1417 * be exposed to the rest of the kernel. Include these directly here.
1419 #ifdef CONFIG_CPA_DEBUG
1420 #include "pageattr-test.c"