2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00ac7"
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS | ATA_FLAG_DETECT_POLLING,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
110 ATA_FLAG_DETECT_POLLING,
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
122 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
126 ich_pata_133 = 4, /* ICH up to UDMA 133 */
134 /* constants for mapping table */
140 NA = -2, /* not avaliable */
141 RV = -3, /* reserved */
143 PIIX_AHCI_DEVICE = 6,
148 const u16 port_enable;
149 const int present_shift;
153 struct piix_host_priv {
155 const struct piix_map_db *map_db;
158 static int piix_init_one (struct pci_dev *pdev,
159 const struct pci_device_id *ent);
160 static void piix_host_stop(struct ata_host *host);
161 static void piix_pata_error_handler(struct ata_port *ap);
162 static void ich_pata_error_handler(struct ata_port *ap);
163 static void piix_sata_error_handler(struct ata_port *ap);
164 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
165 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
166 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
168 static unsigned int in_module_init = 1;
170 static const struct pci_device_id piix_pci_tbl[] = {
171 #ifdef ATA_ENABLE_PATA
172 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
173 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
174 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
175 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
176 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
178 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel ICH (i810, i815, i840) UDMA 66*/
184 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
185 /* Intel ICH0 : UDMA 33*/
186 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
188 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
190 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH3 (E7500/1) UDMA 100 */
194 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
196 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
201 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
203 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* ICH6 (and 6) (i915) UDMA 100 */
205 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ICH7/7-R (i945, i975) UDMA 100*/
207 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
208 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* NOTE: The following PCI ids must be kept in sync with the
212 * list in drivers/pci/quirks.c.
216 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
218 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
219 /* 6300ESB (ICH5 variant with broken PCS present bits) */
220 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
221 /* 6300ESB pretending RAID */
222 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
223 /* 82801FB/FW (ICH6/ICH6W) */
224 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
225 /* 82801FR/FRW (ICH6R/ICH6RW) */
226 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
227 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
228 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
229 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
230 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
231 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
232 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* Enterprise Southbridge 2 (where's the datasheet?) */
234 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
235 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
236 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
237 /* SATA Controller 2 IDE (ICH8, ditto) */
238 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
239 /* Mobile SATA Controller IDE (ICH8M, ditto) */
240 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 { } /* terminate list */
245 static struct pci_driver piix_pci_driver = {
247 .id_table = piix_pci_tbl,
248 .probe = piix_init_one,
249 .remove = ata_pci_remove_one,
250 .suspend = ata_pci_device_suspend,
251 .resume = ata_pci_device_resume,
254 static struct scsi_host_template piix_sht = {
255 .module = THIS_MODULE,
257 .ioctl = ata_scsi_ioctl,
258 .queuecommand = ata_scsi_queuecmd,
259 .can_queue = ATA_DEF_QUEUE,
260 .this_id = ATA_SHT_THIS_ID,
261 .sg_tablesize = LIBATA_MAX_PRD,
262 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
263 .emulated = ATA_SHT_EMULATED,
264 .use_clustering = ATA_SHT_USE_CLUSTERING,
265 .proc_name = DRV_NAME,
266 .dma_boundary = ATA_DMA_BOUNDARY,
267 .slave_configure = ata_scsi_slave_config,
268 .slave_destroy = ata_scsi_slave_destroy,
269 .bios_param = ata_std_bios_param,
270 .resume = ata_scsi_device_resume,
271 .suspend = ata_scsi_device_suspend,
274 static const struct ata_port_operations piix_pata_ops = {
275 .port_disable = ata_port_disable,
276 .set_piomode = piix_set_piomode,
277 .set_dmamode = piix_set_dmamode,
278 .mode_filter = ata_pci_default_filter,
280 .tf_load = ata_tf_load,
281 .tf_read = ata_tf_read,
282 .check_status = ata_check_status,
283 .exec_command = ata_exec_command,
284 .dev_select = ata_std_dev_select,
286 .bmdma_setup = ata_bmdma_setup,
287 .bmdma_start = ata_bmdma_start,
288 .bmdma_stop = ata_bmdma_stop,
289 .bmdma_status = ata_bmdma_status,
290 .qc_prep = ata_qc_prep,
291 .qc_issue = ata_qc_issue_prot,
292 .data_xfer = ata_pio_data_xfer,
294 .freeze = ata_bmdma_freeze,
295 .thaw = ata_bmdma_thaw,
296 .error_handler = piix_pata_error_handler,
297 .post_internal_cmd = ata_bmdma_post_internal_cmd,
299 .irq_handler = ata_interrupt,
300 .irq_clear = ata_bmdma_irq_clear,
302 .port_start = ata_port_start,
303 .port_stop = ata_port_stop,
304 .host_stop = piix_host_stop,
307 static const struct ata_port_operations ich_pata_ops = {
308 .port_disable = ata_port_disable,
309 .set_piomode = piix_set_piomode,
310 .set_dmamode = ich_set_dmamode,
311 .mode_filter = ata_pci_default_filter,
313 .tf_load = ata_tf_load,
314 .tf_read = ata_tf_read,
315 .check_status = ata_check_status,
316 .exec_command = ata_exec_command,
317 .dev_select = ata_std_dev_select,
319 .bmdma_setup = ata_bmdma_setup,
320 .bmdma_start = ata_bmdma_start,
321 .bmdma_stop = ata_bmdma_stop,
322 .bmdma_status = ata_bmdma_status,
323 .qc_prep = ata_qc_prep,
324 .qc_issue = ata_qc_issue_prot,
325 .data_xfer = ata_pio_data_xfer,
327 .freeze = ata_bmdma_freeze,
328 .thaw = ata_bmdma_thaw,
329 .error_handler = ich_pata_error_handler,
330 .post_internal_cmd = ata_bmdma_post_internal_cmd,
332 .irq_handler = ata_interrupt,
333 .irq_clear = ata_bmdma_irq_clear,
335 .port_start = ata_port_start,
336 .port_stop = ata_port_stop,
337 .host_stop = ata_host_stop,
340 static const struct ata_port_operations piix_sata_ops = {
341 .port_disable = ata_port_disable,
343 .tf_load = ata_tf_load,
344 .tf_read = ata_tf_read,
345 .check_status = ata_check_status,
346 .exec_command = ata_exec_command,
347 .dev_select = ata_std_dev_select,
349 .bmdma_setup = ata_bmdma_setup,
350 .bmdma_start = ata_bmdma_start,
351 .bmdma_stop = ata_bmdma_stop,
352 .bmdma_status = ata_bmdma_status,
353 .qc_prep = ata_qc_prep,
354 .qc_issue = ata_qc_issue_prot,
355 .data_xfer = ata_pio_data_xfer,
357 .freeze = ata_bmdma_freeze,
358 .thaw = ata_bmdma_thaw,
359 .error_handler = piix_sata_error_handler,
360 .post_internal_cmd = ata_bmdma_post_internal_cmd,
362 .irq_handler = ata_interrupt,
363 .irq_clear = ata_bmdma_irq_clear,
365 .port_start = ata_port_start,
366 .port_stop = ata_port_stop,
367 .host_stop = piix_host_stop,
370 static const struct piix_map_db ich5_map_db = {
375 /* PM PS SM SS MAP */
376 { P0, NA, P1, NA }, /* 000b */
377 { P1, NA, P0, NA }, /* 001b */
380 { P0, P1, IDE, IDE }, /* 100b */
381 { P1, P0, IDE, IDE }, /* 101b */
382 { IDE, IDE, P0, P1 }, /* 110b */
383 { IDE, IDE, P1, P0 }, /* 111b */
387 static const struct piix_map_db ich6_map_db = {
392 /* PM PS SM SS MAP */
393 { P0, P2, P1, P3 }, /* 00b */
394 { IDE, IDE, P1, P3 }, /* 01b */
395 { P0, P2, IDE, IDE }, /* 10b */
400 static const struct piix_map_db ich6m_map_db = {
405 /* Map 01b isn't specified in the doc but some notebooks use
406 * it anyway. MAP 01b have been spotted on both ICH6M and
410 /* PM PS SM SS MAP */
411 { P0, P2, RV, RV }, /* 00b */
412 { IDE, IDE, P1, P3 }, /* 01b */
413 { P0, P2, IDE, IDE }, /* 10b */
418 static const struct piix_map_db ich8_map_db = {
423 /* PM PS SM SS MAP */
424 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
426 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
431 static const struct piix_map_db *piix_map_db_table[] = {
432 [ich5_sata] = &ich5_map_db,
433 [esb_sata] = &ich5_map_db,
434 [ich6_sata] = &ich6_map_db,
435 [ich6_sata_ahci] = &ich6_map_db,
436 [ich6m_sata_ahci] = &ich6m_map_db,
437 [ich8_sata_ahci] = &ich8_map_db,
440 static struct ata_port_info piix_port_info[] = {
441 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
444 .flags = PIIX_PATA_FLAGS,
445 .pio_mask = 0x1f, /* pio0-4 */
446 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
447 .udma_mask = ATA_UDMA_MASK_40C,
448 .port_ops = &piix_pata_ops,
451 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
454 .flags = PIIX_PATA_FLAGS,
455 .pio_mask = 0x1f, /* pio 0-4 */
456 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
457 .udma_mask = ATA_UDMA2, /* UDMA33 */
458 .port_ops = &ich_pata_ops,
460 /* ich_pata_66: 2 ICH controllers up to 66MHz */
463 .flags = PIIX_PATA_FLAGS,
464 .pio_mask = 0x1f, /* pio 0-4 */
465 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
466 .udma_mask = ATA_UDMA4,
467 .port_ops = &ich_pata_ops,
470 /* ich_pata_100: 3 */
473 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
474 .pio_mask = 0x1f, /* pio0-4 */
475 .mwdma_mask = 0x06, /* mwdma1-2 */
476 .udma_mask = ATA_UDMA5, /* udma0-5 */
477 .port_ops = &ich_pata_ops,
480 /* ich_pata_133: 4 ICH with full UDMA6 */
483 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
484 .pio_mask = 0x1f, /* pio 0-4 */
485 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
486 .udma_mask = ATA_UDMA6, /* UDMA133 */
487 .port_ops = &ich_pata_ops,
493 .flags = PIIX_SATA_FLAGS,
494 .pio_mask = 0x1f, /* pio0-4 */
495 .mwdma_mask = 0x07, /* mwdma0-2 */
496 .udma_mask = 0x7f, /* udma0-6 */
497 .port_ops = &piix_sata_ops,
500 /* i6300esb_sata: 6 */
503 .flags = PIIX_SATA_FLAGS,
504 .pio_mask = 0x1f, /* pio0-4 */
505 .mwdma_mask = 0x07, /* mwdma0-2 */
506 .udma_mask = 0x7f, /* udma0-6 */
507 .port_ops = &piix_sata_ops,
513 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
514 .pio_mask = 0x1f, /* pio0-4 */
515 .mwdma_mask = 0x07, /* mwdma0-2 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &piix_sata_ops,
520 /* ich6_sata_ahci: 8 */
523 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
525 .pio_mask = 0x1f, /* pio0-4 */
526 .mwdma_mask = 0x07, /* mwdma0-2 */
527 .udma_mask = 0x7f, /* udma0-6 */
528 .port_ops = &piix_sata_ops,
531 /* ich6m_sata_ahci: 9 */
534 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
536 .pio_mask = 0x1f, /* pio0-4 */
537 .mwdma_mask = 0x07, /* mwdma0-2 */
538 .udma_mask = 0x7f, /* udma0-6 */
539 .port_ops = &piix_sata_ops,
542 /* ich8_sata_ahci: 10 */
545 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
547 .pio_mask = 0x1f, /* pio0-4 */
548 .mwdma_mask = 0x07, /* mwdma0-2 */
549 .udma_mask = 0x7f, /* udma0-6 */
550 .port_ops = &piix_sata_ops,
555 static struct pci_bits piix_enable_bits[] = {
556 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
557 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
560 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
561 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
562 MODULE_LICENSE("GPL");
563 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
564 MODULE_VERSION(DRV_VERSION);
573 * List of laptops that use short cables rather than 80 wire
576 static const struct ich_laptop ich_laptop[] = {
577 /* devid, subvendor, subdev */
578 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
584 * piix_pata_cbl_detect - Probe host controller cable detect info
585 * @ap: Port for which cable detect info is desired
587 * Read 80c cable indicator from ATA PCI device's PCI config
588 * register. This register is normally set by firmware (BIOS).
591 * None (inherited from caller).
594 static void ich_pata_cbl_detect(struct ata_port *ap)
596 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
597 const struct ich_laptop *lap = &ich_laptop[0];
600 /* no 80c support in host controller? */
601 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
604 /* Check for specials - Acer Aspire 5602WLMi */
605 while (lap->device) {
606 if (lap->device == pdev->device &&
607 lap->subvendor == pdev->subsystem_vendor &&
608 lap->subdevice == pdev->subsystem_device) {
609 ap->cbl = ATA_CBL_PATA40_SHORT;
615 /* check BIOS cable detect results */
616 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
617 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
618 if ((tmp & mask) == 0)
621 ap->cbl = ATA_CBL_PATA80;
625 ap->cbl = ATA_CBL_PATA40;
629 * piix_pata_prereset - prereset for PATA host controller
634 * None (inherited from caller).
636 static int piix_pata_prereset(struct ata_port *ap)
638 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
640 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
643 ap->cbl = ATA_CBL_PATA40;
644 return ata_std_prereset(ap);
647 static void piix_pata_error_handler(struct ata_port *ap)
649 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
655 * ich_pata_prereset - prereset for PATA host controller
660 * None (inherited from caller).
662 static int ich_pata_prereset(struct ata_port *ap)
664 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
666 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
667 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
668 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
672 ich_pata_cbl_detect(ap);
674 return ata_std_prereset(ap);
677 static void ich_pata_error_handler(struct ata_port *ap)
679 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
683 static void piix_sata_error_handler(struct ata_port *ap)
685 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
690 * piix_set_piomode - Initialize host controller PATA PIO timings
691 * @ap: Port whose timings we are configuring
694 * Set PIO mode for device, in host controller PCI config space.
697 * None (inherited from caller).
700 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
702 unsigned int pio = adev->pio_mode - XFER_PIO_0;
703 struct pci_dev *dev = to_pci_dev(ap->host->dev);
704 unsigned int is_slave = (adev->devno != 0);
705 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
706 unsigned int slave_port = 0x44;
713 * See Intel Document 298600-004 for the timing programing rules
714 * for ICH controllers.
717 static const /* ISP RTC */
718 u8 timings[][2] = { { 0, 0 },
725 control |= 1; /* TIME1 enable */
726 if (ata_pio_need_iordy(adev))
727 control |= 2; /* IE enable */
729 /* Intel specifies that the PPE functionality is for disk only */
730 if (adev->class == ATA_DEV_ATA)
731 control |= 4; /* PPE enable */
733 pci_read_config_word(dev, master_port, &master_data);
735 /* Enable SITRE (seperate slave timing register) */
736 master_data |= 0x4000;
737 /* enable PPE1, IE1 and TIME1 as needed */
738 master_data |= (control << 4);
739 pci_read_config_byte(dev, slave_port, &slave_data);
740 slave_data &= (ap->port_no ? 0x0f : 0xf0);
741 /* Load the timing nibble for this slave */
742 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
744 /* Master keeps the bits in a different format */
745 master_data &= 0xccf8;
746 /* Enable PPE, IE and TIME as appropriate */
747 master_data |= control;
749 (timings[pio][0] << 12) |
750 (timings[pio][1] << 8);
752 pci_write_config_word(dev, master_port, master_data);
754 pci_write_config_byte(dev, slave_port, slave_data);
756 /* Ensure the UDMA bit is off - it will be turned back on if
760 pci_read_config_byte(dev, 0x48, &udma_enable);
761 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
762 pci_write_config_byte(dev, 0x48, udma_enable);
767 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
768 * @ap: Port whose timings we are configuring
769 * @adev: Drive in question
770 * @udma: udma mode, 0 - 6
771 * @isich: set if the chip is an ICH device
773 * Set UDMA mode for device, in host controller PCI config space.
776 * None (inherited from caller).
779 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
781 struct pci_dev *dev = to_pci_dev(ap->host->dev);
782 u8 master_port = ap->port_no ? 0x42 : 0x40;
784 u8 speed = adev->dma_mode;
785 int devid = adev->devno + 2 * ap->port_no;
788 static const /* ISP RTC */
789 u8 timings[][2] = { { 0, 0 },
795 pci_read_config_word(dev, master_port, &master_data);
796 pci_read_config_byte(dev, 0x48, &udma_enable);
798 if (speed >= XFER_UDMA_0) {
799 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
802 int u_clock, u_speed;
805 * UDMA is handled by a combination of clock switching and
806 * selection of dividers
808 * Handy rule: Odd modes are UDMATIMx 01, even are 02
809 * except UDMA0 which is 00
811 u_speed = min(2 - (udma & 1), udma);
813 u_clock = 0x1000; /* 100Mhz */
815 u_clock = 1; /* 66Mhz */
817 u_clock = 0; /* 33Mhz */
819 udma_enable |= (1 << devid);
821 /* Load the CT/RP selection */
822 pci_read_config_word(dev, 0x4A, &udma_timing);
823 udma_timing &= ~(3 << (4 * devid));
824 udma_timing |= u_speed << (4 * devid);
825 pci_write_config_word(dev, 0x4A, udma_timing);
828 /* Select a 33/66/100Mhz clock */
829 pci_read_config_word(dev, 0x54, &ideconf);
830 ideconf &= ~(0x1001 << devid);
831 ideconf |= u_clock << devid;
832 /* For ICH or later we should set bit 10 for better
833 performance (WR_PingPong_En) */
834 pci_write_config_word(dev, 0x54, ideconf);
838 * MWDMA is driven by the PIO timings. We must also enable
839 * IORDY unconditionally along with TIME1. PPE has already
840 * been set when the PIO timing was set.
842 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
843 unsigned int control;
845 const unsigned int needed_pio[3] = {
846 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
848 int pio = needed_pio[mwdma] - XFER_PIO_0;
850 control = 3; /* IORDY|TIME1 */
852 /* If the drive MWDMA is faster than it can do PIO then
853 we must force PIO into PIO0 */
855 if (adev->pio_mode < needed_pio[mwdma])
856 /* Enable DMA timing only */
857 control |= 8; /* PIO cycles in PIO0 */
859 if (adev->devno) { /* Slave */
860 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
861 master_data |= control << 4;
862 pci_read_config_byte(dev, 0x44, &slave_data);
863 slave_data &= (0x0F + 0xE1 * ap->port_no);
864 /* Load the matching timing */
865 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
866 pci_write_config_byte(dev, 0x44, slave_data);
867 } else { /* Master */
868 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
869 and master timing bits */
870 master_data |= control;
872 (timings[pio][0] << 12) |
873 (timings[pio][1] << 8);
875 udma_enable &= ~(1 << devid);
876 pci_write_config_word(dev, master_port, master_data);
878 /* Don't scribble on 0x48 if the controller does not support UDMA */
880 pci_write_config_byte(dev, 0x48, udma_enable);
884 * piix_set_dmamode - Initialize host controller PATA DMA timings
885 * @ap: Port whose timings we are configuring
888 * Set MW/UDMA mode for device, in host controller PCI config space.
891 * None (inherited from caller).
894 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
896 do_pata_set_dmamode(ap, adev, 0);
900 * ich_set_dmamode - Initialize host controller PATA DMA timings
901 * @ap: Port whose timings we are configuring
904 * Set MW/UDMA mode for device, in host controller PCI config space.
907 * None (inherited from caller).
910 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
912 do_pata_set_dmamode(ap, adev, 1);
915 #define AHCI_PCI_BAR 5
916 #define AHCI_GLOBAL_CTL 0x04
917 #define AHCI_ENABLE (1 << 31)
918 static int piix_disable_ahci(struct pci_dev *pdev)
924 /* BUG: pci_enable_device has not yet been called. This
925 * works because this device is usually set up by BIOS.
928 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
929 !pci_resource_len(pdev, AHCI_PCI_BAR))
932 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
936 tmp = readl(mmio + AHCI_GLOBAL_CTL);
937 if (tmp & AHCI_ENABLE) {
939 writel(tmp, mmio + AHCI_GLOBAL_CTL);
941 tmp = readl(mmio + AHCI_GLOBAL_CTL);
942 if (tmp & AHCI_ENABLE)
946 pci_iounmap(pdev, mmio);
951 * piix_check_450nx_errata - Check for problem 450NX setup
952 * @ata_dev: the PCI device to check
954 * Check for the present of 450NX errata #19 and errata #25. If
955 * they are found return an error code so we can turn off DMA
958 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
960 struct pci_dev *pdev = NULL;
965 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
967 /* Look for 450NX PXB. Check for problem configurations
968 A PCI quirk checks bit 6 already */
969 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
970 pci_read_config_word(pdev, 0x41, &cfg);
971 /* Only on the original revision: IDE DMA can hang */
974 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
975 else if (cfg & (1<<14) && rev < 5)
979 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
980 if (no_piix_dma == 2)
981 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
985 static void __devinit piix_init_pcs(struct pci_dev *pdev,
986 struct ata_port_info *pinfo,
987 const struct piix_map_db *map_db)
991 pci_read_config_word(pdev, ICH5_PCS, &pcs);
993 new_pcs = pcs | map_db->port_enable;
995 if (new_pcs != pcs) {
996 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
997 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1002 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1003 struct ata_port_info *pinfo,
1004 const struct piix_map_db *map_db)
1006 struct piix_host_priv *hpriv = pinfo[0].private_data;
1007 const unsigned int *map;
1008 int i, invalid_map = 0;
1011 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1013 map = map_db->map[map_value & map_db->mask];
1015 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1016 for (i = 0; i < 4; i++) {
1028 WARN_ON((i & 1) || map[i + 1] != IDE);
1029 pinfo[i / 2] = piix_port_info[ich_pata_100];
1030 pinfo[i / 2].private_data = hpriv;
1036 printk(" P%d", map[i]);
1038 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1045 dev_printk(KERN_ERR, &pdev->dev,
1046 "invalid MAP value %u\n", map_value);
1049 hpriv->map_db = map_db;
1053 * piix_init_one - Register PIIX ATA PCI device with kernel services
1054 * @pdev: PCI device to register
1055 * @ent: Entry in piix_pci_tbl matching with @pdev
1057 * Called from kernel PCI layer. We probe for combined mode (sigh),
1058 * and then hand over control to libata, for it to do the rest.
1061 * Inherited from PCI layer (may sleep).
1064 * Zero on success, or -ERRNO value.
1067 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1069 static int printed_version;
1070 struct ata_port_info port_info[2];
1071 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
1072 struct piix_host_priv *hpriv;
1073 unsigned long port_flags;
1075 if (!printed_version++)
1076 dev_printk(KERN_DEBUG, &pdev->dev,
1077 "version " DRV_VERSION "\n");
1079 /* no hotplugging support (FIXME) */
1080 if (!in_module_init)
1083 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1087 port_info[0] = piix_port_info[ent->driver_data];
1088 port_info[1] = piix_port_info[ent->driver_data];
1089 port_info[0].private_data = hpriv;
1090 port_info[1].private_data = hpriv;
1092 port_flags = port_info[0].flags;
1094 if (port_flags & PIIX_FLAG_AHCI) {
1096 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1097 if (tmp == PIIX_AHCI_DEVICE) {
1098 int rc = piix_disable_ahci(pdev);
1104 /* Initialize SATA map */
1105 if (port_flags & ATA_FLAG_SATA) {
1106 piix_init_sata_map(pdev, port_info,
1107 piix_map_db_table[ent->driver_data]);
1108 piix_init_pcs(pdev, port_info,
1109 piix_map_db_table[ent->driver_data]);
1112 /* On ICH5, some BIOSen disable the interrupt using the
1113 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1114 * On ICH6, this bit has the same effect, but only when
1115 * MSI is disabled (and it is disabled, as we don't use
1116 * message-signalled interrupts currently).
1118 if (port_flags & PIIX_FLAG_CHECKINTR)
1121 if (piix_check_450nx_errata(pdev)) {
1122 /* This writes into the master table but it does not
1123 really matter for this errata as we will apply it to
1124 all the PIIX devices on the board */
1125 port_info[0].mwdma_mask = 0;
1126 port_info[0].udma_mask = 0;
1127 port_info[1].mwdma_mask = 0;
1128 port_info[1].udma_mask = 0;
1130 return ata_pci_init_one(pdev, ppinfo, 2);
1133 static void piix_host_stop(struct ata_host *host)
1135 struct piix_host_priv *hpriv = host->private_data;
1137 ata_host_stop(host);
1142 static int __init piix_init(void)
1146 DPRINTK("pci_register_driver\n");
1147 rc = pci_register_driver(&piix_pci_driver);
1157 static void __exit piix_exit(void)
1159 pci_unregister_driver(&piix_pci_driver);
1162 module_init(piix_init);
1163 module_exit(piix_exit);