drivers/base/regmap/regmap-irq.c

   1 /*
   2  * regmap based irq_chip
   3  *
   4  * Copyright 2011 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/export.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/slab.h>
  21
  22 #include "internal.h"
  23
  24 struct regmap_irq_chip_data {
  25         struct mutex lock;
  26         struct irq_chip irq_chip;
  27
  28         struct regmap *map;
  29         const struct regmap_irq_chip *chip;
  30
  31         int irq_base;
  32         struct irq_domain *domain;
  33
  34         int irq;
  35         int wake_count;
  36
  37         void *status_reg_buf;
  38         unsigned int *status_buf;
  39         unsigned int *mask_buf;
  40         unsigned int *mask_buf_def;
  41         unsigned int *wake_buf;
  42         unsigned int *type_buf;
  43         unsigned int *type_buf_def;
  44
  45         unsigned int irq_reg_stride;
  46         unsigned int type_reg_stride;
  47 };
  48
  49 static inline const
  50 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  51                                      int irq)
  52 {
  53         return &data->chip->irqs[irq];
  54 }
  55
  56 static void regmap_irq_lock(struct irq_data *data)
  57 {
  58         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  59
  60         mutex_lock(&d->lock);
  61 }
  62
  63 static void regmap_irq_sync_unlock(struct irq_data *data)
  64 {
  65         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  66         struct regmap *map = d->map;
  67         int i, ret;
  68         u32 reg;
  69         u32 unmask_offset;
  70
  71         if (d->chip->runtime_pm) {
  72                 ret = pm_runtime_get_sync(map->dev);
  73                 if (ret < 0)
  74                         dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  75                                 ret);
  76         }
  77
  78         /*
  79          * If there's been a change in the mask write it back to the
  80          * hardware.  We rely on the use of the regmap core cache to
  81          * suppress pointless writes.
  82          */
  83         for (i = 0; i < d->chip->num_regs; i++) {
  84                 reg = d->chip->mask_base +
  85                         (i * map->reg_stride * d->irq_reg_stride);
  86                 if (d->chip->mask_invert) {
  87                         ret = regmap_update_bits(d->map, reg,
  88                                          d->mask_buf_def[i], ~d->mask_buf[i]);
  89                 } else if (d->chip->unmask_base) {
  90                         /* set mask with mask_base register */
  91                         ret = regmap_update_bits(d->map, reg,
  92                                         d->mask_buf_def[i], ~d->mask_buf[i]);
  93                         if (ret < 0)
  94                                 dev_err(d->map->dev,
  95                                         "Failed to sync unmasks in %x\n",
  96                                         reg);
  97                         unmask_offset = d->chip->unmask_base -
  98                                                         d->chip->mask_base;
  99                         /* clear mask with unmask_base register */
 100                         ret = regmap_update_bits(d->map,
 101                                         reg + unmask_offset,
 102                                         d->mask_buf_def[i],
 103                                         d->mask_buf[i]);
 104                 } else {
 105                         ret = regmap_update_bits(d->map, reg,
 106                                          d->mask_buf_def[i], d->mask_buf[i]);
 107                 }
 108                 if (ret != 0)
 109                         dev_err(d->map->dev, "Failed to sync masks in %x\n",
 110                                 reg);
 111
 112                 reg = d->chip->wake_base +
 113                         (i * map->reg_stride * d->irq_reg_stride);
 114                 if (d->wake_buf) {
 115                         if (d->chip->wake_invert)
 116                                 ret = regmap_update_bits(d->map, reg,
 117                                                          d->mask_buf_def[i],
 118                                                          ~d->wake_buf[i]);
 119                         else
 120                                 ret = regmap_update_bits(d->map, reg,
 121                                                          d->mask_buf_def[i],
 122                                                          d->wake_buf[i]);
 123                         if (ret != 0)
 124                                 dev_err(d->map->dev,
 125                                         "Failed to sync wakes in %x: %d\n",
 126                                         reg, ret);
 127                 }
 128
 129                 if (!d->chip->init_ack_masked)
 130                         continue;
 131                 /*
 132                  * Ack all the masked interrupts unconditionally,
 133                  * OR if there is masked interrupt which hasn't been Acked,
 134                  * it'll be ignored in irq handler, then may introduce irq storm
 135                  */
 136                 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 137                         reg = d->chip->ack_base +
 138                                 (i * map->reg_stride * d->irq_reg_stride);
 139                         /* some chips ack by write 0 */
 140                         if (d->chip->ack_invert)
 141                                 ret = regmap_write(map, reg, ~d->mask_buf[i]);
 142                         else
 143                                 ret = regmap_write(map, reg, d->mask_buf[i]);
 144                         if (ret != 0)
 145                                 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 146                                         reg, ret);
 147                 }
 148         }
 149
 150         for (i = 0; i < d->chip->num_type_reg; i++) {
 151                 if (!d->type_buf_def[i])
 152                         continue;
 153                 reg = d->chip->type_base +
 154                         (i * map->reg_stride * d->type_reg_stride);
 155                 if (d->chip->type_invert)
 156                         ret = regmap_update_bits(d->map, reg,
 157                                 d->type_buf_def[i], ~d->type_buf[i]);
 158                 else
 159                         ret = regmap_update_bits(d->map, reg,
 160                                 d->type_buf_def[i], d->type_buf[i]);
 161                 if (ret != 0)
 162                         dev_err(d->map->dev, "Failed to sync type in %x\n",
 163                                 reg);
 164         }
 165
 166         if (d->chip->runtime_pm)
 167                 pm_runtime_put(map->dev);
 168
 169         /* If we've changed our wakeup count propagate it to the parent */
 170         if (d->wake_count < 0)
 171                 for (i = d->wake_count; i < 0; i++)
 172                         irq_set_irq_wake(d->irq, 0);
 173         else if (d->wake_count > 0)
 174                 for (i = 0; i < d->wake_count; i++)
 175                         irq_set_irq_wake(d->irq, 1);
 176
 177         d->wake_count = 0;
 178
 179         mutex_unlock(&d->lock);
 180 }
 181
 182 static void regmap_irq_enable(struct irq_data *data)
 183 {
 184         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 185         struct regmap *map = d->map;
 186         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 187
 188         d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
 189 }
 190
 191 static void regmap_irq_disable(struct irq_data *data)
 192 {
 193         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 194         struct regmap *map = d->map;
 195         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 196
 197         d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 198 }
 199
 200 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 201 {
 202         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 203         struct regmap *map = d->map;
 204         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 205         int reg = irq_data->type_reg_offset / map->reg_stride;
 206
 207         if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
 208                 return 0;
 209
 210         d->type_buf[reg] &= ~(irq_data->type_falling_mask |
 211                                         irq_data->type_rising_mask);
 212         switch (type) {
 213         case IRQ_TYPE_EDGE_FALLING:
 214                 d->type_buf[reg] |= irq_data->type_falling_mask;
 215                 break;
 216
 217         case IRQ_TYPE_EDGE_RISING:
 218                 d->type_buf[reg] |= irq_data->type_rising_mask;
 219                 break;
 220
 221         case IRQ_TYPE_EDGE_BOTH:
 222                 d->type_buf[reg] |= (irq_data->type_falling_mask |
 223                                         irq_data->type_rising_mask);
 224                 break;
 225
 226         default:
 227                 return -EINVAL;
 228         }
 229         return 0;
 230 }
 231
 232 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 233 {
 234         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 235         struct regmap *map = d->map;
 236         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 237
 238         if (on) {
 239                 if (d->wake_buf)
 240                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 241                                 &= ~irq_data->mask;
 242                 d->wake_count++;
 243         } else {
 244                 if (d->wake_buf)
 245                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 246                                 |= irq_data->mask;
 247                 d->wake_count--;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static const struct irq_chip regmap_irq_chip = {
 254         .irq_bus_lock           = regmap_irq_lock,
 255         .irq_bus_sync_unlock    = regmap_irq_sync_unlock,
 256         .irq_disable            = regmap_irq_disable,
 257         .irq_enable             = regmap_irq_enable,
 258         .irq_set_type           = regmap_irq_set_type,
 259         .irq_set_wake           = regmap_irq_set_wake,
 260 };
 261
 262 static irqreturn_t regmap_irq_thread(int irq, void *d)
 263 {
 264         struct regmap_irq_chip_data *data = d;
 265         const struct regmap_irq_chip *chip = data->chip;
 266         struct regmap *map = data->map;
 267         int ret, i;
 268         bool handled = false;
 269         u32 reg;
 270
 271         if (chip->runtime_pm) {
 272                 ret = pm_runtime_get_sync(map->dev);
 273                 if (ret < 0) {
 274                         dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 275                                 ret);
 276                         pm_runtime_put(map->dev);
 277                         return IRQ_NONE;
 278                 }
 279         }
 280
 281         /*
 282          * Read in the statuses, using a single bulk read if possible
 283          * in order to reduce the I/O overheads.
 284          */
 285         if (!map->use_single_read && map->reg_stride == 1 &&
 286             data->irq_reg_stride == 1) {
 287                 u8 *buf8 = data->status_reg_buf;
 288                 u16 *buf16 = data->status_reg_buf;
 289                 u32 *buf32 = data->status_reg_buf;
 290
 291                 BUG_ON(!data->status_reg_buf);
 292
 293                 ret = regmap_bulk_read(map, chip->status_base,
 294                                        data->status_reg_buf,
 295                                        chip->num_regs);
 296                 if (ret != 0) {
 297                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 298                                 ret);
 299                         return IRQ_NONE;
 300                 }
 301
 302                 for (i = 0; i < data->chip->num_regs; i++) {
 303                         switch (map->format.val_bytes) {
 304                         case 1:
 305                                 data->status_buf[i] = buf8[i];
 306                                 break;
 307                         case 2:
 308                                 data->status_buf[i] = buf16[i];
 309                                 break;
 310                         case 4:
 311                                 data->status_buf[i] = buf32[i];
 312                                 break;
 313                         default:
 314                                 BUG();
 315                                 return IRQ_NONE;
 316                         }
 317                 }
 318
 319         } else {
 320                 for (i = 0; i < data->chip->num_regs; i++) {
 321                         ret = regmap_read(map, chip->status_base +
 322                                           (i * map->reg_stride
 323                                            * data->irq_reg_stride),
 324                                           &data->status_buf[i]);
 325
 326                         if (ret != 0) {
 327                                 dev_err(map->dev,
 328                                         "Failed to read IRQ status: %d\n",
 329                                         ret);
 330                                 if (chip->runtime_pm)
 331                                         pm_runtime_put(map->dev);
 332                                 return IRQ_NONE;
 333                         }
 334                 }
 335         }
 336
 337         /*
 338          * Ignore masked IRQs and ack if we need to; we ack early so
 339          * there is no race between handling and acknowleding the
 340          * interrupt.  We assume that typically few of the interrupts
 341          * will fire simultaneously so don't worry about overhead from
 342          * doing a write per register.
 343          */
 344         for (i = 0; i < data->chip->num_regs; i++) {
 345                 data->status_buf[i] &= ~data->mask_buf[i];
 346
 347                 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 348                         reg = chip->ack_base +
 349                                 (i * map->reg_stride * data->irq_reg_stride);
 350                         ret = regmap_write(map, reg, data->status_buf[i]);
 351                         if (ret != 0)
 352                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 353                                         reg, ret);
 354                 }
 355         }
 356
 357         for (i = 0; i < chip->num_irqs; i++) {
 358                 if (data->status_buf[chip->irqs[i].reg_offset /
 359                                      map->reg_stride] & chip->irqs[i].mask) {
 360                         handle_nested_irq(irq_find_mapping(data->domain, i));
 361                         handled = true;
 362                 }
 363         }
 364
 365         if (chip->runtime_pm)
 366                 pm_runtime_put(map->dev);
 367
 368         if (handled)
 369                 return IRQ_HANDLED;
 370         else
 371                 return IRQ_NONE;
 372 }
 373
 374 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 375                           irq_hw_number_t hw)
 376 {
 377         struct regmap_irq_chip_data *data = h->host_data;
 378
 379         irq_set_chip_data(virq, data);
 380         irq_set_chip(virq, &data->irq_chip);
 381         irq_set_nested_thread(virq, 1);
 382         irq_set_noprobe(virq);
 383
 384         return 0;
 385 }
 386
 387 static const struct irq_domain_ops regmap_domain_ops = {
 388         .map    = regmap_irq_map,
 389         .xlate  = irq_domain_xlate_twocell,
 390 };
 391
 392 /**
 393  * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
 394  *
 395  * map:       The regmap for the device.
 396  * irq:       The IRQ the device uses to signal interrupts
 397  * irq_flags: The IRQF_ flags to use for the primary interrupt.
 398  * chip:      Configuration for the interrupt controller.
 399  * data:      Runtime data structure for the controller, allocated on success
 400  *
 401  * Returns 0 on success or an errno on failure.
 402  *
 403  * In order for this to be efficient the chip really should use a
 404  * register cache.  The chip driver is responsible for restoring the
 405  * register values used by the IRQ controller over suspend and resume.
 406  */
 407 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 408                         int irq_base, const struct regmap_irq_chip *chip,
 409                         struct regmap_irq_chip_data **data)
 410 {
 411         struct regmap_irq_chip_data *d;
 412         int i;
 413         int ret = -ENOMEM;
 414         u32 reg;
 415         u32 unmask_offset;
 416
 417         if (chip->num_regs <= 0)
 418                 return -EINVAL;
 419
 420         for (i = 0; i < chip->num_irqs; i++) {
 421                 if (chip->irqs[i].reg_offset % map->reg_stride)
 422                         return -EINVAL;
 423                 if (chip->irqs[i].reg_offset / map->reg_stride >=
 424                     chip->num_regs)
 425                         return -EINVAL;
 426         }
 427
 428         if (irq_base) {
 429                 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 430                 if (irq_base < 0) {
 431                         dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 432                                  irq_base);
 433                         return irq_base;
 434                 }
 435         }
 436
 437         d = kzalloc(sizeof(*d), GFP_KERNEL);
 438         if (!d)
 439                 return -ENOMEM;
 440
 441         d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 442                                 GFP_KERNEL);
 443         if (!d->status_buf)
 444                 goto err_alloc;
 445
 446         d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 447                               GFP_KERNEL);
 448         if (!d->mask_buf)
 449                 goto err_alloc;
 450
 451         d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
 452                                   GFP_KERNEL);
 453         if (!d->mask_buf_def)
 454                 goto err_alloc;
 455
 456         if (chip->wake_base) {
 457                 d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 458                                       GFP_KERNEL);
 459                 if (!d->wake_buf)
 460                         goto err_alloc;
 461         }
 462
 463         if (chip->num_type_reg) {
 464                 d->type_buf_def = kcalloc(chip->num_type_reg,
 465                                         sizeof(unsigned int), GFP_KERNEL);
 466                 if (!d->type_buf_def)
 467                         goto err_alloc;
 468
 469                 d->type_buf = kcalloc(chip->num_type_reg, sizeof(unsigned int),
 470                                       GFP_KERNEL);
 471                 if (!d->type_buf)
 472                         goto err_alloc;
 473         }
 474
 475         d->irq_chip = regmap_irq_chip;
 476         d->irq_chip.name = chip->name;
 477         d->irq = irq;
 478         d->map = map;
 479         d->chip = chip;
 480         d->irq_base = irq_base;
 481
 482         if (chip->irq_reg_stride)
 483                 d->irq_reg_stride = chip->irq_reg_stride;
 484         else
 485                 d->irq_reg_stride = 1;
 486
 487         if (chip->type_reg_stride)
 488                 d->type_reg_stride = chip->type_reg_stride;
 489         else
 490                 d->type_reg_stride = 1;
 491
 492         if (!map->use_single_read && map->reg_stride == 1 &&
 493             d->irq_reg_stride == 1) {
 494                 d->status_reg_buf = kmalloc_array(chip->num_regs,
 495                                                   map->format.val_bytes,
 496                                                   GFP_KERNEL);
 497                 if (!d->status_reg_buf)
 498                         goto err_alloc;
 499         }
 500
 501         mutex_init(&d->lock);
 502
 503         for (i = 0; i < chip->num_irqs; i++)
 504                 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 505                         |= chip->irqs[i].mask;
 506
 507         /* Mask all the interrupts by default */
 508         for (i = 0; i < chip->num_regs; i++) {
 509                 d->mask_buf[i] = d->mask_buf_def[i];
 510                 reg = chip->mask_base +
 511                         (i * map->reg_stride * d->irq_reg_stride);
 512                 if (chip->mask_invert)
 513                         ret = regmap_update_bits(map, reg,
 514                                          d->mask_buf[i], ~d->mask_buf[i]);
 515                 else if (d->chip->unmask_base) {
 516                         unmask_offset = d->chip->unmask_base -
 517                                         d->chip->mask_base;
 518                         ret = regmap_update_bits(d->map,
 519                                         reg + unmask_offset,
 520                                         d->mask_buf[i],
 521                                         d->mask_buf[i]);
 522                 } else
 523                         ret = regmap_update_bits(map, reg,
 524                                          d->mask_buf[i], d->mask_buf[i]);
 525                 if (ret != 0) {
 526                         dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 527                                 reg, ret);
 528                         goto err_alloc;
 529                 }
 530
 531                 if (!chip->init_ack_masked)
 532                         continue;
 533
 534                 /* Ack masked but set interrupts */
 535                 reg = chip->status_base +
 536                         (i * map->reg_stride * d->irq_reg_stride);
 537                 ret = regmap_read(map, reg, &d->status_buf[i]);
 538                 if (ret != 0) {
 539                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 540                                 ret);
 541                         goto err_alloc;
 542                 }
 543
 544                 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 545                         reg = chip->ack_base +
 546                                 (i * map->reg_stride * d->irq_reg_stride);
 547                         if (chip->ack_invert)
 548                                 ret = regmap_write(map, reg,
 549                                         ~(d->status_buf[i] & d->mask_buf[i]));
 550                         else
 551                                 ret = regmap_write(map, reg,
 552                                         d->status_buf[i] & d->mask_buf[i]);
 553                         if (ret != 0) {
 554                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 555                                         reg, ret);
 556                                 goto err_alloc;
 557                         }
 558                 }
 559         }
 560
 561         /* Wake is disabled by default */
 562         if (d->wake_buf) {
 563                 for (i = 0; i < chip->num_regs; i++) {
 564                         d->wake_buf[i] = d->mask_buf_def[i];
 565                         reg = chip->wake_base +
 566                                 (i * map->reg_stride * d->irq_reg_stride);
 567
 568                         if (chip->wake_invert)
 569                                 ret = regmap_update_bits(map, reg,
 570                                                          d->mask_buf_def[i],
 571                                                          0);
 572                         else
 573                                 ret = regmap_update_bits(map, reg,
 574                                                          d->mask_buf_def[i],
 575                                                          d->wake_buf[i]);
 576                         if (ret != 0) {
 577                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 578                                         reg, ret);
 579                                 goto err_alloc;
 580                         }
 581                 }
 582         }
 583
 584         if (chip->num_type_reg) {
 585                 for (i = 0; i < chip->num_irqs; i++) {
 586                         reg = chip->irqs[i].type_reg_offset / map->reg_stride;
 587                         d->type_buf_def[reg] |= chip->irqs[i].type_rising_mask |
 588                                         chip->irqs[i].type_falling_mask;
 589                 }
 590                 for (i = 0; i < chip->num_type_reg; ++i) {
 591                         if (!d->type_buf_def[i])
 592                                 continue;
 593
 594                         reg = chip->type_base +
 595                                 (i * map->reg_stride * d->type_reg_stride);
 596                         if (chip->type_invert)
 597                                 ret = regmap_update_bits(map, reg,
 598                                         d->type_buf_def[i], 0xFF);
 599                         else
 600                                 ret = regmap_update_bits(map, reg,
 601                                         d->type_buf_def[i], 0x0);
 602                         if (ret != 0) {
 603                                 dev_err(map->dev,
 604                                         "Failed to set type in 0x%x: %x\n",
 605                                         reg, ret);
 606                                 goto err_alloc;
 607                         }
 608                 }
 609         }
 610
 611         if (irq_base)
 612                 d->domain = irq_domain_add_legacy(map->dev->of_node,
 613                                                   chip->num_irqs, irq_base, 0,
 614                                                   &regmap_domain_ops, d);
 615         else
 616                 d->domain = irq_domain_add_linear(map->dev->of_node,
 617                                                   chip->num_irqs,
 618                                                   &regmap_domain_ops, d);
 619         if (!d->domain) {
 620                 dev_err(map->dev, "Failed to create IRQ domain\n");
 621                 ret = -ENOMEM;
 622                 goto err_alloc;
 623         }
 624
 625         ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 626                                    irq_flags | IRQF_ONESHOT,
 627                                    chip->name, d);
 628         if (ret != 0) {
 629                 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 630                         irq, chip->name, ret);
 631                 goto err_domain;
 632         }
 633
 634         *data = d;
 635
 636         return 0;
 637
 638 err_domain:
 639         /* Should really dispose of the domain but... */
 640 err_alloc:
 641         kfree(d->type_buf);
 642         kfree(d->type_buf_def);
 643         kfree(d->wake_buf);
 644         kfree(d->mask_buf_def);
 645         kfree(d->mask_buf);
 646         kfree(d->status_buf);
 647         kfree(d->status_reg_buf);
 648         kfree(d);
 649         return ret;
 650 }
 651 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 652
 653 /**
 654  * regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
 655  *
 656  * @irq: Primary IRQ for the device
 657  * @d:   regmap_irq_chip_data allocated by regmap_add_irq_chip()
 658  */
 659 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 660 {
 661         if (!d)
 662                 return;
 663
 664         free_irq(irq, d);
 665         irq_domain_remove(d->domain);
 666         kfree(d->type_buf);
 667         kfree(d->type_buf_def);
 668         kfree(d->wake_buf);
 669         kfree(d->mask_buf_def);
 670         kfree(d->mask_buf);
 671         kfree(d->status_reg_buf);
 672         kfree(d->status_buf);
 673         kfree(d);
 674 }
 675 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 676
 677 /**
 678  * regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
 679  *
 680  * Useful for drivers to request their own IRQs.
 681  *
 682  * @data: regmap_irq controller to operate on.
 683  */
 684 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
 685 {
 686         WARN_ON(!data->irq_base);
 687         return data->irq_base;
 688 }
 689 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
 690
 691 /**
 692  * regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
 693  *
 694  * Useful for drivers to request their own IRQs.
 695  *
 696  * @data: regmap_irq controller to operate on.
 697  * @irq: index of the interrupt requested in the chip IRQs
 698  */
 699 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
 700 {
 701         /* Handle holes in the IRQ list */
 702         if (!data->chip->irqs[irq].mask)
 703                 return -EINVAL;
 704
 705         return irq_create_mapping(data->domain, irq);
 706 }
 707 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
 708
 709 /**
 710  * regmap_irq_get_domain(): Retrieve the irq_domain for the chip
 711  *
 712  * Useful for drivers to request their own IRQs and for integration
 713  * with subsystems.  For ease of integration NULL is accepted as a
 714  * domain, allowing devices to just call this even if no domain is
 715  * allocated.
 716  *
 717  * @data: regmap_irq controller to operate on.
 718  */
 719 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
 720 {
 721         if (data)
 722                 return data->domain;
 723         else
 724                 return NULL;
 725 }
 726 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);