drivers/bus/arm-ccn.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * Copyright (C) 2014 ARM Limited
  12  */
  13
  14 #include <linux/ctype.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/idr.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/perf_event.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define CCN_NUM_XP_PORTS 2
  25 #define CCN_NUM_VCS 4
  26 #define CCN_NUM_REGIONS 256
  27 #define CCN_REGION_SIZE 0x10000
  28
  29 #define CCN_ALL_OLY_ID                  0xff00
  30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT                   0
  31 #define CCN_ALL_OLY_ID__OLY_ID__MASK                    0x1f
  32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT                  8
  33 #define CCN_ALL_OLY_ID__NODE_ID__MASK                   0x3f
  34
  35 #define CCN_MN_ERRINT_STATUS            0x0008
  36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT           0x11
  37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE        0x02
  38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED      0x20
  39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE       0x22
  40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE   0x04
  41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
  42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE  0x44
  43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE        0x08
  44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED      0x80
  45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE       0x88
  46 #define CCN_MN_OLY_COMP_LIST_63_0       0x01e0
  47 #define CCN_MN_ERR_SIG_VAL_63_0         0x0300
  48 #define CCN_MN_ERR_SIG_VAL_63_0__DT                     (1 << 1)
  49
  50 #define CCN_DT_ACTIVE_DSM               0x0000
  51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n)             ((n) * 8)
  52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK                 0xff
  53 #define CCN_DT_CTL                      0x0028
  54 #define CCN_DT_CTL__DT_EN                               (1 << 0)
  55 #define CCN_DT_PMEVCNT(n)               (0x0100 + (n) * 0x8)
  56 #define CCN_DT_PMCCNTR                  0x0140
  57 #define CCN_DT_PMCCNTRSR                0x0190
  58 #define CCN_DT_PMOVSR                   0x0198
  59 #define CCN_DT_PMOVSR_CLR               0x01a0
  60 #define CCN_DT_PMOVSR_CLR__MASK                         0x1f
  61 #define CCN_DT_PMCR                     0x01a8
  62 #define CCN_DT_PMCR__OVFL_INTR_EN                       (1 << 6)
  63 #define CCN_DT_PMCR__PMU_EN                             (1 << 0)
  64 #define CCN_DT_PMSR                     0x01b0
  65 #define CCN_DT_PMSR_REQ                 0x01b8
  66 #define CCN_DT_PMSR_CLR                 0x01c0
  67
  68 #define CCN_HNF_PMU_EVENT_SEL           0x0600
  69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n)             ((n) * 4)
  70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK                 0xf
  71
  72 #define CCN_XP_DT_CONFIG                0x0300
  73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n)              ((n) * 4)
  74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK                  0xf
  75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH          0x0
  76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1     0x1
  77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n)         (0x2 + (n))
  78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n)       (0x4 + (n))
  79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
  80 #define CCN_XP_DT_INTERFACE_SEL         0x0308
  81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n)    (0 + (n) * 8)
  82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK        0x1
  83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n)   (1 + (n) * 8)
  84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK       0x1
  85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n)    (2 + (n) * 8)
  86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK        0x3
  87 #define CCN_XP_DT_CMP_VAL_L(n)          (0x0310 + (n) * 0x40)
  88 #define CCN_XP_DT_CMP_VAL_H(n)          (0x0318 + (n) * 0x40)
  89 #define CCN_XP_DT_CMP_MASK_L(n)         (0x0320 + (n) * 0x40)
  90 #define CCN_XP_DT_CMP_MASK_H(n)         (0x0328 + (n) * 0x40)
  91 #define CCN_XP_DT_CONTROL               0x0370
  92 #define CCN_XP_DT_CONTROL__DT_ENABLE                    (1 << 0)
  93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n)         (12 + (n) * 4)
  94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK             0xf
  95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS           0xf
  96 #define CCN_XP_PMU_EVENT_SEL            0x0600
  97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n)              ((n) * 7)
  98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK                  0x3f
  99
 100 #define CCN_SBAS_PMU_EVENT_SEL          0x0600
 101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n)            ((n) * 4)
 102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK                0xf
 103
 104 #define CCN_RNI_PMU_EVENT_SEL           0x0600
 105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n)             ((n) * 4)
 106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK                 0xf
 107
 108 #define CCN_TYPE_MN     0x01
 109 #define CCN_TYPE_DT     0x02
 110 #define CCN_TYPE_HNF    0x04
 111 #define CCN_TYPE_HNI    0x05
 112 #define CCN_TYPE_XP     0x08
 113 #define CCN_TYPE_SBSX   0x0c
 114 #define CCN_TYPE_SBAS   0x10
 115 #define CCN_TYPE_RNI_1P 0x14
 116 #define CCN_TYPE_RNI_2P 0x15
 117 #define CCN_TYPE_RNI_3P 0x16
 118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
 119 #define CCN_TYPE_RND_2P 0x19
 120 #define CCN_TYPE_RND_3P 0x1a
 121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
 122
 123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
 124
 125 #define CCN_NUM_PMU_EVENTS              4
 126 #define CCN_NUM_XP_WATCHPOINTS          2 /* See DT.dbg_id.num_watchpoints */
 127 #define CCN_NUM_PMU_EVENT_COUNTERS      8 /* See DT.dbg_id.num_pmucntr */
 128 #define CCN_IDX_PMU_CYCLE_COUNTER       CCN_NUM_PMU_EVENT_COUNTERS
 129
 130 #define CCN_NUM_PREDEFINED_MASKS        4
 131 #define CCN_IDX_MASK_ANY                (CCN_NUM_PMU_EVENT_COUNTERS + 0)
 132 #define CCN_IDX_MASK_EXACT              (CCN_NUM_PMU_EVENT_COUNTERS + 1)
 133 #define CCN_IDX_MASK_ORDER              (CCN_NUM_PMU_EVENT_COUNTERS + 2)
 134 #define CCN_IDX_MASK_OPCODE             (CCN_NUM_PMU_EVENT_COUNTERS + 3)
 135
 136 struct arm_ccn_component {
 137         void __iomem *base;
 138         u32 type;
 139
 140         DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
 141         union {
 142                 struct {
 143                         DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
 144                 } xp;
 145         };
 146 };
 147
 148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
 149         struct arm_ccn_dt, pmu), struct arm_ccn, dt)
 150
 151 struct arm_ccn_dt {
 152         int id;
 153         void __iomem *base;
 154
 155         spinlock_t config_lock;
 156
 157         DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
 158         struct {
 159                 struct arm_ccn_component *source;
 160                 struct perf_event *event;
 161         } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
 162
 163         struct {
 164                u64 l, h;
 165         } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
 166
 167         struct hrtimer hrtimer;
 168
 169         cpumask_t cpu;
 170         struct list_head entry;
 171
 172         struct pmu pmu;
 173 };
 174
 175 struct arm_ccn {
 176         struct device *dev;
 177         void __iomem *base;
 178         unsigned int irq;
 179
 180         unsigned sbas_present:1;
 181         unsigned sbsx_present:1;
 182
 183         int num_nodes;
 184         struct arm_ccn_component *node;
 185
 186         int num_xps;
 187         struct arm_ccn_component *xp;
 188
 189         struct arm_ccn_dt dt;
 190         int mn_id;
 191 };
 192
 193 static DEFINE_MUTEX(arm_ccn_mutex);
 194 static LIST_HEAD(arm_ccn_list);
 195
 196 static int arm_ccn_node_to_xp(int node)
 197 {
 198         return node / CCN_NUM_XP_PORTS;
 199 }
 200
 201 static int arm_ccn_node_to_xp_port(int node)
 202 {
 203         return node % CCN_NUM_XP_PORTS;
 204 }
 205
 206
 207 /*
 208  * Bit shifts and masks in these defines must be kept in sync with
 209  * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
 210  */
 211 #define CCN_CONFIG_NODE(_config)        (((_config) >> 0) & 0xff)
 212 #define CCN_CONFIG_XP(_config)          (((_config) >> 0) & 0xff)
 213 #define CCN_CONFIG_TYPE(_config)        (((_config) >> 8) & 0xff)
 214 #define CCN_CONFIG_EVENT(_config)       (((_config) >> 16) & 0xff)
 215 #define CCN_CONFIG_PORT(_config)        (((_config) >> 24) & 0x3)
 216 #define CCN_CONFIG_BUS(_config)         (((_config) >> 24) & 0x3)
 217 #define CCN_CONFIG_VC(_config)          (((_config) >> 26) & 0x7)
 218 #define CCN_CONFIG_DIR(_config)         (((_config) >> 29) & 0x1)
 219 #define CCN_CONFIG_MASK(_config)        (((_config) >> 30) & 0xf)
 220
 221 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
 222 {
 223         *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
 224         *config |= (node_xp << 0) | (type << 8) | (port << 24);
 225 }
 226
 227 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
 228                 struct device_attribute *attr, char *buf)
 229 {
 230         struct dev_ext_attribute *ea = container_of(attr,
 231                         struct dev_ext_attribute, attr);
 232
 233         return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
 234 }
 235
 236 #define CCN_FORMAT_ATTR(_name, _config) \
 237         struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
 238                         { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
 239                         NULL), _config }
 240
 241 static CCN_FORMAT_ATTR(node, "config:0-7");
 242 static CCN_FORMAT_ATTR(xp, "config:0-7");
 243 static CCN_FORMAT_ATTR(type, "config:8-15");
 244 static CCN_FORMAT_ATTR(event, "config:16-23");
 245 static CCN_FORMAT_ATTR(port, "config:24-25");
 246 static CCN_FORMAT_ATTR(bus, "config:24-25");
 247 static CCN_FORMAT_ATTR(vc, "config:26-28");
 248 static CCN_FORMAT_ATTR(dir, "config:29-29");
 249 static CCN_FORMAT_ATTR(mask, "config:30-33");
 250 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
 251 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
 252
 253 static struct attribute *arm_ccn_pmu_format_attrs[] = {
 254         &arm_ccn_pmu_format_attr_node.attr.attr,
 255         &arm_ccn_pmu_format_attr_xp.attr.attr,
 256         &arm_ccn_pmu_format_attr_type.attr.attr,
 257         &arm_ccn_pmu_format_attr_event.attr.attr,
 258         &arm_ccn_pmu_format_attr_port.attr.attr,
 259         &arm_ccn_pmu_format_attr_bus.attr.attr,
 260         &arm_ccn_pmu_format_attr_vc.attr.attr,
 261         &arm_ccn_pmu_format_attr_dir.attr.attr,
 262         &arm_ccn_pmu_format_attr_mask.attr.attr,
 263         &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
 264         &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
 265         NULL
 266 };
 267
 268 static struct attribute_group arm_ccn_pmu_format_attr_group = {
 269         .name = "format",
 270         .attrs = arm_ccn_pmu_format_attrs,
 271 };
 272
 273
 274 struct arm_ccn_pmu_event {
 275         struct device_attribute attr;
 276         u32 type;
 277         u32 event;
 278         int num_ports;
 279         int num_vcs;
 280         const char *def;
 281         int mask;
 282 };
 283
 284 #define CCN_EVENT_ATTR(_name) \
 285         __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
 286
 287 /*
 288  * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
 289  * their ports in XP they are connected to. For the sake of usability they are
 290  * explicitly defined here (and translated into a relevant watchpoint in
 291  * arm_ccn_pmu_event_init()) so the user can easily request them without deep
 292  * knowledge of the flit format.
 293  */
 294
 295 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
 296                 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
 297                 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
 298                 .def = _def, .mask = _mask, }
 299
 300 #define CCN_EVENT_HNI(_name, _def, _mask) { \
 301                 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
 302                 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
 303                 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
 304
 305 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
 306                 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
 307                 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
 308                 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
 309
 310 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
 311                 .type = CCN_TYPE_HNF, .event = _event, }
 312
 313 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
 314                 .type = CCN_TYPE_XP, .event = _event, \
 315                 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
 316
 317 /*
 318  * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
 319  * on configuration. One of them is picked to represent the whole group,
 320  * as they all share the same event types.
 321  */
 322 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
 323                 .type = CCN_TYPE_RNI_3P, .event = _event, }
 324
 325 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
 326                 .type = CCN_TYPE_SBAS, .event = _event, }
 327
 328 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
 329                 .type = CCN_TYPE_CYCLES }
 330
 331
 332 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
 333                 struct device_attribute *attr, char *buf)
 334 {
 335         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 336         struct arm_ccn_pmu_event *event = container_of(attr,
 337                         struct arm_ccn_pmu_event, attr);
 338         ssize_t res;
 339
 340         res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
 341         if (event->event)
 342                 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
 343                                 event->event);
 344         if (event->def)
 345                 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
 346                                 event->def);
 347         if (event->mask)
 348                 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
 349                                 event->mask);
 350
 351         /* Arguments required by an event */
 352         switch (event->type) {
 353         case CCN_TYPE_CYCLES:
 354                 break;
 355         case CCN_TYPE_XP:
 356                 res += snprintf(buf + res, PAGE_SIZE - res,
 357                                 ",xp=?,vc=?");
 358                 if (event->event == CCN_EVENT_WATCHPOINT)
 359                         res += snprintf(buf + res, PAGE_SIZE - res,
 360                                         ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
 361                 else
 362                         res += snprintf(buf + res, PAGE_SIZE - res,
 363                                         ",bus=?");
 364
 365                 break;
 366         case CCN_TYPE_MN:
 367                 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
 368                 break;
 369         default:
 370                 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
 371                 break;
 372         }
 373
 374         res += snprintf(buf + res, PAGE_SIZE - res, "\n");
 375
 376         return res;
 377 }
 378
 379 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
 380                                      struct attribute *attr, int index)
 381 {
 382         struct device *dev = kobj_to_dev(kobj);
 383         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 384         struct device_attribute *dev_attr = container_of(attr,
 385                         struct device_attribute, attr);
 386         struct arm_ccn_pmu_event *event = container_of(dev_attr,
 387                         struct arm_ccn_pmu_event, attr);
 388
 389         if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
 390                 return 0;
 391         if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
 392                 return 0;
 393
 394         return attr->mode;
 395 }
 396
 397 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
 398         CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
 399         CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
 400         CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
 401         CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
 402         CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
 403         CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
 404         CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
 405         CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
 406                         CCN_IDX_MASK_ORDER),
 407         CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
 408         CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
 409         CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
 410         CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
 411         CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
 412                         CCN_IDX_MASK_ORDER),
 413         CCN_EVENT_HNF(cache_miss, 0x1),
 414         CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
 415         CCN_EVENT_HNF(cache_fill, 0x3),
 416         CCN_EVENT_HNF(pocq_retry, 0x4),
 417         CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
 418         CCN_EVENT_HNF(sf_hit, 0x6),
 419         CCN_EVENT_HNF(sf_evictions, 0x7),
 420         CCN_EVENT_HNF(snoops_sent, 0x8),
 421         CCN_EVENT_HNF(snoops_broadcast, 0x9),
 422         CCN_EVENT_HNF(l3_eviction, 0xa),
 423         CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
 424         CCN_EVENT_HNF(mc_retries, 0xc),
 425         CCN_EVENT_HNF(mc_reqs, 0xd),
 426         CCN_EVENT_HNF(qos_hh_retry, 0xe),
 427         CCN_EVENT_RNI(rdata_beats_p0, 0x1),
 428         CCN_EVENT_RNI(rdata_beats_p1, 0x2),
 429         CCN_EVENT_RNI(rdata_beats_p2, 0x3),
 430         CCN_EVENT_RNI(rxdat_flits, 0x4),
 431         CCN_EVENT_RNI(txdat_flits, 0x5),
 432         CCN_EVENT_RNI(txreq_flits, 0x6),
 433         CCN_EVENT_RNI(txreq_flits_retried, 0x7),
 434         CCN_EVENT_RNI(rrt_full, 0x8),
 435         CCN_EVENT_RNI(wrt_full, 0x9),
 436         CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
 437         CCN_EVENT_XP(upload_starvation, 0x1),
 438         CCN_EVENT_XP(download_starvation, 0x2),
 439         CCN_EVENT_XP(respin, 0x3),
 440         CCN_EVENT_XP(valid_flit, 0x4),
 441         CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
 442         CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
 443         CCN_EVENT_SBAS(rxdat_flits, 0x4),
 444         CCN_EVENT_SBAS(txdat_flits, 0x5),
 445         CCN_EVENT_SBAS(txreq_flits, 0x6),
 446         CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
 447         CCN_EVENT_SBAS(rrt_full, 0x8),
 448         CCN_EVENT_SBAS(wrt_full, 0x9),
 449         CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
 450         CCN_EVENT_CYCLES(cycles),
 451 };
 452
 453 /* Populated in arm_ccn_init() */
 454 static struct attribute
 455                 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
 456
 457 static struct attribute_group arm_ccn_pmu_events_attr_group = {
 458         .name = "events",
 459         .is_visible = arm_ccn_pmu_events_is_visible,
 460         .attrs = arm_ccn_pmu_events_attrs,
 461 };
 462
 463
 464 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
 465 {
 466         unsigned long i;
 467
 468         if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
 469                 return NULL;
 470         i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
 471
 472         switch (name[1]) {
 473         case 'l':
 474                 return &ccn->dt.cmp_mask[i].l;
 475         case 'h':
 476                 return &ccn->dt.cmp_mask[i].h;
 477         default:
 478                 return NULL;
 479         }
 480 }
 481
 482 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
 483                 struct device_attribute *attr, char *buf)
 484 {
 485         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 486         u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
 487
 488         return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
 489 }
 490
 491 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
 492                 struct device_attribute *attr, const char *buf, size_t count)
 493 {
 494         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 495         u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
 496         int err = -EINVAL;
 497
 498         if (mask)
 499                 err = kstrtoull(buf, 0, mask);
 500
 501         return err ? err : count;
 502 }
 503
 504 #define CCN_CMP_MASK_ATTR(_name) \
 505         struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
 506                         __ATTR(_name, S_IRUGO | S_IWUSR, \
 507                         arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
 508
 509 #define CCN_CMP_MASK_ATTR_RO(_name) \
 510         struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
 511                         __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
 512
 513 static CCN_CMP_MASK_ATTR(0l);
 514 static CCN_CMP_MASK_ATTR(0h);
 515 static CCN_CMP_MASK_ATTR(1l);
 516 static CCN_CMP_MASK_ATTR(1h);
 517 static CCN_CMP_MASK_ATTR(2l);
 518 static CCN_CMP_MASK_ATTR(2h);
 519 static CCN_CMP_MASK_ATTR(3l);
 520 static CCN_CMP_MASK_ATTR(3h);
 521 static CCN_CMP_MASK_ATTR(4l);
 522 static CCN_CMP_MASK_ATTR(4h);
 523 static CCN_CMP_MASK_ATTR(5l);
 524 static CCN_CMP_MASK_ATTR(5h);
 525 static CCN_CMP_MASK_ATTR(6l);
 526 static CCN_CMP_MASK_ATTR(6h);
 527 static CCN_CMP_MASK_ATTR(7l);
 528 static CCN_CMP_MASK_ATTR(7h);
 529 static CCN_CMP_MASK_ATTR_RO(8l);
 530 static CCN_CMP_MASK_ATTR_RO(8h);
 531 static CCN_CMP_MASK_ATTR_RO(9l);
 532 static CCN_CMP_MASK_ATTR_RO(9h);
 533 static CCN_CMP_MASK_ATTR_RO(al);
 534 static CCN_CMP_MASK_ATTR_RO(ah);
 535 static CCN_CMP_MASK_ATTR_RO(bl);
 536 static CCN_CMP_MASK_ATTR_RO(bh);
 537
 538 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
 539         &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
 540         &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
 541         &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
 542         &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
 543         &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
 544         &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
 545         &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
 546         &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
 547         &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
 548         &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
 549         &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
 550         &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
 551         NULL
 552 };
 553
 554 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
 555         .name = "cmp_mask",
 556         .attrs = arm_ccn_pmu_cmp_mask_attrs,
 557 };
 558
 559 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
 560                                      struct device_attribute *attr, char *buf)
 561 {
 562         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 563
 564         return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
 565 }
 566
 567 static struct device_attribute arm_ccn_pmu_cpumask_attr =
 568                 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
 569
 570 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
 571         &arm_ccn_pmu_cpumask_attr.attr,
 572         NULL,
 573 };
 574
 575 static struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
 576         .attrs = arm_ccn_pmu_cpumask_attrs,
 577 };
 578
 579 /*
 580  * Default poll period is 10ms, which is way over the top anyway,
 581  * as in the worst case scenario (an event every cycle), with 1GHz
 582  * clocked bus, the smallest, 32 bit counter will overflow in
 583  * more than 4s.
 584  */
 585 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
 586 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
 587                 S_IRUGO | S_IWUSR);
 588
 589 static ktime_t arm_ccn_pmu_timer_period(void)
 590 {
 591         return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
 592 }
 593
 594
 595 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
 596         &arm_ccn_pmu_events_attr_group,
 597         &arm_ccn_pmu_format_attr_group,
 598         &arm_ccn_pmu_cmp_mask_attr_group,
 599         &arm_ccn_pmu_cpumask_attr_group,
 600         NULL
 601 };
 602
 603
 604 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
 605 {
 606         int bit;
 607
 608         do {
 609                 bit = find_first_zero_bit(bitmap, size);
 610                 if (bit >= size)
 611                         return -EAGAIN;
 612         } while (test_and_set_bit(bit, bitmap));
 613
 614         return bit;
 615 }
 616
 617 /* All RN-I and RN-D nodes have identical PMUs */
 618 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
 619 {
 620         if (a == b)
 621                 return 1;
 622
 623         switch (a) {
 624         case CCN_TYPE_RNI_1P:
 625         case CCN_TYPE_RNI_2P:
 626         case CCN_TYPE_RNI_3P:
 627         case CCN_TYPE_RND_1P:
 628         case CCN_TYPE_RND_2P:
 629         case CCN_TYPE_RND_3P:
 630                 switch (b) {
 631                 case CCN_TYPE_RNI_1P:
 632                 case CCN_TYPE_RNI_2P:
 633                 case CCN_TYPE_RNI_3P:
 634                 case CCN_TYPE_RND_1P:
 635                 case CCN_TYPE_RND_2P:
 636                 case CCN_TYPE_RND_3P:
 637                         return 1;
 638                 }
 639                 break;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
 646 {
 647         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 648         struct hw_perf_event *hw = &event->hw;
 649         u32 node_xp, type, event_id;
 650         struct arm_ccn_component *source;
 651         int bit;
 652
 653         node_xp = CCN_CONFIG_NODE(event->attr.config);
 654         type = CCN_CONFIG_TYPE(event->attr.config);
 655         event_id = CCN_CONFIG_EVENT(event->attr.config);
 656
 657         /* Allocate the cycle counter */
 658         if (type == CCN_TYPE_CYCLES) {
 659                 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
 660                                 ccn->dt.pmu_counters_mask))
 661                         return -EAGAIN;
 662
 663                 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
 664                 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
 665
 666                 return 0;
 667         }
 668
 669         /* Allocate an event counter */
 670         hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
 671                         CCN_NUM_PMU_EVENT_COUNTERS);
 672         if (hw->idx < 0) {
 673                 dev_dbg(ccn->dev, "No more counters available!\n");
 674                 return -EAGAIN;
 675         }
 676
 677         if (type == CCN_TYPE_XP)
 678                 source = &ccn->xp[node_xp];
 679         else
 680                 source = &ccn->node[node_xp];
 681         ccn->dt.pmu_counters[hw->idx].source = source;
 682
 683         /* Allocate an event source or a watchpoint */
 684         if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
 685                 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
 686                                 CCN_NUM_XP_WATCHPOINTS);
 687         else
 688                 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
 689                                 CCN_NUM_PMU_EVENTS);
 690         if (bit < 0) {
 691                 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
 692                                 node_xp);
 693                 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
 694                 return -EAGAIN;
 695         }
 696         hw->config_base = bit;
 697
 698         ccn->dt.pmu_counters[hw->idx].event = event;
 699
 700         return 0;
 701 }
 702
 703 static void arm_ccn_pmu_event_release(struct perf_event *event)
 704 {
 705         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 706         struct hw_perf_event *hw = &event->hw;
 707
 708         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
 709                 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
 710         } else {
 711                 struct arm_ccn_component *source =
 712                                 ccn->dt.pmu_counters[hw->idx].source;
 713
 714                 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
 715                                 CCN_CONFIG_EVENT(event->attr.config) ==
 716                                 CCN_EVENT_WATCHPOINT)
 717                         clear_bit(hw->config_base, source->xp.dt_cmp_mask);
 718                 else
 719                         clear_bit(hw->config_base, source->pmu_events_mask);
 720                 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
 721         }
 722
 723         ccn->dt.pmu_counters[hw->idx].source = NULL;
 724         ccn->dt.pmu_counters[hw->idx].event = NULL;
 725 }
 726
 727 static int arm_ccn_pmu_event_init(struct perf_event *event)
 728 {
 729         struct arm_ccn *ccn;
 730         struct hw_perf_event *hw = &event->hw;
 731         u32 node_xp, type, event_id;
 732         int valid;
 733         int i;
 734         struct perf_event *sibling;
 735
 736         if (event->attr.type != event->pmu->type)
 737                 return -ENOENT;
 738
 739         ccn = pmu_to_arm_ccn(event->pmu);
 740
 741         if (hw->sample_period) {
 742                 dev_warn(ccn->dev, "Sampling not supported!\n");
 743                 return -EOPNOTSUPP;
 744         }
 745
 746         if (has_branch_stack(event) || event->attr.exclude_user ||
 747                         event->attr.exclude_kernel || event->attr.exclude_hv ||
 748                         event->attr.exclude_idle) {
 749                 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
 750                 return -EOPNOTSUPP;
 751         }
 752
 753         if (event->cpu < 0) {
 754                 dev_warn(ccn->dev, "Can't provide per-task data!\n");
 755                 return -EOPNOTSUPP;
 756         }
 757         /*
 758          * Many perf core operations (eg. events rotation) operate on a
 759          * single CPU context. This is obvious for CPU PMUs, where one
 760          * expects the same sets of events being observed on all CPUs,
 761          * but can lead to issues for off-core PMUs, like CCN, where each
 762          * event could be theoretically assigned to a different CPU. To
 763          * mitigate this, we enforce CPU assignment to one, selected
 764          * processor (the one described in the "cpumask" attribute).
 765          */
 766         event->cpu = cpumask_first(&ccn->dt.cpu);
 767
 768         node_xp = CCN_CONFIG_NODE(event->attr.config);
 769         type = CCN_CONFIG_TYPE(event->attr.config);
 770         event_id = CCN_CONFIG_EVENT(event->attr.config);
 771
 772         /* Validate node/xp vs topology */
 773         switch (type) {
 774         case CCN_TYPE_MN:
 775                 if (node_xp != ccn->mn_id) {
 776                         dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
 777                         return -EINVAL;
 778                 }
 779                 break;
 780         case CCN_TYPE_XP:
 781                 if (node_xp >= ccn->num_xps) {
 782                         dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
 783                         return -EINVAL;
 784                 }
 785                 break;
 786         case CCN_TYPE_CYCLES:
 787                 break;
 788         default:
 789                 if (node_xp >= ccn->num_nodes) {
 790                         dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
 791                         return -EINVAL;
 792                 }
 793                 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
 794                         dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
 795                                         type, node_xp);
 796                         return -EINVAL;
 797                 }
 798                 break;
 799         }
 800
 801         /* Validate event ID vs available for the type */
 802         for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
 803                         i++) {
 804                 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
 805                 u32 port = CCN_CONFIG_PORT(event->attr.config);
 806                 u32 vc = CCN_CONFIG_VC(event->attr.config);
 807
 808                 if (!arm_ccn_pmu_type_eq(type, e->type))
 809                         continue;
 810                 if (event_id != e->event)
 811                         continue;
 812                 if (e->num_ports && port >= e->num_ports) {
 813                         dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
 814                                         port, node_xp);
 815                         return -EINVAL;
 816                 }
 817                 if (e->num_vcs && vc >= e->num_vcs) {
 818                         dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
 819                                         vc, node_xp);
 820                         return -EINVAL;
 821                 }
 822                 valid = 1;
 823         }
 824         if (!valid) {
 825                 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
 826                                 event_id, node_xp);
 827                 return -EINVAL;
 828         }
 829
 830         /* Watchpoint-based event for a node is actually set on XP */
 831         if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
 832                 u32 port;
 833
 834                 type = CCN_TYPE_XP;
 835                 port = arm_ccn_node_to_xp_port(node_xp);
 836                 node_xp = arm_ccn_node_to_xp(node_xp);
 837
 838                 arm_ccn_pmu_config_set(&event->attr.config,
 839                                 node_xp, type, port);
 840         }
 841
 842         /*
 843          * We must NOT create groups containing mixed PMUs, although software
 844          * events are acceptable (for example to create a CCN group
 845          * periodically read when a hrtimer aka cpu-clock leader triggers).
 846          */
 847         if (event->group_leader->pmu != event->pmu &&
 848                         !is_software_event(event->group_leader))
 849                 return -EINVAL;
 850
 851         list_for_each_entry(sibling, &event->group_leader->sibling_list,
 852                         group_entry)
 853                 if (sibling->pmu != event->pmu &&
 854                                 !is_software_event(sibling))
 855                         return -EINVAL;
 856
 857         return 0;
 858 }
 859
 860 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
 861 {
 862         u64 res;
 863
 864         if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
 865 #ifdef readq
 866                 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
 867 #else
 868                 /* 40 bit counter, can do snapshot and read in two parts */
 869                 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
 870                 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
 871                         ;
 872                 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
 873                 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
 874                 res <<= 32;
 875                 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
 876 #endif
 877         } else {
 878                 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
 879         }
 880
 881         return res;
 882 }
 883
 884 static void arm_ccn_pmu_event_update(struct perf_event *event)
 885 {
 886         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 887         struct hw_perf_event *hw = &event->hw;
 888         u64 prev_count, new_count, mask;
 889
 890         do {
 891                 prev_count = local64_read(&hw->prev_count);
 892                 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
 893         } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
 894
 895         mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
 896
 897         local64_add((new_count - prev_count) & mask, &event->count);
 898 }
 899
 900 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
 901 {
 902         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 903         struct hw_perf_event *hw = &event->hw;
 904         struct arm_ccn_component *xp;
 905         u32 val, dt_cfg;
 906
 907         /* Nothing to do for cycle counter */
 908         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
 909                 return;
 910
 911         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
 912                 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
 913         else
 914                 xp = &ccn->xp[arm_ccn_node_to_xp(
 915                                 CCN_CONFIG_NODE(event->attr.config))];
 916
 917         if (enable)
 918                 dt_cfg = hw->event_base;
 919         else
 920                 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
 921
 922         spin_lock(&ccn->dt.config_lock);
 923
 924         val = readl(xp->base + CCN_XP_DT_CONFIG);
 925         val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
 926                         CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
 927         val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
 928         writel(val, xp->base + CCN_XP_DT_CONFIG);
 929
 930         spin_unlock(&ccn->dt.config_lock);
 931 }
 932
 933 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
 934 {
 935         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 936         struct hw_perf_event *hw = &event->hw;
 937
 938         local64_set(&event->hw.prev_count,
 939                         arm_ccn_pmu_read_counter(ccn, hw->idx));
 940         hw->state = 0;
 941
 942         /*
 943          * Pin the timer, so that the overflows are handled by the chosen
 944          * event->cpu (this is the same one as presented in "cpumask"
 945          * attribute).
 946          */
 947         if (!ccn->irq)
 948                 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
 949                                 HRTIMER_MODE_REL_PINNED);
 950
 951         /* Set the DT bus input, engaging the counter */
 952         arm_ccn_pmu_xp_dt_config(event, 1);
 953 }
 954
 955 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
 956 {
 957         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 958         struct hw_perf_event *hw = &event->hw;
 959         u64 timeout;
 960
 961         /* Disable counting, setting the DT bus to pass-through mode */
 962         arm_ccn_pmu_xp_dt_config(event, 0);
 963
 964         if (!ccn->irq)
 965                 hrtimer_cancel(&ccn->dt.hrtimer);
 966
 967         /* Let the DT bus drain */
 968         timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
 969                         ccn->num_xps;
 970         while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
 971                         timeout)
 972                 cpu_relax();
 973
 974         if (flags & PERF_EF_UPDATE)
 975                 arm_ccn_pmu_event_update(event);
 976
 977         hw->state |= PERF_HES_STOPPED;
 978 }
 979
 980 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
 981 {
 982         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 983         struct hw_perf_event *hw = &event->hw;
 984         struct arm_ccn_component *source =
 985                         ccn->dt.pmu_counters[hw->idx].source;
 986         unsigned long wp = hw->config_base;
 987         u32 val;
 988         u64 cmp_l = event->attr.config1;
 989         u64 cmp_h = event->attr.config2;
 990         u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
 991         u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
 992
 993         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
 994
 995         /* Direction (RX/TX), device (port) & virtual channel */
 996         val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
 997         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
 998                         CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
 999         val |= CCN_CONFIG_DIR(event->attr.config) <<
1000                         CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
1001         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
1002                         CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
1003         val |= CCN_CONFIG_PORT(event->attr.config) <<
1004                         CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
1005         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
1006                         CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
1007         val |= CCN_CONFIG_VC(event->attr.config) <<
1008                         CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
1009         writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
1010
1011         /* Comparison values */
1012         writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
1013         writel((cmp_l >> 32) & 0x7fffffff,
1014                         source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
1015         writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
1016         writel((cmp_h >> 32) & 0x0fffffff,
1017                         source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
1018
1019         /* Mask */
1020         writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
1021         writel((mask_l >> 32) & 0x7fffffff,
1022                         source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
1023         writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
1024         writel((mask_h >> 32) & 0x0fffffff,
1025                         source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1026 }
1027
1028 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1029 {
1030         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1031         struct hw_perf_event *hw = &event->hw;
1032         struct arm_ccn_component *source =
1033                         ccn->dt.pmu_counters[hw->idx].source;
1034         u32 val, id;
1035
1036         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1037
1038         id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1039                         (CCN_CONFIG_BUS(event->attr.config) << 3) |
1040                         (CCN_CONFIG_EVENT(event->attr.config) << 0);
1041
1042         val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1043         val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1044                         CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1045         val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1046         writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1047 }
1048
1049 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1050 {
1051         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1052         struct hw_perf_event *hw = &event->hw;
1053         struct arm_ccn_component *source =
1054                         ccn->dt.pmu_counters[hw->idx].source;
1055         u32 type = CCN_CONFIG_TYPE(event->attr.config);
1056         u32 val, port;
1057
1058         port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1059         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1060                         hw->config_base);
1061
1062         /* These *_event_sel regs should be identical, but let's make sure... */
1063         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1064         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1065         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1066                         CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1067         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1068                         CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1069         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1070                         CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1071         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1072                         CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1073         if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1074                         !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1075                 return;
1076
1077         /* Set the event id for the pre-allocated counter */
1078         val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1079         val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1080                 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1081         val |= CCN_CONFIG_EVENT(event->attr.config) <<
1082                 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1083         writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1084 }
1085
1086 static void arm_ccn_pmu_event_config(struct perf_event *event)
1087 {
1088         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1089         struct hw_perf_event *hw = &event->hw;
1090         u32 xp, offset, val;
1091
1092         /* Cycle counter requires no setup */
1093         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1094                 return;
1095
1096         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1097                 xp = CCN_CONFIG_XP(event->attr.config);
1098         else
1099                 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1100
1101         spin_lock(&ccn->dt.config_lock);
1102
1103         /* Set the DT bus "distance" register */
1104         offset = (hw->idx / 4) * 4;
1105         val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1106         val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1107                         CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1108         val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1109         writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1110
1111         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1112                 if (CCN_CONFIG_EVENT(event->attr.config) ==
1113                                 CCN_EVENT_WATCHPOINT)
1114                         arm_ccn_pmu_xp_watchpoint_config(event);
1115                 else
1116                         arm_ccn_pmu_xp_event_config(event);
1117         } else {
1118                 arm_ccn_pmu_node_event_config(event);
1119         }
1120
1121         spin_unlock(&ccn->dt.config_lock);
1122 }
1123
1124 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1125 {
1126         int err;
1127         struct hw_perf_event *hw = &event->hw;
1128
1129         err = arm_ccn_pmu_event_alloc(event);
1130         if (err)
1131                 return err;
1132
1133         arm_ccn_pmu_event_config(event);
1134
1135         hw->state = PERF_HES_STOPPED;
1136
1137         if (flags & PERF_EF_START)
1138                 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1139
1140         return 0;
1141 }
1142
1143 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1144 {
1145         arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1146
1147         arm_ccn_pmu_event_release(event);
1148 }
1149
1150 static void arm_ccn_pmu_event_read(struct perf_event *event)
1151 {
1152         arm_ccn_pmu_event_update(event);
1153 }
1154
1155 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1156 {
1157         u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1158         int idx;
1159
1160         if (!pmovsr)
1161                 return IRQ_NONE;
1162
1163         writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1164
1165         BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1166
1167         for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1168                 struct perf_event *event = dt->pmu_counters[idx].event;
1169                 int overflowed = pmovsr & BIT(idx);
1170
1171                 WARN_ON_ONCE(overflowed && !event &&
1172                                 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1173
1174                 if (!event || !overflowed)
1175                         continue;
1176
1177                 arm_ccn_pmu_event_update(event);
1178         }
1179
1180         return IRQ_HANDLED;
1181 }
1182
1183 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1184 {
1185         struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1186                         hrtimer);
1187         unsigned long flags;
1188
1189         local_irq_save(flags);
1190         arm_ccn_pmu_overflow_handler(dt);
1191         local_irq_restore(flags);
1192
1193         hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1194         return HRTIMER_RESTART;
1195 }
1196
1197
1198 static int arm_ccn_pmu_offline_cpu(unsigned int cpu)
1199 {
1200         struct arm_ccn_dt *dt;
1201         unsigned int target;
1202
1203         mutex_lock(&arm_ccn_mutex);
1204         list_for_each_entry(dt, &arm_ccn_list, entry) {
1205                 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1206
1207                 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1208                         continue;
1209                 target = cpumask_any_but(cpu_online_mask, cpu);
1210                 if (target >= nr_cpu_ids)
1211                         continue;
1212                 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1213                 cpumask_set_cpu(target, &dt->cpu);
1214                 if (ccn->irq)
1215                         WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0);
1216         }
1217         mutex_unlock(&arm_ccn_mutex);
1218         return 0;
1219 }
1220
1221
1222 static DEFINE_IDA(arm_ccn_pmu_ida);
1223
1224 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1225 {
1226         int i;
1227         char *name;
1228         int err;
1229
1230         /* Initialize DT subsystem */
1231         ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1232         spin_lock_init(&ccn->dt.config_lock);
1233         writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1234         writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1235         writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1236                         ccn->dt.base + CCN_DT_PMCR);
1237         writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1238         for (i = 0; i < ccn->num_xps; i++) {
1239                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1240                 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1241                                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1242                                 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1243                                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1244                                 CCN_XP_DT_CONTROL__DT_ENABLE,
1245                                 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1246         }
1247         ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1248         ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1249         ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1250         ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1251         ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1252         ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1253         ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1254         ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1255
1256         /* Get a convenient /sys/event_source/devices/ name */
1257         ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1258         if (ccn->dt.id == 0) {
1259                 name = "ccn";
1260         } else {
1261                 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1262
1263                 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1264                 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1265         }
1266
1267         /* Perf driver registration */
1268         ccn->dt.pmu = (struct pmu) {
1269                 .attr_groups = arm_ccn_pmu_attr_groups,
1270                 .task_ctx_nr = perf_invalid_context,
1271                 .event_init = arm_ccn_pmu_event_init,
1272                 .add = arm_ccn_pmu_event_add,
1273                 .del = arm_ccn_pmu_event_del,
1274                 .start = arm_ccn_pmu_event_start,
1275                 .stop = arm_ccn_pmu_event_stop,
1276                 .read = arm_ccn_pmu_event_read,
1277         };
1278
1279         /* No overflow interrupt? Have to use a timer instead. */
1280         if (!ccn->irq) {
1281                 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1282                 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1283                                 HRTIMER_MODE_REL);
1284                 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1285         }
1286
1287         /* Pick one CPU which we will use to collect data from CCN... */
1288         cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);
1289
1290         /* Also make sure that the overflow interrupt is handled by this CPU */
1291         if (ccn->irq) {
1292                 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu);
1293                 if (err) {
1294                         dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1295                         goto error_set_affinity;
1296                 }
1297         }
1298
1299         err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1300         if (err)
1301                 goto error_pmu_register;
1302
1303         mutex_lock(&arm_ccn_mutex);
1304         list_add(&ccn->dt.entry, &arm_ccn_list);
1305         mutex_unlock(&arm_ccn_mutex);
1306         return 0;
1307
1308 error_pmu_register:
1309 error_set_affinity:
1310         ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1311         for (i = 0; i < ccn->num_xps; i++)
1312                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1313         writel(0, ccn->dt.base + CCN_DT_PMCR);
1314         return err;
1315 }
1316
1317 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1318 {
1319         int i;
1320
1321         mutex_lock(&arm_ccn_mutex);
1322         list_del(&ccn->dt.entry);
1323         mutex_unlock(&arm_ccn_mutex);
1324
1325         if (ccn->irq)
1326                 irq_set_affinity_hint(ccn->irq, NULL);
1327         for (i = 0; i < ccn->num_xps; i++)
1328                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1329         writel(0, ccn->dt.base + CCN_DT_PMCR);
1330         perf_pmu_unregister(&ccn->dt.pmu);
1331         ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1332 }
1333
1334 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1335                 int (*callback)(struct arm_ccn *ccn, int region,
1336                 void __iomem *base, u32 type, u32 id))
1337 {
1338         int region;
1339
1340         for (region = 0; region < CCN_NUM_REGIONS; region++) {
1341                 u32 val, type, id;
1342                 void __iomem *base;
1343                 int err;
1344
1345                 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1346                                 4 * (region / 32));
1347                 if (!(val & (1 << (region % 32))))
1348                         continue;
1349
1350                 base = ccn->base + region * CCN_REGION_SIZE;
1351                 val = readl(base + CCN_ALL_OLY_ID);
1352                 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1353                                 CCN_ALL_OLY_ID__OLY_ID__MASK;
1354                 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1355                                 CCN_ALL_OLY_ID__NODE_ID__MASK;
1356
1357                 err = callback(ccn, region, base, type, id);
1358                 if (err)
1359                         return err;
1360         }
1361
1362         return 0;
1363 }
1364
1365 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1366                 void __iomem *base, u32 type, u32 id)
1367 {
1368
1369         if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1370                 ccn->num_xps = id + 1;
1371         else if (id >= ccn->num_nodes)
1372                 ccn->num_nodes = id + 1;
1373
1374         return 0;
1375 }
1376
1377 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1378                 void __iomem *base, u32 type, u32 id)
1379 {
1380         struct arm_ccn_component *component;
1381
1382         dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1383
1384         switch (type) {
1385         case CCN_TYPE_MN:
1386                 ccn->mn_id = id;
1387                 return 0;
1388         case CCN_TYPE_DT:
1389                 return 0;
1390         case CCN_TYPE_XP:
1391                 component = &ccn->xp[id];
1392                 break;
1393         case CCN_TYPE_SBSX:
1394                 ccn->sbsx_present = 1;
1395                 component = &ccn->node[id];
1396                 break;
1397         case CCN_TYPE_SBAS:
1398                 ccn->sbas_present = 1;
1399                 /* Fall-through */
1400         default:
1401                 component = &ccn->node[id];
1402                 break;
1403         }
1404
1405         component->base = base;
1406         component->type = type;
1407
1408         return 0;
1409 }
1410
1411
1412 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1413                 const u32 *err_sig_val)
1414 {
1415         /* This should be really handled by firmware... */
1416         dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1417                         err_sig_val[5], err_sig_val[4], err_sig_val[3],
1418                         err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1419         dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1420         writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1421                         ccn->base + CCN_MN_ERRINT_STATUS);
1422
1423         return IRQ_HANDLED;
1424 }
1425
1426
1427 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1428 {
1429         irqreturn_t res = IRQ_NONE;
1430         struct arm_ccn *ccn = dev_id;
1431         u32 err_sig_val[6];
1432         u32 err_or;
1433         int i;
1434
1435         /* PMU overflow is a special case */
1436         err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1437         if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1438                 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1439                 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1440         }
1441
1442         /* Have to read all err_sig_vals to clear them */
1443         for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1444                 err_sig_val[i] = readl(ccn->base +
1445                                 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1446                 err_or |= err_sig_val[i];
1447         }
1448         if (err_or)
1449                 res |= arm_ccn_error_handler(ccn, err_sig_val);
1450
1451         if (res != IRQ_NONE)
1452                 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1453                                 ccn->base + CCN_MN_ERRINT_STATUS);
1454
1455         return res;
1456 }
1457
1458
1459 static int arm_ccn_probe(struct platform_device *pdev)
1460 {
1461         struct arm_ccn *ccn;
1462         struct resource *res;
1463         unsigned int irq;
1464         int err;
1465
1466         ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1467         if (!ccn)
1468                 return -ENOMEM;
1469         ccn->dev = &pdev->dev;
1470         platform_set_drvdata(pdev, ccn);
1471
1472         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1473         if (!res)
1474                 return -EINVAL;
1475
1476         if (!devm_request_mem_region(ccn->dev, res->start,
1477                         resource_size(res), pdev->name))
1478                 return -EBUSY;
1479
1480         ccn->base = devm_ioremap(ccn->dev, res->start,
1481                                 resource_size(res));
1482         if (!ccn->base)
1483                 return -EFAULT;
1484
1485         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1486         if (!res)
1487                 return -EINVAL;
1488         irq = res->start;
1489
1490         /* Check if we can use the interrupt */
1491         writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1492                         ccn->base + CCN_MN_ERRINT_STATUS);
1493         if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1494                         CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1495                 /* Can set 'disable' bits, so can acknowledge interrupts */
1496                 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1497                                 ccn->base + CCN_MN_ERRINT_STATUS);
1498                 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
1499                                 dev_name(ccn->dev), ccn);
1500                 if (err)
1501                         return err;
1502
1503                 ccn->irq = irq;
1504         }
1505
1506
1507         /* Build topology */
1508
1509         err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1510         if (err)
1511                 return err;
1512
1513         ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1514                 GFP_KERNEL);
1515         ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1516                 GFP_KERNEL);
1517         if (!ccn->node || !ccn->xp)
1518                 return -ENOMEM;
1519
1520         err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1521         if (err)
1522                 return err;
1523
1524         return arm_ccn_pmu_init(ccn);
1525 }
1526
1527 static int arm_ccn_remove(struct platform_device *pdev)
1528 {
1529         struct arm_ccn *ccn = platform_get_drvdata(pdev);
1530
1531         arm_ccn_pmu_cleanup(ccn);
1532
1533         return 0;
1534 }
1535
1536 static const struct of_device_id arm_ccn_match[] = {
1537         { .compatible = "arm,ccn-504", },
1538         {},
1539 };
1540
1541 static struct platform_driver arm_ccn_driver = {
1542         .driver = {
1543                 .name = "arm-ccn",
1544                 .of_match_table = arm_ccn_match,
1545         },
1546         .probe = arm_ccn_probe,
1547         .remove = arm_ccn_remove,
1548 };
1549
1550 static int __init arm_ccn_init(void)
1551 {
1552         int i, ret;
1553
1554         ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1555                                         "AP_PERF_ARM_CCN_ONLINE", NULL,
1556                                         arm_ccn_pmu_offline_cpu);
1557         if (ret)
1558                 return ret;
1559
1560         for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1561                 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1562
1563         return platform_driver_register(&arm_ccn_driver);
1564 }
1565
1566 static void __exit arm_ccn_exit(void)
1567 {
1568         cpuhp_remove_state_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1569         platform_driver_unregister(&arm_ccn_driver);
1570 }
1571
1572 module_init(arm_ccn_init);
1573 module_exit(arm_ccn_exit);
1574
1575 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1576 MODULE_LICENSE("GPL");