2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/mbus.h>
55 #include <linux/ioport.h>
57 #include <linux/of_address.h>
58 #include <linux/debugfs.h>
59 #include <linux/log2.h>
60 #include <linux/syscore_ops.h>
63 * DDR target is the same on all platforms.
68 * CPU Address Decode Windows registers
70 #define WIN_CTRL_OFF 0x0000
71 #define WIN_CTRL_ENABLE BIT(0)
72 #define WIN_CTRL_SYNCBARRIER BIT(1)
73 #define WIN_CTRL_TGT_MASK 0xf0
74 #define WIN_CTRL_TGT_SHIFT 4
75 #define WIN_CTRL_ATTR_MASK 0xff00
76 #define WIN_CTRL_ATTR_SHIFT 8
77 #define WIN_CTRL_SIZE_MASK 0xffff0000
78 #define WIN_CTRL_SIZE_SHIFT 16
79 #define WIN_BASE_OFF 0x0004
80 #define WIN_BASE_LOW 0xffff0000
81 #define WIN_BASE_HIGH 0xf
82 #define WIN_REMAP_LO_OFF 0x0008
83 #define WIN_REMAP_LOW 0xffff0000
84 #define WIN_REMAP_HI_OFF 0x000c
86 #define UNIT_SYNC_BARRIER_OFF 0x84
87 #define UNIT_SYNC_BARRIER_ALL 0xFFFF
89 #define ATTR_HW_COHERENCY (0x1 << 4)
91 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
92 #define DDR_BASE_CS_HIGH_MASK 0xf
93 #define DDR_BASE_CS_LOW_MASK 0xff000000
94 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
95 #define DDR_SIZE_ENABLED BIT(0)
96 #define DDR_SIZE_CS_MASK 0x1c
97 #define DDR_SIZE_CS_SHIFT 2
98 #define DDR_SIZE_MASK 0xff000000
100 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
102 /* Relative to mbusbridge_base */
103 #define MBUS_BRIDGE_CTRL_OFF 0x0
104 #define MBUS_BRIDGE_BASE_OFF 0x4
106 /* Maximum number of windows, for all known platforms */
107 #define MBUS_WINS_MAX 20
109 struct mvebu_mbus_state;
111 struct mvebu_mbus_soc_data {
112 unsigned int num_wins;
113 unsigned int num_remappable_wins;
114 bool has_mbus_bridge;
115 unsigned int (*win_cfg_offset)(const int win);
116 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
117 int (*save_cpu_target)(struct mvebu_mbus_state *s,
119 int (*show_cpu_target)(struct mvebu_mbus_state *s,
120 struct seq_file *seq, void *v);
124 * Used to store the state of one MBus window accross suspend/resume.
126 struct mvebu_mbus_win_data {
133 struct mvebu_mbus_state {
134 void __iomem *mbuswins_base;
135 void __iomem *sdramwins_base;
136 void __iomem *mbusbridge_base;
137 phys_addr_t sdramwins_phys_base;
138 struct dentry *debugfs_root;
139 struct dentry *debugfs_sdram;
140 struct dentry *debugfs_devs;
141 struct resource pcie_mem_aperture;
142 struct resource pcie_io_aperture;
143 const struct mvebu_mbus_soc_data *soc;
146 /* Used during suspend/resume */
147 u32 mbus_bridge_ctrl;
148 u32 mbus_bridge_base;
149 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
152 static struct mvebu_mbus_state mbus_state;
154 static struct mbus_dram_target_info mvebu_mbus_dram_info;
155 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
157 return &mvebu_mbus_dram_info;
159 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
162 * Functions to manipulate the address decoding windows
165 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
166 int win, int *enabled, u64 *base,
167 u32 *size, u8 *target, u8 *attr,
170 void __iomem *addr = mbus->mbuswins_base +
171 mbus->soc->win_cfg_offset(win);
172 u32 basereg = readl(addr + WIN_BASE_OFF);
173 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
175 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
181 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
182 *base |= (basereg & WIN_BASE_LOW);
183 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
186 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
189 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
192 if (win < mbus->soc->num_remappable_wins) {
193 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
194 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
195 *remap = ((u64)remap_hi << 32) | remap_low;
201 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
206 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
208 writel(0, addr + WIN_BASE_OFF);
209 writel(0, addr + WIN_CTRL_OFF);
210 if (win < mbus->soc->num_remappable_wins) {
211 writel(0, addr + WIN_REMAP_LO_OFF);
212 writel(0, addr + WIN_REMAP_HI_OFF);
216 /* Checks whether the given window number is available */
218 /* On Armada XP, 375 and 38x the MBus window 13 has the remap
219 * capability, like windows 0 to 7. However, the mvebu-mbus driver
220 * isn't currently taking into account this special case, which means
221 * that when window 13 is actually used, the remap registers are left
222 * to 0, making the device using this MBus window unavailable. The
223 * quick fix for stable is to not use window 13. A follow up patch
224 * will correctly handle this window.
226 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
229 void __iomem *addr = mbus->mbuswins_base +
230 mbus->soc->win_cfg_offset(win);
231 u32 ctrl = readl(addr + WIN_CTRL_OFF);
236 return !(ctrl & WIN_CTRL_ENABLE);
240 * Checks whether the given (base, base+size) area doesn't overlap an
243 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
244 phys_addr_t base, size_t size,
247 u64 end = (u64)base + size;
250 for (win = 0; win < mbus->soc->num_wins; win++) {
256 mvebu_mbus_read_window(mbus, win,
257 &enabled, &wbase, &wsize,
258 &wtarget, &wattr, NULL);
263 wend = wbase + wsize;
266 * Check if the current window overlaps with the
267 * proposed physical range
269 if ((u64)base < wend && end > wbase)
276 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
277 phys_addr_t base, size_t size)
281 for (win = 0; win < mbus->soc->num_wins; win++) {
286 mvebu_mbus_read_window(mbus, win,
287 &enabled, &wbase, &wsize,
293 if (base == wbase && size == wsize)
300 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
301 int win, phys_addr_t base, size_t size,
302 phys_addr_t remap, u8 target,
305 void __iomem *addr = mbus->mbuswins_base +
306 mbus->soc->win_cfg_offset(win);
307 u32 ctrl, remap_addr;
309 if (!is_power_of_2(size)) {
310 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
314 if ((base & (phys_addr_t)(size - 1)) != 0) {
315 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
320 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
321 (attr << WIN_CTRL_ATTR_SHIFT) |
322 (target << WIN_CTRL_TGT_SHIFT) |
323 WIN_CTRL_SYNCBARRIER |
326 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
327 writel(ctrl, addr + WIN_CTRL_OFF);
328 if (win < mbus->soc->num_remappable_wins) {
329 if (remap == MVEBU_MBUS_NO_REMAP)
333 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
334 writel(0, addr + WIN_REMAP_HI_OFF);
340 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
341 phys_addr_t base, size_t size,
342 phys_addr_t remap, u8 target,
347 if (remap == MVEBU_MBUS_NO_REMAP) {
348 for (win = mbus->soc->num_remappable_wins;
349 win < mbus->soc->num_wins; win++)
350 if (mvebu_mbus_window_is_free(mbus, win))
351 return mvebu_mbus_setup_window(mbus, win, base,
357 for (win = 0; win < mbus->soc->num_wins; win++)
358 if (mvebu_mbus_window_is_free(mbus, win))
359 return mvebu_mbus_setup_window(mbus, win, base, size,
360 remap, target, attr);
369 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
370 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
371 struct seq_file *seq, void *v)
375 for (i = 0; i < 4; i++) {
376 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
377 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
381 if (!(sizereg & DDR_SIZE_ENABLED)) {
382 seq_printf(seq, "[%d] disabled\n", i);
386 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
387 base |= basereg & DDR_BASE_CS_LOW_MASK;
388 size = (sizereg | ~DDR_SIZE_MASK);
390 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
391 i, (unsigned long long)base,
392 (unsigned long long)base + size + 1,
393 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
399 /* Special function for Dove */
400 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
401 struct seq_file *seq, void *v)
405 for (i = 0; i < 2; i++) {
406 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
411 seq_printf(seq, "[%d] disabled\n", i);
415 base = map & 0xff800000;
416 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
418 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
419 i, (unsigned long long)base,
420 (unsigned long long)base + size, i);
426 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
428 struct mvebu_mbus_state *mbus = &mbus_state;
429 return mbus->soc->show_cpu_target(mbus, seq, v);
432 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
434 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
437 static const struct file_operations mvebu_sdram_debug_fops = {
438 .open = mvebu_sdram_debug_open,
441 .release = single_release,
444 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
446 struct mvebu_mbus_state *mbus = &mbus_state;
449 for (win = 0; win < mbus->soc->num_wins; win++) {
455 mvebu_mbus_read_window(mbus, win,
456 &enabled, &wbase, &wsize,
457 &wtarget, &wattr, &wremap);
460 seq_printf(seq, "[%02d] disabled\n", win);
464 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
465 win, (unsigned long long)wbase,
466 (unsigned long long)(wbase + wsize), wtarget, wattr);
468 if (!is_power_of_2(wsize) ||
469 ((wbase & (u64)(wsize - 1)) != 0))
470 seq_puts(seq, " (Invalid base/size!!)");
472 if (win < mbus->soc->num_remappable_wins) {
473 seq_printf(seq, " (remap %016llx)\n",
474 (unsigned long long)wremap);
476 seq_printf(seq, "\n");
482 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
484 return single_open(file, mvebu_devs_debug_show, inode->i_private);
487 static const struct file_operations mvebu_devs_debug_fops = {
488 .open = mvebu_devs_debug_open,
491 .release = single_release,
495 * SoC-specific functions and definitions
498 static unsigned int orion_mbus_win_offset(int win)
503 static unsigned int armada_370_xp_mbus_win_offset(int win)
505 /* The register layout is a bit annoying and the below code
506 * tries to cope with it.
507 * - At offset 0x0, there are the registers for the first 8
508 * windows, with 4 registers of 32 bits per window (ctrl,
509 * base, remap low, remap high)
510 * - Then at offset 0x80, there is a hole of 0x10 bytes for
511 * the internal registers base address and internal units
512 * sync barrier register.
513 * - Then at offset 0x90, there the registers for 12
514 * windows, with only 2 registers of 32 bits per window
520 return 0x90 + ((win - 8) << 3);
523 static unsigned int mv78xx0_mbus_win_offset(int win)
528 return 0x900 + ((win - 8) << 4);
532 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
537 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
539 for (i = 0, cs = 0; i < 4; i++) {
540 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
541 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
544 * We only take care of entries for which the chip
545 * select is enabled, and that don't have high base
546 * address bits set (devices can only access the first
547 * 32 bits of the memory).
549 if ((size & DDR_SIZE_ENABLED) &&
550 !(base & DDR_BASE_CS_HIGH_MASK)) {
551 struct mbus_dram_window *w;
553 w = &mvebu_mbus_dram_info.cs[cs++];
555 w->mbus_attr = 0xf & ~(1 << i);
556 if (mbus->hw_io_coherency)
557 w->mbus_attr |= ATTR_HW_COHERENCY;
558 w->base = base & DDR_BASE_CS_LOW_MASK;
559 w->size = (size | ~DDR_SIZE_MASK) + 1;
562 mvebu_mbus_dram_info.num_cs = cs;
566 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
571 for (i = 0; i < 4; i++) {
572 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
573 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
575 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
577 writel(base, store_addr++);
578 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
580 writel(size, store_addr++);
583 /* We've written 16 words to the store address */
588 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
593 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
595 for (i = 0, cs = 0; i < 2; i++) {
596 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
599 * Chip select enabled?
602 struct mbus_dram_window *w;
604 w = &mvebu_mbus_dram_info.cs[cs++];
606 w->mbus_attr = 0; /* CS address decoding done inside */
607 /* the DDR controller, no need to */
608 /* provide attributes */
609 w->base = map & 0xff800000;
610 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
614 mvebu_mbus_dram_info.num_cs = cs;
618 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
623 for (i = 0; i < 2; i++) {
624 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
626 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
628 writel(map, store_addr++);
631 /* We've written 4 words to the store address */
635 int mvebu_mbus_save_cpu_target(u32 *store_addr)
637 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
640 static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
642 .num_remappable_wins = 8,
643 .has_mbus_bridge = true,
644 .win_cfg_offset = armada_370_xp_mbus_win_offset,
645 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
646 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
647 .show_cpu_target = mvebu_sdram_debug_show_orion,
650 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
652 .num_remappable_wins = 4,
653 .win_cfg_offset = orion_mbus_win_offset,
654 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
655 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
656 .show_cpu_target = mvebu_sdram_debug_show_orion,
659 static const struct mvebu_mbus_soc_data dove_mbus_data = {
661 .num_remappable_wins = 4,
662 .win_cfg_offset = orion_mbus_win_offset,
663 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
664 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
665 .show_cpu_target = mvebu_sdram_debug_show_dove,
669 * Some variants of Orion5x have 4 remappable windows, some other have
672 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
674 .num_remappable_wins = 4,
675 .win_cfg_offset = orion_mbus_win_offset,
676 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
677 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
678 .show_cpu_target = mvebu_sdram_debug_show_orion,
681 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
683 .num_remappable_wins = 2,
684 .win_cfg_offset = orion_mbus_win_offset,
685 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
686 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
687 .show_cpu_target = mvebu_sdram_debug_show_orion,
690 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
692 .num_remappable_wins = 8,
693 .win_cfg_offset = mv78xx0_mbus_win_offset,
694 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
695 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
696 .show_cpu_target = mvebu_sdram_debug_show_orion,
699 static const struct of_device_id of_mvebu_mbus_ids[] = {
700 { .compatible = "marvell,armada370-mbus",
701 .data = &armada_370_xp_mbus_data, },
702 { .compatible = "marvell,armadaxp-mbus",
703 .data = &armada_370_xp_mbus_data, },
704 { .compatible = "marvell,kirkwood-mbus",
705 .data = &kirkwood_mbus_data, },
706 { .compatible = "marvell,dove-mbus",
707 .data = &dove_mbus_data, },
708 { .compatible = "marvell,orion5x-88f5281-mbus",
709 .data = &orion5x_4win_mbus_data, },
710 { .compatible = "marvell,orion5x-88f5182-mbus",
711 .data = &orion5x_2win_mbus_data, },
712 { .compatible = "marvell,orion5x-88f5181-mbus",
713 .data = &orion5x_2win_mbus_data, },
714 { .compatible = "marvell,orion5x-88f6183-mbus",
715 .data = &orion5x_4win_mbus_data, },
716 { .compatible = "marvell,mv78xx0-mbus",
717 .data = &mv78xx0_mbus_data, },
722 * Public API of the driver
724 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
725 unsigned int attribute,
726 phys_addr_t base, size_t size,
729 struct mvebu_mbus_state *s = &mbus_state;
731 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
732 pr_err("cannot add window '%x:%x', conflicts with another window\n",
737 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
740 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
741 phys_addr_t base, size_t size)
743 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
744 size, MVEBU_MBUS_NO_REMAP);
747 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
751 win = mvebu_mbus_find_window(&mbus_state, base, size);
755 mvebu_mbus_disable_window(&mbus_state, win);
759 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
763 *res = mbus_state.pcie_mem_aperture;
766 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
770 *res = mbus_state.pcie_io_aperture;
773 static __init int mvebu_mbus_debugfs_init(void)
775 struct mvebu_mbus_state *s = &mbus_state;
778 * If no base has been initialized, doesn't make sense to
779 * register the debugfs entries. We may be on a multiplatform
780 * kernel that isn't running a Marvell EBU SoC.
782 if (!s->mbuswins_base)
785 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
786 if (s->debugfs_root) {
787 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
788 s->debugfs_root, NULL,
789 &mvebu_sdram_debug_fops);
790 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
791 s->debugfs_root, NULL,
792 &mvebu_devs_debug_fops);
797 fs_initcall(mvebu_mbus_debugfs_init);
799 static int mvebu_mbus_suspend(void)
801 struct mvebu_mbus_state *s = &mbus_state;
804 if (!s->mbusbridge_base)
807 for (win = 0; win < s->soc->num_wins; win++) {
808 void __iomem *addr = s->mbuswins_base +
809 s->soc->win_cfg_offset(win);
811 s->wins[win].base = readl(addr + WIN_BASE_OFF);
812 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
814 if (win >= s->soc->num_remappable_wins)
817 s->wins[win].remap_lo = readl(addr + WIN_REMAP_LO_OFF);
818 s->wins[win].remap_hi = readl(addr + WIN_REMAP_HI_OFF);
821 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
822 MBUS_BRIDGE_CTRL_OFF);
823 s->mbus_bridge_base = readl(s->mbusbridge_base +
824 MBUS_BRIDGE_BASE_OFF);
829 static void mvebu_mbus_resume(void)
831 struct mvebu_mbus_state *s = &mbus_state;
834 writel(s->mbus_bridge_ctrl,
835 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
836 writel(s->mbus_bridge_base,
837 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
839 for (win = 0; win < s->soc->num_wins; win++) {
840 void __iomem *addr = s->mbuswins_base +
841 s->soc->win_cfg_offset(win);
843 writel(s->wins[win].base, addr + WIN_BASE_OFF);
844 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
846 if (win >= s->soc->num_remappable_wins)
849 writel(s->wins[win].remap_lo, addr + WIN_REMAP_LO_OFF);
850 writel(s->wins[win].remap_hi, addr + WIN_REMAP_HI_OFF);
854 struct syscore_ops mvebu_mbus_syscore_ops = {
855 .suspend = mvebu_mbus_suspend,
856 .resume = mvebu_mbus_resume,
859 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
860 phys_addr_t mbuswins_phys_base,
861 size_t mbuswins_size,
862 phys_addr_t sdramwins_phys_base,
863 size_t sdramwins_size,
864 phys_addr_t mbusbridge_phys_base,
865 size_t mbusbridge_size,
870 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
871 if (!mbus->mbuswins_base)
874 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
875 if (!mbus->sdramwins_base) {
876 iounmap(mbus_state.mbuswins_base);
880 mbus->sdramwins_phys_base = sdramwins_phys_base;
882 if (mbusbridge_phys_base) {
883 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
885 if (!mbus->mbusbridge_base) {
886 iounmap(mbus->sdramwins_base);
887 iounmap(mbus->mbuswins_base);
891 mbus->mbusbridge_base = NULL;
893 for (win = 0; win < mbus->soc->num_wins; win++)
894 mvebu_mbus_disable_window(mbus, win);
896 mbus->soc->setup_cpu_target(mbus);
899 writel(UNIT_SYNC_BARRIER_ALL,
900 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
902 register_syscore_ops(&mvebu_mbus_syscore_ops);
907 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
908 size_t mbuswins_size,
909 phys_addr_t sdramwins_phys_base,
910 size_t sdramwins_size)
912 const struct of_device_id *of_id;
914 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
915 if (!strcmp(of_id->compatible, soc))
918 if (!of_id->compatible[0]) {
919 pr_err("could not find a matching SoC family\n");
923 mbus_state.soc = of_id->data;
925 return mvebu_mbus_common_init(&mbus_state,
929 sdramwins_size, 0, 0, false);
934 * The window IDs in the ranges DT property have the following format:
935 * - bits 28 to 31: MBus custom field
936 * - bits 24 to 27: window target ID
937 * - bits 16 to 23: window attribute ID
938 * - bits 0 to 15: unused
940 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
941 #define TARGET(id) (((id) & 0x0F000000) >> 24)
942 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
944 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
948 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
949 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
954 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
956 pr_err("cannot add window '%04x:%04x', too many windows\n",
964 mbus_parse_ranges(struct device_node *node,
965 int *addr_cells, int *c_addr_cells, int *c_size_cells,
966 int *cell_count, const __be32 **ranges_start,
967 const __be32 **ranges_end)
970 int ranges_len, tuple_len;
972 /* Allow a node with no 'ranges' property */
973 *ranges_start = of_get_property(node, "ranges", &ranges_len);
974 if (*ranges_start == NULL) {
975 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
976 *ranges_start = *ranges_end = NULL;
979 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
981 *addr_cells = of_n_addr_cells(node);
983 prop = of_get_property(node, "#address-cells", NULL);
984 *c_addr_cells = be32_to_cpup(prop);
986 prop = of_get_property(node, "#size-cells", NULL);
987 *c_size_cells = be32_to_cpup(prop);
989 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
990 tuple_len = (*cell_count) * sizeof(__be32);
992 if (ranges_len % tuple_len) {
993 pr_warn("malformed ranges entry '%s'\n", node->name);
999 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1000 struct device_node *np)
1002 int addr_cells, c_addr_cells, c_size_cells;
1003 int i, ret, cell_count;
1004 const __be32 *r, *ranges_start, *ranges_end;
1006 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1007 &c_size_cells, &cell_count,
1008 &ranges_start, &ranges_end);
1012 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1013 u32 windowid, base, size;
1017 * An entry with a non-zero custom field do not
1018 * correspond to a static window, so skip it.
1020 windowid = of_read_number(r, 1);
1021 if (CUSTOM(windowid))
1024 target = TARGET(windowid);
1025 attr = ATTR(windowid);
1027 base = of_read_number(r + c_addr_cells, addr_cells);
1028 size = of_read_number(r + c_addr_cells + addr_cells,
1030 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1037 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1038 struct resource *mem,
1039 struct resource *io)
1045 * These are optional, so we make sure that resource_size(x) will
1048 memset(mem, 0, sizeof(struct resource));
1050 memset(io, 0, sizeof(struct resource));
1053 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1055 mem->start = reg[0];
1056 mem->end = mem->start + reg[1] - 1;
1057 mem->flags = IORESOURCE_MEM;
1060 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1063 io->end = io->start + reg[1] - 1;
1064 io->flags = IORESOURCE_IO;
1068 int __init mvebu_mbus_dt_init(bool is_coherent)
1070 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1071 struct device_node *np, *controller;
1072 const struct of_device_id *of_id;
1076 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1078 pr_err("could not find a matching SoC family\n");
1082 mbus_state.soc = of_id->data;
1084 prop = of_get_property(np, "controller", NULL);
1086 pr_err("required 'controller' property missing\n");
1090 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1092 pr_err("could not find an 'mbus-controller' node\n");
1096 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1097 pr_err("cannot get MBUS register address\n");
1101 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1102 pr_err("cannot get SDRAM register address\n");
1107 * Set the resource to 0 so that it can be left unmapped by
1108 * mvebu_mbus_common_init() if the DT doesn't carry the
1109 * necessary information. This is needed to preserve backward
1112 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1114 if (mbus_state.soc->has_mbus_bridge) {
1115 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1116 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1119 mbus_state.hw_io_coherency = is_coherent;
1121 /* Get optional pcie-{mem,io}-aperture properties */
1122 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1123 &mbus_state.pcie_io_aperture);
1125 ret = mvebu_mbus_common_init(&mbus_state,
1127 resource_size(&mbuswins_res),
1128 sdramwins_res.start,
1129 resource_size(&sdramwins_res),
1130 mbusbridge_res.start,
1131 resource_size(&mbusbridge_res),
1136 /* Setup statically declared windows in the DT */
1137 return mbus_dt_setup(&mbus_state, np);