drivers/bus/omap_l3_noc.h

   1 /*
   2  * OMAP L3 Interconnect  error handling driver header
   3  *
   4  * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *      sricharan <r.sricharan@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #ifndef __OMAP_L3_NOC_H
  18 #define __OMAP_L3_NOC_H
  19
  20 #define L3_MODULES                      3
  21 #define CLEAR_STDERR_LOG                (1 << 31)
  22 #define CUSTOM_ERROR                    0x2
  23 #define STANDARD_ERROR                  0x0
  24 #define INBAND_ERROR                    0x0
  25 #define L3_APPLICATION_ERROR            0x0
  26 #define L3_DEBUG_ERROR                  0x1
  27
  28 /* L3 TARG register offsets */
  29 #define L3_TARG_STDERRLOG_MAIN          0x48
  30 #define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
  31 #define L3_TARG_STDERRLOG_MSTADDR       0x68
  32 #define L3_FLAGMUX_REGERR0              0xc
  33
  34 #define NUM_OF_L3_MASTERS       (sizeof(l3_masters)/sizeof(l3_masters[0]))
  35
  36 /**
  37  * struct l3_masters_data - L3 Master information
  38  * @id:         ID of the L3 Master
  39  * @name:       master name
  40  */
  41 struct l3_masters_data {
  42         u32 id;
  43         char *name;
  44 };
  45
  46 static u32 l3_flagmux[L3_MODULES] = {
  47         0x500,
  48         0x1000,
  49         0X0200
  50 };
  51
  52 /* L3 Target standard Error register offsets */
  53 static u32 l3_targ_inst_clk1[] = {
  54         0x100, /* DMM1 */
  55         0x200, /* DMM2 */
  56         0x300, /* ABE */
  57         0x400, /* L4CFG */
  58         0x600,  /* CLK2 PWR DISC */
  59         0x0,    /* Host CLK1 */
  60         0x900   /* L4 Wakeup */
  61 };
  62
  63 static u32 l3_targ_inst_clk2[] = {
  64         0x500, /* CORTEX M3 */
  65         0x300, /* DSS */
  66         0x100, /* GPMC */
  67         0x400, /* ISS */
  68         0x700, /* IVAHD */
  69         0xD00, /* missing in TRM  corresponds to AES1*/
  70         0x900, /* L4 PER0*/
  71         0x200, /* OCMRAM */
  72         0x100, /* missing in TRM corresponds to GPMC sERROR*/
  73         0x600, /* SGX */
  74         0x800, /* SL2 */
  75         0x1600, /* C2C */
  76         0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
  77         0xF00, /* missing in TRM corrsponds to SHA1*/
  78         0xE00, /* missing in TRM corresponds to AES2*/
  79         0xC00, /* L4 PER3 */
  80         0xA00, /* L4 PER1*/
  81         0xB00, /* L4 PER2*/
  82         0x0, /* HOST CLK2 */
  83         0x1800, /* CAL */
  84         0x1700 /* LLI */
  85 };
  86
  87 static u32 l3_targ_inst_clk3[] = {
  88         0x0100  /* EMUSS */,
  89         0x0300, /* DEBUGSS_CT_TBR */
  90         0x0 /* HOST CLK3 */
  91 };
  92
  93 static struct l3_masters_data l3_masters[] = {
  94         { 0x0 , "MPU"},
  95         { 0x10, "CS_ADP"},
  96         { 0x14, "xxx"},
  97         { 0x20, "DSP"},
  98         { 0x30, "IVAHD"},
  99         { 0x40, "ISS"},
 100         { 0x44, "DucatiM3"},
 101         { 0x48, "FaceDetect"},
 102         { 0x50, "SDMA_Rd"},
 103         { 0x54, "SDMA_Wr"},
 104         { 0x58, "xxx"},
 105         { 0x5C, "xxx"},
 106         { 0x60, "SGX"},
 107         { 0x70, "DSS"},
 108         { 0x80, "C2C"},
 109         { 0x88, "xxx"},
 110         { 0x8C, "xxx"},
 111         { 0x90, "HSI"},
 112         { 0xA0, "MMC1"},
 113         { 0xA4, "MMC2"},
 114         { 0xA8, "MMC6"},
 115         { 0xB0, "UNIPRO1"},
 116         { 0xC0, "USBHOSTHS"},
 117         { 0xC4, "USBOTGHS"},
 118         { 0xC8, "USBHOSTFS"}
 119 };
 120
 121 static char *l3_targ_inst_name[L3_MODULES][21] = {
 122         {
 123                 "DMM1",
 124                 "DMM2",
 125                 "ABE",
 126                 "L4CFG",
 127                 "CLK2 PWR DISC",
 128                 "HOST CLK1",
 129                 "L4 WAKEUP"
 130         },
 131         {
 132                 "CORTEX M3" ,
 133                 "DSS ",
 134                 "GPMC ",
 135                 "ISS ",
 136                 "IVAHD ",
 137                 "AES1",
 138                 "L4 PER0",
 139                 "OCMRAM ",
 140                 "GPMC sERROR",
 141                 "SGX ",
 142                 "SL2 ",
 143                 "C2C ",
 144                 "PWR DISC CLK1",
 145                 "SHA1",
 146                 "AES2",
 147                 "L4 PER3",
 148                 "L4 PER1",
 149                 "L4 PER2",
 150                 "HOST CLK2",
 151                 "CAL",
 152                 "LLI"
 153         },
 154         {
 155                 "EMUSS",
 156                 "DEBUG SOURCE",
 157                 "HOST CLK3"
 158         },
 159 };
 160
 161 static u32 *l3_targ[L3_MODULES] = {
 162         l3_targ_inst_clk1,
 163         l3_targ_inst_clk2,
 164         l3_targ_inst_clk3,
 165 };
 166
 167 struct omap_l3 {
 168         struct device *dev;
 169
 170         /* memory base */
 171         void __iomem *l3_base[L3_MODULES];
 172
 173         int debug_irq;
 174         int app_irq;
 175 };
 176
 177 #endif  /* __OMAP_L3_NOC_H */