1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
101 #define DRIVER_MAJOR 1
102 #define DRIVER_MINOR 27
103 #define DRIVER_PATCHLEVEL 0
106 * Radeon chip families
128 enum radeon_cp_microcode_version {
137 enum radeon_chip_flags {
138 RADEON_FAMILY_MASK = 0x0000ffffUL,
139 RADEON_FLAGS_MASK = 0xffff0000UL,
140 RADEON_IS_MOBILITY = 0x00010000UL,
141 RADEON_IS_IGP = 0x00020000UL,
142 RADEON_SINGLE_CRTC = 0x00040000UL,
143 RADEON_IS_AGP = 0x00080000UL,
144 RADEON_HAS_HIERZ = 0x00100000UL,
145 RADEON_IS_PCIE = 0x00200000UL,
146 RADEON_NEW_MEMMAP = 0x00400000UL,
147 RADEON_IS_PCI = 0x00800000UL,
148 RADEON_IS_IGPGART = 0x01000000UL,
151 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
152 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
153 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
155 typedef struct drm_radeon_freelist {
158 struct drm_radeon_freelist *next;
159 struct drm_radeon_freelist *prev;
160 } drm_radeon_freelist_t;
162 typedef struct drm_radeon_ring_buffer {
173 } drm_radeon_ring_buffer_t;
175 typedef struct drm_radeon_depth_clear_t {
177 u32 rb3d_zstencilcntl;
179 } drm_radeon_depth_clear_t;
181 struct drm_radeon_driver_file_fields {
182 int64_t radeon_fb_delta;
186 struct mem_block *next;
187 struct mem_block *prev;
190 DRMFILE filp; /* 0: free, -1: heap, other: real files */
193 struct radeon_surface {
200 struct radeon_virt_surface {
208 typedef struct drm_radeon_private {
209 drm_radeon_ring_buffer_t ring;
210 drm_radeon_sarea_t *sarea_priv;
218 unsigned long gart_buffers_offset;
223 drm_radeon_freelist_t *head;
224 drm_radeon_freelist_t *tail;
226 volatile u32 *scratch;
231 int microcode_version;
235 int freelist_timeouts;
238 int last_frame_reads;
239 int last_clear_reads;
249 unsigned int front_offset;
250 unsigned int front_pitch;
251 unsigned int back_offset;
252 unsigned int back_pitch;
255 unsigned int depth_offset;
256 unsigned int depth_pitch;
258 u32 front_pitch_offset;
259 u32 back_pitch_offset;
260 u32 depth_pitch_offset;
262 drm_radeon_depth_clear_t depth_clear;
264 unsigned long ring_offset;
265 unsigned long ring_rptr_offset;
266 unsigned long buffers_offset;
267 unsigned long gart_textures_offset;
269 drm_local_map_t *sarea;
270 drm_local_map_t *mmio;
271 drm_local_map_t *cp_ring;
272 drm_local_map_t *ring_rptr;
273 drm_local_map_t *gart_textures;
275 struct mem_block *gart_heap;
276 struct mem_block *fb_heap;
279 wait_queue_head_t swi_queue;
280 atomic_t swi_emitted;
282 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
283 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
285 unsigned long pcigart_offset;
286 unsigned int pcigart_offset_set;
287 drm_ati_pcigart_info gart_info;
291 /* starting from here on, data is preserved accross an open */
292 uint32_t flags; /* see radeon_chip_flags */
293 } drm_radeon_private_t;
295 typedef struct drm_radeon_buf_priv {
297 } drm_radeon_buf_priv_t;
299 typedef struct drm_radeon_kcmd_buffer {
303 drm_clip_rect_t __user *boxes;
304 } drm_radeon_kcmd_buffer_t;
306 extern int radeon_no_wb;
307 extern drm_ioctl_desc_t radeon_ioctls[];
308 extern int radeon_max_ioctl;
310 /* Check whether the given hardware address is inside the framebuffer or the
313 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
316 u32 fb_start = dev_priv->fb_location;
317 u32 fb_end = fb_start + dev_priv->fb_size - 1;
318 u32 gart_start = dev_priv->gart_vm_start;
319 u32 gart_end = gart_start + dev_priv->gart_size - 1;
321 return ((off >= fb_start && off <= fb_end) ||
322 (off >= gart_start && off <= gart_end));
326 extern int radeon_cp_init(DRM_IOCTL_ARGS);
327 extern int radeon_cp_start(DRM_IOCTL_ARGS);
328 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
329 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
330 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
331 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
332 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
333 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
334 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
336 extern void radeon_freelist_reset(drm_device_t * dev);
337 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
339 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
341 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
343 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
344 extern int radeon_presetup(struct drm_device *dev);
345 extern int radeon_driver_postcleanup(struct drm_device *dev);
347 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
348 extern int radeon_mem_free(DRM_IOCTL_ARGS);
349 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
350 extern void radeon_mem_takedown(struct mem_block **heap);
351 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
354 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
355 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
357 extern void radeon_do_release(drm_device_t * dev);
358 extern int radeon_driver_vblank_wait(drm_device_t * dev,
359 unsigned int *sequence);
360 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
361 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
362 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
363 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
365 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
366 extern int radeon_driver_unload(struct drm_device *dev);
367 extern int radeon_driver_firstopen(struct drm_device *dev);
368 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
369 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
370 extern void radeon_driver_lastclose(drm_device_t * dev);
371 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
372 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
376 extern void r300_init_reg_flags(void);
378 extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
379 drm_file_t * filp_priv,
380 drm_radeon_kcmd_buffer_t * cmdbuf);
382 /* Flags for stats.boxes
384 #define RADEON_BOX_DMA_IDLE 0x1
385 #define RADEON_BOX_RING_FULL 0x2
386 #define RADEON_BOX_FLIP 0x4
387 #define RADEON_BOX_WAIT_IDLE 0x8
388 #define RADEON_BOX_TEXTURE_LOAD 0x10
390 /* Register definitions, register access macros and drmAddMap constants
391 * for Radeon kernel driver.
394 #define RADEON_AGP_COMMAND 0x0f60
395 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
396 # define RADEON_AGP_ENABLE (1<<8)
397 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
398 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
399 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
400 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
401 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
402 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
403 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
405 #define RADEON_BUS_CNTL 0x0030
406 # define RADEON_BUS_MASTER_DIS (1 << 6)
408 #define RADEON_CLOCK_CNTL_DATA 0x000c
409 # define RADEON_PLL_WR_EN (1 << 7)
410 #define RADEON_CLOCK_CNTL_INDEX 0x0008
411 #define RADEON_CONFIG_APER_SIZE 0x0108
412 #define RADEON_CONFIG_MEMSIZE 0x00f8
413 #define RADEON_CRTC_OFFSET 0x0224
414 #define RADEON_CRTC_OFFSET_CNTL 0x0228
415 # define RADEON_CRTC_TILE_EN (1 << 15)
416 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
417 #define RADEON_CRTC2_OFFSET 0x0324
418 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
420 #define RADEON_PCIE_INDEX 0x0030
421 #define RADEON_PCIE_DATA 0x0034
422 #define RADEON_PCIE_TX_GART_CNTL 0x10
423 # define RADEON_PCIE_TX_GART_EN (1 << 0)
424 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
425 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
426 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
427 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
428 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
429 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
430 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
431 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
432 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
433 #define RADEON_PCIE_TX_GART_BASE 0x13
434 #define RADEON_PCIE_TX_GART_START_LO 0x14
435 #define RADEON_PCIE_TX_GART_START_HI 0x15
436 #define RADEON_PCIE_TX_GART_END_LO 0x16
437 #define RADEON_PCIE_TX_GART_END_HI 0x17
439 #define RADEON_IGPGART_INDEX 0x168
440 #define RADEON_IGPGART_DATA 0x16c
441 #define RADEON_IGPGART_UNK_18 0x18
442 #define RADEON_IGPGART_CTRL 0x2b
443 #define RADEON_IGPGART_BASE_ADDR 0x2c
444 #define RADEON_IGPGART_FLUSH 0x2e
445 #define RADEON_IGPGART_ENABLE 0x38
446 #define RADEON_IGPGART_UNK_39 0x39
448 #define RADEON_MPP_TB_CONFIG 0x01c0
449 #define RADEON_MEM_CNTL 0x0140
450 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
451 #define RADEON_AGP_BASE 0x0170
453 #define RADEON_RB3D_COLOROFFSET 0x1c40
454 #define RADEON_RB3D_COLORPITCH 0x1c48
456 #define RADEON_SRC_X_Y 0x1590
458 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
459 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
460 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
461 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
462 # define RADEON_GMC_BRUSH_NONE (15 << 4)
463 # define RADEON_GMC_DST_16BPP (4 << 8)
464 # define RADEON_GMC_DST_24BPP (5 << 8)
465 # define RADEON_GMC_DST_32BPP (6 << 8)
466 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
467 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
468 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
469 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
470 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
471 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
472 # define RADEON_ROP3_S 0x00cc0000
473 # define RADEON_ROP3_P 0x00f00000
474 #define RADEON_DP_WRITE_MASK 0x16cc
475 #define RADEON_SRC_PITCH_OFFSET 0x1428
476 #define RADEON_DST_PITCH_OFFSET 0x142c
477 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
478 # define RADEON_DST_TILE_LINEAR (0 << 30)
479 # define RADEON_DST_TILE_MACRO (1 << 30)
480 # define RADEON_DST_TILE_MICRO (2 << 30)
481 # define RADEON_DST_TILE_BOTH (3 << 30)
483 #define RADEON_SCRATCH_REG0 0x15e0
484 #define RADEON_SCRATCH_REG1 0x15e4
485 #define RADEON_SCRATCH_REG2 0x15e8
486 #define RADEON_SCRATCH_REG3 0x15ec
487 #define RADEON_SCRATCH_REG4 0x15f0
488 #define RADEON_SCRATCH_REG5 0x15f4
489 #define RADEON_SCRATCH_UMSK 0x0770
490 #define RADEON_SCRATCH_ADDR 0x0774
492 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
494 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
495 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
496 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
498 #define RADEON_GEN_INT_CNTL 0x0040
499 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
500 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
501 # define RADEON_SW_INT_ENABLE (1 << 25)
503 #define RADEON_GEN_INT_STATUS 0x0044
504 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
505 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
506 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
507 # define RADEON_SW_INT_TEST (1 << 25)
508 # define RADEON_SW_INT_TEST_ACK (1 << 25)
509 # define RADEON_SW_INT_FIRE (1 << 26)
511 #define RADEON_HOST_PATH_CNTL 0x0130
512 # define RADEON_HDP_SOFT_RESET (1 << 26)
513 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
514 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
516 #define RADEON_ISYNC_CNTL 0x1724
517 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
518 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
519 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
520 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
521 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
522 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
524 #define RADEON_RBBM_GUICNTL 0x172c
525 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
526 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
527 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
528 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
530 #define RADEON_MC_AGP_LOCATION 0x014c
531 #define RADEON_MC_FB_LOCATION 0x0148
532 #define RADEON_MCLK_CNTL 0x0012
533 # define RADEON_FORCEON_MCLKA (1 << 16)
534 # define RADEON_FORCEON_MCLKB (1 << 17)
535 # define RADEON_FORCEON_YCLKA (1 << 18)
536 # define RADEON_FORCEON_YCLKB (1 << 19)
537 # define RADEON_FORCEON_MC (1 << 20)
538 # define RADEON_FORCEON_AIC (1 << 21)
540 #define RADEON_PP_BORDER_COLOR_0 0x1d40
541 #define RADEON_PP_BORDER_COLOR_1 0x1d44
542 #define RADEON_PP_BORDER_COLOR_2 0x1d48
543 #define RADEON_PP_CNTL 0x1c38
544 # define RADEON_SCISSOR_ENABLE (1 << 1)
545 #define RADEON_PP_LUM_MATRIX 0x1d00
546 #define RADEON_PP_MISC 0x1c14
547 #define RADEON_PP_ROT_MATRIX_0 0x1d58
548 #define RADEON_PP_TXFILTER_0 0x1c54
549 #define RADEON_PP_TXOFFSET_0 0x1c5c
550 #define RADEON_PP_TXFILTER_1 0x1c6c
551 #define RADEON_PP_TXFILTER_2 0x1c84
553 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
554 # define RADEON_RB2D_DC_FLUSH (3 << 0)
555 # define RADEON_RB2D_DC_FREE (3 << 2)
556 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
557 # define RADEON_RB2D_DC_BUSY (1 << 31)
558 #define RADEON_RB3D_CNTL 0x1c3c
559 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
560 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
561 # define RADEON_DITHER_ENABLE (1 << 2)
562 # define RADEON_ROUND_ENABLE (1 << 3)
563 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
564 # define RADEON_DITHER_INIT (1 << 5)
565 # define RADEON_ROP_ENABLE (1 << 6)
566 # define RADEON_STENCIL_ENABLE (1 << 7)
567 # define RADEON_Z_ENABLE (1 << 8)
568 # define RADEON_ZBLOCK16 (1 << 15)
569 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
570 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
571 #define RADEON_RB3D_DEPTHPITCH 0x1c28
572 #define RADEON_RB3D_PLANEMASK 0x1d84
573 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
574 #define RADEON_RB3D_ZCACHE_MODE 0x3250
575 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
576 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
577 # define RADEON_RB3D_ZC_FREE (1 << 2)
578 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
579 # define RADEON_RB3D_ZC_BUSY (1 << 31)
580 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
581 # define RADEON_RB3D_DC_FLUSH (3 << 0)
582 # define RADEON_RB3D_DC_FREE (3 << 2)
583 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
584 # define RADEON_RB3D_DC_BUSY (1 << 31)
585 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
586 # define RADEON_Z_TEST_MASK (7 << 4)
587 # define RADEON_Z_TEST_ALWAYS (7 << 4)
588 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
589 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
590 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
591 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
592 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
593 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
594 # define RADEON_FORCE_Z_DIRTY (1 << 29)
595 # define RADEON_Z_WRITE_ENABLE (1 << 30)
596 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
597 #define RADEON_RBBM_SOFT_RESET 0x00f0
598 # define RADEON_SOFT_RESET_CP (1 << 0)
599 # define RADEON_SOFT_RESET_HI (1 << 1)
600 # define RADEON_SOFT_RESET_SE (1 << 2)
601 # define RADEON_SOFT_RESET_RE (1 << 3)
602 # define RADEON_SOFT_RESET_PP (1 << 4)
603 # define RADEON_SOFT_RESET_E2 (1 << 5)
604 # define RADEON_SOFT_RESET_RB (1 << 6)
605 # define RADEON_SOFT_RESET_HDP (1 << 7)
606 #define RADEON_RBBM_STATUS 0x0e40
607 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
608 # define RADEON_RBBM_ACTIVE (1 << 31)
609 #define RADEON_RE_LINE_PATTERN 0x1cd0
610 #define RADEON_RE_MISC 0x26c4
611 #define RADEON_RE_TOP_LEFT 0x26c0
612 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
613 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
614 #define RADEON_RE_STIPPLE_DATA 0x1ccc
616 #define RADEON_SCISSOR_TL_0 0x1cd8
617 #define RADEON_SCISSOR_BR_0 0x1cdc
618 #define RADEON_SCISSOR_TL_1 0x1ce0
619 #define RADEON_SCISSOR_BR_1 0x1ce4
620 #define RADEON_SCISSOR_TL_2 0x1ce8
621 #define RADEON_SCISSOR_BR_2 0x1cec
622 #define RADEON_SE_COORD_FMT 0x1c50
623 #define RADEON_SE_CNTL 0x1c4c
624 # define RADEON_FFACE_CULL_CW (0 << 0)
625 # define RADEON_BFACE_SOLID (3 << 1)
626 # define RADEON_FFACE_SOLID (3 << 3)
627 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
628 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
629 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
630 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
631 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
632 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
633 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
634 # define RADEON_FOG_SHADE_FLAT (1 << 14)
635 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
636 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
637 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
638 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
639 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
640 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
641 #define RADEON_SE_CNTL_STATUS 0x2140
642 #define RADEON_SE_LINE_WIDTH 0x1db8
643 #define RADEON_SE_VPORT_XSCALE 0x1d98
644 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
645 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
646 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
647 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
648 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
649 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
650 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
651 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
652 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
653 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
654 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
655 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
656 #define RADEON_SURFACE_CNTL 0x0b00
657 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
658 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
659 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
660 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
661 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
662 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
663 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
664 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
665 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
666 #define RADEON_SURFACE0_INFO 0x0b0c
667 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
668 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
669 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
670 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
671 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
672 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
673 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
674 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
675 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
676 #define RADEON_SURFACE1_INFO 0x0b1c
677 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
678 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
679 #define RADEON_SURFACE2_INFO 0x0b2c
680 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
681 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
682 #define RADEON_SURFACE3_INFO 0x0b3c
683 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
684 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
685 #define RADEON_SURFACE4_INFO 0x0b4c
686 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
687 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
688 #define RADEON_SURFACE5_INFO 0x0b5c
689 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
690 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
691 #define RADEON_SURFACE6_INFO 0x0b6c
692 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
693 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
694 #define RADEON_SURFACE7_INFO 0x0b7c
695 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
696 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
697 #define RADEON_SW_SEMAPHORE 0x013c
699 #define RADEON_WAIT_UNTIL 0x1720
700 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
701 # define RADEON_WAIT_2D_IDLE (1 << 14)
702 # define RADEON_WAIT_3D_IDLE (1 << 15)
703 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
704 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
705 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
707 #define RADEON_RB3D_ZMASKOFFSET 0x3234
708 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
709 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
710 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
713 #define RADEON_CP_ME_RAM_ADDR 0x07d4
714 #define RADEON_CP_ME_RAM_RADDR 0x07d8
715 #define RADEON_CP_ME_RAM_DATAH 0x07dc
716 #define RADEON_CP_ME_RAM_DATAL 0x07e0
718 #define RADEON_CP_RB_BASE 0x0700
719 #define RADEON_CP_RB_CNTL 0x0704
720 # define RADEON_BUF_SWAP_32BIT (2 << 16)
721 # define RADEON_RB_NO_UPDATE (1 << 27)
722 #define RADEON_CP_RB_RPTR_ADDR 0x070c
723 #define RADEON_CP_RB_RPTR 0x0710
724 #define RADEON_CP_RB_WPTR 0x0714
726 #define RADEON_CP_RB_WPTR_DELAY 0x0718
727 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
728 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
730 #define RADEON_CP_IB_BASE 0x0738
732 #define RADEON_CP_CSQ_CNTL 0x0740
733 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
734 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
735 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
736 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
737 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
738 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
739 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
741 #define RADEON_AIC_CNTL 0x01d0
742 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
743 #define RADEON_AIC_STAT 0x01d4
744 #define RADEON_AIC_PT_BASE 0x01d8
745 #define RADEON_AIC_LO_ADDR 0x01dc
746 #define RADEON_AIC_HI_ADDR 0x01e0
747 #define RADEON_AIC_TLB_ADDR 0x01e4
748 #define RADEON_AIC_TLB_DATA 0x01e8
750 /* CP command packets */
751 #define RADEON_CP_PACKET0 0x00000000
752 # define RADEON_ONE_REG_WR (1 << 15)
753 #define RADEON_CP_PACKET1 0x40000000
754 #define RADEON_CP_PACKET2 0x80000000
755 #define RADEON_CP_PACKET3 0xC0000000
756 # define RADEON_CP_NOP 0x00001000
757 # define RADEON_CP_NEXT_CHAR 0x00001900
758 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
759 # define RADEON_CP_SET_SCISSORS 0x00001E00
760 /* GEN_INDX_PRIM is unsupported starting with R300 */
761 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
762 # define RADEON_WAIT_FOR_IDLE 0x00002600
763 # define RADEON_3D_DRAW_VBUF 0x00002800
764 # define RADEON_3D_DRAW_IMMD 0x00002900
765 # define RADEON_3D_DRAW_INDX 0x00002A00
766 # define RADEON_CP_LOAD_PALETTE 0x00002C00
767 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
768 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
769 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
770 # define RADEON_3D_CLEAR_ZMASK 0x00003200
771 # define RADEON_CP_INDX_BUFFER 0x00003300
772 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
773 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
774 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
775 # define RADEON_3D_CLEAR_HIZ 0x00003700
776 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
777 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
778 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
779 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
780 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
782 #define RADEON_CP_PACKET_MASK 0xC0000000
783 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
784 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
785 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
786 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
788 #define RADEON_VTX_Z_PRESENT (1 << 31)
789 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
791 #define RADEON_PRIM_TYPE_NONE (0 << 0)
792 #define RADEON_PRIM_TYPE_POINT (1 << 0)
793 #define RADEON_PRIM_TYPE_LINE (2 << 0)
794 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
795 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
796 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
797 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
798 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
799 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
800 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
801 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
802 #define RADEON_PRIM_TYPE_MASK 0xf
803 #define RADEON_PRIM_WALK_IND (1 << 4)
804 #define RADEON_PRIM_WALK_LIST (2 << 4)
805 #define RADEON_PRIM_WALK_RING (3 << 4)
806 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
807 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
808 #define RADEON_MAOS_ENABLE (1 << 7)
809 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
810 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
811 #define RADEON_NUM_VERTICES_SHIFT 16
813 #define RADEON_COLOR_FORMAT_CI8 2
814 #define RADEON_COLOR_FORMAT_ARGB1555 3
815 #define RADEON_COLOR_FORMAT_RGB565 4
816 #define RADEON_COLOR_FORMAT_ARGB8888 6
817 #define RADEON_COLOR_FORMAT_RGB332 7
818 #define RADEON_COLOR_FORMAT_RGB8 9
819 #define RADEON_COLOR_FORMAT_ARGB4444 15
821 #define RADEON_TXFORMAT_I8 0
822 #define RADEON_TXFORMAT_AI88 1
823 #define RADEON_TXFORMAT_RGB332 2
824 #define RADEON_TXFORMAT_ARGB1555 3
825 #define RADEON_TXFORMAT_RGB565 4
826 #define RADEON_TXFORMAT_ARGB4444 5
827 #define RADEON_TXFORMAT_ARGB8888 6
828 #define RADEON_TXFORMAT_RGBA8888 7
829 #define RADEON_TXFORMAT_Y8 8
830 #define RADEON_TXFORMAT_VYUY422 10
831 #define RADEON_TXFORMAT_YVYU422 11
832 #define RADEON_TXFORMAT_DXT1 12
833 #define RADEON_TXFORMAT_DXT23 14
834 #define RADEON_TXFORMAT_DXT45 15
836 #define R200_PP_TXCBLEND_0 0x2f00
837 #define R200_PP_TXCBLEND_1 0x2f10
838 #define R200_PP_TXCBLEND_2 0x2f20
839 #define R200_PP_TXCBLEND_3 0x2f30
840 #define R200_PP_TXCBLEND_4 0x2f40
841 #define R200_PP_TXCBLEND_5 0x2f50
842 #define R200_PP_TXCBLEND_6 0x2f60
843 #define R200_PP_TXCBLEND_7 0x2f70
844 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
845 #define R200_PP_TFACTOR_0 0x2ee0
846 #define R200_SE_VTX_FMT_0 0x2088
847 #define R200_SE_VAP_CNTL 0x2080
848 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
849 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
850 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
851 #define R200_PP_TXFILTER_5 0x2ca0
852 #define R200_PP_TXFILTER_4 0x2c80
853 #define R200_PP_TXFILTER_3 0x2c60
854 #define R200_PP_TXFILTER_2 0x2c40
855 #define R200_PP_TXFILTER_1 0x2c20
856 #define R200_PP_TXFILTER_0 0x2c00
857 #define R200_PP_TXOFFSET_5 0x2d78
858 #define R200_PP_TXOFFSET_4 0x2d60
859 #define R200_PP_TXOFFSET_3 0x2d48
860 #define R200_PP_TXOFFSET_2 0x2d30
861 #define R200_PP_TXOFFSET_1 0x2d18
862 #define R200_PP_TXOFFSET_0 0x2d00
864 #define R200_PP_CUBIC_FACES_0 0x2c18
865 #define R200_PP_CUBIC_FACES_1 0x2c38
866 #define R200_PP_CUBIC_FACES_2 0x2c58
867 #define R200_PP_CUBIC_FACES_3 0x2c78
868 #define R200_PP_CUBIC_FACES_4 0x2c98
869 #define R200_PP_CUBIC_FACES_5 0x2cb8
870 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
871 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
872 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
873 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
874 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
875 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
876 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
877 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
878 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
879 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
880 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
881 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
882 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
883 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
884 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
885 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
886 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
887 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
888 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
889 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
890 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
891 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
892 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
893 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
894 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
895 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
896 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
897 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
898 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
899 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
901 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
902 #define R200_SE_VTE_CNTL 0x20b0
903 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
904 #define R200_PP_TAM_DEBUG3 0x2d9c
905 #define R200_PP_CNTL_X 0x2cc4
906 #define R200_SE_VAP_CNTL_STATUS 0x2140
907 #define R200_RE_SCISSOR_TL_0 0x1cd8
908 #define R200_RE_SCISSOR_TL_1 0x1ce0
909 #define R200_RE_SCISSOR_TL_2 0x1ce8
910 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
911 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
912 #define R200_SE_VTX_STATE_CNTL 0x2180
913 #define R200_RE_POINTSIZE 0x2648
914 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
916 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
917 #define RADEON_PP_TEX_SIZE_1 0x1d0c
918 #define RADEON_PP_TEX_SIZE_2 0x1d14
920 #define RADEON_PP_CUBIC_FACES_0 0x1d24
921 #define RADEON_PP_CUBIC_FACES_1 0x1d28
922 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
923 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
924 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
925 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
927 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
929 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
930 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
931 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
932 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
933 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
934 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
935 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
936 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
937 #define R200_3D_DRAW_IMMD_2 0xC0003500
938 #define R200_SE_VTX_FMT_1 0x208c
939 #define R200_RE_CNTL 0x1c50
941 #define R200_RB3D_BLENDCOLOR 0x3218
943 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
945 #define R200_PP_TRI_PERF 0x2cf8
947 #define R200_PP_AFS_0 0x2f80
948 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
950 #define R200_VAP_PVS_CNTL_1 0x22D0
953 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
955 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
956 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
957 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
958 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
959 #define RADEON_LAST_DISPATCH 1
961 #define RADEON_MAX_VB_AGE 0x7fffffff
962 #define RADEON_MAX_VB_VERTS (0xffff)
964 #define RADEON_RING_HIGH_MARK 128
966 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
968 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
969 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
970 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
971 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
973 #define RADEON_WRITE_PLL( addr, val ) \
975 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
976 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
977 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
980 #define RADEON_WRITE_IGPGART( addr, val ) \
982 RADEON_WRITE( RADEON_IGPGART_INDEX, \
983 ((addr) & 0x7f) | (1 << 8)); \
984 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
985 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
988 #define RADEON_WRITE_PCIE( addr, val ) \
990 RADEON_WRITE8( RADEON_PCIE_INDEX, \
992 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
995 #define CP_PACKET0( reg, n ) \
996 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
997 #define CP_PACKET0_TABLE( reg, n ) \
998 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
999 #define CP_PACKET1( reg0, reg1 ) \
1000 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1001 #define CP_PACKET2() \
1003 #define CP_PACKET3( pkt, n ) \
1004 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1006 /* ================================================================
1007 * Engine control helper macros
1010 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1011 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1012 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1013 RADEON_WAIT_HOST_IDLECLEAN) ); \
1016 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1017 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1018 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1019 RADEON_WAIT_HOST_IDLECLEAN) ); \
1022 #define RADEON_WAIT_UNTIL_IDLE() do { \
1023 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1024 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1025 RADEON_WAIT_3D_IDLECLEAN | \
1026 RADEON_WAIT_HOST_IDLECLEAN) ); \
1029 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1030 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1031 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1034 #define RADEON_FLUSH_CACHE() do { \
1035 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1036 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1039 #define RADEON_PURGE_CACHE() do { \
1040 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1041 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1044 #define RADEON_FLUSH_ZCACHE() do { \
1045 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1046 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1049 #define RADEON_PURGE_ZCACHE() do { \
1050 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1051 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1054 /* ================================================================
1055 * Misc helper macros
1058 /* Perfbox functionality only.
1060 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1062 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1063 u32 head = GET_RING_HEAD( dev_priv ); \
1064 if (head == dev_priv->ring.tail) \
1065 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1069 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1071 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1072 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1073 int __ret = radeon_do_cp_idle( dev_priv ); \
1074 if ( __ret ) return __ret; \
1075 sarea_priv->last_dispatch = 0; \
1076 radeon_freelist_reset( dev ); \
1080 #define RADEON_DISPATCH_AGE( age ) do { \
1081 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1085 #define RADEON_FRAME_AGE( age ) do { \
1086 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1090 #define RADEON_CLEAR_AGE( age ) do { \
1091 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1095 /* ================================================================
1099 #define RADEON_VERBOSE 0
1101 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1103 #define BEGIN_RING( n ) do { \
1104 if ( RADEON_VERBOSE ) { \
1105 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1106 n, __FUNCTION__ ); \
1108 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1110 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1112 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1113 ring = dev_priv->ring.start; \
1114 write = dev_priv->ring.tail; \
1115 mask = dev_priv->ring.tail_mask; \
1118 #define ADVANCE_RING() do { \
1119 if ( RADEON_VERBOSE ) { \
1120 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1121 write, dev_priv->ring.tail ); \
1123 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1125 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1126 ((dev_priv->ring.tail + _nr) & mask), \
1129 dev_priv->ring.tail = write; \
1132 #define COMMIT_RING() do { \
1133 /* Flush writes to ring */ \
1134 DRM_MEMORYBARRIER(); \
1135 GET_RING_HEAD( dev_priv ); \
1136 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1137 /* read from PCI bus to ensure correct posting */ \
1138 RADEON_READ( RADEON_CP_RB_RPTR ); \
1141 #define OUT_RING( x ) do { \
1142 if ( RADEON_VERBOSE ) { \
1143 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1144 (unsigned int)(x), write ); \
1146 ring[write++] = (x); \
1150 #define OUT_RING_REG( reg, val ) do { \
1151 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1155 #define OUT_RING_TABLE( tab, sz ) do { \
1157 int *_tab = (int *)(tab); \
1159 if (write + _size > mask) { \
1160 int _i = (mask+1) - write; \
1163 *(int *)(ring + write) = *_tab++; \
1170 while (_size > 0) { \
1171 *(ring + write) = *_tab++; \
1178 #endif /* __RADEON_DRV_H__ */