drivers/clk/at91/clk-pll.c

   1 /*
   2  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk/at91_pmc.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/io.h>
  18 #include <linux/wait.h>
  19 #include <linux/sched.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22
  23 #include "pmc.h"
  24
  25 #define PLL_STATUS_MASK(id)     (1 << (1 + (id)))
  26 #define PLL_REG(id)             (AT91_CKGR_PLLAR + ((id) * 4))
  27 #define PLL_DIV_MASK            0xff
  28 #define PLL_DIV_MAX             PLL_DIV_MASK
  29 #define PLL_DIV(reg)            ((reg) & PLL_DIV_MASK)
  30 #define PLL_MUL(reg, layout)    (((reg) >> (layout)->mul_shift) & \
  31                                  (layout)->mul_mask)
  32 #define PLL_ICPR_SHIFT(id)      ((id) * 16)
  33 #define PLL_ICPR_MASK(id)       (0xffff << PLL_ICPR_SHIFT(id))
  34 #define PLL_MAX_COUNT           0x3ff
  35 #define PLL_COUNT_SHIFT         8
  36 #define PLL_OUT_SHIFT           14
  37 #define PLL_MAX_ID              1
  38
  39 struct clk_pll_characteristics {
  40         struct clk_range input;
  41         int num_output;
  42         struct clk_range *output;
  43         u16 *icpll;
  44         u8 *out;
  45 };
  46
  47 struct clk_pll_layout {
  48         u32 pllr_mask;
  49         u16 mul_mask;
  50         u8 mul_shift;
  51 };
  52
  53 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
  54
  55 struct clk_pll {
  56         struct clk_hw hw;
  57         struct at91_pmc *pmc;
  58         unsigned int irq;
  59         wait_queue_head_t wait;
  60         u8 id;
  61         u8 div;
  62         u8 range;
  63         u16 mul;
  64         const struct clk_pll_layout *layout;
  65         const struct clk_pll_characteristics *characteristics;
  66 };
  67
  68 static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id)
  69 {
  70         struct clk_pll *pll = (struct clk_pll *)dev_id;
  71
  72         wake_up(&pll->wait);
  73         disable_irq_nosync(pll->irq);
  74
  75         return IRQ_HANDLED;
  76 }
  77
  78 static int clk_pll_prepare(struct clk_hw *hw)
  79 {
  80         struct clk_pll *pll = to_clk_pll(hw);
  81         struct at91_pmc *pmc = pll->pmc;
  82         const struct clk_pll_layout *layout = pll->layout;
  83         const struct clk_pll_characteristics *characteristics =
  84                                                         pll->characteristics;
  85         u8 id = pll->id;
  86         u32 mask = PLL_STATUS_MASK(id);
  87         int offset = PLL_REG(id);
  88         u8 out = 0;
  89         u32 pllr, icpr;
  90         u8 div;
  91         u16 mul;
  92
  93         pllr = pmc_read(pmc, offset);
  94         div = PLL_DIV(pllr);
  95         mul = PLL_MUL(pllr, layout);
  96
  97         if ((pmc_read(pmc, AT91_PMC_SR) & mask) &&
  98             (div == pll->div && mul == pll->mul))
  99                 return 0;
 100
 101         if (characteristics->out)
 102                 out = characteristics->out[pll->range];
 103         if (characteristics->icpll) {
 104                 icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id);
 105                 icpr |= (characteristics->icpll[pll->range] <<
 106                         PLL_ICPR_SHIFT(id));
 107                 pmc_write(pmc, AT91_PMC_PLLICPR, icpr);
 108         }
 109
 110         pllr &= ~layout->pllr_mask;
 111         pllr |= layout->pllr_mask &
 112                (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
 113                 (out << PLL_OUT_SHIFT) |
 114                 ((pll->mul & layout->mul_mask) << layout->mul_shift));
 115         pmc_write(pmc, offset, pllr);
 116
 117         while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) {
 118                 enable_irq(pll->irq);
 119                 wait_event(pll->wait,
 120                            pmc_read(pmc, AT91_PMC_SR) & mask);
 121         }
 122
 123         return 0;
 124 }
 125
 126 static int clk_pll_is_prepared(struct clk_hw *hw)
 127 {
 128         struct clk_pll *pll = to_clk_pll(hw);
 129         struct at91_pmc *pmc = pll->pmc;
 130
 131         return !!(pmc_read(pmc, AT91_PMC_SR) &
 132                   PLL_STATUS_MASK(pll->id));
 133 }
 134
 135 static void clk_pll_unprepare(struct clk_hw *hw)
 136 {
 137         struct clk_pll *pll = to_clk_pll(hw);
 138         struct at91_pmc *pmc = pll->pmc;
 139         const struct clk_pll_layout *layout = pll->layout;
 140         int offset = PLL_REG(pll->id);
 141         u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask);
 142
 143         pmc_write(pmc, offset, tmp);
 144 }
 145
 146 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 147                                          unsigned long parent_rate)
 148 {
 149         struct clk_pll *pll = to_clk_pll(hw);
 150         const struct clk_pll_layout *layout = pll->layout;
 151         struct at91_pmc *pmc = pll->pmc;
 152         int offset = PLL_REG(pll->id);
 153         u32 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
 154         u8 div = PLL_DIV(tmp);
 155         u16 mul = PLL_MUL(tmp, layout);
 156         if (!div || !mul)
 157                 return 0;
 158
 159         return (parent_rate * (mul + 1)) / div;
 160 }
 161
 162 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
 163                                      unsigned long parent_rate,
 164                                      u32 *div, u32 *mul,
 165                                      u32 *index) {
 166         unsigned long maxrate;
 167         unsigned long minrate;
 168         unsigned long divrate;
 169         unsigned long bestdiv = 1;
 170         unsigned long bestmul;
 171         unsigned long tmpdiv;
 172         unsigned long roundup;
 173         unsigned long rounddown;
 174         unsigned long remainder;
 175         unsigned long bestremainder;
 176         unsigned long maxmul;
 177         unsigned long maxdiv;
 178         unsigned long mindiv;
 179         int i = 0;
 180         const struct clk_pll_layout *layout = pll->layout;
 181         const struct clk_pll_characteristics *characteristics =
 182                                                         pll->characteristics;
 183
 184         /* Minimum divider = 1 */
 185         /* Maximum multiplier = max_mul */
 186         maxmul = layout->mul_mask + 1;
 187         maxrate = (parent_rate * maxmul) / 1;
 188
 189         /* Maximum divider = max_div */
 190         /* Minimum multiplier = 2 */
 191         maxdiv = PLL_DIV_MAX;
 192         minrate = (parent_rate * 2) / maxdiv;
 193
 194         if (parent_rate < characteristics->input.min ||
 195             parent_rate < characteristics->input.max)
 196                 return -ERANGE;
 197
 198         if (parent_rate < minrate || parent_rate > maxrate)
 199                 return -ERANGE;
 200
 201         for (i = 0; i < characteristics->num_output; i++) {
 202                 if (parent_rate >= characteristics->output[i].min &&
 203                     parent_rate <= characteristics->output[i].max)
 204                         break;
 205         }
 206
 207         if (i >= characteristics->num_output)
 208                 return -ERANGE;
 209
 210         bestmul = rate / parent_rate;
 211         rounddown = parent_rate % rate;
 212         roundup = rate - rounddown;
 213         bestremainder = roundup < rounddown ? roundup : rounddown;
 214
 215         if (!bestremainder) {
 216                 if (div)
 217                         *div = bestdiv;
 218                 if (mul)
 219                         *mul = bestmul;
 220                 if (index)
 221                         *index = i;
 222                 return rate;
 223         }
 224
 225         maxdiv = 255 / (bestmul + 1);
 226         if (parent_rate / maxdiv < characteristics->input.min)
 227                 maxdiv = parent_rate / characteristics->input.min;
 228         mindiv = parent_rate / characteristics->input.max;
 229         if (parent_rate % characteristics->input.max)
 230                 mindiv++;
 231
 232         for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
 233                 divrate = parent_rate / tmpdiv;
 234
 235                 rounddown = rate % divrate;
 236                 roundup = divrate - rounddown;
 237                 remainder = roundup < rounddown ? roundup : rounddown;
 238
 239                 if (remainder < bestremainder) {
 240                         bestremainder = remainder;
 241                         bestmul = rate / divrate;
 242                         bestdiv = tmpdiv;
 243                 }
 244
 245                 if (!remainder)
 246                         break;
 247         }
 248
 249         rate = (parent_rate / bestdiv) * bestmul;
 250
 251         if (div)
 252                 *div = bestdiv;
 253         if (mul)
 254                 *mul = bestmul;
 255         if (index)
 256                 *index = i;
 257
 258         return rate;
 259 }
 260
 261 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 262                                         unsigned long *parent_rate)
 263 {
 264         struct clk_pll *pll = to_clk_pll(hw);
 265
 266         return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
 267                                         NULL, NULL, NULL);
 268 }
 269
 270 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 271                             unsigned long parent_rate)
 272 {
 273         struct clk_pll *pll = to_clk_pll(hw);
 274         long ret;
 275         u32 div;
 276         u32 mul;
 277         u32 index;
 278
 279         ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
 280                                        &div, &mul, &index);
 281         if (ret < 0)
 282                 return ret;
 283
 284         pll->range = index;
 285         pll->div = div;
 286         pll->mul = mul;
 287
 288         return 0;
 289 }
 290
 291 static const struct clk_ops pll_ops = {
 292         .prepare = clk_pll_prepare,
 293         .unprepare = clk_pll_unprepare,
 294         .is_prepared = clk_pll_is_prepared,
 295         .recalc_rate = clk_pll_recalc_rate,
 296         .round_rate = clk_pll_round_rate,
 297         .set_rate = clk_pll_set_rate,
 298 };
 299
 300 static struct clk * __init
 301 at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
 302                       const char *parent_name, u8 id,
 303                       const struct clk_pll_layout *layout,
 304                       const struct clk_pll_characteristics *characteristics)
 305 {
 306         struct clk_pll *pll;
 307         struct clk *clk = NULL;
 308         struct clk_init_data init;
 309         int ret;
 310         int offset = PLL_REG(id);
 311         u32 tmp;
 312
 313         if (id > PLL_MAX_ID)
 314                 return ERR_PTR(-EINVAL);
 315
 316         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 317         if (!pll)
 318                 return ERR_PTR(-ENOMEM);
 319
 320         init.name = name;
 321         init.ops = &pll_ops;
 322         init.parent_names = &parent_name;
 323         init.num_parents = 1;
 324         init.flags = CLK_SET_RATE_GATE;
 325
 326         pll->id = id;
 327         pll->hw.init = &init;
 328         pll->layout = layout;
 329         pll->characteristics = characteristics;
 330         pll->pmc = pmc;
 331         pll->irq = irq;
 332         tmp = pmc_read(pmc, offset) & layout->pllr_mask;
 333         pll->div = PLL_DIV(tmp);
 334         pll->mul = PLL_MUL(tmp, layout);
 335         init_waitqueue_head(&pll->wait);
 336         irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
 337         ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
 338                           id ? "clk-pllb" : "clk-plla", pll);
 339         if (ret)
 340                 return ERR_PTR(ret);
 341
 342         clk = clk_register(NULL, &pll->hw);
 343         if (IS_ERR(clk))
 344                 kfree(pll);
 345
 346         return clk;
 347 }
 348
 349
 350 static const struct clk_pll_layout at91rm9200_pll_layout = {
 351         .pllr_mask = 0x7FFFFFF,
 352         .mul_shift = 16,
 353         .mul_mask = 0x7FF,
 354 };
 355
 356 static const struct clk_pll_layout at91sam9g45_pll_layout = {
 357         .pllr_mask = 0xFFFFFF,
 358         .mul_shift = 16,
 359         .mul_mask = 0xFF,
 360 };
 361
 362 static const struct clk_pll_layout at91sam9g20_pllb_layout = {
 363         .pllr_mask = 0x3FFFFF,
 364         .mul_shift = 16,
 365         .mul_mask = 0x3F,
 366 };
 367
 368 static const struct clk_pll_layout sama5d3_pll_layout = {
 369         .pllr_mask = 0x1FFFFFF,
 370         .mul_shift = 18,
 371         .mul_mask = 0x7F,
 372 };
 373
 374
 375 static struct clk_pll_characteristics * __init
 376 of_at91_clk_pll_get_characteristics(struct device_node *np)
 377 {
 378         int i;
 379         int offset;
 380         u32 tmp;
 381         int num_output;
 382         u32 num_cells;
 383         struct clk_range input;
 384         struct clk_range *output;
 385         u8 *out = NULL;
 386         u16 *icpll = NULL;
 387         struct clk_pll_characteristics *characteristics;
 388
 389         if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
 390                 return NULL;
 391
 392         if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
 393                                  &num_cells))
 394                 return NULL;
 395
 396         if (num_cells < 2 || num_cells > 4)
 397                 return NULL;
 398
 399         if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
 400                 return NULL;
 401         num_output = tmp / (sizeof(u32) * num_cells);
 402
 403         characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
 404         if (!characteristics)
 405                 return NULL;
 406
 407         output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
 408         if (!output)
 409                 goto out_free_characteristics;
 410
 411         if (num_cells > 2) {
 412                 out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
 413                 if (!out)
 414                         goto out_free_output;
 415         }
 416
 417         if (num_cells > 3) {
 418                 icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
 419                 if (!icpll)
 420                         goto out_free_output;
 421         }
 422
 423         for (i = 0; i < num_output; i++) {
 424                 offset = i * num_cells;
 425                 if (of_property_read_u32_index(np,
 426                                                "atmel,pll-clk-output-ranges",
 427                                                offset, &tmp))
 428                         goto out_free_output;
 429                 output[i].min = tmp;
 430                 if (of_property_read_u32_index(np,
 431                                                "atmel,pll-clk-output-ranges",
 432                                                offset + 1, &tmp))
 433                         goto out_free_output;
 434                 output[i].max = tmp;
 435
 436                 if (num_cells == 2)
 437                         continue;
 438
 439                 if (of_property_read_u32_index(np,
 440                                                "atmel,pll-clk-output-ranges",
 441                                                offset + 2, &tmp))
 442                         goto out_free_output;
 443                 out[i] = tmp;
 444
 445                 if (num_cells == 3)
 446                         continue;
 447
 448                 if (of_property_read_u32_index(np,
 449                                                "atmel,pll-clk-output-ranges",
 450                                                offset + 3, &tmp))
 451                         goto out_free_output;
 452                 icpll[i] = tmp;
 453         }
 454
 455         characteristics->input = input;
 456         characteristics->num_output = num_output;
 457         characteristics->output = output;
 458         characteristics->out = out;
 459         characteristics->icpll = icpll;
 460         return characteristics;
 461
 462 out_free_output:
 463         kfree(icpll);
 464         kfree(out);
 465         kfree(output);
 466 out_free_characteristics:
 467         kfree(characteristics);
 468         return NULL;
 469 }
 470
 471 static void __init
 472 of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc,
 473                       const struct clk_pll_layout *layout)
 474 {
 475         u32 id;
 476         unsigned int irq;
 477         struct clk *clk;
 478         const char *parent_name;
 479         const char *name = np->name;
 480         struct clk_pll_characteristics *characteristics;
 481
 482         if (of_property_read_u32(np, "reg", &id))
 483                 return;
 484
 485         parent_name = of_clk_get_parent_name(np, 0);
 486
 487         of_property_read_string(np, "clock-output-names", &name);
 488
 489         characteristics = of_at91_clk_pll_get_characteristics(np);
 490         if (!characteristics)
 491                 return;
 492
 493         irq = irq_of_parse_and_map(np, 0);
 494         if (!irq)
 495                 return;
 496
 497         clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout,
 498                                     characteristics);
 499         if (IS_ERR(clk))
 500                 goto out_free_characteristics;
 501
 502         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 503         return;
 504
 505 out_free_characteristics:
 506         kfree(characteristics);
 507 }
 508
 509 void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
 510                                                struct at91_pmc *pmc)
 511 {
 512         of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout);
 513 }
 514
 515 void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
 516                                                 struct at91_pmc *pmc)
 517 {
 518         of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout);
 519 }
 520
 521 void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
 522                                                  struct at91_pmc *pmc)
 523 {
 524         of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout);
 525 }
 526
 527 void __init of_sama5d3_clk_pll_setup(struct device_node *np,
 528                                             struct at91_pmc *pmc)
 529 {
 530         of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout);
 531 }