2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_LOCK (0x1 << 31)
26 #define IMX7_ENET_PLL_POWER (0x1 << 5)
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source
31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL
33 * @powerdown: pll powerdown offset bit
34 * @div_mask: mask of divider bits
35 * @div_shift: shift of divider bits
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
38 * is actually a multiplier, and always sits at bit 0.
49 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
51 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
53 unsigned long timeout = jiffies + msecs_to_jiffies(10);
54 u32 val = readl_relaxed(pll->base) & pll->powerdown;
56 /* No need to wait for lock when pll is not powered up */
57 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
60 /* Wait for PLL to lock */
62 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
64 if (time_after(jiffies, timeout))
66 usleep_range(50, 500);
69 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
72 static int clk_pllv3_prepare(struct clk_hw *hw)
74 struct clk_pllv3 *pll = to_clk_pllv3(hw);
77 val = readl_relaxed(pll->base);
82 writel_relaxed(val, pll->base);
84 return clk_pllv3_wait_lock(pll);
87 static void clk_pllv3_unprepare(struct clk_hw *hw)
89 struct clk_pllv3 *pll = to_clk_pllv3(hw);
92 val = readl_relaxed(pll->base);
97 writel_relaxed(val, pll->base);
100 static int clk_pllv3_is_prepared(struct clk_hw *hw)
102 struct clk_pllv3 *pll = to_clk_pllv3(hw);
104 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
110 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate)
113 struct clk_pllv3 *pll = to_clk_pllv3(hw);
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
116 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
119 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
120 unsigned long *prate)
122 unsigned long parent_rate = *prate;
124 return (rate >= parent_rate * 22) ? parent_rate * 22 :
128 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
129 unsigned long parent_rate)
131 struct clk_pllv3 *pll = to_clk_pllv3(hw);
134 if (rate == parent_rate * 22)
136 else if (rate == parent_rate * 20)
141 val = readl_relaxed(pll->base);
142 val &= ~(pll->div_mask << pll->div_shift);
143 val |= (div << pll->div_shift);
144 writel_relaxed(val, pll->base);
146 return clk_pllv3_wait_lock(pll);
149 static const struct clk_ops clk_pllv3_ops = {
150 .prepare = clk_pllv3_prepare,
151 .unprepare = clk_pllv3_unprepare,
152 .is_prepared = clk_pllv3_is_prepared,
153 .recalc_rate = clk_pllv3_recalc_rate,
154 .round_rate = clk_pllv3_round_rate,
155 .set_rate = clk_pllv3_set_rate,
158 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
159 unsigned long parent_rate)
161 struct clk_pllv3 *pll = to_clk_pllv3(hw);
162 u32 div = readl_relaxed(pll->base) & pll->div_mask;
164 return parent_rate * div / 2;
167 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
168 unsigned long *prate)
170 unsigned long parent_rate = *prate;
171 unsigned long min_rate = parent_rate * 54 / 2;
172 unsigned long max_rate = parent_rate * 108 / 2;
177 else if (rate < min_rate)
179 div = rate * 2 / parent_rate;
181 return parent_rate * div / 2;
184 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
185 unsigned long parent_rate)
187 struct clk_pllv3 *pll = to_clk_pllv3(hw);
188 unsigned long min_rate = parent_rate * 54 / 2;
189 unsigned long max_rate = parent_rate * 108 / 2;
192 if (rate < min_rate || rate > max_rate)
195 div = rate * 2 / parent_rate;
196 val = readl_relaxed(pll->base);
197 val &= ~pll->div_mask;
199 writel_relaxed(val, pll->base);
201 return clk_pllv3_wait_lock(pll);
204 static const struct clk_ops clk_pllv3_sys_ops = {
205 .prepare = clk_pllv3_prepare,
206 .unprepare = clk_pllv3_unprepare,
207 .is_prepared = clk_pllv3_is_prepared,
208 .recalc_rate = clk_pllv3_sys_recalc_rate,
209 .round_rate = clk_pllv3_sys_round_rate,
210 .set_rate = clk_pllv3_sys_set_rate,
213 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
214 unsigned long parent_rate)
216 struct clk_pllv3 *pll = to_clk_pllv3(hw);
217 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
218 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
219 u32 div = readl_relaxed(pll->base) & pll->div_mask;
221 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
224 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long *prate)
227 unsigned long parent_rate = *prate;
228 unsigned long min_rate = parent_rate * 27;
229 unsigned long max_rate = parent_rate * 54;
231 u32 mfn, mfd = 1000000;
236 else if (rate < min_rate)
239 div = rate / parent_rate;
240 temp64 = (u64) (rate - div * parent_rate);
242 do_div(temp64, parent_rate);
245 return parent_rate * div + parent_rate / mfd * mfn;
248 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long parent_rate)
251 struct clk_pllv3 *pll = to_clk_pllv3(hw);
252 unsigned long min_rate = parent_rate * 27;
253 unsigned long max_rate = parent_rate * 54;
255 u32 mfn, mfd = 1000000;
258 if (rate < min_rate || rate > max_rate)
261 div = rate / parent_rate;
262 temp64 = (u64) (rate - div * parent_rate);
264 do_div(temp64, parent_rate);
267 val = readl_relaxed(pll->base);
268 val &= ~pll->div_mask;
270 writel_relaxed(val, pll->base);
271 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
272 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
274 return clk_pllv3_wait_lock(pll);
277 static const struct clk_ops clk_pllv3_av_ops = {
278 .prepare = clk_pllv3_prepare,
279 .unprepare = clk_pllv3_unprepare,
280 .is_prepared = clk_pllv3_is_prepared,
281 .recalc_rate = clk_pllv3_av_recalc_rate,
282 .round_rate = clk_pllv3_av_round_rate,
283 .set_rate = clk_pllv3_av_set_rate,
286 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
287 unsigned long parent_rate)
292 static const struct clk_ops clk_pllv3_enet_ops = {
293 .prepare = clk_pllv3_prepare,
294 .unprepare = clk_pllv3_unprepare,
295 .is_prepared = clk_pllv3_is_prepared,
296 .recalc_rate = clk_pllv3_enet_recalc_rate,
299 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
300 const char *parent_name, void __iomem *base,
303 struct clk_pllv3 *pll;
304 const struct clk_ops *ops;
306 struct clk_init_data init;
308 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
310 return ERR_PTR(-ENOMEM);
312 pll->powerdown = BM_PLL_POWER;
316 ops = &clk_pllv3_sys_ops;
318 case IMX_PLLV3_USB_VF610:
321 ops = &clk_pllv3_ops;
322 pll->powerup_set = true;
325 ops = &clk_pllv3_av_ops;
327 case IMX_PLLV3_ENET_IMX7:
328 pll->powerdown = IMX7_ENET_PLL_POWER;
330 ops = &clk_pllv3_enet_ops;
333 ops = &clk_pllv3_ops;
336 pll->div_mask = div_mask;
341 init.parent_names = &parent_name;
342 init.num_parents = 1;
344 pll->hw.init = &init;
346 clk = clk_register(NULL, &pll->hw);