2 * Marvell EBU SoC common clock handling
4 * Copyright (C) 2012 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/kernel.h>
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk-provider.h>
21 #include <linux/of_address.h>
22 #include <linux/syscore_ops.h>
30 #define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3)
31 #define SSCG_SPREAD_DOWN 0x0
32 #define SSCG_SPREAD_UP 0x1
33 #define SSCG_SPREAD_CENTRAL 0x2
34 #define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF)
35 #define SSCG_CONF_HIGH(reg) ((reg) & 0xFF)
37 static struct clk_onecell_data clk_data;
40 * This function can be used by the Kirkwood, the Armada 370, the
41 * Armada XP and the Armada 375 SoC. The name of the function was
42 * chosen following the dt convention: using the first known SoC
45 u32 kirkwood_fix_sscg_deviation(u32 system_clk)
47 struct device_node *sscg_np = NULL;
48 void __iomem *sscg_map;
50 s32 low_bound, high_bound;
53 sscg_np = of_find_node_by_name(NULL, "sscg");
54 if (sscg_np == NULL) {
55 pr_err("cannot get SSCG register node\n");
59 sscg_map = of_iomap(sscg_np, 0);
60 if (sscg_map == NULL) {
61 pr_err("cannot map SSCG register\n");
65 sscg_reg = readl(sscg_map);
66 high_bound = SSCG_CONF_HIGH(sscg_reg);
67 low_bound = SSCG_CONF_LOW(sscg_reg);
69 if ((high_bound - low_bound) <= 0)
72 * From Marvell engineer we got the following formula (when
73 * this code was written, the datasheet was erroneous)
74 * Spread percentage = 1/96 * (H - L) / H
75 * H = SSCG_High_Boundary
76 * L = SSCG_Low_Boundary
78 * As the deviation is half of spread then it lead to the
79 * following formula in the code.
81 * To avoid an overflow and not lose any significant digit in
82 * the same time we have to use a 64 bit integer.
85 freq_swing_half = (((u64)high_bound - (u64)low_bound)
87 do_div(freq_swing_half, (2 * 96 * high_bound));
89 switch (SSCG_CONF_MODE(sscg_reg)) {
90 case SSCG_SPREAD_DOWN:
91 system_clk -= freq_swing_half;
94 system_clk += freq_swing_half;
96 case SSCG_SPREAD_CENTRAL:
104 of_node_put(sscg_np);
109 void __init mvebu_coreclk_setup(struct device_node *np,
110 const struct coreclk_soc_desc *desc)
112 const char *tclk_name = "tclk";
113 const char *cpuclk_name = "cpuclk";
118 base = of_iomap(np, 0);
122 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
123 clk_data.clk_num = 2 + desc->num_ratios;
124 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
126 if (WARN_ON(!clk_data.clks)) {
132 of_property_read_string_index(np, "clock-output-names", 0,
134 rate = desc->get_tclk_freq(base);
135 clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
137 WARN_ON(IS_ERR(clk_data.clks[0]));
139 /* Register CPU clock */
140 of_property_read_string_index(np, "clock-output-names", 1,
142 rate = desc->get_cpu_freq(base);
144 if (desc->is_sscg_enabled && desc->fix_sscg_deviation
145 && desc->is_sscg_enabled(base))
146 rate = desc->fix_sscg_deviation(rate);
148 clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
150 WARN_ON(IS_ERR(clk_data.clks[1]));
152 /* Register fixed-factor clocks derived from CPU clock */
153 for (n = 0; n < desc->num_ratios; n++) {
154 const char *rclk_name = desc->ratios[n].name;
157 of_property_read_string_index(np, "clock-output-names",
159 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
160 clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
161 cpuclk_name, 0, mult, div);
162 WARN_ON(IS_ERR(clk_data.clks[2+n]));
165 /* SAR register isn't needed anymore */
168 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
172 * Clock Gating Control
175 DEFINE_SPINLOCK(ctrl_gating_lock);
177 struct clk_gating_ctrl {
185 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
187 static struct clk_gating_ctrl *ctrl;
189 static struct clk *clk_gating_get_src(
190 struct of_phandle_args *clkspec, void *data)
194 if (clkspec->args_count < 1)
195 return ERR_PTR(-EINVAL);
197 for (n = 0; n < ctrl->num_gates; n++) {
198 struct clk_gate *gate =
199 to_clk_gate(__clk_get_hw(ctrl->gates[n]));
200 if (clkspec->args[0] == gate->bit_idx)
201 return ctrl->gates[n];
203 return ERR_PTR(-ENODEV);
206 static int mvebu_clk_gating_suspend(void)
208 ctrl->saved_reg = readl(ctrl->base);
212 static void mvebu_clk_gating_resume(void)
214 writel(ctrl->saved_reg, ctrl->base);
217 static struct syscore_ops clk_gate_syscore_ops = {
218 .suspend = mvebu_clk_gating_suspend,
219 .resume = mvebu_clk_gating_resume,
222 void __init mvebu_clk_gating_setup(struct device_node *np,
223 const struct clk_gating_soc_desc *desc)
227 const char *default_parent = NULL;
231 pr_err("mvebu-clk-gating: cannot instantiate more than one gatable clock device\n");
235 base = of_iomap(np, 0);
239 clk = of_clk_get(np, 0);
241 default_parent = __clk_get_name(clk);
245 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
249 /* lock must already be initialized */
250 ctrl->lock = &ctrl_gating_lock;
254 /* Count, allocate, and register clock gates */
255 for (n = 0; desc[n].name;)
259 ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
261 if (WARN_ON(!ctrl->gates))
264 for (n = 0; n < ctrl->num_gates; n++) {
266 (desc[n].parent) ? desc[n].parent : default_parent;
267 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
268 desc[n].flags, base, desc[n].bit_idx,
270 WARN_ON(IS_ERR(ctrl->gates[n]));
273 of_clk_add_provider(np, clk_gating_get_src, ctrl);
275 register_syscore_ops(&clk_gate_syscore_ops);