drivers/clk/qcom/gcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll3 = {
  36         .l_reg = 0x3164,
  37         .m_reg = 0x3168,
  38         .n_reg = 0x316c,
  39         .config_reg = 0x3174,
  40         .mode_reg = 0x3160,
  41         .status_reg = 0x3178,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll3",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_pll pll8 = {
  52         .l_reg = 0x3144,
  53         .m_reg = 0x3148,
  54         .n_reg = 0x314c,
  55         .config_reg = 0x3154,
  56         .mode_reg = 0x3140,
  57         .status_reg = 0x3158,
  58         .status_bit = 16,
  59         .clkr.hw.init = &(struct clk_init_data){
  60                 .name = "pll8",
  61                 .parent_names = (const char *[]){ "pxo" },
  62                 .num_parents = 1,
  63                 .ops = &clk_pll_ops,
  64         },
  65 };
  66
  67 static struct clk_regmap pll8_vote = {
  68         .enable_reg = 0x34c0,
  69         .enable_mask = BIT(8),
  70         .hw.init = &(struct clk_init_data){
  71                 .name = "pll8_vote",
  72                 .parent_names = (const char *[]){ "pll8" },
  73                 .num_parents = 1,
  74                 .ops = &clk_pll_vote_ops,
  75         },
  76 };
  77
  78 static struct clk_pll pll14 = {
  79         .l_reg = 0x31c4,
  80         .m_reg = 0x31c8,
  81         .n_reg = 0x31cc,
  82         .config_reg = 0x31d4,
  83         .mode_reg = 0x31c0,
  84         .status_reg = 0x31d8,
  85         .status_bit = 16,
  86         .clkr.hw.init = &(struct clk_init_data){
  87                 .name = "pll14",
  88                 .parent_names = (const char *[]){ "pxo" },
  89                 .num_parents = 1,
  90                 .ops = &clk_pll_ops,
  91         },
  92 };
  93
  94 static struct clk_regmap pll14_vote = {
  95         .enable_reg = 0x34c0,
  96         .enable_mask = BIT(14),
  97         .hw.init = &(struct clk_init_data){
  98                 .name = "pll14_vote",
  99                 .parent_names = (const char *[]){ "pll14" },
 100                 .num_parents = 1,
 101                 .ops = &clk_pll_vote_ops,
 102         },
 103 };
 104
 105 #define P_PXO   0
 106 #define P_PLL8  1
 107 #define P_PLL3  2
 108 #define P_CXO   2
 109
 110 static const u8 gcc_pxo_pll8_map[] = {
 111         [P_PXO]         = 0,
 112         [P_PLL8]        = 3,
 113 };
 114
 115 static const char *gcc_pxo_pll8[] = {
 116         "pxo",
 117         "pll8_vote",
 118 };
 119
 120 static const u8 gcc_pxo_pll8_cxo_map[] = {
 121         [P_PXO]         = 0,
 122         [P_PLL8]        = 3,
 123         [P_CXO]         = 5,
 124 };
 125
 126 static const char *gcc_pxo_pll8_cxo[] = {
 127         "pxo",
 128         "pll8_vote",
 129         "cxo",
 130 };
 131
 132 static const u8 gcc_pxo_pll8_pll3_map[] = {
 133         [P_PXO]         = 0,
 134         [P_PLL8]        = 3,
 135         [P_PLL3]        = 6,
 136 };
 137
 138 static const char *gcc_pxo_pll8_pll3[] = {
 139         "pxo",
 140         "pll8_vote",
 141         "pll3",
 142 };
 143
 144 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 145         {  1843200, P_PLL8, 2,  6, 625 },
 146         {  3686400, P_PLL8, 2, 12, 625 },
 147         {  7372800, P_PLL8, 2, 24, 625 },
 148         { 14745600, P_PLL8, 2, 48, 625 },
 149         { 16000000, P_PLL8, 4,  1,   6 },
 150         { 24000000, P_PLL8, 4,  1,   4 },
 151         { 32000000, P_PLL8, 4,  1,   3 },
 152         { 40000000, P_PLL8, 1,  5,  48 },
 153         { 46400000, P_PLL8, 1, 29, 240 },
 154         { 48000000, P_PLL8, 4,  1,   2 },
 155         { 51200000, P_PLL8, 1,  2,  15 },
 156         { 56000000, P_PLL8, 1,  7,  48 },
 157         { 58982400, P_PLL8, 1, 96, 625 },
 158         { 64000000, P_PLL8, 2,  1,   3 },
 159         { }
 160 };
 161
 162 static struct clk_rcg gsbi1_uart_src = {
 163         .ns_reg = 0x29d4,
 164         .md_reg = 0x29d0,
 165         .mn = {
 166                 .mnctr_en_bit = 8,
 167                 .mnctr_reset_bit = 7,
 168                 .mnctr_mode_shift = 5,
 169                 .n_val_shift = 16,
 170                 .m_val_shift = 16,
 171                 .width = 16,
 172         },
 173         .p = {
 174                 .pre_div_shift = 3,
 175                 .pre_div_width = 2,
 176         },
 177         .s = {
 178                 .src_sel_shift = 0,
 179                 .parent_map = gcc_pxo_pll8_map,
 180         },
 181         .freq_tbl = clk_tbl_gsbi_uart,
 182         .clkr = {
 183                 .enable_reg = 0x29d4,
 184                 .enable_mask = BIT(11),
 185                 .hw.init = &(struct clk_init_data){
 186                         .name = "gsbi1_uart_src",
 187                         .parent_names = gcc_pxo_pll8,
 188                         .num_parents = 2,
 189                         .ops = &clk_rcg_ops,
 190                         .flags = CLK_SET_PARENT_GATE,
 191                 },
 192         },
 193 };
 194
 195 static struct clk_branch gsbi1_uart_clk = {
 196         .halt_reg = 0x2fcc,
 197         .halt_bit = 10,
 198         .clkr = {
 199                 .enable_reg = 0x29d4,
 200                 .enable_mask = BIT(9),
 201                 .hw.init = &(struct clk_init_data){
 202                         .name = "gsbi1_uart_clk",
 203                         .parent_names = (const char *[]){
 204                                 "gsbi1_uart_src",
 205                         },
 206                         .num_parents = 1,
 207                         .ops = &clk_branch_ops,
 208                         .flags = CLK_SET_RATE_PARENT,
 209                 },
 210         },
 211 };
 212
 213 static struct clk_rcg gsbi2_uart_src = {
 214         .ns_reg = 0x29f4,
 215         .md_reg = 0x29f0,
 216         .mn = {
 217                 .mnctr_en_bit = 8,
 218                 .mnctr_reset_bit = 7,
 219                 .mnctr_mode_shift = 5,
 220                 .n_val_shift = 16,
 221                 .m_val_shift = 16,
 222                 .width = 16,
 223         },
 224         .p = {
 225                 .pre_div_shift = 3,
 226                 .pre_div_width = 2,
 227         },
 228         .s = {
 229                 .src_sel_shift = 0,
 230                 .parent_map = gcc_pxo_pll8_map,
 231         },
 232         .freq_tbl = clk_tbl_gsbi_uart,
 233         .clkr = {
 234                 .enable_reg = 0x29f4,
 235                 .enable_mask = BIT(11),
 236                 .hw.init = &(struct clk_init_data){
 237                         .name = "gsbi2_uart_src",
 238                         .parent_names = gcc_pxo_pll8,
 239                         .num_parents = 2,
 240                         .ops = &clk_rcg_ops,
 241                         .flags = CLK_SET_PARENT_GATE,
 242                 },
 243         },
 244 };
 245
 246 static struct clk_branch gsbi2_uart_clk = {
 247         .halt_reg = 0x2fcc,
 248         .halt_bit = 6,
 249         .clkr = {
 250                 .enable_reg = 0x29f4,
 251                 .enable_mask = BIT(9),
 252                 .hw.init = &(struct clk_init_data){
 253                         .name = "gsbi2_uart_clk",
 254                         .parent_names = (const char *[]){
 255                                 "gsbi2_uart_src",
 256                         },
 257                         .num_parents = 1,
 258                         .ops = &clk_branch_ops,
 259                         .flags = CLK_SET_RATE_PARENT,
 260                 },
 261         },
 262 };
 263
 264 static struct clk_rcg gsbi3_uart_src = {
 265         .ns_reg = 0x2a14,
 266         .md_reg = 0x2a10,
 267         .mn = {
 268                 .mnctr_en_bit = 8,
 269                 .mnctr_reset_bit = 7,
 270                 .mnctr_mode_shift = 5,
 271                 .n_val_shift = 16,
 272                 .m_val_shift = 16,
 273                 .width = 16,
 274         },
 275         .p = {
 276                 .pre_div_shift = 3,
 277                 .pre_div_width = 2,
 278         },
 279         .s = {
 280                 .src_sel_shift = 0,
 281                 .parent_map = gcc_pxo_pll8_map,
 282         },
 283         .freq_tbl = clk_tbl_gsbi_uart,
 284         .clkr = {
 285                 .enable_reg = 0x2a14,
 286                 .enable_mask = BIT(11),
 287                 .hw.init = &(struct clk_init_data){
 288                         .name = "gsbi3_uart_src",
 289                         .parent_names = gcc_pxo_pll8,
 290                         .num_parents = 2,
 291                         .ops = &clk_rcg_ops,
 292                         .flags = CLK_SET_PARENT_GATE,
 293                 },
 294         },
 295 };
 296
 297 static struct clk_branch gsbi3_uart_clk = {
 298         .halt_reg = 0x2fcc,
 299         .halt_bit = 2,
 300         .clkr = {
 301                 .enable_reg = 0x2a14,
 302                 .enable_mask = BIT(9),
 303                 .hw.init = &(struct clk_init_data){
 304                         .name = "gsbi3_uart_clk",
 305                         .parent_names = (const char *[]){
 306                                 "gsbi3_uart_src",
 307                         },
 308                         .num_parents = 1,
 309                         .ops = &clk_branch_ops,
 310                         .flags = CLK_SET_RATE_PARENT,
 311                 },
 312         },
 313 };
 314
 315 static struct clk_rcg gsbi4_uart_src = {
 316         .ns_reg = 0x2a34,
 317         .md_reg = 0x2a30,
 318         .mn = {
 319                 .mnctr_en_bit = 8,
 320                 .mnctr_reset_bit = 7,
 321                 .mnctr_mode_shift = 5,
 322                 .n_val_shift = 16,
 323                 .m_val_shift = 16,
 324                 .width = 16,
 325         },
 326         .p = {
 327                 .pre_div_shift = 3,
 328                 .pre_div_width = 2,
 329         },
 330         .s = {
 331                 .src_sel_shift = 0,
 332                 .parent_map = gcc_pxo_pll8_map,
 333         },
 334         .freq_tbl = clk_tbl_gsbi_uart,
 335         .clkr = {
 336                 .enable_reg = 0x2a34,
 337                 .enable_mask = BIT(11),
 338                 .hw.init = &(struct clk_init_data){
 339                         .name = "gsbi4_uart_src",
 340                         .parent_names = gcc_pxo_pll8,
 341                         .num_parents = 2,
 342                         .ops = &clk_rcg_ops,
 343                         .flags = CLK_SET_PARENT_GATE,
 344                 },
 345         },
 346 };
 347
 348 static struct clk_branch gsbi4_uart_clk = {
 349         .halt_reg = 0x2fd0,
 350         .halt_bit = 26,
 351         .clkr = {
 352                 .enable_reg = 0x2a34,
 353                 .enable_mask = BIT(9),
 354                 .hw.init = &(struct clk_init_data){
 355                         .name = "gsbi4_uart_clk",
 356                         .parent_names = (const char *[]){
 357                                 "gsbi4_uart_src",
 358                         },
 359                         .num_parents = 1,
 360                         .ops = &clk_branch_ops,
 361                         .flags = CLK_SET_RATE_PARENT,
 362                 },
 363         },
 364 };
 365
 366 static struct clk_rcg gsbi5_uart_src = {
 367         .ns_reg = 0x2a54,
 368         .md_reg = 0x2a50,
 369         .mn = {
 370                 .mnctr_en_bit = 8,
 371                 .mnctr_reset_bit = 7,
 372                 .mnctr_mode_shift = 5,
 373                 .n_val_shift = 16,
 374                 .m_val_shift = 16,
 375                 .width = 16,
 376         },
 377         .p = {
 378                 .pre_div_shift = 3,
 379                 .pre_div_width = 2,
 380         },
 381         .s = {
 382                 .src_sel_shift = 0,
 383                 .parent_map = gcc_pxo_pll8_map,
 384         },
 385         .freq_tbl = clk_tbl_gsbi_uart,
 386         .clkr = {
 387                 .enable_reg = 0x2a54,
 388                 .enable_mask = BIT(11),
 389                 .hw.init = &(struct clk_init_data){
 390                         .name = "gsbi5_uart_src",
 391                         .parent_names = gcc_pxo_pll8,
 392                         .num_parents = 2,
 393                         .ops = &clk_rcg_ops,
 394                         .flags = CLK_SET_PARENT_GATE,
 395                 },
 396         },
 397 };
 398
 399 static struct clk_branch gsbi5_uart_clk = {
 400         .halt_reg = 0x2fd0,
 401         .halt_bit = 22,
 402         .clkr = {
 403                 .enable_reg = 0x2a54,
 404                 .enable_mask = BIT(9),
 405                 .hw.init = &(struct clk_init_data){
 406                         .name = "gsbi5_uart_clk",
 407                         .parent_names = (const char *[]){
 408                                 "gsbi5_uart_src",
 409                         },
 410                         .num_parents = 1,
 411                         .ops = &clk_branch_ops,
 412                         .flags = CLK_SET_RATE_PARENT,
 413                 },
 414         },
 415 };
 416
 417 static struct clk_rcg gsbi6_uart_src = {
 418         .ns_reg = 0x2a74,
 419         .md_reg = 0x2a70,
 420         .mn = {
 421                 .mnctr_en_bit = 8,
 422                 .mnctr_reset_bit = 7,
 423                 .mnctr_mode_shift = 5,
 424                 .n_val_shift = 16,
 425                 .m_val_shift = 16,
 426                 .width = 16,
 427         },
 428         .p = {
 429                 .pre_div_shift = 3,
 430                 .pre_div_width = 2,
 431         },
 432         .s = {
 433                 .src_sel_shift = 0,
 434                 .parent_map = gcc_pxo_pll8_map,
 435         },
 436         .freq_tbl = clk_tbl_gsbi_uart,
 437         .clkr = {
 438                 .enable_reg = 0x2a74,
 439                 .enable_mask = BIT(11),
 440                 .hw.init = &(struct clk_init_data){
 441                         .name = "gsbi6_uart_src",
 442                         .parent_names = gcc_pxo_pll8,
 443                         .num_parents = 2,
 444                         .ops = &clk_rcg_ops,
 445                         .flags = CLK_SET_PARENT_GATE,
 446                 },
 447         },
 448 };
 449
 450 static struct clk_branch gsbi6_uart_clk = {
 451         .halt_reg = 0x2fd0,
 452         .halt_bit = 18,
 453         .clkr = {
 454                 .enable_reg = 0x2a74,
 455                 .enable_mask = BIT(9),
 456                 .hw.init = &(struct clk_init_data){
 457                         .name = "gsbi6_uart_clk",
 458                         .parent_names = (const char *[]){
 459                                 "gsbi6_uart_src",
 460                         },
 461                         .num_parents = 1,
 462                         .ops = &clk_branch_ops,
 463                         .flags = CLK_SET_RATE_PARENT,
 464                 },
 465         },
 466 };
 467
 468 static struct clk_rcg gsbi7_uart_src = {
 469         .ns_reg = 0x2a94,
 470         .md_reg = 0x2a90,
 471         .mn = {
 472                 .mnctr_en_bit = 8,
 473                 .mnctr_reset_bit = 7,
 474                 .mnctr_mode_shift = 5,
 475                 .n_val_shift = 16,
 476                 .m_val_shift = 16,
 477                 .width = 16,
 478         },
 479         .p = {
 480                 .pre_div_shift = 3,
 481                 .pre_div_width = 2,
 482         },
 483         .s = {
 484                 .src_sel_shift = 0,
 485                 .parent_map = gcc_pxo_pll8_map,
 486         },
 487         .freq_tbl = clk_tbl_gsbi_uart,
 488         .clkr = {
 489                 .enable_reg = 0x2a94,
 490                 .enable_mask = BIT(11),
 491                 .hw.init = &(struct clk_init_data){
 492                         .name = "gsbi7_uart_src",
 493                         .parent_names = gcc_pxo_pll8,
 494                         .num_parents = 2,
 495                         .ops = &clk_rcg_ops,
 496                         .flags = CLK_SET_PARENT_GATE,
 497                 },
 498         },
 499 };
 500
 501 static struct clk_branch gsbi7_uart_clk = {
 502         .halt_reg = 0x2fd0,
 503         .halt_bit = 14,
 504         .clkr = {
 505                 .enable_reg = 0x2a94,
 506                 .enable_mask = BIT(9),
 507                 .hw.init = &(struct clk_init_data){
 508                         .name = "gsbi7_uart_clk",
 509                         .parent_names = (const char *[]){
 510                                 "gsbi7_uart_src",
 511                         },
 512                         .num_parents = 1,
 513                         .ops = &clk_branch_ops,
 514                         .flags = CLK_SET_RATE_PARENT,
 515                 },
 516         },
 517 };
 518
 519 static struct clk_rcg gsbi8_uart_src = {
 520         .ns_reg = 0x2ab4,
 521         .md_reg = 0x2ab0,
 522         .mn = {
 523                 .mnctr_en_bit = 8,
 524                 .mnctr_reset_bit = 7,
 525                 .mnctr_mode_shift = 5,
 526                 .n_val_shift = 16,
 527                 .m_val_shift = 16,
 528                 .width = 16,
 529         },
 530         .p = {
 531                 .pre_div_shift = 3,
 532                 .pre_div_width = 2,
 533         },
 534         .s = {
 535                 .src_sel_shift = 0,
 536                 .parent_map = gcc_pxo_pll8_map,
 537         },
 538         .freq_tbl = clk_tbl_gsbi_uart,
 539         .clkr = {
 540                 .enable_reg = 0x2ab4,
 541                 .enable_mask = BIT(11),
 542                 .hw.init = &(struct clk_init_data){
 543                         .name = "gsbi8_uart_src",
 544                         .parent_names = gcc_pxo_pll8,
 545                         .num_parents = 2,
 546                         .ops = &clk_rcg_ops,
 547                         .flags = CLK_SET_PARENT_GATE,
 548                 },
 549         },
 550 };
 551
 552 static struct clk_branch gsbi8_uart_clk = {
 553         .halt_reg = 0x2fd0,
 554         .halt_bit = 10,
 555         .clkr = {
 556                 .enable_reg = 0x2ab4,
 557                 .enable_mask = BIT(9),
 558                 .hw.init = &(struct clk_init_data){
 559                         .name = "gsbi8_uart_clk",
 560                         .parent_names = (const char *[]){ "gsbi8_uart_src" },
 561                         .num_parents = 1,
 562                         .ops = &clk_branch_ops,
 563                         .flags = CLK_SET_RATE_PARENT,
 564                 },
 565         },
 566 };
 567
 568 static struct clk_rcg gsbi9_uart_src = {
 569         .ns_reg = 0x2ad4,
 570         .md_reg = 0x2ad0,
 571         .mn = {
 572                 .mnctr_en_bit = 8,
 573                 .mnctr_reset_bit = 7,
 574                 .mnctr_mode_shift = 5,
 575                 .n_val_shift = 16,
 576                 .m_val_shift = 16,
 577                 .width = 16,
 578         },
 579         .p = {
 580                 .pre_div_shift = 3,
 581                 .pre_div_width = 2,
 582         },
 583         .s = {
 584                 .src_sel_shift = 0,
 585                 .parent_map = gcc_pxo_pll8_map,
 586         },
 587         .freq_tbl = clk_tbl_gsbi_uart,
 588         .clkr = {
 589                 .enable_reg = 0x2ad4,
 590                 .enable_mask = BIT(11),
 591                 .hw.init = &(struct clk_init_data){
 592                         .name = "gsbi9_uart_src",
 593                         .parent_names = gcc_pxo_pll8,
 594                         .num_parents = 2,
 595                         .ops = &clk_rcg_ops,
 596                         .flags = CLK_SET_PARENT_GATE,
 597                 },
 598         },
 599 };
 600
 601 static struct clk_branch gsbi9_uart_clk = {
 602         .halt_reg = 0x2fd0,
 603         .halt_bit = 6,
 604         .clkr = {
 605                 .enable_reg = 0x2ad4,
 606                 .enable_mask = BIT(9),
 607                 .hw.init = &(struct clk_init_data){
 608                         .name = "gsbi9_uart_clk",
 609                         .parent_names = (const char *[]){ "gsbi9_uart_src" },
 610                         .num_parents = 1,
 611                         .ops = &clk_branch_ops,
 612                         .flags = CLK_SET_RATE_PARENT,
 613                 },
 614         },
 615 };
 616
 617 static struct clk_rcg gsbi10_uart_src = {
 618         .ns_reg = 0x2af4,
 619         .md_reg = 0x2af0,
 620         .mn = {
 621                 .mnctr_en_bit = 8,
 622                 .mnctr_reset_bit = 7,
 623                 .mnctr_mode_shift = 5,
 624                 .n_val_shift = 16,
 625                 .m_val_shift = 16,
 626                 .width = 16,
 627         },
 628         .p = {
 629                 .pre_div_shift = 3,
 630                 .pre_div_width = 2,
 631         },
 632         .s = {
 633                 .src_sel_shift = 0,
 634                 .parent_map = gcc_pxo_pll8_map,
 635         },
 636         .freq_tbl = clk_tbl_gsbi_uart,
 637         .clkr = {
 638                 .enable_reg = 0x2af4,
 639                 .enable_mask = BIT(11),
 640                 .hw.init = &(struct clk_init_data){
 641                         .name = "gsbi10_uart_src",
 642                         .parent_names = gcc_pxo_pll8,
 643                         .num_parents = 2,
 644                         .ops = &clk_rcg_ops,
 645                         .flags = CLK_SET_PARENT_GATE,
 646                 },
 647         },
 648 };
 649
 650 static struct clk_branch gsbi10_uart_clk = {
 651         .halt_reg = 0x2fd0,
 652         .halt_bit = 2,
 653         .clkr = {
 654                 .enable_reg = 0x2af4,
 655                 .enable_mask = BIT(9),
 656                 .hw.init = &(struct clk_init_data){
 657                         .name = "gsbi10_uart_clk",
 658                         .parent_names = (const char *[]){ "gsbi10_uart_src" },
 659                         .num_parents = 1,
 660                         .ops = &clk_branch_ops,
 661                         .flags = CLK_SET_RATE_PARENT,
 662                 },
 663         },
 664 };
 665
 666 static struct clk_rcg gsbi11_uart_src = {
 667         .ns_reg = 0x2b14,
 668         .md_reg = 0x2b10,
 669         .mn = {
 670                 .mnctr_en_bit = 8,
 671                 .mnctr_reset_bit = 7,
 672                 .mnctr_mode_shift = 5,
 673                 .n_val_shift = 16,
 674                 .m_val_shift = 16,
 675                 .width = 16,
 676         },
 677         .p = {
 678                 .pre_div_shift = 3,
 679                 .pre_div_width = 2,
 680         },
 681         .s = {
 682                 .src_sel_shift = 0,
 683                 .parent_map = gcc_pxo_pll8_map,
 684         },
 685         .freq_tbl = clk_tbl_gsbi_uart,
 686         .clkr = {
 687                 .enable_reg = 0x2b14,
 688                 .enable_mask = BIT(11),
 689                 .hw.init = &(struct clk_init_data){
 690                         .name = "gsbi11_uart_src",
 691                         .parent_names = gcc_pxo_pll8,
 692                         .num_parents = 2,
 693                         .ops = &clk_rcg_ops,
 694                         .flags = CLK_SET_PARENT_GATE,
 695                 },
 696         },
 697 };
 698
 699 static struct clk_branch gsbi11_uart_clk = {
 700         .halt_reg = 0x2fd4,
 701         .halt_bit = 17,
 702         .clkr = {
 703                 .enable_reg = 0x2b14,
 704                 .enable_mask = BIT(9),
 705                 .hw.init = &(struct clk_init_data){
 706                         .name = "gsbi11_uart_clk",
 707                         .parent_names = (const char *[]){ "gsbi11_uart_src" },
 708                         .num_parents = 1,
 709                         .ops = &clk_branch_ops,
 710                         .flags = CLK_SET_RATE_PARENT,
 711                 },
 712         },
 713 };
 714
 715 static struct clk_rcg gsbi12_uart_src = {
 716         .ns_reg = 0x2b34,
 717         .md_reg = 0x2b30,
 718         .mn = {
 719                 .mnctr_en_bit = 8,
 720                 .mnctr_reset_bit = 7,
 721                 .mnctr_mode_shift = 5,
 722                 .n_val_shift = 16,
 723                 .m_val_shift = 16,
 724                 .width = 16,
 725         },
 726         .p = {
 727                 .pre_div_shift = 3,
 728                 .pre_div_width = 2,
 729         },
 730         .s = {
 731                 .src_sel_shift = 0,
 732                 .parent_map = gcc_pxo_pll8_map,
 733         },
 734         .freq_tbl = clk_tbl_gsbi_uart,
 735         .clkr = {
 736                 .enable_reg = 0x2b34,
 737                 .enable_mask = BIT(11),
 738                 .hw.init = &(struct clk_init_data){
 739                         .name = "gsbi12_uart_src",
 740                         .parent_names = gcc_pxo_pll8,
 741                         .num_parents = 2,
 742                         .ops = &clk_rcg_ops,
 743                         .flags = CLK_SET_PARENT_GATE,
 744                 },
 745         },
 746 };
 747
 748 static struct clk_branch gsbi12_uart_clk = {
 749         .halt_reg = 0x2fd4,
 750         .halt_bit = 13,
 751         .clkr = {
 752                 .enable_reg = 0x2b34,
 753                 .enable_mask = BIT(9),
 754                 .hw.init = &(struct clk_init_data){
 755                         .name = "gsbi12_uart_clk",
 756                         .parent_names = (const char *[]){ "gsbi12_uart_src" },
 757                         .num_parents = 1,
 758                         .ops = &clk_branch_ops,
 759                         .flags = CLK_SET_RATE_PARENT,
 760                 },
 761         },
 762 };
 763
 764 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 765         {  1100000, P_PXO,  1, 2, 49 },
 766         {  5400000, P_PXO,  1, 1,  5 },
 767         { 10800000, P_PXO,  1, 2,  5 },
 768         { 15060000, P_PLL8, 1, 2, 51 },
 769         { 24000000, P_PLL8, 4, 1,  4 },
 770         { 25600000, P_PLL8, 1, 1, 15 },
 771         { 27000000, P_PXO,  1, 0,  0 },
 772         { 48000000, P_PLL8, 4, 1,  2 },
 773         { 51200000, P_PLL8, 1, 2, 15 },
 774         { }
 775 };
 776
 777 static struct clk_rcg gsbi1_qup_src = {
 778         .ns_reg = 0x29cc,
 779         .md_reg = 0x29c8,
 780         .mn = {
 781                 .mnctr_en_bit = 8,
 782                 .mnctr_reset_bit = 7,
 783                 .mnctr_mode_shift = 5,
 784                 .n_val_shift = 16,
 785                 .m_val_shift = 16,
 786                 .width = 8,
 787         },
 788         .p = {
 789                 .pre_div_shift = 3,
 790                 .pre_div_width = 2,
 791         },
 792         .s = {
 793                 .src_sel_shift = 0,
 794                 .parent_map = gcc_pxo_pll8_map,
 795         },
 796         .freq_tbl = clk_tbl_gsbi_qup,
 797         .clkr = {
 798                 .enable_reg = 0x29cc,
 799                 .enable_mask = BIT(11),
 800                 .hw.init = &(struct clk_init_data){
 801                         .name = "gsbi1_qup_src",
 802                         .parent_names = gcc_pxo_pll8,
 803                         .num_parents = 2,
 804                         .ops = &clk_rcg_ops,
 805                         .flags = CLK_SET_PARENT_GATE,
 806                 },
 807         },
 808 };
 809
 810 static struct clk_branch gsbi1_qup_clk = {
 811         .halt_reg = 0x2fcc,
 812         .halt_bit = 9,
 813         .clkr = {
 814                 .enable_reg = 0x29cc,
 815                 .enable_mask = BIT(9),
 816                 .hw.init = &(struct clk_init_data){
 817                         .name = "gsbi1_qup_clk",
 818                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 819                         .num_parents = 1,
 820                         .ops = &clk_branch_ops,
 821                         .flags = CLK_SET_RATE_PARENT,
 822                 },
 823         },
 824 };
 825
 826 static struct clk_rcg gsbi2_qup_src = {
 827         .ns_reg = 0x29ec,
 828         .md_reg = 0x29e8,
 829         .mn = {
 830                 .mnctr_en_bit = 8,
 831                 .mnctr_reset_bit = 7,
 832                 .mnctr_mode_shift = 5,
 833                 .n_val_shift = 16,
 834                 .m_val_shift = 16,
 835                 .width = 8,
 836         },
 837         .p = {
 838                 .pre_div_shift = 3,
 839                 .pre_div_width = 2,
 840         },
 841         .s = {
 842                 .src_sel_shift = 0,
 843                 .parent_map = gcc_pxo_pll8_map,
 844         },
 845         .freq_tbl = clk_tbl_gsbi_qup,
 846         .clkr = {
 847                 .enable_reg = 0x29ec,
 848                 .enable_mask = BIT(11),
 849                 .hw.init = &(struct clk_init_data){
 850                         .name = "gsbi2_qup_src",
 851                         .parent_names = gcc_pxo_pll8,
 852                         .num_parents = 2,
 853                         .ops = &clk_rcg_ops,
 854                         .flags = CLK_SET_PARENT_GATE,
 855                 },
 856         },
 857 };
 858
 859 static struct clk_branch gsbi2_qup_clk = {
 860         .halt_reg = 0x2fcc,
 861         .halt_bit = 4,
 862         .clkr = {
 863                 .enable_reg = 0x29ec,
 864                 .enable_mask = BIT(9),
 865                 .hw.init = &(struct clk_init_data){
 866                         .name = "gsbi2_qup_clk",
 867                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 868                         .num_parents = 1,
 869                         .ops = &clk_branch_ops,
 870                         .flags = CLK_SET_RATE_PARENT,
 871                 },
 872         },
 873 };
 874
 875 static struct clk_rcg gsbi3_qup_src = {
 876         .ns_reg = 0x2a0c,
 877         .md_reg = 0x2a08,
 878         .mn = {
 879                 .mnctr_en_bit = 8,
 880                 .mnctr_reset_bit = 7,
 881                 .mnctr_mode_shift = 5,
 882                 .n_val_shift = 16,
 883                 .m_val_shift = 16,
 884                 .width = 8,
 885         },
 886         .p = {
 887                 .pre_div_shift = 3,
 888                 .pre_div_width = 2,
 889         },
 890         .s = {
 891                 .src_sel_shift = 0,
 892                 .parent_map = gcc_pxo_pll8_map,
 893         },
 894         .freq_tbl = clk_tbl_gsbi_qup,
 895         .clkr = {
 896                 .enable_reg = 0x2a0c,
 897                 .enable_mask = BIT(11),
 898                 .hw.init = &(struct clk_init_data){
 899                         .name = "gsbi3_qup_src",
 900                         .parent_names = gcc_pxo_pll8,
 901                         .num_parents = 2,
 902                         .ops = &clk_rcg_ops,
 903                         .flags = CLK_SET_PARENT_GATE,
 904                 },
 905         },
 906 };
 907
 908 static struct clk_branch gsbi3_qup_clk = {
 909         .halt_reg = 0x2fcc,
 910         .halt_bit = 0,
 911         .clkr = {
 912                 .enable_reg = 0x2a0c,
 913                 .enable_mask = BIT(9),
 914                 .hw.init = &(struct clk_init_data){
 915                         .name = "gsbi3_qup_clk",
 916                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
 917                         .num_parents = 1,
 918                         .ops = &clk_branch_ops,
 919                         .flags = CLK_SET_RATE_PARENT,
 920                 },
 921         },
 922 };
 923
 924 static struct clk_rcg gsbi4_qup_src = {
 925         .ns_reg = 0x2a2c,
 926         .md_reg = 0x2a28,
 927         .mn = {
 928                 .mnctr_en_bit = 8,
 929                 .mnctr_reset_bit = 7,
 930                 .mnctr_mode_shift = 5,
 931                 .n_val_shift = 16,
 932                 .m_val_shift = 16,
 933                 .width = 8,
 934         },
 935         .p = {
 936                 .pre_div_shift = 3,
 937                 .pre_div_width = 2,
 938         },
 939         .s = {
 940                 .src_sel_shift = 0,
 941                 .parent_map = gcc_pxo_pll8_map,
 942         },
 943         .freq_tbl = clk_tbl_gsbi_qup,
 944         .clkr = {
 945                 .enable_reg = 0x2a2c,
 946                 .enable_mask = BIT(11),
 947                 .hw.init = &(struct clk_init_data){
 948                         .name = "gsbi4_qup_src",
 949                         .parent_names = gcc_pxo_pll8,
 950                         .num_parents = 2,
 951                         .ops = &clk_rcg_ops,
 952                         .flags = CLK_SET_PARENT_GATE,
 953                 },
 954         },
 955 };
 956
 957 static struct clk_branch gsbi4_qup_clk = {
 958         .halt_reg = 0x2fd0,
 959         .halt_bit = 24,
 960         .clkr = {
 961                 .enable_reg = 0x2a2c,
 962                 .enable_mask = BIT(9),
 963                 .hw.init = &(struct clk_init_data){
 964                         .name = "gsbi4_qup_clk",
 965                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 966                         .num_parents = 1,
 967                         .ops = &clk_branch_ops,
 968                         .flags = CLK_SET_RATE_PARENT,
 969                 },
 970         },
 971 };
 972
 973 static struct clk_rcg gsbi5_qup_src = {
 974         .ns_reg = 0x2a4c,
 975         .md_reg = 0x2a48,
 976         .mn = {
 977                 .mnctr_en_bit = 8,
 978                 .mnctr_reset_bit = 7,
 979                 .mnctr_mode_shift = 5,
 980                 .n_val_shift = 16,
 981                 .m_val_shift = 16,
 982                 .width = 8,
 983         },
 984         .p = {
 985                 .pre_div_shift = 3,
 986                 .pre_div_width = 2,
 987         },
 988         .s = {
 989                 .src_sel_shift = 0,
 990                 .parent_map = gcc_pxo_pll8_map,
 991         },
 992         .freq_tbl = clk_tbl_gsbi_qup,
 993         .clkr = {
 994                 .enable_reg = 0x2a4c,
 995                 .enable_mask = BIT(11),
 996                 .hw.init = &(struct clk_init_data){
 997                         .name = "gsbi5_qup_src",
 998                         .parent_names = gcc_pxo_pll8,
 999                         .num_parents = 2,
1000                         .ops = &clk_rcg_ops,
1001                         .flags = CLK_SET_PARENT_GATE,
1002                 },
1003         },
1004 };
1005
1006 static struct clk_branch gsbi5_qup_clk = {
1007         .halt_reg = 0x2fd0,
1008         .halt_bit = 20,
1009         .clkr = {
1010                 .enable_reg = 0x2a4c,
1011                 .enable_mask = BIT(9),
1012                 .hw.init = &(struct clk_init_data){
1013                         .name = "gsbi5_qup_clk",
1014                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
1015                         .num_parents = 1,
1016                         .ops = &clk_branch_ops,
1017                         .flags = CLK_SET_RATE_PARENT,
1018                 },
1019         },
1020 };
1021
1022 static struct clk_rcg gsbi6_qup_src = {
1023         .ns_reg = 0x2a6c,
1024         .md_reg = 0x2a68,
1025         .mn = {
1026                 .mnctr_en_bit = 8,
1027                 .mnctr_reset_bit = 7,
1028                 .mnctr_mode_shift = 5,
1029                 .n_val_shift = 16,
1030                 .m_val_shift = 16,
1031                 .width = 8,
1032         },
1033         .p = {
1034                 .pre_div_shift = 3,
1035                 .pre_div_width = 2,
1036         },
1037         .s = {
1038                 .src_sel_shift = 0,
1039                 .parent_map = gcc_pxo_pll8_map,
1040         },
1041         .freq_tbl = clk_tbl_gsbi_qup,
1042         .clkr = {
1043                 .enable_reg = 0x2a6c,
1044                 .enable_mask = BIT(11),
1045                 .hw.init = &(struct clk_init_data){
1046                         .name = "gsbi6_qup_src",
1047                         .parent_names = gcc_pxo_pll8,
1048                         .num_parents = 2,
1049                         .ops = &clk_rcg_ops,
1050                         .flags = CLK_SET_PARENT_GATE,
1051                 },
1052         },
1053 };
1054
1055 static struct clk_branch gsbi6_qup_clk = {
1056         .halt_reg = 0x2fd0,
1057         .halt_bit = 16,
1058         .clkr = {
1059                 .enable_reg = 0x2a6c,
1060                 .enable_mask = BIT(9),
1061                 .hw.init = &(struct clk_init_data){
1062                         .name = "gsbi6_qup_clk",
1063                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
1064                         .num_parents = 1,
1065                         .ops = &clk_branch_ops,
1066                         .flags = CLK_SET_RATE_PARENT,
1067                 },
1068         },
1069 };
1070
1071 static struct clk_rcg gsbi7_qup_src = {
1072         .ns_reg = 0x2a8c,
1073         .md_reg = 0x2a88,
1074         .mn = {
1075                 .mnctr_en_bit = 8,
1076                 .mnctr_reset_bit = 7,
1077                 .mnctr_mode_shift = 5,
1078                 .n_val_shift = 16,
1079                 .m_val_shift = 16,
1080                 .width = 8,
1081         },
1082         .p = {
1083                 .pre_div_shift = 3,
1084                 .pre_div_width = 2,
1085         },
1086         .s = {
1087                 .src_sel_shift = 0,
1088                 .parent_map = gcc_pxo_pll8_map,
1089         },
1090         .freq_tbl = clk_tbl_gsbi_qup,
1091         .clkr = {
1092                 .enable_reg = 0x2a8c,
1093                 .enable_mask = BIT(11),
1094                 .hw.init = &(struct clk_init_data){
1095                         .name = "gsbi7_qup_src",
1096                         .parent_names = gcc_pxo_pll8,
1097                         .num_parents = 2,
1098                         .ops = &clk_rcg_ops,
1099                         .flags = CLK_SET_PARENT_GATE,
1100                 },
1101         },
1102 };
1103
1104 static struct clk_branch gsbi7_qup_clk = {
1105         .halt_reg = 0x2fd0,
1106         .halt_bit = 12,
1107         .clkr = {
1108                 .enable_reg = 0x2a8c,
1109                 .enable_mask = BIT(9),
1110                 .hw.init = &(struct clk_init_data){
1111                         .name = "gsbi7_qup_clk",
1112                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
1113                         .num_parents = 1,
1114                         .ops = &clk_branch_ops,
1115                         .flags = CLK_SET_RATE_PARENT,
1116                 },
1117         },
1118 };
1119
1120 static struct clk_rcg gsbi8_qup_src = {
1121         .ns_reg = 0x2aac,
1122         .md_reg = 0x2aa8,
1123         .mn = {
1124                 .mnctr_en_bit = 8,
1125                 .mnctr_reset_bit = 7,
1126                 .mnctr_mode_shift = 5,
1127                 .n_val_shift = 16,
1128                 .m_val_shift = 16,
1129                 .width = 8,
1130         },
1131         .p = {
1132                 .pre_div_shift = 3,
1133                 .pre_div_width = 2,
1134         },
1135         .s = {
1136                 .src_sel_shift = 0,
1137                 .parent_map = gcc_pxo_pll8_map,
1138         },
1139         .freq_tbl = clk_tbl_gsbi_qup,
1140         .clkr = {
1141                 .enable_reg = 0x2aac,
1142                 .enable_mask = BIT(11),
1143                 .hw.init = &(struct clk_init_data){
1144                         .name = "gsbi8_qup_src",
1145                         .parent_names = gcc_pxo_pll8,
1146                         .num_parents = 2,
1147                         .ops = &clk_rcg_ops,
1148                         .flags = CLK_SET_PARENT_GATE,
1149                 },
1150         },
1151 };
1152
1153 static struct clk_branch gsbi8_qup_clk = {
1154         .halt_reg = 0x2fd0,
1155         .halt_bit = 8,
1156         .clkr = {
1157                 .enable_reg = 0x2aac,
1158                 .enable_mask = BIT(9),
1159                 .hw.init = &(struct clk_init_data){
1160                         .name = "gsbi8_qup_clk",
1161                         .parent_names = (const char *[]){ "gsbi8_qup_src" },
1162                         .num_parents = 1,
1163                         .ops = &clk_branch_ops,
1164                         .flags = CLK_SET_RATE_PARENT,
1165                 },
1166         },
1167 };
1168
1169 static struct clk_rcg gsbi9_qup_src = {
1170         .ns_reg = 0x2acc,
1171         .md_reg = 0x2ac8,
1172         .mn = {
1173                 .mnctr_en_bit = 8,
1174                 .mnctr_reset_bit = 7,
1175                 .mnctr_mode_shift = 5,
1176                 .n_val_shift = 16,
1177                 .m_val_shift = 16,
1178                 .width = 8,
1179         },
1180         .p = {
1181                 .pre_div_shift = 3,
1182                 .pre_div_width = 2,
1183         },
1184         .s = {
1185                 .src_sel_shift = 0,
1186                 .parent_map = gcc_pxo_pll8_map,
1187         },
1188         .freq_tbl = clk_tbl_gsbi_qup,
1189         .clkr = {
1190                 .enable_reg = 0x2acc,
1191                 .enable_mask = BIT(11),
1192                 .hw.init = &(struct clk_init_data){
1193                         .name = "gsbi9_qup_src",
1194                         .parent_names = gcc_pxo_pll8,
1195                         .num_parents = 2,
1196                         .ops = &clk_rcg_ops,
1197                         .flags = CLK_SET_PARENT_GATE,
1198                 },
1199         },
1200 };
1201
1202 static struct clk_branch gsbi9_qup_clk = {
1203         .halt_reg = 0x2fd0,
1204         .halt_bit = 4,
1205         .clkr = {
1206                 .enable_reg = 0x2acc,
1207                 .enable_mask = BIT(9),
1208                 .hw.init = &(struct clk_init_data){
1209                         .name = "gsbi9_qup_clk",
1210                         .parent_names = (const char *[]){ "gsbi9_qup_src" },
1211                         .num_parents = 1,
1212                         .ops = &clk_branch_ops,
1213                         .flags = CLK_SET_RATE_PARENT,
1214                 },
1215         },
1216 };
1217
1218 static struct clk_rcg gsbi10_qup_src = {
1219         .ns_reg = 0x2aec,
1220         .md_reg = 0x2ae8,
1221         .mn = {
1222                 .mnctr_en_bit = 8,
1223                 .mnctr_reset_bit = 7,
1224                 .mnctr_mode_shift = 5,
1225                 .n_val_shift = 16,
1226                 .m_val_shift = 16,
1227                 .width = 8,
1228         },
1229         .p = {
1230                 .pre_div_shift = 3,
1231                 .pre_div_width = 2,
1232         },
1233         .s = {
1234                 .src_sel_shift = 0,
1235                 .parent_map = gcc_pxo_pll8_map,
1236         },
1237         .freq_tbl = clk_tbl_gsbi_qup,
1238         .clkr = {
1239                 .enable_reg = 0x2aec,
1240                 .enable_mask = BIT(11),
1241                 .hw.init = &(struct clk_init_data){
1242                         .name = "gsbi10_qup_src",
1243                         .parent_names = gcc_pxo_pll8,
1244                         .num_parents = 2,
1245                         .ops = &clk_rcg_ops,
1246                         .flags = CLK_SET_PARENT_GATE,
1247                 },
1248         },
1249 };
1250
1251 static struct clk_branch gsbi10_qup_clk = {
1252         .halt_reg = 0x2fd0,
1253         .halt_bit = 0,
1254         .clkr = {
1255                 .enable_reg = 0x2aec,
1256                 .enable_mask = BIT(9),
1257                 .hw.init = &(struct clk_init_data){
1258                         .name = "gsbi10_qup_clk",
1259                         .parent_names = (const char *[]){ "gsbi10_qup_src" },
1260                         .num_parents = 1,
1261                         .ops = &clk_branch_ops,
1262                         .flags = CLK_SET_RATE_PARENT,
1263                 },
1264         },
1265 };
1266
1267 static struct clk_rcg gsbi11_qup_src = {
1268         .ns_reg = 0x2b0c,
1269         .md_reg = 0x2b08,
1270         .mn = {
1271                 .mnctr_en_bit = 8,
1272                 .mnctr_reset_bit = 7,
1273                 .mnctr_mode_shift = 5,
1274                 .n_val_shift = 16,
1275                 .m_val_shift = 16,
1276                 .width = 8,
1277         },
1278         .p = {
1279                 .pre_div_shift = 3,
1280                 .pre_div_width = 2,
1281         },
1282         .s = {
1283                 .src_sel_shift = 0,
1284                 .parent_map = gcc_pxo_pll8_map,
1285         },
1286         .freq_tbl = clk_tbl_gsbi_qup,
1287         .clkr = {
1288                 .enable_reg = 0x2b0c,
1289                 .enable_mask = BIT(11),
1290                 .hw.init = &(struct clk_init_data){
1291                         .name = "gsbi11_qup_src",
1292                         .parent_names = gcc_pxo_pll8,
1293                         .num_parents = 2,
1294                         .ops = &clk_rcg_ops,
1295                         .flags = CLK_SET_PARENT_GATE,
1296                 },
1297         },
1298 };
1299
1300 static struct clk_branch gsbi11_qup_clk = {
1301         .halt_reg = 0x2fd4,
1302         .halt_bit = 15,
1303         .clkr = {
1304                 .enable_reg = 0x2b0c,
1305                 .enable_mask = BIT(9),
1306                 .hw.init = &(struct clk_init_data){
1307                         .name = "gsbi11_qup_clk",
1308                         .parent_names = (const char *[]){ "gsbi11_qup_src" },
1309                         .num_parents = 1,
1310                         .ops = &clk_branch_ops,
1311                         .flags = CLK_SET_RATE_PARENT,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_rcg gsbi12_qup_src = {
1317         .ns_reg = 0x2b2c,
1318         .md_reg = 0x2b28,
1319         .mn = {
1320                 .mnctr_en_bit = 8,
1321                 .mnctr_reset_bit = 7,
1322                 .mnctr_mode_shift = 5,
1323                 .n_val_shift = 16,
1324                 .m_val_shift = 16,
1325                 .width = 8,
1326         },
1327         .p = {
1328                 .pre_div_shift = 3,
1329                 .pre_div_width = 2,
1330         },
1331         .s = {
1332                 .src_sel_shift = 0,
1333                 .parent_map = gcc_pxo_pll8_map,
1334         },
1335         .freq_tbl = clk_tbl_gsbi_qup,
1336         .clkr = {
1337                 .enable_reg = 0x2b2c,
1338                 .enable_mask = BIT(11),
1339                 .hw.init = &(struct clk_init_data){
1340                         .name = "gsbi12_qup_src",
1341                         .parent_names = gcc_pxo_pll8,
1342                         .num_parents = 2,
1343                         .ops = &clk_rcg_ops,
1344                         .flags = CLK_SET_PARENT_GATE,
1345                 },
1346         },
1347 };
1348
1349 static struct clk_branch gsbi12_qup_clk = {
1350         .halt_reg = 0x2fd4,
1351         .halt_bit = 11,
1352         .clkr = {
1353                 .enable_reg = 0x2b2c,
1354                 .enable_mask = BIT(9),
1355                 .hw.init = &(struct clk_init_data){
1356                         .name = "gsbi12_qup_clk",
1357                         .parent_names = (const char *[]){ "gsbi12_qup_src" },
1358                         .num_parents = 1,
1359                         .ops = &clk_branch_ops,
1360                         .flags = CLK_SET_RATE_PARENT,
1361                 },
1362         },
1363 };
1364
1365 static const struct freq_tbl clk_tbl_gp[] = {
1366         { 9600000, P_CXO,  2, 0, 0 },
1367         { 13500000, P_PXO,  2, 0, 0 },
1368         { 19200000, P_CXO,  1, 0, 0 },
1369         { 27000000, P_PXO,  1, 0, 0 },
1370         { 64000000, P_PLL8, 2, 1, 3 },
1371         { 76800000, P_PLL8, 1, 1, 5 },
1372         { 96000000, P_PLL8, 4, 0, 0 },
1373         { 128000000, P_PLL8, 3, 0, 0 },
1374         { 192000000, P_PLL8, 2, 0, 0 },
1375         { }
1376 };
1377
1378 static struct clk_rcg gp0_src = {
1379         .ns_reg = 0x2d24,
1380         .md_reg = 0x2d00,
1381         .mn = {
1382                 .mnctr_en_bit = 8,
1383                 .mnctr_reset_bit = 7,
1384                 .mnctr_mode_shift = 5,
1385                 .n_val_shift = 16,
1386                 .m_val_shift = 16,
1387                 .width = 8,
1388         },
1389         .p = {
1390                 .pre_div_shift = 3,
1391                 .pre_div_width = 2,
1392         },
1393         .s = {
1394                 .src_sel_shift = 0,
1395                 .parent_map = gcc_pxo_pll8_cxo_map,
1396         },
1397         .freq_tbl = clk_tbl_gp,
1398         .clkr = {
1399                 .enable_reg = 0x2d24,
1400                 .enable_mask = BIT(11),
1401                 .hw.init = &(struct clk_init_data){
1402                         .name = "gp0_src",
1403                         .parent_names = gcc_pxo_pll8_cxo,
1404                         .num_parents = 3,
1405                         .ops = &clk_rcg_ops,
1406                         .flags = CLK_SET_PARENT_GATE,
1407                 },
1408         }
1409 };
1410
1411 static struct clk_branch gp0_clk = {
1412         .halt_reg = 0x2fd8,
1413         .halt_bit = 7,
1414         .clkr = {
1415                 .enable_reg = 0x2d24,
1416                 .enable_mask = BIT(9),
1417                 .hw.init = &(struct clk_init_data){
1418                         .name = "gp0_clk",
1419                         .parent_names = (const char *[]){ "gp0_src" },
1420                         .num_parents = 1,
1421                         .ops = &clk_branch_ops,
1422                         .flags = CLK_SET_RATE_PARENT,
1423                 },
1424         },
1425 };
1426
1427 static struct clk_rcg gp1_src = {
1428         .ns_reg = 0x2d44,
1429         .md_reg = 0x2d40,
1430         .mn = {
1431                 .mnctr_en_bit = 8,
1432                 .mnctr_reset_bit = 7,
1433                 .mnctr_mode_shift = 5,
1434                 .n_val_shift = 16,
1435                 .m_val_shift = 16,
1436                 .width = 8,
1437         },
1438         .p = {
1439                 .pre_div_shift = 3,
1440                 .pre_div_width = 2,
1441         },
1442         .s = {
1443                 .src_sel_shift = 0,
1444                 .parent_map = gcc_pxo_pll8_cxo_map,
1445         },
1446         .freq_tbl = clk_tbl_gp,
1447         .clkr = {
1448                 .enable_reg = 0x2d44,
1449                 .enable_mask = BIT(11),
1450                 .hw.init = &(struct clk_init_data){
1451                         .name = "gp1_src",
1452                         .parent_names = gcc_pxo_pll8_cxo,
1453                         .num_parents = 3,
1454                         .ops = &clk_rcg_ops,
1455                         .flags = CLK_SET_RATE_GATE,
1456                 },
1457         }
1458 };
1459
1460 static struct clk_branch gp1_clk = {
1461         .halt_reg = 0x2fd8,
1462         .halt_bit = 6,
1463         .clkr = {
1464                 .enable_reg = 0x2d44,
1465                 .enable_mask = BIT(9),
1466                 .hw.init = &(struct clk_init_data){
1467                         .name = "gp1_clk",
1468                         .parent_names = (const char *[]){ "gp1_src" },
1469                         .num_parents = 1,
1470                         .ops = &clk_branch_ops,
1471                         .flags = CLK_SET_RATE_PARENT,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_rcg gp2_src = {
1477         .ns_reg = 0x2d64,
1478         .md_reg = 0x2d60,
1479         .mn = {
1480                 .mnctr_en_bit = 8,
1481                 .mnctr_reset_bit = 7,
1482                 .mnctr_mode_shift = 5,
1483                 .n_val_shift = 16,
1484                 .m_val_shift = 16,
1485                 .width = 8,
1486         },
1487         .p = {
1488                 .pre_div_shift = 3,
1489                 .pre_div_width = 2,
1490         },
1491         .s = {
1492                 .src_sel_shift = 0,
1493                 .parent_map = gcc_pxo_pll8_cxo_map,
1494         },
1495         .freq_tbl = clk_tbl_gp,
1496         .clkr = {
1497                 .enable_reg = 0x2d64,
1498                 .enable_mask = BIT(11),
1499                 .hw.init = &(struct clk_init_data){
1500                         .name = "gp2_src",
1501                         .parent_names = gcc_pxo_pll8_cxo,
1502                         .num_parents = 3,
1503                         .ops = &clk_rcg_ops,
1504                         .flags = CLK_SET_RATE_GATE,
1505                 },
1506         }
1507 };
1508
1509 static struct clk_branch gp2_clk = {
1510         .halt_reg = 0x2fd8,
1511         .halt_bit = 5,
1512         .clkr = {
1513                 .enable_reg = 0x2d64,
1514                 .enable_mask = BIT(9),
1515                 .hw.init = &(struct clk_init_data){
1516                         .name = "gp2_clk",
1517                         .parent_names = (const char *[]){ "gp2_src" },
1518                         .num_parents = 1,
1519                         .ops = &clk_branch_ops,
1520                         .flags = CLK_SET_RATE_PARENT,
1521                 },
1522         },
1523 };
1524
1525 static struct clk_branch pmem_clk = {
1526         .hwcg_reg = 0x25a0,
1527         .hwcg_bit = 6,
1528         .halt_reg = 0x2fc8,
1529         .halt_bit = 20,
1530         .clkr = {
1531                 .enable_reg = 0x25a0,
1532                 .enable_mask = BIT(4),
1533                 .hw.init = &(struct clk_init_data){
1534                         .name = "pmem_clk",
1535                         .ops = &clk_branch_ops,
1536                         .flags = CLK_IS_ROOT,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_rcg prng_src = {
1542         .ns_reg = 0x2e80,
1543         .p = {
1544                 .pre_div_shift = 3,
1545                 .pre_div_width = 4,
1546         },
1547         .s = {
1548                 .src_sel_shift = 0,
1549                 .parent_map = gcc_pxo_pll8_map,
1550         },
1551         .clkr = {
1552                 .hw.init = &(struct clk_init_data){
1553                         .name = "prng_src",
1554                         .parent_names = gcc_pxo_pll8,
1555                         .num_parents = 2,
1556                         .ops = &clk_rcg_ops,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch prng_clk = {
1562         .halt_reg = 0x2fd8,
1563         .halt_check = BRANCH_HALT_VOTED,
1564         .halt_bit = 10,
1565         .clkr = {
1566                 .enable_reg = 0x3080,
1567                 .enable_mask = BIT(10),
1568                 .hw.init = &(struct clk_init_data){
1569                         .name = "prng_clk",
1570                         .parent_names = (const char *[]){ "prng_src" },
1571                         .num_parents = 1,
1572                         .ops = &clk_branch_ops,
1573                 },
1574         },
1575 };
1576
1577 static const struct freq_tbl clk_tbl_sdc[] = {
1578         {    144000, P_PXO,   3, 2, 125 },
1579         {    400000, P_PLL8,  4, 1, 240 },
1580         {  16000000, P_PLL8,  4, 1,   6 },
1581         {  17070000, P_PLL8,  1, 2,  45 },
1582         {  20210000, P_PLL8,  1, 1,  19 },
1583         {  24000000, P_PLL8,  4, 1,   4 },
1584         {  48000000, P_PLL8,  4, 1,   2 },
1585         {  64000000, P_PLL8,  3, 1,   2 },
1586         {  96000000, P_PLL8,  4, 0,   0 },
1587         { 192000000, P_PLL8,  2, 0,   0 },
1588         { }
1589 };
1590
1591 static struct clk_rcg sdc1_src = {
1592         .ns_reg = 0x282c,
1593         .md_reg = 0x2828,
1594         .mn = {
1595                 .mnctr_en_bit = 8,
1596                 .mnctr_reset_bit = 7,
1597                 .mnctr_mode_shift = 5,
1598                 .n_val_shift = 16,
1599                 .m_val_shift = 16,
1600                 .width = 8,
1601         },
1602         .p = {
1603                 .pre_div_shift = 3,
1604                 .pre_div_width = 2,
1605         },
1606         .s = {
1607                 .src_sel_shift = 0,
1608                 .parent_map = gcc_pxo_pll8_map,
1609         },
1610         .freq_tbl = clk_tbl_sdc,
1611         .clkr = {
1612                 .enable_reg = 0x282c,
1613                 .enable_mask = BIT(11),
1614                 .hw.init = &(struct clk_init_data){
1615                         .name = "sdc1_src",
1616                         .parent_names = gcc_pxo_pll8,
1617                         .num_parents = 2,
1618                         .ops = &clk_rcg_ops,
1619                         .flags = CLK_SET_RATE_GATE,
1620                 },
1621         }
1622 };
1623
1624 static struct clk_branch sdc1_clk = {
1625         .halt_reg = 0x2fc8,
1626         .halt_bit = 6,
1627         .clkr = {
1628                 .enable_reg = 0x282c,
1629                 .enable_mask = BIT(9),
1630                 .hw.init = &(struct clk_init_data){
1631                         .name = "sdc1_clk",
1632                         .parent_names = (const char *[]){ "sdc1_src" },
1633                         .num_parents = 1,
1634                         .ops = &clk_branch_ops,
1635                         .flags = CLK_SET_RATE_PARENT,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_rcg sdc2_src = {
1641         .ns_reg = 0x284c,
1642         .md_reg = 0x2848,
1643         .mn = {
1644                 .mnctr_en_bit = 8,
1645                 .mnctr_reset_bit = 7,
1646                 .mnctr_mode_shift = 5,
1647                 .n_val_shift = 16,
1648                 .m_val_shift = 16,
1649                 .width = 8,
1650         },
1651         .p = {
1652                 .pre_div_shift = 3,
1653                 .pre_div_width = 2,
1654         },
1655         .s = {
1656                 .src_sel_shift = 0,
1657                 .parent_map = gcc_pxo_pll8_map,
1658         },
1659         .freq_tbl = clk_tbl_sdc,
1660         .clkr = {
1661                 .enable_reg = 0x284c,
1662                 .enable_mask = BIT(11),
1663                 .hw.init = &(struct clk_init_data){
1664                         .name = "sdc2_src",
1665                         .parent_names = gcc_pxo_pll8,
1666                         .num_parents = 2,
1667                         .ops = &clk_rcg_ops,
1668                         .flags = CLK_SET_RATE_GATE,
1669                 },
1670         }
1671 };
1672
1673 static struct clk_branch sdc2_clk = {
1674         .halt_reg = 0x2fc8,
1675         .halt_bit = 5,
1676         .clkr = {
1677                 .enable_reg = 0x284c,
1678                 .enable_mask = BIT(9),
1679                 .hw.init = &(struct clk_init_data){
1680                         .name = "sdc2_clk",
1681                         .parent_names = (const char *[]){ "sdc2_src" },
1682                         .num_parents = 1,
1683                         .ops = &clk_branch_ops,
1684                         .flags = CLK_SET_RATE_PARENT,
1685                 },
1686         },
1687 };
1688
1689 static struct clk_rcg sdc3_src = {
1690         .ns_reg = 0x286c,
1691         .md_reg = 0x2868,
1692         .mn = {
1693                 .mnctr_en_bit = 8,
1694                 .mnctr_reset_bit = 7,
1695                 .mnctr_mode_shift = 5,
1696                 .n_val_shift = 16,
1697                 .m_val_shift = 16,
1698                 .width = 8,
1699         },
1700         .p = {
1701                 .pre_div_shift = 3,
1702                 .pre_div_width = 2,
1703         },
1704         .s = {
1705                 .src_sel_shift = 0,
1706                 .parent_map = gcc_pxo_pll8_map,
1707         },
1708         .freq_tbl = clk_tbl_sdc,
1709         .clkr = {
1710                 .enable_reg = 0x286c,
1711                 .enable_mask = BIT(11),
1712                 .hw.init = &(struct clk_init_data){
1713                         .name = "sdc3_src",
1714                         .parent_names = gcc_pxo_pll8,
1715                         .num_parents = 2,
1716                         .ops = &clk_rcg_ops,
1717                         .flags = CLK_SET_RATE_GATE,
1718                 },
1719         }
1720 };
1721
1722 static struct clk_branch sdc3_clk = {
1723         .halt_reg = 0x2fc8,
1724         .halt_bit = 4,
1725         .clkr = {
1726                 .enable_reg = 0x286c,
1727                 .enable_mask = BIT(9),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "sdc3_clk",
1730                         .parent_names = (const char *[]){ "sdc3_src" },
1731                         .num_parents = 1,
1732                         .ops = &clk_branch_ops,
1733                         .flags = CLK_SET_RATE_PARENT,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_rcg sdc4_src = {
1739         .ns_reg = 0x288c,
1740         .md_reg = 0x2888,
1741         .mn = {
1742                 .mnctr_en_bit = 8,
1743                 .mnctr_reset_bit = 7,
1744                 .mnctr_mode_shift = 5,
1745                 .n_val_shift = 16,
1746                 .m_val_shift = 16,
1747                 .width = 8,
1748         },
1749         .p = {
1750                 .pre_div_shift = 3,
1751                 .pre_div_width = 2,
1752         },
1753         .s = {
1754                 .src_sel_shift = 0,
1755                 .parent_map = gcc_pxo_pll8_map,
1756         },
1757         .freq_tbl = clk_tbl_sdc,
1758         .clkr = {
1759                 .enable_reg = 0x288c,
1760                 .enable_mask = BIT(11),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "sdc4_src",
1763                         .parent_names = gcc_pxo_pll8,
1764                         .num_parents = 2,
1765                         .ops = &clk_rcg_ops,
1766                         .flags = CLK_SET_RATE_GATE,
1767                 },
1768         }
1769 };
1770
1771 static struct clk_branch sdc4_clk = {
1772         .halt_reg = 0x2fc8,
1773         .halt_bit = 3,
1774         .clkr = {
1775                 .enable_reg = 0x288c,
1776                 .enable_mask = BIT(9),
1777                 .hw.init = &(struct clk_init_data){
1778                         .name = "sdc4_clk",
1779                         .parent_names = (const char *[]){ "sdc4_src" },
1780                         .num_parents = 1,
1781                         .ops = &clk_branch_ops,
1782                         .flags = CLK_SET_RATE_PARENT,
1783                 },
1784         },
1785 };
1786
1787 static struct clk_rcg sdc5_src = {
1788         .ns_reg = 0x28ac,
1789         .md_reg = 0x28a8,
1790         .mn = {
1791                 .mnctr_en_bit = 8,
1792                 .mnctr_reset_bit = 7,
1793                 .mnctr_mode_shift = 5,
1794                 .n_val_shift = 16,
1795                 .m_val_shift = 16,
1796                 .width = 8,
1797         },
1798         .p = {
1799                 .pre_div_shift = 3,
1800                 .pre_div_width = 2,
1801         },
1802         .s = {
1803                 .src_sel_shift = 0,
1804                 .parent_map = gcc_pxo_pll8_map,
1805         },
1806         .freq_tbl = clk_tbl_sdc,
1807         .clkr = {
1808                 .enable_reg = 0x28ac,
1809                 .enable_mask = BIT(11),
1810                 .hw.init = &(struct clk_init_data){
1811                         .name = "sdc5_src",
1812                         .parent_names = gcc_pxo_pll8,
1813                         .num_parents = 2,
1814                         .ops = &clk_rcg_ops,
1815                         .flags = CLK_SET_RATE_GATE,
1816                 },
1817         }
1818 };
1819
1820 static struct clk_branch sdc5_clk = {
1821         .halt_reg = 0x2fc8,
1822         .halt_bit = 2,
1823         .clkr = {
1824                 .enable_reg = 0x28ac,
1825                 .enable_mask = BIT(9),
1826                 .hw.init = &(struct clk_init_data){
1827                         .name = "sdc5_clk",
1828                         .parent_names = (const char *[]){ "sdc5_src" },
1829                         .num_parents = 1,
1830                         .ops = &clk_branch_ops,
1831                         .flags = CLK_SET_RATE_PARENT,
1832                 },
1833         },
1834 };
1835
1836 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1837         { 105000, P_PXO,  1, 1, 256 },
1838         { }
1839 };
1840
1841 static struct clk_rcg tsif_ref_src = {
1842         .ns_reg = 0x2710,
1843         .md_reg = 0x270c,
1844         .mn = {
1845                 .mnctr_en_bit = 8,
1846                 .mnctr_reset_bit = 7,
1847                 .mnctr_mode_shift = 5,
1848                 .n_val_shift = 16,
1849                 .m_val_shift = 16,
1850                 .width = 16,
1851         },
1852         .p = {
1853                 .pre_div_shift = 3,
1854                 .pre_div_width = 2,
1855         },
1856         .s = {
1857                 .src_sel_shift = 0,
1858                 .parent_map = gcc_pxo_pll8_map,
1859         },
1860         .freq_tbl = clk_tbl_tsif_ref,
1861         .clkr = {
1862                 .enable_reg = 0x2710,
1863                 .enable_mask = BIT(11),
1864                 .hw.init = &(struct clk_init_data){
1865                         .name = "tsif_ref_src",
1866                         .parent_names = gcc_pxo_pll8,
1867                         .num_parents = 2,
1868                         .ops = &clk_rcg_ops,
1869                         .flags = CLK_SET_RATE_GATE,
1870                 },
1871         }
1872 };
1873
1874 static struct clk_branch tsif_ref_clk = {
1875         .halt_reg = 0x2fd4,
1876         .halt_bit = 5,
1877         .clkr = {
1878                 .enable_reg = 0x2710,
1879                 .enable_mask = BIT(9),
1880                 .hw.init = &(struct clk_init_data){
1881                         .name = "tsif_ref_clk",
1882                         .parent_names = (const char *[]){ "tsif_ref_src" },
1883                         .num_parents = 1,
1884                         .ops = &clk_branch_ops,
1885                         .flags = CLK_SET_RATE_PARENT,
1886                 },
1887         },
1888 };
1889
1890 static const struct freq_tbl clk_tbl_usb[] = {
1891         { 60000000, P_PLL8, 1, 5, 32 },
1892         { }
1893 };
1894
1895 static struct clk_rcg usb_hs1_xcvr_src = {
1896         .ns_reg = 0x290c,
1897         .md_reg = 0x2908,
1898         .mn = {
1899                 .mnctr_en_bit = 8,
1900                 .mnctr_reset_bit = 7,
1901                 .mnctr_mode_shift = 5,
1902                 .n_val_shift = 16,
1903                 .m_val_shift = 16,
1904                 .width = 8,
1905         },
1906         .p = {
1907                 .pre_div_shift = 3,
1908                 .pre_div_width = 2,
1909         },
1910         .s = {
1911                 .src_sel_shift = 0,
1912                 .parent_map = gcc_pxo_pll8_map,
1913         },
1914         .freq_tbl = clk_tbl_usb,
1915         .clkr = {
1916                 .enable_reg = 0x290c,
1917                 .enable_mask = BIT(11),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "usb_hs1_xcvr_src",
1920                         .parent_names = gcc_pxo_pll8,
1921                         .num_parents = 2,
1922                         .ops = &clk_rcg_ops,
1923                         .flags = CLK_SET_RATE_GATE,
1924                 },
1925         }
1926 };
1927
1928 static struct clk_branch usb_hs1_xcvr_clk = {
1929         .halt_reg = 0x2fc8,
1930         .halt_bit = 0,
1931         .clkr = {
1932                 .enable_reg = 0x290c,
1933                 .enable_mask = BIT(9),
1934                 .hw.init = &(struct clk_init_data){
1935                         .name = "usb_hs1_xcvr_clk",
1936                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1937                         .num_parents = 1,
1938                         .ops = &clk_branch_ops,
1939                         .flags = CLK_SET_RATE_PARENT,
1940                 },
1941         },
1942 };
1943
1944 static struct clk_rcg usb_hs3_xcvr_src = {
1945         .ns_reg = 0x370c,
1946         .md_reg = 0x3708,
1947         .mn = {
1948                 .mnctr_en_bit = 8,
1949                 .mnctr_reset_bit = 7,
1950                 .mnctr_mode_shift = 5,
1951                 .n_val_shift = 16,
1952                 .m_val_shift = 16,
1953                 .width = 8,
1954         },
1955         .p = {
1956                 .pre_div_shift = 3,
1957                 .pre_div_width = 2,
1958         },
1959         .s = {
1960                 .src_sel_shift = 0,
1961                 .parent_map = gcc_pxo_pll8_map,
1962         },
1963         .freq_tbl = clk_tbl_usb,
1964         .clkr = {
1965                 .enable_reg = 0x370c,
1966                 .enable_mask = BIT(11),
1967                 .hw.init = &(struct clk_init_data){
1968                         .name = "usb_hs3_xcvr_src",
1969                         .parent_names = gcc_pxo_pll8,
1970                         .num_parents = 2,
1971                         .ops = &clk_rcg_ops,
1972                         .flags = CLK_SET_RATE_GATE,
1973                 },
1974         }
1975 };
1976
1977 static struct clk_branch usb_hs3_xcvr_clk = {
1978         .halt_reg = 0x2fc8,
1979         .halt_bit = 30,
1980         .clkr = {
1981                 .enable_reg = 0x370c,
1982                 .enable_mask = BIT(9),
1983                 .hw.init = &(struct clk_init_data){
1984                         .name = "usb_hs3_xcvr_clk",
1985                         .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1986                         .num_parents = 1,
1987                         .ops = &clk_branch_ops,
1988                         .flags = CLK_SET_RATE_PARENT,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_rcg usb_hs4_xcvr_src = {
1994         .ns_reg = 0x372c,
1995         .md_reg = 0x3728,
1996         .mn = {
1997                 .mnctr_en_bit = 8,
1998                 .mnctr_reset_bit = 7,
1999                 .mnctr_mode_shift = 5,
2000                 .n_val_shift = 16,
2001                 .m_val_shift = 16,
2002                 .width = 8,
2003         },
2004         .p = {
2005                 .pre_div_shift = 3,
2006                 .pre_div_width = 2,
2007         },
2008         .s = {
2009                 .src_sel_shift = 0,
2010                 .parent_map = gcc_pxo_pll8_map,
2011         },
2012         .freq_tbl = clk_tbl_usb,
2013         .clkr = {
2014                 .enable_reg = 0x372c,
2015                 .enable_mask = BIT(11),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "usb_hs4_xcvr_src",
2018                         .parent_names = gcc_pxo_pll8,
2019                         .num_parents = 2,
2020                         .ops = &clk_rcg_ops,
2021                         .flags = CLK_SET_RATE_GATE,
2022                 },
2023         }
2024 };
2025
2026 static struct clk_branch usb_hs4_xcvr_clk = {
2027         .halt_reg = 0x2fc8,
2028         .halt_bit = 2,
2029         .clkr = {
2030                 .enable_reg = 0x372c,
2031                 .enable_mask = BIT(9),
2032                 .hw.init = &(struct clk_init_data){
2033                         .name = "usb_hs4_xcvr_clk",
2034                         .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2035                         .num_parents = 1,
2036                         .ops = &clk_branch_ops,
2037                         .flags = CLK_SET_RATE_PARENT,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2043         .ns_reg = 0x2928,
2044         .md_reg = 0x2924,
2045         .mn = {
2046                 .mnctr_en_bit = 8,
2047                 .mnctr_reset_bit = 7,
2048                 .mnctr_mode_shift = 5,
2049                 .n_val_shift = 16,
2050                 .m_val_shift = 16,
2051                 .width = 8,
2052         },
2053         .p = {
2054                 .pre_div_shift = 3,
2055                 .pre_div_width = 2,
2056         },
2057         .s = {
2058                 .src_sel_shift = 0,
2059                 .parent_map = gcc_pxo_pll8_map,
2060         },
2061         .freq_tbl = clk_tbl_usb,
2062         .clkr = {
2063                 .enable_reg = 0x2928,
2064                 .enable_mask = BIT(11),
2065                 .hw.init = &(struct clk_init_data){
2066                         .name = "usb_hsic_xcvr_fs_src",
2067                         .parent_names = gcc_pxo_pll8,
2068                         .num_parents = 2,
2069                         .ops = &clk_rcg_ops,
2070                         .flags = CLK_SET_RATE_GATE,
2071                 },
2072         }
2073 };
2074
2075 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2076
2077 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2078         .halt_reg = 0x2fc8,
2079         .halt_bit = 2,
2080         .clkr = {
2081                 .enable_reg = 0x2928,
2082                 .enable_mask = BIT(9),
2083                 .hw.init = &(struct clk_init_data){
2084                         .name = "usb_hsic_xcvr_fs_clk",
2085                         .parent_names = usb_hsic_xcvr_fs_src_p,
2086                         .num_parents = 1,
2087                         .ops = &clk_branch_ops,
2088                         .flags = CLK_SET_RATE_PARENT,
2089                 },
2090         },
2091 };
2092
2093 static struct clk_branch usb_hsic_system_clk = {
2094         .halt_reg = 0x2fcc,
2095         .halt_bit = 24,
2096         .clkr = {
2097                 .enable_reg = 0x292c,
2098                 .enable_mask = BIT(4),
2099                 .hw.init = &(struct clk_init_data){
2100                         .parent_names = usb_hsic_xcvr_fs_src_p,
2101                         .num_parents = 1,
2102                         .name = "usb_hsic_system_clk",
2103                         .ops = &clk_branch_ops,
2104                         .flags = CLK_SET_RATE_PARENT,
2105                 },
2106         },
2107 };
2108
2109 static struct clk_branch usb_hsic_hsic_clk = {
2110         .halt_reg = 0x2fcc,
2111         .halt_bit = 19,
2112         .clkr = {
2113                 .enable_reg = 0x2b44,
2114                 .enable_mask = BIT(0),
2115                 .hw.init = &(struct clk_init_data){
2116                         .parent_names = (const char *[]){ "pll14_vote" },
2117                         .num_parents = 1,
2118                         .name = "usb_hsic_hsic_clk",
2119                         .ops = &clk_branch_ops,
2120                 },
2121         },
2122 };
2123
2124 static struct clk_branch usb_hsic_hsio_cal_clk = {
2125         .halt_reg = 0x2fcc,
2126         .halt_bit = 23,
2127         .clkr = {
2128                 .enable_reg = 0x2b48,
2129                 .enable_mask = BIT(0),
2130                 .hw.init = &(struct clk_init_data){
2131                         .name = "usb_hsic_hsio_cal_clk",
2132                         .ops = &clk_branch_ops,
2133                         .flags = CLK_IS_ROOT,
2134                 },
2135         },
2136 };
2137
2138 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2139         .ns_reg = 0x2968,
2140         .md_reg = 0x2964,
2141         .mn = {
2142                 .mnctr_en_bit = 8,
2143                 .mnctr_reset_bit = 7,
2144                 .mnctr_mode_shift = 5,
2145                 .n_val_shift = 16,
2146                 .m_val_shift = 16,
2147                 .width = 8,
2148         },
2149         .p = {
2150                 .pre_div_shift = 3,
2151                 .pre_div_width = 2,
2152         },
2153         .s = {
2154                 .src_sel_shift = 0,
2155                 .parent_map = gcc_pxo_pll8_map,
2156         },
2157         .freq_tbl = clk_tbl_usb,
2158         .clkr = {
2159                 .enable_reg = 0x2968,
2160                 .enable_mask = BIT(11),
2161                 .hw.init = &(struct clk_init_data){
2162                         .name = "usb_fs1_xcvr_fs_src",
2163                         .parent_names = gcc_pxo_pll8,
2164                         .num_parents = 2,
2165                         .ops = &clk_rcg_ops,
2166                         .flags = CLK_SET_RATE_GATE,
2167                 },
2168         }
2169 };
2170
2171 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2172
2173 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2174         .halt_reg = 0x2fcc,
2175         .halt_bit = 15,
2176         .clkr = {
2177                 .enable_reg = 0x2968,
2178                 .enable_mask = BIT(9),
2179                 .hw.init = &(struct clk_init_data){
2180                         .name = "usb_fs1_xcvr_fs_clk",
2181                         .parent_names = usb_fs1_xcvr_fs_src_p,
2182                         .num_parents = 1,
2183                         .ops = &clk_branch_ops,
2184                         .flags = CLK_SET_RATE_PARENT,
2185                 },
2186         },
2187 };
2188
2189 static struct clk_branch usb_fs1_system_clk = {
2190         .halt_reg = 0x2fcc,
2191         .halt_bit = 16,
2192         .clkr = {
2193                 .enable_reg = 0x296c,
2194                 .enable_mask = BIT(4),
2195                 .hw.init = &(struct clk_init_data){
2196                         .parent_names = usb_fs1_xcvr_fs_src_p,
2197                         .num_parents = 1,
2198                         .name = "usb_fs1_system_clk",
2199                         .ops = &clk_branch_ops,
2200                         .flags = CLK_SET_RATE_PARENT,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2206         .ns_reg = 0x2988,
2207         .md_reg = 0x2984,
2208         .mn = {
2209                 .mnctr_en_bit = 8,
2210                 .mnctr_reset_bit = 7,
2211                 .mnctr_mode_shift = 5,
2212                 .n_val_shift = 16,
2213                 .m_val_shift = 16,
2214                 .width = 8,
2215         },
2216         .p = {
2217                 .pre_div_shift = 3,
2218                 .pre_div_width = 2,
2219         },
2220         .s = {
2221                 .src_sel_shift = 0,
2222                 .parent_map = gcc_pxo_pll8_map,
2223         },
2224         .freq_tbl = clk_tbl_usb,
2225         .clkr = {
2226                 .enable_reg = 0x2988,
2227                 .enable_mask = BIT(11),
2228                 .hw.init = &(struct clk_init_data){
2229                         .name = "usb_fs2_xcvr_fs_src",
2230                         .parent_names = gcc_pxo_pll8,
2231                         .num_parents = 2,
2232                         .ops = &clk_rcg_ops,
2233                         .flags = CLK_SET_RATE_GATE,
2234                 },
2235         }
2236 };
2237
2238 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2239
2240 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2241         .halt_reg = 0x2fcc,
2242         .halt_bit = 12,
2243         .clkr = {
2244                 .enable_reg = 0x2988,
2245                 .enable_mask = BIT(9),
2246                 .hw.init = &(struct clk_init_data){
2247                         .name = "usb_fs2_xcvr_fs_clk",
2248                         .parent_names = usb_fs2_xcvr_fs_src_p,
2249                         .num_parents = 1,
2250                         .ops = &clk_branch_ops,
2251                         .flags = CLK_SET_RATE_PARENT,
2252                 },
2253         },
2254 };
2255
2256 static struct clk_branch usb_fs2_system_clk = {
2257         .halt_reg = 0x2fcc,
2258         .halt_bit = 13,
2259         .clkr = {
2260                 .enable_reg = 0x298c,
2261                 .enable_mask = BIT(4),
2262                 .hw.init = &(struct clk_init_data){
2263                         .name = "usb_fs2_system_clk",
2264                         .parent_names = usb_fs2_xcvr_fs_src_p,
2265                         .num_parents = 1,
2266                         .ops = &clk_branch_ops,
2267                         .flags = CLK_SET_RATE_PARENT,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch ce1_core_clk = {
2273         .hwcg_reg = 0x2724,
2274         .hwcg_bit = 6,
2275         .halt_reg = 0x2fd4,
2276         .halt_bit = 27,
2277         .clkr = {
2278                 .enable_reg = 0x2724,
2279                 .enable_mask = BIT(4),
2280                 .hw.init = &(struct clk_init_data){
2281                         .name = "ce1_core_clk",
2282                         .ops = &clk_branch_ops,
2283                         .flags = CLK_IS_ROOT,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch ce1_h_clk = {
2289         .halt_reg = 0x2fd4,
2290         .halt_bit = 1,
2291         .clkr = {
2292                 .enable_reg = 0x2720,
2293                 .enable_mask = BIT(4),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "ce1_h_clk",
2296                         .ops = &clk_branch_ops,
2297                         .flags = CLK_IS_ROOT,
2298                 },
2299         },
2300 };
2301
2302 static struct clk_branch dma_bam_h_clk = {
2303         .hwcg_reg = 0x25c0,
2304         .hwcg_bit = 6,
2305         .halt_reg = 0x2fc8,
2306         .halt_bit = 12,
2307         .clkr = {
2308                 .enable_reg = 0x25c0,
2309                 .enable_mask = BIT(4),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "dma_bam_h_clk",
2312                         .ops = &clk_branch_ops,
2313                         .flags = CLK_IS_ROOT,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch gsbi1_h_clk = {
2319         .hwcg_reg = 0x29c0,
2320         .hwcg_bit = 6,
2321         .halt_reg = 0x2fcc,
2322         .halt_bit = 11,
2323         .clkr = {
2324                 .enable_reg = 0x29c0,
2325                 .enable_mask = BIT(4),
2326                 .hw.init = &(struct clk_init_data){
2327                         .name = "gsbi1_h_clk",
2328                         .ops = &clk_branch_ops,
2329                         .flags = CLK_IS_ROOT,
2330                 },
2331         },
2332 };
2333
2334 static struct clk_branch gsbi2_h_clk = {
2335         .hwcg_reg = 0x29e0,
2336         .hwcg_bit = 6,
2337         .halt_reg = 0x2fcc,
2338         .halt_bit = 7,
2339         .clkr = {
2340                 .enable_reg = 0x29e0,
2341                 .enable_mask = BIT(4),
2342                 .hw.init = &(struct clk_init_data){
2343                         .name = "gsbi2_h_clk",
2344                         .ops = &clk_branch_ops,
2345                         .flags = CLK_IS_ROOT,
2346                 },
2347         },
2348 };
2349
2350 static struct clk_branch gsbi3_h_clk = {
2351         .hwcg_reg = 0x2a00,
2352         .hwcg_bit = 6,
2353         .halt_reg = 0x2fcc,
2354         .halt_bit = 3,
2355         .clkr = {
2356                 .enable_reg = 0x2a00,
2357                 .enable_mask = BIT(4),
2358                 .hw.init = &(struct clk_init_data){
2359                         .name = "gsbi3_h_clk",
2360                         .ops = &clk_branch_ops,
2361                         .flags = CLK_IS_ROOT,
2362                 },
2363         },
2364 };
2365
2366 static struct clk_branch gsbi4_h_clk = {
2367         .hwcg_reg = 0x2a20,
2368         .hwcg_bit = 6,
2369         .halt_reg = 0x2fd0,
2370         .halt_bit = 27,
2371         .clkr = {
2372                 .enable_reg = 0x2a20,
2373                 .enable_mask = BIT(4),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gsbi4_h_clk",
2376                         .ops = &clk_branch_ops,
2377                         .flags = CLK_IS_ROOT,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch gsbi5_h_clk = {
2383         .hwcg_reg = 0x2a40,
2384         .hwcg_bit = 6,
2385         .halt_reg = 0x2fd0,
2386         .halt_bit = 23,
2387         .clkr = {
2388                 .enable_reg = 0x2a40,
2389                 .enable_mask = BIT(4),
2390                 .hw.init = &(struct clk_init_data){
2391                         .name = "gsbi5_h_clk",
2392                         .ops = &clk_branch_ops,
2393                         .flags = CLK_IS_ROOT,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch gsbi6_h_clk = {
2399         .hwcg_reg = 0x2a60,
2400         .hwcg_bit = 6,
2401         .halt_reg = 0x2fd0,
2402         .halt_bit = 19,
2403         .clkr = {
2404                 .enable_reg = 0x2a60,
2405                 .enable_mask = BIT(4),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gsbi6_h_clk",
2408                         .ops = &clk_branch_ops,
2409                         .flags = CLK_IS_ROOT,
2410                 },
2411         },
2412 };
2413
2414 static struct clk_branch gsbi7_h_clk = {
2415         .hwcg_reg = 0x2a80,
2416         .hwcg_bit = 6,
2417         .halt_reg = 0x2fd0,
2418         .halt_bit = 15,
2419         .clkr = {
2420                 .enable_reg = 0x2a80,
2421                 .enable_mask = BIT(4),
2422                 .hw.init = &(struct clk_init_data){
2423                         .name = "gsbi7_h_clk",
2424                         .ops = &clk_branch_ops,
2425                         .flags = CLK_IS_ROOT,
2426                 },
2427         },
2428 };
2429
2430 static struct clk_branch gsbi8_h_clk = {
2431         .hwcg_reg = 0x2aa0,
2432         .hwcg_bit = 6,
2433         .halt_reg = 0x2fd0,
2434         .halt_bit = 11,
2435         .clkr = {
2436                 .enable_reg = 0x2aa0,
2437                 .enable_mask = BIT(4),
2438                 .hw.init = &(struct clk_init_data){
2439                         .name = "gsbi8_h_clk",
2440                         .ops = &clk_branch_ops,
2441                         .flags = CLK_IS_ROOT,
2442                 },
2443         },
2444 };
2445
2446 static struct clk_branch gsbi9_h_clk = {
2447         .hwcg_reg = 0x2ac0,
2448         .hwcg_bit = 6,
2449         .halt_reg = 0x2fd0,
2450         .halt_bit = 7,
2451         .clkr = {
2452                 .enable_reg = 0x2ac0,
2453                 .enable_mask = BIT(4),
2454                 .hw.init = &(struct clk_init_data){
2455                         .name = "gsbi9_h_clk",
2456                         .ops = &clk_branch_ops,
2457                         .flags = CLK_IS_ROOT,
2458                 },
2459         },
2460 };
2461
2462 static struct clk_branch gsbi10_h_clk = {
2463         .hwcg_reg = 0x2ae0,
2464         .hwcg_bit = 6,
2465         .halt_reg = 0x2fd0,
2466         .halt_bit = 3,
2467         .clkr = {
2468                 .enable_reg = 0x2ae0,
2469                 .enable_mask = BIT(4),
2470                 .hw.init = &(struct clk_init_data){
2471                         .name = "gsbi10_h_clk",
2472                         .ops = &clk_branch_ops,
2473                         .flags = CLK_IS_ROOT,
2474                 },
2475         },
2476 };
2477
2478 static struct clk_branch gsbi11_h_clk = {
2479         .hwcg_reg = 0x2b00,
2480         .hwcg_bit = 6,
2481         .halt_reg = 0x2fd4,
2482         .halt_bit = 18,
2483         .clkr = {
2484                 .enable_reg = 0x2b00,
2485                 .enable_mask = BIT(4),
2486                 .hw.init = &(struct clk_init_data){
2487                         .name = "gsbi11_h_clk",
2488                         .ops = &clk_branch_ops,
2489                         .flags = CLK_IS_ROOT,
2490                 },
2491         },
2492 };
2493
2494 static struct clk_branch gsbi12_h_clk = {
2495         .hwcg_reg = 0x2b20,
2496         .hwcg_bit = 6,
2497         .halt_reg = 0x2fd4,
2498         .halt_bit = 14,
2499         .clkr = {
2500                 .enable_reg = 0x2b20,
2501                 .enable_mask = BIT(4),
2502                 .hw.init = &(struct clk_init_data){
2503                         .name = "gsbi12_h_clk",
2504                         .ops = &clk_branch_ops,
2505                         .flags = CLK_IS_ROOT,
2506                 },
2507         },
2508 };
2509
2510 static struct clk_branch tsif_h_clk = {
2511         .hwcg_reg = 0x2700,
2512         .hwcg_bit = 6,
2513         .halt_reg = 0x2fd4,
2514         .halt_bit = 7,
2515         .clkr = {
2516                 .enable_reg = 0x2700,
2517                 .enable_mask = BIT(4),
2518                 .hw.init = &(struct clk_init_data){
2519                         .name = "tsif_h_clk",
2520                         .ops = &clk_branch_ops,
2521                         .flags = CLK_IS_ROOT,
2522                 },
2523         },
2524 };
2525
2526 static struct clk_branch usb_fs1_h_clk = {
2527         .halt_reg = 0x2fcc,
2528         .halt_bit = 17,
2529         .clkr = {
2530                 .enable_reg = 0x2960,
2531                 .enable_mask = BIT(4),
2532                 .hw.init = &(struct clk_init_data){
2533                         .name = "usb_fs1_h_clk",
2534                         .ops = &clk_branch_ops,
2535                         .flags = CLK_IS_ROOT,
2536                 },
2537         },
2538 };
2539
2540 static struct clk_branch usb_fs2_h_clk = {
2541         .halt_reg = 0x2fcc,
2542         .halt_bit = 14,
2543         .clkr = {
2544                 .enable_reg = 0x2980,
2545                 .enable_mask = BIT(4),
2546                 .hw.init = &(struct clk_init_data){
2547                         .name = "usb_fs2_h_clk",
2548                         .ops = &clk_branch_ops,
2549                         .flags = CLK_IS_ROOT,
2550                 },
2551         },
2552 };
2553
2554 static struct clk_branch usb_hs1_h_clk = {
2555         .hwcg_reg = 0x2900,
2556         .hwcg_bit = 6,
2557         .halt_reg = 0x2fc8,
2558         .halt_bit = 1,
2559         .clkr = {
2560                 .enable_reg = 0x2900,
2561                 .enable_mask = BIT(4),
2562                 .hw.init = &(struct clk_init_data){
2563                         .name = "usb_hs1_h_clk",
2564                         .ops = &clk_branch_ops,
2565                         .flags = CLK_IS_ROOT,
2566                 },
2567         },
2568 };
2569
2570 static struct clk_branch usb_hs3_h_clk = {
2571         .halt_reg = 0x2fc8,
2572         .halt_bit = 31,
2573         .clkr = {
2574                 .enable_reg = 0x3700,
2575                 .enable_mask = BIT(4),
2576                 .hw.init = &(struct clk_init_data){
2577                         .name = "usb_hs3_h_clk",
2578                         .ops = &clk_branch_ops,
2579                         .flags = CLK_IS_ROOT,
2580                 },
2581         },
2582 };
2583
2584 static struct clk_branch usb_hs4_h_clk = {
2585         .halt_reg = 0x2fc8,
2586         .halt_bit = 7,
2587         .clkr = {
2588                 .enable_reg = 0x3720,
2589                 .enable_mask = BIT(4),
2590                 .hw.init = &(struct clk_init_data){
2591                         .name = "usb_hs4_h_clk",
2592                         .ops = &clk_branch_ops,
2593                         .flags = CLK_IS_ROOT,
2594                 },
2595         },
2596 };
2597
2598 static struct clk_branch usb_hsic_h_clk = {
2599         .halt_reg = 0x2fcc,
2600         .halt_bit = 28,
2601         .clkr = {
2602                 .enable_reg = 0x2920,
2603                 .enable_mask = BIT(4),
2604                 .hw.init = &(struct clk_init_data){
2605                         .name = "usb_hsic_h_clk",
2606                         .ops = &clk_branch_ops,
2607                         .flags = CLK_IS_ROOT,
2608                 },
2609         },
2610 };
2611
2612 static struct clk_branch sdc1_h_clk = {
2613         .hwcg_reg = 0x2820,
2614         .hwcg_bit = 6,
2615         .halt_reg = 0x2fc8,
2616         .halt_bit = 11,
2617         .clkr = {
2618                 .enable_reg = 0x2820,
2619                 .enable_mask = BIT(4),
2620                 .hw.init = &(struct clk_init_data){
2621                         .name = "sdc1_h_clk",
2622                         .ops = &clk_branch_ops,
2623                         .flags = CLK_IS_ROOT,
2624                 },
2625         },
2626 };
2627
2628 static struct clk_branch sdc2_h_clk = {
2629         .hwcg_reg = 0x2840,
2630         .hwcg_bit = 6,
2631         .halt_reg = 0x2fc8,
2632         .halt_bit = 10,
2633         .clkr = {
2634                 .enable_reg = 0x2840,
2635                 .enable_mask = BIT(4),
2636                 .hw.init = &(struct clk_init_data){
2637                         .name = "sdc2_h_clk",
2638                         .ops = &clk_branch_ops,
2639                         .flags = CLK_IS_ROOT,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch sdc3_h_clk = {
2645         .hwcg_reg = 0x2860,
2646         .hwcg_bit = 6,
2647         .halt_reg = 0x2fc8,
2648         .halt_bit = 9,
2649         .clkr = {
2650                 .enable_reg = 0x2860,
2651                 .enable_mask = BIT(4),
2652                 .hw.init = &(struct clk_init_data){
2653                         .name = "sdc3_h_clk",
2654                         .ops = &clk_branch_ops,
2655                         .flags = CLK_IS_ROOT,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_branch sdc4_h_clk = {
2661         .hwcg_reg = 0x2880,
2662         .hwcg_bit = 6,
2663         .halt_reg = 0x2fc8,
2664         .halt_bit = 8,
2665         .clkr = {
2666                 .enable_reg = 0x2880,
2667                 .enable_mask = BIT(4),
2668                 .hw.init = &(struct clk_init_data){
2669                         .name = "sdc4_h_clk",
2670                         .ops = &clk_branch_ops,
2671                         .flags = CLK_IS_ROOT,
2672                 },
2673         },
2674 };
2675
2676 static struct clk_branch sdc5_h_clk = {
2677         .hwcg_reg = 0x28a0,
2678         .hwcg_bit = 6,
2679         .halt_reg = 0x2fc8,
2680         .halt_bit = 7,
2681         .clkr = {
2682                 .enable_reg = 0x28a0,
2683                 .enable_mask = BIT(4),
2684                 .hw.init = &(struct clk_init_data){
2685                         .name = "sdc5_h_clk",
2686                         .ops = &clk_branch_ops,
2687                         .flags = CLK_IS_ROOT,
2688                 },
2689         },
2690 };
2691
2692 static struct clk_branch adm0_clk = {
2693         .halt_reg = 0x2fdc,
2694         .halt_check = BRANCH_HALT_VOTED,
2695         .halt_bit = 14,
2696         .clkr = {
2697                 .enable_reg = 0x3080,
2698                 .enable_mask = BIT(2),
2699                 .hw.init = &(struct clk_init_data){
2700                         .name = "adm0_clk",
2701                         .ops = &clk_branch_ops,
2702                         .flags = CLK_IS_ROOT,
2703                 },
2704         },
2705 };
2706
2707 static struct clk_branch adm0_pbus_clk = {
2708         .hwcg_reg = 0x2208,
2709         .hwcg_bit = 6,
2710         .halt_reg = 0x2fdc,
2711         .halt_check = BRANCH_HALT_VOTED,
2712         .halt_bit = 13,
2713         .clkr = {
2714                 .enable_reg = 0x3080,
2715                 .enable_mask = BIT(3),
2716                 .hw.init = &(struct clk_init_data){
2717                         .name = "adm0_pbus_clk",
2718                         .ops = &clk_branch_ops,
2719                         .flags = CLK_IS_ROOT,
2720                 },
2721         },
2722 };
2723
2724 static struct freq_tbl clk_tbl_ce3[] = {
2725         { 48000000, P_PLL8, 8 },
2726         { 100000000, P_PLL3, 12 },
2727         { 120000000, P_PLL3, 10 },
2728         { }
2729 };
2730
2731 static struct clk_rcg ce3_src = {
2732         .ns_reg = 0x36c0,
2733         .p = {
2734                 .pre_div_shift = 3,
2735                 .pre_div_width = 4,
2736         },
2737         .s = {
2738                 .src_sel_shift = 0,
2739                 .parent_map = gcc_pxo_pll8_pll3_map,
2740         },
2741         .freq_tbl = clk_tbl_ce3,
2742         .clkr = {
2743                 .enable_reg = 0x2c08,
2744                 .enable_mask = BIT(7),
2745                 .hw.init = &(struct clk_init_data){
2746                         .name = "ce3_src",
2747                         .parent_names = gcc_pxo_pll8_pll3,
2748                         .num_parents = 3,
2749                         .ops = &clk_rcg_ops,
2750                         .flags = CLK_SET_RATE_GATE,
2751                 },
2752         },
2753 };
2754
2755 static struct clk_branch ce3_core_clk = {
2756         .halt_reg = 0x2fdc,
2757         .halt_bit = 5,
2758         .clkr = {
2759                 .enable_reg = 0x36c4,
2760                 .enable_mask = BIT(4),
2761                 .hw.init = &(struct clk_init_data){
2762                         .name = "ce3_core_clk",
2763                         .parent_names = (const char *[]){ "ce3_src" },
2764                         .num_parents = 1,
2765                         .ops = &clk_branch_ops,
2766                         .flags = CLK_SET_RATE_PARENT,
2767                 },
2768         },
2769 };
2770
2771 static struct clk_branch ce3_h_clk = {
2772         .halt_reg = 0x2fc4,
2773         .halt_bit = 16,
2774         .clkr = {
2775                 .enable_reg = 0x36c4,
2776                 .enable_mask = BIT(4),
2777                 .hw.init = &(struct clk_init_data){
2778                         .name = "ce3_h_clk",
2779                         .parent_names = (const char *[]){ "ce3_src" },
2780                         .num_parents = 1,
2781                         .ops = &clk_branch_ops,
2782                         .flags = CLK_SET_RATE_PARENT,
2783                 },
2784         },
2785 };
2786
2787 static const struct freq_tbl clk_tbl_sata_ref[] = {
2788         { 48000000, P_PLL8, 8, 0, 0 },
2789         { 100000000, P_PLL3, 12, 0, 0 },
2790         { }
2791 };
2792
2793 static struct clk_rcg sata_clk_src = {
2794         .ns_reg = 0x2c08,
2795         .p = {
2796                 .pre_div_shift = 3,
2797                 .pre_div_width = 4,
2798         },
2799         .s = {
2800                 .src_sel_shift = 0,
2801                 .parent_map = gcc_pxo_pll8_pll3_map,
2802         },
2803         .freq_tbl = clk_tbl_sata_ref,
2804         .clkr = {
2805                 .enable_reg = 0x2c08,
2806                 .enable_mask = BIT(7),
2807                 .hw.init = &(struct clk_init_data){
2808                         .name = "sata_clk_src",
2809                         .parent_names = gcc_pxo_pll8_pll3,
2810                         .num_parents = 3,
2811                         .ops = &clk_rcg_ops,
2812                         .flags = CLK_SET_RATE_GATE,
2813                 },
2814         },
2815 };
2816
2817 static struct clk_branch sata_rxoob_clk = {
2818         .halt_reg = 0x2fdc,
2819         .halt_bit = 26,
2820         .clkr = {
2821                 .enable_reg = 0x2c0c,
2822                 .enable_mask = BIT(4),
2823                 .hw.init = &(struct clk_init_data){
2824                         .name = "sata_rxoob_clk",
2825                         .parent_names = (const char *[]){ "sata_clk_src" },
2826                         .num_parents = 1,
2827                         .ops = &clk_branch_ops,
2828                         .flags = CLK_SET_RATE_PARENT,
2829                 },
2830         },
2831 };
2832
2833 static struct clk_branch sata_pmalive_clk = {
2834         .halt_reg = 0x2fdc,
2835         .halt_bit = 25,
2836         .clkr = {
2837                 .enable_reg = 0x2c10,
2838                 .enable_mask = BIT(4),
2839                 .hw.init = &(struct clk_init_data){
2840                         .name = "sata_pmalive_clk",
2841                         .parent_names = (const char *[]){ "sata_clk_src" },
2842                         .num_parents = 1,
2843                         .ops = &clk_branch_ops,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                 },
2846         },
2847 };
2848
2849 static struct clk_branch sata_phy_ref_clk = {
2850         .halt_reg = 0x2fdc,
2851         .halt_bit = 24,
2852         .clkr = {
2853                 .enable_reg = 0x2c14,
2854                 .enable_mask = BIT(4),
2855                 .hw.init = &(struct clk_init_data){
2856                         .name = "sata_phy_ref_clk",
2857                         .parent_names = (const char *[]){ "pxo" },
2858                         .num_parents = 1,
2859                         .ops = &clk_branch_ops,
2860                 },
2861         },
2862 };
2863
2864 static struct clk_branch sata_a_clk = {
2865         .halt_reg = 0x2fc0,
2866         .halt_bit = 12,
2867         .clkr = {
2868                 .enable_reg = 0x2c20,
2869                 .enable_mask = BIT(4),
2870                 .hw.init = &(struct clk_init_data){
2871                         .name = "sata_a_clk",
2872                         .ops = &clk_branch_ops,
2873                         .flags = CLK_IS_ROOT,
2874                 },
2875         },
2876 };
2877
2878 static struct clk_branch sata_h_clk = {
2879         .halt_reg = 0x2fdc,
2880         .halt_bit = 27,
2881         .clkr = {
2882                 .enable_reg = 0x2c00,
2883                 .enable_mask = BIT(4),
2884                 .hw.init = &(struct clk_init_data){
2885                         .name = "sata_h_clk",
2886                         .ops = &clk_branch_ops,
2887                         .flags = CLK_IS_ROOT,
2888                 },
2889         },
2890 };
2891
2892 static struct clk_branch sfab_sata_s_h_clk = {
2893         .halt_reg = 0x2fc4,
2894         .halt_bit = 14,
2895         .clkr = {
2896                 .enable_reg = 0x2480,
2897                 .enable_mask = BIT(4),
2898                 .hw.init = &(struct clk_init_data){
2899                         .name = "sfab_sata_s_h_clk",
2900                         .ops = &clk_branch_ops,
2901                         .flags = CLK_IS_ROOT,
2902                 },
2903         },
2904 };
2905
2906 static struct clk_branch sata_phy_cfg_clk = {
2907         .halt_reg = 0x2fcc,
2908         .halt_bit = 12,
2909         .clkr = {
2910                 .enable_reg = 0x2c40,
2911                 .enable_mask = BIT(4),
2912                 .hw.init = &(struct clk_init_data){
2913                         .name = "sata_phy_cfg_clk",
2914                         .ops = &clk_branch_ops,
2915                         .flags = CLK_IS_ROOT,
2916                 },
2917         },
2918 };
2919
2920 static struct clk_branch pcie_phy_ref_clk = {
2921         .halt_reg = 0x2fdc,
2922         .halt_bit = 29,
2923         .clkr = {
2924                 .enable_reg = 0x22d0,
2925                 .enable_mask = BIT(4),
2926                 .hw.init = &(struct clk_init_data){
2927                         .name = "pcie_phy_ref_clk",
2928                         .ops = &clk_branch_ops,
2929                         .flags = CLK_IS_ROOT,
2930                 },
2931         },
2932 };
2933
2934 static struct clk_branch pcie_h_clk = {
2935         .halt_reg = 0x2fd4,
2936         .halt_bit = 8,
2937         .clkr = {
2938                 .enable_reg = 0x22cc,
2939                 .enable_mask = BIT(4),
2940                 .hw.init = &(struct clk_init_data){
2941                         .name = "pcie_h_clk",
2942                         .ops = &clk_branch_ops,
2943                         .flags = CLK_IS_ROOT,
2944                 },
2945         },
2946 };
2947
2948 static struct clk_branch pcie_a_clk = {
2949         .halt_reg = 0x2fc0,
2950         .halt_bit = 13,
2951         .clkr = {
2952                 .enable_reg = 0x22c0,
2953                 .enable_mask = BIT(4),
2954                 .hw.init = &(struct clk_init_data){
2955                         .name = "pcie_a_clk",
2956                         .ops = &clk_branch_ops,
2957                         .flags = CLK_IS_ROOT,
2958                 },
2959         },
2960 };
2961
2962 static struct clk_branch pmic_arb0_h_clk = {
2963         .halt_reg = 0x2fd8,
2964         .halt_check = BRANCH_HALT_VOTED,
2965         .halt_bit = 22,
2966         .clkr = {
2967                 .enable_reg = 0x3080,
2968                 .enable_mask = BIT(8),
2969                 .hw.init = &(struct clk_init_data){
2970                         .name = "pmic_arb0_h_clk",
2971                         .ops = &clk_branch_ops,
2972                         .flags = CLK_IS_ROOT,
2973                 },
2974         },
2975 };
2976
2977 static struct clk_branch pmic_arb1_h_clk = {
2978         .halt_reg = 0x2fd8,
2979         .halt_check = BRANCH_HALT_VOTED,
2980         .halt_bit = 21,
2981         .clkr = {
2982                 .enable_reg = 0x3080,
2983                 .enable_mask = BIT(9),
2984                 .hw.init = &(struct clk_init_data){
2985                         .name = "pmic_arb1_h_clk",
2986                         .ops = &clk_branch_ops,
2987                         .flags = CLK_IS_ROOT,
2988                 },
2989         },
2990 };
2991
2992 static struct clk_branch pmic_ssbi2_clk = {
2993         .halt_reg = 0x2fd8,
2994         .halt_check = BRANCH_HALT_VOTED,
2995         .halt_bit = 23,
2996         .clkr = {
2997                 .enable_reg = 0x3080,
2998                 .enable_mask = BIT(7),
2999                 .hw.init = &(struct clk_init_data){
3000                         .name = "pmic_ssbi2_clk",
3001                         .ops = &clk_branch_ops,
3002                         .flags = CLK_IS_ROOT,
3003                 },
3004         },
3005 };
3006
3007 static struct clk_branch rpm_msg_ram_h_clk = {
3008         .hwcg_reg = 0x27e0,
3009         .hwcg_bit = 6,
3010         .halt_reg = 0x2fd8,
3011         .halt_check = BRANCH_HALT_VOTED,
3012         .halt_bit = 12,
3013         .clkr = {
3014                 .enable_reg = 0x3080,
3015                 .enable_mask = BIT(6),
3016                 .hw.init = &(struct clk_init_data){
3017                         .name = "rpm_msg_ram_h_clk",
3018                         .ops = &clk_branch_ops,
3019                         .flags = CLK_IS_ROOT,
3020                 },
3021         },
3022 };
3023
3024 static struct clk_regmap *gcc_msm8960_clks[] = {
3025         [PLL3] = &pll3.clkr,
3026         [PLL8] = &pll8.clkr,
3027         [PLL8_VOTE] = &pll8_vote,
3028         [PLL14] = &pll14.clkr,
3029         [PLL14_VOTE] = &pll14_vote,
3030         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3031         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3032         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3033         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3034         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3035         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3036         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3037         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3038         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3039         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3040         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3041         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3042         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3043         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3044         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3045         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3046         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3047         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3048         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3049         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3050         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3051         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3052         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3053         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3054         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3055         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3056         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3057         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3058         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3059         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3060         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3061         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3062         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3063         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3064         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3065         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3066         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3067         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3068         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3069         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3070         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3071         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3072         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3073         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3074         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3075         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3076         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3077         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3078         [GP0_SRC] = &gp0_src.clkr,
3079         [GP0_CLK] = &gp0_clk.clkr,
3080         [GP1_SRC] = &gp1_src.clkr,
3081         [GP1_CLK] = &gp1_clk.clkr,
3082         [GP2_SRC] = &gp2_src.clkr,
3083         [GP2_CLK] = &gp2_clk.clkr,
3084         [PMEM_A_CLK] = &pmem_clk.clkr,
3085         [PRNG_SRC] = &prng_src.clkr,
3086         [PRNG_CLK] = &prng_clk.clkr,
3087         [SDC1_SRC] = &sdc1_src.clkr,
3088         [SDC1_CLK] = &sdc1_clk.clkr,
3089         [SDC2_SRC] = &sdc2_src.clkr,
3090         [SDC2_CLK] = &sdc2_clk.clkr,
3091         [SDC3_SRC] = &sdc3_src.clkr,
3092         [SDC3_CLK] = &sdc3_clk.clkr,
3093         [SDC4_SRC] = &sdc4_src.clkr,
3094         [SDC4_CLK] = &sdc4_clk.clkr,
3095         [SDC5_SRC] = &sdc5_src.clkr,
3096         [SDC5_CLK] = &sdc5_clk.clkr,
3097         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3098         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3099         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3100         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3101         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3102         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3103         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3104         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3105         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3106         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3107         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3108         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3109         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3110         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3111         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3112         [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3113         [CE1_H_CLK] = &ce1_h_clk.clkr,
3114         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3115         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3116         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3117         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3118         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3119         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3120         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3121         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3122         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3123         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3124         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3125         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3126         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3127         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3128         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3129         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3130         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3131         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3132         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3133         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3134         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3135         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3136         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3137         [ADM0_CLK] = &adm0_clk.clkr,
3138         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3139         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3140         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3141         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3142         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3143 };
3144
3145 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3146         [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3147         [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3148         [QDSS_STM_RESET] = { 0x2060, 6 },
3149         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3150         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3151         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3152         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3153         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3154         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3155         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3156         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3157         [ADM0_C2_RESET] = { 0x220c, 4},
3158         [ADM0_C1_RESET] = { 0x220c, 3},
3159         [ADM0_C0_RESET] = { 0x220c, 2},
3160         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3161         [ADM0_RESET] = { 0x220c },
3162         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3163         [QDSS_POR_RESET] = { 0x2260, 4 },
3164         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3165         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3166         [QDSS_AXI_RESET] = { 0x2260, 1 },
3167         [QDSS_DBG_RESET] = { 0x2260 },
3168         [PCIE_A_RESET] = { 0x22c0, 7 },
3169         [PCIE_AUX_RESET] = { 0x22c8, 7 },
3170         [PCIE_H_RESET] = { 0x22d0, 7 },
3171         [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3172         [SFAB_PCIE_S_RESET] = { 0x22d4 },
3173         [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3174         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3175         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3176         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3177         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3178         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3179         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3180         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3181         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3182         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3183         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3184         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3185         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3186         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3187         [PPSS_PROC_RESET] = { 0x2594, 1 },
3188         [PPSS_RESET] = { 0x2594},
3189         [DMA_BAM_RESET] = { 0x25c0, 7 },
3190         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3191         [SLIMBUS_H_RESET] = { 0x2620, 7 },
3192         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3193         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3194         [TSIF_H_RESET] = { 0x2700, 7 },
3195         [CE1_H_RESET] = { 0x2720, 7 },
3196         [CE1_CORE_RESET] = { 0x2724, 7 },
3197         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3198         [CE2_H_RESET] = { 0x2740, 7 },
3199         [CE2_CORE_RESET] = { 0x2744, 7 },
3200         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3201         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3202         [RPM_PROC_RESET] = { 0x27c0, 7 },
3203         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3204         [SDC1_RESET] = { 0x2830 },
3205         [SDC2_RESET] = { 0x2850 },
3206         [SDC3_RESET] = { 0x2870 },
3207         [SDC4_RESET] = { 0x2890 },
3208         [SDC5_RESET] = { 0x28b0 },
3209         [DFAB_A2_RESET] = { 0x28c0, 7 },
3210         [USB_HS1_RESET] = { 0x2910 },
3211         [USB_HSIC_RESET] = { 0x2934 },
3212         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3213         [USB_FS1_RESET] = { 0x2974 },
3214         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3215         [USB_FS2_RESET] = { 0x2994 },
3216         [GSBI1_RESET] = { 0x29dc },
3217         [GSBI2_RESET] = { 0x29fc },
3218         [GSBI3_RESET] = { 0x2a1c },
3219         [GSBI4_RESET] = { 0x2a3c },
3220         [GSBI5_RESET] = { 0x2a5c },
3221         [GSBI6_RESET] = { 0x2a7c },
3222         [GSBI7_RESET] = { 0x2a9c },
3223         [GSBI8_RESET] = { 0x2abc },
3224         [GSBI9_RESET] = { 0x2adc },
3225         [GSBI10_RESET] = { 0x2afc },
3226         [GSBI11_RESET] = { 0x2b1c },
3227         [GSBI12_RESET] = { 0x2b3c },
3228         [SPDM_RESET] = { 0x2b6c },
3229         [TLMM_H_RESET] = { 0x2ba0, 7 },
3230         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3231         [MSS_SLP_RESET] = { 0x2c60, 7 },
3232         [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3233         [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3234         [MSS_RESET] = { 0x2c64 },
3235         [SATA_H_RESET] = { 0x2c80, 7 },
3236         [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3237         [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3238         [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3239         [TSSC_RESET] = { 0x2ca0, 7 },
3240         [PDM_RESET] = { 0x2cc0, 12 },
3241         [MPM_H_RESET] = { 0x2da0, 7 },
3242         [MPM_RESET] = { 0x2da4 },
3243         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3244         [PRNG_RESET] = { 0x2e80, 12 },
3245         [RIVA_RESET] = { 0x35e0 },
3246 };
3247
3248 static struct clk_regmap *gcc_apq8064_clks[] = {
3249         [PLL3] = &pll3.clkr,
3250         [PLL8] = &pll8.clkr,
3251         [PLL8_VOTE] = &pll8_vote,
3252         [PLL14] = &pll14.clkr,
3253         [PLL14_VOTE] = &pll14_vote,
3254         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3255         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3256         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3257         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3258         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3259         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3260         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3261         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3262         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3263         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3264         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3265         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3266         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3267         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3268         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3269         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3270         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3271         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3272         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3273         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3274         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3275         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3276         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3277         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3278         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3279         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3280         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3281         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3282         [GP0_SRC] = &gp0_src.clkr,
3283         [GP0_CLK] = &gp0_clk.clkr,
3284         [GP1_SRC] = &gp1_src.clkr,
3285         [GP1_CLK] = &gp1_clk.clkr,
3286         [GP2_SRC] = &gp2_src.clkr,
3287         [GP2_CLK] = &gp2_clk.clkr,
3288         [PMEM_A_CLK] = &pmem_clk.clkr,
3289         [PRNG_SRC] = &prng_src.clkr,
3290         [PRNG_CLK] = &prng_clk.clkr,
3291         [SDC1_SRC] = &sdc1_src.clkr,
3292         [SDC1_CLK] = &sdc1_clk.clkr,
3293         [SDC2_SRC] = &sdc2_src.clkr,
3294         [SDC2_CLK] = &sdc2_clk.clkr,
3295         [SDC3_SRC] = &sdc3_src.clkr,
3296         [SDC3_CLK] = &sdc3_clk.clkr,
3297         [SDC4_SRC] = &sdc4_src.clkr,
3298         [SDC4_CLK] = &sdc4_clk.clkr,
3299         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3300         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3301         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3302         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3303         [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3304         [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3305         [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3306         [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3307         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3308         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3309         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3310         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3311         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3312         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3313         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3314         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3315         [SATA_H_CLK] = &sata_h_clk.clkr,
3316         [SATA_CLK_SRC] = &sata_clk_src.clkr,
3317         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3318         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3319         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3320         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3321         [SATA_A_CLK] = &sata_a_clk.clkr,
3322         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3323         [CE3_SRC] = &ce3_src.clkr,
3324         [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3325         [CE3_H_CLK] = &ce3_h_clk.clkr,
3326         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3327         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3328         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3329         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3330         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3331         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3332         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3333         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3334         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3335         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3336         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3337         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3338         [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3339         [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3340         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3341         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3342         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3343         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3344         [ADM0_CLK] = &adm0_clk.clkr,
3345         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3346         [PCIE_A_CLK] = &pcie_a_clk.clkr,
3347         [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3348         [PCIE_H_CLK] = &pcie_h_clk.clkr,
3349         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3350         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3351         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3352         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3353 };
3354
3355 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3356         [QDSS_STM_RESET] = { 0x2060, 6 },
3357         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3358         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3359         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3360         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3361         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3362         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3363         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3364         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3365         [ADM0_C2_RESET] = { 0x220c, 4},
3366         [ADM0_C1_RESET] = { 0x220c, 3},
3367         [ADM0_C0_RESET] = { 0x220c, 2},
3368         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3369         [ADM0_RESET] = { 0x220c },
3370         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3371         [QDSS_POR_RESET] = { 0x2260, 4 },
3372         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3373         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3374         [QDSS_AXI_RESET] = { 0x2260, 1 },
3375         [QDSS_DBG_RESET] = { 0x2260 },
3376         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3377         [SFAB_PCIE_S_RESET] = { 0x22d8 },
3378         [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3379         [PCIE_PHY_RESET] = { 0x22dc, 5 },
3380         [PCIE_PCI_RESET] = { 0x22dc, 4 },
3381         [PCIE_POR_RESET] = { 0x22dc, 3 },
3382         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3383         [PCIE_ACLK_RESET] = { 0x22dc },
3384         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3385         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3386         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3387         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3388         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3389         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3390         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3391         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3392         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3393         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3394         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3395         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3396         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3397         [PPSS_PROC_RESET] = { 0x2594, 1 },
3398         [PPSS_RESET] = { 0x2594},
3399         [DMA_BAM_RESET] = { 0x25c0, 7 },
3400         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3401         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3402         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3403         [TSIF_H_RESET] = { 0x2700, 7 },
3404         [CE1_H_RESET] = { 0x2720, 7 },
3405         [CE1_CORE_RESET] = { 0x2724, 7 },
3406         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3407         [CE2_H_RESET] = { 0x2740, 7 },
3408         [CE2_CORE_RESET] = { 0x2744, 7 },
3409         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3410         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3411         [RPM_PROC_RESET] = { 0x27c0, 7 },
3412         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3413         [SDC1_RESET] = { 0x2830 },
3414         [SDC2_RESET] = { 0x2850 },
3415         [SDC3_RESET] = { 0x2870 },
3416         [SDC4_RESET] = { 0x2890 },
3417         [USB_HS1_RESET] = { 0x2910 },
3418         [USB_HSIC_RESET] = { 0x2934 },
3419         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3420         [USB_FS1_RESET] = { 0x2974 },
3421         [GSBI1_RESET] = { 0x29dc },
3422         [GSBI2_RESET] = { 0x29fc },
3423         [GSBI3_RESET] = { 0x2a1c },
3424         [GSBI4_RESET] = { 0x2a3c },
3425         [GSBI5_RESET] = { 0x2a5c },
3426         [GSBI6_RESET] = { 0x2a7c },
3427         [GSBI7_RESET] = { 0x2a9c },
3428         [SPDM_RESET] = { 0x2b6c },
3429         [TLMM_H_RESET] = { 0x2ba0, 7 },
3430         [SATA_SFAB_M_RESET] = { 0x2c18 },
3431         [SATA_RESET] = { 0x2c1c },
3432         [GSS_SLP_RESET] = { 0x2c60, 7 },
3433         [GSS_RESET] = { 0x2c64 },
3434         [TSSC_RESET] = { 0x2ca0, 7 },
3435         [PDM_RESET] = { 0x2cc0, 12 },
3436         [MPM_H_RESET] = { 0x2da0, 7 },
3437         [MPM_RESET] = { 0x2da4 },
3438         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3439         [PRNG_RESET] = { 0x2e80, 12 },
3440         [RIVA_RESET] = { 0x35e0 },
3441         [CE3_H_RESET] = { 0x36c4, 7 },
3442         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3443         [SFAB_CE3_S_RESET] = { 0x36c8 },
3444         [CE3_RESET] = { 0x36cc, 7 },
3445         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3446         [USB_HS3_RESET] = { 0x3710 },
3447         [USB_HS4_RESET] = { 0x3730 },
3448 };
3449
3450 static const struct regmap_config gcc_msm8960_regmap_config = {
3451         .reg_bits       = 32,
3452         .reg_stride     = 4,
3453         .val_bits       = 32,
3454         .max_register   = 0x3660,
3455         .fast_io        = true,
3456 };
3457
3458 static const struct regmap_config gcc_apq8064_regmap_config = {
3459         .reg_bits       = 32,
3460         .reg_stride     = 4,
3461         .val_bits       = 32,
3462         .max_register   = 0x3880,
3463         .fast_io        = true,
3464 };
3465
3466 static const struct qcom_cc_desc gcc_msm8960_desc = {
3467         .config = &gcc_msm8960_regmap_config,
3468         .clks = gcc_msm8960_clks,
3469         .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3470         .resets = gcc_msm8960_resets,
3471         .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3472 };
3473
3474 static const struct qcom_cc_desc gcc_apq8064_desc = {
3475         .config = &gcc_apq8064_regmap_config,
3476         .clks = gcc_apq8064_clks,
3477         .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3478         .resets = gcc_apq8064_resets,
3479         .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3480 };
3481
3482 static const struct of_device_id gcc_msm8960_match_table[] = {
3483         { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3484         { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3485         { }
3486 };
3487 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3488
3489 static int gcc_msm8960_probe(struct platform_device *pdev)
3490 {
3491         struct clk *clk;
3492         struct device *dev = &pdev->dev;
3493         const struct of_device_id *match;
3494
3495         match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3496         if (!match)
3497                 return -EINVAL;
3498
3499         /* Temporary until RPM clocks supported */
3500         clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
3501         if (IS_ERR(clk))
3502                 return PTR_ERR(clk);
3503
3504         clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
3505         if (IS_ERR(clk))
3506                 return PTR_ERR(clk);
3507
3508         return qcom_cc_probe(pdev, match->data);
3509 }
3510
3511 static int gcc_msm8960_remove(struct platform_device *pdev)
3512 {
3513         qcom_cc_remove(pdev);
3514         return 0;
3515 }
3516
3517 static struct platform_driver gcc_msm8960_driver = {
3518         .probe          = gcc_msm8960_probe,
3519         .remove         = gcc_msm8960_remove,
3520         .driver         = {
3521                 .name   = "gcc-msm8960",
3522                 .owner  = THIS_MODULE,
3523                 .of_match_table = gcc_msm8960_match_table,
3524         },
3525 };
3526
3527 static int __init gcc_msm8960_init(void)
3528 {
3529         return platform_driver_register(&gcc_msm8960_driver);
3530 }
3531 core_initcall(gcc_msm8960_init);
3532
3533 static void __exit gcc_msm8960_exit(void)
3534 {
3535         platform_driver_unregister(&gcc_msm8960_driver);
3536 }
3537 module_exit(gcc_msm8960_exit);
3538
3539 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3540 MODULE_LICENSE("GPL v2");
3541 MODULE_ALIAS("platform:gcc-msm8960");